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comparison packages/hal/mips/arch/current/src/context.S @ 6:d376b777e2ce ecos-sw-1999-05-14

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Merge from eCos master repository on 1999-05-14-19:27:43-BST
author jlarmour
date Fri, 14 May 1999 12:20:00 +0000
parents 443894e2e912
children ece80412419a
comparison
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5:4e8259f41183 6:d376b777e2ce
40 ## 40 ##
41 ##============================================================================= 41 ##=============================================================================
42 42
43 #include <pkgconf/hal.h> 43 #include <pkgconf/hal.h>
44 44
45 #include <cyg/hal/mips.inc> 45 #include <cyg/hal/arch.inc>
46 46
47 .set noat 47 .set noat
48 48
49 #------------------------------------------------------------------------------ 49 #------------------------------------------------------------------------------
50 # hal_thread_switch_context 50 # hal_thread_switch_context
57 57
58 addi sp,sp,-mipsreg_size # space for registers 58 addi sp,sp,-mipsreg_size # space for registers
59 59
60 # store GPRs 60 # store GPRs
61 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM 61 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
62 sw $0,(mipsreg_regs+0*4)(sp) 62 sw $0,(mipsreg_regs+0*mips_regsize)(sp)
63 sw $1,(mipsreg_regs+1*4)(sp) 63 sw $1,(mipsreg_regs+1*mips_regsize)(sp)
64 sw $2,(mipsreg_regs+2*4)(sp) 64 sw $2,(mipsreg_regs+2*mips_regsize)(sp)
65 sw $3,(mipsreg_regs+3*4)(sp) 65 sw $3,(mipsreg_regs+3*mips_regsize)(sp)
66 sw $4,(mipsreg_regs+4*4)(sp) 66 sw $4,(mipsreg_regs+4*mips_regsize)(sp)
67 sw $5,(mipsreg_regs+5*4)(sp) 67 sw $5,(mipsreg_regs+5*mips_regsize)(sp)
68 sw $6,(mipsreg_regs+6*4)(sp) 68 sw $6,(mipsreg_regs+6*mips_regsize)(sp)
69 sw $7,(mipsreg_regs+7*4)(sp) 69 sw $7,(mipsreg_regs+7*mips_regsize)(sp)
70 sw $8,(mipsreg_regs+8*4)(sp) 70 sw $8,(mipsreg_regs+8*mips_regsize)(sp)
71 sw $9,(mipsreg_regs+9*4)(sp) 71 sw $9,(mipsreg_regs+9*mips_regsize)(sp)
72 sw $10,(mipsreg_regs+10*4)(sp) 72 sw $10,(mipsreg_regs+10*mips_regsize)(sp)
73 sw $11,(mipsreg_regs+11*4)(sp) 73 sw $11,(mipsreg_regs+11*mips_regsize)(sp)
74 sw $12,(mipsreg_regs+12*4)(sp) 74 sw $12,(mipsreg_regs+12*mips_regsize)(sp)
75 sw $13,(mipsreg_regs+13*4)(sp) 75 sw $13,(mipsreg_regs+13*mips_regsize)(sp)
76 sw $14,(mipsreg_regs+14*4)(sp) 76 sw $14,(mipsreg_regs+14*mips_regsize)(sp)
77 sw $15,(mipsreg_regs+15*4)(sp) 77 sw $15,(mipsreg_regs+15*mips_regsize)(sp)
78 sw $24,(mipsreg_regs+24*4)(sp) 78 sw $24,(mipsreg_regs+24*mips_regsize)(sp)
79 sw $25,(mipsreg_regs+25*4)(sp) 79 sw $25,(mipsreg_regs+25*mips_regsize)(sp)
80 sw $28,(mipsreg_regs+28*4)(sp) # == GP 80 sw $28,(mipsreg_regs+28*mips_regsize)(sp) # == GP
81 #endif 81 #endif
82 sw $16,(mipsreg_regs+16*4)(sp) 82 sw $16,(mipsreg_regs+16*mips_regsize)(sp)
83 sw $17,(mipsreg_regs+17*4)(sp) 83 sw $17,(mipsreg_regs+17*mips_regsize)(sp)
84 sw $18,(mipsreg_regs+18*4)(sp) 84 sw $18,(mipsreg_regs+18*mips_regsize)(sp)
85 sw $19,(mipsreg_regs+19*4)(sp) 85 sw $19,(mipsreg_regs+19*mips_regsize)(sp)
86 sw $20,(mipsreg_regs+20*4)(sp) 86 sw $20,(mipsreg_regs+20*mips_regsize)(sp)
87 sw $21,(mipsreg_regs+21*4)(sp) 87 sw $21,(mipsreg_regs+21*mips_regsize)(sp)
88 sw $22,(mipsreg_regs+22*4)(sp) 88 sw $22,(mipsreg_regs+22*mips_regsize)(sp)
89 sw $23,(mipsreg_regs+23*4)(sp) 89 sw $23,(mipsreg_regs+23*mips_regsize)(sp)
90 # sw $26,(mipsreg_regs+26*4)(sp) # == K0 90 # sw $26,(mipsreg_regs+26*mips_regsize)(sp) # == K0
91 # sw $27,(mipsreg_regs+27*4)(sp) # == K1 91 # sw $27,(mipsreg_regs+27*mips_regsize)(sp) # == K1
92 # sw $29,(mipsreg_regs+29*4)(sp) # == SP 92 # sw $29,(mipsreg_regs+29*mips_regsize)(sp) # == SP
93 sw $30,(mipsreg_regs+30*4)(sp) # == FP 93 sw $30,(mipsreg_regs+30*mips_regsize)(sp) # == FP
94 sw $31,(mipsreg_regs+31*4)(sp) # == RA 94 sw $31,(mipsreg_regs+31*mips_regsize)(sp) # == RA
95 sw $31,(mipsreg_pc)(sp) # == PC (to help with debugging) 95 sw $31,(mipsreg_pc)(sp) # == PC (to help with debugging)
96 96
97 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM 97 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
98 98
99 mflo t0 # save LO and HI regs 99 mflo t0 # save LO and HI regs
101 sw t0,mipsreg_lo(sp) 101 sw t0,mipsreg_lo(sp)
102 sw t1,mipsreg_hi(sp) 102 sw t1,mipsreg_hi(sp)
103 103
104 #endif 104 #endif
105 105
106 hal_fpu_save_callee sp
107
108 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
109
110 hal_fpu_save_caller sp
111
112 #endif
113
106 addi t0,sp,mipsreg_size # save SP in reg dump 114 addi t0,sp,mipsreg_size # save SP in reg dump
107 sw t0,(mipsreg_regs+29*4)(sp) 115 sw t0,(mipsreg_regs+29*mips_regsize)(sp)
108 116
117 mfc0 t1,status # Save status register
118 sw t1,mipsreg_sr(sp)
119
109 sw sp,0(a1) # save sp in save loc 120 sw sp,0(a1) # save sp in save loc
110 121
111 # Now load the destination thread by dropping through 122 # Now load the destination thread by dropping through
112 # to hal_thread_load_context 123 # to hal_thread_load_context
113 124
122 hal_thread_load_context: 133 hal_thread_load_context:
123 134
124 lw sp,0(a0) # load new SP directly 135 lw sp,0(a0) # load new SP directly
125 136
126 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM 137 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
138
139 hal_fpu_load_caller sp
140
141 #endif
142
143 hal_fpu_load_callee sp
144
145 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
127 146
128 lw t0,mipsreg_hi(sp) # load HI and LO regs 147 lw t0,mipsreg_hi(sp) # load HI and LO regs
129 lw t1,mipsreg_lo(sp) 148 lw t1,mipsreg_lo(sp)
130 mthi t0 149 mthi t0
131 mtlo t1 150 mtlo t1
132 151
133 #endif 152 #endif
134 153
135 # load GPRs 154 # load GPRs
136 # lw $0,(mipsreg_regs+0*4)(sp) 155 # lw $0,(mipsreg_regs+0*mips_regsize)(sp)
137 lw $4,(mipsreg_regs+4*4)(sp) # A0, must load for thread startup 156 lw $4,(mipsreg_regs+4*mips_regsize)(sp) # A0, must load for thread startup
138 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM 157 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
139 lw $1,(mipsreg_regs+1*4)(sp) 158 lw $1,(mipsreg_regs+1*mips_regsize)(sp)
140 lw $2,(mipsreg_regs+2*4)(sp) 159 lw $2,(mipsreg_regs+2*mips_regsize)(sp)
141 lw $3,(mipsreg_regs+3*4)(sp) 160 lw $3,(mipsreg_regs+3*mips_regsize)(sp)
142 lw $5,(mipsreg_regs+5*4)(sp) 161 lw $5,(mipsreg_regs+5*mips_regsize)(sp)
143 lw $6,(mipsreg_regs+6*4)(sp) 162 lw $6,(mipsreg_regs+6*mips_regsize)(sp)
144 lw $7,(mipsreg_regs+7*4)(sp) 163 lw $7,(mipsreg_regs+7*mips_regsize)(sp)
145 lw $8,(mipsreg_regs+8*4)(sp) 164 lw $8,(mipsreg_regs+8*mips_regsize)(sp)
146 lw $9,(mipsreg_regs+9*4)(sp) 165 lw $9,(mipsreg_regs+9*mips_regsize)(sp)
147 lw $10,(mipsreg_regs+10*4)(sp) 166 lw $10,(mipsreg_regs+10*mips_regsize)(sp)
148 lw $11,(mipsreg_regs+11*4)(sp) 167 lw $11,(mipsreg_regs+11*mips_regsize)(sp)
149 lw $12,(mipsreg_regs+12*4)(sp) 168 lw $12,(mipsreg_regs+12*mips_regsize)(sp)
150 lw $13,(mipsreg_regs+13*4)(sp) 169 lw $13,(mipsreg_regs+13*mips_regsize)(sp)
151 lw $14,(mipsreg_regs+14*4)(sp) 170 lw $14,(mipsreg_regs+14*mips_regsize)(sp)
152 lw $15,(mipsreg_regs+15*4)(sp) 171 lw $15,(mipsreg_regs+15*mips_regsize)(sp)
153 lw $24,(mipsreg_regs+24*4)(sp) 172 lw $24,(mipsreg_regs+24*mips_regsize)(sp)
154 lw $25,(mipsreg_regs+25*4)(sp) 173 lw $25,(mipsreg_regs+25*mips_regsize)(sp)
155 #endif 174 #endif
156 lw $16,(mipsreg_regs+16*4)(sp) 175 lw $16,(mipsreg_regs+16*mips_regsize)(sp)
157 lw $17,(mipsreg_regs+17*4)(sp) 176 lw $17,(mipsreg_regs+17*mips_regsize)(sp)
158 lw $18,(mipsreg_regs+18*4)(sp) 177 lw $18,(mipsreg_regs+18*mips_regsize)(sp)
159 lw $19,(mipsreg_regs+19*4)(sp) 178 lw $19,(mipsreg_regs+19*mips_regsize)(sp)
160 lw $20,(mipsreg_regs+20*4)(sp) 179 lw $20,(mipsreg_regs+20*mips_regsize)(sp)
161 lw $21,(mipsreg_regs+21*4)(sp) 180 lw $21,(mipsreg_regs+21*mips_regsize)(sp)
162 lw $22,(mipsreg_regs+22*4)(sp) 181 lw $22,(mipsreg_regs+22*mips_regsize)(sp)
163 lw $23,(mipsreg_regs+23*4)(sp) 182 lw $23,(mipsreg_regs+23*mips_regsize)(sp)
164 # lw $26,(mipsreg_regs+26*4)(sp) # == K0 183 # lw $26,(mipsreg_regs+26*mips_regsize)(sp) # == K0
165 # lw $27,(mipsreg_regs+27*4)(sp) # == K1 184 # lw $27,(mipsreg_regs+27*mips_regsize)(sp) # == K1
166 # lw $28,(mipsreg_regs+28*4)(sp) # == GP 185 # lw $28,(mipsreg_regs+28*mips_regsize)(sp) # == GP
167 # lw $29,(mipsreg_regs+29*4)(sp) # == SP 186 # lw $29,(mipsreg_regs+29*mips_regsize)(sp) # == SP
168 lw $30,(mipsreg_regs+30*4)(sp) # == FP 187 lw $30,(mipsreg_regs+30*mips_regsize)(sp) # == FP
169 lw $31,(mipsreg_regs+31*4)(sp) # == RA 188 lw $31,(mipsreg_regs+31*mips_regsize)(sp) # == RA
170 189
171 # Note that the following lw must go here and not 190 lw a2,mipsreg_sr(sp) # A2 = saved SR
172 # in the jr delay slot, since it has a delay slot 191 lw sp,(mipsreg_regs+29*mips_regsize)(sp) # SP = saved SP
173 # of its own. 192
174 lw sp,(mipsreg_regs+29*4)(sp) # load SP 193 hal_cpu_int_merge a2 # Merge with current SR
194
175 jr ra # return via ra 195 jr ra # return via ra
176 nop # delay slot - must be nop 196 nop # delay slot - must be nop
177 197
178 #------------------------------------------------------------------------------ 198 #------------------------------------------------------------------------------
179 # HAL longjmp, setjmp implementations 199 # HAL longjmp, setjmp implementations
198 #define CYGARC_JMP_BUF_SIZE 12 218 #define CYGARC_JMP_BUF_SIZE 12
199 219
200 .globl hal_setjmp 220 .globl hal_setjmp
201 .ent hal_setjmp 221 .ent hal_setjmp
202 hal_setjmp: 222 hal_setjmp:
203 sw $31,CYGARC_JMP_BUF_R31*4(a0) # ra (link) 223 sw $31,CYGARC_JMP_BUF_R31*mips_regsize(a0) # ra (link)
204 sw $30,CYGARC_JMP_BUF_R30*4(a0) 224 sw $30,CYGARC_JMP_BUF_R30*mips_regsize(a0)
205 sw $28,CYGARC_JMP_BUF_R28*4(a0) # gp, optimize out? 225 sw $28,CYGARC_JMP_BUF_R28*mips_regsize(a0) # gp, optimize out?
206 sw $23,CYGARC_JMP_BUF_R23*4(a0) 226 sw $23,CYGARC_JMP_BUF_R23*mips_regsize(a0)
207 sw $22,CYGARC_JMP_BUF_R22*4(a0) 227 sw $22,CYGARC_JMP_BUF_R22*mips_regsize(a0)
208 sw $21,CYGARC_JMP_BUF_R21*4(a0) 228 sw $21,CYGARC_JMP_BUF_R21*mips_regsize(a0)
209 sw $20,CYGARC_JMP_BUF_R20*4(a0) 229 sw $20,CYGARC_JMP_BUF_R20*mips_regsize(a0)
210 sw $19,CYGARC_JMP_BUF_R19*4(a0) 230 sw $19,CYGARC_JMP_BUF_R19*mips_regsize(a0)
211 sw $18,CYGARC_JMP_BUF_R18*4(a0) 231 sw $18,CYGARC_JMP_BUF_R18*mips_regsize(a0)
212 sw $17,CYGARC_JMP_BUF_R17*4(a0) 232 sw $17,CYGARC_JMP_BUF_R17*mips_regsize(a0)
213 sw $16,CYGARC_JMP_BUF_R16*4(a0) 233 sw $16,CYGARC_JMP_BUF_R16*mips_regsize(a0)
214 sw sp,CYGARC_JMP_BUF_SP*4(a0) # $29 234 sw sp,CYGARC_JMP_BUF_SP*mips_regsize(a0) # $29
215 li v0,0 235 li v0,0
216 jr ra 236 jr ra
217 nop # delay slot 237 nop # delay slot
218 .end hal_setjmp 238 .end hal_setjmp
219 239
220 .globl hal_longjmp 240 .globl hal_longjmp
221 .ent hal_longjmp 241 .ent hal_longjmp
222 hal_longjmp: 242 hal_longjmp:
223 lw $31,CYGARC_JMP_BUF_R31*4(a0) # ra (link) 243 lw $31,CYGARC_JMP_BUF_R31*mips_regsize(a0) # ra (link)
224 lw $30,CYGARC_JMP_BUF_R30*4(a0) 244 lw $30,CYGARC_JMP_BUF_R30*mips_regsize(a0)
225 lw $28,CYGARC_JMP_BUF_R28*4(a0) # gp, optimize out? 245 lw $28,CYGARC_JMP_BUF_R28*mips_regsize(a0) # gp, optimize out?
226 lw $23,CYGARC_JMP_BUF_R23*4(a0) 246 lw $23,CYGARC_JMP_BUF_R23*mips_regsize(a0)
227 lw $22,CYGARC_JMP_BUF_R22*4(a0) 247 lw $22,CYGARC_JMP_BUF_R22*mips_regsize(a0)
228 lw $21,CYGARC_JMP_BUF_R21*4(a0) 248 lw $21,CYGARC_JMP_BUF_R21*mips_regsize(a0)
229 lw $20,CYGARC_JMP_BUF_R20*4(a0) 249 lw $20,CYGARC_JMP_BUF_R20*mips_regsize(a0)
230 lw $19,CYGARC_JMP_BUF_R19*4(a0) 250 lw $19,CYGARC_JMP_BUF_R19*mips_regsize(a0)
231 lw $18,CYGARC_JMP_BUF_R18*4(a0) 251 lw $18,CYGARC_JMP_BUF_R18*mips_regsize(a0)
232 lw $17,CYGARC_JMP_BUF_R17*4(a0) 252 lw $17,CYGARC_JMP_BUF_R17*mips_regsize(a0)
233 lw $16,CYGARC_JMP_BUF_R16*4(a0) 253 lw $16,CYGARC_JMP_BUF_R16*mips_regsize(a0)
234 lw sp,CYGARC_JMP_BUF_SP*4(a0) # $29 254 lw sp,CYGARC_JMP_BUF_SP*mips_regsize(a0) # $29
235 move v0,a1 255 move v0,a1
236 jr ra 256 jr ra
237 nop # delay slot 257 nop # delay slot
238 .end hal_longjmp 258 .end hal_longjmp
239 259