Mercurial > nand-ecoscentric
diff packages/hal/mips/arch/current/include/hal_cache.h @ 10:d3fbcdfa1b2f ecos-sw-1999-05-29
Merge from eCos master repository on 1999-05-29-00:13:11-BST
| author | jlarmour |
|---|---|
| date | Fri, 28 May 1999 16:43:09 +0000 |
| parents | d376b777e2ce |
| children | 7253dcc42a09 |
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--- a/packages/hal/mips/arch/current/include/hal_cache.h +++ b/packages/hal/mips/arch/current/include/hal_cache.h @@ -93,6 +93,10 @@ #define HAL_DCACHE_DISABLE() #endif +#ifndef HAL_DCACHE_IS_ENABLED_DEFINED +#define HAL_DCACHE_IS_ENABLED(_state_) (_state_) = 1; +#endif + // Invalidate the entire cache // We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this // is not quite what we want, but there is no index-invalidate operation @@ -109,12 +113,14 @@ register CYG_ADDRESS _baddr_ = 0x80000000; \ register CYG_ADDRESS _addr_ = 0x80000000; \ register CYG_WORD _size_ = HAL_DCACHE_SIZE; \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED(_state_); \ HAL_DCACHE_DISABLE(); \ for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ { \ asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); \ } \ - HAL_DCACHE_ENABLE(); \ + if( _state_ ) HAL_DCACHE_ENABLE(); \ } #endif @@ -136,12 +142,14 @@ CYG_MACRO_START register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED(_state_); \ HAL_DCACHE_DISABLE(); \ for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ { \ asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); \ } \ - HAL_DCACHE_ENABLE(); \ + if( _state_ ) HAL_DCACHE_ENABLE(); \ CYG_MACRO_END #endif @@ -174,12 +182,14 @@ CYG_MACRO_END register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED(_state_); \ HAL_DCACHE_DISABLE(); \ for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ { \ asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); \ } \ - HAL_DCACHE_ENABLE(); \ + if( _state_ ) HAL_DCACHE_ENABLE(); \ } #endif @@ -191,12 +201,14 @@ CYG_MACRO_END register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED(_state_); \ HAL_DCACHE_DISABLE(); \ for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ { \ asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); \ } \ - HAL_DCACHE_ENABLE(); \ + if( _state_ ) HAL_DCACHE_ENABLE(); \ } #endif @@ -208,12 +220,14 @@ CYG_MACRO_END register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED(_state_); \ HAL_DCACHE_DISABLE(); \ for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ { \ asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); \ } \ - HAL_DCACHE_ENABLE(); \ + if( _state_ ) HAL_DCACHE_ENABLE(); \ } #endif @@ -242,6 +256,10 @@ CYG_MACRO_END #define HAL_ICACHE_DISABLE() #endif +#ifndef HAL_ICACHE_IS_ENABLED_DEFINED +#define HAL_ICACHE_IS_ENABLED(_state_) (_state_) = 1; +#endif + // Invalidate the entire cache // This uses the index-invalidate cache operation. #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED @@ -249,12 +267,14 @@ CYG_MACRO_END { \ register CYG_ADDRESS _baddr_ = 0x80000000; \ register CYG_ADDRESS _addr_ = 0x80000000; \ + register CYG_WORD _state_; \ + HAL_ICACHE_IS_ENABLED(_state_); \ HAL_ICACHE_DISABLE(); \ for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ { \ asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \ } \ - HAL_ICACHE_ENABLE(); \ + if( _state_ ) HAL_ICACHE_ENABLE(); \ } #endif @@ -276,12 +296,14 @@ CYG_MACRO_START register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ register CYG_WORD _size_ = (_asize_); \ - HAL_DCACHE_DISABLE(); \ + register CYG_WORD _state_; \ + HAL_ICACHE_IS_ENABLED(_state_); \ + HAL_ICACHE_DISABLE(); \ for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ { \ asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); \ } \ - HAL_DCACHE_ENABLE(); \ + if( _state_ ) HAL_ICACHE_ENABLE(); \ CYG_MACRO_END #endif @@ -306,12 +328,14 @@ CYG_MACRO_END register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ register CYG_WORD _size_ = (_asize_); \ - HAL_DCACHE_DISABLE(); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + register CYG_WORD _state_; \ + HAL_ICACHE_IS_ENABLED(_state_); \ + HAL_ICACHE_DISABLE(); \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ { \ asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); \ } \ - HAL_DCACHE_ENABLE(); \ + HAL_ICACHE_ENABLE(); \ } #endif