# HG changeset patch
# User jld
# Date 1296751490 0
# Node ID 5698d1884c8c757a76a39dc809bdeea9121845cf
# Parent  990c52b02d9c8b73f3c5b32194a0a9e277224046
* include/var_io.h: Fix CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_* definitions.
  [ Bugzilla 1001137 ]

diff --git a/packages/hal/cortexm/stm32/var/current/ChangeLog b/packages/hal/cortexm/stm32/var/current/ChangeLog
--- a/packages/hal/cortexm/stm32/var/current/ChangeLog
+++ b/packages/hal/cortexm/stm32/var/current/ChangeLog
@@ -1,3 +1,8 @@
+2011-02-03  Alan Bowman  <alan.bowman@datong.co.uk>
+
+	* include/var_io.h: Fix CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_*
+	definitions. [ Bugzilla 1001137 ]
+
 2011-01-21  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* src/stm32_misc.c (hal_start_clocks): Added optional calculation of
diff --git a/packages/hal/cortexm/stm32/var/current/include/var_io.h b/packages/hal/cortexm/stm32/var/current/include/var_io.h
--- a/packages/hal/cortexm/stm32/var/current/include/var_io.h
+++ b/packages/hal/cortexm/stm32/var/current/include/var_io.h
@@ -169,10 +169,10 @@
 #define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_8       VALUE_(8,6)
 #define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_16      VALUE_(8,7)
 #define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_1       VALUE_(11,0)
-#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_2       VALUE_(11,0)
-#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_4       VALUE_(11,0)
-#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_8       VALUE_(11,0)
-#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_16      VALUE_(11,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_2       VALUE_(11,4)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_4       VALUE_(11,5)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_8       VALUE_(11,6)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_16      VALUE_(11,7)
 #define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_2      VALUE_(14,0)
 #define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_4      VALUE_(14,1)
 #define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_6      VALUE_(14,2)