# HG changeset patch
# User Ross Younger <wry@ecoscentric.com>
# Date 1406883255 -43200
# Node ID 56fc685b878cc8d80c3afe227f0a68b29c139550
# Parent  a9d12f1a0c5bd25fe164f288288d973ca6546165# Parent  a1df75458e136955a3270e0108bb2d9a93d2e3c2
Merge from anon-hg

diff --git a/doc/ChangeLog b/doc/ChangeLog
--- a/doc/ChangeLog
+++ b/doc/ChangeLog
@@ -1,3 +1,40 @@
+2014-02-13  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* sgml/doclist: Add Freescale eDMA entry.
+
+2013-07-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* sgml/doclist: Add K60F120M entry (document body provided by Mike Jones)
+
+2013-06-12  John Dallaway  <john@dallaway.org.uk>
+
+	* sgml/doclist: Add STM32F4-Discovery documentation.
+
+2013-05-09  John Dallaway  <john@dallaway.org.uk>
+
+	* sgml/makemakefile: Update copyright dates.
+
+2012-05-18  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* sgml/doclist: Add Freescale Kinetis documentation.
+
+2012-03-13  John Dallaway  <john@dallaway.org.uk>
+
+	* sgml/doclist: Add Actel SmartFusion documentation.
+	* sgml/makemakefile: Update copyright dates.
+
+2011-02-09  John Dallaway  <john@dallaway.org.uk>
+
+	* sgml/makemakefile: Update copyright dates.
+
+2011-02-09  Christophe Coutand  <ccoutand@stmi.com>
+
+	* sgml/doclist: Add EK-LM3S811 documentation.
+
+2010-11-13  John Dallaway  <john@dallaway.org.uk>
+
+	* sgml/doclist: Add USB mass storage documentation.
+	
 2010-02-25  John Dallaway  <john@dallaway.org.uk>
 
 	* sgml/makemakefile: Update copyright dates.
diff --git a/doc/sgml/doclist b/doc/sgml/doclist
--- a/doc/sgml/doclist
+++ b/doc/sgml/doclist
@@ -41,11 +41,22 @@ services/power/common/current/doc/power.
 io/usb/slave/current/doc/usbs.sgml
 io/usb/eth/slave/current/doc/usbseth.sgml
 io/usb/serial/slave/current/doc/usbs_serial.sgml
+io/usb/msd/slave/current/doc/usbs_msd.sgml
 hal/synth/arch/current/doc/synth.sgml
 hal/m68k/arch/current/doc/m68k.sgml
 hal/m68k/mcf52xx/var/current/doc/mcf52xx.sgml
 hal/m68k/mcf52xx/mcf5272/proc/current/doc/mcf5272.sgml
 hal/m68k/mcf52xx/mcf5272/m5272c3/current/doc/m5272c3.sgml
+hal/cortexm/kinetis/var/current/doc/kinetis_begin.sgml
+hal/cortexm/kinetis/var/current/doc/kinetis.sgml
+hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml
+hal/cortexm/kinetis/twr_k60n512/current/doc/twr_k60n512.sgml
+hal/cortexm/kinetis/twr_k60f120m/current/doc/twr_k60f120m.sgml
+hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml
+hal/cortexm/kinetis/var/current/doc/kinetis_end.sgml
+hal/cortexm/a2fxxx/a2f200_eval/current/doc/a2f200e.sgml
+hal/cortexm/lm3s/ek_lm3s811/current/doc/ek_lm3s811.sgml
+hal/cortexm/stm32/stm32f4discovery/current/doc/stm32f4discovery.sgml
 hal/sh/sh4_202_md/current/doc/sh4_202_md.sgml
 devs/usb/sa11x0/current/doc/usbs_sa11x0.sgml
 devs/usb/nec_upd985xx/current/doc/usbs_upd985xx.sgml
@@ -59,3 +70,6 @@ devs/framebuf/synth/current/doc/synth_fr
 devs/flash/amd/am29xxxxxv2/current/doc/am29xxxxx.sgml
 devs/flash/intel/stratav2/current/doc/strata.sgml
 devs/i2c/m68k/mcf52xx/current/doc/mcf52xx_i2c.sgml
+hal/misc/freescale/edma/current/doc/freescale_begin.sgml
+hal/misc/freescale/edma/current/doc/edma.sgml
+hal/misc/freescale/edma/current/doc/freescale_end.sgml
diff --git a/doc/sgml/makemakefile b/doc/sgml/makemakefile
--- a/doc/sgml/makemakefile
+++ b/doc/sgml/makemakefile
@@ -20,7 +20,7 @@ cat > makefile <<EOF
 # ####ECOSGPLCOPYRIGHTBEGIN####                                             
 # -------------------------------------------                               
 # This file is part of eCos, the Embedded Configurable Operating System.    
-# Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2009, 2010 Free Software Foundation, Inc.
+# Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc.
 #
 # eCos is free software; you can redistribute it and/or modify it under     
 # the terms of the GNU General Public License as published by the Free      
@@ -123,6 +123,9 @@ cat >> ecos-ref.sgml <<EOF
       <year>2008</year>
       <year>2009</year>
       <year>2010</year>
+      <year>2011</year>
+      <year>2012</year>
+      <year>2013</year>
       <holder>Free Software Foundation, Inc.</holder>
     </copyright>
 
diff --git a/doc/sgml/user-guide/ChangeLog b/doc/sgml/user-guide/ChangeLog
--- a/doc/sgml/user-guide/ChangeLog
+++ b/doc/sgml/user-guide/ChangeLog
@@ -1,3 +1,9 @@
+2011-08-25  John Dallaway  <john@dallaway.org.uk>
+
+	* target-setup.sgml: Add instructions for booting with GRUB2.
+	Patch from Stephen Polkowski. [ Bugzilla 1001254 ]
+	* user-guide.sgml: Update copyright dates.
+
 2010-02-17  John Dallaway  <john@dallaway.org.uk>
 
 	* introduction.sgml: Mention PPP, lwIP and uSTL. Mention
diff --git a/doc/sgml/user-guide/target-setup.sgml b/doc/sgml/user-guide/target-setup.sgml
--- a/doc/sgml/user-guide/target-setup.sgml
+++ b/doc/sgml/user-guide/target-setup.sgml
@@ -9,7 +9,7 @@
 <!-- =============================================================== -->
 <!-- ####ECOSDOCCOPYRIGHTBEGIN####                                       -->
 <!-- ===============================================================     -->
-<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. -->
+<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2011 Free Software Foundation, Inc. -->
 <!-- This material may be distributed only subject to the terms          -->
 <!-- and conditions set forth in the Open Publication License, v1.0      -->
 <!-- or later (the latest version is presently available at              -->
@@ -2974,7 +2974,7 @@ different disk.</para>
 </note>
 </sect2>
 <sect2>
-<title>GRUB Bootloader Support</title>
+<title>GRUB Bootloader Support (version 0.97)</title>
 <para>
 If an application is built with the GRUB startup type, it is
 configured to be loaded by the GRUB bootloader.
@@ -3033,6 +3033,85 @@ version 7.2 and later, you can just add 
 </para>
 </sect2>
 <sect2>
+<title>GRUB 2 Bootloader Support (version 1.98)</title>
+<para>
+If an application is built with the GRUB startup type, it is
+configured to be loaded by the GRUB bootloader.
+</para>
+<para>
+GRUB 2 is an open source boot loader that supports many different
+operating systems.  GRUB 2 is the sucessor to the legacy GRUB boot 
+loader.  It has been rewritten and requires a new configuration 
+file that is different from the legacy GRUB loader.
+It is available from
+<ulink
+url="http://www.gnu.org/software/grub">http://www.gnu.org/software/grub</ulink>.
+The latest version of GRUB should be downloaded from there and installed.
+Cygwin users will need to install the GRand Unified Bootloader package on their
+system.
+</para>
+<para>
+To install GRUB 2 on a disk drive from Cygwin you will first need to
+format your disk.  Begin by launching a windows Command Prompt with 
+ADMINISTRATOR priviledges. This example assumes that your destination
+drive is E and the filesystem type is FAT32.
+</para>
+<screen>
+$ <userinput>format e: /fs:fat32 /q</userinput>
+
+The type of the file system is FAT32.
+WARNING, ALL DATA ON NON-REMOVABLE DISK
+DRIVE E: WILL BE LOST!
+Proceed with Format (Y/N)? y
+QuickFormatting 512M
+Initializing the File Allocation Table (FAT)...
+Volume label (11 characters, ENTER for none)?
+Format complete.
+</screen>
+<para>
+When your drive is finished formatting, Cygwin will automatically
+mount the drive under /cygdrive/e.  Next, launch a bash shell.  
+Cygwin users should run their shell as ADMINISTRATOR otherwise 
+the grub-install program will fail.  To install GRUB we need to
+know the device name for your disk.  A second disk drive is usually
+called /dev/sdb.  The C: drive is usually called /dev/sda.  Determine
+your device name by reading the /proc/partitions file.
+This example uses /dev/sdb as input to the GRUB install program.
+</para>
+<screen>
+$ <userinput>cat /proc/partitions</userinput>
+major minor  #blocks  name
+    8     0 156290904 sda
+    8     1    102400 sda1
+    8     2 156185600 sda2
+    8    16 156290904 sdb
+    8    17    524288 sdb1
+
+$ <userinput>grub-install --root-directory=/cygdrive/e /dev/sdb</userinput>
+Installation finished. No error reported.
+
+$ <userinput>cp $ECOS_REPOSITORY/packages/hal/i386/pc/current/misc/grub.cfg /cygdrive/e/boot/grub</userinput>
+
+$ <userinput>cp redboot.elf /cygdrive/e/boot</userinput>
+</screen>
+<para>
+After installing GRUB 2, we need to a copy a configuration 
+file for grub to use.  The file <filename>grub.cfg</filename> is an example 
+configuration file that loads redboot.elf.  You should, of course, customize 
+this file to load your own application. Alternatively you can use the command-line 
+interface of GRUB to input commands yourself. Applications can be installed or 
+updated simply by copying them to the location expected by the 
+<filename>grub.cfg</filename> file. In this example the /boot directory is used.
+</para>
+<para>
+When installing GRUB on a hard disk, refer to the GRUB documentation. Be
+warned, however, that if you get this wrong it may compromise any
+existing bootloader that exists on the hard disk and may make any
+other operating systems unbootable. Practice on a spare disk or
+sacrificial hard disks first. 
+</para>
+</sect2>
+<sect2>
 <title>Debugging FLOPPY and GRUB Applications</title>
 <para>
 When RedBoot loads an application it also provides debugging services
diff --git a/doc/sgml/user-guide/user-guide.sgml b/doc/sgml/user-guide/user-guide.sgml
--- a/doc/sgml/user-guide/user-guide.sgml
+++ b/doc/sgml/user-guide/user-guide.sgml
@@ -73,7 +73,7 @@
 <BOOK ID="ECOS-USER-GUIDE">
   <bookinfo>
     <TITLE>eCos User Guide</TITLE>
-    <copyright><year>2001, 2002, 2003, 2004, 2009, 2010</year><holder>Free Software Foundation, Inc.</holder></copyright>
+    <copyright><year>2001, 2002, 2003, 2004, 2009, 2010, 2011</year><holder>Free Software Foundation, Inc.</holder></copyright>
 
     <legalnotice>
 	<title>Documentation licensing terms</title>
diff --git a/host/infra/ChangeLog b/host/infra/ChangeLog
--- a/host/infra/ChangeLog
+++ b/host/infra/ChangeLog
@@ -1,3 +1,8 @@
+2014-03-13  Andy Jackson  <andy@xylanta.com>
+
+	* trace.cxx: Silence "set but unused" variable warnings with
+	recent GCC. [ Bugzilla 1001949 ]
+
 2008-08-18  Bart Veer  <bartv@ecoscentric.com>
 
 	* configure.in, Makefile.am: update host-side configury
@@ -177,7 +182,7 @@ 1998-12-24  Bart Veer  <bartv@cygnus.co.
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc.            
+// Copyright (C) 1998, 1999, 2000, 2014 Free Software Foundation, Inc.            
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/host/infra/trace.cxx b/host/infra/trace.cxx
--- a/host/infra/trace.cxx
+++ b/host/infra/trace.cxx
@@ -10,7 +10,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -555,6 +555,7 @@ parse_msg(const char* msg, trace_entry& 
             format        += *msg++;
             long_version   = true;
         }
+        CYG_UNUSED_PARAM(bool, short_version);
 
         // The end of the format string has been reached.
         int format_ch  = *msg;
diff --git a/host/libcdl/ChangeLog b/host/libcdl/ChangeLog
--- a/host/libcdl/ChangeLog
+++ b/host/libcdl/ChangeLog
@@ -1,3 +1,8 @@
+2014-03-13  Andy Jackson  <andy@xylanta.com>
+
+	* build.cxx, expr.cxx: Silence "set but unused" variable
+	warnings with recent GCC. [ Bugzilla 1001949 ]
+
 2008-09-18  John Dallaway  <jld@ecoscentric.com>
 
 	* build.cxx (generate_config_headers): Create Tcl channels for
@@ -1006,7 +1011,7 @@ 1999-01-21  Bart Veer  <bartv@cygnus.co.
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1999, 2000, 2001, 2004, 2008 Free Software Foundation, Inc.
+// Copyright (C) 1999, 2000, 2001, 2004, 2008, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/host/libcdl/build.cxx b/host/libcdl/build.cxx
--- a/host/libcdl/build.cxx
+++ b/host/libcdl/build.cxx
@@ -10,7 +10,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1999, 2000, 2001, 2002, 2003, 2008 Free Software Foundation, Inc.
+// Copyright (C) 1999, 2000, 2001, 2002, 2003, 2008, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -639,6 +639,7 @@ CdlBuildableBody::update_all_build_info(
 
         result = CdlBuildableBody::split_custom_build_step(raw_data, target, deps, rules, error_msg);
         CYG_ASSERTC(true == result);
+        CYG_UNUSED_PARAM(bool, result);
 
         // Construct a local object, then copy it into the vector
         CdlBuildInfo_MakeObject local_copy;
@@ -676,6 +677,7 @@ CdlBuildableBody::update_all_build_info(
 
         result = CdlBuildableBody::split_custom_build_step(raw_data, target, deps, rules, error_msg);
         CYG_ASSERTC(true == result);
+        CYG_UNUSED_PARAM(bool, result);
 
         // Construct a local object, then copy it into the vector
         CdlBuildInfo_Make local_copy;
diff --git a/host/libcdl/expr.cxx b/host/libcdl/expr.cxx
--- a/host/libcdl/expr.cxx
+++ b/host/libcdl/expr.cxx
@@ -10,7 +10,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.            
+// Copyright (C) 1999, 2000, 2001, 2014 Free Software Foundation, Inc.            
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -2994,6 +2994,7 @@ CdlListExpressionBody::update(CdlTransac
             CYG_ASSERTC(handled);
             handled = pair_i->second->update(transact, source, source_prop, dest, change);
             CYG_ASSERTC(handled);
+            CYG_UNUSED_PARAM(bool, handled);
         }
         
         result = true;
diff --git a/host/tools/Utils/ChangeLog b/host/tools/Utils/ChangeLog
--- a/host/tools/Utils/ChangeLog
+++ b/host/tools/Utils/ChangeLog
@@ -1,3 +1,10 @@
+2014-03-13  Andy Jackson  <andy@xylanta.com>
+
+	* common/eCosStd.h: Silence "set but unused" variable warnings with
+	recent GCC. [ Bugzilla 1001949 ]
+	* common/Subprocess.cpp: Silence signed/unsigned compiler warning
+	with recent GCC. [ Bugzilla 1001955 ]
+
 2006-03-29  John Dallaway  <jld@ecoscentric.com>
 
 	* common/eCosSocket.h: Specify CeCosSerial as a friend class to
diff --git a/host/tools/Utils/common/Subprocess.cpp b/host/tools/Utils/common/Subprocess.cpp
--- a/host/tools/Utils/common/Subprocess.cpp
+++ b/host/tools/Utils/common/Subprocess.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2004 Free Software Foundation, Inc.      
+// Copyright (C) 1998, 1999, 2000, 2004, 2014 Free Software Foundation, Inc.      
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -638,7 +638,7 @@ bool CSubprocess::PSExtract(CSubprocess:
             
             if(dwPidSize/sizeof(DWORD)<dwMaxPids){
               rc=true;
-              for( DWORD dwIndex = 0 ; (signed)dwIndex < dwPidSize/sizeof(DWORD); dwIndex++ ) {
+              for( DWORD dwIndex = 0 ; dwIndex < dwPidSize/sizeof(DWORD); dwIndex++ ) {
                 // Regardless of OpenProcess success or failure, we
                 // still call the enum func with the ProcID.
                 DWORD pid=arPids[dwIndex];
diff --git a/host/tools/Utils/common/eCosStd.h b/host/tools/Utils/common/eCosStd.h
--- a/host/tools/Utils/common/eCosStd.h
+++ b/host/tools/Utils/common/eCosStd.h
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc.            
+// Copyright (C) 1998, 1999, 2000, 2014 Free Software Foundation, Inc.            
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -138,6 +138,9 @@ extern Time Now();
 extern int MIN(int a, int b);
 extern int MAX(int a, int b);
 
+// Get the CYG_UNUSED_PARAM() macro.
+#include <cyg/infra/cyg_type.h>
+
 #include <string.h>
 
 #include <time.h>
diff --git a/host/tools/configtool/ChangeLog b/host/tools/configtool/ChangeLog
--- a/host/tools/configtool/ChangeLog
+++ b/host/tools/configtool/ChangeLog
@@ -1,3 +1,75 @@
+2014-03-13  Andy Jackson  <andy@xylanta.com>
+
+	* standalone/wxwin/admindlg.cpp,
+	  standalone/wxwin/configtooldoc.cpp,
+	  standalone/wxwin/configtree.cpp: Silence "set but unused" variable
+	warnings with recent GCC. [ Bugzilla 1001949 ]
+	* standalone/common/ecosconfig.cxx: Update copyright string.
+	* standalone/wxwin/configtool.cpp,
+	  standalone/wxwin/configtooldoc.cpp,
+	  standalone/wxwin/configtree.cpp,
+	  standalone/wxwin/configtree.h,
+	  standalone/wxwin/filename.cpp,
+	  standalone/wxwin/packagesdlg.cpp,
+	  standalone/wxwin/propertywin.cpp,
+	  standalone/wxwin/runtestsdlg.cpp,
+	  standalone/wxwin/templatesdlg.cpp: Silence unused variable warnings
+	with recent GCC. [ Bugzilla 1001950 ]
+
+2014-02-28  Andy Jackson  <andy@xylanta.com>
+
+	* standalone/wxwin/standalone/wxwin/finddlg.cpp,
+	  standalone/wxwin/msgdlgex.cpp,
+	  standalone/wxwin/packagesdlg.cpp,
+	  standalone/wxwin/packagesdlg.h,
+	  standalone/wxwin/settingsdlg.cpp,
+	  standalone/wxwin/templatesdlg.cpp: Eliminate deprecated wxWidgets
+	calls. [ Bugzilla 1001947 ]
+	* standalone/wxwin/appsettings.cpp,
+	  standalone/wxwin/conflictsdlg.cpp: Silence initialization order
+	compiler warnings with recent GCC. [ Bugzilla 1001948 ]
+	* standalone/wxwin/appsettings.cpp,
+	  standalone/wxwin/conflictsdlg.cpp,
+	  standalonw/wxwin/docsystem.cpp,
+	  standalone/wxwin/ecutils.cpp,
+	  standalone/wxwin/packagesdlg.cpp: Silence miscellaneous compiler
+	warnings with recent GCC. [ Bugzilla 1001951 ]
+	* standalone/wxwin/mainwin.cpp, standalone/wxwin/configtool.cpp:
+	Update copyright strings.
+
+2013-03-15  John Dallaway  <john@dallaway.org.uk>
+
+	* standalone/wxwin/admindlg.cpp: Pass POSIX-style paths to
+	ecosadmin.tcl for recent versions of Cygwin. [ Bugzilla 1001798 ]
+	* standalone/wxwin/mainwin.cpp, standalone/wxwin/configtool.cpp:
+	Update copyright strings.
+
+2012-06-22  John Dallaway  <john@dallaway.org.uk>
+
+	* standalone/wxwin/makefile.gnu: Update linker flags for recent
+	versions of Fedora with modified DSO-linking semantics. Issue
+	reported by David Fernandez. [ Bugzilla 1001613 ]
+
+2012-04-23  John Dallaway  <john@dallaway.org.uk>
+
+	* standalone/wxwin/makefile.gnu: Update build flags for recent
+	versions of Cygwin.
+	* standalone/wxwin/configtool.cpp, standalone/wxwin/mainwin.cpp:
+	Update copyright strings.
+
+2011-02-07  John Dallaway  <john@dallaway.org.uk>
+
+	* standalone/wxwin/configitem.cpp: Escape newline chars in CDL
+	values for display and in-cell editing. [ Bugzilla 1001144 ]
+	* standalone/wxwin/mainwin.cpp, standalone/wxwin/configtool.cpp:
+	Update copyright strings.
+
+2010-09-10  John Dallaway  <john@dallaway.org.uk>
+
+	* standalone/wxwin/configtooldoc.cpp: Allow import/export of
+	eCos minimal configuration files with non-standard file suffixes.
+	Based on patch from Ross Younger. [ Bugzilla 85580 ]
+
 2010-02-17  John Dallaway  <john@dallaway.org.uk>
 
 	* standalone/common/ecosconfig.cxx: Fix compilation on recent
diff --git a/host/tools/configtool/standalone/common/ecosconfig.cxx b/host/tools/configtool/standalone/common/ecosconfig.cxx
--- a/host/tools/configtool/standalone/common/ecosconfig.cxx
+++ b/host/tools/configtool/standalone/common/ecosconfig.cxx
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2010 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2010, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -50,7 +50,7 @@
 #include "ecosconfig.hxx"
 
 #define TOOL_VERSION "3.net"
-#define TOOL_COPYRIGHT "Copyright (c) 2002-2010 Free Software Foundation, Inc."
+#define TOOL_COPYRIGHT "Copyright (c) 2002-2014 Free Software Foundation, Inc."
 #define DEFAULT_SAVE_FILE "ecos.ecc"
 static const char* tool = "ecosconfig";
 
diff --git a/host/tools/configtool/standalone/wxwin/admindlg.cpp b/host/tools/configtool/standalone/wxwin/admindlg.cpp
--- a/host/tools/configtool/standalone/wxwin/admindlg.cpp
+++ b/host/tools/configtool/standalone/wxwin/admindlg.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2003 Free Software Foundation, Inc.      
+// Copyright (C) 1998, 1999, 2000, 2003, 2013, 2014 Free Software Foundation, Inc.      
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -240,8 +240,7 @@ void ecAdminDialog::OnAdd(wxCommandEvent
                 // extract the licence file
 
                 wxString strCommand;
-                strCommand.Printf(wxT("add %s --extract_license"), (const wxChar*) strPathName);
-                strCommand.Replace(wxT("\\"), wxT("/")); // backslashes -> forward slashes for Tcl_EvalFile
+                strCommand.Printf(wxT("add %s --extract_license"), (const wxChar*) ecUtils::NativeToPosixPath(strPathName));
                 EvalTclFile (3, strCommand, _("Adding package"));
 
                 wxString strLicenseFile = m_strRepository + wxString(wxFILE_SEP_PATH) + wxT("pkgadd.txt");
@@ -277,8 +276,7 @@ void ecAdminDialog::OnAdd(wxCommandEvent
                 
                 // add the contents of the package distribution file
                 
-                strCommand.Printf (wxT("add %s --accept_license"), (const wxChar*) strPathName);
-                strCommand.Replace (wxT("\\"), wxT("/")); // backslashes -> forward slashes for Tcl_EvalFile
+                strCommand.Printf (wxT("add %s --accept_license"), (const wxChar*) ecUtils::NativeToPosixPath(strPathName));
                 if (! EvalTclFile (3, strCommand, _("Adding package")))  // if not successful
                 {
                     // try the next file
@@ -474,6 +472,7 @@ bool ecAdminDialog::PopulatePackageTree 
     
     // Add a root item
     wxTreeItemId rootId = m_treeCtrl->AddRoot(_("Packages"), 0, -1);
+    CYG_UNUSED_PARAM(wxTreeItemId, rootId);
 
     // populate the new package tree
     
@@ -521,14 +520,14 @@ bool ecAdminDialog::EvalTclFile(int narg
 
     wxString strArgc;
     strArgc.Printf (wxT("%d"), nargc);
-    std::string argv0 = ecUtils::UnicodeToStdStr (m_strRepository) + "/ecosadmin.tcl";
+    std::string argv0 = ecUtils::UnicodeToStdStr (ecUtils::NativeToPosixPath (m_strRepository)) + "/ecosadmin.tcl";
     std::string argv = ecUtils::UnicodeToStdStr (Argv);
     std::string argc = ecUtils::UnicodeToStdStr (strArgc);
 
     Tcl_Interp * interp = Tcl_CreateInterp ();
 
 #ifdef __WXMSW__
-    Tcl_Channel outchan = Tcl_OpenFileChannel (interp, "nul", "a+", 777);
+    Tcl_Channel outchan = Tcl_OpenFileChannel (interp, "/dev/null", "a+", 777);
     Tcl_SetStdChannel (outchan, TCL_STDOUT); // direct standard output to NUL:
 #endif
 
@@ -536,6 +535,7 @@ bool ecAdminDialog::EvalTclFile(int narg
     pszStatus = Tcl_SetVar (interp, "argv", (char*) argv.c_str(), 0);
     pszStatus = Tcl_SetVar (interp, "argc", (char*) argc.c_str(), 0);
     pszStatus = Tcl_SetVar (interp, "gui_mode", "1", 0); // return errors in result string
+    CYG_UNUSED_PARAM(const char *, pszStatus);
     int nStatus = Tcl_EvalFile (interp, (char*) argv0.c_str());
     const char* result = Tcl_GetStringResult (interp);
 
diff --git a/host/tools/configtool/standalone/wxwin/appsettings.cpp b/host/tools/configtool/standalone/wxwin/appsettings.cpp
--- a/host/tools/configtool/standalone/wxwin/appsettings.cpp
+++ b/host/tools/configtool/standalone/wxwin/appsettings.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2003, 2005, 2006, 2008 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2003, 2005, 2006, 2008, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -351,7 +351,7 @@ bool ecSettings::LoadConfig()
 #ifdef __WXMSW__
         SYSTEM_INFO SystemInfo;
         GetSystemInfo(&SystemInfo);
-        m_strMakeOptions.Printf(_T("-j%d"),SystemInfo.dwNumberOfProcessors);
+        m_strMakeOptions.Printf(_T("-j%ld"),SystemInfo.dwNumberOfProcessors);
 #else
         long lProcessors;
         lProcessors = sysconf(_SC_NPROCESSORS_ONLN);
@@ -909,13 +909,13 @@ ecRunTestsSettings::ecRunTestsSettings()
     m_nDownloadTimeoutType(TIMEOUT_SPECIFIED),
     m_bRemote(FALSE),
     m_bSerial(TRUE),
-    m_strPort(wxT("/dev/ttyS0")),
     m_nBaud(38400),
     m_nLocalTCPIPPort(9000),
     m_nReset(RESET_MANUAL),
     m_nResourcePort(1),
     m_nRemotePort(1),
-    m_bFarmed(TRUE),
+    m_bFarmed(TRUE),
+    m_strPort(wxT("/dev/ttyS0")),
     m_strRemoteHost(wxT("")),
     m_strResourceHost(wxT("")),
     m_strLocalTCPIPHost(wxT("")),
diff --git a/host/tools/configtool/standalone/wxwin/configitem.cpp b/host/tools/configtool/standalone/wxwin/configitem.cpp
--- a/host/tools/configtool/standalone/wxwin/configitem.cpp
+++ b/host/tools/configtool/standalone/wxwin/configitem.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2006, 2008, 2009 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2006, 2008, 2009, 2011 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -434,6 +434,7 @@ wxString ecConfigItem::GetDisplayValue()
         {
             if (GetCdlValuable())
                 str = StringValue();
+                str.Replace("\n", "\\n"); // escape any newline chars (eg CYGDAT_UITRON_TASK_INITIALIZERS)
         }
         break;
     default:
@@ -610,7 +611,9 @@ bool ecConfigItem::TransferDataFromWindo
         wxASSERT ( GetOptionType() == ecString );
 
         // TODO: do checking
-        doc->SetValue(*this, win->GetValue());
+        wxString str(win->GetValue());
+        str.Replace("\\n", "\n"); // remove escaping of newline chars
+        doc->SetValue(*this, str);
     }
     else if (window->IsKindOf(CLASSINFO(ecDoubleEditorCtrl)))
     {
@@ -1380,6 +1383,7 @@ void ecTextEditorCtrl::OnLeftDClick(wxMo
     ecConfigToolDoc* doc = wxGetApp().GetConfigToolDoc();
     
     wxString initialValue(GetValue());
+    initialValue.Replace("\\n", "\n"); // remove escaping of newline chars
     
     ecEditStringDialog dialog(initialValue, wxGetApp().GetTopWindow(), ecID_EDIT_STRING_DIALOG);
     if (dialog.ShowModal() == wxID_OK)
diff --git a/host/tools/configtool/standalone/wxwin/configtool.cpp b/host/tools/configtool/standalone/wxwin/configtool.cpp
--- a/host/tools/configtool/standalone/wxwin/configtool.cpp
+++ b/host/tools/configtool/standalone/wxwin/configtool.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2003, 2004, 2005, 2006, 2008, 2009 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2003, 2004, 2005, 2006, 2008, 2009, 2011, 2012, 2013, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -284,7 +284,7 @@ bool ecApp::OnInit()
         wxLog::SetActiveTarget(new wxLogStderr);
 #endif
         wxString msg;
-        msg.Printf(wxT("eCos Configuration Tool (c) Free Software Foundation, Inc., 1998-2009 Version %s, %s"), ecCONFIGURATION_TOOL_VERSION, __DATE__);
+        msg.Printf(wxT("eCos Configuration Tool (c) Free Software Foundation, Inc., 1998-2014 Version %s, %s"), ecCONFIGURATION_TOOL_VERSION, __DATE__);
         wxLogMessage(msg);
         return FALSE;
     }
@@ -781,6 +781,8 @@ bool ecApp::InitializeHelpController()
 
             wxGetApp().GetHelpController().SetBookBasePath(htmlDir);
         }
+#else
+        CYG_UNUSED_PARAM(ecConfigToolDoc *, doc);
 #endif
         return TRUE;
     }
diff --git a/host/tools/configtool/standalone/wxwin/configtooldoc.cpp b/host/tools/configtool/standalone/wxwin/configtooldoc.cpp
--- a/host/tools/configtool/standalone/wxwin/configtooldoc.cpp
+++ b/host/tools/configtool/standalone/wxwin/configtooldoc.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2003, 2005, 2006, 2008, 2009 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2003, 2005, 2006, 2008, 2009, 2010, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -355,6 +355,7 @@ bool ecConfigToolDoc::CanGenerateBuildTr
     }
     else
         return FALSE;
+    CYG_UNUSED_PARAM(int, nCount);
 
     return TRUE;
 }
@@ -382,6 +383,7 @@ bool ecConfigToolDoc::GenerateBuildTree(
             // copy new MLT files to the build tree as necessary
             bool rc = generate_build_tree (GetCdlConfig(), ecUtils::UnicodeToStdStr(m_strBuildTree.CygPath()), ecUtils::UnicodeToStdStr(m_strInstallTree.CygPath()));
             rc = TRUE;
+            CYG_UNUSED_PARAM(bool, rc);
         }
 
     }
@@ -1307,6 +1309,7 @@ CdlInferenceCallbackResult ecConfigToolD
         wxGetApp().UnlockValues();
 
     }
+    CYG_UNUSED_PARAM(ecConfigToolDoc *, pDoc);
     return rc;
 }
 
@@ -1360,6 +1363,7 @@ void ecConfigToolDoc::CdlTransactionHand
         (CdlValueSource_Inferred == source) ? "inferred" :
         (CdlValueSource_Wizard   == source) ? "wizard"   : "user"));
 */
+        CYG_UNUSED_PARAM(CdlValueSource, source);
         pControlView->Refresh (strName);
     }
 
@@ -2144,12 +2148,17 @@ const wxString ecConfigToolDoc::CurrentM
 
 bool ecConfigToolDoc::ExportFile()
 {
+    wxFileDialog dialog(wxGetApp().GetTopWindow(), _("Export eCos Minimal Configuration"),
+        wxT(""), wxT(""),
+#ifdef __WXMSW__
+	wxT("eCos Minimal Configuration Files (*.ecm)|*.ecm|All Files (*.*)|*.*"),
+#else
+	wxT("eCos Minimal Configuration Files (*.ecm)|*.ecm|All Files (*)|*"),
+#endif
 #if wxCHECK_VERSION(2, 6, 0)
-    wxFileDialog dialog(wxGetApp().GetTopWindow(), _("Export eCos Minimal Configuration"),
-        wxT(""), wxT(""), wxT("eCos Minimal Configuration (*.ecm)|*.ecm"), wxSAVE|wxOVERWRITE_PROMPT);
+	wxSAVE|wxOVERWRITE_PROMPT);
 #else
-    wxFileDialog dialog(wxGetApp().GetTopWindow(), _("Export eCos Minimal Configuration"),
-        wxT(""), wxT(""), wxT("eCos Minimal Configuration (*.ecm)|*.ecm"), wxSAVE|wxOVERWRITE_PROMPT|wxHIDE_READONLY);
+	wxSAVE|wxOVERWRITE_PROMPT|wxHIDE_READONLY);
 #endif
 
     if (dialog.ShowModal() == wxID_OK)
@@ -2178,12 +2187,17 @@ bool ecConfigToolDoc::ExportFile()
 
 bool ecConfigToolDoc::ImportFile()
 {
+    wxFileDialog dialog(wxGetApp().GetTopWindow(), _("Import eCos Minimal Configuration"),
+        wxT(""), wxT(""),
+#ifdef __WXMSW__
+	wxT("eCos Minimal Configuration Files (*.ecm)|*.ecm|All Files (*.*)|*.*"),
+#else
+	wxT("eCos Minimal Configuration Files (*.ecm)|*.ecm|All Files (*)|*"),
+#endif
 #if wxCHECK_VERSION(2, 6, 0)
-    wxFileDialog dialog(wxGetApp().GetTopWindow(), _("Import eCos Minimal Configuration"),
-        wxT(""), wxT(""), wxT("eCos Minimal Configuration (*.ecm)|*.ecm"), wxOPEN|wxFILE_MUST_EXIST);
+	wxOPEN|wxFILE_MUST_EXIST);
 #else
-    wxFileDialog dialog(wxGetApp().GetTopWindow(), _("Import eCos Minimal Configuration"),
-        wxT(""), wxT(""), wxT("eCos Minimal Configuration (*.ecm)|*.ecm"), wxOPEN|wxFILE_MUST_EXIST|wxHIDE_READONLY);
+	wxOPEN|wxFILE_MUST_EXIST|wxHIDE_READONLY);
 #endif
 
     if (dialog.ShowModal() == wxID_OK)
@@ -2236,6 +2250,7 @@ bool ecConfigToolDoc::SwitchMemoryLayout
         // copy default MLT save files for the selected target/platform from the repository to the build tree if they do not already exist
         CopyMLTFiles();
     }
+    CYG_UNUSED_PARAM(bool, rc);
 
     if (m_strBuildTree.IsEmpty ()) // load the memory layout from the repository
     {
diff --git a/host/tools/configtool/standalone/wxwin/configtree.cpp b/host/tools/configtool/standalone/wxwin/configtree.cpp
--- a/host/tools/configtool/standalone/wxwin/configtree.cpp
+++ b/host/tools/configtool/standalone/wxwin/configtree.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2008, 2009 Free Software Foundation, Inc.      
+// Copyright (C) 1998, 1999, 2000, 2008, 2009, 2014 Free Software Foundation, Inc.      
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -408,6 +408,7 @@ void ecValueWindow::OnMouseEvent(wxMouse
             m_treeCtrl->SelectItem(item);
             ((ecConfigTreeCtrl*) m_treeCtrl)->GetPropertiesMenu()->SetClientData((void*) TRUE);
             PopupMenu(((ecConfigTreeCtrl*) m_treeCtrl)->GetPropertiesMenu(), event.GetX(), event.GetY());
+            CYG_UNUSED_PARAM(ecConfigItem *, configItem);
         }
         else
         {
@@ -717,6 +718,7 @@ void ecSplitterScrolledWindow::OnPropert
         // or not
         menu = (wxMenu*) obj;
     }
+    CYG_UNUSED_PARAM(wxMenu *, menu);
 
     ecConfigTreeCtrl* treeCtrl = (ecConfigTreeCtrl*) FindWindow(ecID_TREE_CTRL);
     wxASSERT (treeCtrl != NULL) ;
@@ -903,6 +905,7 @@ void ecSplitterScrolledWindow::OnUpdateR
         ecConfigItem* item = ((ecTreeItemData*) treeCtrl->GetItemData(id))->GetConfigItem();
         
         event.Enable( IsChanged(id, TRUE ) );
+        CYG_UNUSED_PARAM(ecConfigItem *, item);
     }
 }
 
diff --git a/host/tools/configtool/standalone/wxwin/configtree.h b/host/tools/configtool/standalone/wxwin/configtree.h
--- a/host/tools/configtool/standalone/wxwin/configtree.h
+++ b/host/tools/configtool/standalone/wxwin/configtree.h
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2008 Free Software Foundation, Inc.      
+// Copyright (C) 1998, 1999, 2000, 2008, 2014 Free Software Foundation, Inc.      
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -105,7 +105,7 @@ public:
     // enabled/disabled
     int GetStateCount() const { return m_maxStates; };
 
-    void SetStateCount(int count) { m_maxStates; }
+    void SetStateCount(int count) { /* m_maxStates; */ }
     int GetIconId(int state, bool enabled = TRUE) const;
     void SetIconId(int state, bool enabled, int iconId);
 
diff --git a/host/tools/configtool/standalone/wxwin/conflictsdlg.cpp b/host/tools/configtool/standalone/wxwin/conflictsdlg.cpp
--- a/host/tools/configtool/standalone/wxwin/conflictsdlg.cpp
+++ b/host/tools/configtool/standalone/wxwin/conflictsdlg.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc.            
+// Copyright (C) 1998, 1999, 2000, 2014 Free Software Foundation, Inc.            
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -85,11 +85,10 @@ END_EVENT_TABLE()
 
 // Frame constructor
 ecResolveConflictsDialog::ecResolveConflictsDialog(wxWindow* parent, std::list<CdlConflict> conflicts, CdlTransaction transaction, wxList *parConflictsOfInterest):
+    m_Map(wxKEY_INTEGER),
     m_conflicts(conflicts),
     m_Transaction(transaction),
-    m_parConflictsOfInterest(parConflictsOfInterest),
-    m_Map(wxKEY_INTEGER)
-
+    m_parConflictsOfInterest(parConflictsOfInterest)
 {
     // Stop values from being changed by other mechanisms during the
     // duration of this dialog.
@@ -313,6 +312,8 @@ void ecResolveConflictsDialog::OnContinu
                     case CdlValueFlavor_Data :
                         str.Printf(_("set %s to %s\n"), (const wxChar*) strName, (const wxChar*) strValue);
                         valuable->set_value (m_Transaction, ecUtils::UnicodeToStdStr (strValue), CdlValueSource_User);
+                        break;
+                    default :
                         break;
                     }
                 }
@@ -455,6 +456,8 @@ void ecResolveConflictsDialog::AddConfli
             break;
         case CdlValueFlavor_Data :
             strValue = value.get_value().c_str();
+            break;
+        default :
             break;
         }
         
diff --git a/host/tools/configtool/standalone/wxwin/docsystem.cpp b/host/tools/configtool/standalone/wxwin/docsystem.cpp
--- a/host/tools/configtool/standalone/wxwin/docsystem.cpp
+++ b/host/tools/configtool/standalone/wxwin/docsystem.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2003, 2008 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2003, 2008, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -493,10 +493,11 @@ mainwin=\"eCos Documentation\",\"eCos.hh
 index.html\n\
 \n\
 [INFOTYPES]\n" ;
-
+
+/*
     // When we have the ability to generate a hhk, replace above line with:
     // mainwin=\"eCos Documentation\",\"eCos.hhc\",\"eCos.hhk\",,\"index.html\",\"http://sources.redhat.com/ecos/\",\"Net Release\",\"http://www.redhat.com/products/ecos/\",\"eCos Product\",0x40060420,,0xc287e,[0,0,762,400],,,,,,,0\n\
-
+*/
     return TRUE;
 
 }
diff --git a/host/tools/configtool/standalone/wxwin/ecutils.cpp b/host/tools/configtool/standalone/wxwin/ecutils.cpp
--- a/host/tools/configtool/standalone/wxwin/ecutils.cpp
+++ b/host/tools/configtool/standalone/wxwin/ecutils.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2003, 2008 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2003, 2008, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -202,7 +202,7 @@ bool ecUtils::StrToItemIntegerType(const
 const wxString ecUtils::IntToStr(long d,bool bHex)
 {
   wxString s;
-  s.Printf(bHex?wxT("0x%08x"):wxT("%d"),d);
+  s.Printf(bHex?wxT("0x%08lx"):wxT("%ld"),d);
   return s;
 }
 
diff --git a/host/tools/configtool/standalone/wxwin/filename.cpp b/host/tools/configtool/standalone/wxwin/filename.cpp
--- a/host/tools/configtool/standalone/wxwin/filename.cpp
+++ b/host/tools/configtool/standalone/wxwin/filename.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2003, 2005, 2009 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2003, 2005, 2009, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -220,6 +220,7 @@ void ecFileName::ConcatCopy(const wxStri
             return;
         }
     }
+    CYG_UNUSED_PARAM(int, nNewLen);
 }
 
 void ecFileName::Normalize()
diff --git a/host/tools/configtool/standalone/wxwin/finddlg.cpp b/host/tools/configtool/standalone/wxwin/finddlg.cpp
--- a/host/tools/configtool/standalone/wxwin/finddlg.cpp
+++ b/host/tools/configtool/standalone/wxwin/finddlg.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc.            
+// Copyright (C) 1998, 1999, 2000, 2014 Free Software Foundation, Inc.            
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -237,7 +237,11 @@ void ecFindDialog::OnFindNext(wxCommandE
 
             rect2 = GetRect(); // screen coords
 
-            if (rect2.Inside(topLeft) || rect2.Inside(bottomRight))
+#if wxCHECK_VERSION(2, 8, 0)
+            if (rect2.Contains(topLeft) || rect2.Contains(bottomRight))
+#else
+            if (rect2.Inside(topLeft) || rect2.Inside(bottomRight))
+#endif
             {
                 Move(wxPoint(topLeft.x + rect1.width, rect2.y));
             }
diff --git a/host/tools/configtool/standalone/wxwin/mainwin.cpp b/host/tools/configtool/standalone/wxwin/mainwin.cpp
--- a/host/tools/configtool/standalone/wxwin/mainwin.cpp
+++ b/host/tools/configtool/standalone/wxwin/mainwin.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2003, 2004, 2005, 2006, 2008, 2009 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2003, 2004, 2005, 2006, 2008, 2009, 2011, 2012, 2013, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -571,7 +571,7 @@ void ecMainFrame::OnAbout(wxCommandEvent
 	int iTclVerMajor, iTclVerMinor, iTclVerPatchLevel;
 	Tcl_GetVersion (&iTclVerMajor, &iTclVerMinor, &iTclVerPatchLevel, NULL);
 	msg.Printf("eCos Configuration Tool %s (%s %s)\n\n"
-		"Copyright (c) Free Software Foundation, Inc. 1998-2009\n\n"
+		"Copyright (c) Free Software Foundation, Inc. 1998-2014\n\n"
 		"Using %s %s and Tcl %d.%d.%d",
 		ecCONFIGURATION_TOOL_VERSION, __DATE__, __TIME__,
 		wxPlatformInfo::Get().GetPortIdName().c_str(), wxVERSION_NUM_DOT_STRING,
diff --git a/host/tools/configtool/standalone/wxwin/makefile.gnu b/host/tools/configtool/standalone/wxwin/makefile.gnu
--- a/host/tools/configtool/standalone/wxwin/makefile.gnu
+++ b/host/tools/configtool/standalone/wxwin/makefile.gnu
@@ -1,7 +1,7 @@
 # ####ECOSHOSTGPLCOPYRIGHTBEGIN####
 # -------------------------------------------                              
 # This file is part of the eCos host tools.                                
-# Copyright (C) 2003, 2005, 2006 Free Software Foundation, Inc.
+# Copyright (C) 2003, 2005, 2006, 2012 Free Software Foundation, Inc.
 #
 # This program is free software; you can redistribute it and/or modify     
 # it under the terms of the GNU General Public License as published by     
@@ -59,14 +59,14 @@ EXTRALDFLAGS=-L$(TCLDIR)/lib -L$(INSTALL
 
 ifneq (,$(findstring CYGWIN, $(shell uname)))
   PROGRAM=configtool.exe
-  CPPFLAGS=`$(WXDIR)/bin/wx-config --cppflags` -D_WIN32 -D__WIN32__ -DSTRICT -D__USE_W32_SOCKETS
+  CPPFLAGS=`$(WXDIR)/bin/wx-config --cppflags` -DSTRICT -D__USE_W32_SOCKETS
   LDFLAGS=`$(WXDIR)/bin/wx-config --libs std,gizmos` -lshlwapi -Wl,--subsystem,windows
   EXTRAOBJECTS=$(CTBUILDDIR)/configtoolres.o
   RCFLAGS=`$(WXDIR)/bin/wx-config --cppflags`
 else
   PROGRAM=configtool
   CPPFLAGS=`$(WXDIR)/bin/wx-config --cppflags`
-  LDFLAGS=`$(WXDIR)/bin/wx-config --libs std,gizmos`
+  LDFLAGS=-lX11 `$(WXDIR)/bin/wx-config --libs std,gizmos`
   EXTRAOBJECTS=
   RCFLAGS=`$(WXDIR)/bin/wx-config --cppflags`
 endif
diff --git a/host/tools/configtool/standalone/wxwin/msgdlgex.cpp b/host/tools/configtool/standalone/wxwin/msgdlgex.cpp
--- a/host/tools/configtool/standalone/wxwin/msgdlgex.cpp
+++ b/host/tools/configtool/standalone/wxwin/msgdlgex.cpp
@@ -46,7 +46,10 @@
 #include "wx/statbox.h"
 #include "wx/stattext.h"
 #include "wx/statbmp.h"
-#include "wx/bmpbuttn.h"
+#include "wx/bmpbuttn.h"
+#if wxCHECK_VERSION(2, 8, 0)
+#include "wx/artprov.h"
+#endif
 
 //----------------------------------------------------------------------------
 // wxMessageDialogEx
@@ -73,8 +76,13 @@ wxMessageDialogEx::wxMessageDialogEx( wx
     // 1) icon
     if (style & wxICON_MASK)
     {
-         wxStaticBitmap *icon = new wxStaticBitmap(
-            this, -1, wxTheApp->GetStdIcon((int)(style & wxICON_MASK)));
+#if wxCHECK_VERSION(2, 8, 0)
+         wxStaticBitmap *icon = new wxStaticBitmap(this, wxID_ANY,
+                            wxArtProvider::GetIcon(wxART_INFORMATION));
+#else
+         wxStaticBitmap *icon = new wxStaticBitmap(
+            this, -1, wxTheApp->GetStdIcon((int)(style & wxICON_MASK)));
+#endif
          icon_text->Add( icon, 0, wxCENTER );
     }
 
diff --git a/host/tools/configtool/standalone/wxwin/packagesdlg.cpp b/host/tools/configtool/standalone/wxwin/packagesdlg.cpp
--- a/host/tools/configtool/standalone/wxwin/packagesdlg.cpp
+++ b/host/tools/configtool/standalone/wxwin/packagesdlg.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2003, 2005, 2009 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2003, 2005, 2009, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -97,7 +97,11 @@ m_timer(this)
     m_keywords = wxEmptyString;
     m_updateLists = FALSE;
     m_updateInterval = 600; // Milliseconds
-    wxStartTimer();
+#if wxCHECK_VERSION(2, 8, 0)
+    m_StopWatch.Start();
+#else
+    wxStartTimer();
+#endif
     
     SetExtraStyle(wxDIALOG_EX_CONTEXTHELP);
     
@@ -362,10 +366,18 @@ void ecPackagesDialog::Fill()
     // wxGTK doesn't deselect items properly when clearing, I think
     int i;
     for (i = 0; i < availableList->GetCount(); i++)
-        if (availableList->Selected(i))
+#if wxCHECK_VERSION(2, 8, 0)
+        if (availableList->IsSelected(i))
+#else
+        if (availableList->Selected(i))
+#endif
             availableList->Deselect(i);
     for (i = 0; i < useList->GetCount(); i++)
-        if (useList->Selected(i))
+#if wxCHECK_VERSION(2, 8, 0)
+        if (useList->IsSelected(i))
+#else
+        if (useList->Selected(i))
+#endif
             useList->Deselect(i);
     
     availableList->Clear();
@@ -613,6 +625,8 @@ void ecPackagesDialog::OnClickListBox1(w
         // TODO: check that this works for multiple-selection listboxes
         DisplayDescription(availableList->GetString(sel));
     }
+#else
+    CYG_UNUSED_PARAM(wxListBox *, availableList);
 #endif
     
     ClearSelections(*useList);
@@ -634,6 +648,8 @@ void ecPackagesDialog::OnClickListBox2(w
         // TODO: check that this works for multiple-selection listboxes
         DisplayDescription(useList->GetString(sel));
     }
+#else
+    CYG_UNUSED_PARAM(wxListBox *, useList);
 #endif
     
     ClearSelections(*availableList);
@@ -698,7 +714,11 @@ void ecPackagesDialog::OnClearKeywords(w
     TransferDataFromWindow();
     Fill();
     m_updateLists = FALSE;
-    wxStartTimer();
+#if wxCHECK_VERSION(2, 8, 0)
+    m_StopWatch.Start();
+#else
+    wxStartTimer();
+#endif
     FindWindow( ecID_PACKAGES_DIALOG_KEYWORDS )->SetFocus();
 }
 
@@ -713,7 +733,11 @@ void ecPackagesDialog::OnUpdateKeywordTe
     
     TransferDataFromWindow();
     m_updateLists = TRUE;
-    wxStartTimer();
+#if wxCHECK_VERSION(2, 8, 0)
+    m_StopWatch.Start();
+#else
+    wxStartTimer();
+#endif
 }
 
 void ecPackagesDialog::OnClickOmitHardwarePackages(wxCommandEvent& event)
@@ -730,12 +754,20 @@ void ecPackagesDialog::OnClickExactMatch
 
 void ecPackagesDialog::OnIdle(wxIdleEvent& event)
 {
-    long elapsed = wxGetElapsedTime(FALSE);
+#if wxCHECK_VERSION(2, 8, 0)
+    long elapsed = m_StopWatch.Time();
+#else
+    long elapsed = wxGetElapsedTime(FALSE);
+#endif
     if (m_updateLists && (elapsed > m_updateInterval))
     {
         m_updateLists = FALSE;
         Fill();
-        wxStartTimer();
+#if wxCHECK_VERSION(2, 8, 0)
+        m_StopWatch.Start();
+#else
+        wxStartTimer();
+#endif
     }
 }
 
@@ -753,6 +785,8 @@ void ecPackagesDialog::Insert(const wxSt
         m_added.Add(str);
     
     //(added ? useList : availableList) -> Append(str);
+    CYG_UNUSED_PARAM(wxListBox *, availableList);
+    CYG_UNUSED_PARAM(wxListBox *, useList);
 }
 
 bool ecPackagesDialog::IsAdded(const wxString& str)
@@ -761,7 +795,8 @@ bool ecPackagesDialog::IsAdded(const wxS
     
     //	return (((wxListBox*) FindWindow( ecID_PACKAGES_DIALOG_USE_LIST ))->FindString(str) > -1) ;
 }
-
+
+#if 0
 static int ecPositionInStringList(const wxStringList& list, const wxString& item)
 {
     int i;
@@ -772,6 +807,7 @@ static int ecPositionInStringList(const 
             i ++;
         return -1;
 }
+#endif
 
 void ecPackagesDialog::DisplayDescription(const wxString& item)
 {
@@ -937,6 +973,7 @@ void ecPackagesDialog::UpdatePackageDesc
         m_packageDescription = wxEmptyString;
     }
     TransferDataToWindow ();
+    CYG_UNUSED_PARAM(ecConfigToolDoc *, pDoc);
 }
 
 void ecPackagesDialog::UpdateVersionList ()
diff --git a/host/tools/configtool/standalone/wxwin/packagesdlg.h b/host/tools/configtool/standalone/wxwin/packagesdlg.h
--- a/host/tools/configtool/standalone/wxwin/packagesdlg.h
+++ b/host/tools/configtool/standalone/wxwin/packagesdlg.h
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc.            
+// Copyright (C) 1998, 1999, 2000, 2014 Free Software Foundation, Inc.            
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -143,7 +143,10 @@ private:
     wxString        m_keywords;
     bool            m_updateLists; // If true, the keyword changed and we need to update the lists
     long            m_updateInterval; // Interval before display is updated
-    ecPackagesTimer m_timer;
+    ecPackagesTimer m_timer;
+#if wxCHECK_VERSION(2, 8, 0)
+    wxStopWatch     m_StopWatch;
+#endif
 };
 
 #define ecID_PACKAGES_DIALOG_AVAILABLE_LIST     10066
diff --git a/host/tools/configtool/standalone/wxwin/propertywin.cpp b/host/tools/configtool/standalone/wxwin/propertywin.cpp
--- a/host/tools/configtool/standalone/wxwin/propertywin.cpp
+++ b/host/tools/configtool/standalone/wxwin/propertywin.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2008, 2009 Free Software Foundation, Inc.      
+// Copyright (C) 1998, 1999, 2000, 2008, 2009, 2014 Free Software Foundation, Inc.      
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -296,6 +296,7 @@ void ecPropertyListCtrl::Fill(ecConfigIt
 
                     // TODO: set the image for a conflict item
                     // CListCtrl::SetItem (nIndex, 0, LVIF_IMAGE, NULL, bConflictItem ? 1 : 0, 0, 0, 0 );
+                    CYG_UNUSED_PARAM(bool, bConflictItem);
                 }
             }
         }
@@ -360,6 +361,7 @@ void ecPropertyListCtrl::RefreshValue()
         
         // TODO
         // CListCtrl::SetItem (nItem, 0, LVIF_IMAGE, NULL, bConflictItem ? 1 : 0, 0, 0, 0 );
+        CYG_UNUSED_PARAM(bool, bConflictItem);
     }
     
 }
diff --git a/host/tools/configtool/standalone/wxwin/runtestsdlg.cpp b/host/tools/configtool/standalone/wxwin/runtestsdlg.cpp
--- a/host/tools/configtool/standalone/wxwin/runtestsdlg.cpp
+++ b/host/tools/configtool/standalone/wxwin/runtestsdlg.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc.            
+// Copyright (C) 1998, 1999, 2000, 2014 Free Software Foundation, Inc.            
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -383,7 +383,7 @@ wxString ecRunTestsDialog::TranslatePort
 
 void ecRunTestsDialog::SubmitTests()
 {
-    int iTest;
+//    int iTest;
     int nResources=wxGetApp().GetSettings().GetRunTestsSettings().m_bRemote ? wxMax(1,CTestResource::GetMatchCount (m_ep)):1;
     if(nResources>CeCosTest::InstanceCount){
         if (m_nNextToSubmit >= m_executables->SelectedTestCount()){
@@ -725,6 +725,7 @@ void ecRunTestsExecutablesDialog::Create
 
     parent->SetAutoLayout( TRUE );
     parent->SetSizer( item0 );
+    CYG_UNUSED_PARAM(wxCheckListBox *, listBox);
 }
 
 void ecRunTestsExecutablesDialog::OnCheckAll(wxCommandEvent& event)
@@ -1129,6 +1130,8 @@ void ecRunTestsSummaryDialog::AddResult 
         m_List.SetItemText(nItem,1+i,arstr[i]);
         arstr[i].ReleaseBuffer();
     }
+#else
+    CYG_UNUSED_PARAM(int, nLength);
 #endif
 }
 
diff --git a/host/tools/configtool/standalone/wxwin/settingsdlg.cpp b/host/tools/configtool/standalone/wxwin/settingsdlg.cpp
--- a/host/tools/configtool/standalone/wxwin/settingsdlg.cpp
+++ b/host/tools/configtool/standalone/wxwin/settingsdlg.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2005, 2008, 2009 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2005, 2008, 2009, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -443,7 +443,11 @@ void ecDisplayOptionsDialog::OnChangeFon
         wxFontData data;
         data.SetInitialFont(wxGetApp().GetSettings().GetWindowSettings().GetFont(str));
 
-        wxFontDialog dlg(this, & data);
+#if wxCHECK_VERSION(2, 8, 0)
+        wxFontDialog dlg(this, data);
+#else
+        wxFontDialog dlg(this, & data);
+#endif
         if (dlg.ShowModal() == wxID_OK)
         {
             wxGetApp().GetSettings().GetWindowSettings().SetFont(str, dlg.GetFontData().GetChosenFont()) ;
diff --git a/host/tools/configtool/standalone/wxwin/templatesdlg.cpp b/host/tools/configtool/standalone/wxwin/templatesdlg.cpp
--- a/host/tools/configtool/standalone/wxwin/templatesdlg.cpp
+++ b/host/tools/configtool/standalone/wxwin/templatesdlg.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc.            
+// Copyright (C) 1998, 1999, 2000, 2014 Free Software Foundation, Inc.            
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -350,8 +350,13 @@ void ecTemplatesDialog::ShowDetails(bool
     }
     else
     {
-        GetSizer()->Remove(win1);
-        GetSizer()->Remove(win2);
+#if wxCHECK_VERSION(2, 8, 0)
+        GetSizer()->Detach(win1);
+        GetSizer()->Detach(win2);
+#else
+        GetSizer()->Remove(win1);
+        GetSizer()->Remove(win2);
+#endif
         button->SetLabel("&Details >>");
     }
     win1->Show(show);
@@ -380,6 +385,7 @@ void ecTemplatesDialog::OnSelHardwareTem
     UpdateDetails (); // display new hardware packages in details box
 
     TransferDataToWindow (); // display new target description
+    CYG_UNUSED_PARAM(wxChoice *, cdlPackageCtrl);
 }
 
 void ecTemplatesDialog::OnSelPackageTemplates(wxCommandEvent& event)
@@ -395,6 +401,7 @@ void ecTemplatesDialog::OnSelPackageTemp
 	m_template = template_i->c_str();
 	
 	UpdateVersionList (wxT("")); // repopulate template versions combo box and select most recent version
+    CYG_UNUSED_PARAM(wxComboBox *, cdlHardwareCtrl);
 }
 
 void ecTemplatesDialog::OnSelPackageVersion(wxCommandEvent& event)
@@ -447,6 +454,8 @@ void ecTemplatesDialog::UpdateVersionLis
 	
 	// enable the version combo box only if there are multiple versions
 	cdlVersionCtrl->Enable (versions.size () > 1);
+    CYG_UNUSED_PARAM(wxComboBox *, cdlHardwareCtrl);
+    CYG_UNUSED_PARAM(wxChoice *, cdlPackageCtrl);
 }
 
 void ecTemplatesDialog::UpdateDetails()
diff --git a/host/tools/ecostest/ChangeLog b/host/tools/ecostest/ChangeLog
--- a/host/tools/ecostest/ChangeLog
+++ b/host/tools/ecostest/ChangeLog
@@ -1,3 +1,15 @@
+2014-03-13  Andy Jackson  <andy@xylanta.com>
+
+	* common/eCosTest.cpp: Silence "set but unused" variable warnings
+	with recent GCC. [ Bugzilla 1001949 ]
+	* common/eCosTest.cpp: Silence unused variable warnings	with recent
+	GCC. [ Bugzilla 1001950 ]
+
+2012-04-23  John Dallaway  <john@dallaway.org.uk>
+
+	* common/eCosTestPlatform.cpp: Include limits.h for PATH_MAX
+	definition.
+
 2009-09-25  John Dallaway  <john@dallaway.org.uk>
 
 	* common/eCosTestPlatform.cpp (CeCosTestPlatform::LoadFromDir): Use
diff --git a/host/tools/ecostest/common/eCosTest.cpp b/host/tools/ecostest/common/eCosTest.cpp
--- a/host/tools/ecostest/common/eCosTest.cpp
+++ b/host/tools/ecostest/common/eCosTest.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2009 Free Software Foundation, Inc.            
+// Copyright (C) 1998, 1999, 2000, 2009, 2014 Free Software Foundation, Inc.            
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -869,6 +869,7 @@ void CeCosTest::ConnectSocketToSerialThr
   }
   TRACE(_T("ConnectSocketToSerial : done\n"));
   CeCosSocket::CloseSocket(m_nAuxListenSock);
+  CYG_UNUSED_PARAM(bool, rc);
 }
 
 static bool CALLBACK DerefBool(void *pParam)
@@ -935,6 +936,7 @@ void CeCosTest::AcceptThreadFunc()
       SetExecutable(m_strExecutable); // to set stripped length and title
       RunLocal();
       _tunlink(m_strExecutable);
+      CYG_UNUSED_PARAM(bool, bCanRun);
     }
     sendResult();
     m_pSock->recvInteger(n); // receive an ack
@@ -1248,7 +1250,7 @@ BOOL WINAPI HandlerRoutine(
                            DWORD dwCtrlType   //  control signal type
                            )
 {
-  dwCtrlType; // eliminate compiler warning
+  CYG_UNUSED_PARAM(DWORD, dwCtrlType);
   return TRUE;
 }
 #endif
diff --git a/host/tools/ecostest/common/eCosTestPlatform.cpp b/host/tools/ecostest/common/eCosTestPlatform.cpp
--- a/host/tools/ecostest/common/eCosTestPlatform.cpp
+++ b/host/tools/ecostest/common/eCosTestPlatform.cpp
@@ -1,7 +1,7 @@
 // ####ECOSHOSTGPLCOPYRIGHTBEGIN####                                        
 // -------------------------------------------                              
 // This file is part of the eCos host tools.                                
-// Copyright (C) 1998, 1999, 2000, 2003, 2009 Free Software Foundation, Inc.      
+// Copyright (C) 1998, 1999, 2000, 2003, 2009, 2012 Free Software Foundation, Inc.      
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
@@ -26,6 +26,7 @@
 //        platform information implementation
 //
 //=================================================================
+#include <limits.h>
 #include "eCosTestPlatform.h"
 #include "eCosTestUtils.h"
 #include "eCosTrace.h"
diff --git a/packages/ChangeLog b/packages/ChangeLog
--- a/packages/ChangeLog
+++ b/packages/ChangeLog
@@ -1,3 +1,127 @@
+2013-09-11  Uwe Kindler  <uwe_kindler@web.de>
+
+	* ecos.db: Add CAN driver entry for olcpl2294 target (Olimex
+	LPC-L2294-1M development board).
+
+2013-07-01  Mike Jones <mjones@proclivis.com.>
+
+	* ecos.db: Add TWR-K60F120M platform HAL package and target
+	records.
+
+2013-06-12  John Dallaway  <john@dallaway.org.uk>
+
+	* ecos.db: Add STM32F4-Discovery platform HAL package and target
+	records.
+
+2013-05-2013  Uwe Kindler  <uwe_kindler@web.de>
+
+	* ecos.db: Add CAN driver entry for olcpe2294 target (Olimex
+	LPC-E2294 development board).
+
+2013-04-26  Tomas Frydrych <tomas@sleepfive.com>
+2013-04-26  Mike Jones <mike@proclivis.com>
+
+	* ecos.db: Add Freescale I2C driver and I2C driver entries for
+	Kinetis targets.
+
+2013-04-14  Jerzy Dyrda  <jerzdy@gmail.com>
+
+	* ecos.db: Add STM32 Erhernet driver and Ethernet  driver entries
+	to STM3220G-eval and STM3240G-eval boards.
+
+2012-11-04  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* ecos.db: Add Kinetis internal flash driver contributed by
+	Nicolas Aujoux. Added flash driver entries
+	to: TWR-K60N512, TWR-K40X256, TWR-K70F120M and Kwikstik.
+
+2012-02-22  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* ecos.db: Add TWR-K70F120M bsp and target.
+
+2012-05-04  Ilija Stanislevik  <ilijas@siva.mk>
+
+	* ecos.db: Add Microchip ENC424J600 / ENC624J600 ethernet controller
+	driver package.
+
+2012-03-30  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* NEWS, ecos.db: Add  STM3220G-eval and STM3240G-evalW board port and
+	targets. Contributed by eCosCentric Limited.
+
+2012-03-30  John Dallaway  <john@dallaway.org.uk>
+
+	* NEWS, ecos.db: Add Freescale KwikStik HAL package and target.
+	Patch from Tomas Frydrych.
+
+2012-03-12 Christophe Coutand  <ecos@hotmail.co.uk>
+
+    	* ecos.db: Add Actel SmartFusion A2Fvvv variant HAL, board support
+	package for Actel A2F200 inluding Actel serial, ethernet, spi and
+	i2c drivers as well as spi flash driver.
+
+2012-02-22  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* ecos.db: Add TWR-K60N512-FXM, Freescale DSPI driver,
+	Freescale EDMA library, Micron CellularRAM support.
+
+2011-10-30  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* NEWS, ecos.db: Add Freescale Kinetis variant HAL, board support
+	packages for TWR-K60N512 and TWR-K40X256 including Freescale serial
+	and ethernet drivers.
+
+2011-05-25  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* NEWS, ecos.db: Add SPI flash driver for SST25xx devices.
+
+2011-05-25  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* NEWS, ecos.db: Add SPI flash driver for Atmel AT25DFxxx.
+
+2011-03-13  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* NEWS, ecos.db: Add LPC17XX variant HAL, support for
+	NXP Cortex M3 LPC17XX CPUs. BSP for Olimex LPC-1766-STK
+	board including ethernet, serial and wallclock drivers.
+
+2011-03-13  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* ecos.db: Ethernet, serial, and wallclock drivers for LPC17XX.
+	(CYGPKG_DEVICES_WALLCLOCK_ARM_LPC2XXX): Fixed alias/description;
+	(CYGPKG_DEVS_ETH_ARM_LPC2XXX): Ditto.
+	(CYGPKG_IO_SERIAL_ARM_LPC24XX): Ditto.
+
+2011-02-22  John Dallaway  <john@dallaway.org.uk>
+
+	* ecos.db: Add hardware package CYGPKG_DEVS_ADC_ARM_AT91 to
+	applicable target records: at91sam7sek, at91sam7xek, sam7ex256,
+	eb55, phycore
+
+2011-02-18  John Dallaway  <john@dallaway.org.uk>
+
+	* ecos.db: Remove non-hardware package CYGPKG_IO_ADC from the
+	ek-lm3s811 target definition and eliminate leading space in alias
+	string for correct sorting of targets by name.
+
+2011-02-09  Christophe Coutand  <ccoutand@stmi.com>
+
+	* NEWS, ecos.db: Add Stellaris Cortex M3 variant HAL, support for
+	Stellaris Cortex M3 800 series CPUs. BSP for Stellaris EK-LM3S811
+	board including ADC and I2C drivers.
+
+2010-11-12  John Dallaway  <john@dallaway.org.uk>
+
+	* ecos.db: Add USB mass storage function driver package.
+
+2010-10-27  John Dallaway  <john@dallaway.org.uk>
+
+	* ecos.db: Add STM32 USB slave driver package.
+
+2010-05-30  Christophe Coutand  <ccoutand@stmi.com>
+
+	* ecos.db: Add AT91 ADC driver.
+
 2009-11-13  John Dallaway  <john@dallaway.org.uk>
 
 	* ecosadmin.tcl: Keep target records containing removed packages
@@ -2776,7 +2900,7 @@ 1998-07-23  Bart Veer  <bartv@cygnus.co.
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2009 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2009, 2010, 2011 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/NEWS b/packages/NEWS
--- a/packages/NEWS
+++ b/packages/NEWS
@@ -1,3 +1,39 @@
+* PowerPC call-graph profiling support by John Dallaway.
+* ARM call-graph profiling support by John Dallaway.
+* Cortex-M call-graph profiling support by John Dallaway.
+* Complex number math library port from newlib by Ilija Kocho.
+* Single-precision floating point math library port from newlib by
+  Ilija Kocho and Visar Zejnullahu.
+* Freescale Kinetis TWR-K60F120M platform HAL by Mike Jones.
+* STMicroelectronics STM32F4-Discovery platform HAL by John Dallaway.
+* Freescale I2C driver by Tomas Frydrych.
+* STMicroelectronics STM32 ethernet driver by Jerzy Dyrda.
+* Freescale Kinetis TWR-K70F120M port by Ilija Kocho.
+* Microchip ENC424J600 ethernet driver by Ilija Stanislevik.
+* Cortex-M STM32 F2 processor support with board support for STM3220G-EVAL
+  and STM3240G-EVAL, along with many STM32 improvements. Contributed
+  by eCosCentric Limited.
+* Freescale KwikStik platform HAL by Tomas Frydrych.
+* Actel SmartFusion variant HAL and BSP by Christophe Coutand.
+* Freescale Kinetis variant HAL and BSP for TWR-K60N512 and TWR-K40X256
+  including Freescale UART and Ethernet drivers by Ilija Kocho.
+* SPI flash driver for Silicon Storage Technology (SST25xx devices)
+  by Christophe Coutand.
+* SPI flash driver for Atmel AT25DFxxx devices by Christophe Coutand.
+* LPC17XX variant HAL and BSP for Olimex LPC-1766-STK board including
+  ethernet, serial and wallclock drivers by Ilija Kocho.
+* LM3S variant HAL, generic support for the LM3S800 CPUs, and BSP for
+  Stellaris EK-LM3S811 board including ADC and I2C drivers by Christophe
+  Coutand
+* USB mass storage function driver by Christophe Coutand
+* AT91 USB slave driver halting endpoint support by Christophe Coutand
+* USB slave device driver for STM32 by Chris Holgate
+* Support for dynamic data endpoint configuration in USB serial function
+  device package by John Dallaway
+* Support for dynamic data endpoint configuration in USB slave API by
+  Chris Holgate
+* Update to uSTL 1.4 by Simon Kallweit
+* ADC device driver for AT91 by Christophe Coutand 
 * Major update of lwIP stack to v1.3.2 by Simon Kallweit
 * Port of uSTL 1.3 by Uwe Kindler
 * Port of PDCurses 3.4 by Sergei Gavrikov
diff --git a/packages/compat/linux/current/ChangeLog b/packages/compat/linux/current/ChangeLog
--- a/packages/compat/linux/current/ChangeLog
+++ b/packages/compat/linux/current/ChangeLog
@@ -1,3 +1,9 @@
+2012-05-27  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* include/linux/kernel.h (jiffies): Use cyg_current_time(), not
+	a constant. JFFS2 at least uses it to occasionally vary behaviour.
+	Fixes bug #1001591.
+
 2005-09-21  Steven_cheng <05071@alphanetworks.com>
 
 	* include/linux/types.h: Added unsigned types.
diff --git a/packages/compat/linux/current/include/linux/kernel.h b/packages/compat/linux/current/include/linux/kernel.h
--- a/packages/compat/linux/current/include/linux/kernel.h
+++ b/packages/compat/linux/current/include/linux/kernel.h
@@ -1,8 +1,10 @@
 #ifndef __LINUX_KERNEL_H__
 #define __LINUX_KERNEL_H__
-#include <cyg/infra/diag.h>
+#include <cyg/infra/diag.h>       // For diag_printf
+#include <cyg/fileio/fileio.h>    // For cyg_timestamp
+#include <cyg/kernel/kapi.h>      // For cyg_current_time
 
-#define jiffies 100
+#define jiffies ((unsigned long)cyg_current_time())
 
 #define ERR_PTR(err) ((void*)(err))
 #define PTR_ERR(err) ((unsigned long)(err))
diff --git a/packages/compat/posix/current/ChangeLog b/packages/compat/posix/current/ChangeLog
--- a/packages/compat/posix/current/ChangeLog
+++ b/packages/compat/posix/current/ChangeLog
@@ -1,3 +1,19 @@
+2013-02-03  John Dallaway  <john@dallaway.org.uk>
+
+	* src/pthread.cxx (pthread_create): Include terminating NUL char
+	when initializing thread name from template. [ Bugzilla 1001743 ]
+
+2012-03-08  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* src/mqueue.cxx: Fix compiler warnings about variables that are set
+	but not used.
+	* tests/signal2.c: Ditto.
+
+2010-02-08  Jay Foster  <jay@systech.com>
+
+	* src/signal.cxx (pthread_kill): Corrected return value for
+	pthread_kill() to match POSIX standard.
+
 2009-03-25  John Dallaway  <john@dallaway.org.uk>
 
 	* src/signal.cxx (pause): Revert change of 2006-07-18 pending
@@ -1111,7 +1127,7 @@ 2000-03-24  Nick Garnett  <nickg@cygnus.
 ## ####GPLCOPYRIGHTBEGIN####                                                
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2009 Free Software Foundation, Inc.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2009, 2013 Free Software Foundation, Inc.
 ##
 ## This program is free software; you can redistribute it and/or modify     
 ## it under the terms of the GNU General Public License as published by     
diff --git a/packages/compat/posix/current/src/mqueue.cxx b/packages/compat/posix/current/src/mqueue.cxx
--- a/packages/compat/posix/current/src/mqueue.cxx
+++ b/packages/compat/posix/current/src/mqueue.cxx
@@ -227,7 +227,7 @@ mq_open( const char *name, int oflag, ..
     mqd_t retval;
     cyg_ucount32 i;
     struct mqtabent *qtabent=NULL;
-    int interr;
+    int interr CYGBLD_ATTRIB_UNUSED;
 
     interr = pthread_mutex_lock( &mqtab_mut );
     // should never fail
@@ -256,7 +256,7 @@ mq_open( const char *name, int oflag, ..
 
     // so if we didn't find something, we must be being asked to create it
     if (NULL == qtabent) {
-        mode_t mode; // FIXME: mode ignored for now
+        mode_t mode CYGBLD_ATTRIB_UNUSED; // FIXME: mode ignored for now
         const struct mq_attr *attr;
         const struct mq_attr default_attr = { 0, MQ_OPEN_MAX, 128 };
         va_list args;
@@ -426,7 +426,7 @@ mq_close( mqd_t mqdes )
     }
 #endif
     
-    int interr;
+    int interr CYGBLD_ATTRIB_UNUSED;
 
     interr = pthread_mutex_lock( &mqtab_mut );
     // should never fail
@@ -493,7 +493,8 @@ mq_unlink( const char *name )
     CYG_REPORT_FUNCTYPE( "returning %d" );
     CYG_REPORT_FUNCARG1( "name=%s", name );
 
-    int retval, interr;
+    int retval;
+    int interr CYGBLD_ATTRIB_UNUSED;
     cyg_ucount32 i;
     struct mqtabent *qtabent=NULL;
 
diff --git a/packages/compat/posix/current/src/pthread.cxx b/packages/compat/posix/current/src/pthread.cxx
--- a/packages/compat/posix/current/src/pthread.cxx
+++ b/packages/compat/posix/current/src/pthread.cxx
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2013 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -596,7 +596,7 @@ externC int pthread_create ( pthread_t *
     static char *name_template = "pthread.00000000";
     pthread_t id = nthread->id;
     
-    for( int i = 0; name_template[i]; i++ ) name[i] = name_template[i];
+    for( int i = 0; ( name[i] = name_template[i] ); i++ );
 
     // dump the id, in hex into the name.
     for( int i = 15; i >= 8; i-- )
diff --git a/packages/compat/posix/current/src/signal.cxx b/packages/compat/posix/current/src/signal.cxx
--- a/packages/compat/posix/current/src/signal.cxx
+++ b/packages/compat/posix/current/src/signal.cxx
@@ -554,14 +554,14 @@ externC int pthread_kill (pthread_t thre
     SIGNAL_ENTRY();
 
     if( !SIGNAL_VALID(sig) )
-        SIGNAL_RETURN(EINVAL);
+        SIGNAL_RETURN_VALUE(EINVAL);
     
     struct sigevent sev;
 
     pthread_info *thread = pthread_info_id(threadid);
 
     if( thread == NULL )
-        SIGNAL_RETURN(ESRCH);
+        SIGNAL_RETURN_VALUE(ESRCH);
     
     sev.sigev_notify           = SIGEV_SIGNAL;
     sev.sigev_signo            = sig;
@@ -571,7 +571,7 @@ externC int pthread_kill (pthread_t thre
 
     cyg_deliver_signals();
     
-    SIGNAL_RETURN(0);
+    SIGNAL_RETURN_VALUE(0);
 }
 
 //==========================================================================
diff --git a/packages/compat/posix/current/tests/signal2.c b/packages/compat/posix/current/tests/signal2.c
--- a/packages/compat/posix/current/tests/signal2.c
+++ b/packages/compat/posix/current/tests/signal2.c
@@ -125,7 +125,7 @@ cause_illegal_access(void)
             );
     
 #else    
-    volatile int x;
+    volatile int x CYGBLD_ATTRIB_UNUSED;
     volatile CYG_ADDRESS p=(CYG_ADDRESS) &jbuf;
 
     do
diff --git a/packages/compat/uitron/current/ChangeLog b/packages/compat/uitron/current/ChangeLog
--- a/packages/compat/uitron/current/ChangeLog
+++ b/packages/compat/uitron/current/ChangeLog
@@ -1,3 +1,8 @@
+2013-05-09  John Dallaway  <john@dallaway.org.uk>
+
+	* doc/uitron.sgml: Update documentation link to uITRON specification.
+	[ Bug 1001840 ]
+
 2009-03-02  Nick Garnett  <nickg@ecoscentric.com>
 
 	* tests/test2.c: 
@@ -865,7 +870,7 @@ Fri Jul 24 13:02:46 1998  Hugo Tyson  <h
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006, 2013 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/compat/uitron/current/doc/uitron.sgml b/packages/compat/uitron/current/doc/uitron.sgml
--- a/packages/compat/uitron/current/doc/uitron.sgml
+++ b/packages/compat/uitron/current/doc/uitron.sgml
@@ -9,7 +9,7 @@
 <!-- =============================================================== -->
 <!-- ####ECOSDOCCOPYRIGHTBEGIN####                                       -->
 <!-- ===============================================================     -->
-<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. -->
+<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2013 Free Software Foundation, Inc. -->
 <!-- This material may be distributed only subject to the terms          -->
 <!-- and conditions set forth in the Open Publication License, v1.0      -->
 <!-- or later (the latest version is presently available at              -->
@@ -52,11 +52,9 @@ porting application software to new proc
 	  System for Embedded Systems</CITETITLE>. 
 	The book can be purchased from the IEEE Press, and
 	an ASCII version of the standard can be found online at
-<ulink url="http://www.itron.gr.jp/">http://www.itron.gr.jp/</ulink>.
-The old address 
-<ulink url="http://tron.um.u-tokyo.ac.jp/TRON/ITRON/">
-http://tron.um.u-tokyo.ac.jp/TRON/ITRON/</ulink>
-still exists as a mirror site. </PARA>
+<ulink url="http://www.t-engine.org/specifications">
+http://www.t-engine.org/specifications</ulink>.
+</PARA>
 </SECT1>
 <SECT1 id="compat-uitron-over-ecos">
 <TITLE><!-- <index></index> -->&micro;ITRON and <EMPHASIS>eCos</EMPHASIS></TITLE>
diff --git a/packages/devs/adc/arm/at91/current/ChangeLog b/packages/devs/adc/arm/at91/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/adc/arm/at91/current/ChangeLog
@@ -0,0 +1,31 @@
+2010-05-18  ccoutand  <ccoutand@stmi.com>
+
+        * AT91 ADC driver package created
+        * cdl/adc_at91.cdl
+        * src/adc_at91.c
+        * include/adc_at91.inl
+        * tests/at91_adc_test.c
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/adc/arm/at91/current/cdl/adc_at91.cdl b/packages/devs/adc/arm/at91/current/cdl/adc_at91.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/adc/arm/at91/current/cdl/adc_at91.cdl
@@ -0,0 +1,355 @@
+# ====================================================================
+#
+#      adc_at91.cdl
+#
+#      eCos AT91 ADC configuration data
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2008 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      ccoutand@stmi.com
+# Contributors:   
+# Date:           2010-02-12
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+
+cdl_package CYGPKG_DEVS_ADC_ARM_AT91 {
+    display     "ADC hardware device driver for AT91 family of ARM controllers"
+    
+    parent      CYGPKG_IO_ADC_DEVICES
+    active_if   CYGPKG_IO_ADC_DEVICES
+    active_if   CYGPKG_HAL_ARM_AT91
+    description " 
+           This package provides a generic ADC device driver for the on-chip
+           ADC peripherals in AT91 processors."
+           
+    include_dir cyg/io
+    compile     -library=libextras.a adc_at91.c
+    
+    define_proc {
+      puts $::cdl_system_header "#define CYGDAT_DEVS_ADC_ARM_AT91_INL <cyg/io/adc_at91.inl>"
+    }
+    
+    # 
+    # Primary ADC ( ADC0 )
+    #
+    cdl_component CYGPKG_DEVS_ADC_ARM_AT91_ADC0 {
+       display       "Atmel AT91 ADC port 0 driver"
+       flavor        bool
+       default_value 1
+       description "
+           This option includes the device driver for the on-chip ADC 0 of the
+           AT91 processors"
+    
+    
+       cdl_interface CYGINT_DEVS_ADC_ARM_AT91_ADC0_CHANNELS {
+          display "Number of ADC0 channels"
+       }  
+   
+       cdl_option CYGNUM_DEVS_ADC_ARM_AT91_ADC0_SELECT_TIMER {
+          display       "Interrupt priority"
+          flavor        data
+          legal_values {0 1 2}
+          default_value 1
+          description   "
+              This option selects the timer channel to be used for 
+              generating the sampling interval. Timer channel 0 can 
+              be assigned as Real Time Kernel clock so timer channel 
+              1 is set to be the default value."
+       }
+
+       cdl_option CYGNUM_DEVS_ADC_ARM_AT91_ADC0_PRESCAL {
+           display       "ADC clock setting"
+           flavor        data
+           legal_values  0 to 255
+           default_value 128
+           description   "
+               This option sets the AT91 ADC PRESCAL value. 
+               ADCClock = MCK / ((PRESCAL + 1) * 2)"
+       }
+
+       cdl_option CYGNUM_DEVS_ADC_ARM_AT91_ADC0_STARTUP_TIME {
+           display       "ADC start-up time"
+           flavor        data
+           legal_values  0 to 255
+           default_value 128
+           description   "
+               This option sets the AT91 ADC start-up time value. 
+               ADC start-up time = (STARTUP+1) * 8 / ADCClock"
+       }
+
+       cdl_option CYGNUM_DEVS_ADC_ARM_AT91_ADC0_SHTIM {
+           display       "ADC start up time"
+           flavor        data
+           legal_values  0 to 15
+           default_value 7
+           description   "
+               This option sets the AT91 ADC Sample and Hold Time. 
+               Sample and Hold Time = SHTIM / ADCClock"
+       }
+
+       cdl_option CYGNUM_DEVS_ADC_ARM_AT91_ADC0_INTPRIO {
+           display       "Interrupt priority"
+           flavor        data
+           legal_values  0 to 15
+           default_value 15
+           description   "
+               This option selects the interrupt priority for the ADC
+               interrupts.  Timer x is used for generating the sample
+               clock. So this option configures the interrupt priority
+               for timer x. There are 16 priority levels corresponding to
+               the values 0 through 15 decimal, of which 15 is the lowest
+               priority. The reset value of these registers defaults all
+               interrupts to the lowest priority, allowing a single write
+               to elevate the priority of an individual interrupt."
+       }
+
+       cdl_option CYGNUM_DEVS_ADC_ARM_AT91_ADC0_DEFAULT_RATE {
+           display "Default sample rate"
+           flavor   data
+           legal_values 1 to 10000
+           default_value 100
+           description "
+               The driver will be initialized with the default sample rate.
+               If you raise the default sample rate you might need to increase
+               the buffer size for each channel."
+       }
+                
+       # Support up to 8 ADC channels
+       for { set ::channel 0 } { $::channel < 8 } { incr ::channel } {  
+    
+           cdl_component CYGPKG_DEVS_ADC_ARM_AT91_ADC0_CHANNEL[set ::channel] {
+               display        "Access ADC channel [set ::channel]"
+               flavor          bool
+               default_value   [set ::channel] == 0
+               implements      CYGINT_DEVS_ADC_ARM_AT91_ADC0_CHANNELS
+               description "
+                   If the application needs to access the on-chip ADC
+                   channel [set ::channel] via an eCos ADC driver then
+                   this option should be enabled."
+     
+               cdl_option CYGDAT_DEVS_ADC_ARM_AT91_ADC0_CHANNEL[set ::channel]_NAME {
+                   display "Device name"
+                   flavor      data
+                   default_value   [format {"\"/dev/adc0%d\""} $::channel]
+                   description "
+                       This option controls the name that an eCos application
+                       should use to access this device via cyg_io_lookup(),
+                       open(), or similar calls."
+               }
+        
+               cdl_option CYGDAT_DEVS_ADC_ARM_AT91_ADC0_CHANNEL[set ::channel]_BUFSIZE {
+                   display "Size of data buffer"
+                   flavor  data
+                   legal_values  0x01 to 0x2000000
+                   default_value 512
+                   description "
+                       This option controls the number of samples the
+                       buffer can store. The required RAM depends on the
+                       sample size and on the number of samples. If the
+                       sample size is <= 8 bit the the required RAM =
+                       size of data buffer. If the sample size is 9 or 10
+                       bit then required RAM = size of data buffer * 2."
+               } 
+           } 
+        }
+     }
+     
+    # 
+    # ADC1
+    #
+    cdl_component CYGPKG_DEVS_ADC_ARM_AT91_ADC1 {
+       display       "Atmel AT91 ADC port 1 driver"
+       flavor        bool
+       default_value 0
+       
+       requires      { CYGHWR_HAL_ARM_AT91 == "M55800A" }
+       
+       description "
+           This option includes the device driver for the on-chip ADC 1 of the
+           AT91 processors"
+    
+    
+       cdl_interface CYGINT_DEVS_ADC_ARM_AT91_ADC1_CHANNELS {
+          display "Number of ADC1 channels"
+       }  
+   
+       cdl_option CYGNUM_DEVS_ADC_ARM_AT91_ADC1_SELECT_TIMER {
+          display       "Interrupt priority"
+          flavor        data
+          legal_values {0 1 2}
+          default_value 2
+          description   "
+              This option selects the timer channel to be used for 
+              generating the sampling interval. Timer channel 0 can 
+              be assigned as Real Time Kernel clock so timer channel 
+              1 is set to be the default value."
+       }
+
+       cdl_option CYGNUM_DEVS_ADC_ARM_AT91_ADC1_PRESCAL {
+           display       "ADC clock setting"
+           flavor        data
+           legal_values  0 to 255
+           default_value 128
+           description   "
+               This option sets the AT91 ADC PRESCAL value. 
+               ADCClock = MCK / ((PRESCAL + 1) * 2)"
+       }
+
+       cdl_option CYGNUM_DEVS_ADC_ARM_AT91_ADC1_STARTUP_TIME {
+           display       "ADC start-up time"
+           flavor        data
+           legal_values  0 to 255
+           default_value 128
+           description   "
+               This option sets the AT91 ADC start-up time value. 
+               ADC start-up time = (STARTUP+1) * 8 / ADCClock"
+       }
+
+       cdl_option CYGNUM_DEVS_ADC_ARM_AT91_ADC1_SHTIM {
+           display       "ADC start up time"
+           flavor        data
+           legal_values  0 to 15
+           default_value 7
+           description   "
+               This option sets the AT91 ADC Sample and Hold Time. 
+               Sample and Hold Time = SHTIM / ADCClock"
+       }
+
+       cdl_option CYGNUM_DEVS_ADC_ARM_AT91_ADC1_INTPRIO {
+           display       "Interrupt priority"
+           flavor        data
+           legal_values  0 to 15
+           default_value 15
+           description   "
+               This option selects the interrupt priority for the ADC
+               interrupts.  Timer x is used for generating the sample
+               clock. So this option configures the interrupt priority
+               for timer x. There are 16 priority levels corresponding to
+               the values 0 through 15 decimal, of which 15 is the lowest
+               priority. The reset value of these registers defaults all
+               interrupts to the lowest priority, allowing a single write
+               to elevate the priority of an individual interrupt."
+       }
+
+       cdl_option CYGNUM_DEVS_ADC_ARM_AT91_ADC1_DEFAULT_RATE {
+           display "Default sample rate"
+           flavor   data
+           legal_values 1 to 10000
+           default_value 100
+           description "
+               The driver will be initialized with the default sample rate.
+               If you raise the default sample rate you might need to increase
+               the buffer size for each channel."
+       }
+                
+       # Support up to 8 ADC channels
+       for { set ::channel 0 } { $::channel < 8 } { incr ::channel } {  
+    
+           cdl_component CYGPKG_DEVS_ADC_ARM_AT91_ADC1_CHANNEL[set ::channel] {
+               display        "Access ADC channel [set ::channel]"
+               flavor          bool
+               default_value   [set ::channel] == 0
+               implements      CYGINT_DEVS_ADC_ARM_AT91_ADC1_CHANNELS
+               description "
+                   If the application needs to access the on-chip ADC
+                   channel [set ::channel] via an eCos ADC driver then
+                   this option should be enabled."
+     
+               cdl_option CYGDAT_DEVS_ADC_ARM_AT91_ADC1_CHANNEL[set ::channel]_NAME {
+                   display "Device name"
+                   flavor      data
+                   default_value   [format {"\"/dev/adc1%d\""} $::channel]
+                   description "
+                       This option controls the name that an eCos application
+                       should use to access this device via cyg_io_lookup(),
+                       open(), or similar calls."
+               }
+        
+               cdl_option CYGDAT_DEVS_ADC_ARM_AT91_ADC1_CHANNEL[set ::channel]_BUFSIZE {
+                   display "Size of data buffer"
+                   flavor  data
+                   legal_values  0x01 to 0x2000000
+                   default_value 512
+                   description "
+                       This option controls the number of samples the
+                       buffer can store. The required RAM depends on the
+                       sample size and on the number of samples. If the
+                       sample size is <= 8 bit the the required RAM =
+                       size of data buffer. If the sample size is 9 or 10
+                       bit then required RAM = size of data buffer * 2."
+               } 
+           } 
+        }
+     }     
+     
+     cdl_option CYGPKG_DEVS_ADC_ARM_AT91_DEBUG_LEVEL {
+         display "Driver debug output level"
+         flavor  data
+         legal_values {0 1}
+         default_value 0
+         description   "
+              This option specifies the level of debug data output by
+              the AT91 ADC device driver. A value of 0 signifies
+              no debug data output; 1 signifies normal debug data
+              output. If an overrun occurred then this can only be
+              detected by debug output messages."         
+     }     
+
+     cdl_component CYGSEM_DEVS_ADC_ARM_AT91_SAMPLE_SIZE_LIMIT {
+         display       "Sample size limit"
+         flavor          bool
+         calculated    1
+         requires      { ( CYGNUM_IO_ADC_SAMPLE_SIZE == 8 )
+                            || ( CYGNUM_IO_ADC_SAMPLE_SIZE == 10 ) }
+         description   "
+             This component forces a limit (or rounds) the sample
+             size for AT91 ADC channels which in the most are 10-bit."
+     }
+
+    cdl_option CYGPKG_DEVS_ADC_ARM_AT91_TESTS {
+        display "Tests for AT91 ADC driver"
+        flavor  data
+        no_define
+        calculated { "tests/at91_adc_test" }
+        description   "
+            This option specifies the set of tests for the AT91
+            ADC device driver."
+    }
+
+}
diff --git a/packages/devs/adc/arm/at91/current/include/adc_at91.inl b/packages/devs/adc/arm/at91/current/include/adc_at91.inl
new file mode 100644
--- /dev/null
+++ b/packages/devs/adc/arm/at91/current/include/adc_at91.inl
@@ -0,0 +1,200 @@
+//==========================================================================
+//
+//      adc_at91.inl
+//
+//      ADC driver for AT91 on chip ADC
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Atmel AT91 on-chip ADC device driver, ccoutand
+//              
+// Contributors:
+// Date:         2010-05-27
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#ifndef CYGONCE_DEVS_ADC_ARM_AT91_INL
+#define CYGONCE_DEVS_ADC_ARM_AT91_INL
+
+// Some AT91 HAL are defining the timer 0 vector as TC0 and other as TIMER0
+#ifndef CYGNUM_HAL_INTERRUPT_TC0
+#define CYGNUM_HAL_INTERRUPT_TC0 CYGNUM_HAL_INTERRUPT_TIMER0
+#endif
+
+// Declare ADC0
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC0
+
+static at91_adc_info at91_adc0_info =
+{
+    .adc_base         = AT91_ADC,
+    .timer_base       = AT91_TC,
+    .tc_base          = AT91_TC + (AT91_TC_TC_SIZE * CYGNUM_DEVS_ADC_ARM_AT91_ADC0_SELECT_TIMER),
+    .timer_vector     = CYGNUM_HAL_INTERRUPT_TC0 + CYGNUM_DEVS_ADC_ARM_AT91_ADC0_SELECT_TIMER,
+    .timer_intprio    = CYGNUM_DEVS_ADC_ARM_AT91_ADC0_INTPRIO,
+    .timer_id         = CYGNUM_DEVS_ADC_ARM_AT91_ADC0_SELECT_TIMER,
+    .int_handle       = 0,
+    .adc_prescal      = CYGNUM_DEVS_ADC_ARM_AT91_ADC0_PRESCAL,
+    .adc_startup_time = CYGNUM_DEVS_ADC_ARM_AT91_ADC0_STARTUP_TIME,
+    .adc_shtim        = CYGNUM_DEVS_ADC_ARM_AT91_ADC0_SHTIM,
+#if CYGNUM_IO_ADC_SAMPLE_SIZE > 8
+     .resolution      = AT91_ADC_MR_LOWREC_10BITS,
+#else
+     .resolution      = AT91_ADC_MR_LOWRES_8BITS,
+#endif
+    .chan_mask        = 0
+};
+
+CYG_ADC_DEVICE( at91_adc0_device,
+                &at91_adc_funs,
+                &at91_adc0_info,
+                CYGNUM_DEVS_ADC_ARM_AT91_ADC0_DEFAULT_RATE);
+
+#define AT91_ADC0_CHANNEL( __chan )                                        \
+CYG_ADC_CHANNEL( at91_adc0_channel##__chan,                                \
+                 __chan,                                                   \
+                 CYGDAT_DEVS_ADC_ARM_AT91_ADC0_CHANNEL##__chan##_BUFSIZE,  \
+                 &at91_adc0_device );                                       \
+                                                                           \
+DEVTAB_ENTRY( at91_adc0_channel##__chan##_device,                          \
+              CYGDAT_DEVS_ADC_ARM_AT91_ADC0_CHANNEL##__chan##_NAME,        \
+              0,                                                           \
+              &cyg_io_adc_devio,                                           \
+              at91_adc_init,                                               \
+              at91_adc_lookup,                                             \
+              &at91_adc0_channel##__chan );
+
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC0_CHANNEL0
+AT91_ADC0_CHANNEL(0);
+#endif
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC0_CHANNEL1
+AT91_ADC0_CHANNEL(1);
+#endif
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC0_CHANNEL2
+AT91_ADC0_CHANNEL(2);
+#endif
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC0_CHANNEL3
+AT91_ADC0_CHANNEL(3);
+#endif
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC0_CHANNEL4
+AT91_ADC0_CHANNEL(4);
+#endif
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC0_CHANNEL5
+AT91_ADC0_CHANNEL(5);
+#endif
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC0_CHANNEL6
+AT91_ADC0_CHANNEL(6);
+#endif
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC0_CHANNEL7
+AT91_ADC0_CHANNEL(7);
+#endif
+
+#endif // CYGPKG_DEVS_ADC_ARM_AT91_ADC0
+
+
+
+// Declare ADC1
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC1
+
+static at91_adc_info at91_adc1_info =
+{
+    .adc_base         = AT91_ADC1,
+    .timer_base       = AT91_TC,
+    .tc_base          = AT91_TC + (AT91_TC_TC_SIZE * CYGNUM_DEVS_ADC_ARM_AT91_ADC1_SELECT_TIMER),
+    .timer_vector     = CYGNUM_HAL_INTERRUPT_TC0 + CYGNUM_DEVS_ADC_ARM_AT91_ADC1_SELECT_TIMER,
+    .timer_intprio    = CYGNUM_DEVS_ADC_ARM_AT91_ADC1_INTPRIO,
+    .timer_id         = CYGNUM_DEVS_ADC_ARM_AT91_ADC1_SELECT_TIMER,
+    .int_handle       = 0,
+    .adc_prescal      = CYGNUM_DEVS_ADC_ARM_AT91_ADC1_PRESCAL,
+    .adc_startup_time = CYGNUM_DEVS_ADC_ARM_AT91_ADC1_STARTUP_TIME,
+    .adc_shtim        = CYGNUM_DEVS_ADC_ARM_AT91_ADC1_SHTIM,
+#if CYGNUM_IO_ADC_SAMPLE_SIZE > 8
+     .resolution      = AT91_ADC_MR_LOWREC_10BITS,
+#else
+     .resolution      = AT91_ADC_MR_LOWRES_8BITS,
+#endif
+    .chan_mask        = 0
+};
+CYG_ADC_DEVICE( at91_adc1_device,
+                &at91_adc_funs,
+                &at91_adc1_info,
+                CYGNUM_DEVS_ADC_ARM_AT91_ADC1_DEFAULT_RATE);
+
+#define AT91_ADC1_CHANNEL( __chan )                                        \
+CYG_ADC_CHANNEL( at91_adc1_channel##__chan,                                \
+                 __chan,                                                   \
+                 CYGDAT_DEVS_ADC_ARM_AT91_ADC1_CHANNEL##__chan##_BUFSIZE,  \
+                 &at91_adc1_device );                                       \
+                                                                           \
+DEVTAB_ENTRY( at91_adc1_channel##__chan##_device,                          \
+              CYGDAT_DEVS_ADC_ARM_AT91_ADC1_CHANNEL##__chan##_NAME,        \
+              0,                                                           \
+              &cyg_io_adc_devio,                                           \
+              at91_adc_init,                                               \
+              at91_adc_lookup,                                             \
+              &at91_adc1_channel##__chan );
+
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC1_CHANNEL0
+AT91_ADC1_CHANNEL(0);
+#endif
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC1_CHANNEL1
+AT91_ADC1_CHANNEL(1);
+#endif
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC1_CHANNEL2
+AT91_ADC1_CHANNEL(2);
+#endif
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC1_CHANNEL3
+AT91_ADC1_CHANNEL(3);
+#endif
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC1_CHANNEL4
+AT91_ADC1_CHANNEL(4);
+#endif
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC1_CHANNEL5
+AT91_ADC1_CHANNEL(5);
+#endif
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC1_CHANNEL6
+AT91_ADC1_CHANNEL(6);
+#endif
+#ifdef CYGPKG_DEVS_ADC_ARM_AT91_ADC1_CHANNEL7
+AT91_ADC1_CHANNEL(7);
+#endif
+
+#endif // CYGPKG_DEVS_ADC_ARM_AT91_ADC1
+
+#endif // CYGONCE_DEVS_ADC_ARM_AT91_INL
diff --git a/packages/devs/adc/arm/at91/current/src/adc_at91.c b/packages/devs/adc/arm/at91/current/src/adc_at91.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/adc/arm/at91/current/src/adc_at91.c
@@ -0,0 +1,457 @@
+//==========================================================================
+//
+//      adc_at91.c
+//
+//      ADC driver for AT91 on chip ADC
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Uwe Kindler <uwe_kindler@web.de>
+//              Updated for Atmel AT91 device, ccoutand <ccoutand@stmi.com>
+// Contributors:
+// Date:         2010-02-15
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+
+//==========================================================================
+//                                 INCLUDES
+//==========================================================================
+#include <pkgconf/system.h>
+#include <pkgconf/devs_adc_arm_at91.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/diag.h>
+#include <cyg/io/adc.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/drv_api.h>
+
+#if CYGPKG_DEVS_ADC_ARM_AT91_DEBUG_LEVEL > 0
+   #define at91_adc_printf(args...) diag_printf(args)
+#else
+   #define at91_adc_printf(args...)
+#endif
+
+#define AT91_ADC_CHER_CHx(_ch_)  (0x1 << _ch_)
+#define AT91_ADC_CHER_CDRx(_ch_) (_ch_ << 2)
+
+//==========================================================================
+//                                  DATA TYPES
+//==========================================================================
+typedef struct at91_adc_info
+{
+    cyg_uint32              adc_base;          // base address of ADC peripheral
+    cyg_uint8               adc_prescal;       // ADC prescal value
+    cyg_uint8               adc_startup_time;  // ADC Startup Time value
+    cyg_uint8               adc_shtim;         // ADC SHTIM value
+    cyg_uint8               timer_id;          // select timer
+    cyg_uint32              timer_base;        // base address of Timer peripheral
+    cyg_uint32              tc_base;           // base address of Timer channel
+    cyg_vector_t            timer_vector;      // interrupt vector number
+    int                     timer_intprio;     // interrupt priority of ADC interrupt
+    cyg_uint32              timer_cnt;         // Timer value
+    cyg_uint8               timer_clk;         // Timer clock setting
+    cyg_uint32              resolution;
+    cyg_handle_t            int_handle;        // For initializing the interrupt
+    cyg_interrupt           int_data;
+    struct cyg_adc_channel *channel[AT91_MAX_ADC_CHAN]; // stores references to channel objects
+    cyg_uint8               chan_mask;         // mask that indicates channels used
+                                               // by ADC driver
+} at91_adc_info;
+
+
+//==========================================================================
+//                               DECLARATIONS
+//==========================================================================
+static bool at91_adc_init(struct cyg_devtab_entry *tab);
+static Cyg_ErrNo at91_adc_lookup(struct cyg_devtab_entry **tab,
+                                    struct cyg_devtab_entry  *sub_tab,
+                                    const char               *name);
+static void at91_adc_enable( cyg_adc_channel *chan );
+static void at91_adc_disable( cyg_adc_channel *chan );
+static void at91_adc_set_rate( cyg_adc_channel *chan, cyg_uint32 rate );
+static cyg_uint32 at91_adc_isr(cyg_vector_t vector, cyg_addrword_t data);
+static void at91_adc_dsr(cyg_vector_t vector,
+                            cyg_ucount32 count,
+                            cyg_addrword_t data);
+
+// -------------------------------------------------------------------------
+// Driver functions:
+CYG_ADC_FUNCTIONS( at91_adc_funs,
+                   at91_adc_enable,
+                   at91_adc_disable,
+                   at91_adc_set_rate );
+
+
+#include CYGDAT_DEVS_ADC_ARM_AT91_INL // Instantiate ADCs
+
+//==========================================================================
+// This function is called from the device IO infrastructure to initialize
+// the device. It should perform any work needed to start up the device,
+// short of actually starting the generation of samples. This function will
+// be called for each channel, so if there is initialization that only needs
+// to be done once, such as creating and interrupt object, then care should
+// be taken to do this. This function should also call cyg_adc_device_init()
+// to initialize the generic parts of the driver.
+//==========================================================================
+static bool at91_adc_init(struct cyg_devtab_entry *tab)
+{
+    cyg_adc_channel *chan   = (cyg_adc_channel *)tab->priv;
+    cyg_adc_device *device  = chan->device;
+    at91_adc_info *info     = device->dev_priv;
+    cyg_uint32 regval;
+
+    if (!info->int_handle)
+    {
+       cyg_drv_interrupt_create(info->timer_vector,
+                                 info->timer_intprio,
+                                (cyg_addrword_t)device,
+                                &at91_adc_isr,
+                                &at91_adc_dsr,
+                                &(info->int_handle),
+                                &(info->int_data));
+       cyg_drv_interrupt_attach(info->int_handle);
+       cyg_drv_interrupt_mask(info->timer_vector);
+
+       // Reset ADC
+       HAL_WRITE_UINT32((info->adc_base + AT91_ADC_CR), AT91_ADC_CR_SWRST);
+
+       // Disable counter interrupts
+       HAL_WRITE_UINT32(info->tc_base+AT91_TC_CCR, AT91_TC_CCR_CLKDIS);
+       HAL_WRITE_UINT32(info->tc_base+AT91_TC_IDR, 0xffffffff);
+
+       // Clear status bit
+       HAL_READ_UINT32(info->tc_base + AT91_TC_SR, regval);
+
+       // Enable peripheral clocks for TC
+       HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCER,  \
+             ((AT91_PMC_PCER_TC0) << info->timer_id));
+
+       //
+       // Disable all interrupts, all channels
+       //
+       HAL_WRITE_UINT32((info->adc_base + AT91_ADC_CHDR), \
+                     AT91_ADC_CHER_CH0  |\
+                     AT91_ADC_CHER_CH1  |\
+                     AT91_ADC_CHER_CH2  |\
+                     AT91_ADC_CHER_CH3  |\
+                     AT91_ADC_CHER_CH4  |\
+                     AT91_ADC_CHER_CH5  |\
+                     AT91_ADC_CHER_CH6  |\
+                     AT91_ADC_CHER_CH7);
+       HAL_WRITE_UINT32((info->adc_base + AT91_ADC_IDR), \
+                     AT91_ADC_CHER_CH0  |\
+                     AT91_ADC_CHER_CH1  |\
+                     AT91_ADC_CHER_CH2  |\
+                     AT91_ADC_CHER_CH3  |\
+                     AT91_ADC_CHER_CH4  |\
+                     AT91_ADC_CHER_CH5  |\
+                     AT91_ADC_CHER_CH6  |\
+                     AT91_ADC_CHER_CH7);
+
+       //
+       // setup the default sample rate
+       //
+       at91_adc_set_rate(chan, chan->device->config.rate);
+
+       // setup ADC mode
+       HAL_WRITE_UINT32((info->adc_base + AT91_ADC_MR), \
+                    ( ( info->adc_prescal  << AT91_ADC_MR_PRESCAL_SHIFT ) & \
+                        AT91_ADC_MR_PRESCAL_MASK ) | \
+                    ( ( info->adc_startup_time   << AT91_ADC_MR_STARTUP_SHIFT ) & \
+                        AT91_ADC_MR_STARTUP_MASK ) | \
+                    ( (  info->adc_shtim << AT91_ADC_MR_SHTIM_SHIFT ) & \
+                        AT91_ADC_MR_SHTIM_MASK ) | \
+                        AT91_ADC_MR_TRGSEL_TIOA0  | \
+                        info->resolution);
+
+
+    } // if (!info->int_handle)
+
+    cyg_adc_device_init(device); // initialize generic parts of driver
+
+    return true;
+}
+
+
+//==========================================================================
+// This function is called when a client looks up or opens a channel. It
+// should call cyg_adc_channel_init() to initialize the generic part of
+// the channel. It should also perform any operations needed to start the
+// channel generating samples.
+//==========================================================================
+static Cyg_ErrNo at91_adc_lookup(struct cyg_devtab_entry **tab,
+                                    struct cyg_devtab_entry  *sub_tab,
+                                    const char               *name)
+{
+    cyg_adc_channel  *chan     = (cyg_adc_channel *)(*tab)->priv;
+    at91_adc_info *info     = chan->device->dev_priv;
+
+    info->channel[chan->channel] = chan;
+    cyg_adc_channel_init(chan); // initialize generic parts of channel
+
+    //
+    // The generic ADC manual says: When a channel is first looked up or
+    // opened, then it is automatically enabled and samples start to
+    // accumulate - so we start the channel now
+    //
+    chan->enabled = true;
+    at91_adc_enable(chan);
+
+    return ENOERR;
+}
+
+
+//==========================================================================
+// This function is called from the generic ADC package to enable the
+// channel in response to a CYG_IO_SET_CONFIG_ADC_ENABLE config operation.
+// It should take any steps needed to start the channel generating samples
+//==========================================================================
+static void at91_adc_enable(cyg_adc_channel *chan)
+{
+    at91_adc_info *info      = chan->device->dev_priv;
+
+    // Enable the channel
+    HAL_WRITE_UINT32((info->adc_base + AT91_ADC_CHER), \
+                      AT91_ADC_CHER_CHx(chan->channel));
+
+    //
+    // Unmask interrupt as soon as 1 channel is enable
+    //
+    if (!info->chan_mask)
+    {
+       cyg_drv_interrupt_unmask(info->timer_vector);
+
+       // Enable timer interrupt
+       HAL_WRITE_UINT32(info->tc_base+AT91_TC_IER, AT91_TC_IER_CPC);
+
+       // Enable the clock
+       HAL_WRITE_UINT32(info->tc_base+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);
+
+       // Start timer
+       HAL_WRITE_UINT32(info->tc_base+AT91_TC_CCR,  AT91_TC_CCR_TRIG);
+
+       // Start ADC sampling
+       HAL_WRITE_UINT32((info->adc_base + AT91_ADC_CR), AT91_ADC_CR_START);
+
+    }
+
+    info->chan_mask |= AT91_ADC_CHER_CHx(chan->channel);
+
+}
+
+
+//==========================================================================
+// This function is called from the generic ADC package to enable the
+// channel in response to a CYG_IO_SET_CONFIG_ADC_DISABLE config operation.
+// It should take any steps needed to stop the channel generating samples.
+//==========================================================================
+static void at91_adc_disable(cyg_adc_channel *chan)
+{
+    at91_adc_info *info  = chan->device->dev_priv;
+    cyg_uint32 sr;
+
+    info->chan_mask &= ~ AT91_ADC_CHER_CHx(chan->channel);
+
+    // Disable the channel
+    HAL_WRITE_UINT32((info->adc_base + AT91_ADC_CHDR), \
+                      AT91_ADC_CHER_CHx(chan->channel));
+
+    //
+    // If no channel is enabled the we disable interrupts now
+    //
+    if (!info->chan_mask)
+    {
+       cyg_drv_interrupt_mask(info->timer_vector);
+
+       // Clear interrupt
+       HAL_READ_UINT32(info->tc_base+AT91_TC_SR, sr);
+
+       // Disable  timer interrupt
+       HAL_WRITE_UINT32(info->tc_base+AT91_TC_IDR, AT91_TC_IER_CPC);
+
+       // Disable the clock
+       HAL_WRITE_UINT32(info->tc_base+AT91_TC_CCR, AT91_TC_CCR_CLKDIS);
+
+    }
+}
+
+
+//==========================================================================
+// This function is called from the generic ADC package to enable the
+// channel in response to a CYG_IO_SET_CONFIG_ADC_RATE config operation.
+// It should take any steps needed to change the sample rate of the channel,
+// or of the entire device.
+// We use a timer channel to generate the interrupts for sampling the
+// analog channels
+//==========================================================================
+static void at91_adc_set_rate( cyg_adc_channel *chan, cyg_uint32 rate)
+{
+    cyg_adc_device   *device = chan->device;
+    at91_adc_info *info   = (at91_adc_info *)device->dev_priv;
+    cyg_uint8 timer_clk   = AT91_TC_CMR_CLKS_MCK2;
+    cyg_uint32 tmr_period = CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / ( rate << 1);
+
+    if( tmr_period > 0xffff )
+    {
+       tmr_period = CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / ( rate << 5);
+       timer_clk  = AT91_TC_CMR_CLKS_MCK32;
+    }
+
+    if( tmr_period > 0xffff )
+    {
+       tmr_period = CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / ( rate << 7);
+       timer_clk  = AT91_TC_CMR_CLKS_MCK128;
+    }
+
+    if( tmr_period > 0xffff )
+    {
+       tmr_period = CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / ( rate << 10);
+       timer_clk  = AT91_TC_CMR_CLKS_MCK1024;
+    }
+
+    if( tmr_period > 0xffff )
+    {
+       tmr_period = 0xffff;
+       timer_clk  = AT91_TC_CMR_CLKS_MCK1024;
+       at91_adc_printf("AT91 ADC timer, rate too high!");
+    }
+
+    device->config.rate = rate;
+    info->timer_clk = timer_clk;
+    info->timer_cnt = tmr_period;
+
+    // Set timer values
+    HAL_WRITE_UINT32(info->tc_base+AT91_TC_CMR,  AT91_TC_CMR_CPCTRG | info->timer_clk);
+    HAL_WRITE_UINT32(info->tc_base+AT91_TC_RC,  info->timer_cnt);
+
+    at91_adc_printf("AT91 ADC Timer settings %d, %d", info->timer_clk, info->timer_cnt);
+
+    return;
+}
+
+
+//==========================================================================
+// This function is the ISR attached to the ADC device's interrupt vector.
+// It is responsible for reading samples from the channels and passing them
+// on to the generic layer. It needs to check each channel for data, and call
+// cyg_adc_receive_sample() for each new sample available, and then ready the
+// device for the next interrupt.
+//==========================================================================
+static cyg_uint32 at91_adc_isr(cyg_vector_t vector, cyg_addrword_t data)
+{
+    cyg_adc_device   *device = (cyg_adc_device *) data;
+    at91_adc_info *info   = (at91_adc_info *)device->dev_priv;
+    cyg_uint32        regval,  adc_status;
+    cyg_uint32        res = 0;
+    cyg_adc_sample_t  adcdata;
+    cyg_uint32 sr;
+
+    cyg_uint8 active_channels = info->chan_mask;
+    cyg_uint8 channel_no = 0;
+
+    // Clear timer interrupt
+    HAL_READ_UINT32(info->tc_base+AT91_TC_SR, sr);
+
+    // Check on channel conversion done
+    HAL_READ_UINT32(info->adc_base + AT91_ADC_SR, adc_status);
+
+    while (active_channels)
+    {
+        if (active_channels & 0x01)
+        {
+            // If ADC conversion done, save sample
+            if(adc_status & AT91_ADC_CHER_CHx(channel_no))
+            {
+              HAL_READ_UINT32((info->adc_base + AT91_ADC_CDR0 + AT91_ADC_CHER_CDRx(channel_no)), regval);
+              adcdata = regval & 0x3FF;
+              res |= CYG_ISR_HANDLED
+                |  cyg_adc_receive_sample(info->channel[channel_no],
+                                          adcdata);
+            }
+        } // if (active_channels & 0x01)
+        active_channels >>= 1;
+        channel_no++;
+    } // while (active_channels)
+
+    // Restart sampling
+    HAL_WRITE_UINT32((info->adc_base + AT91_ADC_CR), AT91_ADC_CR_START);
+
+    cyg_drv_interrupt_acknowledge(info->timer_vector);
+
+    return res;
+}
+
+
+//==========================================================================
+// This function is the DSR attached to the ADC device's interrupt vector.
+// It is called by the kernel if the ISR return value contains the
+// CYG_ISR_HANDLED bit. It needs to call cyg_adc_wakeup() for each channel
+// that has its wakeup field set.
+//==========================================================================
+static void at91_adc_dsr(cyg_vector_t vector,
+                            cyg_ucount32 count,
+                            cyg_addrword_t data)
+{
+    cyg_adc_device   *device          = (cyg_adc_device *) data;
+    at91_adc_info *info            = device->dev_priv;
+    cyg_uint8         active_channels = info->chan_mask;
+    cyg_uint8         chan_no         = 0;
+
+    while (active_channels)
+    {
+        if (active_channels & 0x01)
+        {
+            if(info->channel[chan_no]->wakeup)
+            {
+                cyg_adc_wakeup(info->channel[chan_no]);
+            }
+        }
+        chan_no++;
+        active_channels >>= 1;
+    }
+}
+
+
+//---------------------------------------------------------------------------
+// eof adc_at91.c
diff --git a/packages/devs/adc/arm/at91/current/tests/at91_adc_test.c b/packages/devs/adc/arm/at91/current/tests/at91_adc_test.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/adc/arm/at91/current/tests/at91_adc_test.c
@@ -0,0 +1,290 @@
+//==========================================================================
+//
+//      at91_adc_test.c
+//
+//      ADC driver for AT91 on chip ADC
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):  Uwe Kindler <uwe_kindler@web.de>
+//             Updated for Atmel AT91 device, ccoutand <ccoutand@stmi.com>
+// Contributors:
+// Date:         2010-02-15
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+
+#include <cyg/infra/testcase.h>         // test macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+#include <cyg/infra/diag.h>
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_arch.h>           // CYGNUM_HAL_STACK_SIZE_TYPICAL
+
+// Package requirements
+#if defined(CYGPKG_IO_ADC) && defined(CYGPKG_KERNEL)
+
+#include <pkgconf/kernel.h>
+#include <cyg/io/io.h>
+#include <cyg/io/adc.h>
+#include <pkgconf/devs_adc_arm_at91.h>
+
+// Package option requirements
+#if defined(CYGFUN_KERNEL_API_C)
+
+#include <cyg/kernel/kapi.h>
+
+#if CYGINT_DEVS_ADC_ARM_AT91_ADC0_CHANNELS > 0
+
+#define MAX_ADC_CHANNEL_TO_TEST 4
+
+//===========================================================================
+//                               DATA TYPES
+//===========================================================================
+typedef struct st_thread_data
+{
+    cyg_thread   obj;
+    long         stack[CYGNUM_HAL_STACK_SIZE_TYPICAL];
+    cyg_handle_t hdl;
+} thread_data_t;
+
+
+//===========================================================================
+//                              LOCAL DATA
+//===========================================================================
+cyg_thread_entry_t adc_thread;
+thread_data_t      adc_thread_data;
+
+
+//===========================================================================
+//                             ADC THREAD
+//===========================================================================
+void adc_thread(cyg_addrword_t data)
+{
+    int             res;
+    cyg_io_handle_t handle[8]     = {0, 0, 0, 0, 0, 0, 0, 0};
+    cyg_uint32      sample_cnt[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+    cyg_uint32      cfg_data;
+    cyg_uint32      len;
+    cyg_uint32      start_time;
+    cyg_uint32      end_time;
+    int             i;
+    cyg_uint8       seconds = 0;
+    float           final_seconds;
+    cyg_uint32      samples_expected;
+
+
+    diag_printf("This test reads samples from all enabled ADC channels.\n"
+                "Each second the number of already acquired samples\n"
+                "will be printed. After 10 seconds all ADC channels\n"
+                "will be stopped and each ADC buffer will be read until\n"
+                "it is empty. If the number of acquired samples is much\n"
+                "smaller than the number of expected samples, then you\n"
+                "should lower the sample rate.\n\n");
+
+    // Get a handle for ADC device 0 channel 0 - 3 (lookup also trigger a channel enable)
+    res = cyg_io_lookup( "/dev/adc00", &handle[0]);
+    res = cyg_io_lookup( "/dev/adc01", &handle[1]);
+    res = cyg_io_lookup( "/dev/adc02", &handle[2]);
+    res = cyg_io_lookup( "/dev/adc03", &handle[3]);
+
+    //
+    // switch all channels to non blocking
+    //
+    for (i = 0; i < MAX_ADC_CHANNEL_TO_TEST; ++i)
+    {
+        if (handle[i])
+        {
+            cfg_data = 0;
+            len = sizeof(cfg_data);
+            res = cyg_io_set_config(handle[i],
+                                    CYG_IO_SET_CONFIG_READ_BLOCKING,
+                                    &cfg_data,
+                                    &len);
+            if (ENOERR != res)
+            {
+                CYG_TEST_FAIL_FINISH("Error switching ADC channel to non blocking");
+            }
+            sample_cnt[i] = 0;
+        }
+    }
+
+    start_time = cyg_current_time();
+    do
+    {
+        for (i = 0; i < MAX_ADC_CHANNEL_TO_TEST; ++i)
+        {
+            if (handle[i])
+            {
+                cyg_adc_sample_t sample;
+
+                // read a sample from the channel
+                do
+                {
+                    cyg_uint32 len = sizeof(sample);
+                    res = cyg_io_read( handle[i], &sample, &len );
+                }
+                while (-EAGAIN == res);
+                if (ENOERR == res)
+                {
+                    sample_cnt[i]++;
+                }
+            } // if (handle[i])
+        }
+        //
+        // print number of acquired samples - if one second is expired.
+        // we expect that the number of acquired samples is nearly the
+        // sample rate
+        //
+        end_time = cyg_current_time();
+        if ((end_time - start_time) >= 100)
+        {
+            start_time = end_time;
+            diag_printf("%d\t %d\t %d\t %d\n",
+                        sample_cnt[0],
+                        sample_cnt[1],
+                        sample_cnt[2],
+                        sample_cnt[3]);
+            seconds++;
+        } // if ((end_time - start_time) >= 100)
+    } while (seconds < 10);
+
+    //
+    // Now stop all channels
+    //
+    for (i = 0; i < MAX_ADC_CHANNEL_TO_TEST; ++i)
+    {
+        if (handle[i])
+        {
+            res = cyg_io_set_config(handle[i],
+                                    CYG_IO_SET_CONFIG_ADC_DISABLE,
+                                    0,
+                                    0);
+            if (ENOERR != res)
+            {
+                CYG_TEST_FAIL_FINISH("Error disabling ADC channel");
+            }
+        } // if (handle[i])
+    }
+    end_time = cyg_current_time();
+    end_time = seconds * 1000 + (end_time - start_time) * 10;
+    final_seconds = end_time / 1000.0;
+
+    //
+    // Now read all remaining samples from buffer
+    //
+    for (i = 0; i < MAX_ADC_CHANNEL_TO_TEST; ++i)
+    {
+        if (handle[i])
+        {
+            do
+            {
+                cyg_adc_sample_t sample;
+                cyg_uint32 len = sizeof(sample);
+                res = cyg_io_read( handle[i], &sample, &len );
+                if (ENOERR == res)
+                {
+                    sample_cnt[i]++;
+                }
+            } while (ENOERR == res);
+        } // if (handle[i])
+    }
+
+    diag_printf("\n\n----------------------------------------\n");
+    samples_expected = final_seconds * CYGNUM_DEVS_ADC_ARM_AT91_ADC0_DEFAULT_RATE;
+    diag_printf("Samples expected after %d milliseconds: %d\n",
+                end_time, samples_expected);
+    diag_printf("Samples read (per channel):\n");
+    diag_printf("%d\t %d\t %d\t %d\n",
+                sample_cnt[0],
+                sample_cnt[1],
+                sample_cnt[2],
+                sample_cnt[3]);
+
+    CYG_TEST_PASS_FINISH("ADC test OK");
+}
+
+
+void
+cyg_start(void)
+{
+    CYG_TEST_INIT();
+
+    //
+    // create the main ADC test thread
+    //
+    cyg_thread_create(4, adc_thread,
+                      (cyg_addrword_t) 0,
+                      "at91_adc_thread",
+                      (void *) adc_thread_data.stack,
+                      1024 * sizeof(long),
+                      &adc_thread_data.hdl,
+                      &adc_thread_data.obj);
+
+    cyg_thread_resume(adc_thread_data.hdl);
+
+    cyg_scheduler_start();
+}
+#else // CYGINT_DEVS_ADC_ARM_AT91_CHANNELS > 0
+#define N_A_MSG "Needs at least one enabled ADC channel"
+#endif
+
+#else // CYGFUN_KERNEL_API_C
+#define N_A_MSG "Needs kernel C API"
+#endif
+
+#else // CYGPKG_IO_ADC && CYGPKG_KERNEL
+#define N_A_MSG "Needs Kernel and ADC support"
+#endif
+
+#ifdef N_A_MSG
+void
+cyg_start( void )
+{
+    CYG_TEST_INIT();
+    CYG_TEST_NA(N_A_MSG);
+}
+#endif // N_A_MSG
+
+
+// EOF can_tx.c
+
+//---------------------------------------------------------------------------
+// eof at91_adc_test.c
diff --git a/packages/devs/adc/cortexm/lm3s/current/ChangeLog b/packages/devs/adc/cortexm/lm3s/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/adc/cortexm/lm3s/current/ChangeLog
@@ -0,0 +1,31 @@
+2011-01-18  Christophe Coutand  <ccoutand@stmi.com>
+
+	* cdl/adc_lm3s.cdl:
+	* src/adc_lm3s.c:
+	* include/adc_lm3s.inl:
+	* tests/lm3s_adc_test.c:
+	New package -- Stellaris Cortex M3 ADC driver package.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/adc/cortexm/lm3s/current/cdl/adc_lm3s.cdl b/packages/devs/adc/cortexm/lm3s/current/cdl/adc_lm3s.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/adc/cortexm/lm3s/current/cdl/adc_lm3s.cdl
@@ -0,0 +1,217 @@
+# ====================================================================
+#
+#      adc_lm3s.cdl
+#
+#      eCos Stellaris Cortex M3 ADC configuration data
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      ccoutand
+# Contributors:   
+# Date:           2011-01-12
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_ADC_CORTEXM_LM3S {
+    display       "ADC driver for Stellaris Cortex M3 microcontroller family"
+
+    parent        CYGPKG_IO_ADC_DEVICES
+    active_if     CYGPKG_IO_ADC_DEVICES
+    active_if     CYGPKG_HAL_CORTEXM_LM3S
+    include_dir   cyg/io
+    description   "
+        This package provides a generic ADC device driver for the on-chip
+        ADC peripherals in Stellaris microcontroller."
+
+    compile       -library=libextras.a adc_lm3s.c
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGDAT_DEVS_ADC_CORTEXM_LM3S_INL <cyg/io/adc_lm3s.inl>"
+    }
+
+    # ---------------------------------------------------------------------
+    # Primary ADC ( ADC0 ) port
+
+    cdl_component CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0 {
+        display       "ADC port 0"
+        flavor        bool
+        default_value 1
+        description   "
+            This option includes the device driver for the on-chip ADC0
+            of the Stellaris device."
+
+        cdl_interface CYGINT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNELS {
+            display "Number of ADC0 channels"
+        }
+
+        cdl_option CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_SELECT_TIMER {
+            display       "ADC sampling timer"
+            flavor        data
+            legal_values  { 0 1 2 }
+            default_value 0
+            description   "
+                This option selects the timer channel generating the
+                ADC sampling interval."
+        }
+
+        cdl_option CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_INTPRIO {
+            display       "ADC Interrupt priority"
+            flavor        data
+            default_value 0x60
+            description   "
+               This option selects the interrupt priority for the ADC
+               interrupts."
+        }
+
+        cdl_option CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_DEFAULT_RATE {
+            display       "Default sample rate"
+            flavor        data
+            legal_values  1 to 10000
+            default_value 100
+            description   "
+                The driver will be initialized with the default sample
+                rate.  If you raise the default sample rate you might
+                need to increase the buffer size for each channel."
+        }
+
+        cdl_option CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING {
+            display       "Sample averaging"
+            flavor        data
+            legal_values  { 0 2 4 8 16 32 64 }
+            default_value 0
+            description   "
+                Select the ADC sample averaging."
+        }
+
+        cdl_component CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_TEMP_SENSOR {
+            display       "Internal Temperature Sensor"
+            flavor        bool
+            default_value 0
+            description   "
+                Enable one ADC channel for internal temperature sensor
+                reading."
+
+            cdl_option CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_TEMP_SENSOR_CHANNEL {
+                display       "Select sensor channel"
+                flavor        data
+                legal_values  { 0 to (CYGINT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNELS-1) }
+                default_value 1
+                description   "
+                    This option select ADC channel reserved for
+                    temperature sensor reading."
+            }
+        }
+
+        # -----------------------------------------------------------------
+        # Support up to 8 ADC channels
+
+        for { set ::channel 0 } { $::channel < 8 } { incr ::channel } {
+            cdl_component CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL[set ::channel] {
+                display       "Access ADC channel [set ::channel]"
+                flavor        bool
+                default_value [set ::channel] == 0
+                implements    CYGINT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNELS
+                description   "
+                    If the application needs to access the on-chip ADC0
+                    channel [set ::channel] via an eCos ADC driver then
+                    this option should be enabled."
+
+                cdl_option CYGDAT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL[set ::channel]_NAME {
+                    display       "Device name"
+                    flavor        data
+                    default_value [format {"\"/dev/adc0%d\""} $::channel]
+                    description   "
+                        This option controls the name that an eCos
+                        application should use to access this device
+                        via cyg_io_lookup(), open(), or similar calls."
+                }
+
+                cdl_option CYGDAT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL[set ::channel]_BUFSIZE {
+                    display       "Size of data buffer"
+                    flavor        data
+                    legal_values  0x01 to 0x16
+                    default_value 0x4
+                    description   "
+                        This option controls the number of samples the
+                        buffer can store. The required RAM depends on the
+                        sample size and on the number of samples. If the
+                        sample size is <= 8 bit the the required RAM =
+                        size of data buffer. If the sample size is 9 or 10
+                        bit then required RAM = size of data buffer * 2."
+                }
+            }
+        }
+    }
+
+    cdl_option CYGPKG_DEVS_ADC_CORTEXM_LM3S_DEBUG_LEVEL {
+        display       "Driver debug output level"
+        flavor        data
+        legal_values  { 0 1 }
+        default_value 0
+        description   "
+            This option specifies the level of debug data output by
+            the Stellaris ADC device driver. A value of 0 signifies no
+            debug data output; 1 signifies normal debug data output. If
+            an overrun occurred then this can only be detected by debug
+            output messages."
+    }
+
+    cdl_component CYGSEM_DEVS_ADC_CORTEXM_LM3S_SAMPLE_SIZE_LIMIT {
+        display       "Sample size limit"
+        flavor        bool
+        calculated    1
+        requires      { ( CYGNUM_IO_ADC_SAMPLE_SIZE == 10 ) }
+        description   "
+            This component forces a limit (or rounds) the sample size
+            for Stellaris ADC channels which in the most are 10-bit."
+    }
+
+    cdl_option CYGPKG_DEVS_ADC_CORTEXM_LM3S_TESTS {
+        display       "Tests for Stellaris 800 Series ADC driver"
+        flavor        data
+        no_define
+        active_if     CYGPKG_KERNEL
+        active_if     CYGPKG_IO_ADC
+        calculated    { "tests/lm3s_adc_test" }
+        description   "
+            This option specifies the set of tests for the Stellaris
+            ADC device driver."
+    }
+}
+
+# EOF adc_lm3s.cdl
diff --git a/packages/devs/adc/cortexm/lm3s/current/include/adc_lm3s.inl b/packages/devs/adc/cortexm/lm3s/current/include/adc_lm3s.inl
new file mode 100644
--- /dev/null
+++ b/packages/devs/adc/cortexm/lm3s/current/include/adc_lm3s.inl
@@ -0,0 +1,140 @@
+//==========================================================================
+//
+//      adc_lm3s.inl
+//
+//      ADC driver for Stellaris Cortex M3 microcontroller
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+//              
+// Contributors:
+// Date:         2011-01-08
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#ifndef CYGONCE_DEVS_ADC_CORTEXM_LM3S_INL
+#define CYGONCE_DEVS_ADC_CORTEXM_LM3S_INL
+
+// Declare ADC0
+#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0
+
+static lm3s_adc_info lm3s_adc0_info =
+{
+    .timer_base       = CYGHWR_HAL_LM3S_GPTIM0 + ( 0x1000 * CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_SELECT_TIMER ),
+    .adc_intprio      = CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_INTPRIO,
+    .adc_vector       = CYGNUM_HAL_INTERRUPT_ADC0_S0,
+    .adc_base         = CYGHWR_HAL_LM3S_ADC0,
+    .adc_periph       = CYGHWR_HAL_LM3S_P_ADC0,
+    .timer_periph     = (CYGHWR_HAL_LM3S_SC_RCGC1_TIMER0 << CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_SELECT_TIMER),
+#if   CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING == 0
+    .adc_avg          = 0,
+#elif CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING == 2
+    .adc_avg          = 1,
+#elif CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING == 4
+    .adc_avg          = 2,
+#elif CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING == 8
+    .adc_avg          = 3,
+#elif CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING == 16
+    .adc_avg          = 4,
+#elif CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING == 32
+    .adc_avg          = 5,
+#elif CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING == 64
+    .adc_avg          = 6,
+#endif
+#if defined(CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_TEMP_SENSOR)
+    .sensor_channel   = CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_TEMP_SENSOR_CHANNEL,
+#else
+    .sensor_channel   = 0xff,
+#endif
+    .max_channel      = CYGINT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNELS,
+    .int_handle       = 0,
+    .chan_mask        = 0
+};
+
+CYG_ADC_DEVICE(                                                 \
+         lm3s_adc0_device,                                      \
+         &lm3s_adc_funs,                                        \
+         &lm3s_adc0_info,                                       \
+         CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_DEFAULT_RATE);
+
+#define LM3S_ADC0_CHANNEL( __chan )                                      \
+CYG_ADC_CHANNEL(                                                         \
+         lm3s_adc0_channel##__chan,                                      \
+         __chan,                                                         \
+         CYGDAT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL##__chan##_BUFSIZE,    \
+         &lm3s_adc0_device );                                            \
+DEVTAB_ENTRY(                                                            \
+         lm3s_adc0_channel##__chan##_device,                             \
+         CYGDAT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL##__chan##_NAME,       \
+         0,                                                              \
+         &cyg_io_adc_devio,                                              \
+         lm3s_adc_init,                                                  \
+         lm3s_adc_lookup,                                                \
+         &lm3s_adc0_channel##__chan );
+
+#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL0
+LM3S_ADC0_CHANNEL(0);
+#endif
+#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL1
+LM3S_ADC0_CHANNEL(1);
+#endif
+#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL2
+LM3S_ADC0_CHANNEL(2);
+#endif
+#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL3
+LM3S_ADC0_CHANNEL(3);
+#endif
+#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL4
+LM3S_ADC0_CHANNEL(4);
+#endif
+#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL5
+LM3S_ADC0_CHANNEL(5);
+#endif
+#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL6
+LM3S_ADC0_CHANNEL(6);
+#endif
+#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL7
+LM3S_ADC0_CHANNEL(7);
+#endif
+
+#endif // CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0
+
+#endif // CYGONCE_DEVS_ADC_CORTEXM_LM3S_INL
diff --git a/packages/devs/adc/cortexm/lm3s/current/src/adc_lm3s.c b/packages/devs/adc/cortexm/lm3s/current/src/adc_lm3s.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/adc/cortexm/lm3s/current/src/adc_lm3s.c
@@ -0,0 +1,489 @@
+//==========================================================================
+//
+//      adc_lm3s.c
+//
+//      ADC driver for Stellaris Cortex M3 microcontroller
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Uwe Kindler <uwe_kindler@web.de>
+//              Updated for Stellaris device, ccoutand
+// Contributors:
+// Date:         2011-01-08
+// Purpose:
+// Description:
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+
+//==========================================================================
+//                                 INCLUDES
+//==========================================================================
+#include <pkgconf/system.h>
+#include <pkgconf/devs_adc_cortexm_lm3s.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/diag.h>
+#include <cyg/io/adc.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/drv_api.h>
+
+#if CYGPKG_DEVS_ADC_CORTEXM_LM3S_DEBUG_LEVEL > 0
+# define lm3s_adc_diag(args...) diag_printf(args)
+#else
+# define lm3s_adc_diag(args...)
+#endif
+
+#define CYGHWR_HAL_LM3S_ADC_MAX_CHAN 8
+
+//==========================================================================
+//                                  DATA TYPES
+//==========================================================================
+typedef struct lm3s_adc_info {
+    cyg_uint32      adc_base;          // ADC base address
+    cyg_uint32      adc_periph;        // ADC peripheral mask
+    cyg_vector_t    adc_vector;        // Interrupt vector number
+    cyg_priority_t  adc_intprio;       // Interrupt priority of ADC interrupt
+    cyg_uint32      timer_base;        // Base address of Timer peripheral
+    cyg_uint32      timer_interval;    // Timer value
+    cyg_uint32      timer_periph;      // Timer peripheral mask
+    cyg_uint8       sensor_channel;    // Temperature sensor channel if any
+    cyg_uint8       max_channel;       // Number of ADC channel
+    cyg_handle_t    int_handle;        // For initializing the interrupt
+    cyg_interrupt   int_data;
+    cyg_uint8       adc_avg;           // Sample averaging
+    // Stores references to channel objects
+    struct cyg_adc_channel *channel[CYGHWR_HAL_LM3S_ADC_MAX_CHAN];
+    cyg_uint8       chan_mask;         // Mask that indicates channels used
+                                       // by ADC driver
+} lm3s_adc_info;
+
+
+//==========================================================================
+//                               DECLARATIONS
+//==========================================================================
+static bool     lm3s_adc_init(struct cyg_devtab_entry *tab);
+static Cyg_ErrNo lm3s_adc_lookup(struct cyg_devtab_entry **tab,
+                                 struct cyg_devtab_entry *sub_tab,
+                                 const char *name);
+static void     lm3s_adc_enable(cyg_adc_channel * chan);
+static void     lm3s_adc_disable(cyg_adc_channel * chan);
+static void     lm3s_adc_set_rate(cyg_adc_channel * chan, cyg_uint32 rate);
+static cyg_uint32 lm3s_adc_isr(cyg_vector_t vector, cyg_addrword_t data);
+static void     lm3s_adc_dsr(cyg_vector_t vector,
+                             cyg_ucount32 count, cyg_addrword_t data);
+
+static void     lm3s_adc_disable_sequencer0(cyg_uint32);
+static void     lm3s_adc_enable_sequencer0(cyg_uint32);
+static void     lm3s_adc_flush(cyg_uint32);
+static void     lm3s_adc_update_sequencer0(cyg_adc_channel *);
+
+// -------------------------------------------------------------------------
+// Driver functions:
+CYG_ADC_FUNCTIONS( lm3s_adc_funs,
+                   lm3s_adc_enable,
+                   lm3s_adc_disable,
+                   lm3s_adc_set_rate );
+
+
+#include CYGDAT_DEVS_ADC_CORTEXM_LM3S_INL       // Instantiate ADCs
+
+
+//==========================================================================
+//
+// The eCos Sellaris ADC drivers uses a single sequencer ( sequencer 0 ).
+// The same sequencer is used to sample all channels.
+// Sampling of the different channel is triggered from a timer interrupt.
+// The ADC driver flexibility does not allow to trigger sampling from
+// external GPIO or analog comparator event. It should be noted that enabling
+// / disabling an ADC channel disturbs the sampling of other channels since it
+// requires to stop sampling to re-organize the sequencer. Also the FIFO
+// is flushed to ensure correct sample order out of the sequencer FIFO.
+//
+//==========================================================================
+static bool
+lm3s_adc_init(struct cyg_devtab_entry *tab)
+{
+    cyg_adc_channel *chan = (cyg_adc_channel *) tab->priv;
+    cyg_adc_device *device = chan->device;
+    lm3s_adc_info  *info = device->dev_priv;
+
+    lm3s_adc_diag("ADC: Init\n");
+
+    if (!info->int_handle) {
+        lm3s_adc_diag("ADC: IRQ vect %d, pri %d\n",
+                      info->adc_vector, info->adc_intprio);
+
+        cyg_drv_interrupt_create(info->adc_vector,
+                                 info->adc_intprio,
+                                 (cyg_addrword_t)device,
+                                 &lm3s_adc_isr,
+                                 &lm3s_adc_dsr,
+                                 &(info->int_handle), &(info->int_data));
+        cyg_drv_interrupt_attach(info->int_handle);
+        cyg_drv_interrupt_mask(info->adc_vector);
+
+        // Enable ADC and sampling timer peripheral
+        CYGHWR_HAL_LM3S_PERIPH_SET(info->adc_periph, 1);
+        CYGHWR_HAL_LM3S_PERIPH_SET((CYGHWR_HAL_LM3S_PERIPH_GC1 | info->
+                                    timer_periph), 1);
+
+        // Disable timer
+        HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_CTL, 0);
+
+        // Disable / reset sequencer
+        HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_ACTSS, 0);
+        HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_SS_MUX0, 0);
+        HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_SS_CTL0, 0);
+
+        // Trigger sampling from timer
+        HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_EMUX,
+                         CYGHWR_HAL_LM3S_ADC_EMUX_EM_TIMER(0));
+
+        // Set Averaging
+        HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_SAC,
+                         info->adc_avg);
+
+        // Setup timer
+        HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_CFG,
+                         CYGHWR_HAL_LM3S_GPTIM_CFG_32BIT);
+        HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_TAMR,
+                         CYGHWR_HAL_LM3S_GPTIM_TAMR_PERIODIC);
+
+        // Setup the default sample rate
+        lm3s_adc_set_rate(chan, chan->device->config.rate);
+
+    }
+
+    // Initialize generic parts of driver
+    cyg_adc_device_init(device);
+
+    return true;
+}
+
+
+//==========================================================================
+// This function is called when a client looks up or opens a channel. It
+// should call cyg_adc_channel_init() to initialize the generic part of
+// the channel. It should also perform any operations needed to start the
+// channel generating samples.
+//==========================================================================
+static Cyg_ErrNo
+lm3s_adc_lookup(struct cyg_devtab_entry **tab,
+                struct cyg_devtab_entry *sub_tab, const char *name)
+{
+    cyg_adc_channel *chan = (cyg_adc_channel *) (*tab)->priv;
+    lm3s_adc_info  *info = chan->device->dev_priv;
+
+    lm3s_adc_diag("ADC: Opening channel %d\n", chan->channel);
+
+    if (chan->channel > info->max_channel)
+        return ENOENT;
+
+    info->channel[chan->channel] = chan;
+
+    // Initialize generic parts of channel
+    cyg_adc_channel_init(chan);
+
+    // The generic ADC manual says: When a channel is first looked up or
+    // opened, then it is automatically enabled and samples start to
+    // accumulate - so we start the channel now
+    chan->enabled = true;
+    lm3s_adc_enable(chan);
+
+    return ENOERR;
+}
+
+
+//==========================================================================
+// This function is called from the generic ADC package to enable the
+// channel in response to a CYG_IO_SET_CONFIG_ADC_ENABLE config operation.
+// It should take any steps needed to start the channel generating samples
+//==========================================================================
+static void
+lm3s_adc_enable(cyg_adc_channel * chan)
+{
+    lm3s_adc_info  *info = chan->device->dev_priv;
+    cyg_uint32      ctl =
+        CYGHWR_HAL_LM3S_GPTIM_CTL_TAEN | CYGHWR_HAL_LM3S_GPTIM_CTL_TAOTE;
+    cyg_uint32      start = !info->chan_mask;
+
+    // Disable ADC sequencer 0 and timer
+    HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_CTL, 0);
+    lm3s_adc_disable_sequencer0(info->adc_base);
+
+    // Update sequencer
+    info->chan_mask |= (1 << chan->channel);
+    lm3s_adc_update_sequencer0(chan);
+
+    // Unmask interrupt as soon as 1 channel is enable
+    if (start) {
+        cyg_drv_interrupt_unmask(info->adc_vector);
+    }
+    // Enable sequencer and timer
+    lm3s_adc_enable_sequencer0(info->adc_base);
+    HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_CTL, ctl);
+}
+
+
+//==========================================================================
+// This function is called from the generic ADC package to enable the
+// channel in response to a CYG_IO_SET_CONFIG_ADC_DISABLE config operation.
+// It should take any steps needed to stop the channel generating samples.
+//==========================================================================
+static void
+lm3s_adc_disable(cyg_adc_channel * chan)
+{
+    lm3s_adc_info  *info = chan->device->dev_priv;
+    cyg_uint32      ctl =
+        CYGHWR_HAL_LM3S_GPTIM_CTL_TAEN | CYGHWR_HAL_LM3S_GPTIM_CTL_TAOTE;
+
+    // Disable ADC sequencer 0 and timer
+    HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_CTL, 0);
+    lm3s_adc_disable_sequencer0(info->adc_base);
+
+    // Update sequencer
+    info->chan_mask &= ~(1 << chan->channel);
+    lm3s_adc_update_sequencer0(chan);
+
+    // Stop scanning when no channel is active
+    if (!info->chan_mask) {
+        cyg_drv_interrupt_mask(info->adc_vector);
+        return;
+    }
+    // Enable sequencer and timer
+    lm3s_adc_enable_sequencer0(info->adc_base);
+    HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_CTL, ctl);
+}
+
+
+//==========================================================================
+// This function is called from the generic ADC package to enable the
+// channel in response to a CYG_IO_SET_CONFIG_ADC_RATE config operation.
+// It should take any steps needed to change the sample rate of the channel,
+// or of the entire device.
+// We use a timer channel to generate the interrupts for sampling the
+// analog channels
+//==========================================================================
+static void
+lm3s_adc_set_rate(cyg_adc_channel * chan, cyg_uint32 rate)
+{
+    cyg_adc_device *device = chan->device;
+    lm3s_adc_info  *info = (lm3s_adc_info *) device->dev_priv;
+
+    info->timer_interval = hal_lm3s_timer_clock() / rate;
+
+    lm3s_adc_diag("ADC: Timer interval %d\n", info->timer_interval);
+
+    HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_TAILR,
+                     info->timer_interval);
+}
+
+
+//==========================================================================
+// This function is the ISR attached to the ADC device's interrupt vector.
+// It is responsible for reading samples from the channels and passing them
+// on to the generic layer. It needs to check each channel for data, and call
+// cyg_adc_receive_sample() for each new sample available, and then ready the
+// device for the next interrupt.
+//==========================================================================
+static cyg_uint32
+lm3s_adc_isr(cyg_vector_t vector, cyg_addrword_t data)
+{
+    cyg_adc_device *device = (cyg_adc_device *) data;
+    lm3s_adc_info  *info = (lm3s_adc_info *) device->dev_priv;
+    cyg_uint32      regval;
+    cyg_uint32      res = 0;
+    cyg_adc_sample_t adcdata;
+    cyg_uint32      sr;
+
+    cyg_uint8       active_channels = info->chan_mask;
+    cyg_uint8       channel_no = 0;
+
+    while (active_channels) {
+        HAL_READ_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_SS_FIFO0_SR, sr);
+        // Check FIFO Full
+        if ((sr & CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_FULL)) {
+            lm3s_adc_diag("ADC: FIFO Full\n");
+        }
+        // Check FIFO Empty
+        if ((sr & CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_EMPTY)) {
+            lm3s_adc_diag("ADC: FIFO Empty\n");
+        }
+        if (active_channels & 0x01) {
+            // If ADC conversion done, save sample
+            if (!(sr & CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_EMPTY)) {
+                HAL_READ_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_SS_FIFO0,
+                                regval);
+                adcdata = regval & 0x3FF;
+                res |= CYG_ISR_HANDLED
+                    | cyg_adc_receive_sample(info->channel[channel_no],
+                                             adcdata);
+            }
+        }
+        active_channels >>= 1;
+        channel_no++;
+    }
+
+    HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_ISCR,
+                     CYGHWR_HAL_LM3S_ADC_ISCR_IN(0));
+
+    cyg_drv_interrupt_acknowledge(info->adc_vector);
+
+    return res;
+}
+
+
+//==========================================================================
+// This function is the DSR attached to the ADC device's interrupt vector.
+// It is called by the kernel if the ISR return value contains the
+// CYG_ISR_HANDLED bit. It needs to call cyg_adc_wakeup() for each channel
+// that has its wakeup field set.
+//==========================================================================
+static void
+lm3s_adc_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
+{
+    cyg_adc_device *device = (cyg_adc_device *) data;
+    lm3s_adc_info  *info = device->dev_priv;
+    cyg_uint8       active_channels = info->chan_mask;
+    cyg_uint8       chan_no = 0;
+
+    while (active_channels) {
+        if (active_channels & 0x01) {
+            if (info->channel[chan_no]->wakeup) {
+                cyg_adc_wakeup(info->channel[chan_no]);
+            }
+        }
+        chan_no++;
+        active_channels >>= 1;
+    }
+}
+
+
+static void
+lm3s_adc_disable_sequencer0(cyg_uint32 base)
+{
+    cyg_uint32      reg;
+
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_ADC_IMR, 0);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_ADC_ISCR,
+                     CYGHWR_HAL_LM3S_ADC_ISCR_IN(0));
+    HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_ADC_ACTSS, reg);
+    reg &= ~(CYGHWR_HAL_LM3S_ADC_ACTSS_ASEN(0));
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_ADC_ACTSS, reg);
+}
+
+
+static void
+lm3s_adc_enable_sequencer0(cyg_uint32 base)
+{
+    cyg_uint32      reg;
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_ADC_ACTSS, reg);
+    reg |= (CYGHWR_HAL_LM3S_ADC_ACTSS_ASEN(0));
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_ADC_ACTSS, reg);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_ADC_IMR,
+                     CYGHWR_HAL_LM3S_ADC_IMR_MASK(0));
+}
+
+
+static void
+lm3s_adc_flush(cyg_uint32 base)
+{
+    volatile cyg_uint32 d;
+    volatile cyg_uint32 i;
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_ADC_SS_FIFO0_SR, i);
+    while (!(i & CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_EMPTY)) {
+        HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_ADC_SS_FIFO0, d);
+        HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_ADC_SS_FIFO0_SR, i);
+    }
+}
+
+
+static void
+lm3s_adc_update_sequencer0(cyg_adc_channel * chan)
+{
+    lm3s_adc_info  *info = chan->device->dev_priv;
+    cyg_uint8       i;
+    cyg_uint8       cnt = 0;
+    cyg_uint32      mux = 0;
+    cyg_uint32      ctl = 0;
+
+    lm3s_adc_diag("ADC: Update sequencer for channel %d\n", chan->channel);
+
+    // Update sequencer
+    for (i = 0; i < info->max_channel; i++) {
+        if (!(info->chan_mask & (1 << i)))
+            continue;
+
+        // Clear and update MUX register
+        mux &= ~(CYGHWR_HAL_LM3S_ADC_SS_MUX0_M(cnt));
+        mux |= CYGHWR_HAL_LM3S_ADC_SS_MUX0_V(i, cnt);
+
+        // Temperature sensor channel
+        if (i == info->sensor_channel) {
+            ctl |= CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS(cnt);
+            lm3s_adc_diag("ADC: Channel %d mapped to temperature sensor\n",
+                          i);
+        }
+
+        cnt++;
+    }
+
+    lm3s_adc_diag("ADC: MUX0 Register: 0x%x\n", mux);
+    HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_SS_MUX0, mux);
+
+    if (info->chan_mask) {
+        ctl |= CYGHWR_HAL_LM3S_ADC_SS_CTL0_END((cnt - 1));
+        ctl |= CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE((cnt - 1));
+    }
+
+    lm3s_adc_diag("ADC: CTL0 Register: 0x%x\n", ctl);
+    HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_SS_CTL0, ctl);
+
+    lm3s_adc_flush(info->adc_base);
+}
+
+
+//---------------------------------------------------------------------------
+// EOF adc_lm3s.c
diff --git a/packages/devs/adc/cortexm/lm3s/current/tests/lm3s_adc_test.c b/packages/devs/adc/cortexm/lm3s/current/tests/lm3s_adc_test.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/adc/cortexm/lm3s/current/tests/lm3s_adc_test.c
@@ -0,0 +1,256 @@
+//==========================================================================
+//
+//      lm3s_adc_test.c
+//
+//      ADC driver for Stellaris Cortex M3 microcontroller
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):  Uwe Kindler <uwe_kindler@web.de>
+//             Updated for Stellaris Cortex microcontroller, ccoutand
+// Contributors:
+// Date:         2011-01-11
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+
+#include <cyg/infra/testcase.h>        // test macros
+#include <cyg/infra/cyg_ass.h>         // assertion macros
+#include <cyg/infra/diag.h>
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_arch.h>          // CYGNUM_HAL_STACK_SIZE_TYPICAL
+
+#include <pkgconf/kernel.h>
+#include <cyg/io/io.h>
+#include <cyg/io/adc.h>
+#include <pkgconf/devs_adc_cortexm_lm3s.h>
+
+// Package option requirements
+#if defined(CYGFUN_KERNEL_API_C)
+
+# include <cyg/kernel/kapi.h>
+
+# if CYGINT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNELS > 0
+
+#  define MAX_ADC_CHANNEL_TO_TEST 4
+
+//===========================================================================
+//                               DATA TYPES
+//===========================================================================
+typedef struct st_thread_data {
+    cyg_thread      obj;
+    int             stack[(CYGNUM_HAL_STACK_SIZE_MINIMUM / sizeof(int))];
+    cyg_handle_t    hdl;
+} thread_data_t;
+
+
+//===========================================================================
+//                              LOCAL DATA
+//===========================================================================
+cyg_thread_entry_t adc_thread;
+thread_data_t   adc_thread_data;
+
+
+//===========================================================================
+//                             ADC THREAD
+//===========================================================================
+void
+adc_thread(cyg_addrword_t data)
+{
+    int             res;
+    cyg_io_handle_t handle[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+    cyg_uint32      sample_cnt[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+    cyg_uint32      cfg_data;
+    cyg_uint32      len;
+    cyg_uint32      start_time;
+    cyg_uint32      end_time;
+    int             i;
+    cyg_uint8       seconds = 0;
+    float           final_seconds;
+    cyg_uint32      samples_expected;
+
+
+    diag_printf("This test reads samples from all enabled ADC channels.\n"
+                "Each second the number of already acquired samples\n"
+                "will be printed. After 10 seconds all ADC channels\n"
+                "will be stopped and each ADC buffer will be read until\n"
+                "it is empty. If the number of acquired samples is much\n"
+                "smaller than the number of expected samples, then you\n"
+                "should lower the sample rate.\n\n");
+
+    // Get a handle for ADC device 0 channel 0 - 3 (lookup also trigger a
+    // channel enable)
+    res = cyg_io_lookup("/dev/adc00", &handle[0]);
+    res = cyg_io_lookup("/dev/adc01", &handle[1]);
+    res = cyg_io_lookup("/dev/adc02", &handle[2]);
+    res = cyg_io_lookup("/dev/adc03", &handle[3]);
+
+    // Switch all channels to non blocking
+    for (i = 0; i < MAX_ADC_CHANNEL_TO_TEST; ++i) {
+        if (handle[i]) {
+            cfg_data = 0;
+            len = sizeof(cfg_data);
+            res = cyg_io_set_config(handle[i],
+                                    CYG_IO_SET_CONFIG_READ_BLOCKING,
+                                    &cfg_data, &len);
+            if (ENOERR != res) {
+                CYG_TEST_FAIL_FINISH
+                    ("Error switching ADC channel to non blocking");
+            }
+            sample_cnt[i] = 0;
+        }
+    }
+
+    start_time = cyg_current_time();
+
+    do {
+        for (i = 0; i < MAX_ADC_CHANNEL_TO_TEST; ++i) {
+            if (handle[i]) {
+                cyg_adc_sample_t sample;
+
+                // read a sample from the channel
+                do {
+                    cyg_uint32      len = sizeof(sample);
+                    res = cyg_io_read(handle[i], &sample, &len);
+                }
+                while (-EAGAIN == res);
+                if (ENOERR == res) {
+                    sample_cnt[i]++;
+                }
+            }
+        }
+
+        end_time = cyg_current_time();
+
+        // Print number of acquired samples - if one second is expired.
+        // we expect that the number of acquired samples is nearly the
+        // sample rate.
+        if ((end_time - start_time) >= 100) {
+            start_time = end_time;
+            diag_printf("%d\t %d\t %d\t %d\n",
+                        sample_cnt[0],
+                        sample_cnt[1], sample_cnt[2], sample_cnt[3]);
+            seconds++;
+        }
+    } while (seconds < 10);
+
+    // Now stop all channels
+    for (i = 0; i < MAX_ADC_CHANNEL_TO_TEST; ++i) {
+        if (handle[i]) {
+            res = cyg_io_set_config(handle[i],
+                                    CYG_IO_SET_CONFIG_ADC_DISABLE, 0, 0);
+            if (ENOERR != res) {
+                CYG_TEST_FAIL_FINISH("Error disabling ADC channel");
+            }
+        }
+    }
+
+    end_time = cyg_current_time();
+    end_time = seconds * 1000 + (end_time - start_time) * 10;
+    final_seconds = end_time / 1000.0;
+
+    // Now read all remaining samples from buffer
+    for (i = 0; i < MAX_ADC_CHANNEL_TO_TEST; ++i) {
+        if (handle[i]) {
+            do {
+                cyg_adc_sample_t sample;
+                cyg_uint32      len = sizeof(sample);
+                res = cyg_io_read(handle[i], &sample, &len);
+                if (ENOERR == res) {
+                    sample_cnt[i]++;
+                }
+            } while (ENOERR == res);
+        }
+    }
+
+    diag_printf("\n\n----------------------------------------\n");
+    samples_expected =
+        final_seconds * CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_DEFAULT_RATE;
+    diag_printf("Samples expected after %d milliseconds: %d\n", end_time,
+                samples_expected);
+    diag_printf("Samples read (per channel):\n");
+    diag_printf("%d\t %d\t %d\t %d\n",
+                sample_cnt[0], sample_cnt[1], sample_cnt[2], sample_cnt[3]);
+
+    CYG_TEST_PASS_FINISH("ADC test OK");
+}
+
+
+void
+cyg_start(void)
+{
+    CYG_TEST_INIT();
+
+    // Create the main ADC test thread
+    cyg_thread_create(4,
+                      adc_thread,
+                      (cyg_addrword_t)0,
+                      "lm3s_adc_thread",
+                      (void *)adc_thread_data.stack,
+                      CYGNUM_HAL_STACK_SIZE_MINIMUM,
+                      &adc_thread_data.hdl,
+                      &adc_thread_data.obj
+        );
+
+    cyg_thread_resume(adc_thread_data.hdl);
+
+    cyg_scheduler_start();
+}
+# else// CYGINT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNELS > 0
+#  define N_A_MSG "Needs at least one enabled ADC channel"
+# endif
+
+#else // CYGFUN_KERNEL_API_C
+# define N_A_MSG "Needs kernel C API"
+#endif
+
+#ifdef N_A_MSG
+void
+cyg_start(void)
+{
+    CYG_TEST_INIT();
+    CYG_TEST_NA(N_A_MSG);
+}
+#endif // N_A_MSG
+
+
+//---------------------------------------------------------------------------
+// EOF lm3s_adc_test.c
diff --git a/packages/devs/adc/cortexm/stm32/current/ChangeLog b/packages/devs/adc/cortexm/stm32/current/ChangeLog
--- a/packages/devs/adc/cortexm/stm32/current/ChangeLog
+++ b/packages/devs/adc/cortexm/stm32/current/ChangeLog
@@ -1,3 +1,20 @@
+2012-04-13  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* src/adc_stm32.c:
+	* src/adc1.inl:
+	* src/adc3.inl:
+	Peripheral clocks are enable / disable using new 
+	CYGHWR_HAL_STM32_CLOCK_DISABLE / CYGHWR_HAL_STM32_CLOCK_ENABLE
+	macro supplied from the variant HAL. In addition, make sure timer
+	clock is enable.
+
+2011-05-02  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* cdl/adc_stm32.cdl:
+	* src/adc_stm32.c:
+	Make sure DMA clock is enabled. Fix ADC clock divider not set in
+	stm32_adc_init_clock.
+
 2009-03-05  Simon Kallweit  <simon.kallweit@intefo.ch>
 
 	* src/adc_stm32.c:
@@ -15,7 +32,7 @@ 2009-02-24  Simon Kallweit  <simon.kallw
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2009 Free Software Foundation, Inc.                        
+// Copyright (C) 2009, 2011 Free Software Foundation, Inc.                  
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/devs/adc/cortexm/stm32/current/cdl/adc_stm32.cdl b/packages/devs/adc/cortexm/stm32/current/cdl/adc_stm32.cdl
--- a/packages/devs/adc/cortexm/stm32/current/cdl/adc_stm32.cdl
+++ b/packages/devs/adc/cortexm/stm32/current/cdl/adc_stm32.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 2009 Free Software Foundation, Inc.                        
+## Copyright (C) 2009, 2011 Free Software Foundation, Inc                   
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -63,18 +63,23 @@ cdl_package CYGPKG_DEVS_ADC_CORTEXM_STM3
            
     include_dir cyg/io
     compile     -library=libextras.a adc_stm32.c
-    
+
+    cdl_option CYGPKG_DEVS_ADC_CORTEXM_STM32_TRACE {
+        display       "ADC driver tracing"
+        flavor        bool
+        default_value 0
+        description   "
+            Enable tracing of the ADC driver. Select to debug the driver."
+    }
+
     cdl_option CYGNUM_DEVS_ADC_CORTEXM_STM32_CLOCK_DIV {
          display        "ADC clock divider"
          flavor         data
          legal_values   { 2 4 6 8 }
          default_value  8
          description    "
-             This option specifies the level of debug data output by
-             the STM32 ADC device driver. A value of 0 signifies
-             no debug data output; 1 signifies normal debug data
-             output. If an overrun occurred then this can only be
-             detected by debug output messages."         
+             This option specifies the ADC clock divider value. The 
+             ADC clock frequency is defined as PCLK2 / ADC divider. "
     }
     
     cdl_component CYGHWR_DEVS_ADC_CORTEXM_STM32_ADC1 {
diff --git a/packages/devs/adc/cortexm/stm32/current/src/adc1.inl b/packages/devs/adc/cortexm/stm32/current/src/adc1.inl
--- a/packages/devs/adc/cortexm/stm32/current/src/adc1.inl
+++ b/packages/devs/adc/cortexm/stm32/current/src/adc1.inl
@@ -82,6 +82,8 @@ static const stm32_adc_setup stm32_adc_s
     .pins           = stm32_adc_pins1,
     .extsel         = 4,
     .sample_time    = CYGNUM_DEVS_ADC_CORTEXM_STM32_ADC1_SAMPLE_TIME,
+    .adc_clkena     = CYGHWR_HAL_STM32_ADC1_CLOCK,
+    .tim_clkena     = CYGHWR_HAL_STM32_TIM3_CLOCK,
 };
 
 // ADC DMA buffer
diff --git a/packages/devs/adc/cortexm/stm32/current/src/adc3.inl b/packages/devs/adc/cortexm/stm32/current/src/adc3.inl
--- a/packages/devs/adc/cortexm/stm32/current/src/adc3.inl
+++ b/packages/devs/adc/cortexm/stm32/current/src/adc3.inl
@@ -80,6 +80,8 @@ static const stm32_adc_setup stm32_adc_s
     .pins           = stm32_adc_pins3,
     .extsel         = 4,
     .sample_time    = CYGNUM_DEVS_ADC_CORTEXM_STM32_ADC3_SAMPLE_TIME,
+    .adc_clkena     = CYGHWR_HAL_STM32_ADC3_CLOCK,
+    .tim_clkena     = CYGHWR_HAL_STM32_TIM8_CLOCK,
 };
 
 // ADC DMA buffer
diff --git a/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c b/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c
--- a/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c
+++ b/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2009 Free Software Foundation, Inc.                        
+// Copyright (C) 2009, 2011 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -64,11 +64,11 @@
 // Diagnostic support
 // Switch the #if to 1 to generate some diagnostic messages.
 
-#if 0
-#include <cyg/infra/diag.h>
-#define adc_diag( __fmt, ... ) diag_printf("ADC: %30s[%4d]: " __fmt, __FUNCTION__, __LINE__, ## __VA_ARGS__ );
+#ifdef CYGPKG_DEVS_ADC_CORTEXM_STM32_TRACE
+# include <cyg/infra/diag.h>
+# define adc_diag( __fmt, ... ) diag_printf("ADC: %30s[%4d]: " __fmt, __FUNCTION__, __LINE__, ## __VA_ARGS__ );
 #else
-#define adc_diag( __fmt, ... ) 
+# define adc_diag( __fmt, ... ) 
 #endif
 
 
@@ -85,6 +85,8 @@ typedef struct stm32_adc_setup {
     const cyg_uint32    *pins;          // ADC associated GPIO pins
     cyg_uint8           extsel;         // ADC EXTSEL value (timer event)
     cyg_uint32          sample_time;    // ADC sampling time in us
+    cyg_uint32          adc_clkena;     // ADC clock enable
+    cyg_uint32          tim_clkena;     // Timer clock enable
 } stm32_adc_setup;
 
 //-----------------------------------------------------------------------------
@@ -361,7 +363,7 @@ stm32_dma_isr(cyg_vector_t vector, cyg_a
     cyg_adc_channel **chan = info->chan;
     cyg_uint32 isr;
     cyg_uint32 res = CYG_ISR_HANDLED;
-    
+
     HAL_READ_UINT32(info->setup->dma_base + CYGHWR_HAL_STM32_DMA_ISR, isr);
     if (!(isr & CYGHWR_HAL_STM32_DMA_ISR_MASK(info->setup->dma_channel)))
         return 0;
@@ -432,7 +434,7 @@ stm32_adc_init_clock(void)
     adc_clock = hal_stm32_pclk2 / 8;
 #endif
 
-    HAL_READ_UINT32(rcc + CYGHWR_HAL_STM32_RCC_CFGR, cfgr);
+    HAL_WRITE_UINT32(rcc + CYGHWR_HAL_STM32_RCC_CFGR, cfgr);
 }
 
 //-----------------------------------------------------------------------------
@@ -447,10 +449,13 @@ stm32_adc_init_device(cyg_adc_device *de
     cyg_uint32 cycles;
     cyg_uint32 smpr;
     int i;
-    
+
     static const cyg_uint32 cycles_table[] = 
         { 15, 75, 135, 285, 415, 555, 715, 2395 };
-    
+
+    CYGHWR_HAL_STM32_CLOCK_ENABLE( info->setup->adc_clkena );
+    CYGHWR_HAL_STM32_CLOCK_ENABLE( info->setup->tim_clkena );
+
     // Make sure ADC is powered on
     cr = CYGHWR_HAL_STM32_ADC_CR2_ADON;
     HAL_WRITE_UINT32(info->setup->adc_base + CYGHWR_HAL_STM32_ADC_CR2, cr);
@@ -470,7 +475,7 @@ stm32_adc_init_device(cyg_adc_device *de
     } while (cr & CYGHWR_HAL_STM32_ADC_CR2_CAL);
     
     // Power off ADC 
-    cr &= CYGHWR_HAL_STM32_ADC_CR2_ADON;
+    cr &= ~CYGHWR_HAL_STM32_ADC_CR2_ADON;
     HAL_WRITE_UINT32(info->setup->adc_base + CYGHWR_HAL_STM32_ADC_CR2, cr);
     
     // Enable external triggering and DMA
@@ -491,9 +496,15 @@ stm32_adc_init_device(cyg_adc_device *de
     // Enable generation of TRGO event
     cr = CYGHWR_HAL_STM32_TIM_CR2_MMS_UPDATE;
     HAL_WRITE_UINT32(info->setup->tim_base + CYGHWR_HAL_STM32_TIM_CR2, cr);
-    
+
 
     // Setup DMA channel
+    // Ensure that the DMA clocks are enabled.
+    if (info->setup->dma_base == CYGHWR_HAL_STM32_DMA1)
+      CYGHWR_HAL_STM32_CLOCK_ENABLE( CYGHWR_HAL_STM32_DMA1_CLOCK );
+    else
+      CYGHWR_HAL_STM32_CLOCK_ENABLE( CYGHWR_HAL_STM32_DMA2_CLOCK );
+
     HAL_WRITE_UINT32(info->setup->dma_base + 
                      CYGHWR_HAL_STM32_DMA_CPAR(info->setup->dma_channel),
                      info->setup->adc_base + CYGHWR_HAL_STM32_ADC_DR);
@@ -557,7 +568,7 @@ stm32_adc_update_sequence(cyg_adc_device
     cyg_uint32 sqr2 = 0;
     cyg_uint32 sqr3 = 0;
     
-    adc_diag("Updateing regular group\n");
+    adc_diag("Updating regular group\n");
     
     // Disable ADC
     HAL_READ_UINT32(info->setup->adc_base + CYGHWR_HAL_STM32_ADC_CR2, cr);
diff --git a/packages/devs/can/arm/at91/at91sam7/current/ChangeLog b/packages/devs/can/arm/at91/at91sam7/current/ChangeLog
--- a/packages/devs/can/arm/at91/at91sam7/current/ChangeLog
+++ b/packages/devs/can/arm/at91/at91sam7/current/ChangeLog
@@ -1,3 +1,9 @@
+2012-01-25  Bernard Fouché <bernard.fouche@kuantic.com>
+
+	* src/can_at91sam7.c: CYGNUM_CAN_EVENT_OVERRUN_RX_HW instead of
+	CYGNUM_CAN_EVENT_OVERRUN_RX. CYGNUM_CAN_MODE_LISTEN_ONLY_ENTER &
+	CYGNUM_CAN_MODE_LISTEN_ONLY_EXIT return -EINVAL. [ Bugzilla 1001453 ]
+
 2007-03-23  Uwe Kindler  <uwe_kindler@web.de>
 
 	* AT91SAM7 CAN driver package created
diff --git a/packages/devs/can/arm/at91/at91sam7/current/src/can_at91sam7.c b/packages/devs/can/arm/at91/at91sam7/current/src/can_at91sam7.c
--- a/packages/devs/can/arm/at91/at91sam7/current/src/can_at91sam7.c
+++ b/packages/devs/can/arm/at91/at91sam7/current/src/can_at91sam7.c
@@ -947,6 +947,8 @@ static Cyg_ErrNo at91sam7_can_set_config
                     case CYGNUM_CAN_MODE_START :   at91sam7_start_module(chan);        break;                       
                     case CYGNUM_CAN_MODE_STANDBY : at91sam7_enter_lowpower_mode(chan); break;
                     case CYGNUM_CAN_MODE_CONFIG :  at91sam7_enter_lowpower_mode(chan); break;
+                    case CYGNUM_CAN_MODE_LISTEN_ONLY_ENTER: return -EINVAL;
+                    case CYGNUM_CAN_MODE_LISTEN_ONLY_EXIT: return -EINVAL;
                 }
              }
              break; // case CYG_IO_SET_CONFIG_CAN_MODE :         
@@ -1132,7 +1134,7 @@ static bool at91sam7_can_getevent(can_ch
             pevent->flags |= CYGNUM_CAN_EVENT_RX; 
             if (msr & MSR_MSG_IGNORED)
             {
-                pevent->flags |= CYGNUM_CAN_EVENT_OVERRUN_RX;
+                pevent->flags |= CYGNUM_CAN_EVENT_OVERRUN_RX_HW;
             }
             
             //
diff --git a/packages/devs/can/arm/lpc2xxx/current/ChangeLog b/packages/devs/can/arm/lpc2xxx/current/ChangeLog
--- a/packages/devs/can/arm/lpc2xxx/current/ChangeLog
+++ b/packages/devs/can/arm/lpc2xxx/current/ChangeLog
@@ -1,3 +1,55 @@
+2013-09-17  Uwe Kindler <uwe_kindler@web.de>
+
+	* cdl/can_lpc2xxx.cdl: Add CYGHWR_DEVS_CAN_LPC2XXX_BUSOFF_WORKAROUND
+	to enable conditional Bus-Off reset mode workaround. [Bug 1001897]
+	* src/can_lpc2xxx.c: Add function lpc2xxx_reset_error_counters to
+	reset TX and RX error counters to certain values. Function
+	lpc2xxx_start_module now clears both error counters. Add some
+	LPC2XXX_DBG_PRINT statements to lpc2xxx_can_getevent function. Add
+	function lpc2xxx_print_status to ease printing status register
+	content. If a bus error condition occures (ICR_BUS_ERR) the function
+	lpc2xxx_can_getevent now clears the error counters to prevent error
+	ISR from blocking application and to support recovery from bus off
+	condition if option CYGHWR_DEVS_CAN_LPC2XXX_BUSOFF_WORKAROUND is
+	enabled.
+
+2013-09-11  Uwe Kindler <uwe_kindler@web.de>
+
+	* src/can_accfilt_lpc2xxx.c, src/can_lpc2xxx.c: Fix a compile issue of
+	the lpc2xxx driver that only occurs if support for extended 29-bit CAN
+	identifiers is enabled and support for message filtering is disabled.
+	[ Bugzilla 1001901 ]
+
+2013-08-29  Uwe Kindler <uwe_kindler@web.de>
+
+	* includes/can_lpc2xxx_baudrates.h: Added baudrate table for CAN clock
+	of 14.745600 MHz. [ Bugzilla 1001900 ]
+
+2013-06-24  Uwe Kindler <uwe_kindler@web.de>
+
+	* src/can_lpc2xxx.c: Add support for new config key
+	  CYG_IO_GET_CONFIG_CAN_ERR_COUNTERS.
+
+2013-05-06  Uwe Kindler <uwe_kindler@web.de>
+
+	* src/can_lpc2xxx.c: Changed return code for message filter
+	configuration to -ENOSPC if no filters are available to match
+	documentation change.
+
+2012-01-25  Bernard Fouché <bernard.fouche@kuantic.com>
+
+	* Changes made to support CAN IO package update:
+	* cdl/can_lpc2xxx.cdl: CYGOPT_DEVS_CAN_LPC2XXX_EXTENDED_CFG_KEYS
+	replaced by CYG_IO_SET_CONFIG_CAN_RANGE_FILTER.
+	* include/can_lpc2xxx.h: Commented out unused and not implemented
+	things.
+	* src/can_lpc2xxx.c: CYGNUM_CAN_EVENT_OVERRUN_RX_HW instead of
+	CYGNUM_CAN_EVENT_OVERRUN_RX. CYGOPT_DEVS_CAN_LPC2XXX_EXTENDED_CFG_KEYS
+	replaced by CYG_IO_SET_CONFIG_CAN_RANGE_FILTER. can_lpc2xxx.h not
+	required any more. CYGNUM_CAN_MODE_LISTEN_ONLY_ENTER &
+	CYGNUM_CAN_MODE_LISTEN_ONLY_EXIT return -EINVAL.
+	[ Bugzilla 1001453 ]
+
 2008-07-21  Uwe Kindler <uwe_kindler@web.de>
 	
 	* cdl/can_lpc2xxx.cdl: Added CYGOPT_DEVS_CAN_LPC2XXX_ALIE to make 
diff --git a/packages/devs/can/arm/lpc2xxx/current/cdl/can_lpc2xxx.cdl b/packages/devs/can/arm/lpc2xxx/current/cdl/can_lpc2xxx.cdl
--- a/packages/devs/can/arm/lpc2xxx/current/cdl/can_lpc2xxx.cdl
+++ b/packages/devs/can/arm/lpc2xxx/current/cdl/can_lpc2xxx.cdl
@@ -84,8 +84,8 @@ cdl_package CYGPKG_DEVS_CAN_LPC2XXX {
             the configuration key CYG_IO_SET_CONFIG_CAN_MSGBUF is not
             supported by this driver."
 
-            cdl_option CYGOPT_DEVS_CAN_LPC2XXX_EXTENDED_CFG_KEYS {
-                display       "Extended acceptance filtering"
+            cdl_option CYGOPT_DEVS_CAN_RANGE_FILTERING_CFG_KEYS {
+                display       "Range filtering"
                 flavor        bool
                 default_value 0
                 description   "
@@ -93,16 +93,12 @@ cdl_package CYGPKG_DEVS_CAN_LPC2XXX {
                     message filters for reception of single CAN
                     messages. The global LPC2xxx acceptance filter
                     supports not only single message filters but also
-                    message groups.  A message group is defined by a
+                    message ranges.  A message range is defined by a
                     lower bound CAN identifier and an upper bound CAN
                     identifier. The acceptance filter will accept all
                     messages within this range of CAN identifiers. The
                     acceptance filter supports a number of message
-                    groups for each CAN channel. The support of
-                    message filter groups is not conform to the
-                    standard API of the CAN I/O layer and should only
-                    be used for application where portability is not
-                    important."
+                    ranges for each CAN channel."
              }
              
          cdl_option CYGOPT_DEVS_CAN_LPC2XXX_LUT_ERR_SUPP {
@@ -333,6 +329,27 @@ cdl_package CYGPKG_DEVS_CAN_LPC2XXX {
             to the lowest priority 15, allowing a single write to 
             elevate the priority of an individual interrupt."
     }
+
+    # Enable this by default for "LPX22xx" parts only.
+    cdl_option CYGHWR_DEVS_CAN_LPC2XXX_BUSOFF_WORKAROUND {
+        display       "Bus-Off Reset Mode workaround"
+        flavor        bool
+        default_value { CYGHWR_HAL_ARM_LPC2XXX_VARIANT_VERSION == 2 }
+        description   "
+            If the Transmit Error counter contains 255 and another
+            error occurs, the CAN Controller is forced into a state
+            called Bus-Off.  In this state, the following register bits
+            and register values are set: BS (Bus Off Set) in CANxSR, BEI
+            (Bus Error Interrupt) and EI (Error Warning Interrupt) in
+            CANxICR, RM (Reset Mode) in CANxMOD, Transmit Error Counter
+            is set to 127, Receive Error Counter is cleared.
+            On some chips RM (Reset Mode) is not set and RX / TX error
+            counters are not cleared. This may lead to a permanent
+            re-calling of the Bus-Off error ISR which in turn may block
+            the application code from running.  If this workaround is
+            active, the Bus-Off error ISR sets RM (Reset Mode), clears
+            RX / TX error counters."
+    }
     
     cdl_option CYGPKG_DEVS_CAN_LPC2XXX_TESTS {
         display "CAN LPC2xxx device driver tests"
diff --git a/packages/devs/can/arm/lpc2xxx/current/include/can_lpc2xxx.h b/packages/devs/can/arm/lpc2xxx/current/include/can_lpc2xxx.h
--- a/packages/devs/can/arm/lpc2xxx/current/include/can_lpc2xxx.h
+++ b/packages/devs/can/arm/lpc2xxx/current/include/can_lpc2xxx.h
@@ -64,13 +64,14 @@
 //--------------------------------------------------------------------------
 // Message filter configuration
 //
-#define CYG_IO_SET_CONFIG_LPC2XXX_ACCFILT_GROUP  CYG_IO_SET_CONFIG_CAN_ABORT + 0x10 // add message filter group
+//#define CYG_IO_SET_CONFIG_LPC2XXX_ACCFILT_GROUP  CYG_IO_SET_CONFIG_CAN_ABORT + 0x10 // add message filter group
 
 
 //--------------------------------------------------------------------------
 // Mode setup of LPC2XXX
 //
-#define CYGNUM_CAN_MODE_LPC2XXX_LISTEN_ONLY       0x80 // set controller in listen only mode
+// NOT IMPLEMENTED!
+//#define CYGNUM_CAN_MODE_LPC2XXX_LISTEN_ONLY       0x80 // set controller in listen only mode
 
 
 //==========================================================================
@@ -79,12 +80,12 @@
 //
 // structure for configuration of message filter groups
 //
-typedef struct cyg_can_filtergroup_cfg_st
-{
-    cyg_can_id_type        ext;   
-    cyg_uint32             lower_id_bound;
-    cyg_uint32             upper_id_bound;
-} cyg_can_filtergroup_cfg;
+//typedef struct cyg_can_filtergroup_cfg_st
+//{
+//    cyg_can_id_type        ext;
+//    cyg_uint32             lower_id_bound;
+//    cyg_uint32             upper_id_bound;
+//} cyg_can_filtergroup_cfg;
 
 
 //---------------------------------------------------------------------------
diff --git a/packages/devs/can/arm/lpc2xxx/current/include/can_lpc2xxx_baudrates.h b/packages/devs/can/arm/lpc2xxx/current/include/can_lpc2xxx_baudrates.h
--- a/packages/devs/can/arm/lpc2xxx/current/include/can_lpc2xxx_baudrates.h
+++ b/packages/devs/can/arm/lpc2xxx/current/include/can_lpc2xxx_baudrates.h
@@ -185,6 +185,32 @@ static const cyg_uint32 lpc2xxx_br_tbl[]
 #define HAL_LPC2XXX_BAUD_TBL_DEFINED 1
 #endif // CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 12000000
 
+#if CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 14745600
+#warning "You can't get exactly the desired CAN bus speeds with the specified CAN clock of 14.7456 MHz"
+//
+// Table with register values for baudrates at peripheral clock of 14.7456 MHz
+// The clock of 14.7456 MHz is not suited for a good CAN bitrate timing because
+// you can't get exactly the desired CAN bus speed with the specified CAN
+// clock frequency. Be sure to check the error values behind the table entries.
+// Settings leading to speed deviations of more than 1.5% should be discarded.
+//
+static const cyg_uint32 lpc2xxx_br_tbl[] =
+{
+    //----------brp  tseg1 tseg2 sjw sam ------------
+    CAN_BR_TBL_ENTRY(58, 20, 2, 0, 1), // 10  kbaud - Timing Error  0.030%
+    CAN_BR_TBL_ENTRY(66,  8, 0, 0, 1), // 20  kbaud - Timing Error -0.038%
+    CAN_BR_TBL_ENTRY(13, 17, 1, 0, 1), // 50  kbaud - Timing Error -0.310%
+    CAN_BR_TBL_ENTRY( 6, 17, 1, 0, 1), // 100 kbaud - Timing Error -0.310%
+    CAN_BR_TBL_ENTRY(12,  6, 0, 0, 1), // 125 kbaud - Timing Error -0.825%
+    CAN_BR_TBL_ENTRY( 5,  7, 0, 0, 1), // 250 kbaud - Timing Error 1.696%
+    CAN_BR_TBL_ENTRY( 2,  7, 0, 0, 0), // 500 kbaud - Timing Error 1.696%
+    CAN_BR_TBL_ENTRY( 1,  6, 0, 0, 0), // 800 kbaud  - Timing Error -2.4%
+    CAN_BR_TBL_ENTRY( 0, 11, 1, 0, 0), // 1000 kbaud - Timing Error 1.696%
+    CAN_BR_TBL_ENTRY( 0,  0, 0, 0, 0), // Autobaud  - not supported
+};
+#define HAL_LPC2XXX_BAUD_TBL_DEFINED 1
+#endif // CYGNUM_HAL_ARM_LPC2XXX_CAN_CLK == 14745600
+
 
 //==========================================================================
 //                          BIT TIMING MACRO
diff --git a/packages/devs/can/arm/lpc2xxx/current/src/can_accfilt_lpc2xxx.c b/packages/devs/can/arm/lpc2xxx/current/src/can_accfilt_lpc2xxx.c
--- a/packages/devs/can/arm/lpc2xxx/current/src/can_accfilt_lpc2xxx.c
+++ b/packages/devs/can/arm/lpc2xxx/current/src/can_accfilt_lpc2xxx.c
@@ -771,7 +771,7 @@ static void lpc2xxx_can_accfilt_simple_r
 #ifdef CYGOPT_IO_CAN_STD_CAN_ID
     cyg_uint8                 std_address = 0;     // std group entry address
 #ifdef CYGOPT_IO_CAN_EXT_CAN_ID
-    cyg_uint8                 ext_address = lpc2xxx_global_can_info.init_cnt << 2;
+    cyg_uint8                 ext_address = LPC2XXX_INIT_CNT << 2;
 #endif
 #else
     cyg_uint8                 ext_address = 0;
diff --git a/packages/devs/can/arm/lpc2xxx/current/src/can_lpc2xxx.c b/packages/devs/can/arm/lpc2xxx/current/src/can_lpc2xxx.c
--- a/packages/devs/can/arm/lpc2xxx/current/src/can_lpc2xxx.c
+++ b/packages/devs/can/arm/lpc2xxx/current/src/can_lpc2xxx.c
@@ -70,7 +70,6 @@
 #include <cyg/io/io.h>
 #include <cyg/io/devtab.h>
 #include <cyg/io/can.h>
-#include <cyg/io/can_lpc2xxx.h>
 #include <cyg/io/can_lpc2xxx_baudrates.h>
 
 
@@ -539,8 +538,10 @@ typedef struct lpc2xxx_global_can_info_s
 
 #if CYGINT_IO_CAN_CHANNELS > 1
 #define LPC2XXX_GET_CAN_CHANNEL(_can_info_, _chan_no_) ((can_channel*)(_can_info_).active_channels[_chan_no_])
+#define LPC2XXX_INIT_CNT lpc2xxx_global_can_info.init_cnt
 #else
 #define LPC2XXX_GET_CAN_CHANNEL(_can_info_, _chan_no_) ((can_channel*)(_can_info_).active_channels[0])
+#define LPC2XXX_INIT_CNT 1
 #endif
 
 //
@@ -1167,7 +1168,7 @@ static Cyg_ErrNo lpc2xxx_can_config_msgb
                  //
                  if (!lpc2xxx_can_add_rx_filter(info, filter))
                  {
-                     return -EPERM;
+                     return -ENOSPC;
                  }
              }
              break; //CYGNUM_CAN_MSGBUF_RX_FILTER_ADD
@@ -1264,14 +1265,45 @@ static Cyg_ErrNo lpc2xxx_enter_lowpower_
 }
 
 
+#ifdef CYGHWR_DEVS_CAN_LPC2XXX_BUSOFF_WORKAROUND
+//===========================================================================
+// Reset error counters to the given values
+//===========================================================================
+static void lpc2xxx_reset_error_counters(lpc2xxx_can_info_t *info,
+    cyg_uint8 rx_errcnt, cyg_uint8 tx_errcnt)
+{
+    lsc_buf_t data;
+    cyg_uint32 regval;
+    HAL_READ_UINT32(CAN_CTRL_MOD(info), regval);
+
+    HAL_WRITE_UINT32(CAN_CTRL_MOD(info), CANMOD_RESET);
+    HAL_READ_UINT32(CAN_CTRL_GSR(info), data.dword);
+    data.bytes[2] = rx_errcnt; // reset RX error counter
+    data.bytes[3] = tx_errcnt; // reset TX error counter to 0
+    HAL_WRITE_UINT32(CAN_CTRL_GSR(info), data.dword);
+
+    HAL_WRITE_UINT32(CAN_CTRL_MOD(info), regval);
+}
+#endif // #ifdef CYGHWR_DEVS_CAN_LPC2XXX_BUSOFF_WORKAROUND
+
+
 //===========================================================================
 // Start CAN module - set CANMOD operational and enable all interrupts
 //===========================================================================
 static void lpc2xxx_start_module(can_channel *chan)
 {
+    lsc_buf_t data;
     cyg_uint32          regval;
     lpc2xxx_can_info_t *info = (lpc2xxx_can_info_t *)chan->dev_priv;
     
+    // before we start CAN module, we clear both error counters to start
+    // with a clean error counter state
+    HAL_WRITE_UINT32(CAN_CTRL_MOD(info), CANMOD_RESET);
+    HAL_READ_UINT32(CAN_CTRL_GSR(info), data.dword);
+    data.bytes[2] = 0; // reset RX error counter to 0
+    data.bytes[3] = 0; // reset TX error counter to 0
+    HAL_WRITE_UINT32(CAN_CTRL_GSR(info), data.dword);
+
     HAL_WRITE_UINT32(CAN_CTRL_MOD(info), CANMOD_OPERATIONAL);  
     //
     // The interrupt enable register is also modified by ISR and DSR so
@@ -1298,18 +1330,18 @@ static void lpc2xxx_enter_reset_mode(can
 }
 
 
-#ifdef CYGOPT_DEVS_CAN_LPC2XXX_EXTENDED_CFG_KEYS
+#ifdef CYGOPT_DEVS_CAN_RANGE_FILTERING_CFG_KEYS
 //===========================================================================
 // Add message filter group
 //===========================================================================
 static Cyg_ErrNo lpc2xxx_can_config_accfilt_group(can_channel *chan, const void* buf, cyg_uint32* len)
 {
     bool                     res;
-    cyg_can_filtergroup_cfg *filter_grp = (cyg_can_filtergroup_cfg *)buf;
+    cyg_can_filter_range_cfg *filter_grp = (cyg_can_filter_range_cfg *)buf;
     lpc2xxx_can_info_t      *info = (lpc2xxx_can_info_t *)chan->dev_priv; 
     
     
-    if (*len != sizeof(cyg_can_filtergroup_cfg))
+    if (*len != sizeof(cyg_can_filter_range_cfg))
     {
         return -EINVAL;
     }
@@ -1337,9 +1369,9 @@ static Cyg_ErrNo lpc2xxx_can_config_accf
 #ifdef CYGDBG_DEVS_CAN_LPC2XXX_DEBUG
     lpc2xxx_can_accfilt_dbg_dump();
 #endif        
-    return res ? ENOERR : -EPERM;
+    return res ? ENOERR : -ENOSPC;
 }
-#endif // CYGOPT_DEVS_CAN_LPC2XXX_EXTENDED_CFG_KEYS
+#endif // CYGOPT_DEVS_CAN_RANGE_FILTERING_CFG_KEYS
 
 
 //===========================================================================
@@ -1380,16 +1412,16 @@ static Cyg_ErrNo lpc2xxx_can_set_config(
              break;
 #endif // CYGOPT_IO_CAN_RUNTIME_MBOX_CFG
          
-#ifdef CYGOPT_DEVS_CAN_LPC2XXX_EXTENDED_CFG_KEYS
+#ifdef CYGOPT_DEVS_CAN_RANGE_FILTERING_CFG_KEYS
         //
         // Add message filter group to acceptance filter
         //
-        case CYG_IO_SET_CONFIG_LPC2XXX_ACCFILT_GROUP :
+        case CYG_IO_SET_CONFIG_CAN_RANGE_FILTER :
              {
                  return lpc2xxx_can_config_accfilt_group(chan, buf, len);
              }
              break;
-#endif // CYGOPT_DEVS_CAN_LPC2XXX_EXTENDED_CFG_KEYS 
+#endif // CYGOPT_DEVS_CAN_RANGE_FILTERING_CFG_KEYS
                         
         //
         // Change CAN state of CAN module
@@ -1418,6 +1450,8 @@ static Cyg_ErrNo lpc2xxx_can_set_config(
                     case CYGNUM_CAN_MODE_START :   lpc2xxx_start_module(chan);        break;                       
                     case CYGNUM_CAN_MODE_STANDBY : lpc2xxx_enter_lowpower_mode(chan); break;
                     case CYGNUM_CAN_MODE_CONFIG :  lpc2xxx_enter_reset_mode(chan);    break;
+                    case CYGNUM_CAN_MODE_LISTEN_ONLY_ENTER: return -EINVAL;
+                    case CYGNUM_CAN_MODE_LISTEN_ONLY_EXIT: return -EINVAL;
                 }
              }
              break; // case CYG_IO_SET_CONFIG_CAN_MODE :
@@ -1483,7 +1517,7 @@ static Cyg_ErrNo lpc2xxx_can_get_config(
 
         
         //
-        // Query hardware description of FlexCAN device driver
+        // Query hardware description of LPC2xxx CAN device driver
         //     
         case CYG_IO_GET_CONFIG_CAN_HDI :
              {
@@ -1496,6 +1530,20 @@ static Cyg_ErrNo lpc2xxx_can_get_config(
                                    | CYGNUM_CAN_HDI_FULLCAN;
              }
              break;
+
+        //
+        // Read error counters from device hardware
+        //
+        case CYG_IO_GET_CONFIG_CAN_ERR_COUNTERS :
+             {
+                 lsc_buf_t data;
+                 cyg_can_err_count_info* err_info = (cyg_can_err_count_info*)buf;
+                 HAL_READ_UINT32(CAN_CTRL_GSR(info), data.dword);
+                 err_info->rx_err_count = data.bytes[2];
+                 err_info->tx_err_count = data.bytes[3];
+                 *len = sizeof(cyg_can_err_count_info);
+             }
+             break;
              
         default :
             res = -EINVAL;
@@ -1583,6 +1631,27 @@ static bool lpc2xxx_can_putmsg(can_chann
 }
 
 
+#ifdef CYGDBG_DEVS_CAN_LPC2XXX_DEBUG
+//===========================================================================
+// Print status registers
+// This function is only here for debugging purposes to ease printing
+// of status register content
+//===========================================================================
+static void lpc2xxx_print_status(lpc2xxx_can_info_t *info)
+{
+    cyg_uint32 regval;
+    lsc_buf_t data;
+
+    HAL_READ_UINT32(CAN_CTRL_MOD(info), regval);
+    LPC2XXX_DBG_PRINT("CANREG_MOD: 0x%08x\n", regval);
+
+    HAL_READ_UINT32(CAN_CTRL_GSR(info), data.dword);
+    LPC2XXX_DBG_PRINT("RXERR: %d\n", data.bytes[2]);
+    LPC2XXX_DBG_PRINT("TXERR: %d\n", data.bytes[3]);
+}
+#endif
+
+
 //===========================================================================
 // Read event from device driver
 //===========================================================================
@@ -1645,7 +1714,7 @@ static bool lpc2xxx_can_getevent(can_cha
         HAL_READ_UINT32(CAN_CTRL_GSR(info), regval);
         if (regval & GSR_DATA_OVR)
         {
-            pevent->flags |= CYGNUM_CAN_EVENT_OVERRUN_RX;
+            pevent->flags |= CYGNUM_CAN_EVENT_OVERRUN_RX_HW;
             HAL_WRITE_UINT32(CAN_CTRL_CMR(info), CMR_CLEAR_DATA_OVR);
         }
     }
@@ -1683,15 +1752,18 @@ static bool lpc2xxx_can_getevent(can_cha
             {
                 pevent->flags |= CYGNUM_CAN_EVENT_WARNING_RX;  
                 info->state = CYGNUM_CAN_STATE_BUS_WARN;
+                LPC2XXX_DBG_PRINT("CYGNUM_CAN_EVENT_WARNING_RX counter (%d) (%p)\n", data.bytes[2], (void*) chan);
             }
             else if (data.bytes[3] >= 96)
             {
                 pevent->flags |= CYGNUM_CAN_EVENT_WARNING_TX;
                 info->state = CYGNUM_CAN_STATE_BUS_WARN;
+                LPC2XXX_DBG_PRINT("CYGNUM_CAN_EVENT_WARNING_TX counter (%d) (%p)\n", data.bytes[3], (void*) chan);
             }
             else
             {
                 info->state = CYGNUM_CAN_STATE_ACTIVE;
+                LPC2XXX_DBG_PRINT("CYGNUM_CAN_STATE_ACTIVE (%p)\n", (void*) chan);
             }
             LPC2XXX_DBG_PRINT("ICR_ERR_WARN (%p)\n", (void*) chan);
         }
@@ -1720,10 +1792,13 @@ static bool lpc2xxx_can_getevent(can_cha
             {
                 pevent->flags |= CYGNUM_CAN_EVENT_ERR_PASSIVE;    
                 info->state = CYGNUM_CAN_STATE_ERR_PASSIVE;
+                LPC2XXX_DBG_PRINT("CYGNUM_CAN_EVENT_ERR_PASSIVE (%p)\n", (void*) chan);
             }
             else
             {
+                pevent->flags |= CYGNUM_CAN_EVENT_ERR_ACTIVE;
                 info->state = CYGNUM_CAN_STATE_ACTIVE;    
+                LPC2XXX_DBG_PRINT("CYGNUM_CAN_EVENT_ERR_ACTIVE (%p)\n", (void*) chan);
             }
             LPC2XXX_DBG_PRINT("ICR_ERR_PASSIVE (%p)\n", (void*) chan);
         }
@@ -1741,13 +1816,30 @@ static bool lpc2xxx_can_getevent(can_cha
 #endif // CYGOPT_DEVS_CAN_LPC2XXX_ALIE
         
         //
-        // 1: Bus Error Interrupt -- this bit is set if the BEIE bit in CANIE is 1, and the CAN
-        // controller detects an error on the bus.
+        // 1: Bus Error Interrupt -- this bit is set if the BEIE bit in CANIE
+        // is 1, and the CAN controller detects an error on the bus.
         //
         if (event & ICR_BUS_ERR)
         {
             pevent->flags |= CYGNUM_CAN_EVENT_BUS_OFF; 
             LPC2XXX_DBG_PRINT("ICR_BUS_ERR (%p)\n", (void*) chan);
+
+#ifdef CYGHWR_DEVS_CAN_LPC2XXX_BUSOFF_WORKAROUND
+            //
+            // we do exactly here, what is written in the user manual
+            // 1. we go into reset mode
+            // 2. we clear the RX error counter and set the TX error counter
+            //    to 127
+            // 3. we clear the reset mode
+            // This ensures, that this ISR does not fire again and again and
+            // blocks the application while the bus off condition is active.
+            // Setting the TX error counter to 127 ensures that the controller
+            // is in TX error passive mode and that it does not flood the CAN
+            // bus with error messages. This makes it possible for the
+            // controller to properly recover from a bus off condition
+            //
+            lpc2xxx_reset_error_counters(info, 0, 127);
+#endif
         }
         
 #ifdef CYGOPT_DEVS_CAN_LPC2XXX_LUT_ERR_SUPP
@@ -1834,7 +1926,7 @@ static void lpc2xxx_can_tx_DSR(cyg_vecto
 {
     can_channel              *chan = (can_channel *)data;
     cyg_uint32                regval;
-    lpc2xxx_can_info_t       *info = (lpc2xxx_can_info_t *)chan->dev_priv;
+    CAN_DECLARE_INFO(chan);
     
     //
     // First read the ICR register to acknowledge all interrupts and
@@ -2008,8 +2100,8 @@ static void lpc2xxx_can_DSR(cyg_vector_t
     // Loop through all channels - we need to do this only if we have more
     // than one channel so we can optimize here for single channel
     //
+    cyg_uint8 i = 0;
 #if CYGINT_IO_CAN_CHANNELS > 1 
-    cyg_uint8 i = 0;     
     while (lpc2xxx_global_can_info.active_channels[i])
 #endif
     {
diff --git a/packages/devs/can/m68k/mcf52xx/current/ChangeLog b/packages/devs/can/m68k/mcf52xx/current/ChangeLog
--- a/packages/devs/can/m68k/mcf52xx/current/ChangeLog
+++ b/packages/devs/can/m68k/mcf52xx/current/ChangeLog
@@ -1,3 +1,9 @@
+2012-01-25  Bernard Fouché <bernard.fouche@kuantic.com>
+
+	* src/can_mcf52xx.c CYGNUM_CAN_EVENT_OVERRUN_RX_HW instead of
+	CYGNUM_CAN_EVENT_OVERRUN_RX. CYGNUM_CAN_MODE_LISTEN_ONLY_ENTER &
+	CYGNUM_CAN_MODE_LISTEN_ONLY_EXIT return -EINVAL.
+
 2007-03-23  Uwe Kindler  <uwe_kindler@web.de>
 
 	* cdl/can_mcf52xx.cdl Removed interfaces 
diff --git a/packages/devs/can/m68k/mcf52xx/current/src/can_mcf52xx.c b/packages/devs/can/m68k/mcf52xx/current/src/can_mcf52xx.c
--- a/packages/devs/can/m68k/mcf52xx/current/src/can_mcf52xx.c
+++ b/packages/devs/can/m68k/mcf52xx/current/src/can_mcf52xx.c
@@ -1224,6 +1224,10 @@ flexcan_set_config(can_channel *chan, cy
                     case CYGNUM_CAN_MODE_CONFIG : // stop FlexCAN modul for configuration
                     	 flexcan_stop_chip(chan);
                     	 break;
+
+                    case CYGNUM_CAN_MODE_LISTEN_ONLY_ENTER:
+                    case CYGNUM_CAN_MODE_LISTEN_ONLY_EXIT:
+                    	return -EINVAL;
                 }
              }
              break; // case CYG_IO_SET_CONFIG_CAN_MODE :         
@@ -1329,7 +1333,7 @@ static bool flexcan_is_no_self_tx(cyg_ca
         //
         if ((pmbox->ctrlstat_shadow & MBOX_RXCODE_OVERRUN) == MBOX_RXCODE_OVERRUN)
         {
-            pevent->flags |= CYGNUM_CAN_EVENT_OVERRUN_RX;
+            pevent->flags |= CYGNUM_CAN_EVENT_OVERRUN_RX_HW;
         }
 
         return true;
diff --git a/packages/devs/disk/generic/mmc/current/ChangeLog b/packages/devs/disk/generic/mmc/current/ChangeLog
--- a/packages/devs/disk/generic/mmc/current/ChangeLog
+++ b/packages/devs/disk/generic/mmc/current/ChangeLog
@@ -1,3 +1,19 @@
+2013-02-18  Ilija Stanislevik  <ilijas@siva.mk>
+
+	* src/mmc_spi.c: Add support for high capacity SD cards.
+	* include/mmc_protocol.h: Add definitions of V2 specific commands,
+	responses and card structure. [ Bugzilla 1001764 ]
+
+2013-02-21  Mike Jones  <mike@proclivis.com>
+
+	* src/mmc_spi.c (mmc_spi_check_for_disk): Modify DEBUG1 to to show
+	CHS in partition table.
+
+2012-05-04  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* src/mmc_spi.c (mmc_spi_send_init): Silence unused var warning.
+	Spotted by Ilija Kocho.
+
 2008-08-19  Andrew Lunn  <andrew.lunn@ascom.ch>
 
 	* cdl/devs_disk_mmc.cdl: Renamed the device to /dev/mmcdiskX so
diff --git a/packages/devs/disk/generic/mmc/current/include/mmc_protocol.h b/packages/devs/disk/generic/mmc/current/include/mmc_protocol.h
--- a/packages/devs/disk/generic/mmc/current/include/mmc_protocol.h
+++ b/packages/devs/disk/generic/mmc/current/include/mmc_protocol.h
@@ -102,9 +102,17 @@
 #define MMC_REQUEST_READ_OCR                0x3A
 #define MMC_REQUEST_CRC_ON_OFF              0x3B
 
+// SD V2.x specific commands
+#define SD_REQUEST_SEND_IF_COND             8
+#define SD_REQUEST_SD_SEND_OP_COND          41
+#define SD_REQUEST_APP_CMD                  55
+
 // Response formats are different for MMC vs. SPI mode, so are defined
 // in the appropriate source files.
 
+// SD V2.x specific responses
+#define SD_ARGUMENT_HCS                    ( 1 << 30 )
+
 // The CID register is generally treated as an opaque data structure
 // used only for unique identification of cards.
 typedef struct mmc_cid_register {
@@ -122,7 +130,7 @@ typedef struct mmc_cid_register {
                                                          ((_data_)->cid_data[13]))
 #define MMC_CID_REGISTER_MDT(_data_)                    ((_data_)->cid_data[14])
 #define MMC_CID_REGISTER_CRC(_data_)                    ((_data_)->cid_data[15] >> 1)
-                                                         
+
 
 // The CSD register is just lots of small bitfields. For now keep it
 // as an array of 16 bytes and provide macros to read the fields.
@@ -170,6 +178,19 @@ typedef struct mmc_csd_register {
 #define MMC_CSD_REGISTER_ECC(_data_)                    ((_data_)->csd_data[14] & 0x0003)
 #define MMC_CSD_REGISTER_CRC(_data_)                    (((_data_)->csd_data[15] & 0xFE) >> 1)
 
+// CSD V2.x structure
+#define SD_CSD_V2_REGISTER_C_SIZE(_data_)              ((((_data_)->csd_data[7] & 0x007f) << 16) |     \
+                                                          ((_data_)->csd_data[8] << 8)            |     \
+                                                          ((_data_)->csd_data[9] ))
+
+// OCR
+typedef struct sd_ocr_register {
+    cyg_uint8   ocr_data[4];
+} sd_ocr_register_t;
+
+#define SD_OCR_REGISTER_POWER_UP(_data_)               (((_data_)->ocr_data[0] & 0x80) >> 7)
+// CCS bit denotes Standard (0) or High/Extended (1) capacity
+#define SD_OCR_REGISTER_CCS(_data_)                    (((_data_)->ocr_data[0] & 0x40) >> 6)
 
 #endif //  ifdef CYGONCE_DEVS_DISK_MMC_PROTOCOL_H
 
diff --git a/packages/devs/disk/generic/mmc/current/src/mmc_spi.c b/packages/devs/disk/generic/mmc/current/src/mmc_spi.c
--- a/packages/devs/disk/generic/mmc/current/src/mmc_spi.c
+++ b/packages/devs/disk/generic/mmc/current/src/mmc_spi.c
@@ -113,6 +113,11 @@ cyg_bool    cyg_mmc_spi_polled = false;
 // ----------------------------------------------------------------------------
 // SPI-specific parts of the MMC protocol.
 //
+// Host supply voltage information
+#define MMC_SPI_VHS                         0x01  // 2.7 - 3.6V
+// Check pattern
+#define MMC_CMD8_CHECK_PATTERN              0xaa
+//
 // The main response byte. 0 indicates success, other bits
 // indicate various error conditions.
 #define MMC_REPLY_SUCCESS                   0x00
@@ -163,14 +168,20 @@ static cyg_uint8        mmc_spi_ff_data[
     memset(mmc_spi_ff_data, 0x00FF, 512);   \
     CYG_MACRO_END
 
+typedef enum sd_capacity_e {
+  STANDARD_CAPACITY,
+  HIGH_CAPACITY,
+  EXTENDED_CAPACITY
+} sd_capacity_t;
+
 // Details of a specific MMC card
 typedef struct cyg_mmc_spi_disk_info_t {
     cyg_spi_device*     mmc_spi_dev;
     cyg_uint32          mmc_saved_baudrate;
     cyg_uint32          mmc_block_count;
-#ifdef MMC_SPI_BACKGROUND_WRITES    
+#ifdef MMC_SPI_BACKGROUND_WRITES
     cyg_bool            mmc_writing;
-#endif    
+#endif
     cyg_bool            mmc_read_only;
     cyg_bool            mmc_connected;
     cyg_uint32          mmc_heads_per_cylinder;
@@ -178,6 +189,10 @@ typedef struct cyg_mmc_spi_disk_info_t {
     cyg_uint32          mmc_read_block_length;
     cyg_uint32          mmc_write_block_length;
     mmc_cid_register    mmc_id;
+    sd_ocr_register_t   sd_ocr;
+    cyg_uint32          sd_version;
+    sd_capacity_t       sd_capacity;
+    cyg_uint32          sd_csd_version;
 } cyg_mmc_spi_disk_info_t;
 
 // There is no need for a hardware-specific disk controller structure.
@@ -196,12 +211,12 @@ typedef struct cyg_mmc_spi_disk_info_t {
 static void
 mmc_spi_send_init(cyg_mmc_spi_disk_info_t* disk)
 {
-    cyg_spi_bus     *bus;
-    cyg_spi_device  *dev;
+#if DEBUG > 1
+    cyg_spi_device  *dev = disk->mmc_spi_dev;
+    cyg_spi_bus     *bus = dev->spi_bus;
+#endif
 
-    DEBUG2("mmc_spi_send_init(): dev pointer 0x%p, %d\n", disk->mmc_spi_dev, cyg_mmc_spi_polled );
-    dev = disk->mmc_spi_dev;
-    bus = dev->spi_bus;
+    DEBUG2("%s(): dev pointer 0x%p, %d\n", __FUNCTION__, disk->mmc_spi_dev, cyg_mmc_spi_polled );
     DEBUG2("                   : begin pointer %p\n", bus->spi_transaction_begin );
     cyg_spi_tick(disk->mmc_spi_dev, cyg_mmc_spi_polled, 10);
 }
@@ -218,7 +233,7 @@ mmc_spi_send_command_start(cyg_mmc_spi_d
     cyg_uint8       reply;
     int             i;
 
-#ifdef MMC_SPI_BACKGROUND_WRITES    
+#ifdef MMC_SPI_BACKGROUND_WRITES
     // If the last operation was a block write, those can take a while
     // to complete. Rather than wait at the end of the write(), do so
     // at the beginning of the next operation i.e. here. This also
@@ -233,25 +248,29 @@ mmc_spi_send_command_start(cyg_mmc_spi_d
     // the end, Either way, when the card sends a byte 0xff it should
     // be ready for the next command.
     if (disk->mmc_writing) {
-        DEBUG2("mmc_spi_send_command_start(): polling for completion of previous write\n");
+        DEBUG2("%s(): polling for completion of previous write\n", __FUNCTION__);
         disk->mmc_writing   = 0;
         response[0]    = 0x00;
         for (i = 0; (i < MMC_SPI_WRITE_BUSY_RETRIES) && (0x00FF != response[0]); i++) {
             cyg_spi_transfer(dev, cyg_mmc_spi_polled, 1, mmc_spi_ff_data, response);
         }
     }
-#endif    
-    
+#endif
+
     request[0]  = command | 0x0040;
     request[1]  = (arg >> 24) & 0x00FF;
     request[2]  = (arg >> 16) & 0x00FF;
     request[3]  = (arg >>  8) & 0x00FF;
     request[4]  = arg         & 0x00FF;
     // A CRC is needed for the go-idle-state command, because that
-    // command switches the device from MMC to SPI mode. That CRC is
-    // well-known. Once in SPI mode the card will not use CRCs by
-    // default.
-    request[5]  = (command == 0x00) ? 0x0095 : 0x00ff;
+    // command switches the device from MMC to SPI mode.  Also, a CRC
+    // is needed in case of CMD8. Here we take for granted that the
+    // host has 2.7-3.6V range and that the check pattern is 0xaa.
+    // These CRCs are well-known. Once in SPI mode the card will not
+    // use CRCs by default.
+    request[5]  = (command == 0x00) ? 0x0095 :
+                  (command == SD_REQUEST_SEND_IF_COND) ? 0x87 : 0xff;
+
     // There will need to be at least one extra byte transfer to get
     // the card's response, so send that straightaway. Extra
     // outgoing data like this should be 0xff so that the card
@@ -261,13 +280,13 @@ mmc_spi_send_command_start(cyg_mmc_spi_d
     // Lock the SPI bus. It remains locked until a subsequent call to
     // mmc_spi_end_command().
     cyg_spi_transaction_begin(dev);
-    
+
     // Transfer the whole command, and try to read the response back
     // immediately.
     cyg_spi_transaction_transfer(dev, cyg_mmc_spi_polled, 7, request, response, 0);
     DEBUG2("Sent command %02x %d: reply bytes %02x %02x %02x %02x %02x %02x %02x\n", command, arg, \
                 response[0], response[1], response[2], response[3], response[4], response[5], response[6]);
-    
+
     // The response will be a single byte with the top bit clear.
     // The remaining bits are error/status flags. If the command
     // involves an additional response then that will be handled
@@ -339,9 +358,9 @@ mmc_spi_read_data(cyg_mmc_spi_disk_info_
     for (i = 0; (i < retries) && (0x00FF == response[0]); i++) {
         cyg_spi_transaction_transfer(dev, cyg_mmc_spi_polled, 1, mmc_spi_ff_data, response, 0);
     }
-    
+
     if (MMC_DATA_TOKEN_SUCCESS != response[0]) {
-        DEBUG1("mmc_spi_read_data(): got error response %02x after %d iterations\n", response[0], i);
+        DEBUG1("%s(): got error response %02x after %d iterations\n", __FUNCTION__, response[0], i);
         return response[0];
     }
 
@@ -350,27 +369,100 @@ mmc_spi_read_data(cyg_mmc_spi_disk_info_
     cyg_spi_transaction_transfer(dev, cyg_mmc_spi_polled, count, mmc_spi_ff_data, buf, 0);
     // And the CRC, which can be ignored
     cyg_spi_transaction_transfer(dev, cyg_mmc_spi_polled, 2, mmc_spi_ff_data, response, 0);
-    DEBUG2("mmc_spi_read_data(): got data and CRC %02x %02x\n", response[0], response[1]);
-    
+    DEBUG2("%s(): got data and CRC %02x %02x\n", __FUNCTION__, response[0], response[1]);
+
     return MMC_DATA_TOKEN_SUCCESS;
 }
 
+// Determine if card complies with SD Physical Spec. Version 1.x or 2.x
+// If it is V1, also set information on capacity. MMC cards are recognized as SD V1.
+static Cyg_ErrNo
+mmc_spi_check_version(cyg_mmc_spi_disk_info_t* disk)
+{
+#define R7_RESPONSE_LENGTH 5
+  cyg_uint32  reply;
+  cyg_uint8   response[R7_RESPONSE_LENGTH];
+  cyg_spi_device* dev = disk->mmc_spi_dev;
+
+  disk->sd_version = 0;
+  reply = mmc_spi_send_command_start(disk, SD_REQUEST_SEND_IF_COND,
+          ( MMC_SPI_VHS << 8 ) + MMC_CMD8_CHECK_PATTERN);
+  DEBUG2("SEND_IF_COND (CMD8) reply: %02x\n", reply);
+
+  if (MMC_REPLY_ILLEGAL_COMMAND & reply) { // V1 cards do not understand CMD8
+    disk->sd_version = 1;
+    disk->sd_capacity = STANDARD_CAPACITY;
+    mmc_spi_end_command(disk);
+    return ENOERR;
+  }
+  disk->sd_version = 2;
+  if (~MMC_REPLY_IN_IDLE_STATE & reply) { // Anything other than idle state?
+    DEBUG1("SEND_IF_COND (CMD8) replies error %02x\n", reply);
+    mmc_spi_end_command(disk);
+    return -EIO;
+  }
+
+  // Card gives no error, so the response is R7. Take the rest of it.
+  cyg_spi_transaction_transfer(dev, cyg_mmc_spi_polled,
+      R7_RESPONSE_LENGTH, mmc_spi_ff_data, response, 0);
+  DEBUG2("%s(): R7: %02x %02x %02x %02x %02x.\n", __FUNCTION__,
+      response[0], response[1], response[2], response[3], response[4]);
+  if (0 == (MMC_SPI_VHS & response[2])) {
+    DEBUG1("%s(): card doesn't accept voltage %02x\n", __FUNCTION__, MMC_SPI_VHS);
+    mmc_spi_end_command(disk);
+    return -ENOTSUP;
+  }
+
+  mmc_spi_end_command(disk);
+  return ENOERR;
+}
+
+static Cyg_ErrNo
+mmc_spi_sd_check_v2_capacity_class(cyg_mmc_spi_disk_info_t* disk)
+{
+#define R3_RESPONSE_LENGTH 4
+  cyg_uint32  reply;
+  cyg_spi_device* dev = disk->mmc_spi_dev;
+
+  reply = mmc_spi_send_command_start(disk, MMC_REQUEST_READ_OCR, 0);
+  if (MMC_REPLY_SUCCESS != reply) {
+    DEBUG1("READ_OCR (CMD58) replies error %02x\n", reply);
+    mmc_spi_end_command(disk);
+    return -EIO;
+  }
+
+  // Card gives no error. Take the rest of response.
+  cyg_spi_transaction_transfer(dev, cyg_mmc_spi_polled,
+      R3_RESPONSE_LENGTH, mmc_spi_ff_data, disk->sd_ocr.ocr_data, 0);
+  DEBUG2("%s(): R3: %02x %02x %02x %02x.\n", __FUNCTION__,
+      disk->sd_ocr.ocr_data[0], disk->sd_ocr.ocr_data[1], disk->sd_ocr.ocr_data[2],
+      disk->sd_ocr.ocr_data[3]);
+  mmc_spi_end_command(disk);
+
+  disk->sd_capacity = (SD_OCR_REGISTER_CCS(&(disk->sd_ocr))) ?
+      HIGH_CAPACITY : STANDARD_CAPACITY ;
+
+  return ENOERR;
+}
+
 // Read one of the card registers, e.g. CSD or CID
 static Cyg_ErrNo
 mmc_spi_read_register(cyg_mmc_spi_disk_info_t* disk, cyg_uint32 command, cyg_uint8* buf, cyg_uint32 count)
 {
     cyg_uint32      reply;
-    
+
     reply = mmc_spi_send_command_start(disk, command, 0);
     if (MMC_REPLY_SUCCESS != reply) {
-        DEBUG1("mmc_spi_read_register(): unexpected response to command %02x, reply code %02x\n", command, reply);
+        DEBUG1("%s(): unexpected response to command %02x, reply code %02x\n",
+            __FUNCTION__, command, reply);
         mmc_spi_end_command(disk);
         return (0x00FF == reply) ? -ENODEV : -EIO;
     }
     reply = mmc_spi_read_data(disk, buf, count, false);
     mmc_spi_end_command(disk);
     if (MMC_DATA_TOKEN_SUCCESS != reply) {
-        DEBUG1("mmc_spi_read_register(): unexpected response to command %02x, expected 0x00FE data token, got %02x\n", command, reply);
+        DEBUG1("%s(): unexpected response to command %02x, expected 0x00FE data token, got %02x\n",
+            __FUNCTION__, command, reply);
         return -EIO;
     }
     return ENOERR;
@@ -384,12 +476,18 @@ static Cyg_ErrNo
 mmc_spi_read_disk_block(cyg_mmc_spi_disk_info_t* disk, cyg_uint8* buf, cyg_uint32 block, cyg_bool extra_delay)
 {
     cyg_uint32 reply;
-    
+
     // First the command itself.
-    DEBUG2("mmc_spi_read_disk_block(%d): sending command\n", block);
-    reply = mmc_spi_send_command_start(disk, MMC_REQUEST_READ_SINGLE_BLOCK, block * MMC_SPI_BLOCK_SIZE);
+    DEBUG2("%s(%d): sending command\n", __FUNCTION__, block);
+    if (STANDARD_CAPACITY == disk->sd_capacity) {
+      reply = mmc_spi_send_command_start(disk, MMC_REQUEST_READ_SINGLE_BLOCK, block * MMC_SPI_BLOCK_SIZE);
+    }
+    else {
+      reply = mmc_spi_send_command_start(disk, MMC_REQUEST_READ_SINGLE_BLOCK, block);
+    }
     if (MMC_REPLY_SUCCESS != reply) {
-        DEBUG1("mmc_spi_read_disk_block(%d): unexpected response to READ_SINGLE_BLOCK command, code %02x\n", block, reply);
+        DEBUG1("%s(%d): unexpected response to READ_SINGLE_BLOCK command, code %02x\n",
+            __FUNCTION__, block, reply);
         mmc_spi_end_command(disk);
         // A byte 0xFF indicates the card has been removed.
         if (0x00FF == reply) {
@@ -406,15 +504,16 @@ mmc_spi_read_disk_block(cyg_mmc_spi_disk
         // else is an I/O error.
         return -EIO;
     }
-    
+
     // Now read back the data block. That code can be shared with other read
     // operations, e.g. for retrieving registers.
-    DEBUG2("mmc_spi_read_disk_block(%d): reading data token/data/crc\n", block);
+    DEBUG2("%s(%d): reading data token/data/crc\n", __FUNCTION__, block);
     reply = mmc_spi_read_data(disk, buf, MMC_SPI_BLOCK_SIZE, extra_delay);
     mmc_spi_end_command(disk);
     if (MMC_DATA_TOKEN_SUCCESS != reply) {
-        DEBUG1("mmc_spi_read_disk_block(%d): failed to retrieve data, error token %02x\n", block, reply);
-        
+        DEBUG1("%s(%d): failed to retrieve data, error token %02x\n",
+            __FUNCTION__, block, reply);
+
         // Possibilities are password-locked, range error, ECC failure
         // if the raw data is corrupt, CC error for an internal card
         // error, or some other error. A byte 0xFF indicates the card
@@ -444,12 +543,18 @@ mmc_spi_write_disk_block(cyg_mmc_spi_dis
     cyg_uint32      reply;
     cyg_uint8       extra[4];
     int             i;
-   
+
     // First, send the command itself and get the initial response
-    DEBUG2("mmc_spi_write_disk_block(), sending command\n");
-    reply = mmc_spi_send_command_start(disk, MMC_REQUEST_WRITE_BLOCK, block * MMC_SPI_BLOCK_SIZE);
+    DEBUG2("%s(): sending command\n", __FUNCTION__);
+    if (STANDARD_CAPACITY == disk->sd_capacity) {
+      reply = mmc_spi_send_command_start(disk, MMC_REQUEST_WRITE_BLOCK, block * MMC_SPI_BLOCK_SIZE);
+    }
+    else {
+      reply = mmc_spi_send_command_start(disk, MMC_REQUEST_WRITE_BLOCK, block );
+    }
     if (MMC_REPLY_SUCCESS != reply) {
-        DEBUG1("mmc_spi_write_disk_block(): unexpected response to WRITE_BLOCK command, code %02x\n", reply);
+        DEBUG1("%s(): unexpected response to WRITE_BLOCK command, code %02x\n",
+            __FUNCTION__, reply);
         mmc_spi_end_command(disk);
         if (0x00FF == reply) {
             return -ENODEV;
@@ -469,7 +574,7 @@ mmc_spi_write_disk_block(cyg_mmc_spi_dis
     // The card is now expecting a data block. This consists of a single byte
     // 0x00FE, then the data itself, and a dummy CRC. The reply from the card
     // does not contain any useful information.
-    DEBUG2("mmc_spi_write_disk_block(): sending data token/data/crc\n");
+    DEBUG2("%s(): sending data token/data/crc\n", __FUNCTION__);
     extra[0]    = 0x00FE;
     cyg_spi_transaction_transfer(dev, cyg_mmc_spi_polled, 1, extra, (cyg_uint8*)0, 0);
     cyg_spi_transaction_transfer(dev, cyg_mmc_spi_polled, MMC_SPI_BLOCK_SIZE, buf, (cyg_uint8*)0, 0);
@@ -477,13 +582,13 @@ mmc_spi_write_disk_block(cyg_mmc_spi_dis
 
     // The card should respond immediately with a data response token.
     cyg_spi_transaction_transfer(dev, cyg_mmc_spi_polled, 1, mmc_spi_ff_data, extra, 0);
-    DEBUG2("mmc_spi_write_disk_block(): got data response token %02x\n", extra[0]);
+    DEBUG2("%s(): got data response token %02x\n", __FUNCTION__, extra[0]);
 
     // The bottom five bits contain the response. 00101 indicates success,
     // anything else is a CRC error. Everything else will have been checked
     // before the data got transferred.
     if (0x05 != (extra[0] & 0x1F)) {
-        DEBUG1("mmc_spi_write_disk_block(): invalid data response token %02x\n", extra[0]);
+        DEBUG1("%s(): invalid data response token %02x\n", __FUNCTION__, extra[0]);
         mmc_spi_end_command(disk);
         if (0x00FF == extra[0]) {
             return -ENODEV;
@@ -491,7 +596,7 @@ mmc_spi_write_disk_block(cyg_mmc_spi_dis
         return -EIO;
     }
 
-#ifdef MMC_SPI_BACKGROUND_WRITES    
+#ifdef MMC_SPI_BACKGROUND_WRITES
     // Mark the card as writing. The next operation will poll for completion.
     disk->mmc_writing   = true;
 #else
@@ -506,10 +611,10 @@ mmc_spi_write_disk_block(cyg_mmc_spi_dis
     extra[0]    = 0x00;
     for (i = 0; (i < MMC_SPI_WRITE_BUSY_RETRIES) && (0x00 == extra[0]); i++) {
         cyg_spi_transaction_transfer(dev, cyg_mmc_spi_polled, 1, mmc_spi_ff_data, extra, 0);
-        DEBUG2("mmc_spi_write_disk_block(), polling for ! busy, got response %02x\n", extra[0]);
+        DEBUG2("%s(): polling for ! busy, got response %02x\n", __FUNCTION__, extra[0]);
     }
 #endif
-    
+
     // Assume that the loop did in fact terminate.
     mmc_spi_end_command(disk);
     return ENOERR;
@@ -544,13 +649,13 @@ mmc_spi_check_for_disk(cyg_mmc_spi_disk_
     Cyg_ErrNo           code;
     mmc_csd_register    csd;
 
-#ifdef MMC_SPI_BACKGROUND_WRITES    
+#ifdef MMC_SPI_BACKGROUND_WRITES
     // If we have unmounted a disk and are remounting it, assume that
     // any writes have completed.
     disk->mmc_writing   = false;
-#endif    
+#endif
     reply               = 0x00ff;
-    
+
     for (i = 0; (i < MMC_SPI_GO_IDLE_RETRIES) && (0x01 != reply); i++) {
         // Allow platform HALs to provide additional initialization,
         // if the hardware needs it.
@@ -564,7 +669,7 @@ mmc_spi_check_for_disk(cyg_mmc_spi_disk_
         // been plugged in so there is no guarantee that any previous
         // init() calls or other traffic will have affected this card.
         mmc_spi_send_init(disk);
-    
+
         // Now set the card to idle state. This involves the GO_IDLE_STATE
         // command which will be accepted irrespective of whether the card is
         // currently in MMC or SPI mode, and will leave the card in SPI mode.
@@ -577,39 +682,74 @@ mmc_spi_check_for_disk(cyg_mmc_spi_disk_
         // inconvenient moment. Some dummy traffic is generated in the
         // hope that this gets things back in sync.
         if (0x01 != reply) {
-            DEBUG1("mmc_spi_check_for_disk(): loop %d, card did not enter idle state, code %02x\n", i, reply);
+            DEBUG1("%s(): loop %d, card did not enter idle state, code %02x\n",
+                __FUNCTION__, i, reply);
             if (0x0ff != reply) {
                 cyg_spi_transfer(dev, cyg_mmc_spi_polled, 128, mmc_spi_ff_data, (cyg_uint8*) 0);
             }
         }
     }
     if (0x0ff == reply) {
-        DEBUG1("mmc_spi_check_for_disk(): unable to get a response from the MMC card: code %02x\n", reply);
+        DEBUG1("%s(): unable to get a response from the MMC card: code %02x\n",
+            __FUNCTION__, reply);
         // A working card should be returning some data
         return -ENODEV;
     }
     if (0x01 != reply) {
-        DEBUG1("mmc_spi_check_for_disk(): card did not enter idle state, code %02x\n", reply);
+        DEBUG1("%s(): card did not enter idle state, code %02x\n", __FUNCTION__, reply);
         return -EIO;
     }
-    
+
+    // Determine if card complies with SD Physical Spec Version 1 or 2 or later.
+    reply = mmc_spi_check_version(disk);
+    if (ENOERR != reply) {
+      DEBUG1("%s(): can't determine card's version, code %02x\n", __FUNCTION__, reply);
+      return reply;
+    }
+    DEBUG2("%s(): card version %u\n", __FUNCTION__, disk->sd_version);
+
     // Next, wait for the card to initialize. This involves repeatedly
     // trying the SEND_OP_COND command until we get a reply that is
-    // not idle
+    // not idle.
     reply = 0x00ff;
     for (i = 0; (i < MMC_SPI_OP_COND_RETRIES) && ((0x00ff == reply) || (0 != (MMC_REPLY_IN_IDLE_STATE & reply))); i++) {
 #ifdef CYGPKG_DEVS_DISK_MMC_SPI_IDLE_RETRIES_WAIT
         CYGACC_CALL_IF_DELAY_US(CYGPKG_DEVS_DISK_MMC_SPI_IDLE_RETRIES_WAIT);
 #endif
-        reply = mmc_spi_send_command(disk, MMC_REQUEST_SEND_OP_COND, 0);
+        if (1 == disk->sd_version) {
+          reply = mmc_spi_send_command(disk, MMC_REQUEST_SEND_OP_COND, 0);
+        }
+        else {
+          reply = mmc_spi_send_command(disk, SD_REQUEST_APP_CMD, 0);
+          reply &= ~MMC_REPLY_IN_IDLE_STATE;
+          if (MMC_REPLY_SUCCESS != reply) {
+            DEBUG1("%s(): card doesn't accept APP_CMD: reply code %02x\n",
+                __FUNCTION__, reply);
+            return -EIO;
+          }
+          reply = mmc_spi_send_command(disk, SD_REQUEST_SD_SEND_OP_COND, SD_ARGUMENT_HCS);
+        }
     }
     if (MMC_REPLY_SUCCESS != reply) {
-        DEBUG1("mmc_spi_check_for_disk(): card has not entered operational state: reply code %02x\n", reply);
+        DEBUG1("%s(): card has not entered operational state: reply code %02x\n",
+            __FUNCTION__, reply);
         return (0x00FF == reply) ? -ENODEV : -EIO;
     }
 
     // The card has now generated sufficient responses that we don't need to
     // worry about a missing card anymore.
+    // In case of V2 card, determine its capacity class
+    if (2 == disk->sd_version) {
+      reply = mmc_spi_sd_check_v2_capacity_class(disk);
+      if (MMC_REPLY_SUCCESS != reply) {
+          DEBUG1("%s(): can't establish card's capacity class: reply code %02x\n",
+              __FUNCTION__, reply);
+          return -EIO;
+      }
+    }
+    DEBUG2("%s capacity card.\n", (STANDARD_CAPACITY == disk->sd_capacity) ?
+        "Standard" : (HIGH_CAPACITY == disk->sd_capacity) ? "High" : "Extended" );
+
     // Get hold of the card's unique ID and store it, to allow disk changes
     // to be detected.
     code = mmc_spi_read_register(disk, MMC_REQUEST_SEND_CID, (cyg_uint8*) &(disk->mmc_id), 16);
@@ -650,7 +790,9 @@ mmc_spi_check_for_disk(cyg_mmc_spi_disk_
            csd.csd_data[ 4], csd.csd_data[ 5], csd.csd_data[ 6], csd.csd_data[7],                           \
            csd.csd_data[ 8], csd.csd_data[ 9], csd.csd_data[10], csd.csd_data[11],                          \
            csd.csd_data[12], csd.csd_data[13], csd.csd_data[14], csd.csd_data[15]);
-    
+
+    disk->sd_csd_version = MMC_CSD_REGISTER_CSD_STRUCTURE(&csd) + 1 ;
+
     // Optionally dump the whole CSD register. This takes a lot of
     // code but gives a lot of info about the card. If the info looks
     // correct then we really are interacting properly with an MMC card.
@@ -668,6 +810,7 @@ mmc_spi_check_for_disk(cyg_mmc_spi_disk_
     } else {
         DEBUG1("        : Others/Unknown disk, FILE_FORMAT_GROUP 0, FILE_FORMAT 3\n");
     }
+
     {
         static const cyg_uint32 mantissa_speeds_x10[16]   = { 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 };
         static const cyg_uint32 exponent_speeds_div10[8]  = { 10000, 100000, 1000000, 10000000, 0, 0, 0, 0 };
@@ -676,11 +819,15 @@ mmc_spi_check_for_disk(cyg_mmc_spi_disk_
         speed /= 1000;
         DEBUG1("        : TRAN_SPEED %d %d -> %d kbit/s\n", \
                MMC_CSD_REGISTER_TRAN_SPEED_MANTISSA(&csd), MMC_CSD_REGISTER_TRAN_SPEED_EXPONENT(&csd), speed);
-    }        
+    }
+
     DEBUG1("        : READ_BL_LEN block length 2^%d (%d)\n", MMC_CSD_REGISTER_READ_BL_LEN(&csd), \
                 0x01 << MMC_CSD_REGISTER_READ_BL_LEN(&csd));
-    DEBUG1("        : C_SIZE %d, C_SIZE_MULT %d\n", MMC_CSD_REGISTER_C_SIZE(&csd), MMC_CSD_REGISTER_C_SIZE_MULT(&csd));
-    {
+
+    if (1 == disk->sd_csd_version) {
+      DEBUG1("        : C_SIZE %d, C_SIZE_MULT %d\n", \
+          MMC_CSD_REGISTER_C_SIZE(&csd), MMC_CSD_REGISTER_C_SIZE_MULT(&csd));
+      {
         cyg_uint32 block_len = 0x01 << MMC_CSD_REGISTER_READ_BL_LEN(&csd);
         cyg_uint32 mult      = 0x01 << (MMC_CSD_REGISTER_C_SIZE_MULT(&csd) + 2);
         cyg_uint32 size      = block_len * mult * (MMC_CSD_REGISTER_C_SIZE(&csd) + 1);
@@ -688,10 +835,22 @@ mmc_spi_check_for_disk(cyg_mmc_spi_disk_
         cyg_uint32 sizeM     =  sizeK / 1024;
         sizeK  -= (sizeM * 1024);
         DEBUG1("        : total card size %dM%dK\n", sizeM, sizeK);
+      }
     }
+    else {
+      DEBUG1("        : C_SIZE %d\n", SD_CSD_V2_REGISTER_C_SIZE(&csd));
+      {
+        cyg_uint32 sizeK     = 512 * (SD_CSD_V2_REGISTER_C_SIZE(&csd) + 1 ) ;
+        cyg_uint32 sizeM     =  sizeK / 1024;
+        sizeK  -= (sizeM * 1024);
+        DEBUG1("        : total card size %uM%uK\n", sizeM, sizeK);
+      }
+    }
+
     DEBUG1("        : WR_BL_LEN block length 2^%d (%d)\n", \
            MMC_CSD_REGISTER_WRITE_BL_LEN(&csd), 0x01 << MMC_CSD_REGISTER_WRITE_BL_LEN(&csd));
-    {
+
+    if ( 1 == disk->sd_csd_version) {
         static cyg_uint32 taac_mantissa_speeds_x10[16]   = { 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 };
         static cyg_uint32 taac_exponent_speeds_div10[8]  = { 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000 };
         cyg_uint32 taac_speed = taac_mantissa_speeds_x10[MMC_CSD_REGISTER_TAAC_MANTISSA(&csd)] *
@@ -700,15 +859,18 @@ mmc_spi_check_for_disk(cyg_mmc_spi_disk_
         DEBUG1("        : asynchronous read access time TAAC %d %d -> %d ns\n", \
                MMC_CSD_REGISTER_TAAC_MANTISSA(&csd), MMC_CSD_REGISTER_TAAC_EXPONENT(&csd), taac_speed);
     }
-    DEBUG1("        : synchronous read access time NSAC %d * 100 cycles\n", \
-           MMC_CSD_REGISTER_NSAC(&csd));
+    if ( 1 == disk->sd_csd_version) {
+      DEBUG1("        : synchronous read access time NSAC %d * 100 cycles\n", \
+             MMC_CSD_REGISTER_NSAC(&csd));
+    }
     DEBUG1("        : typical write program time %d * read time\n", MMC_CSD_REGISTER_R2W_FACTOR(&csd));
     DEBUG1("        : CCC command classes 0x%04x\n", MMC_CSD_REGISTER_CCC(&csd));
     DEBUG1("        : READ_BL_PARTIAL %d, WRITE_BLK_MISALIGN %d, READ_BLK_MISALIGN %d, DSR_IMP %d\n",   \
            MMC_CSD_REGISTER_READ_BL_PARTIAL(&csd), MMC_CSD_REGISTER_WRITE_BLK_MISALIGN(&csd),           \
            MMC_CSD_REGISTER_READ_BLK_MISALIGN(&csd), MMC_CSD_REGISTER_DSR_IMP(&csd));
     DEBUG1("        : WR_BL_PARTIAL %d\n", MMC_CSD_REGISTER_WR_BL_PARTIAL(&csd));
-    {
+
+    if ( 1 == disk->sd_csd_version) {
         static cyg_uint8    min_currents[8] = { 1, 1, 5, 10, 25, 35, 60, 100 };
         static cyg_uint8    max_currents[8] = { 1, 5, 10, 25, 35, 45, 80, 200 };
         DEBUG1("        : read current min %dmA, max %dmA\n",               \
@@ -718,26 +880,32 @@ mmc_spi_check_for_disk(cyg_mmc_spi_disk_
                     min_currents[MMC_CSD_REGISTER_VDD_W_CURR_MIN(&csd)],    \
                     max_currents[MMC_CSD_REGISTER_VDD_W_CURR_MAX(&csd)]);
     }
-    DEBUG1("        : erase sector size %d, erase group size %d\n", \
-           MMC_CSD_REGISTER_SECTOR_SIZE(&csd) + 1, MMC_CSD_REGISTER_ERASE_GRP_SIZE(&csd) + 1);
-    DEBUG1("        : write group enable %d, write group size %d\n", \
-           MMC_CSD_REGISTER_WR_GRP_ENABLE(&csd), MMC_CSD_REGISTER_WR_GRP_SIZE(&csd) + 1);
+    if ( 1 == disk->sd_csd_version) {
+      DEBUG1("        : erase sector size %d, erase group size %d\n", \
+             MMC_CSD_REGISTER_SECTOR_SIZE(&csd) + 1, MMC_CSD_REGISTER_ERASE_GRP_SIZE(&csd) + 1);
+      DEBUG1("        : write group enable %d, write group size %d\n", \
+             MMC_CSD_REGISTER_WR_GRP_ENABLE(&csd), MMC_CSD_REGISTER_WR_GRP_SIZE(&csd) + 1);
+    }
     DEBUG1("        : copy bit %d\n", MMC_CSD_REGISTER_COPY(&csd));
     DEBUG1("        : permanent write protect %d, temporary write protect %d\n", \
            MMC_CSD_REGISTER_PERM_WRITE_PROTECT(&csd), MMC_CSD_REGISTER_TMP_WRITE_PROTECT(&csd));
-    DEBUG1("        : ecc %d, default ecc %d\n", MMC_CSD_REGISTER_ECC(&csd), MMC_CSD_REGISTER_DEFAULT_ECC(&csd));
+    if ( 1 == disk->sd_csd_version) {
+      DEBUG1("        : ecc %d, default ecc %d\n", MMC_CSD_REGISTER_ECC(&csd), MMC_CSD_REGISTER_DEFAULT_ECC(&csd));
+    }
     DEBUG1("        : crc 0x%08x\n", MMC_CSD_REGISTER_CRC(&csd));
-#endif                
+#endif
 
-    // There is information available about the file format, e.g.
-    // partitioned vs. simple FAT. With the current version of the
-    // generic disk code this needs to be known statically, via
-    // the mbr field of the disk channel structure. If the card
-    // is inappropriately formatted, reject the mount request.
-    if ((0 != MMC_CSD_REGISTER_FILE_FORMAT_GROUP(&csd)) ||
-        (0 != MMC_CSD_REGISTER_FILE_FORMAT(&csd))) {
-        return -ENOTDIR;
-    }
+    if ( 1 == disk->sd_csd_version) {
+      // There is information available about the file format, e.g.
+      // partitioned vs. simple FAT. With the current version of the
+      // generic disk code this needs to be known statically, via
+      // the mbr field of the disk channel structure. If the card
+      // is inappropriately formatted, reject the mount request.
+      if ((0 != MMC_CSD_REGISTER_FILE_FORMAT_GROUP(&csd)) ||
+          (0 != MMC_CSD_REGISTER_FILE_FORMAT(&csd))) {
+          return -ENOTDIR;
+      }
+    } // According to Spec V3.01, host should not use these two fields in CSD V2 cards
 
     // Look for a write-protect bit (permanent or temporary), and set
     // the disk as read-only or read-write as appropriate. The
@@ -750,15 +918,20 @@ mmc_spi_check_for_disk(cyg_mmc_spi_disk_
         disk->mmc_read_only   = false;
     }
     DEBUG1("Disk read-only flag %d\n", disk->mmc_read_only);
-    
+
     // Calculate the disk size, primarily for assertion purposes.
-    // By design MMC cards are limited to 4GB, which still doesn't
-    // quite fit into 32 bits.
-    disk->mmc_block_count = (((cyg_uint64)(0x01 << MMC_CSD_REGISTER_READ_BL_LEN(&csd))) *
-                             ((cyg_uint64)(0x01 << (MMC_CSD_REGISTER_C_SIZE_MULT(&csd) + 2))) *
-                             ((cyg_uint64)(MMC_CSD_REGISTER_C_SIZE(&csd) + 1))) / (cyg_uint64)MMC_SPI_BLOCK_SIZE;
-    DEBUG1("Disk blockcount %d (0x%08x)\n", disk->mmc_block_count, disk->mmc_block_count);
-    
+    if ( 1 == disk->sd_csd_version) {
+      // By design MMC cards are limited to 4GB, which still doesn't
+      // quite fit into 32 bits.
+      disk->mmc_block_count = (((cyg_uint64)(0x01 << MMC_CSD_REGISTER_READ_BL_LEN(&csd))) *
+             ((cyg_uint64)(0x01 << (MMC_CSD_REGISTER_C_SIZE_MULT(&csd) + 2))) *
+             ((cyg_uint64)(MMC_CSD_REGISTER_C_SIZE(&csd) + 1))) / (cyg_uint64)MMC_SPI_BLOCK_SIZE;
+    }
+    else {
+      disk->mmc_block_count = 1024 * ( SD_CSD_V2_REGISTER_C_SIZE(&csd) + 1 ) ;
+    }
+    DEBUG1("Disk blockcount %u (0x%08x)\n", disk->mmc_block_count, disk->mmc_block_count);
+
     // Assume for now that the block length is 512 bytes. This is
     // probably a safe assumption since we have just got the card
     // initialized out of idle state. If it ever proves to be a problem
@@ -775,7 +948,7 @@ mmc_spi_check_for_disk(cyg_mmc_spi_disk_
         static const cyg_uint32 mantissa_speeds_x10[16]   = { 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 };
         static const cyg_uint32 exponent_speeds_div10[8]  = { 10000, 100000, 1000000, 10000000, 0, 0, 0, 0 };
         cyg_uint32 speed, len;
-        
+
         len = sizeof(cyg_uint32);
         if (cyg_spi_get_config(dev, CYG_IO_GET_CONFIG_SPI_CLOCKRATE, (void*) &disk->mmc_saved_baudrate, &len)) {
             DEBUG1("Failed to retrieve current SPI device clockrate\n");
@@ -801,7 +974,7 @@ mmc_spi_check_for_disk(cyg_mmc_spi_disk_
         cyg_uint8   data[MMC_SPI_BLOCK_SIZE];
         cyg_uint8*  partition;
         cyg_uint32  lba_first, lba_size, lba_end, head, cylinder, sector;
-        
+
         code = mmc_spi_read_disk_block(disk, data, 0, true);
         if (code) {
             mmc_spi_restore_baud(disk);
@@ -830,14 +1003,16 @@ mmc_spi_check_for_disk(cyg_mmc_spi_disk_
         // 0x1be, 0x1ce, 0x1de and 0x1ee. The numbers are stored little-endian
         for (i = 0; i < 4; i++) {
             partition = &(data[0x1be + (0x10 * i)]);
-            DEBUG1("Partition %d: boot %02x, first sector %02x %02x %02x, file system %02x, last sector %02x %02x %02x\n", i,   \
-                   partition[0], partition[1], partition[2], partition[3], partition[4], \
+            DEBUG1("Partition %d: boot %02x, first CHS %02x, last CHS %02x, first sector %02x %02x %02x, file system %02x, last sector %02x %02x %02x\n", i,   \
+		   partition[0], \
+		   ((partition[2] & 0xC0) << 2) | partition[3], ((partition[6] & 0xC0) << 2) | partition[7], \
+                   partition[1], partition[2], partition[3], partition[4], \
                    partition[5], partition[6], partition[7]);
             DEBUG1("           : first sector (linear) %02x %02x %02x %02x, sector count %02x %02x %02x %02x\n", \
                    partition[11], partition[10], partition[9], partition[8], \
                    partition[15], partition[14], partition[13], partition[12]);
         }
-#endif        
+#endif
         if ((0x0055 != data[0x1fe]) || (0x00aa != data[0x1ff])) {
             mmc_spi_restore_baud(disk);
             return -ENOTDIR;
@@ -867,7 +1042,7 @@ mmc_spi_check_for_disk(cyg_mmc_spi_disk_
         sector      = partition[6] & 0x3F;
         disk->mmc_heads_per_cylinder = ((((lba_end + 1) - sector) / disk->mmc_sectors_per_head) - head) / cylinder;
     }
-    
+
     return ENOERR;
 }
 
@@ -944,9 +1119,9 @@ mmc_spi_disk_lookup(struct cyg_devtab_en
     cyg_mmc_spi_disk_info_t*    disk    = (cyg_mmc_spi_disk_info_t*) chan->dev_priv;
     Cyg_ErrNo                   result;
 
-    DEBUG2("mmc_spi_disk_lookup(): target name=%s\n", name );
+    DEBUG2("%s(): target name=%s\n", __FUNCTION__, name );
     DEBUG2("                     : device name=%s dep_name=%s\n", tab[0]->name, tab[0]->dep_name );
-    DEBUG2("                     : sub    name=%s dep_name=%s\n", sub_tab->name, sub_tab->dep_name );
+//    DEBUG2("                     : sub    name=%s dep_name=%s\n", sub_tab->name, sub_tab->dep_name );
 
     if (disk->mmc_connected) {
         // There was a card plugged in last time we looked. Is it still there?
@@ -974,7 +1149,7 @@ mmc_spi_disk_lookup(struct cyg_devtab_en
         cyg_uint32          id_data;
         char*               where;
         int                 i;
-        
+
         // The world is consistent and the higher-level code does not
         // know anything about the current card, if any. Is there a
         // card?
@@ -1014,7 +1189,7 @@ mmc_spi_disk_lookup(struct cyg_devtab_en
             ident.firmware_rev[1] = id_data - 10 + 'A';
         }
         ident.firmware_rev[2]   = '\0';
-        
+
         // Model number. There is a six-byte product name in the CID.
         for (i = 0; i < 6; i++) {
             if ((disk->mmc_id.cid_data[i + 3] >= 0x20) && (disk->mmc_id.cid_data[i+3] <= 0x7E)) {
@@ -1056,9 +1231,10 @@ mmc_spi_disk_read(disk_channel* chan, vo
     cyg_uint32                  i;
     cyg_uint8*                  buf = (cyg_uint8*) buf_arg;
     Cyg_ErrNo                   code = ENOERR;
-    
-    DEBUG1("mmc_spi_disk_read(): first block %d, buf %p, len %lu blocks (%lu bytes)\n",
-           first_block, buf, (unsigned long)blocks, (unsigned long)blocks*512);
+
+    DEBUG1("%s(): first block %d, buf %p, len %lu blocks (%lu bytes)\n",
+        __FUNCTION__, first_block, buf, (unsigned long)blocks,
+        (unsigned long)blocks*512);
 
     if (! disk->mmc_connected) {
         return -ENODEV;
@@ -1082,8 +1258,9 @@ mmc_spi_disk_write(disk_channel* chan, c
     const cyg_uint8*            buf = (cyg_uint8*) buf_arg;
     Cyg_ErrNo                   code = ENOERR;
 
-    DEBUG1("mmc_spi_disk_write(): first block %d, buf %p, len %lu blocks (%lu bytes)\n",
-           first_block, buf, (unsigned long)blocks, (unsigned long)blocks*512);
+    DEBUG1("%s(): first block %d, buf %p, len %lu blocks (%lu bytes)\n",
+        __FUNCTION__, first_block, buf, (unsigned long)blocks,
+        (unsigned long)blocks*512);
 
     if (! disk->mmc_connected) {
         return -ENODEV;
@@ -1111,7 +1288,7 @@ mmc_spi_disk_get_config(disk_channel* ch
     CYG_UNUSED_PARAM(cyg_uint32, key);
     CYG_UNUSED_PARAM(const void*, buf);
     CYG_UNUSED_PARAM(cyg_uint32*, len);
-    
+
     return -EINVAL;
 }
 
@@ -1166,9 +1343,9 @@ DISK_FUNS(cyg_mmc_spi_disk_funs,
 
 static cyg_mmc_spi_disk_info_t cyg_mmc_spi_disk0_hwinfo = {
     .mmc_spi_dev        = &cyg_spi_mmc_dev0,
-#ifdef MMC_SPI_BACKGROUND_WRITES    
+#ifdef MMC_SPI_BACKGROUND_WRITES
     .mmc_writing        = 0,
-#endif    
+#endif
     .mmc_connected      = 0
 };
 
@@ -1183,7 +1360,7 @@ DISK_CHANNEL(cyg_mmc_spi_disk0_channel,
              true,                            /* MBR support */
              1                                /* Number of partitions supported */
              );
-             
+
 BLOCK_DEVTAB_ENTRY(cyg_mmc_spi_disk0_devtab_entry,
                    CYGDAT_DEVS_DISK_MMC_SPI_DISK0_NAME,
                    0,
diff --git a/packages/devs/disk/spi/freescale/dspi/mmc/current/ChangeLog b/packages/devs/disk/spi/freescale/dspi/mmc/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/disk/spi/freescale/dspi/mmc/current/ChangeLog
@@ -0,0 +1,29 @@
+2012-01-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/disk_mmc_freescale_dspi.cdl:
+	* src/freescale_dspi_mmc.c:
+	New package -- Disk driver fot Freescale DSPI
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/disk/spi/freescale/dspi/mmc/current/cdl/disk_mmc_freescale_dspi.cdl b/packages/devs/disk/spi/freescale/dspi/mmc/current/cdl/disk_mmc_freescale_dspi.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/disk/spi/freescale/dspi/mmc/current/cdl/disk_mmc_freescale_dspi.cdl
@@ -0,0 +1,92 @@
+##==========================================================================
+##
+##      disk_mmc_freescale_dspi.cdl
+##
+##      MMC/SD disk instatntiation for Freescale DSPI
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-12-27
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+cdl_package CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI {
+    display "MMC/SD disk device for Freescale DSPI"
+
+    active_if CYGPKG_DEVS_DISK_MMC_SPI
+    requires CYGPKG_DEVS_SPI_FREESCALE_DSPI
+    requires is_active(CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS)
+    requires is_active(CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS)
+
+
+    parent CYGPKG_DEVS_DISK_MMC_SPI
+    compile -library=libextras.a freescale_dspi_mmc.c
+
+    cdl_component CYGHWR_DEVS_MMC_SPI_INITIAL_SPEED {
+        display "Initial nominal SPI clock speed Hz"
+        flavor data
+        default_value 400000
+
+        cdl_option CYGHWR_DEVS_MMC_SPI_USE_DBR {
+            display "Use double baud rate"
+            flavor bool
+            default_value 1
+            description "
+                Double baud rate is a feature of Freescale DSPI
+                that may provide higher baud rates but duty the cycle may be
+                different than 50/50 depdent on scaler/prescaler setting
+                for achieved baud rate."
+        }
+    }
+
+    cdl_option CYGHWR_DEVS_DISK_MMC_CS_DELAY {
+        display "Nominal chip select delays (units)"
+        flavor data
+        legal_values { 1 1000 }
+        default_value 1
+    }
+
+    cdl_option CYGHWR_DEVS_DISK_MMC_CS_DELAY_UNIT {
+        display "Chip select delay unit (ns)"
+        flavor data
+        default_value 100
+        legal_values { 100 1000 }
+    }
+}
diff --git a/packages/devs/disk/spi/freescale/dspi/mmc/current/src/freescale_dspi_mmc.c b/packages/devs/disk/spi/freescale/dspi/mmc/current/src/freescale_dspi_mmc.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/disk/spi/freescale/dspi/mmc/current/src/freescale_dspi_mmc.c
@@ -0,0 +1,99 @@
+//==========================================================================
+//
+//      freescale_dspi_mmc.c
+//
+//      Cortex-M4 Freescale DSPI disk device
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2011-12-27
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#include <pkgconf/devs_disk_mmc_freescale_dspi.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/io/spi_freescale_dspi.h>
+
+#define MMC_SPI_FRAME_SIZE      8
+#define MMC_SPI_CLOCK_POL       0
+#define MMC_SPI_CLOCK_PHASE     0
+#define MMC_SPI_INITIAL_SPEED   CYGHWR_DEVS_MMC_SPI_INITIAL_SPEED
+#define MMC_SPI_CSUP_DL         CYGHWR_DEVS_DISK_MMC_CS_DELAY
+#define MMC_SPI_CSDW_DL         CYGHWR_DEVS_DISK_MMC_CS_DELAY
+#define MMC_SPI_TRBD_DL         CYGHWR_DEVS_DISK_MMC_CS_DELAY
+#define MMC_SPI_DELAY_UNIT      CYGHWR_DEVS_DISK_MMC_CS_DELAY_UNIT
+#ifdef CYGHWR_DEVS_MMC_SPI_USE_DBR
+# define MMC_SPI_DBR 1
+#else
+# define MMC_SPI_DBR 0
+#endif
+
+
+CYG_DEVS_SPI_FREESCALE_DSPI_DEVICE(
+    cyg_spi_mmc_dev0,             // Device name
+    CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS, // SPI bus
+    CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS,  // Dev num
+    MMC_SPI_FRAME_SIZE,           // Frame size
+    MMC_SPI_CLOCK_POL,            // Clock pol
+    MMC_SPI_CLOCK_PHASE,          // Clock phase
+    MMC_SPI_INITIAL_SPEED,        // Clock speed (Hz)
+    MMC_SPI_CSUP_DL,              // CS assert delay
+    MMC_SPI_CSDW_DL,              // CS negate delay
+    MMC_SPI_TRBD_DL,              // Delay between transfers
+    MMC_SPI_DELAY_UNIT,           // Delay unit (100 or 1000 ns)
+    MMC_SPI_DBR                   // Use double baud rate
+);
+
+//==========================================================================
+// EOF freescale_spi_disk.c
diff --git a/packages/devs/eth/arm/at91/current/ChangeLog b/packages/devs/eth/arm/at91/current/ChangeLog
--- a/packages/devs/eth/arm/at91/current/ChangeLog
+++ b/packages/devs/eth/arm/at91/current/ChangeLog
@@ -1,3 +1,8 @@
+2010-08-02  John Dallaway  <john@dallaway.org.uk>
+
+	* src/if_at91.c: Invert test for NSR IDLE bit. Issue reported by
+	Will Wagner.
+
 2007-04-08  Uwe Kindler  <uwe_kindler@web.de>
 
 	* cdl/at91_eth.cdl: Fixed typo. (Removed AT91RM9200 from
@@ -11,19 +16,19 @@ 2007-03-23  John Eigelaar  <jeigelaar@mw
 
 2007-01-17  John Eigelaar  <jeigelaar@mweb.co.za>
 
-	* src/if_at91.c * include/at91_eth.cdl: Working implementation
+	* src/if_at91.c, include/at91_eth.cdl: Working implementation
 	of a device driver for the AT91 EMAC device.
 
 2006-06-02  Andrew Lunn  <andrew.lunn@ascom.ch>
 
-	* src/if_at91.c * include/at91_eth.cdl: Partially implementation
+	* src/if_at91.c, include/at91_eth.cdl: Partially implementation
 	of a device driver for the AT91 EMAC device.
 
 //===========================================================================
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2006 Free Software Foundation, Inc.                        
+// Copyright (C) 2006, 2010 Free Software Foundation, Inc.                        
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/devs/eth/arm/at91/current/src/if_at91.c b/packages/devs/eth/arm/at91/current/src/if_at91.c
--- a/packages/devs/eth/arm/at91/current/src/if_at91.c
+++ b/packages/devs/eth/arm/at91/current/src/if_at91.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006, 2010 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -224,7 +224,7 @@ at91_write_phy(int reg_addr, int phy_add
 
    HAL_WRITE_UINT32(AT91_EMAC + AT91_EMAC_MAN, val);
 
-   /* Wait until IDLE bit in Network Status register is cleared */
+   /* Wait until IDLE bit in Network Status register is set */
    while (cnt < 1000000)
    {
       HAL_READ_UINT32((AT91_EMAC + AT91_EMAC_NSR), val);
@@ -252,11 +252,11 @@ at91_read_phy(int reg_addr, int phy_addr
 
 
    HAL_WRITE_UINT32(AT91_EMAC + AT91_EMAC_MAN, val);
-   /* Wait until IDLE bit in Network Status register is cleared */
+   /* Wait until IDLE bit in Network Status register is set */
    do
    {
       HAL_READ_UINT32((AT91_EMAC + AT91_EMAC_NSR), val);
-   }while(val & AT91_EMAC_NSR_IDLE);
+   }while(!(val & AT91_EMAC_NSR_IDLE));
    
    HAL_DELAY_US(50);
 
diff --git a/packages/devs/eth/arm/lpc2xxx/current/ChangeLog b/packages/devs/eth/arm/lpc2xxx/current/ChangeLog
--- a/packages/devs/eth/arm/lpc2xxx/current/ChangeLog
+++ b/packages/devs/eth/arm/lpc2xxx/current/ChangeLog
@@ -1,3 +1,13 @@
+2011-21-21  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/lpc2xxx_eth.cdl, src/if_lpc2xxx.c: Fixed interrupt priority.
+    [Bugzilla 1001432 ]
+
+2011-02-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/lpc2xxx_eth.cdl, src/if_lpc2xxx.c: Added support for
+	LPC17xx CPUs.
+
 2008-09-09  Uwe Kindler  <uwe_kindler@web.de>
 
 	* LPC2xxx ethernet driver package created
@@ -8,7 +18,7 @@ 2008-09-09  Uwe Kindler  <uwe_kindler@we
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.                        
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/devs/eth/arm/lpc2xxx/current/cdl/lpc2xxx_eth.cdl b/packages/devs/eth/arm/lpc2xxx/current/cdl/lpc2xxx_eth.cdl
--- a/packages/devs/eth/arm/lpc2xxx/current/cdl/lpc2xxx_eth.cdl
+++ b/packages/devs/eth/arm/lpc2xxx/current/cdl/lpc2xxx_eth.cdl
@@ -40,6 +40,7 @@
 ######DESCRIPTIONBEGIN####
 #
 # Author(s):    Uwe Kindler
+# Contributors: ilijak
 # Date:         2008-08-05
 #
 #####DESCRIPTIONEND####
@@ -80,19 +81,29 @@ cdl_package CYGPKG_DEVS_ETH_ARM_LPC2XXX 
              debug messages while an application is loaded and run via GDB
              TCP/IP connection"
     }
-    
+
+    # For backward compatibility with LPC24xx platforms
+    # that do not have CYGNUM_HAL_IRQ_PRIORITY_MIN defined.
+    cdl_option CYGNUM_DEVS_ETH_IRQ_PRIORITY_MIN {
+        display       "Interrupt priority levels"
+        flavor        data
+        calculated    { CYGNUM_HAL_IRQ_PRIORITY_MIN ? CYGNUM_HAL_IRQ_PRIORITY_MIN : 15 }
+        description   "
+            For backward compatibility with LPC 24XX plarforms that do
+            not have CYGNUM_HAL_IRQ_PRIORITY_MIN defined."
+    }
+
     cdl_option CYGPKG_DEVS_ETH_ARM_LPC2XXX_INTPRIO {
         display       "Interrupt priority"
         flavor        data
-        legal_values  0 to 15
-        default_value 15
+        legal_values  0 to CYGNUM_DEVS_ETH_IRQ_PRIORITY_MIN
+        default_value CYGNUM_DEVS_ETH_IRQ_PRIORITY_MIN
         description   "
-            This option selects the interrupt priority for the EMAC interrupts. 
-            There are 16 priority levels corresponding to the values 0 through 
-            15 decimal, of which 15 is the lowest priority. The reset value of 
-            these registers defaults all interrupts to the lowest priority, 
-            allowing a single write to elevate the priority of an 
-            individual interrupt."
+            This option selects the interrupt priority for the EMAC
+            interrupts.  The reset value
+            of these registers defaults all interrupts to the lowest
+            priority, allowing a single write to elevate the priority
+            of an individual interrupt."
     }
 
     cdl_option CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS {
diff --git a/packages/devs/eth/arm/lpc2xxx/current/src/if_lpc2xxx.c b/packages/devs/eth/arm/lpc2xxx/current/src/if_lpc2xxx.c
--- a/packages/devs/eth/arm/lpc2xxx/current/src/if_lpc2xxx.c
+++ b/packages/devs/eth/arm/lpc2xxx/current/src/if_lpc2xxx.c
@@ -38,7 +38,7 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):    Uwe Kindler
-// Contributors:
+// Contributors: ilijak
 // Date:         2008-08-10
 // Description:  Hardware driver for LPC2xxx on-chip EMAC peripheral
 //
@@ -254,9 +254,17 @@
 //===========================================================================
 //                ETHERNET RAM AND DMA CONFIGURATION
 //===========================================================================
-#define EMAC_RAM_BASE          0x7FE00000
-#define EMAC_RAM_SIZE          0x00004000
-#define EMAC_BLOCK_SIZE        0x600
+#ifdef CYGHWR_HAL_LPC_EMAC_RAM_AHB
+# include <cyg/infra/cyg_type.h>
+# define EMAC_RAM_MEM_SECTION   CYGBLD_ATTRIB_SECTION(CYGHWR_HAL_LPC_EMAC_MEM_SECTION)
+# define EMAC_RAM_BASE          (&emac_ahb_ram)
+# define EMAC_RAM_SIZE          sizeof(emac_ahb_ram)
+# define EMAC_BLOCK_SIZE        CYGHWR_HAL_LPC_EMAC_BLOCK_SIZE
+#else // Backward compatibility
+# define EMAC_RAM_BASE          0x7FE00000
+# define EMAC_RAM_SIZE          0x00004000
+# define EMAC_BLOCK_SIZE        0x600
+#endif // CYGHWR_HAL_LPC_EMAC_RAM_AHB
 
 //
 // EMAC Descriptor TX and RX Control fields
@@ -345,6 +353,9 @@ typedef struct eth_ram_cfg_st
     volatile eth_buf_t    rx_buf[CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS];
 } eth_ram_cfg_t;
 
+#ifdef CYGHWR_HAL_LPC_EMAC_RAM_AHB
+volatile static eth_ram_cfg_t emac_ahb_ram EMAC_RAM_MEM_SECTION;
+#endif
 
 #if CYGPKG_DEVS_ETH_ARM_LPC2XXX_DEBUG_LEVEL < 3
 #if CYGPKG_DEVS_ETH_ARM_LPC2XXX_DEBUG_LEVEL > 0
diff --git a/packages/devs/eth/cortexm/a2f200_eval/current/ChangeLog b/packages/devs/eth/cortexm/a2f200_eval/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/cortexm/a2f200_eval/current/ChangeLog
@@ -0,0 +1,31 @@
+
+2011-05-07  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* include/a2fxxx_eval_eth.inl: 
+	* cdl/a2fxxx_eval.cdl
+	 New package --Ethernet driver for Actel Smartfusion Evaluation Board
+    [Bugzilla 1001291]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/eth/cortexm/a2f200_eval/current/cdl/a2f200_eval.cdl b/packages/devs/eth/cortexm/a2f200_eval/current/cdl/a2f200_eval.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/cortexm/a2f200_eval/current/cdl/a2f200_eval.cdl
@@ -0,0 +1,121 @@
+# ==========================================================================
+#
+#      a2f200_eval.cdl
+#
+#      Ethernet driver specifics for Actel Smartfusion (A2F200) board
+#
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):    ccoutand
+# Contributors:
+# Date:         2011-05-04
+# Purpose:
+# Description:  Ethernet driver specifics for Actel Smartfusion (A2F200)
+#               board
+#
+#####DESCRIPTIONEND####
+#
+# ==========================================================================
+
+
+cdl_package CYGPKG_DEVS_ETH_CORTEXM_A2F200_EVAL {
+    display       "Actel Smartfusion (A2F200) kit Ethernet support"
+    description   "
+        Ethernet driver specifics for Actel Smartfusion (A2F200) board"
+
+    parent        CYGPKG_IO_ETH_DRIVERS
+    active_if     CYGPKG_IO_ETH_DRIVERS
+    active_if     CYGPKG_HAL_CORTEXM
+    active_if     CYGPKG_HAL_CORTEXM_A2FXXX
+
+    requires      CYGPKG_DEVS_ETH_CORTEXM_A2FXXX
+
+    include_dir   cyg/io
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGDAT_DEVS_CORTEXM_A2FXXX_ETH_CDL <pkgconf/devs_eth_cortexm_a2f200_eval.h>"
+        puts $::cdl_system_header "#define CYGDAT_DEVS_CORTEXM_A2FXXX_ETH_INL <cyg/io/a2f200_eval_eth.inl>"
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_CORTEXM_A2F200_EVAL_ETH0 {
+        display       "Actel Smartfusion (A2F200) Ethernet port 0 driver"
+        flavor        bool
+        default_value 1
+        description   "
+            This option includes the Ethernet device driver on the
+            Actel Smartfusion (A2F200) motherboard."
+
+        implements CYGHWR_NET_DRIVERS
+        implements CYGHWR_NET_DRIVER_ETH0
+
+        cdl_option CYGDAT_DEVS_ETH_CORTEXM_A2F200_EVAL_ETH0_NAME {
+            display       "Device name for the Ethernet port 0 driver"
+            flavor        data
+            default_value {"\"eth0\""}
+            description   "
+                This option sets the name of the Ethernet device for the
+                Ethernet port 0."
+        }
+
+        cdl_option CYGDAT_DEVS_ETH_CORTEXM_A2F200_EVAL_ETH0_PHY_ADDRESS {
+            display       "Ethernet PHY address of the Ethernet port 0 driver"
+            flavor        data
+            default_value 0
+            description   "
+                This option sets the Ethernet PHY address of the Ethernet device for the
+                Ethernet port 0."
+        }
+
+        cdl_component CYGSEM_DEVS_ETH_CORTEXM_A2F200_EVAL_ETH0_SET_ESA {
+            display       "Set the Ethernet station address"
+            flavor        bool
+            default_value !CYGPKG_DEVS_ETH_TSEC_ETH_REDBOOT_HOLDS_ESA
+            description   "Enabling this option will allow the Ethernet
+            station address to be forced to the value set by the
+            configuration.  This may be required if the hardware does
+            not include a serial EEPROM for the ESA, and if RedBoot's
+            flash configuration support is not available."
+
+            cdl_option CYGDAT_DEVS_ETH_CORTEXM_A2F200_EVAL_ETH0_ESA {
+                display       "The Ethernet station address"
+                flavor        data
+                default_value {"{0x00, 0x20, 0x0E, 0x10, 0x39, 0x89}"}
+                description   "The Ethernet station address"
+            }
+        }
+    }
+
+}
diff --git a/packages/devs/eth/cortexm/a2f200_eval/current/include/a2f200_eval_eth.inl b/packages/devs/eth/cortexm/a2f200_eval/current/include/a2f200_eval_eth.inl
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/cortexm/a2f200_eval/current/include/a2f200_eval_eth.inl
@@ -0,0 +1,129 @@
+//==========================================================================
+//
+//      a2f200_eval.inl
+//
+//      Ethernet driver specifics for Actel Smartfusion (A2F200) board
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System. 
+// Copyright (C) 2011 Free Software Foundation, Inc. 
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors:
+// Date:         2011-05-04
+// Purpose:
+// Description:  Ethernet driver specifics for Actel Smartfusion (A2F200) board
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+
+#ifndef CYGONCE_DEVS_A2F200_EVAL_ETH_INL
+#define CYGONCE_DEVS_A2F200_EVAL_ETH_INL
+
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/var_io.h>
+
+// Make sure packet size is multiple of words
+#define CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_ALIGN_BUFSIZE_RX \
+            ((CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_BUFSIZE_RX + 0x00000003) & (0xfffffffc))
+
+#define CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_ALIGN_BUFSIZE_TX \
+            ((CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_BUFSIZE_TX + 0x00000003) & (0xfffffffc))
+
+#define RxBUFSIZE ( CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_RxNUM*CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_ALIGN_BUFSIZE_RX )
+#define TxBUFSIZE ( CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_TxNUM*CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_ALIGN_BUFSIZE_TX )
+
+#ifdef CYGPKG_DEVS_ETH_CORTEXM_A2F200_EVAL_ETH0
+
+#ifdef CYGPKG_DEVS_ETH_PHY
+ETH_PHY_REG_LEVEL_ACCESS_FUNS(eth0_phy,
+                              a2fxxx_phy_init,
+                              NULL,
+                              a2fxxx_mdio_write,
+                              a2fxxx_mdio_read);
+#endif
+
+// Declare TX / RX buffers
+static cyg_uint32 a2fxxx_eth0_rxbufs[ RxBUFSIZE / 4 ];
+static cyg_uint32 a2fxxx_eth0_txbufs[ TxBUFSIZE / 4 ];
+
+// Declare BDs
+static struct a2fxxx_bd
+    a2fxxx_eth0_rxring[CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_RxNUM];
+static struct a2fxxx_bd
+    a2fxxx_eth0_txring[CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_TxNUM];
+
+static struct a2fxxx_eth_info a2fxxx_eth0_info = {
+#ifdef CYGDAT_DEVS_ETH_CORTEXM_A2F200_EVAL_ETH0_ESA
+    .mac_address = CYGDAT_DEVS_ETH_CORTEXM_A2F200_EVAL_ETH0_ESA,
+#endif
+    .base        = CYGHWR_HAL_A2FXXX_MAC,
+    .base_bb     = CYGHWR_HAL_A2FXXX_MAC_BB,
+    .if_num      = 0,
+    .init_rxbufs = (cyg_uint8 *) &a2fxxx_eth0_rxbufs[0],
+    .init_txbufs = (cyg_uint8 *) &a2fxxx_eth0_txbufs[0],
+    .init_rxring = &a2fxxx_eth0_rxring[0],
+    .init_txring = &a2fxxx_eth0_txring[0],
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    .vector = CYGNUM_HAL_INTERRUPT_MAC0,
+#endif
+#ifdef CYGPKG_DEVS_ETH_PHY
+    .phy = &eth0_phy,
+#endif
+};
+
+ETH_DRV_SC(a2fxxx_eth0_sc,
+           &a2fxxx_eth0_info,
+           CYGDAT_DEVS_ETH_CORTEXM_A2F200_EVAL_ETH0_NAME,
+           a2fxxx_eth_start,
+           a2fxxx_eth_stop,
+           a2fxxx_eth_control,
+           a2fxxx_eth_can_send,
+           a2fxxx_eth_send,
+           a2fxxx_eth_recv,
+           a2fxxx_eth_deliver,
+           a2fxxx_eth_poll,
+           a2fxxx_eth_int_vector);
+
+NETDEVTAB_ENTRY(a2fxxx_netdev0,
+                "a2fxxx_" CYGDAT_DEVS_ETH_CORTEXM_A2F200_EVAL_ETH0_NAME,
+                a2fxxx_eth_init,
+                &a2fxxx_eth0_sc);
+
+#endif// CYGPKG_DEVS_ETH_CORTEXM_A2F200_EVAL_ETH0
+
+#endif
diff --git a/packages/devs/eth/cortexm/a2fxxx/current/ChangeLog b/packages/devs/eth/cortexm/a2fxxx/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/cortexm/a2fxxx/current/ChangeLog
@@ -0,0 +1,31 @@
+
+2011-05-07  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* src/if_a2fxxx.c: 
+	* cdl/a2fxxx_eth.cdl
+	New package -- Ethernet driver for Actel Smartfusion
+    [Bugzilla 1001291]
+    
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/eth/cortexm/a2fxxx/current/cdl/a2fxxx_eth.cdl b/packages/devs/eth/cortexm/a2fxxx/current/cdl/a2fxxx_eth.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/cortexm/a2fxxx/current/cdl/a2fxxx_eth.cdl
@@ -0,0 +1,152 @@
+#==========================================================================
+#
+#      a2fxxx_eth.cdl
+#
+#      Ethernet drivers for Actel AF2xxx Controller
+#
+#==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+#==========================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):    ccoutand
+# Contributors:
+# Date:         2011-05-04
+# Purpose:
+# Description:
+#
+#####DESCRIPTIONEND####
+#
+#========================================================================*/
+
+cdl_package CYGPKG_DEVS_ETH_CORTEXM_A2FXXX {
+    display       "Actel Smartfusion Ethernet driver"
+    parent        CYGPKG_IO_ETH_DRIVERS
+    active_if     CYGPKG_IO_ETH_DRIVERS
+    active_if     CYGPKG_HAL_CORTEXM_A2FXXX
+
+    implements    CYGHWR_NET_DRIVERS
+    implements    CYGHWR_NET_DRIVER_ETH0
+
+    include_dir   net
+    description   "
+       Ethernet drivers for Actel AF2xxx Controller."
+
+    compile       -library=libextras.a if_a2fxxx.c
+
+    cdl_option CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_PROMISCUOUS {
+        display         "Promiscuous Mode"
+        flavor          bool
+        default_value   0
+        description     "
+           Selecting this option will set the Ethernet MAC in promiscuous mode, all Ethernet
+           packets will be delivered to the application layer."
+    }
+
+    cdl_option CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_CHATTER {
+        display         "Display status messages during Ethernet operations"
+        flavor          bool
+        default_value   0
+        description     "
+           Selecting this option will cause the Ethernet driver to print status
+           messages as various Ethernet operations are undertaken."
+    }
+
+    cdl_option CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_ISR_PRIORITY {
+        display       "Ethernet interrupt ISR priority"
+        flavor        data
+        default_value CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_ISR_SP
+        description   "
+              Set the Ethernet controller ISR priority."
+    }
+
+    cdl_option CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_STATS {
+        display         "Maintain statistics at the MAC layer"
+        flavor          bool
+        default_value   0
+        description     "
+           Selecting this option will cause the Ethernet driver to accumulate statistics
+           provided from the MAC layer."
+    }
+
+    cdl_option CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_BUFSIZE_TX {
+        display       "Buffer size"
+        flavor        data
+        default_value 1536
+        description   "
+            This option specifies the size of the internal transmit buffers used
+            for the Actel A2Fxxx/Ethernet device."
+    }
+
+    cdl_option CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_BUFSIZE_RX {
+        display       "Buffer size"
+        flavor        data
+        default_value 1536
+        description   "
+            This option specifies the size of the internal receive buffers used
+            for the Actel A2Fxxx/Ethernet device."
+    }
+
+    cdl_option CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_TxNUM {
+        display       "Number of output buffers"
+        flavor        data
+        legal_values  2 to 8
+        default_value 4
+        description   "
+            This option specifies the number of output buffer packets
+            to be used for the Actel A2Fxxx/Ethernet device."
+    }
+
+    cdl_option CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_RxNUM {
+        display       "Number of input buffers"
+        flavor        data
+        legal_values  2 to 8
+        default_value 4
+        description   "
+            This option specifies the number of input buffer packets
+            to be used for the Actel A2Fxxx/Ethernet device."
+    }
+
+    cdl_option  CYGPKG_DEVS_ETH_CORTEXM_A2FXXX_CFLAGS_ADD {
+        display "Additional compiler flags"
+        flavor  data
+        no_define
+        default_value { "-D_KERNEL -D__ECOS" }
+        description   "
+            This option modifies the set of compiler flags for
+            building the Actel A2Fxxx Ethernet driver package.
+            These flags are used in addition to the set of global flags."
+    }
+}
+
+# EOF a2fxxx_eth.cdl
diff --git a/packages/devs/eth/cortexm/a2fxxx/current/src/if_a2fxxx.c b/packages/devs/eth/cortexm/a2fxxx/current/src/if_a2fxxx.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/cortexm/a2fxxx/current/src/if_a2fxxx.c
@@ -0,0 +1,1088 @@
+//==========================================================================
+//
+//      if_a2fxxx.c
+//
+//      Ethernet driver for Actel A2Fxxx device family
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors:
+// Date:         2011-05-05
+// Purpose:      Ethernet driver for Actel A2Fxxx device family
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/system.h>
+#include <pkgconf/devs_eth_cortexm_a2fxxx.h>
+
+#ifdef CYGDAT_DEVS_CORTEXM_A2FXXX_ETH_CDL
+# include CYGDAT_DEVS_CORTEXM_A2FXXX_ETH_CDL
+#endif
+
+#include <pkgconf/io_eth_drivers.h>
+
+#ifdef CYGPKG_NET
+# include <pkgconf/net.h>
+#endif
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/var_io.h>
+
+#include <cyg/io/eth/netdev.h>
+#include <cyg/io/eth/eth_drv.h>
+
+#ifdef CYGPKG_DEVS_ETH_PHY
+# include <cyg/io/eth_phy.h>
+#endif
+
+#include <errno.h>
+#include <string.h>
+
+static unsigned char enaddr[6];
+
+// Buffer descriptor
+struct a2fxxx_bd {
+    cyg_uint32     des0;
+    cyg_uint32     des1;
+    cyg_uint32     des2;
+    cyg_uint32     des3;
+    cyg_uint32     private;
+};
+
+// Some statistics
+#ifdef CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_STATS
+typedef struct {
+    cyg_uint32     rx_mcast;
+    cyg_uint32     rx_des_err;
+    cyg_uint32     rx_collision;
+    cyg_uint32     rx_crc_err;
+    cyg_uint32     rx_too_long;
+    cyg_uint32     tx_fifo_underflow;
+    cyg_uint32     tx_frame_deferred;
+    cyg_uint32     tx_late_collision;
+    cyg_uint32     tx_no_carrier;
+    cyg_uint32     tx_loss_carrier;
+} a2fxxx_eth_stats;
+#endif
+
+// Internal data structure
+struct a2fxxx_eth_info {
+    volatile struct    a2fxxx_bd *txbd,
+                      *rxbd;                   // Next Tx,Rx descriptor to use
+    volatile struct    a2fxxx_bd *tbase,
+                      *rbase;                  // First Tx,Rx descriptor
+    volatile struct    a2fxxx_bd *tnext,
+                      *rnext;                  // Next descriptor to check for interrupt
+    cyg_uint8          txactive;               // Count of active Tx buffers
+    unsigned long      txkey[CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_TxNUM];
+    cyg_uint8          mac_address[6];         // mac (hardware) address
+    cyg_uint8          *init_rxbufs;           // Initial base pointer of RX buffers
+    cyg_uint8          *init_txbufs;           // Initial base pointer of TX buffers
+    volatile struct    a2fxxx_bd *init_rxring; // Initial base pointer of RX ring
+    volatile struct    a2fxxx_bd *init_txring; // Initial base pointer of TX ring
+    cyg_uint32         rx_mac[48];             // Setup frame (192) bytes
+    cyg_uint32         valid_mac;
+#ifdef CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_STATS
+    a2fxxx_eth_stats   stats;                  // MAC statistics
+#endif
+    cyg_uint32         base;                   // MAC base address
+    cyg_uint32         base_bb;                // MAC base address (bit-band)
+    cyg_uint8          if_num;
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    cyg_uint8          vector;
+    cyg_interrupt      interrupt;
+    cyg_handle_t       interrupt_handle;
+#endif
+#ifdef CYGPKG_DEVS_ETH_PHY
+    eth_phy_access_t   *phy;
+#endif
+};
+
+static void     a2fxxx_phy_init(void);
+static bool     a2fxxx_mdio_read(cyg_int32, cyg_int32, cyg_uint16 *);
+static void     a2fxxx_mdio_write(cyg_int32, cyg_int32, cyg_uint16);
+
+static void     a2fxxx_eth_int(struct eth_drv_sc *data);
+
+#ifdef CYGDAT_DEVS_CORTEXM_A2FXXX_ETH_INL
+# include CYGDAT_DEVS_CORTEXM_A2FXXX_ETH_INL
+#endif
+
+#include <cyg/infra/diag.h>
+
+#ifdef CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_CHATTER
+# define a2fxxx_eth_printf(args...)   diag_printf(args)
+#else
+# define a2fxxx_eth_printf(args...)    /* NOOP */
+#endif
+
+// For fetching the ESA from RedBoot
+#include <cyg/hal/hal_if.h>
+#ifndef CONFIG_ESA
+# define CONFIG_ESA 6
+#endif
+
+// ----------------------------------------------------------------
+// Definition
+//
+//
+
+#define RESET_FULL_DUPLEX                     0x00000001
+#define RESET_100MB                           0x00000002
+
+#define MDIO_PREAMBLE_SEQ                     0xffffffff
+#define MDIO_START_SEQ                        0x01
+#define MDIO_WRITE_SEQ                        0x01
+#define MDIO_READ_SEQ                         0x02
+#define MDIO_STOP_WRITE_SEQ                   0x02
+#define MDIO_STOP_READ_SEQ                    0x00
+
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TI_BB(_base_)  \
+    ( _base_ + ( CYGHWR_HAL_A2FXXX_MAC_CSR5 << 5 ) + (  0*sizeof(cyg_uint32) ) )
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RI_BB(_base_)  \
+    ( _base_ + ( CYGHWR_HAL_A2FXXX_MAC_CSR5 << 5 ) + (  6*sizeof(cyg_uint32) ) )
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_NIS_BB(_base_) \
+    ( _base_ + ( CYGHWR_HAL_A2FXXX_MAC_CSR5 << 5 ) + ( 16*sizeof(cyg_uint32) ) )
+
+#define CYGHWR_HAL_A2FXXX_MAC_PRIVATE_SENT    BIT_(0)
+
+#ifdef CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_STATS
+# define A2FXXX_INC_STATS(_x_)                 (qi->stats._x_++)
+#endif
+
+// ----------------------------------------------------------------
+// MDIO API
+//
+//
+
+#define MDIO_XFER_BITS( reg, reg_val, sequence, length )      \
+{                                                             \
+    cyg_uint32 i;                                             \
+    for (i = (1 << (length-1)); i != 0; ) {                   \
+        reg_val &= ~CYGHWR_HAL_A2FXXX_MAC_CSR9_MDC;           \
+        HAL_WRITE_UINT32( reg, reg_val );                     \
+        HAL_DELAY_US(1);                                      \
+        if( i & sequence )                                    \
+            reg_val |= (  CYGHWR_HAL_A2FXXX_MAC_CSR9_MDO );   \
+        else                                                  \
+            reg_val &= ( ~CYGHWR_HAL_A2FXXX_MAC_CSR9_MDO );   \
+        HAL_WRITE_UINT32( reg, reg_val );                     \
+        reg_val |= CYGHWR_HAL_A2FXXX_MAC_CSR9_MDC;            \
+        HAL_WRITE_UINT32( reg, reg_val );                     \
+        HAL_DELAY_US(1);                                      \
+        i = i >> 1;                                           \
+    }                                                         \
+}
+
+//
+// Setup IOs
+//
+static void
+a2fxxx_phy_init(void)
+{
+    a2fxxx_eth_printf("ETH A2Fxxx - PHY Init\n");
+    CYGHWR_HAL_A2FXXX_GPIO_SET(CYGHWR_HAL_A2FXXX_MAC0_MDIO);
+    CYGHWR_HAL_A2FXXX_GPIO_SET(CYGHWR_HAL_A2FXXX_MAC0_MDC);
+}
+
+//
+// Start MDIO transfer -> 32 bits of preamble ('1'), start bits,
+// transfer type bits, phy address and register address bits
+//
+static void
+a2fxxx_mdio_xfer_start(cyg_bool rd, cyg_uint8 phy_addr, cyg_uint8 addr)
+{
+    cyg_uint32      csr9_reg =
+        (CYGHWR_HAL_A2FXXX_MAC + CYGHWR_HAL_A2FXXX_MAC_CSR9);
+    cyg_uint32      csr9_data,
+                    bit_sequence;
+
+    // Enable MDIO write
+    HAL_READ_UINT32(csr9_reg, csr9_data);
+    csr9_data |=
+        (CYGHWR_HAL_A2FXXX_MAC_CSR9_MDEN | CYGHWR_HAL_A2FXXX_MAC_CSR9_MDO |
+         CYGHWR_HAL_A2FXXX_MAC_CSR9_MDC);
+    HAL_WRITE_UINT32(csr9_reg, csr9_data);
+    HAL_DELAY_US(1);
+
+    // Send preamble bits
+    bit_sequence = MDIO_PREAMBLE_SEQ;
+    MDIO_XFER_BITS(csr9_reg, csr9_data, bit_sequence, 32);
+
+    // Send 2 start bits
+    bit_sequence = MDIO_START_SEQ;
+    MDIO_XFER_BITS(csr9_reg, csr9_data, bit_sequence, 2);
+
+    // Send transfer type bits
+    bit_sequence = (rd == true) ? MDIO_READ_SEQ : MDIO_WRITE_SEQ;
+    MDIO_XFER_BITS(csr9_reg, csr9_data, bit_sequence, 2);
+
+    // Send PHY address
+    bit_sequence = (cyg_uint32)phy_addr;
+    MDIO_XFER_BITS(csr9_reg, csr9_data, bit_sequence, 5);
+
+    // Send register address
+    bit_sequence = (cyg_uint32)addr;
+    MDIO_XFER_BITS(csr9_reg, csr9_data, bit_sequence, 5);
+
+    // Send TA sequence
+    if (rd == true) {
+        bit_sequence = MDIO_STOP_READ_SEQ;
+        csr9_data &= ~(CYGHWR_HAL_A2FXXX_MAC_CSR9_MDEN);
+        HAL_WRITE_UINT32(csr9_reg, csr9_data);
+    } else {
+        bit_sequence = MDIO_STOP_WRITE_SEQ;
+    }
+    MDIO_XFER_BITS(csr9_reg, csr9_data, bit_sequence, 2);
+
+    // now we can read or write the 16 bits data ...
+}
+
+//
+// Read 16 bits data from MDIO interface
+//
+static cyg_bool
+a2fxxx_mdio_xfer_read(cyg_uint16 *data)
+{
+    cyg_uint32      csr9_reg =
+        (CYGHWR_HAL_A2FXXX_MAC + CYGHWR_HAL_A2FXXX_MAC_CSR9);
+    cyg_uint32      csr9_data;
+    *data = 0;
+    int             i;
+
+    // Read MDIO register
+    HAL_READ_UINT32(csr9_reg, csr9_data);
+
+    // Clock in the RX data
+    for (i = (1 << 15); i != 0;) {
+        csr9_data &= ~CYGHWR_HAL_A2FXXX_MAC_CSR9_MDC;
+        HAL_WRITE_UINT32(csr9_reg, csr9_data);
+        HAL_DELAY_US(1);
+        HAL_READ_UINT32(csr9_reg, csr9_data);
+        if (csr9_data & CYGHWR_HAL_A2FXXX_MAC_CSR9_MDI)
+            *data |= i;
+        csr9_data |= CYGHWR_HAL_A2FXXX_MAC_CSR9_MDC;
+        HAL_WRITE_UINT32(csr9_reg, csr9_data);
+        HAL_DELAY_US(1);
+        i = i >> 1;
+    }
+
+    return true;
+}
+
+//
+// Write 16 bits data to MDIO interface
+//
+static bool
+a2fxxx_mdio_xfer_write(cyg_uint16 data)
+{
+    cyg_uint32      csr9_reg =
+        (CYGHWR_HAL_A2FXXX_MAC + CYGHWR_HAL_A2FXXX_MAC_CSR9);
+    cyg_uint32      csr9_data,
+                    bit_sequence;
+
+    // Read MDIO register
+    HAL_READ_UINT32(csr9_reg, csr9_data);
+
+    // Write data
+    bit_sequence = (cyg_uint32)data;
+    MDIO_XFER_BITS(csr9_reg, csr9_data, bit_sequence, 16);
+
+    // Set back clock to low
+    csr9_data &= ~CYGHWR_HAL_A2FXXX_MAC_CSR9_MDC;
+    HAL_WRITE_UINT32(csr9_reg, csr9_data);
+
+    return true;
+}
+
+//
+// MDIO read register
+//
+static bool
+a2fxxx_mdio_read(cyg_int32 addr, cyg_int32 phy_addr, cyg_uint16 *data)
+{
+    bool            res;
+    a2fxxx_mdio_xfer_start(true, phy_addr, addr);
+    res = a2fxxx_mdio_xfer_read(data);
+    a2fxxx_eth_printf("ETH A2Fxxx - PHY %x(%x) - RX data %x\n", phy_addr, addr,
+                      *data);
+    return res;
+}
+
+//
+// MDIO write register
+//
+static void
+a2fxxx_mdio_write(cyg_int32 addr, cyg_int32 phy_addr, cyg_uint16 data)
+{
+    a2fxxx_mdio_xfer_start(false, phy_addr, addr);
+    a2fxxx_eth_printf("ETH A2Fxxx - PHY %x(%x) - TX data %x\n", phy_addr, addr,
+                      data);
+    a2fxxx_mdio_xfer_write(data);
+}
+
+
+// ----------------------------------------------------------------
+// Ethernet driver
+//
+//
+#define A2FXXX_RESET_MAC( qi )                                \
+{                                                             \
+    cyg_uint32      swr_addr =                                \
+          qi->base_bb + (CYGHWR_HAL_A2FXXX_MAC_CSR0 << 5);    \
+    cyg_uint32      swr_data = 0x1;                           \
+    HAL_WRITE_UINT32(swr_addr, swr_data);                     \
+    do {                                                      \
+        HAL_READ_UINT32(swr_addr, swr_data);                  \
+    } while (swr_data);                                       \
+}
+
+//
+// Deliver function (ex-DSR) handles the Ethernet [logical] processing
+//
+static void
+a2fxxx_eth_deliver(struct eth_drv_sc *sc)
+{
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    struct a2fxxx_eth_info *qi = (struct a2fxxx_eth_info *)sc->driver_private;
+#endif
+    a2fxxx_eth_int(sc);
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    // Allow interrupts to happen again
+    cyg_drv_interrupt_unmask(qi->vector);
+#endif
+}
+
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+//
+// This ISR is called when the Ethernet interrupt occurs
+//
+static int
+a2fxxx_eth_isr(cyg_vector_t vector, cyg_addrword_t data,
+               HAL_SavedRegisters * regs)
+{
+    a2fxxx_eth_printf("ETH A2Fxxx - ISR\n");
+    cyg_drv_interrupt_mask(vector);
+    cyg_drv_interrupt_acknowledge(vector);
+
+    return (CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);        // Run the DSR
+}
+
+void
+a2fxxx_eth_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
+{
+    a2fxxx_eth_deliver((struct eth_drv_sc *)data);
+    // Allow interrupts to happen again
+    cyg_drv_interrupt_unmask(vector);
+}
+#endif
+
+//
+// This function add MAC address to the list of allowed MAC address
+// that the MAC layer can deliver to the application layer
+//
+static bool
+a2fxxx_eth_add_mac ( struct eth_drv_sc *sc, cyg_uint8 *mac )
+{
+    struct a2fxxx_eth_info *qi = (struct a2fxxx_eth_info *)sc->driver_private;
+    cyg_uint8 idx = 12;
+    struct a2fxxx_bd setup_bd;
+    cyg_uint32 i, csr4, csr5, csr6, csr7;
+
+    // If no MAC to be added, just re-send the setup frame
+    if( mac != NULL )
+    {
+        // no more room
+        if( qi->valid_mac == (cyg_uint32) -1 )
+            return false;
+
+        // Search empty spot
+        while( qi->valid_mac & i ){
+            i = i << 1;
+            idx += 12;
+        }
+
+        qi->rx_mac[idx+0] = mac[0];
+        qi->rx_mac[idx+1] = mac[1];
+        qi->rx_mac[idx+4] = mac[2];
+        qi->rx_mac[idx+5] = mac[3];
+        qi->rx_mac[idx+8] = mac[4];
+        qi->rx_mac[idx+9] = mac[6];
+    }
+
+    a2fxxx_eth_printf("ETH A2Fxxx - Send setup frame for %s\n", sc->dev_name);
+
+    // Stop TX
+    HAL_READ_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR6), csr6);
+    csr6 &= ~( CYGHWR_HAL_A2FXXX_MAC_CSR6_ST );
+    HAL_WRITE_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR6), csr6);
+
+    // Wait until controller is halted
+    do {
+        HAL_READ_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR5), csr5);
+    } while( ((csr5 & CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_MASK)
+                                     != CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_STOP) );
+
+    // Backup the current BD / interrupt mask
+    HAL_READ_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR4), csr4);
+    HAL_READ_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR7), csr7);
+
+    // Disable interrupt
+    HAL_WRITE_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR7), 0);
+
+    // Setup descriptor for setup frame
+    setup_bd.des0 = CYGHWR_HAL_A2FXXX_MAC_TDES0_OWN;
+    setup_bd.des1 = CYGHWR_HAL_A2FXXX_MAC_TDES1_TER |
+                         CYGHWR_HAL_A2FXXX_MAC_TDES1_SET |
+                         CYGHWR_HAL_A2FXXX_MAC_TDES1_TBS1(192);
+    setup_bd.des2 = (cyg_uint32) &qi->rx_mac[0];
+    setup_bd.des3 = (cyg_uint32) NULL;
+    HAL_WRITE_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR4),
+                      (cyg_uint32) &setup_bd);
+
+    // Start transmission
+    csr6 |= ( CYGHWR_HAL_A2FXXX_MAC_CSR6_ST );
+    HAL_WRITE_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR6), csr6);
+
+    // Poll for transmission completed
+    do {
+        HAL_READ_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR5), csr5);
+    } while( ((csr5 & A2FXXX_MAC_TX_STATE_MASK) != A2FXXX_MAC_TX_STATE(SUSPEND)) );
+
+    // Stop transmission
+    csr6 &= ~( CYGHWR_HAL_A2FXXX_MAC_CSR6_ST );
+    HAL_WRITE_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR6), csr6);
+
+    // Wait until controller is halted
+    do {
+        HAL_READ_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR5), csr5);
+    } while( ((csr5 & CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_MASK)
+                                    != CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_STOP) );
+
+    // Restore BD
+    HAL_WRITE_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR4), csr4);
+
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_MAC_CSR5_TI_BB(qi->base_bb), 1);
+
+    // Restore interrupt mask
+    HAL_WRITE_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR7), csr7);
+
+    return true;
+}
+
+//
+// [re]Initialize the Ethernet controller
+//   Done separately since shutting down the device requires a
+//   full reconfiguration when re-enabling.
+//   when
+static bool
+a2fxxx_eth_setup(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
+{
+    struct a2fxxx_eth_info *qi = (struct a2fxxx_eth_info *) sc->driver_private;
+    volatile struct a2fxxx_bd *rxbd, *txbd;
+    cyg_uint8 *RxBUF, *TxBUF;
+    cyg_uint32 csr0, csr6 = 0, csr11;
+    int i = 0;
+
+    qi->valid_mac = 0;
+    qi->rx_mac[5] = enaddr[0];
+    qi->rx_mac[4] = enaddr[1];
+    qi->rx_mac[3] = enaddr[2];
+    qi->rx_mac[2] = enaddr[3];
+    qi->rx_mac[1] = enaddr[4];
+    qi->rx_mac[0] = enaddr[5];
+
+    txbd = qi->init_txring;
+    rxbd = qi->init_rxring;
+
+    /* Init Rx / Tx ring base */
+    qi->tbase = qi->txbd = qi->tnext = txbd;
+    qi->rbase = qi->rxbd = qi->rnext = rxbd;
+    qi->txactive = 0;
+
+    RxBUF = qi->init_rxbufs;
+    TxBUF = qi->init_txbufs;
+
+    /* Initialize Rx BDs */
+    for (i = 0; i < CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_RxNUM; i++)
+    {
+        rxbd->des0 = CYGHWR_HAL_A2FXXX_MAC_RDES0_OWN;
+        rxbd->des1 =
+          CYGHWR_HAL_A2FXXX_MAC_RDES1_RBS1(CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_ALIGN_BUFSIZE_RX);
+        rxbd->des2 = (cyg_uint32) RxBUF;
+        rxbd->des3 = (cyg_uint32) NULL;
+        RxBUF += CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_ALIGN_BUFSIZE_RX;
+        rxbd++;
+    }
+    rxbd--;
+    rxbd->des1 |= CYGHWR_HAL_A2FXXX_MAC_RDES1_RER; // Last buffer
+
+    /* Initialize Tx BDs */
+    for (i = 0; i < CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_TxNUM; i++)
+    {
+        txbd->des1 = 0;
+        txbd->des2 = (cyg_uint32) TxBUF;
+        rxbd->des3 = (cyg_uint32) NULL;
+        txbd->private = 0;
+        TxBUF += CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_ALIGN_BUFSIZE_TX;
+        txbd++;
+    }
+    txbd--;
+    txbd->des1 |= CYGHWR_HAL_A2FXXX_MAC_TDES1_TER; // Last buffer
+
+    // Setup automatic polling
+    csr0 = CYGHWR_HAL_A2FXXX_MAC_CSR0_CLEAR | CYGHWR_HAL_A2FXXX_MAC_CSR0_TAP(3) |
+           CYGHWR_HAL_A2FXXX_MAC_CSR0_DSL(1);
+
+    HAL_WRITE_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR0),
+                      (cyg_uint32) csr0);
+    HAL_WRITE_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR3),
+                      (cyg_uint32) (qi->rbase));
+    HAL_WRITE_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR4),
+                      (cyg_uint32) (qi->tbase));
+
+    csr11 = CYGHWR_HAL_A2FXXX_MAC_CSR11_TT(7) |
+            CYGHWR_HAL_A2FXXX_MAC_CSR11_NTP(1) |
+            CYGHWR_HAL_A2FXXX_MAC_CSR11_RT(7) |
+            CYGHWR_HAL_A2FXXX_MAC_CSR11_NRP(1);
+    HAL_WRITE_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR11), (cyg_uint32) csr11);
+
+    HAL_READ_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR6), csr6);
+    csr6 |= CYGHWR_HAL_A2FXXX_MAC_CSR6_CLEAR;
+
+    csr6 |= ((flags & RESET_100MB) ? CYGHWR_HAL_A2FXXX_MAC_CSR6_TTM : 0x0) |
+           ((flags & RESET_FULL_DUPLEX) ? CYGHWR_HAL_A2FXXX_MAC_CSR6_FD : 0x0);
+
+#ifdef CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_PROMISCUOUS
+    csr6 |= CYGHWR_HAL_A2FXXX_MAC_CSR6_PR;
+#endif
+
+    HAL_WRITE_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR6), csr6);
+
+    return true;
+}
+
+//
+// This function is called to shut down the interface.
+//
+static void
+a2fxxx_eth_stop(struct eth_drv_sc *sc)
+{
+    struct a2fxxx_eth_info *qi = (struct a2fxxx_eth_info *)sc->driver_private;
+    cyg_uint32 csr6, csr5;
+
+    a2fxxx_eth_printf("ETH A2Fxxx - Stop\n");
+
+    // Stop RX / TX
+    HAL_READ_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR6), csr6);
+    csr6 &= ~( CYGHWR_HAL_A2FXXX_MAC_CSR6_SR | CYGHWR_HAL_A2FXXX_MAC_CSR6_ST );
+    HAL_WRITE_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR6), csr6);
+
+    // Stall until controller is halted
+    do {
+        HAL_READ_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR5), csr5);
+    } while( ((csr5 & CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_MASK) != CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_STOP) &&
+             ((csr5 & CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_MASK) != CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_STOP));
+
+}
+
+//
+// Setup Ethernet IOs.
+//
+static void
+a2fxxx_eth_io(void)
+{
+    CYGHWR_HAL_A2FXXX_GPIO_SET(CYGHWR_HAL_A2FXXX_MAC0_TXD0);
+    CYGHWR_HAL_A2FXXX_GPIO_SET(CYGHWR_HAL_A2FXXX_MAC0_TXD1);
+    CYGHWR_HAL_A2FXXX_GPIO_SET(CYGHWR_HAL_A2FXXX_MAC0_RXD0);
+    CYGHWR_HAL_A2FXXX_GPIO_SET(CYGHWR_HAL_A2FXXX_MAC0_RXD1);
+    CYGHWR_HAL_A2FXXX_GPIO_SET(CYGHWR_HAL_A2FXXX_MAC0_TXEN);
+    CYGHWR_HAL_A2FXXX_GPIO_SET(CYGHWR_HAL_A2FXXX_MAC0_CRSDV);
+    CYGHWR_HAL_A2FXXX_GPIO_SET(CYGHWR_HAL_A2FXXX_MAC0_RXER);
+}
+
+//
+// Initialize the interface - performed at system startup
+// This function must set up the interface, including arranging to
+// handle interrupts, etc, so that it may be "started" cheaply later.
+//
+static bool
+a2fxxx_eth_init(struct cyg_netdevtab_entry *tab)
+{
+    struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
+    struct a2fxxx_eth_info *qi = (struct a2fxxx_eth_info *)sc->driver_private;
+    cyg_uint32      speed100 = 0, full_duplex = 0;
+    bool            esa_ok;
+    cyg_uint16      phy_state = 0;
+    cyg_uint32      istate, csr7;
+    bool            ret = true;
+
+    a2fxxx_eth_printf("ETH A2Fxxx - Initialization for %s\n", sc->dev_name);
+
+    // Release MAC controller
+    CYGHWR_HAL_A2FXXX_PERIPH_RELEASE(CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(MAC));
+
+    // Setup IOs
+    a2fxxx_eth_io();
+
+    // Reset MAC
+    A2FXXX_RESET_MAC( qi );
+
+    HAL_DISABLE_INTERRUPTS(istate);
+
+    a2fxxx_eth_stop(sc);
+
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    cyg_drv_interrupt_create(qi->vector,
+                             CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_ISR_PRIORITY,
+                             (cyg_addrword_t)sc,    //  Data item passed to interrupt handler
+                             (cyg_ISR_t *)a2fxxx_eth_isr,
+                             (cyg_DSR_t *)eth_drv_dsr,
+                             &qi->interrupt_handle, &qi->interrupt);
+    cyg_drv_interrupt_attach(qi->interrupt_handle);
+    cyg_drv_interrupt_unmask(qi->vector);
+#endif
+
+    esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+                                         "a2fxxx_esa", enaddr, CONFIG_ESA);
+
+    if (!esa_ok) {
+        a2fxxx_eth_printf("ETH A2Fxxx - Warning! ESA unknown for %s\n", sc->dev_name);
+        memcpy(&enaddr, &qi->mac_address, sizeof(enaddr));
+    }
+
+#ifdef CYGPKG_DEVS_ETH_PHY
+    if (!_eth_phy_init(qi->phy)) {
+        a2fxxx_eth_printf("ETH A2Fxxx - Failed to initialize PHY of %s\n",
+                          sc->dev_name);
+        ret = false;
+        goto exit;
+    }
+    phy_state = _eth_phy_state(qi->phy);
+
+    if (phy_state & ETH_PHY_STAT_100MB)
+        speed100 = 1;
+    if (phy_state & ETH_PHY_STAT_FDX)
+        full_duplex = 1;
+    if (phy_state & ETH_PHY_STAT_LINK) {
+        a2fxxx_eth_printf("Ethernet Mode (%s): %sMbps/%s\n",
+                          sc->dev_name,
+                          (speed100 ? "100" : "10"),
+                          (full_duplex ? "Full" : "Half"));
+    } else {
+        a2fxxx_eth_printf("ETH A2Fxxx - NO LINK on %s\n", sc->dev_name);
+    }
+#else
+    a2fxxx_eth_printf("ETH A2Fxxx - No PHY interface specified for %s\n",
+                      sc->dev_name);
+    ret = false;
+    goto exit;
+#endif
+
+    if (!a2fxxx_eth_setup(sc, enaddr, (full_duplex ? RESET_FULL_DUPLEX
+                         : 0x00000000) | (speed100 ? RESET_100MB : 0x00000000)))
+    {
+      ret = false;
+      goto exit;
+    }
+
+    a2fxxx_eth_add_mac( sc, NULL );
+
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_MAC_CSR5_RI_BB(qi->base_bb), 1);
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_MAC_CSR5_TI_BB(qi->base_bb), 1);
+
+    csr7 = ( CYGHWR_HAL_A2FXXX_MAC_CSR7_TIE | CYGHWR_HAL_A2FXXX_MAC_CSR7_RIE |
+                    CYGHWR_HAL_A2FXXX_MAC_CSR7_NIE);
+    HAL_WRITE_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR7), csr7);
+
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_MAC_CSR5_NIS_BB(qi->base_bb),
+                                                           (cyg_uint32) 0x1);
+
+    // Call upper layer initialization
+    (sc->funs->eth_drv->init)(sc, (unsigned char *) &enaddr);
+
+exit:
+    HAL_RESTORE_INTERRUPTS(istate);
+    return ret;
+}
+
+//
+// This function is called to "start up" the interface.  It may be called
+// multiple times, even when the hardware is already running.  It will be
+// called whenever something "hardware oriented" changes and should leave
+// the hardware ready to send/receive packets.
+//
+static void
+a2fxxx_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
+{
+    struct a2fxxx_eth_info *qi = (struct a2fxxx_eth_info *)sc->driver_private;
+    cyg_uint32 csr6;
+
+    a2fxxx_eth_printf("ETH A2Fxxx - Start\n");
+
+    // Stop RX / TX
+    HAL_READ_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR6), csr6);
+    csr6 |= ( CYGHWR_HAL_A2FXXX_MAC_CSR6_SR | CYGHWR_HAL_A2FXXX_MAC_CSR6_ST );
+    HAL_WRITE_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR6), csr6);
+}
+
+//
+// This function is called for low level "control" operations
+//
+static int
+a2fxxx_eth_control(struct eth_drv_sc *sc, unsigned long key,
+                   void *data, int length)
+{
+    switch (key)
+    {
+    case ETH_DRV_SET_MAC_ADDRESS:
+        return 0;
+        break;
+#ifdef ETH_DRV_SET_MC_ALL
+    case ETH_DRV_SET_MC_ALL:
+    case ETH_DRV_SET_MC_LIST:
+        // TODO
+        return 0;
+        break;
+#endif
+    default:
+        return 1;
+        break;
+    }
+}
+
+//
+// This function is called to see if another packet can be sent.
+// It should return the number of packets which can be handled.
+// Zero should be returned if the interface is busy and can not send any more.
+//
+static int
+a2fxxx_eth_can_send(struct eth_drv_sc *sc)
+{
+    struct a2fxxx_eth_info *qi = (struct a2fxxx_eth_info *) sc->driver_private;
+
+    return (qi->txactive < CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_TxNUM);
+}
+
+//
+// This routine is called to send data to the hardware.
+static void
+a2fxxx_eth_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list,
+                int sg_len, int total_len, unsigned long key)
+{
+    struct a2fxxx_eth_info *qi = (struct a2fxxx_eth_info *) sc->driver_private;
+    volatile struct a2fxxx_bd *txbd, *txfirst;
+    cyg_uint32 des1 = CYGHWR_HAL_A2FXXX_MAC_TDES1_TBS1(total_len);
+    volatile cyg_uint8 *bp;
+    cyg_int32 i, txindex, istate;
+
+    a2fxxx_eth_printf("ETH A2Fxxx - transmit pkt, length %d\n", total_len);
+
+    // Continue from current descriptor
+    txbd = txfirst = qi->txbd;
+
+    if ( (txbd->des0 & CYGHWR_HAL_A2FXXX_MAC_TDES0_OWN) == CYGHWR_HAL_A2FXXX_MAC_TDES0_OWN ) {
+        a2fxxx_eth_printf("ETH A2Fxxx - Fatal error, no free BD for %s\n",
+            sc->dev_name);
+        a2fxxx_eth_printf("ETH A2Fxxx - Cannot transmit packet, active pkt in queue:%d\n",
+            qi->txactive);
+        return;
+    }
+
+    // Set up buffer
+    bp = (cyg_uint8 *) txbd->des2;
+    for (i = 0; i < sg_len; i++) {
+        memcpy((void *) bp, (void *) sg_list[i].buf, sg_list[i].len);
+        bp += sg_list[i].len;
+    }
+
+    if (txbd->des1 & CYGHWR_HAL_A2FXXX_MAC_TDES1_TER) {
+        des1 |= CYGHWR_HAL_A2FXXX_MAC_TDES1_TER;
+    }
+    txbd->des1 =
+      ( des1 | CYGHWR_HAL_A2FXXX_MAC_TDES1_LS | CYGHWR_HAL_A2FXXX_MAC_TDES1_FS |
+        CYGHWR_HAL_A2FXXX_MAC_TDES1_IC );
+    txindex = ((unsigned long) txbd - (unsigned long) qi->tbase)
+                / sizeof(*txbd);
+    qi->txkey[txindex] = key;
+
+    qi->txactive++;
+
+    HAL_DISABLE_INTERRUPTS(istate);
+    // Give ownership to the MAC
+    txbd->des0    = CYGHWR_HAL_A2FXXX_MAC_TDES0_OWN;
+    txbd->private = CYGHWR_HAL_A2FXXX_MAC_PRIVATE_SENT;
+
+    // Remember the next buffer to try
+    if (qi->txbd->des1 & CYGHWR_HAL_A2FXXX_MAC_TDES1_TER){
+        qi->txbd = qi->tbase;
+    }
+    else {
+        qi->txbd++;
+    }
+    HAL_RESTORE_INTERRUPTS(istate);
+}
+
+//
+// This function is called for low level "control" operations
+//
+static void
+a2fxxx_eth_TxEvent(struct eth_drv_sc *sc)
+{
+    struct a2fxxx_eth_info *qi = (struct a2fxxx_eth_info *) sc->driver_private;
+    volatile struct a2fxxx_bd *txbd;
+    int key, txindex;
+
+    txbd = qi->tnext;
+
+    while ( ( (txbd->des0 & CYGHWR_HAL_A2FXXX_MAC_TDES0_OWN ) == 0) &&
+              (txbd->private & CYGHWR_HAL_A2FXXX_MAC_PRIVATE_SENT) )
+    {
+        txindex = ((unsigned long) txbd - (unsigned long) qi->tbase)
+                / sizeof(*txbd);
+        if ((key = qi->txkey[txindex]) != 0)
+        {
+            qi->txkey[txindex] = 0;
+            (sc->funs->eth_drv->tx_done)(sc, key, 0);
+        }
+        qi->txactive--;
+#ifdef CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_STATS
+        if( (txbd->des0 & CYGHWR_HAL_A2FXXX_MAC_TDES0_LC) ) {
+            A2FXXX_INC_STATS(tx_late_collision);
+        }
+        if( (txbd->des0 & CYGHWR_HAL_A2FXXX_MAC_TDES0_NC) ) {
+            A2FXXX_INC_STATS(tx_no_carrier);
+        }
+        if( (txbd->des0 & CYGHWR_HAL_A2FXXX_MAC_TDES0_LO) ) {
+            A2FXXX_INC_STATS(tx_loss_carrier);
+        }
+        if( (txbd->des0 & CYGHWR_HAL_A2FXXX_MAC_TDES0_DE) ) {
+            A2FXXX_INC_STATS(tx_frame_deferred);
+        }
+        if( (txbd->des0 & CYGHWR_HAL_A2FXXX_MAC_TDES0_UF) ) {
+            A2FXXX_INC_STATS(tx_fifo_underflow);
+        }
+#endif
+        txbd->private &= ~CYGHWR_HAL_A2FXXX_MAC_PRIVATE_SENT;
+        if (txbd->des1 & CYGHWR_HAL_A2FXXX_MAC_TDES1_TER){
+            txbd = qi->tbase;
+        } else {
+            txbd++;
+        }
+    }
+    // Remember where we left off
+    qi->tnext = (struct a2fxxx_bd *) txbd;
+}
+
+//
+// Interrupt vector
+//
+static int
+a2fxxx_eth_int_vector(struct eth_drv_sc *sc)
+{
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    struct a2fxxx_eth_info *qi = (struct a2fxxx_eth_info *) sc->driver_private;
+    return (qi->vector);
+#else
+    return 0;
+#endif
+}
+
+//
+// This function is called when a packet has been received.  It's job is
+// to prepare to unload the packet from the hardware.  Once the length of
+// the packet is known, the upper layer of the driver can be told.  When
+// the upper layer is ready to unload the packet, the internal function
+// 'fec_eth_recv' will be called to actually fetch it from the hardware.
+//
+static void
+a2fxxx_eth_RxEvent(struct eth_drv_sc *sc)
+{
+  struct a2fxxx_eth_info *qi = (struct a2fxxx_eth_info *) sc->driver_private;
+  volatile struct a2fxxx_bd *rxbd, *rxfirst;
+  int cnt_bd = 0;
+  cyg_int32 len;
+
+  rxbd = rxfirst = qi->rnext;
+  while ((rxbd->des0 & CYGHWR_HAL_A2FXXX_MAC_RDES0_OWN) == 0)
+  {
+    cnt_bd++;
+    qi->rxbd = rxbd; // Save for callback
+
+#ifdef CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_STATS
+    if( (rxbd->des0 & CYGHWR_HAL_A2FXXX_MAC_RDES0_CE) ) {
+        A2FXXX_INC_STATS(rx_crc_err);
+    }
+    if( (rxbd->des0 & CYGHWR_HAL_A2FXXX_MAC_RDES0_CS) ) {
+        A2FXXX_INC_STATS(rx_collision);
+    }
+    if( (rxbd->des0 & CYGHWR_HAL_A2FXXX_MAC_RDES0_TL) ) {
+        A2FXXX_INC_STATS(rx_too_long);
+    }
+    if( (rxbd->des0 & CYGHWR_HAL_A2FXXX_MAC_RDES0_MF) ) {
+        A2FXXX_INC_STATS(rx_mcast);
+    }
+    if( (rxbd->des0 & CYGHWR_HAL_A2FXXX_MAC_RDES0_DE) ) {
+        A2FXXX_INC_STATS(rx_des_err);
+    }
+#endif
+
+    len = (rxbd->des0 >> 16) & 0x3fff;
+    a2fxxx_eth_printf("ETH A2Fxxx - Receive pkt, length %d\n", len);
+
+    (sc->funs->eth_drv->recv)(sc, len - 4);
+    if (rxbd->des1 & CYGHWR_HAL_A2FXXX_MAC_RDES1_RER){
+        rxbd = qi->rbase;
+    } else {
+        rxbd++;
+    }
+  }
+  // Remember where we left off
+  qi->rnext = (struct a2fxxx_bd *) rxbd;
+}
+
+//
+// Interrupt processing
+//
+static void
+a2fxxx_eth_int(struct eth_drv_sc *sc)
+{
+    struct a2fxxx_eth_info *qi = (struct a2fxxx_eth_info *) sc->driver_private;
+    cyg_uint32 csr5;
+
+     // Check interrupt status
+     HAL_READ_UINT32( (qi->base + CYGHWR_HAL_A2FXXX_MAC_CSR5), csr5);
+
+     if (( csr5 & CYGHWR_HAL_A2FXXX_MAC_CSR5_TI ) != 0)
+     {
+         a2fxxx_eth_printf("%s - Transmit packet irq\n", sc->dev_name);
+         a2fxxx_eth_TxEvent(sc);
+         HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_MAC_CSR5_TI_BB(qi->base_bb), 1);
+     }
+
+     if (( csr5 & CYGHWR_HAL_A2FXXX_MAC_CSR5_RI ) != 0)
+     {
+         a2fxxx_eth_printf("%s - Receive packet irq\n", sc->dev_name);
+         a2fxxx_eth_RxEvent(sc);
+         HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_MAC_CSR5_RI_BB(qi->base_bb), 1);
+     }
+}
+
+//
+// Polling function
+//
+static void
+a2fxxx_eth_poll(struct eth_drv_sc *sc)
+{
+     a2fxxx_eth_int(sc);
+     CYGACC_CALL_IF_DELAY_US(500);
+}
+
+static void
+a2fxxx_eth_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
+{
+    struct a2fxxx_eth_info *qi = (struct a2fxxx_eth_info *) sc->driver_private;
+    cyg_uint8 *bp;
+    int i;
+
+    bp = (cyg_uint8 *) qi->rxbd->des2;
+    for (i = 0; i < sg_len; i++)
+    {
+        if (sg_list[i].buf != 0)
+        {
+            memcpy((void *) sg_list[i].buf, bp, sg_list[i].len);
+            bp += sg_list[i].len;
+        }
+    }
+    qi->rxbd->des0 |= CYGHWR_HAL_A2FXXX_MAC_RDES0_OWN;
+}
+
+
+//
+// Display ETH statistics
+//
+#ifdef CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_STATS
+externC void
+a2fxxx_disp_stats(struct eth_drv_sc *sc , char flag )
+{
+    struct a2fxxx_eth_info *qi = (struct a2fxxx_eth_info *) sc->driver_private;
+
+    diag_printf("Ethernet Statistics\n");
+
+    diag_printf("%17s %10d\n",
+        "RX MCAST",
+        qi->stats.rx_mcast);
+    diag_printf("%17s %10d\n",
+        "RX DESC ERR",
+        qi->stats.rx_des_err);
+    diag_printf("%17s %10d\n",
+        "RX COLLISION",
+        qi->stats.rx_collision);
+    diag_printf("%17s %10d\n",
+        "RX CRC ERR",
+        qi->stats.rx_crc_err);
+    diag_printf("%17s %10d\n",
+        "RX TOO LONG",
+        qi->stats.rx_too_long);
+    diag_printf("%17s %10d\n",
+        "TX FIFO UNDERFLOW",
+        qi->stats.tx_fifo_underflow);
+    diag_printf("%17s %10d\n",
+        "TX FRAME DEFERRED",
+        qi->stats.tx_frame_deferred);
+    diag_printf("%17s %10d\n",
+        "TX LATE COLLISION",
+        qi->stats.tx_late_collision);
+    diag_printf("%17s %10d\n",
+        "TX NO CARRIER",
+        qi->stats.tx_no_carrier);
+    diag_printf("%17s %10d\n",
+        "TX LOSS CARRIER",
+        qi->stats.tx_loss_carrier);
+}
+#endif
+
+// EOF if_a2fxxx.c
diff --git a/packages/devs/eth/cortexm/stm32/current/ChangeLog b/packages/devs/eth/cortexm/stm32/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/cortexm/stm32/current/ChangeLog
@@ -0,0 +1,29 @@
+2010-11-04  Jerzy Dyrda  <jerzdy@gmail.com>
+
+	* cdl/stm32_eth.cdl:
+	* src/if_stm32.c:
+	STM32 ETH driver package created.  [ Bugzilla 1001219 ]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc.      
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/eth/cortexm/stm32/current/cdl/stm32_eth.cdl b/packages/devs/eth/cortexm/stm32/current/cdl/stm32_eth.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/cortexm/stm32/current/cdl/stm32_eth.cdl
@@ -0,0 +1,241 @@
+#==========================================================================
+#
+#      stm32_eth.cdl
+#
+#      Ethernet drivers for ST STM32 Cores
+#
+#==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+#==========================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):    Jerzy Dyrda (jerzdy@gmail.com)
+# Contributors:
+# Date:         2010-11-04
+# Purpose:
+# Description:
+#
+#####DESCRIPTIONEND####
+#
+#========================================================================*/
+
+cdl_package CYGPKG_DEVS_ETH_CORTEXM_STM32 {
+    display       "ST STM32 ethernet driver"
+    parent        CYGPKG_IO_ETH_DRIVERS
+    active_if     CYGPKG_IO_ETH_DRIVERS
+    active_if     CYGPKG_HAL_CORTEXM_STM32
+
+    implements    CYGHWR_NET_DRIVERS
+    implements    CYGHWR_NET_DRIVER_ETH0
+
+    include_dir   net
+    description   "
+       Ethernet driver for ST STM32 controler."
+
+    compile       -library=libextras.a if_stm32.c
+
+    cdl_option CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL {
+         display "Driver debug output level"
+         flavor  data
+         legal_values {0 1 2 3}
+         default_value 0
+         description   "
+             This option specifies the level of debug data output by
+             the STM32 ethernet device driver. A value of 0 signifies
+             no debug data output; 1 signifies normal debug data
+             output; 2 signifies extended debug data output;
+             and 3 signifies maximum debug data output (not
+             suitable when GDB and application are sharing an ethernet
+             port)."
+    }
+
+    cdl_option CYGSEM_DEVS_ETH_CORTEXM_STM32_INTF {
+        display       "Type of interface to PHY"
+        flavor        data
+        default_value {"RMII"}
+        legal_values  {"MII" "RMII"}
+        description   "
+            Type of interface used to connect with PHY : MII or RMII"
+    }
+
+    cdl_option CYGSEM_DEVS_ETH_CORTEXM_STM32_REMAP_PINS {
+        display       "MII/RMII pins remapped"
+        flavor        bool
+        default_value 0
+        description     "
+            MII/RMII interface signals are remapped"
+    }
+
+    cdl_option CYGHWR_DEVS_ETH_CORTEXM_STM32_PHY_CLK_MCO {
+            display         "Configure MCO as PHY clock"
+            default_value   0
+            description     "
+                Enable the MCO clock signals as clock for PHY."
+        }
+
+    cdl_option CYGNUM_DEVS_ETH_CORTEXM_STM32_RX_BUFS {
+        display       "Number of RX buffers"
+        flavor        data
+        default_value 6
+        legal_values  2 to 16
+        description   "
+            Number of receive buffers. Each buffer is 1520 bytes in size"
+    }
+
+    cdl_component CYGSEM_DEVS_ETH_CORTEXM_STM32_CHECKSUM {
+        display "TCP/IP checksums"
+        flavor none
+        no_define
+        active_if { is_active (CYGPKG_LWIP_CHECKSUMS) }
+        description "
+            STM32 Ethernet controller  provides for hardware TCP/IP
+            header checksum generation and check."
+
+        active_if CYGPKG_NET_LWIP
+        requires CYGPKG_LWIP_CHECKSUMS
+
+
+        cdl_option CYGSEM_DEVS_ETH_CORTEXM_STM32_TX_CHECKSUM_GEN {
+            display       "Generating the checksum for transmitting packets"
+            flavor        bool
+            default_value 1
+            requires      { is_active(CYGPKG_LWIP_CHECKSUMS) implies
+                              0 == CYGIMP_LWIP_CHECKSUM_GEN_IP }
+            requires      { is_active(CYGPKG_LWIP_CHECKSUMS) implies
+                              0 == CYGIMP_LWIP_CHECKSUM_GEN_UDP }
+            requires      { is_active(CYGPKG_LWIP_CHECKSUMS) implies
+                              0 == CYGIMP_LWIP_CHECKSUM_GEN_TCP }
+            description     "
+                Generating and inserting the checksum of the IP, UDP, TCP
+                and ICMP protocols by hardware for transmitting packets."
+        }
+
+        cdl_option CYGSEM_DEVS_ETH_CORTEXM_STM32_RX_CHECKSUM_VER {
+            display       "Verifying the checksum for receiving packets"
+            flavor        bool
+            default_value 1
+            requires      { is_active(CYGPKG_LWIP_CHECKSUMS) implies
+                              0 == CYGIMP_LWIP_CHECKSUM_CHECK_IP }
+            requires      { is_active(CYGPKG_LWIP_CHECKSUMS) implies
+                              0 == CYGIMP_LWIP_CHECKSUM_CHECK_UDP }
+            requires      { is_active(CYGPKG_LWIP_CHECKSUMS) implies
+                              0 == CYGIMP_LWIP_CHECKSUM_CHECK_TCP }
+            description   "
+                Verifying the checksum of the IP, UDP, TCP and ICMP
+                protocols by hardware for receiving packets."
+        }
+
+        cdl_option CYGSEM_ETH_LWIP_CHECKSUMS {
+            display "lwIP Checksum calculation"
+            flavor none
+            no_define
+            description "
+                Re-enable lwIP software checksum generation/check if
+                hardware generation/check is disabled."
+
+            requires { !CYGSEM_DEVS_ETH_CORTEXM_STM32_TX_CHECKSUM_GEN implies
+                CYGIMP_LWIP_CHECKSUM_GEN_IP == 1 }
+            requires { !CYGSEM_DEVS_ETH_CORTEXM_STM32_TX_CHECKSUM_GEN implies
+                CYGIMP_LWIP_CHECKSUM_GEN_TCP == 1 }
+            requires { !CYGSEM_DEVS_ETH_CORTEXM_STM32_TX_CHECKSUM_GEN implies
+                CYGIMP_LWIP_CHECKSUM_GEN_UDP == 1 }
+
+            requires { !CYGSEM_DEVS_ETH_CORTEXM_STM32_RX_CHECKSUM_VER implies
+                CYGIMP_LWIP_CHECKSUM_CHECK_IP == 1 }
+            requires { !CYGSEM_DEVS_ETH_CORTEXM_STM32_RX_CHECKSUM_VER implies
+                CYGIMP_LWIP_CHECKSUM_CHECK_TCP == 1 }
+            requires { !CYGSEM_DEVS_ETH_CORTEXM_STM32_RX_CHECKSUM_VER implies
+                CYGIMP_LWIP_CHECKSUM_CHECK_UDP == 1 }
+        }
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_CORTEXM_STM32_REDBOOT_HOLDS_ESA {
+        display         "RedBoot manages ESA initialization data"
+        flavor          bool
+        default_value   0
+
+        active_if     CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+        active_if     (CYGPKG_REDBOOT || CYGSEM_HAL_USE_ROM_MONITOR)
+
+        description   "
+            Enabling this option will allow the ethernet station
+            address to be acquired from RedBoot's configuration data,
+            stored in flash memory.  It can be overridden individually
+            by the 'Set the ethernet station address' option for each
+            interface."
+
+
+        cdl_component CYGPKG_DEVS_ETH_CORTEXM_STM32_REDBOOT_HOLDS_ESA_VARS {
+            display        "Export RedBoot command to set ESA in FLASH config"
+            flavor         none
+            no_define
+            description "
+                This component contains options which, when enabled, allow
+                RedBoot to support the setting of the ESA in the FLASH
+                configuration. This can then subsequently be accessed by
+                applications using virtual vector calls if those applications
+                are also built with
+                CYGPKG_DEVS_ETH_CORTEXM_STM32_REDBOOT_HOLDS_ESA enabled."
+
+            cdl_option CYGSEM_DEVS_ETH_CORTEXM_STM32_REDBOOT_HOLDS_ESA_ETH0 {
+                display         "RedBoot manages ESA for eth0"
+                flavor          bool
+                default_value   1
+                active_if       CYGSEM_REDBOOT_FLASH_CONFIG
+                active_if       CYGPKG_REDBOOT_NETWORKING
+            }
+        }
+    }
+
+    cdl_option CYGPKG_DEVS_ETH_CORTEXM_STM32_MACADDR {
+        display "Ethernet station (MAC) address for eth0"
+        flavor  data
+        default_value {"0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC"}
+        description   "The default ethernet station address. This is the
+                       MAC address used when no value is found in the
+                       RedBoot FLASH configuration field."
+    }
+
+    cdl_option  CYGPKG_DEVS_ETH_CORTEXM_STM32_CFLAGS_ADD {
+        display "Additional compiler flags"
+        flavor  data
+        no_define
+        default_value { "-D_KERNEL -D__ECOS" }
+        description   "
+            This option modifies the set of compiler flags for
+            building the ST STM32 ethernet driver package.
+            These flags are used in addition to the set of global flags."
+    }
+}
+
+# EOF stm32_eth.cdl
diff --git a/packages/devs/eth/cortexm/stm32/current/src/if_stm32.c b/packages/devs/eth/cortexm/stm32/current/src/if_stm32.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/cortexm/stm32/current/src/if_stm32.c
@@ -0,0 +1,1030 @@
+//==========================================================================
+//
+//      if_stm32.c
+//
+//      Fast ethernet device driver for ST STM32 controller
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Jerzy Dyrda <jerzdy@gmail.com>
+// Contributors:
+// Date:         2010-10-05
+// Purpose:
+// Description:	 hardware driver for STM32 ETH
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+#include <pkgconf/devs_eth_cortexm_stm32.h>
+#include <pkgconf/io_eth_drivers.h>
+#if defined(CYGPKG_REDBOOT)
+   #include <pkgconf/redboot.h>
+#endif
+
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/hal/plf_io.h>
+#include <cyg/hal/hal_diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/diag.h>
+#include <cyg/io/eth/netdev.h>
+#include <cyg/io/eth/eth_drv.h>
+#include <cyg/io/eth/eth_drv_stats.h>
+#include <cyg/io/eth_phy.h>
+#include <errno.h>
+#include <string.h>
+
+//-----------------------------------------------------------------------------
+// Maintenance and debug macros.
+
+// Set up the level of debug output
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+#define DIAG_PRINTF(__fmt, ... )                    \
+    diag_printf("if_stm32:%s[%d]:"                  \
+        _fmt, __FUNCTION__, __LINE__, ## __VA_ARGS__ );
+#else
+#define DIAG_PRINTF( __fmt, ... )                   \
+    while(0){}
+#endif
+
+#define IF_STM32_INC_DESC(_curr_desc_, _max_desc_)  \
+    _curr_desc_++;                                  \
+    if (_curr_desc_ >=	_max_desc_) {               \
+        _curr_desc_ = 0;                            \
+    }
+
+//---------------------------------------------------------------------
+// Shorthand for some of the configuration options.
+#define ETH_BASE                    CYGHWR_HAL_STM32_ETH
+#define TDES_NUM                    (CYGNUM_IO_ETH_DRIVERS_SG_LIST_SIZE >> 1)
+#define RDES_NUM                    CYGNUM_DEVS_ETH_CORTEXM_STM32_RX_BUFS
+#define ETH_MAX_PACKET_SIZE         1520
+
+// Bits in status register of tx descriptor which are set up during
+// initialization and remain unchanged while sending process
+#define ETH_DMA_TDES_INIT_MASK    \
+    (CYGHWR_HAL_STM32_ETH_TDES0_TER | CYGHWR_HAL_STM32_ETH_TDES0_CIC_HPP)
+
+//Driver interface callbacks
+#define _eth_drv_init(sc,mac)				\
+    (sc->funs->eth_drv->init)(sc,(unsigned char *)mac)
+#define _eth_drv_tx_done(sc,key,status)			\
+    (sc->funs->eth_drv->tx_done)(sc,key,status)
+#define _eth_drv_recv(sc,len)				\
+    (sc->funs->eth_drv->recv)(sc,len)
+
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+static cyg_uint32 stm32_eth_isr (cyg_vector_t vector, cyg_addrword_t data);
+#endif
+
+// --------------------------------------------------------------
+// RedBoot configuration options for managing ESAs for us
+
+// Decide whether to have redboot config vars for it
+#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYGPKG_REDBOOT_NETWORKING)
+    #include <redboot.h>
+    #include <flash_config.h>
+
+    #ifdef CYGSEM_DEVS_ETH_CORTEXM_STM32_REDBOOT_HOLDS_ESA_ETH0
+RedBoot_config_option("Network hardware address [MAC] for eth0",
+                      eth0_esa_data,
+                      ALWAYS_ENABLED, true,
+                      CONFIG_ESA, 0);
+    #endif
+
+#endif  // CYGPKG_REDBOOT_NETWORKING && CYGSEM_REDBOOT_FLASH_CONFIG
+
+// and initialization code to read them
+// - independent of whether we are building RedBoot right now:
+#ifdef CYGPKG_DEVS_ETH_CORTEXM_STM32_REDBOOT_HOLDS_ESA
+
+    #include <cyg/hal/hal_if.h>
+
+    #ifndef CONFIG_ESA
+        #define CONFIG_ESA (6)
+    #endif
+
+    #define CYGHWR_DEVS_ETH_CORTEXM_STM32_GET_ESA( mac_address, ok )	\
+    CYG_MACRO_START                                                     \
+    ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,     \
+                                    "eth0_esa_data",                    \
+                                    mac_address,                        \
+                                    CONFIG_ESA);                        \
+    CYG_MACRO_END
+
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_REDBOOT_HOLDS_ESA
+
+//============================================================================
+
+// Private Data
+typedef struct stm32_eth_dma_des_s {
+    cyg_uint32   status;          // DES0 : Own and Status
+    cyg_uint32   ctrl_len;        // DES1 : Ctrl/Buffer1 and Buffer2 length
+    cyg_uint32   buff1_addr;      // DES2 : Buffer1 address
+    cyg_uint32   buff2_addr;      // DES3 : Buffer2 address
+} stm32_eth_dma_des_t;
+
+static cyg_uint8 __attribute__ ((aligned (4)))
+    rx_buff[RDES_NUM][ETH_MAX_PACKET_SIZE];
+static stm32_eth_dma_des_t __attribute__ ((aligned (4))) rdes[RDES_NUM];
+
+static stm32_eth_dma_des_t __attribute__ ((aligned (4))) tdes[TDES_NUM];
+
+// STM32 Ethernet private data
+typedef struct stm32_eth_priv_s
+{
+   cyg_uint32    intr_vector;
+   char * esa_key;      // RedBoot 'key' for device ESA
+   eth_phy_access_t *phy;
+   unsigned long tx_key[TDES_NUM];
+   cyg_uint32 curr_tdes_idx;
+   cyg_uint32 prev_tdes_idx;
+   cyg_uint32 curr_rdes_idx;
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+   cyg_interrupt intr;
+   cyg_handle_t  intr_handle;
+#endif
+} stm32_eth_priv_t;
+
+__externC cyg_uint32 hal_stm32_hclk;
+static cyg_uint32 mdc_clock_div;
+
+//============================================================================
+// PHY access bits and pieces
+
+static void stm32_init_phy(void)
+{
+    int stm32_hclk_mhz = hal_stm32_hclk / 1000000;
+    mdc_clock_div = 0;
+
+    CYG_ASSERTC(CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ_CHECK(stm32_hclk_mhz));
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+    DIAG_PRINTF("init phy: hclk %d MHz\n", stm32_hclk_mhz);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+
+    if (CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ_CHECK(stm32_hclk_mhz))
+        mdc_clock_div = CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ(stm32_hclk_mhz);
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+    else
+       DIAG_PRINTF("init phy : clk for ETH module out of supported range\n");
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+}
+
+// Write one of the PHY registers via the MII bus
+
+static void stm32_write_phy(int reg_addr, int phy_addr, unsigned short data)
+{
+    cyg_uint32 addr = 0;
+    volatile cyg_uint32 reg_val;
+
+    CYG_ASSERTC(reg_addr >= 0 && reg_addr < 32);
+    CYG_ASSERTC(phy_addr >= 0 && phy_addr < 32);
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+    DIAG_PRINTF("write phy: addr %d, reg %d, data 0x%x\n",
+        phy_addr, reg_addr, data);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+
+    /* Prepare the ENET MIIA address */
+    addr |= CYGHWR_HAL_STM32_ETH_MACMIIAR_PA(phy_addr);
+    addr |= CYGHWR_HAL_STM32_ETH_MACMIIAR_MR(reg_addr);
+    addr |= mdc_clock_div;
+    addr |= CYGHWR_HAL_STM32_ETH_MACMIIAR_MW;
+    addr |= CYGHWR_HAL_STM32_ETH_MACMIIAR_MB;
+
+    do
+    {
+        HAL_READ_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_MACMIIAR, reg_val);
+    } while (reg_val & CYGHWR_HAL_STM32_ETH_MACMIIAR_MB);
+
+    // Lauch MDIO transaction
+    HAL_WRITE_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_MACMIIDR, data);
+    HAL_WRITE_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_MACMIIAR, addr);
+}
+
+// Read one of the PHY registers via the MII bus
+
+static bool stm32_read_phy(int reg_addr, int phy_addr, unsigned short *data)
+{
+    cyg_uint32 addr = 0;
+    volatile cyg_uint32 reg_val;
+
+    CYG_ASSERTC(reg_addr >= 0 && reg_addr < 32);
+    CYG_ASSERTC(phy_addr >= 0 && phy_addr < 32);
+
+    /* Prepare the ENET MIIA address */
+    addr |= CYGHWR_HAL_STM32_ETH_MACMIIAR_PA(phy_addr);
+    addr |= CYGHWR_HAL_STM32_ETH_MACMIIAR_MR(reg_addr);
+    addr |= mdc_clock_div;
+    addr |= CYGHWR_HAL_STM32_ETH_MACMIIAR_MB;
+
+    do
+    {
+        HAL_READ_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_MACMIIAR, reg_val);
+    } while (reg_val & CYGHWR_HAL_STM32_ETH_MACMIIAR_MB);
+
+    // Lauch MDIO transaction
+    HAL_WRITE_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_MACMIIAR, addr);
+
+    do
+    {
+        HAL_READ_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_MACMIIAR, reg_val);
+    } while (reg_val & CYGHWR_HAL_STM32_ETH_MACMIIAR_MB);
+
+    HAL_READ_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_MACMIIDR, *data);
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+    DIAG_PRINTF("read phy: addr %d, reg %d, data 0x%x\n",
+        phy_addr, reg_addr, *data);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+
+    return (true);
+}
+
+ETH_PHY_REG_LEVEL_ACCESS_FUNS(stm32_phy,
+                              stm32_init_phy,
+                              NULL,
+                              stm32_write_phy,
+                              stm32_read_phy);
+
+//======================================================================
+// Receiver buffer handling
+
+// Initialize the receiver buffers and descriptors in ring mode
+
+static void stm32_rdes_init(void)
+{
+    int ii;
+
+    for (ii = 0; ii < RDES_NUM; ii++) {
+        rdes[ii].status = (cyg_uint32) CYGHWR_HAL_STM32_ETH_RDES0_OWN;
+        rdes[ii].ctrl_len = (cyg_uint32) ETH_MAX_PACKET_SIZE;
+        rdes[ii].buff1_addr = (cyg_uint32) &rx_buff[ii][0];
+    }
+
+    // End of ring
+    rdes[RDES_NUM - 1].ctrl_len |=
+        (cyg_uint32) CYGHWR_HAL_STM32_ETH_RDES1_RER;
+
+    /* Set Receive Desciptor List Address Register */
+    HAL_WRITE_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_DMARDLAR,
+        ((cyg_uint32) &rdes[0]));
+}
+
+//======================================================================
+// Transmit buffer handling
+
+// Initialize the transmit buffer descriptors in ring mode
+
+static void stm32_tdes_init(void)
+{
+
+#ifdef CYGSEM_DEVS_ETH_CORTEXM_STM32_TX_CHECKSUM_GEN
+    int ii;
+
+    for (ii = 0; ii < TDES_NUM; ii++) {
+        tdes[ii].status = (cyg_uint32) CYGHWR_HAL_STM32_ETH_TDES0_CIC_HPP;
+    }
+#endif
+
+    // End of ring
+    tdes[TDES_NUM - 1].status |= (cyg_uint32) CYGHWR_HAL_STM32_ETH_TDES0_TER;
+
+    /* Set Receive Desciptor List Address Register */
+    HAL_WRITE_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_DMATDLAR,
+        ((cyg_uint32) &tdes[0]));
+}
+
+//======================================================================
+// Initialization code
+
+// Set a specific address match to a given address. Packets received which
+// match this address will be passed on.
+
+static void stm32_set_mac(cyg_uint8 * enaddr)
+{
+    cyg_uint32 hi, lo;
+
+    lo = ((enaddr[3] << 24) | (enaddr[2] << 16) |
+	    (enaddr[1] <<  8) | (enaddr[0]));
+
+    hi = ((enaddr[5] <<  8) | (enaddr[4]));
+
+    HAL_WRITE_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_MACA0LR, lo);
+    HAL_WRITE_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_MACA0HR, hi);
+}
+
+// Enable and Disable of the receiver and transmitter.
+// Initialize the interface. This configures the interface ready for use.
+// Interrupts are grabbed etc. This means the start function has
+// little to do except enable the receiver
+
+static bool stm32_eth_init(struct cyg_netdevtab_entry *tab)
+{
+    struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
+    stm32_eth_priv_t *priv = (stm32_eth_priv_t *)sc->driver_private;
+#ifdef CYGHWR_DEVS_ETH_ARM_STM32_GET_ESA
+    bool esa_ok = false;
+#endif
+    unsigned char enaddr[6] = { CYGPKG_DEVS_ETH_CORTEXM_STM32_MACADDR};
+    volatile cyg_uint32 reg_val;
+    unsigned short phy_state = 0;
+
+#ifdef CYGHWR_DEVS_ETH_CORTEXM_STM32_PHY_CLK_MCO
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MCO);
+#endif
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+    DIAG_PRINTF("Initialising ETH module\n");
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+
+    // Enable clock for ETH module
+    HAL_READ_UINT32(CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_AHB1ENR, reg_val);
+    reg_val |= BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMAC) |
+        BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMACTX) |
+        BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMACRX) |
+        BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMACPTP);
+    HAL_WRITE_UINT32(CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_AHB1ENR, reg_val);
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+    HAL_READ_UINT32(CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB2ENR, reg_val);
+    reg_val |= BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_SYSCFG);
+    HAL_WRITE_UINT32(CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB2ENR, reg_val);
+#endif
+    hal_delay_us(100);
+
+    // Configure the GPIO ports
+#ifdef CYGSEM_DEVS_ETH_CORTEXM_STM32_INTF_MII
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+    DIAG_PRINTF("Initialise MII interface\n");
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+
+    // Configure MAC interface in MII mode
+#ifdef CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+    HAL_READ_UINT32(CYGHWR_HAL_STM32_AFIO + CYGHWR_HAL_STM32_AFIO_MAPR, reg_val);
+    reg_val &= ~CYGHWR_HAL_STM32_AFIO_MAPR_ETH_RMII;
+    HAL_WRITE_UINT32(CYGHWR_HAL_STM32_AFIO + CYGHWR_HAL_STM32_AFIO_MAPR, reg_val);
+#else
+    HAL_WRITE_UINT32(CYGHWR_HAL_STM32_SYSCFG + CYGHWR_HAL_STM32_SYSCFG_PMC,
+        CYGHWR_HAL_STM32_SYSCFG_PMC_MII);
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_TX_CLK);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_RX_CLK);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_MDIO);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_MDC);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_COL);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_TX_CRS);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_TX_EN);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_TXD0);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_TXD1);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_TXD2);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_TXD3);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_RX_ER);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_RX_DV);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_RXD0);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_RXD1);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_RXD2);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_MII_RXD3);
+#elif defined(CYGSEM_DEVS_ETH_CORTEXM_STM32_INTF_RMII)
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+    DIAG_PRINTF("Initialise RMII interface\n");
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+
+    // Configure MAC interface in RMII mode
+#ifdef CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+    HAL_READ_UINT32(CYGHWR_HAL_STM32_AFIO + CYGHWR_HAL_STM32_AFIO_MAPR, reg_val);
+    reg_val |= CYGHWR_HAL_STM32_AFIO_MAPR_ETH_RMII;
+    HAL_WRITE_UINT32(CYGHWR_HAL_STM32_AFIO + CYGHWR_HAL_STM32_AFIO_MAPR, reg_val);
+#else
+    HAL_WRITE_UINT32(CYGHWR_HAL_STM32_SYSCFG + CYGHWR_HAL_STM32_SYSCFG_PMC,
+        CYGHWR_HAL_STM32_SYSCFG_PMC_RMII);
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_RMII_REF_CLK);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_RMII_MDIO);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_RMII_MDC);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_RMII_TX_EN);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_RMII_TXD0);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_RMII_TXD1);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_RMII_CRS_DV);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_RMII_RXD0);
+    CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_HAL_STM32_ETH_RMII_RXD1);
+#else
+#error "Neither MII nor RMII interface defined"
+#endif // CYGSEM_DEVS_ETH_CORTEXM_STM32_INTF_MII
+
+#ifdef CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+    HAL_WRITE_UINT32 (CYGHWR_HAL_STM32_AFIO + CYGHWR_HAL_STM32_RCC_AHBRSTR,
+        CYGHWR_HAL_STM32_RCC_AHBRSTR_ETHMACRST);
+    hal_delay_us(1000);
+    HAL_WRITE_UINT32 (CYGHWR_HAL_STM32_AFIO + CYGHWR_HAL_STM32_RCC_AHBRSTR, 0);
+#else
+    HAL_WRITE_UINT32 (CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_AHB1RSTR,
+        CYGHWR_HAL_STM32_RCC_AHB1RSTR_ETHMACRST);
+    hal_delay_us(1000);
+    HAL_WRITE_UINT32 (CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_AHB1RSTR, 0);
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+    DIAG_PRINTF("Reset ETH DMA module\n");
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+
+    // Software reset of ETH module and wait until it will be done
+    HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMABMR,
+        CYGHWR_HAL_STM32_ETH_DMABMR_SR);
+
+    do {
+        hal_delay_us(100);
+        HAL_READ_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMABMR, reg_val);
+    } while (reg_val & CYGHWR_HAL_STM32_ETH_DMABMR_SR);
+
+    // Setup the PHY
+    CYG_ASSERTC(priv->phy);
+
+    if (!_eth_phy_init(priv->phy))
+    {
+        return (false);
+    }
+
+    reg_val = 0;
+
+    // Get the current mode and print it
+    phy_state = _eth_phy_state(priv->phy);
+
+    if ((phy_state & ETH_PHY_STAT_LINK) != 0) {
+        //Connection mode
+        if((phy_state & ETH_PHY_STAT_FDX)) {
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+            DIAG_PRINTF("Link type : Full Duplex\n");
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+            reg_val |= CYGHWR_HAL_STM32_ETH_MACCR_DM;
+	    } else {
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+            DIAG_PRINTF("Link type : Half Duplex\n");
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+            reg_val &= ~(CYGHWR_HAL_STM32_ETH_MACCR_DM);
+	    }
+	    //Connection speed
+	    if((phy_state & ETH_PHY_STAT_100MB)) {
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+            DIAG_PRINTF("Link speed : 100Mbits/s\n");
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+            reg_val |= CYGHWR_HAL_STM32_ETH_MACCR_FES;
+	    } else {
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+            DIAG_PRINTF("Link speed : 10Mbits/s\n");
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+		    reg_val &= ~(CYGHWR_HAL_STM32_ETH_MACCR_FES);
+	    }
+    } else {
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+	    DIAG_PRINTF("No Link\n");
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+    }
+    // ------------------- Configure MAC module -------------------
+
+    reg_val |= CYGHWR_HAL_STM32_ETH_MACCR_RD;
+
+#ifdef CYGSEM_DEVS_ETH_CORTEXM_STM32_RX_CHECKSUM_VER
+    reg_val |= CYGHWR_HAL_STM32_ETH_MACCR_IPCO;
+#endif
+
+    HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_MACCR, reg_val);
+
+    HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_MACFFR,
+        (CYGHWR_HAL_STM32_ETH_MACFFR_HU |
+        CYGHWR_HAL_STM32_ETH_MACFFR_HM |
+        CYGHWR_HAL_STM32_ETH_MACFFR_HPF));
+
+    HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_MACHTHR, 0);
+    HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_MACHTLR, 0);
+
+    // Give the MAC its ethernet address
+    stm32_set_mac(enaddr);
+
+    // ------------------- Configure DMA module -------------------
+
+#ifdef CYGSEM_DEVS_ETH_CORTEXM_STM32_TX_CHECKSUM_GEN
+    // The checksum generation is enabled only if the
+    // Transmit FIFO is configured for Store-and-forward mode
+    HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMAOMR,
+        CYGHWR_HAL_STM32_ETH_DMAOMR_TSF);
+#else
+    HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMAOMR,
+        CYGHWR_HAL_STM32_ETH_DMAOMR_TTC(3) /* TTC = 256 */);
+#endif
+
+    // Clear any pending interrupt and disable it
+    HAL_WRITE_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_DMASR, 0x1FFFF);
+    HAL_WRITE_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_DMAIER, 0x0);
+
+    // If we are building an interrupt enabled version, install the
+    // interrupt handler
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+    DIAG_PRINTF("Installing Interrupts on IRQ %d\n", priv->intr_vector);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+
+    cyg_drv_interrupt_create(priv->intr_vector,
+        4,
+        (cyg_addrword_t)sc,
+        stm32_eth_isr,
+        eth_drv_dsr,
+        &priv->intr_handle,
+        &priv->intr);
+
+    cyg_drv_interrupt_attach(priv->intr_handle);
+    cyg_drv_interrupt_unmask(priv->intr_vector);
+#endif // CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+
+#ifdef CYGHWR_DEVS_ETH_ARM_STM32_GET_ESA
+    // Get MAC address from RedBoot configuration variables
+    CYGHWR_DEVS_ETH_ARM_STM32_GET_ESA(&enaddr[0], esa_ok);
+    // If this call fails myMacAddr is unchanged and MAC address from
+    // CDL is used
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+    if (!esa_ok)
+    {
+        // Can't figure out ESA
+        DIAG_PRINTF("Warning! ESA unknown\n");
+    }
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+#endif // CYGHWR_DEVS_ETH_ARM_STM32_GET_ESA
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+    DIAG_PRINTF("MAC addr: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        enaddr[0],enaddr[1],enaddr[2],
+        enaddr[3],enaddr[4],enaddr[5]);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+
+    // Initialize Rx/Tx Descriptors list
+    stm32_tdes_init();
+    stm32_rdes_init();
+
+    // Enable transmit and receive state machine of the MAC
+    HAL_READ_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_MACCR, reg_val);
+    reg_val |= CYGHWR_HAL_STM32_ETH_MACCR_TE |
+        CYGHWR_HAL_STM32_ETH_MACCR_RE;
+    HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_MACCR, reg_val);
+
+    // Flush Transmit FIFO
+    HAL_READ_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMAOMR, reg_val);
+    reg_val |= CYGHWR_HAL_STM32_ETH_DMAOMR_FTF;
+    HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMAOMR, reg_val);
+
+    do {
+        HAL_READ_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMAOMR, reg_val);
+    } while (reg_val & CYGHWR_HAL_STM32_ETH_DMAOMR_FTF);
+
+    // Initialize the upper layer driver
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+    DIAG_PRINTF("Initialize the upper layer driver\n");
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+    _eth_drv_init(sc,enaddr);
+
+    return (true);
+}
+
+// This function is called to stop the interface.
+
+static void stm32_eth_stop(struct eth_drv_sc *sc)
+{
+    volatile cyg_uint32 reg_val;
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+    DIAG_PRINTF("Stoping \n");
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+
+    HAL_WRITE_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_DMASR, 0x1FFFF);
+    HAL_WRITE_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_DMAIER, 0x0);
+
+    HAL_READ_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMAOMR, reg_val);
+    reg_val &= ~(CYGHWR_HAL_STM32_ETH_DMAOMR_SR |
+        CYGHWR_HAL_STM32_ETH_DMAOMR_ST);
+    HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMAOMR, reg_val);
+}
+
+// This function is called to "start up" the interface. It may be called
+// multiple times, even when the hardware is already running.
+
+static void stm32_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr,
+        int flags)
+{
+    volatile cyg_uint32 reg_val;
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+    DIAG_PRINTF("Starting \n");
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+
+    // Enable the interrupts we are interested in
+    HAL_WRITE_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_DMAIER,
+        (CYGHWR_HAL_STM32_ETH_DMAIER_RIE |
+        CYGHWR_HAL_STM32_ETH_DMAIER_TIE |
+        CYGHWR_HAL_STM32_ETH_DMAIER_NISE));
+
+    // Start DMA transmission and reception
+    HAL_READ_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMAOMR, reg_val);
+    reg_val |= CYGHWR_HAL_STM32_ETH_DMAOMR_SR |
+        CYGHWR_HAL_STM32_ETH_DMAOMR_ST;
+    HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMAOMR, reg_val);
+}
+
+// This function is called for low level "control" operations
+
+static int stm32_eth_control(struct eth_drv_sc *sc, unsigned long key,
+        void *data, int length)
+{
+    switch (key)
+    {
+        case ETH_DRV_SET_MAC_ADDRESS:
+            if(length >= ETHER_ADDR_LEN) {
+                stm32_eth_stop(sc);
+                cyg_uint8 * enaddr = (cyg_uint8 *)data;
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+                DIAG_PRINTF("Change MAC addr: %02x:%02x:%02x:%02x:%02x:%02x\n",
+                    enaddr[0],enaddr[1],enaddr[2],
+                    enaddr[3],enaddr[4],enaddr[5]);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+                stm32_set_mac(enaddr);
+                stm32_eth_start(sc,enaddr,0);
+                return 0;
+            }
+            return 1;
+
+#ifdef CYGPKG_NET
+        case ETH_DRV_GET_IF_STATS:
+        {
+            // todo
+            return 1;
+        }
+#endif
+
+        default:
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+            DIAG_PRINTF("Unsupported key %lx\n", key);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+           return 1;
+    }
+}
+
+// This routine is called to receive data from the hardware
+
+static void stm32_eth_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list,
+        int sg_len)
+{
+    stm32_eth_priv_t *priv = (stm32_eth_priv_t *)sc->driver_private;
+    int ii, rx_frame_length;
+    cyg_uint32 rx_buffer_pos = 0, data_to_copy;
+    cyg_uint8 * psg_buf, * prx_buff;
+
+    prx_buff = (cyg_uint8 *) rx_buff[priv->curr_rdes_idx];
+    rx_frame_length =
+        CYGHWR_HAL_STM32_ETH_RDES0_FL(rdes[priv->curr_rdes_idx].status) - 4;
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+    DIAG_PRINTF("current rx desc %d, sg_len %d, total_len %d\n",
+        priv->curr_rdes_idx, sg_len, rx_frame_length);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+
+    for(ii = 0; (ii < sg_len) && (rx_frame_length > 0); ii++) {
+        psg_buf = (cyg_uint8 *)(sg_list[ii].buf);
+        data_to_copy = rx_frame_length > sg_list[ii].len ?
+        sg_list[ii].len : rx_frame_length;
+        memcpy(psg_buf, &prx_buff[rx_buffer_pos], data_to_copy);
+        // frame copied
+        rx_buffer_pos += data_to_copy;
+        rx_frame_length -= data_to_copy;
+    }
+}
+
+// This function is called to see if another packet can be sent.
+
+static int stm32_eth_can_send(struct eth_drv_sc *sc)
+{
+    stm32_eth_priv_t *priv = (stm32_eth_priv_t *)sc->driver_private;
+
+    return ((tdes[priv->curr_tdes_idx].status &
+        CYGHWR_HAL_STM32_ETH_TDES0_OWN) ? 0 : 1);
+}
+
+// This routine is called to send data to the hardware - zero copying version
+
+static void stm32_eth_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list,
+        int sg_len, int total_len, unsigned long key)
+{
+    stm32_eth_priv_t *priv = (stm32_eth_priv_t *) sc->driver_private;
+    cyg_uint8 sg_item = 0, sg_len_even, sg_len_rest;
+    volatile cyg_uint32 reg_val;
+
+    CYG_ASSERT(total_len <= ETH_MAX_PACKET_SIZE, "packet too long");
+
+    sg_len_even = sg_len / 2;
+    sg_len_rest = sg_len % 2;
+
+    // Look if it's enough numer of free descriptors
+    CYG_ASSERT((sg_len_even + sg_len_rest) <
+        ((priv->curr_tdes_idx >= priv->prev_tdes_idx) ?
+        (TDES_NUM - (priv->curr_tdes_idx - priv->prev_tdes_idx)) :
+        (priv->prev_tdes_idx - priv->curr_tdes_idx)),
+        "not enough number of descriptors");
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+    DIAG_PRINTF("current tx desc %d, sg_len %d, total_len %d\n",
+        priv->curr_tdes_idx, sg_len, total_len);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+
+    for(sg_item = 0; sg_item < 2 * sg_len_even; sg_item += 2) {
+        tdes[priv->curr_tdes_idx].status &= ETH_DMA_TDES_INIT_MASK;
+        tdes[priv->curr_tdes_idx].buff1_addr = sg_list[sg_item].buf;
+        tdes[priv->curr_tdes_idx].ctrl_len =
+        CYGHWR_HAL_STM32_ETH_TDES1_TBS1(sg_list[sg_item].len);
+        tdes[priv->curr_tdes_idx].buff2_addr = sg_list[sg_item + 1].buf;
+        tdes[priv->curr_tdes_idx].ctrl_len |=
+        CYGHWR_HAL_STM32_ETH_TDES1_TBS2(sg_list[sg_item + 1].len);
+
+        if (sg_item == 0)
+            tdes[priv->curr_tdes_idx].status |=
+                CYGHWR_HAL_STM32_ETH_TDES0_FS;
+
+        if ((sg_item == sg_len - 2) && !sg_len_rest) {
+            tdes[priv->curr_tdes_idx].status |=
+                CYGHWR_HAL_STM32_ETH_TDES0_IC |
+                CYGHWR_HAL_STM32_ETH_TDES0_LS;
+        }
+        // All flags set thus gives the buffer back to DMA
+        tdes[priv->curr_tdes_idx].status |=
+            CYGHWR_HAL_STM32_ETH_TDES0_OWN;
+        priv->tx_key[priv->curr_tdes_idx] = key;
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+        DIAG_PRINTF("tx desc %d : status %x, len1 %d, len2 %d\n",
+            priv->curr_tdes_idx, tdes[priv->curr_tdes_idx].status,
+            sg_list[sg_item].len, sg_list[sg_item + 1].len);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+
+        IF_STM32_INC_DESC(priv->curr_tdes_idx, TDES_NUM);
+    }
+
+    if (sg_len_rest) {
+        tdes[priv->curr_tdes_idx].status &= ETH_DMA_TDES_INIT_MASK;
+        tdes[priv->curr_tdes_idx].buff1_addr = sg_list[sg_item].buf;
+        tdes[priv->curr_tdes_idx].ctrl_len =
+            CYGHWR_HAL_STM32_ETH_TDES1_TBS1(sg_list[sg_item].len);
+        tdes[priv->curr_tdes_idx].buff2_addr = 0;
+        if (sg_item == 0) // Only one sg element to send
+            tdes[priv->curr_tdes_idx].status |=
+                CYGHWR_HAL_STM32_ETH_TDES0_FS;
+
+        // All flags set thus gives the buffer back to DMA
+        tdes[priv->curr_tdes_idx].status |=
+            CYGHWR_HAL_STM32_ETH_TDES0_OWN |
+            CYGHWR_HAL_STM32_ETH_TDES0_IC |
+            CYGHWR_HAL_STM32_ETH_TDES0_LS;
+        priv->tx_key[priv->curr_tdes_idx] = key;
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+        DIAG_PRINTF("tx desc %d : status %x, len1 %d\n",
+        priv->curr_tdes_idx, tdes[priv->curr_tdes_idx].status,
+        sg_list[sg_item].len);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+
+        IF_STM32_INC_DESC(priv->curr_tdes_idx, TDES_NUM);
+    }
+
+    // Starts desc refetch by DMA
+    HAL_READ_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMASR, reg_val);
+    if (reg_val & CYGHWR_HAL_STM32_ETH_DMASR_TBUS) {
+        HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMASR,
+            CYGHWR_HAL_STM32_ETH_DMASR_TBUS);
+        HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMATPDR, 0);
+    }
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+    DIAG_PRINTF("packets put into dma - number of used desc %d\n",
+        sg_len_even + sg_len_rest);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+}
+
+//======================================================================
+
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+static cyg_uint32 stm32_eth_isr (cyg_vector_t vector, cyg_addrword_t data)
+{
+    volatile cyg_uint32 status_reg;
+    cyg_uint32 status = CYG_ISR_HANDLED;
+
+    HAL_READ_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_DMASR, status_reg);
+    if (status_reg & CYGHWR_HAL_STM32_ETH_DMASR_NIS) {
+        cyg_interrupt_mask(vector);
+        status |= CYG_ISR_CALL_DSR;
+    }
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+    // It seems that comes other eth int even it's nothing more
+    // enabled than Trans/Recv interrupt
+    else {
+        DIAG_PRINTF("unexpected eth int - reason 0x%x\n",
+            status_reg);
+    }
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+
+    cyg_interrupt_acknowledge(vector);
+
+    return(status);
+}
+#endif
+
+static void stm32_eth_deliver(struct eth_drv_sc *sc)
+{
+    stm32_eth_priv_t *priv = (stm32_eth_priv_t *) sc->driver_private;
+    volatile cyg_uint32 status_reg;
+    cyg_uint32 rx_frame_length;
+
+    // Get the interrupt status
+    HAL_READ_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_DMASR, status_reg);
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+    DIAG_PRINTF("DMA status 0x%x\n", status_reg);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 1
+
+    if (status_reg & CYGHWR_HAL_STM32_ETH_DMASR_RS) {
+        HAL_WRITE_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_DMASR,
+            CYGHWR_HAL_STM32_ETH_DMASR_NIS |
+            CYGHWR_HAL_STM32_ETH_DMASR_RS);
+
+        // check if desc is ready to service - just in case
+        while (!(rdes[priv->curr_rdes_idx].status &
+            CYGHWR_HAL_STM32_ETH_RDES0_OWN)) {
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+            DIAG_PRINTF("New packet in rx desc %d\n",
+                priv->curr_rdes_idx);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+
+            // and eth frame is ok
+            if (((rdes[priv->curr_rdes_idx].status &
+                    CYGHWR_HAL_STM32_ETH_RDES0_ES) == 0) &&
+                ((rdes[priv->curr_rdes_idx].status &
+                        CYGHWR_HAL_STM32_ETH_RDES0_FS) != 0) &&
+                ((rdes[priv->curr_rdes_idx].status &
+                    CYGHWR_HAL_STM32_ETH_RDES0_LS) != 0) &&
+                (CYGHWR_HAL_STM32_ETH_RDES0_FL(
+                    rdes[priv->curr_rdes_idx].status) != 0)) {
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+                DIAG_PRINTF("Rcv packet status 0x%x\n",
+                    rdes[priv->curr_rdes_idx].status);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+                rx_frame_length =
+                    CYGHWR_HAL_STM32_ETH_RDES0_FL(
+                        rdes[priv->curr_rdes_idx].status) - 4;
+                _eth_drv_recv(sc, rx_frame_length);
+            }
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+            else {
+                DIAG_PRINTF("Error in rcv frame - reason 0x%x\n",
+                    rdes[priv->curr_rdes_idx].status);
+            }
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+
+            // Starts desc refetch by DMA
+            if (status_reg & CYGHWR_HAL_STM32_ETH_DMASR_RBUS) {
+                HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMASR,
+                CYGHWR_HAL_STM32_ETH_DMASR_RBUS);
+                HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMARPDR, 0);
+            }
+
+            // Desc handeled
+            rdes[priv->curr_rdes_idx].status = CYGHWR_HAL_STM32_ETH_RDES0_OWN;
+            IF_STM32_INC_DESC(priv->curr_rdes_idx, RDES_NUM);
+        }
+    }
+
+    if (status_reg & CYGHWR_HAL_STM32_ETH_DMASR_TS) {
+        HAL_WRITE_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_DMASR,
+            CYGHWR_HAL_STM32_ETH_DMASR_NIS | CYGHWR_HAL_STM32_ETH_DMASR_TS);
+
+        // Walk throug descriptor list until find serviced last segment
+        while ((priv->prev_tdes_idx != priv->curr_tdes_idx) &&
+            !(tdes[priv->prev_tdes_idx].status &
+                CYGHWR_HAL_STM32_ETH_TDES0_OWN)) {
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+            DIAG_PRINTF("Sent packet (key 0x%x) from desc %d with status 0x%x\n",
+                (cyg_uint32) priv->tx_key[priv->prev_tdes_idx],
+            priv->prev_tdes_idx, tdes[priv->prev_tdes_idx].status);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 2
+
+            // Starts desc refetch by DMA if it happens error during transmit
+            if (tdes[priv->prev_tdes_idx].status &
+                    CYGHWR_HAL_STM32_ETH_TDES0_ES) {
+                HAL_WRITE_UINT32(ETH_BASE + CYGHWR_HAL_STM32_ETH_DMASR,
+                    CYGHWR_HAL_STM32_ETH_DMASR_TUS);
+                HAL_WRITE_UINT32 (ETH_BASE + CYGHWR_HAL_STM32_ETH_DMATPDR, 0);
+
+#if CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+                DIAG_PRINTF("Error in sending - reason 0x%x\n",
+                    tdes[priv->prev_tdes_idx].status);
+#endif // CYGPKG_DEVS_ETH_CORTEXM_STM32_DEBUG_LEVEL > 0
+            }
+
+            if (tdes[priv->prev_tdes_idx].status &
+                    CYGHWR_HAL_STM32_ETH_TDES0_LS) {
+                if (!(tdes[priv->prev_tdes_idx].status &
+                        CYGHWR_HAL_STM32_ETH_TDES0_ES))
+                    _eth_drv_tx_done(sc,
+                        priv->tx_key[priv->prev_tdes_idx], 0);
+                else
+                    _eth_drv_tx_done(sc,
+                        priv->tx_key[priv->prev_tdes_idx], -1);
+            }
+            IF_STM32_INC_DESC(priv->prev_tdes_idx, TDES_NUM);
+        }
+    }
+
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    cyg_interrupt_unmask(priv->intr_vector);
+#endif
+}
+
+// routine called to handle ethernet controller in polled mode
+static void stm32_eth_poll(struct eth_drv_sc *sc)
+{
+    /* Service the buffers */
+    stm32_eth_deliver(sc);
+}
+
+static int stm32_eth_int_vector(struct eth_drv_sc *sc)
+{
+    return(CYGNUM_HAL_INTERRUPT_ETH);
+}
+
+stm32_eth_priv_t stm32_priv_data =
+{
+    .intr_vector = CYGNUM_HAL_INTERRUPT_ETH,
+    .phy = &stm32_phy
+};
+
+ETH_DRV_SC(stm32_sc,
+           &stm32_priv_data,      // Driver specific data
+           "eth0",                // Name for this interface
+           stm32_eth_start,
+           stm32_eth_stop,
+           stm32_eth_control,
+           stm32_eth_can_send,
+           stm32_eth_send,
+           stm32_eth_recv,
+           stm32_eth_deliver,
+           stm32_eth_poll,
+           stm32_eth_int_vector);
+
+NETDEVTAB_ENTRY(stm32_netdev,
+                "stm32",
+                stm32_eth_init,
+                &stm32_sc);
+
+// EOF if_stm32.c
diff --git a/packages/devs/eth/freescale/enet/current/ChangeLog b/packages/devs/eth/freescale/enet/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/freescale/enet/current/ChangeLog
@@ -0,0 +1,47 @@
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/if_freescale_enet.c: Add clock gating enable. [ Bugzilla 1001814 ]
+
+2012-05-04  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/eth_freescale_enet.cdl:
+	* src/if_freescale_enet.c:
+	Add optional non-cached regions for TCD and buffers [Bugzilla 1001579]
+
+2012-01-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/eth_freescale_enet.cdl:
+	* src/if_freescale_enet.c:
+	Add Redboot ESA support [Bugzilla 1001450]
+
+2011-08-26  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/eth_freescale_enet.cdl:
+	* include/if_freescale_enet_bd.h:
+	* include/if_freescale_enet_io.h:
+	* src/if_freescale_enet.c:
+	New package -- Freescale ENET Ethernet driver.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/eth/freescale/enet/current/cdl/eth_freescale_enet.cdl b/packages/devs/eth/freescale/enet/current/cdl/eth_freescale_enet.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/freescale/enet/current/cdl/eth_freescale_enet.cdl
@@ -0,0 +1,453 @@
+#==========================================================================
+#
+#      eth_freescale_enet.cdl
+#
+#      Ethernet driver for Freescale ENET controller
+#
+#==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                           
+## -------------------------------------------                             
+## This file is part of eCos, the Embedded Configurable Operating System.  
+## Copyright (C) 2011 Free Software Foundation, Inc.                       
+##
+## eCos is free software; you can redistribute it and/or modify it under   
+## the terms of the GNU General Public License as published by the Free    
+## Software Foundation; either version 2 or (at your option) any later     
+## version.                                                                
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT     
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or   
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License   
+## for more details.                                                       
+##
+## You should have received a copy of the GNU General Public License       
+## along with eCos; if not, write to the Free Software Foundation, Inc.,   
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.           
+##
+## As a special exception, if other files instantiate templates or use     
+## macros or inline functions from this file, or you compile this file     
+## and link it with other works to produce a work based on this file,      
+## this file does not by itself cause the resulting work to be covered by  
+## the GNU General Public License. However the source code for this file   
+## must still be made available in accordance with section (3) of the GNU  
+## General Public License v2.                                              
+##
+## This exception does not invalidate any other reasons why a work based   
+## on this file might be covered by the GNU General Public License.        
+## -------------------------------------------                             
+## ####ECOSGPLCOPYRIGHTEND####                                             
+#==========================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+# Contributors:
+# Date:         2011-06-14
+#
+#####DESCRIPTIONEND####
+#
+#========================================================================
+
+
+cdl_package CYGPKG_DEVS_ETH_FREESCALE_ENET {
+    display       "Freescale ENET ethernet driver"
+    parent        CYGPKG_IO_ETH_DRIVERS
+    active_if     CYGPKG_IO_ETH_DRIVERS
+
+    implements    CYGHWR_NET_DRIVERS
+    implements    CYGHWR_NET_DRIVER_ETH0
+
+    requires      CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK
+
+    include_dir   cyg/io/eth
+    description   "
+        Ethernet driver for Freescale ENET controller. Freescale ENET
+        Ethernet controller is found on some Freescale families of
+        controllers such as Kinetis and ColdFire+."
+
+    compile       -library=libextras.a if_freescale_enet.c
+
+    # ENET0 Configuration options --------------------------------------------
+    cdl_option CYGDAT_IO_ETH_IF_FREESCALE_ENET0_NAME {
+        display       "Device name for Freescale ENET0 interface"
+        flavor        data
+        default_value { "\"eth0\"" }
+        description   "
+            This option specifies the device name for Freescale ENET0
+            interface."
+    }
+
+    cdl_option CYGPKG_DEVS_ETH_FREESCALE_ENET0_MACADDR {
+        display "Ethernet station (MAC) address for eth0"
+        flavor  data
+        default_value {"0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC"}
+        description   "
+            The default ethernet station address."
+    }
+
+    cdl_option CYGPKG_DEVS_ETH_FREESCALE_ENET0_INTPRIO {
+        display       "Interrupt priority"
+        flavor        data
+        default_value CYGNUM_DEVS_ETH_FREESCALE_ENET0_INTPRIO_SP
+        description   "
+            This option selects the interrupt priority for the EMAC
+            interrupts."
+    }
+
+    cdl_component CYGHWR_DEVS_ETH_FREESCALE_ENET0_FLOW_CONTROL {
+        display "Congestion control"
+        flavor none
+        no_define
+
+        cdl_option CYGSEM_ETH_FREESCALE_ENET0_RCR_FCE {
+            display "Rx Flow control enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 0
+            description "
+                If enabled ENET shall regard pause frames requests from peer."
+        }
+
+        cdl_option CYGNUM_ETH_FREESCALE_ENET0_OPD_PAUSE_DUR {
+            display "Tx flow control pause duration"
+            flavor data
+            legal_values 0 to 255
+            default_value 0
+            description "
+                Flow control pause legth in pause quanta asked from peer.
+                1 pause quant equals to 512 bit time increments."
+        }
+    }
+
+    cdl_component CYGHWR_DEVS_ETH_FREESCALE_ENET0_BUFFS {
+        display "Buffers"
+        flavor none
+        no_define
+        description "Rx and Tx buffers"
+
+        cdl_option CYGNUM_DEVS_ETH_FREESCALE_ENET0_MAX_FRAME_LEN {
+            display "Maximal frame length"
+            flavor data
+            default_value 1518
+            legal_values 64 to 1522
+        }
+
+        cdl_option CYGNUM_DEVS_ETH_FREESCALE_ENET0_RX_BUFS {
+            display       "Number of RX buffers"
+            flavor        data
+            default_value 8
+            legal_values  2 to 64
+            description   "
+                Number of buffers for receiving. The number of receive
+                buffers also defines the number of descriptors in the
+                descriptor array."
+        }
+
+        cdl_option CYGNUM_DEVS_ETH_FREESCALE_ENET0_RXBUF_SIZE {
+            display "Rx buffer size"
+            flavor data
+            requires { (CYGNUM_DEVS_ETH_FREESCALE_ENET0_RXBUF_SIZE %
+                        CYGNUM_DEVS_ETH_FREESCALE_ENET_RXBUF_ALIGN) == 0
+            }
+            legal_values 16 to 1536
+            default_value {
+                ((CYGNUM_DEVS_ETH_FREESCALE_ENET0_MAX_FRAME_LEN +
+                  CYGNUM_DEVS_ETH_FREESCALE_ENET_RXBUF_ALIGN-1)/
+                  (CYGNUM_DEVS_ETH_FREESCALE_ENET_RXBUF_ALIGN ?
+                   CYGNUM_DEVS_ETH_FREESCALE_ENET_RXBUF_ALIGN : 1)) *
+                CYGNUM_DEVS_ETH_FREESCALE_ENET_RXBUF_ALIGN
+            }
+            description "Rx buffer size must be evenly divisible by 16."
+        }
+
+        cdl_option CYGNUM_DEVS_ETH_FREESCALE_ENET0_TX_BUFS {
+            display       "Number of TX descriptors (buffers)"
+            flavor        data
+            default_value ( CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY ? 8 : \
+                            CYGPKG_IO_ETH_DRIVERS_NET ? 8 : 2 )
+            legal_values   2 to 64
+            description   "
+                Number of transmit buffers or descriptors. We need one
+                descriptor/buffer for each element in the scatter/gather list.
+                If NoCopy is selected then only buffer descriptors are allocated.
+                If Copying is selected (NoCopy == 0) then a buffer is allocated
+                for every buffer descriptor."
+        }
+
+        cdl_option CYGNUM_DEVS_ETH_FREESCALE_ENET0_TXBUF_SIZE {
+            display "Tx buffer size"
+            flavor data
+            active_if { !CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY }
+            requires { (CYGNUM_DEVS_ETH_FREESCALE_ENET_TXBUF_SIZE %
+                        CYGNUM_DEVS_ETH_FREESCALE_ENET_TXBUF_ALIGN) == 0
+            }
+
+            legal_values { 16 to 1536 }
+            default_value {
+                ((CYGNUM_DEVS_ETH_FREESCALE_ENET0_MAX_FRAME_LEN +
+                  CYGNUM_DEVS_ETH_FREESCALE_ENET_TXBUF_ALIGN-1)/
+                  (CYGNUM_DEVS_ETH_FREESCALE_ENET_TXBUF_ALIGN ?
+                   CYGNUM_DEVS_ETH_FREESCALE_ENET_TXBUF_ALIGN : 1)) *
+                CYGNUM_DEVS_ETH_FREESCALE_ENET_TXBUF_ALIGN
+            }
+        }
+    }
+
+    # END of ENET0 specific configuration options. ---------------------------
+
+    # Common ENET options. ---------------------------------------------------
+    # Following configuration options are common to all ENET instances
+
+    cdl_option CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED {
+        display "Enhanced buffer descriptors"
+        flavor bool
+        default_value  0
+    }
+
+    cdl_component CYGHWR_DEVS_ETH_FREESCALE_ENET_ALIGN {
+        display "Buffer/descriptor memory alignment"
+        flavor none
+        no_define
+        description "
+            ENET conatins internal DMA controller that
+            requires certain memory alighment"
+
+        cdl_option CYGNUM_DEVS_ETH_FREESCALE_ENET_RXBD_ALIGN {
+            display "Rx buffer descriptor alignment"
+            flavor data
+            default_value 8
+            legal_values { 8 16 }
+        }
+
+        cdl_option CYGNUM_DEVS_ETH_FREESCALE_ENET_RXBUF_ALIGN {
+            display "Rx buffer alignment"
+            flavor data
+            default_value 16
+            legal_values { 16 }
+        }
+
+        cdl_option CYGNUM_DEVS_ETH_FREESCALE_ENET_TXBD_ALIGN {
+            display "Tx buffer descriptor alignment"
+            flavor data
+            default_value 8
+            legal_values { 8 16 }
+        }
+
+        cdl_option CYGNUM_DEVS_ETH_FREESCALE_ENET_TXBUF_ALIGN {
+            display "Tx buffer alignment"
+            flavor data
+            default_value 8
+            legal_values { 8 16 }
+        }
+    }
+
+    cdl_component CYGSEM_DEVS_ETH_FREESCALE_ENET_PHY {
+        display "RMII or MII Phy"
+        flavor data
+        default_value { "RMII" }
+        legal_values { "RMII" "MII" }
+
+        cdl_option CYGOPT_DEVS_ETH_FREESCALE_ENET_PHY_RXER_USE {
+            display "Enable PHY Rx Error signal"
+            flavor bool
+            default_value 1
+        }
+    }
+
+    cdl_component CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL {
+        display "TCP/IP acceleration"
+        flavor none
+        no_define
+        description "
+            Freescale ENET provides for hardware TCP/IP header checksum
+            generation and check."
+
+        active_if CYGPKG_NET_LWIP
+        requires CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+        requires CYGPKG_LWIP_CHECKSUMS
+
+        cdl_component CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_TX_IP {
+            display "IP Checksum generation"
+            flavor bool
+            default_value 1
+
+            requires { is_active(CYGPKG_LWIP_CHECKSUMS) implies
+                (CYGIMP_LWIP_CHECKSUM_GEN_IP == 0) }
+
+            cdl_option CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_TX_PROT {
+                display "TCP and UDP Checksum generation"
+                flavor bool
+                default_value 1
+
+                requires { is_active(CYGPKG_LWIP_CHECKSUMS) implies
+                    (CYGIMP_LWIP_CHECKSUM_GEN_TCP == 0) }
+
+                requires { is_active(CYGPKG_LWIP_CHECKSUMS) implies
+                    (CYGIMP_LWIP_CHECKSUM_GEN_UDP == 0) }
+            }
+        }
+
+        cdl_component CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_RX_IP {
+            display "IP Checksum check"
+            flavor bool
+            default_value 1
+
+            requires { is_active(CYGPKG_LWIP_CHECKSUMS) implies
+                (CYGIMP_LWIP_CHECKSUM_CHECK_IP == 0) }
+
+            cdl_option CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_RX_PROT {
+                display "TCP and UDP checksum check"
+                flavor bool
+                default_value 1
+
+                requires { is_active(CYGPKG_LWIP_CHECKSUMS) implies
+                    (CYGIMP_LWIP_CHECKSUM_CHECK_TCP == 0) }
+
+                requires { is_active(CYGPKG_LWIP_CHECKSUMS) implies
+                    (CYGIMP_LWIP_CHECKSUM_CHECK_UDP == 0) }
+            }
+        }
+
+        cdl_option CYGSEM_ENET_LWIP_CHECKSUMS {
+            display "lwIP Checksum calculation"
+            flavor none
+            no_define
+            description "
+                Re-enable lwIP software checksum generation/check if
+                hardware generation/check is disabled."
+
+            requires { !CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_TX_IP implies
+                CYGIMP_LWIP_CHECKSUM_GEN_IP == 1 }
+            requires { !CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_TX_PROT implies
+                CYGIMP_LWIP_CHECKSUM_GEN_TCP == 1 }
+            requires { !CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_TX_PROT implies
+                CYGIMP_LWIP_CHECKSUM_GEN_UDP == 1 }
+
+            requires { !CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_RX_IP implies
+                CYGIMP_LWIP_CHECKSUM_CHECK_IP == 1 }
+            requires { !CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_RX_PROT implies
+                CYGIMP_LWIP_CHECKSUM_CHECK_TCP == 1 }
+            requires { !CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_RX_PROT implies
+                CYGIMP_LWIP_CHECKSUM_CHECK_UDP == 1 }
+        }
+    }
+
+    cdl_component CYGSEM_DEVS_ETH_FREESCALE_ENET_1588 {
+        display "IEEE 1588 timers"
+        requires CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+        flavor bool
+        default_value 0
+    }
+
+    cdl_component CYGOPT_DEVS_ETH_FREESCALE_ENET_STATS {
+        display "ENET Error statistics"
+        flavor bool
+        default_value 0
+
+        cdl_option CYGOPT_DEVS_ETH_FREESCALE_ENET_STATS_DEBUG {
+            display "Debug print ENET error statistics"
+            flavor bool
+            default_value 0
+        }
+    }
+
+    cdl_option CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY {
+        display "NullCopy send"
+        flavor bool
+        default_value  0
+        active_if (CYGPKG_NET_LWIP)
+
+        requires { is_active(CYGPKG_NET_LWIP) implies
+                   (CYGNUM_LWIP_MEM_ALIGNMENT >=
+                    CYGNUM_DEVS_ETH_FREESCALE_ENET_TXBUF_ALIGN) }
+
+            description "
+                ENET driver can send buffers 'out of place'
+                (wihout making a private copy), offloading CPU from
+                copying data and saving space for Tx buffers . This is
+                'NullCopy' option, opposite to 'Copying' option where ENET
+                driver has private Tx buffers and requires additional copying
+                operation (by CPU).
+                On the pther hand, 'Copying' option needs no Tx IRQ which may
+                make it better choice than NullCopy if system dominantly sends
+                short messages. Also, ENET has some requiresments for buffer
+                alignment, therefore if upper layer networking stack /
+                application can not guarantee for boundary alignment then
+                'Copying' should be used."
+    }
+
+    cdl_option CYGOPT_DEVS_ETH_FREESCALE_ENET_IRQ_FASTMASK {
+        display "Fast IRQ masking"
+        flavor bool
+        default_value 1
+
+        description "
+            Fast (un)masking operates on bits in ENET's EIR
+            register instead of calling cyg_drv_interrupt_(un)mask.
+            This allows sumultaneous (un)masking of both Tx and Rx
+            interrupts and is prefered mode, but  case of compatibility
+            problems disable fast IRQ mask."
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA {
+        display         "RedBoot manages ESA initialization data"
+        flavor          bool
+        default_value   0
+
+        active_if     CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+        active_if     (CYGPKG_REDBOOT || CYGSEM_HAL_USE_ROM_MONITOR)
+
+        description   "
+            Enabling this option will allow the ethernet station
+            address to be acquired from RedBoot's configuration data,
+            stored in flash memory.  It can be overridden individually
+            by the 'Set the ethernet station address' option for each
+            interface."
+
+
+        cdl_component CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA_VARS {
+            display        "Export RedBoot command to set ESA in FLASH config"
+            flavor         none
+            no_define
+            description "
+                This component contains options which, when enabled, allow
+                RedBoot to support the setting of the ESA in the FLASH
+                configuration. This can then subsequently be accessed by
+                applications using virtual vector calls if those applications
+                are also built with
+                CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA enabled."
+
+            cdl_option CYGSEM_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA_ETH0 {
+                display         "RedBoot manages ESA for eth0"
+                flavor          bool
+                default_value   1
+                active_if       CYGSEM_REDBOOT_FLASH_CONFIG
+                active_if       CYGPKG_REDBOOT_NETWORKING
+            }
+        }
+    }
+
+    cdl_option CYGPKG_DEVS_ETH_FREESCALE_ENET_DEBUG_LEVEL {
+         display "Driver debug output level"
+         flavor  data
+         legal_values { 0 1 2 3 }
+         default_value 0
+         description   "
+             This option specifies the level of debug data output by
+             the Freescale ENET ethernet device driver. A value of 0 signifies
+             no debug data output; 1 signifies normal debug data
+             output; and 2 signifies maximum debug data output."
+    }
+
+    cdl_option  CYGPKG_DEVS_ETH_FREESCALE_ENET_CFLAGS_ADD {
+        display "Additional compiler flags"
+        flavor  data
+        no_define
+        default_value { "-D_KERNEL -D__ECOS" }
+        description   "
+            This option modifies the set of compiler flags for
+            building the Freescale ENET ethernet driver package.
+            These flags are used in addition to the set of global flags."
+    }
+}
+
+# EOF eth_freescale_enet.cdl
diff --git a/packages/devs/eth/freescale/enet/current/include/if_freescale_enet_bd.h b/packages/devs/eth/freescale/enet/current/include/if_freescale_enet_bd.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/freescale/enet/current/include/if_freescale_enet_bd.h
@@ -0,0 +1,209 @@
+#ifndef CYGONCE_FREESCALE_ENET_BD_H
+#define CYGONCE_FREESCALE_ENET_BD_H
+//=============================================================================
+//
+//      freescale_enet_bd.h
+//
+//      Variant specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2011-06-05
+// Purpose:       Freescale ENET buffer descriptors
+// Description:
+// Usage:         #include <cyg/io/freescale_enet_bd.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//---------------------------------------------------------------------------
+// ENET Buffer Descriptors
+// All mrmbers except key must be big endian
+typedef volatile struct enet_bd_s {
+    cyg_uint16  ctrl;            // 00
+    cyg_uint16  len;             // 02
+    cyg_uint8   *buffer_p;       // 04
+#ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+    cyg_uint32  ebd_ctrl;        // 08
+    cyg_uint16  hlen_proto;      // 0c
+    cyg_uint16  payload_csum;    // 0e
+    cyg_uint32  bdu;             // 10
+    cyg_uint32  timestamp_1588;  // 14
+    cyg_uint32  reserved[2];     // 18
+#endif //  CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+} enet_bd_t;
+
+
+#if (CYG_BYTEORDER == CYG_LSBFIRST)
+//======================================================================
+// Little Endian
+//----------------------------------------------------------------------
+
+// ----------------------------------------------------------------------
+// TX Buffer Descriptor Bit Definitions
+
+# define ENET_TXBD_R        0x0080
+# define ENET_TXBD_TO1      0x0040
+# define ENET_TXBD_W        0x0020
+# define ENET_TXBD_TO2      0x0010
+# define ENET_TXBD_L        0x0008
+# define ENET_TXBD_TC       0x0004
+# define ENET_TXBD_ABC      0x0002
+
+// ----------------------------------------------------------------------
+// TX Enhanced BD Bit Definitions
+
+# define ENET_TXBD_INT       0x00000040
+# define ENET_TXBD_TS        0x00000020
+# define ENET_TXBD_PINS      0x00000010
+# define ENET_TXBD_IINS      0x00000008
+# define ENET_TXBD_TXE       0x00800000
+# define ENET_TXBD_UE        0x00200000
+# define ENET_TXBD_EE        0x00100000
+# define ENET_TXBD_FE        0x00080000
+# define ENET_TXBD_LCE       0x00040000
+# define ENET_TXBD_OE        0x00020000
+# define ENET_TXBD_TSE       0x00010000
+
+# define ENET_TXBD_BDU       0x00000080
+
+// ----------------------------------------------------------------------
+// RX Buffer Descriptor Bit Definitions
+// Offset 0 flags - ctrl
+# define ENET_RXBD_E        0x0080
+# define ENET_RXBD_R01      0x0040
+# define ENET_RXBD_W        0x0020
+# define ENET_RXBD_R02      0x0010
+# define ENET_RXBD_L        0x0008
+# define ENET_RXBD_M        0x0001
+# define ENET_RXBD_BC       0x8000
+# define ENET_RXBD_MC       0x4000
+# define ENET_RXBD_LG       0x2000
+# define ENET_RXBD_NO       0x1000
+# define ENET_RXBD_CR       0x0400
+# define ENET_RXBD_OV       0x0200
+# define ENET_RXBD_TR       0x0100
+
+// ----------------------------------------------------------------------
+// RX Enhanced BD Bit Definitions
+
+# define ENET_RXBD_ME       0x00000080
+# define ENET_RXBD_PE       0x00000004
+# define ENET_RXBD_CE       0x00000002
+# define ENET_RXBD_UC       0x00000001
+
+# define ENET_RXBD_INT      0x00008000
+
+# define ENET_RXBD_ICE      0x20000000
+# define ENET_RXBD_PCR      0x10000000
+# define ENET_RXBD_VLAN     0x04000000
+# define ENET_RXBD_IPV6     0x02000000
+# define ENET_RXBD_FRAG     0x01000000
+
+# define ENET_RXBD_BDU      0x00000080
+
+#else //(CYG_BYTEORDER == CYG_LSBFIRST)
+//======================================================================
+// Big Endian
+//----------------------------------------------------------------------
+
+// ----------------------------------------------------------------------
+// TX Buffer Descriptor Bit Definitions
+
+# define ENET_TXBD_R        0x8000
+# define ENET_TXBD_TO1      0x4000
+# define ENET_TXBD_W        0x2000
+# define ENET_TXBD_TO2      0x1000
+# define ENET_TXBD_L        0x0800
+# define ENET_TXBD_TC       0x0400
+# define ENET_TXBD_ABC      0x0200
+
+// ----------------------------------------------------------------------
+// TX Enhanced BD Bit Definitions
+
+# define ENET_TXBD_INT       0x40000000
+# define ENET_TXBD_TS        0x20000000
+# define ENET_TXBD_PINS      0x10000000
+# define ENET_TXBD_IINS      0x08000000
+# define ENET_TXBD_TXE       0x00008000
+# define ENET_TXBD_UE        0x00002000
+# define ENET_TXBD_EE        0x00001000
+# define ENET_TXBD_FE        0x00000800
+# define ENET_TXBD_LCE       0x00000400
+# define ENET_TXBD_OE        0x00000200
+# define ENET_TXBD_TSE       0x00000100
+
+# define ENET_TXBD_BDU       0x80000000
+
+// ----------------------------------------------------------------------
+// RX Buffer Descriptor Bit Definitions
+// Offset 0 flags - ctrl
+# define ENET_RXBD_E        0x8000
+# define ENET_RXBD_R01      0x4000
+# define ENET_RXBD_W        0x2000
+# define ENET_RXBD_R02      0x1000
+# define ENET_RXBD_L        0x0800
+# define ENET_RXBD_M        0x0100
+# define ENET_RXBD_BC       0x0080
+# define ENET_RXBD_MC       0x0040
+# define ENET_RXBD_LG       0x0020
+# define ENET_RXBD_NO       0x0010
+# define ENET_RXBD_CR       0x0004
+# define ENET_RXBD_OV       0x0002
+# define ENET_RXBD_TR       0x0001
+
+// ----------------------------------------------------------------------
+// RX Enhanced BD Bit Definitions
+
+# define ENET_RXBD_ME       0x80000000
+# define ENET_RXBD_PE       0x04000000
+# define ENET_RXBD_CE       0x02000000
+# define ENET_RXBD_UC       0x01000000
+# define ENET_RXBD_INT      0x00800000
+# define ENET_RXBD_ICE      0x00000020
+# define ENET_RXBD_PCR      0x00000010
+# define ENET_RXBD_VLAN     0x00000004
+# define ENET_RXBD_IPV6     0x00000002
+# define ENET_RXBD_FRAG     0x00000001
+
+# define ENET_RXBD_BDU      0x80000000
+
+#endif // (CYG_BYTEORDER == CYG_LSBFIRST)
+
+// EOF freescale_enet_bd.h
+#endif // CYGONCE_FREESCALE_ENET_BD_H
diff --git a/packages/devs/eth/freescale/enet/current/include/if_freescale_enet_io.h b/packages/devs/eth/freescale/enet/current/include/if_freescale_enet_io.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/freescale/enet/current/include/if_freescale_enet_io.h
@@ -0,0 +1,685 @@
+#ifndef CYGONCE_IF_FREESCALE_ENET_IO_H
+#define CYGONCE_IF_FREESCALE_ENET_IO_H
+//=============================================================================
+//
+//      if_freescale_enet_io.h
+//
+//      Variant specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2011-06-05
+// Purpose:       Freescale ENET specific registers
+// Description:
+// Usage:         #include <cyg/io/if_freescale_enet_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+
+//=============================================================================
+// Freescale ENET Ethernet controller
+
+// ENET Register offsets relative to   CYGADDR_IO_ETH_FREESCALE_ENET_BASE
+// Note: CYGADDR_IO_ETH_FREESCALE_ENET_BASE is provided by HAL.
+//       Typically you can find CYGADDR_IO_ETH_FREESCALE_ENET_BASE in var_io.h
+//-----------------------------------------------------------------------------
+// Interrupt Event Register
+#define FREESCALE_ENET_REG_EIR                 0x004
+// Interrupt Mask Register
+#define FREESCALE_ENET_REG_EIMR                0x008
+// Receive Descriptor Active Register
+#define FREESCALE_ENET_REG_RDAR                0x010
+// Transmit Descriptor Active Register
+#define FREESCALE_ENET_REG_TDAR                0x014
+// Ethernet Control Register
+#define FREESCALE_ENET_REG_ECR                 0x024
+// MII Management Frame Register
+#define FREESCALE_ENET_REG_MMFR                0x040
+// MII Speed Control Register
+#define FREESCALE_ENET_REG_MSCR                0x044
+// MIB Control Register
+#define FREESCALE_ENET_REG_MIBC                0x064
+// Receive Control Register
+#define FREESCALE_ENET_REG_RCR                 0x084
+// Transmit Control Register
+#define FREESCALE_ENET_REG_TCR                 0x0C4
+// Physical Address Lower Register
+#define FREESCALE_ENET_REG_PALR                0x0E4
+// Physical Address Upper Register
+#define FREESCALE_ENET_REG_PAUR                0x0E8
+// Opcode/Pause Duration Register
+#define FREESCALE_ENET_REG_OPD                 0x0EC
+// Descriptor Individual Upper Address Register
+#define FREESCALE_ENET_REG_IAUR                0x118
+// Descriptor Individual Lower Address Register
+#define FREESCALE_ENET_REG_IALR                0x11C
+// Descriptor Group Upper Address Register
+#define FREESCALE_ENET_REG_GAUR                0x120
+// Descriptor Group Lower Address Register
+#define FREESCALE_ENET_REG_GALR                0x124
+// Transmit FIFO Watermark Register
+#define FREESCALE_ENET_REG_TFWR                0x144
+// Receive Descriptor Ring Start Register
+#define FREESCALE_ENET_REG_RDSR                0x180
+// Transmit Buffer Descriptor Ring Start Register
+#define FREESCALE_ENET_REG_TDSR                0x184
+// Maximum Receive Buffer Size Register
+#define FREESCALE_ENET_REG_MRBR                0x188
+// Receive FIFO Section Full Threshold
+#define FREESCALE_ENET_REG_RSFL                0x190
+// Receive FIFO Section Empty Threshold
+#define FREESCALE_ENET_REG_RSEM                0x194
+// Receive FIFO Almost Empty Threshold
+#define FREESCALE_ENET_REG_RAEM                0x198
+// Receive FIFO Almost Full Threshold
+#define FREESCALE_ENET_REG_RAFL                0x19C
+// Transmit FIFO Section Empty Threshold
+#define FREESCALE_ENET_REG_TSEM                0x1A0
+// Transmit FIFO Almost Empty Threshold
+#define FREESCALE_ENET_REG_TAEM                0x1A4
+// Transmit FIFO Almost Full Threshold
+#define FREESCALE_ENET_REG_TAFL                0x1A8
+// Transmit Inter-Packet Gap
+#define FREESCALE_ENET_REG_TIPG                0x1AC
+// Frame Truncation Length
+#define FREESCALE_ENET_REG_FTRL                0x1B0
+// Transmit Accelerator Function Configuration
+#define FREESCALE_ENET_REG_TACC                0x1C0
+// Receive Accelerator Function Configuration
+#define FREESCALE_ENET_REG_RACC                0x1C4
+// Count of frames not counted correctly (RMON_T_DROP).
+// NOTE: Counter not implemented (read 0 always) as not applicable.
+#define FREESCALE_ENET_REG_RMON_T_DROP         0x200
+// RMON Tx packet count (RMON_T_PACKETS)
+#define FREESCALE_ENET_REG_RMON_T_PACKETS      0x204
+// RMON Tx Broadcast Packets (RMON_T_BC_PKT)
+#define FREESCALE_ENET_REG_RMON_T_BC_PKT       0x208
+// RMON Tx Multicast Packets (RMON_T_MC_PKT)
+#define FREESCALE_ENET_REG_RMON_T_MC_PKT       0x20C
+// RMON Tx Packets w CRC/Align error (RMON_T_CRC_ALIGN)
+#define FREESCALE_ENET_REG_RMON_T_CRC_ALIGN    0x210
+// RMON Tx Packets < 64 bytes
+#define FREESCALE_ENET_REG_RMON_T_UNDERSIZE    0x214
+// RMON Tx Packets > MAX_FL bytes
+#define FREESCALE_ENET_REG_RMON_T_OVERSIZE     0x218
+// RMON Tx Packets < 64 bytes
+#define FREESCALE_ENET_REG_RMON_T_FRAG         0x21C
+// RMON Tx Packets > MAX_FL bytes
+#define FREESCALE_ENET_REG_RMON_T_JAB          0x220
+// RMON Tx collision count (RMON_T_COL)
+#define FREESCALE_ENET_REG_RMON_T_COL          0x224
+// RMON Tx 64 byte packets (RMON_T_P64)
+#define FREESCALE_ENET_REG_RMON_T_P64          0x228
+// RMON Tx 65 to 127 byte packets (RMON_T_P65TO127)
+#define FREESCALE_ENET_REG_RMON_T_P65TO127     0x22C
+// RMON Tx 128 to 255 byte packets (RMON_T_P128TO255)
+#define FREESCALE_ENET_REG_RMON_T_P128TO255    0x230
+// RMON Tx 256 to 511 byte packets (RMON_T_P256TO511)
+#define FREESCALE_ENET_REG_RMON_T_P256TO511    0x234
+// RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023)
+#define FREESCALE_ENET_REG_RMON_T_P512TO1023   0x238
+// RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047)
+#define FREESCALE_ENET_REG_RMON_T_P1024TO2047  0x23C
+// RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048)
+#define FREESCALE_ENET_REG_RMON_T_P_GTE2048    0x240
+// RMON Tx Octets (RMON_T_OCTETS)
+#define FREESCALE_ENET_REG_RMON_T_OCTETS       0x244
+// Count of frames not counted correctly (IEEE_T_DROP).
+//   NOTE: Counter not implemented (read 0 always) as not applicable.
+#define FREESCALE_ENET_REG_IEEE_T_DROP         0x248
+// Frames Transmitted OK (IEEE_T_FRAME_OK)
+#define FREESCALE_ENET_REG_IEEE_T_FRAME_OK     0x24C
+// Frames Transmitted with Single Collision (IEEE_T_1COL)
+#define FREESCALE_ENET_REG_IEEE_T_1COL         0x250
+// Frames Transmitted with Multiple Collisions (IEEE_T_MCOL)
+#define FREESCALE_ENET_REG_IEEE_T_MCOL         0x254
+// Frames Transmitted after Deferral Delay (IEEE_T_DEF)
+#define FREESCALE_ENET_REG_IEEE_T_DEF          0x258
+// Frames Transmitted with Late Collision (IEEE_T_LCOL)
+#define FREESCALE_ENET_REG_IEEE_T_LCOL         0x25C
+// Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL)
+#define FREESCALE_ENET_REG_IEEE_T_EXCOL        0x260
+// Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR)
+#define FREESCALE_ENET_REG_IEEE_T_MACERR       0x264
+// Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR)
+#define FREESCALE_ENET_REG_IEEE_T_CSERR        0x268
+// Frames Transmitted with SQE Error (IEEE_T_SQE).
+//   NOTE: Counter not implemented (read 0 always)
+//         as no SQE information is available.
+#define FREESCALE_ENET_REG_IEEE_T_SQE          0x26C
+// Flow Control Pause frames transmitted (IEEE_T_FDXFC)
+#define FREESCALE_ENET_REG_IEEE_T_FDXFC        0x270
+// Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK).
+//    NOTE: Counts total octets (includes header and FCS fields).
+#define FREESCALE_ENET_REG_IEEE_T_OCTETS_OK    0x274
+// RMON Rx packet count (RMON_R_PACKETS)
+#define FREESCALE_ENET_REG_RMON_R_PACKETS      0x284
+// RMON Rx Broadcast Packets (RMON_R_BC_PKT)
+#define FREESCALE_ENET_REG_RMON_R_BC_PKT       0x288
+// RMON Rx Multicast Packets (RMON_R_MC_PKT)
+#define FREESCALE_ENET_REG_RMON_R_MC_PKT       0x28C
+// RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN)
+#define FREESCALE_ENET_REG_RMON_R_CRC_ALIGN    0x290
+// RMON Rx Packets < 64 bytes
+#define FREESCALE_ENET_REG_RMON_R_UNDERSIZE    0x294
+// RMON Rx Packets > MAX_FL bytes
+#define FREESCALE_ENET_REG_RMON_R_OVERSIZE     0x298
+// RMON Rx Packets < 64 bytes
+#define FREESCALE_ENET_REG_RMON_R_FRAG         0x29C
+// RMON Rx Packets > MAX_FL bytes
+#define FREESCALE_ENET_REG_RMON_R_JAB          0x2A0
+// Reserved (RMON_R_RESVD_0)
+#define FREESCALE_ENET_REG_RMON_R_RESVD_0      0x2A4
+// RMON Rx 64 byte packets (RMON_R_P64)
+#define FREESCALE_ENET_REG_RMON_R_P64          0x2A8
+// RMON Rx 65 to 127 byte packets (RMON_R_P65TO127)
+#define FREESCALE_ENET_REG_RMON_R_P65TO127     0x2AC
+// RMON Rx 128 to 255 byte packets (RMON_R_P128TO255)
+#define FREESCALE_ENET_REG_RMON_R_P128TO255    0x2B0
+// RMON Rx 256 to 511 byte packets (RMON_R_P256TO511)
+#define FREESCALE_ENET_REG_RMON_R_P256TO511    0x2B4
+// RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023)
+#define FREESCALE_ENET_REG_RMON_R_P512TO1023   0x2B8
+// RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047)
+#define FREESCALE_ENET_REG_RMON_R_P1024TO2047  0x2BC
+// RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048)
+#define FREESCALE_ENET_REG_RMON_R_P_GTE2048    0x2C0
+// RMON Rx Octets (RMON_R_OCTETS)
+#define FREESCALE_ENET_REG_RMON_R_OCTETS       0x2C4
+// Count of frames not counted correctly (IEEE_R_DROP).
+//    NOTE: Counter increments if a frame with valid/
+//          missing SFD character is detected and has been dropped.
+//          None of the other counters increments if
+//          this counter increments.
+#define FREESCALE_ENET_REG_RMON_R_DROP         0x2C8
+// Frames Received OK (IEEE_R_FRAME_OK)
+#define FREESCALE_ENET_REG_RMON_R_FRAME_OK     0x2CC
+// Frames Received with CRC Error (IEEE_R_CRC)
+#define FREESCALE_ENET_REG_IEEE_R_CRC          0x2D0
+// Frames Received with Alignment Error (IEEE_R_ALIGN)
+#define FREESCALE_ENET_REG_IEEE_R_ALIGN        0x2D4
+// Receive Fifo Overflow count (IEEE_R_MACERR)
+#define FREESCALE_ENET_REG_IEEE_R_MACERR       0x2D8
+// Flow Control Pause frames received (IEEE_R_FDXFC)
+#define FREESCALE_ENET_REG_IEEE_R_FDXFC        0x2DC
+// Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK).
+//    Counts total octets (includes header and FCS fields).
+#define FREESCALE_ENET_REG_IEEE_R_OCTETS_OK    0x2E0
+// Timer Control Register
+#define FREESCALE_ENET_REG_ATCR                0x400
+// Timer Value Register
+#define FREESCALE_ENET_REG_ATVR                0x404
+// Timer Offset Register
+#define FREESCALE_ENET_REG_ATOFF               0x408
+// Timer Period Register
+#define FREESCALE_ENET_REG_ATPER               0x40C
+// Timer Correction Register
+#define FREESCALE_ENET_REG_ATCOR               0x410
+// Time-Stamping Clock Period Register
+#define FREESCALE_ENET_REG_ATINC               0x414
+// Timestamp of Last Transmitted Frame
+#define FREESCALE_ENET_REG_ATSTMP              0x418
+// Timer Global Status Register
+#define FREESCALE_ENET_REG_TGSR                0x604
+
+// IEEE 1588 Timers
+// Timer 0 Control Status Register
+#define FREESCALE_ENET_REG_TCSR0               0x608
+// Timer 0Control Capture Register
+#define FREESCALE_ENET_REG_TCCR0               0x60c
+// Timer 1 Control Status Register
+#define FREESCALE_ENET_REG_TCSR1               0x610
+// Timer 1 Control Capture Register
+#define FREESCALE_ENET_REG_TCCR1               0x614
+// Timer 2 Control Status Register
+#define FREESCALE_ENET_REG_TCSR2               0x618
+// Timer 2 Control Capture Register
+#define FREESCALE_ENET_REG_TCCR2               0x61C
+// Timer 3 Control Status Register
+#define FREESCALE_ENET_REG_TCSR3               0x620
+// Timer 3 Control Capture Register
+#define FREESCALE_ENET_REG_TCCR3               0x624
+
+
+
+// ----------------------------------------------------------------------------
+// ENET Register Masks
+
+// EIR Bit Fields
+#define FREESCALE_ENET_EIR_TS_TIMER_M                  0x8000
+#define FREESCALE_ENET_EIR_TS_TIMER_S                  15
+#define FREESCALE_ENET_EIR_TS_AVAIL_M                  0x10000
+#define FREESCALE_ENET_EIR_TS_AVAIL_S                  16
+#define FREESCALE_ENET_EIR_WAKEUP_M                    0x20000
+#define FREESCALE_ENET_EIR_WAKEUP_S                    17
+#define FREESCALE_ENET_EIR_PLR_M                       0x40000
+#define FREESCALE_ENET_EIR_PLR_S                       18
+#define FREESCALE_ENET_EIR_UN_M                        0x80000
+#define FREESCALE_ENET_EIR_UN_S                        19
+#define FREESCALE_ENET_EIR_RL_M                        0x100000
+#define FREESCALE_ENET_EIR_RL_S                        20
+#define FREESCALE_ENET_EIR_LC_M                        0x200000
+#define FREESCALE_ENET_EIR_LC_S                        21
+#define FREESCALE_ENET_EIR_EBERR_M                     0x400000
+#define FREESCALE_ENET_EIR_EBERR_S                     22
+#define FREESCALE_ENET_EIR_MII_M                       0x800000
+#define FREESCALE_ENET_EIR_MII_S                       23
+#define FREESCALE_ENET_EIR_RXB_M                       0x1000000
+#define FREESCALE_ENET_EIR_RXB_S                       24
+#define FREESCALE_ENET_EIR_RXF_M                       0x2000000
+#define FREESCALE_ENET_EIR_RXF_S                       25
+#define FREESCALE_ENET_EIR_TXB_M                       0x4000000
+#define FREESCALE_ENET_EIR_TXB_S                       26
+#define FREESCALE_ENET_EIR_TXF_M                       0x8000000
+#define FREESCALE_ENET_EIR_TXF_S                       27
+#define FREESCALE_ENET_EIR_GRA_M                       0x10000000
+#define FREESCALE_ENET_EIR_GRA_S                       28
+#define FREESCALE_ENET_EIR_BABT_M                      0x20000000
+#define FREESCALE_ENET_EIR_BABT_S                      29
+#define FREESCALE_ENET_EIR_BABR_M                      0x40000000
+#define FREESCALE_ENET_EIR_BABR_S                      30
+// EIMR Bit Fields
+#define FREESCALE_ENET_EIMR_TS_TIMER_M                 0x8000
+#define FREESCALE_ENET_EIMR_TS_TIMER_S                 15
+#define FREESCALE_ENET_EIMR_TS_AVAIL_M                 0x10000
+#define FREESCALE_ENET_EIMR_TS_AVAIL_S                 16
+#define FREESCALE_ENET_EIMR_WAKEUP_M                   0x20000
+#define FREESCALE_ENET_EIMR_WAKEUP_S                   17
+#define FREESCALE_ENET_EIMR_PLR_M                      0x40000
+#define FREESCALE_ENET_EIMR_PLR_S                      18
+#define FREESCALE_ENET_EIMR_UN_M                       0x80000
+#define FREESCALE_ENET_EIMR_UN_S                       19
+#define FREESCALE_ENET_EIMR_RL_M                       0x100000
+#define FREESCALE_ENET_EIMR_RL_S                       20
+#define FREESCALE_ENET_EIMR_LC_M                       0x200000
+#define FREESCALE_ENET_EIMR_LC_S                       21
+#define FREESCALE_ENET_EIMR_EBERR_M                    0x400000
+#define FREESCALE_ENET_EIMR_EBERR_S                    22
+#define FREESCALE_ENET_EIMR_MII_M                      0x800000
+#define FREESCALE_ENET_EIMR_MII_S                      23
+#define FREESCALE_ENET_EIMR_RXB_M                      0x1000000
+#define FREESCALE_ENET_EIMR_RXB_S                      24
+#define FREESCALE_ENET_EIMR_RXF_M                      0x2000000
+#define FREESCALE_ENET_EIMR_RXF_S                      25
+#define FREESCALE_ENET_EIMR_TXB_M                      0x4000000
+#define FREESCALE_ENET_EIMR_TXB_S                      26
+#define FREESCALE_ENET_EIMR_TXF_M                      0x8000000
+#define FREESCALE_ENET_EIMR_TXF_S                      27
+#define FREESCALE_ENET_EIMR_GRA_M                      0x10000000
+#define FREESCALE_ENET_EIMR_GRA_S                      28
+#define FREESCALE_ENET_EIMR_BABT_M                     0x20000000
+#define FREESCALE_ENET_EIMR_BABT_S                     29
+#define FREESCALE_ENET_EIMR_BABR_M                     0x40000000
+#define FREESCALE_ENET_EIMR_BABR_S                     30
+// RDAR Bit Fields
+#define FREESCALE_ENET_RDAR_RDAR_M                     0x1000000
+#define FREESCALE_ENET_RDAR_RDAR_S                     24
+// TDAR Bit Fields
+#define FREESCALE_ENET_TDAR_TDAR_M                     0x1000000
+#define FREESCALE_ENET_TDAR_TDAR_S                     24
+// ECR Bit Fields
+#define FREESCALE_ENET_ECR_RESET_M                     0x1
+#define FREESCALE_ENET_ECR_RESET_S                     0
+#define FREESCALE_ENET_ECR_ETHEREN_M                   0x2
+#define FREESCALE_ENET_ECR_ETHEREN_S                   1
+#define FREESCALE_ENET_ECR_MAGICEN_M                   0x4
+#define FREESCALE_ENET_ECR_MAGICEN_S                   2
+#define FREESCALE_ENET_ECR_SLEEP_M                     0x8
+#define FREESCALE_ENET_ECR_SLEEP_S                     3
+#define FREESCALE_ENET_ECR_EN1588_M                    0x10
+#define FREESCALE_ENET_ECR_EN1588_S                    4
+#define FREESCALE_ENET_ECR_DBGEN_M                     0x40
+#define FREESCALE_ENET_ECR_DBGEN_S                     6
+#define FREESCALE_ENET_ECR_STOPEN_M                    0x80
+#define FREESCALE_ENET_ECR_STOPEN_S                    7
+// MMFR Bit Fields
+#define FREESCALE_ENET_MMFR_DATA_M                     0xFFFF
+#define FREESCALE_ENET_MMFR_DATA_S                     0
+#define FREESCALE_ENET_MMFR_DATA(__val)                 \
+        VALUE_(FREESCALE_ENET_MMFR_DATA_S, __val)
+#define FREESCALE_ENET_MMFR_TA_M                       0x30000
+#define FREESCALE_ENET_MMFR_TA_S                       16
+#define FREESCALE_ENET_MMFR_TA(__val)                   \
+        VALUE_(FREESCALE_ENET_MMFR_TA_S, __val)
+#define FREESCALE_ENET_MMFR_RA_M                       0x7C0000
+#define FREESCALE_ENET_MMFR_RA_S                       18
+#define FREESCALE_ENET_MMFR_RA(__val)                   \
+        VALUE_(FREESCALE_ENET_MMFR_RA_S, __val)
+#define FREESCALE_ENET_MMFR_PA_M                       0xF800000
+#define FREESCALE_ENET_MMFR_PA_S                       23
+#define FREESCALE_ENET_MMFR_PA(__val)                   \
+        VALUE_(FREESCALE_ENET_MMFR_PA_S, __val)
+#define FREESCALE_ENET_MMFR_OP_M                       0x30000000
+#define FREESCALE_ENET_MMFR_OP_S                       28
+#define FREESCALE_ENET_MMFR_OP(__val)                   \
+        VALUE_(FREESCALE_ENET_MMFR_OP_S, __val)
+#define FREESCALE_ENET_MMFR_ST_M                       0xC0000000
+#define FREESCALE_ENET_MMFR_ST_S                       30
+#define FREESCALE_ENET_MMFR_ST(__val)                   \
+        VALUE_(FREESCALE_ENET_MMFR_ST_S, __val)
+// MSCR Bit Fields
+#define FREESCALE_ENET_MSCR_MII_SPEED_M                0x7E
+#define FREESCALE_ENET_MSCR_MII_SPEED_S                1
+#define FREESCALE_ENET_MSCR_MII_SPEED(__val)            \
+        VALUE_(FREESCALE_ENET_MSCR_MII_SPEED_S, __val)
+#define FREESCALE_ENET_MSCR_DIS_PRE_M                  0x80
+#define FREESCALE_ENET_MSCR_DIS_PRE_S                  7
+#define FREESCALE_ENET_MSCR_HOLDTIME_M                 0x700
+#define FREESCALE_ENET_MSCR_HOLDTIME_S                 8
+#define FREESCALE_ENET_MSCR_HOLDTIME(__val)             \
+        VALUE_(FREESCALE_ENET_MSCR_HOLDTIME_S, __val)
+// MIBC Bit Fields
+#define FREESCALE_ENET_MIBC_MIB_CLEAR_M                0x20000000
+#define FREESCALE_ENET_MIBC_MIB_CLEAR_S                29
+#define FREESCALE_ENET_MIBC_MIB_IDLE_M                 0x40000000
+#define FREESCALE_ENET_MIBC_MIB_IDLE_S                 30
+#define FREESCALE_ENET_MIBC_MIB_DIS_M                  0x80000000
+#define FREESCALE_ENET_MIBC_MIB_DIS_S                  31
+// RCR Bit Fields
+#define FREESCALE_ENET_RCR_LOOP_M                      0x1
+#define FREESCALE_ENET_RCR_LOOP_S                      0
+#define FREESCALE_ENET_RCR_DRT_M                       0x2
+#define FREESCALE_ENET_RCR_DRT_S                       1
+#define FREESCALE_ENET_RCR_MII_MODE_M                  0x4
+#define FREESCALE_ENET_RCR_MII_MODE_S                  2
+#define FREESCALE_ENET_RCR_PROM_M                      0x8
+#define FREESCALE_ENET_RCR_PROM_S                      3
+#define FREESCALE_ENET_RCR_BC_REJ_M                    0x10
+#define FREESCALE_ENET_RCR_BC_REJ_S                    4
+#define FREESCALE_ENET_RCR_FCE_M                       0x20
+#define FREESCALE_ENET_RCR_FCE_S                       5
+#define FREESCALE_ENET_RCR_RMII_MODE_M                 0x100
+#define FREESCALE_ENET_RCR_RMII_MODE_S                 8
+#define FREESCALE_ENET_RCR_RMII_10T_M                  0x200
+#define FREESCALE_ENET_RCR_RMII_10T_S                  9
+#define FREESCALE_ENET_RCR_PADEN_M                     0x1000
+#define FREESCALE_ENET_RCR_PADEN_S                     12
+#define FREESCALE_ENET_RCR_PAUFWD_M                    0x2000
+#define FREESCALE_ENET_RCR_PAUFWD_S                    13
+#define FREESCALE_ENET_RCR_CRCFWD_M                    0x4000
+#define FREESCALE_ENET_RCR_CRCFWD_S                    14
+#define FREESCALE_ENET_RCR_CFEN_M                      0x8000
+#define FREESCALE_ENET_RCR_CFEN_S                      15
+#define FREESCALE_ENET_RCR_MAX_FL_M                    0x3FFF0000
+#define FREESCALE_ENET_RCR_MAX_FL_S                    16
+#define FREESCALE_ENET_RCR_MAX_FL(__val)                \
+        VALUE_(FREESCALE_ENET_RCR_MAX_FL_S, __val)
+#define FREESCALE_ENET_RCR_NLC_M                       0x40000000
+#define FREESCALE_ENET_RCR_NLC_S                       30
+#define FREESCALE_ENET_RCR_GRS_M                       0x80000000
+#define FREESCALE_ENET_RCR_GRS_S                       31
+// TCR Bit Fields
+#define FREESCALE_ENET_TCR_GTS_M                       0x1
+#define FREESCALE_ENET_TCR_GTS_S                       0
+#define FREESCALE_ENET_TCR_FDEN_M                      0x4
+#define FREESCALE_ENET_TCR_FDEN_S                      2
+#define FREESCALE_ENET_TCR_TFC_PAUSE_M                 0x8
+#define FREESCALE_ENET_TCR_TFC_PAUSE_S                 3
+#define FREESCALE_ENET_TCR_RFC_PAUSE_M                 0x10
+#define FREESCALE_ENET_TCR_RFC_PAUSE_S                 4
+#define FREESCALE_ENET_TCR_ADDSEL_M                    0xE0
+#define FREESCALE_ENET_TCR_ADDSEL_S                    5
+#define FREESCALE_ENET_TCR_ADDSEL(__val)                \
+        VALUE_(FREESCALE_ENET_TCR_ADDSEL_S, __val)
+#define FREESCALE_ENET_TCR_ADDINS_M                    0x100
+#define FREESCALE_ENET_TCR_ADDINS_S                    8
+#define FREESCALE_ENET_TCR_CRCFWD_M                    0x200
+#define FREESCALE_ENET_TCR_CRCFWD_S                    9
+// PALR Bit Fields
+#define FREESCALE_ENET_PALR_PADDR1_M                   0xFFFFFFFF
+#define FREESCALE_ENET_PALR_PADDR1_S                   0
+#define FREESCALE_ENET_PALR_PADDR1(__val)               \
+        VALUE_(FREESCALE_ENET_PALR_PADDR1_S, __val)
+// PAUR Bit Fields
+#define FREESCALE_ENET_PAUR_TYPE_M                     0xFFFF
+#define FREESCALE_ENET_PAUR_TYPE_S                     0
+#define FREESCALE_ENET_PAUR_TYPE(__val)                 \
+        VALUE_(FREESCALE_ENET_PAUR_TYPE_S, __val)
+#define FREESCALE_ENET_PAUR_PADDR2_M                   0xFFFF0000
+#define FREESCALE_ENET_PAUR_PADDR2_S                   16
+#define FREESCALE_ENET_PAUR_PADDR2(__val)               \
+        VALUE_(FREESCALE_ENET_PAUR_PADDR2_S, __val)
+// OPD Bit Fields
+#define FREESCALE_ENET_OPD_PAUSE_DUR_M                 0xFFFF
+#define FREESCALE_ENET_OPD_PAUSE_DUR_S                 0
+#define FREESCALE_ENET_OPD_PAUSE_DUR(__val)             \
+        VALUE_(FREESCALE_ENET_OPD_PAUSE_DUR_S, __val)
+#define FREESCALE_ENET_OPD_OPCODE_M                    0xFFFF0000
+#define FREESCALE_ENET_OPD_OPCODE_S                    16
+#define FREESCALE_ENET_OPD_OPCODE(__val)                \
+        VALUE_(FREESCALE_ENET_OPD_OPCODE_S, __val)
+// IAUR Bit Fields
+#define FREESCALE_ENET_IAUR_IADDR1_M                   0xFFFFFFFF
+#define FREESCALE_ENET_IAUR_IADDR1_S                   0
+#define FREESCALE_ENET_IAUR_IADDR1(__val)               \
+        VALUE_(FREESCALE_ENET_IAUR_IADDR1_S, __val)
+// IALR Bit Fields
+#define FREESCALE_ENET_IALR_IADDR2_M                   0xFFFFFFFF
+#define FREESCALE_ENET_IALR_IADDR2_S                   0
+#define FREESCALE_ENET_IALR_IADDR2(__val)               \
+        VALUE_(FREESCALE_ENET_IALR_IADDR2_S, __val)
+// GAUR Bit Fields
+#define FREESCALE_ENET_GAUR_GADDR1_M                   0xFFFFFFFF
+#define FREESCALE_ENET_GAUR_GADDR1_S                   0
+#define FREESCALE_ENET_GAUR_GADDR1(__val)               \
+        VALUE_(FREESCALE_ENET_GAUR_GADDR1_S, __val)
+// GALR Bit Fields
+#define FREESCALE_ENET_GALR_GADDR2_M                   0xFFFFFFFF
+#define FREESCALE_ENET_GALR_GADDR2_S                   0
+#define FREESCALE_ENET_GALR_GADDR2(__val)               \
+        VALUE_(FREESCALE_ENET_GALR_GADDR2_S, __val)
+// TFWR Bit Fields
+#define FREESCALE_ENET_TFWR_TFWR_M                     0x3F
+#define FREESCALE_ENET_TFWR_TFWR_S                     0
+#define FREESCALE_ENET_TFWR_TFWR(__val)                 \
+        VALUE_(FREESCALE_ENET_TFWR_TFWR_S, __val)
+#define FREESCALE_ENET_TFWR_STRFWD_M                   0x100
+#define FREESCALE_ENET_TFWR_STRFWD_S                   8
+
+#define FREESCALE_ENET_TFWR_TFWR_64                   0x0
+#define FREESCALE_ENET_TFWR_TFWR_64A                  0x1
+#define FREESCALE_ENET_TFWR_TFWR_128                  0x2
+#define FREESCALE_ENET_TFWR_TFWR_192                  0x3
+#define FREESCALE_ENET_TFWR_TFWR_4032                 0x3F
+// RDSR Bit Fields
+#define FREESCALE_ENET_RDSR_R_DES_START_M              0xFFFFFFF8
+#define FREESCALE_ENET_RDSR_R_DES_START_S              3
+#define FREESCALE_ENET_RDSR_R_DES_START(__val)          \
+        VALUE_(FREESCALE_ENET_RDSR_R_DES_S, __val)
+// TDSR Bit Fields
+#define FREESCALE_ENET_TDSR_X_DES_START_M              0xFFFFFFF8
+#define FREESCALE_ENET_TDSR_X_DES_START_S              3
+#define FREESCALE_ENET_TDSR_X_DES_START(__val)          \
+        VALUE_(FREESCALE_ENET_TDSR_X_DES_S, __val)
+// MRBR Bit Fields
+#define FREESCALE_ENET_MRBR_R_BUF_SIZE_M               0x3FF0
+#define FREESCALE_ENET_MRBR_R_BUF_SIZE_S               4
+#define FREESCALE_ENET_MRBR_R_BUF_SIZE(__val)           \
+        VALUE_(FREESCALE_ENET_MRBR_R_BUF_S, __val)
+// RSFL Bit Fields
+#define FREESCALE_ENET_RSFL_RX_SECTION_FULL_M          0xFF
+#define FREESCALE_ENET_RSFL_RX_SECTION_FULL_S          0
+#define FREESCALE_ENET_RSFL_RX_SECTION_FULL(__val)      \
+        VALUE_(FREESCALE_ENET_RSFL_RX_S, __val)
+// RSEM Bit Fields
+#define FREESCALE_ENET_RSEM_RX_SECTION_EMPTY_M         0xFF
+#define FREESCALE_ENET_RSEM_RX_SECTION_EMPTY_S         0
+#define FREESCALE_ENET_RSEM_RX_SECTION_EMPTY(__val)     \
+        VALUE_(FREESCALE_ENET_RSEM_RX_S, __val)
+// RAEM Bit Fields
+#define FREESCALE_ENET_RAEM_RX_ALMOST_EMPTY_M          0xFF
+#define FREESCALE_ENET_RAEM_RX_ALMOST_EMPTY_S          0
+#define FREESCALE_ENET_RAEM_RX_ALMOST_EMPTY(__val)      \
+        VALUE_(FREESCALE_ENET_RAEM_RX_ALMOST_EMPTY_S, __val)
+// RAFL Bit Fields
+#define FREESCALE_ENET_RAFL_RX_ALMOST_FULL_M           0xFF
+#define FREESCALE_ENET_RAFL_RX_ALMOST_FULL_S           0
+#define FREESCALE_ENET_RAFL_RX_ALMOST_FULL(__val)       \
+        VALUE_(FREESCALE_ENET_RAFL_RX_ALMOST_FULL_S, __val)
+// TSEM Bit Fields
+#define FREESCALE_ENET_TSEM_TX_SECTION_EMPTY_M         0xFF
+#define FREESCALE_ENET_TSEM_TX_SECTION_EMPTY_S         0
+#define FREESCALE_ENET_TSEM_TX_SECTION_EMPTY(__val)     \
+        VALUE_(FREESCALE_ENET_TSEM_TX_S, __val)
+// TAEM Bit Fields
+#define FREESCALE_ENET_TAEM_TX_ALMOST_EMPTY_M          0xFF
+#define FREESCALE_ENET_TAEM_TX_ALMOST_EMPTY_S          0
+#define FREESCALE_ENET_TAEM_TX_ALMOST_EMPTY(__val)      \
+        VALUE_(FREESCALE_ENET_TAEM_TX_ALMOST_EMPTY_S, __val)
+// TAFL Bit Fields
+#define FREESCALE_ENET_TAFL_TX_ALMOST_FULL_M           0xFF
+#define FREESCALE_ENET_TAFL_TX_ALMOST_FULL_S           0
+#define FREESCALE_ENET_TAFL_TX_ALMOST_FULL(__val)       \
+        VALUE_(FREESCALE_ENET_TAFL_TX_ALMOST_FULL_S, __val)
+// TIPG Bit Fields
+#define FREESCALE_ENET_TIPG_IPG_M                      0x1F
+#define FREESCALE_ENET_TIPG_IPG_S                      0
+#define FREESCALE_ENET_TIPG_IPG(__val)                  \
+        VALUE_(FREESCALE_ENET_TIPG_IPG_S, __val)
+// FTRL Bit Fields
+#define FREESCALE_ENET_FTRL_TRUNC_FL_M                 0x3FFF
+#define FREESCALE_ENET_FTRL_TRUNC_FL_S                 0
+#define FREESCALE_ENET_FTRL_TRUNC_FL(__val)             \
+        VALUE_(FREESCALE_ENET_FTRL_TRUNC_FL_S, __val)
+// TACC Bit Fields
+#define FREESCALE_ENET_TACC_S16_M                      0x1
+#define FREESCALE_ENET_TACC_S16_S                      0
+#define FREESCALE_ENET_TACC_IPCHK_M                    0x8
+#define FREESCALE_ENET_TACC_IPCHK_S                    3
+#define FREESCALE_ENET_TACC_PROCHK_M                   0x10
+#define FREESCALE_ENET_TACC_PROCHK_S                   4
+// RACC Bit Fields
+#define FREESCALE_ENET_RACC_PADREM_M                   0x1
+#define FREESCALE_ENET_RACC_PADREM_S                   0
+#define FREESCALE_ENET_RACC_IPDIS_M                    0x2
+#define FREESCALE_ENET_RACC_IPDIS_S                    1
+#define FREESCALE_ENET_RACC_PRODIS_M                   0x4
+#define FREESCALE_ENET_RACC_PRODIS_S                   2
+#define FREESCALE_ENET_RACC_LINEDIS_M                  0x40
+#define FREESCALE_ENET_RACC_LINEDIS_S                  6
+#define FREESCALE_ENET_RACC_S16_M                      0x80
+#define FREESCALE_ENET_RACC_S16_S                      7
+// ATCR Bit Fields
+#define FREESCALE_ENET_ATCR_EN_M                       0x1
+#define FREESCALE_ENET_ATCR_EN_S                       0
+#define FREESCALE_ENET_ATCR_OFFEN_M                    0x4
+#define FREESCALE_ENET_ATCR_OFFEN_S                    2
+#define FREESCALE_ENET_ATCR_OFFRST_M                   0x8
+#define FREESCALE_ENET_ATCR_OFFRST_S                   3
+#define FREESCALE_ENET_ATCR_PEREN_M                    0x10
+#define FREESCALE_ENET_ATCR_PEREN_S                    4
+#define FREESCALE_ENET_ATCR_PINPER_M                   0x80
+#define FREESCALE_ENET_ATCR_PINPER_S                   7
+#define FREESCALE_ENET_ATCR_RESTART_M                  0x200
+#define FREESCALE_ENET_ATCR_RESTART_S                  9
+#define FREESCALE_ENET_ATCR_CAPTURE_M                  0x800
+#define FREESCALE_ENET_ATCR_CAPTURE_S                  11
+#define FREESCALE_ENET_ATCR_SLAVE_M                    0x2000
+#define FREESCALE_ENET_ATCR_SLAVE_S                    13
+// ATVR Bit Fields
+#define FREESCALE_ENET_ATVR_ATIME_M                    0xFFFFFFFF
+#define FREESCALE_ENET_ATVR_ATIME_S                    0
+#define FREESCALE_ENET_ATVR_ATIME(__val)                \
+        VALUE_(FREESCALE_ENET_ATVR_ATIME_S, __val)
+// ATOFF Bit Fields
+#define FREESCALE_ENET_ATOFF_OFFSET_M                  0xFFFFFFFF
+#define FREESCALE_ENET_ATOFF_OFFSET_S                  0
+#define FREESCALE_ENET_ATOFF_OFFSET(__val)              \
+        VALUE_(FREESCALE_ENET_ATOFF_OFFSET_S, __val)
+// ATPER Bit Fields
+#define FREESCALE_ENET_ATPER_PERIOD_M                  0xFFFFFFFF
+#define FREESCALE_ENET_ATPER_PERIOD_S                  0
+#define FREESCALE_ENET_ATPER_PERIOD(__val)              \
+        VALUE_(FREESCALE_ENET_ATPER_PERIOD_S, __val)
+// ATCOR Bit Fields
+#define FREESCALE_ENET_ATCOR_COR_M                     0x7FFFFFFF
+#define FREESCALE_ENET_ATCOR_COR_S                     0
+#define FREESCALE_ENET_ATCOR_COR(__val)                 \
+        VALUE_(FREESCALE_ENET_ATCOR_COR_S, __val)
+// ATINC Bit Fields
+#define FREESCALE_ENET_ATINC_INC_M                     0x7F
+#define FREESCALE_ENET_ATINC_INC_S                     0
+#define FREESCALE_ENET_ATINC_INC(__val)                 \
+        VALUE_(FREESCALE_ENET_ATINC_INC_S, __val)
+#define FREESCALE_ENET_ATINC_INC_CORR_M                0x7F00
+#define FREESCALE_ENET_ATINC_INC_CORR_S                8
+#define FREESCALE_ENET_ATINC_INC_CORR(__val)            \
+        VALUE_(FREESCALE_ENET_ATINC_INC_CORR_S, __val)
+// ATSTMP Bit Fields
+#define FREESCALE_ENET_ATSTMP_TIMESTAMP_M              0xFFFFFFFF
+#define FREESCALE_ENET_ATSTMP_TIMESTAMP_S              0
+#define FREESCALE_ENET_ATSTMP_TIMESTAMP(__val)          \
+        VALUE_(FREESCALE_ENET_ATSTMP_TIMESTAMP_S, __val)
+// TGSR Bit Fields
+#define FREESCALE_ENET_TGSR_TF0_M                      0x1
+#define FREESCALE_ENET_TGSR_TF0_S                      0
+#define FREESCALE_ENET_TGSR_TF1_M                      0x2
+#define FREESCALE_ENET_TGSR_TF1_S                      1
+#define FREESCALE_ENET_TGSR_TF2_M                      0x4
+#define FREESCALE_ENET_TGSR_TF2_S                      2
+#define FREESCALE_ENET_TGSR_TF3_M                      0x8
+#define FREESCALE_ENET_TGSR_TF3_S                      3
+// TCSR Bit Fields
+#define FREESCALE_ENET_TCSR_TDRE_M                     0x1
+#define FREESCALE_ENET_TCSR_TDRE_S                     0
+#define FREESCALE_ENET_TCSR_TMODE_M                    0x3C
+#define FREESCALE_ENET_TCSR_TMODE_S                    2
+#define FREESCALE_ENET_TCSR_TMODE(__val)                \
+        VALUE_(FREESCALE_ENET_TCSR_TMODE_S, __val)
+#define FREESCALE_ENET_TCSR_TIE_M                      0x40
+#define FREESCALE_ENET_TCSR_TIE_S                      6
+#define FREESCALE_ENET_TCSR_TF_M                       0x80
+#define FREESCALE_ENET_TCSR_TF_S                       7
+// TCCR Bit Fields
+#define FREESCALE_ENET_TCCR_TCC_M                      0xFFFFFFFF
+#define FREESCALE_ENET_TCCR_TCC_S                      0
+#define FREESCALE_ENET_TCCR_TCC(__val)                  \
+        VALUE_(FREESCALE_ENET_TCCR_TCC_S, __val)
+
+#define FREESCALE_ENET_EIR_ERROR     \
+       (FREESCALE_ENET_EIR_PLR_M   | \
+        FREESCALE_ENET_EIR_UN_M    | \
+        FREESCALE_ENET_EIR_RL_M    | \
+        FREESCALE_ENET_EIR_LC_M    | \
+        FREESCALE_ENET_EIR_EBERR_M | \
+        FREESCALE_ENET_EIR_BABT_M  | \
+        FREESCALE_ENET_EIR_BABR_M)
+
+// EOF if_freescale_enet_io.h
+#endif // CYGONCE_IF_FREESCALE_ENET_IO_H
diff --git a/packages/devs/eth/freescale/enet/current/src/if_freescale_enet.c b/packages/devs/eth/freescale/enet/current/src/if_freescale_enet.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/freescale/enet/current/src/if_freescale_enet.c
@@ -0,0 +1,1616 @@
+//==========================================================================
+//
+//      if_freescale_enet.c
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+// Contributors:
+// Date:         2011-06-04
+// Description:  Hardware driver for Freescale ENET peripheral
+//
+//               This driver was originally written for Kinetis and may
+//               require some modifications to work on other Freescale
+//               families such as ColdFire+.
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+#include <pkgconf/devs_eth_freescale_enet.h>
+#include <pkgconf/io_eth_drivers.h>
+
+#if defined(CYGPKG_REDBOOT)
+# include <pkgconf/redboot.h>
+#endif
+
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/hal/hal_diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/diag.h>
+#include <cyg/io/eth/netdev.h>
+#include <cyg/io/eth/eth_drv.h>
+#include <cyg/io/eth/eth_drv_stats.h>
+#include <cyg/io/eth_phy.h>
+#include <errno.h>
+#include <string.h>
+
+#ifdef CYGPKG_NET
+# include <pkgconf/net.h>
+# include <net/if.h>  //Needed for struct ifnet
+#endif
+
+#include <cyg/hal/hal_endian.h>
+#include <cyg/io/eth/if_freescale_enet_bd.h>
+#include <cyg/io/eth/if_freescale_enet_io.h>
+
+#if defined CYGHWR_HAL_ENET_TCD_SECTION || defined CYGHWR_HAL_ENET_BUF_SECTION
+# include <cyg/infra/cyg_type.h>
+#endif
+// Some debugging helpers ---------------------------------------------------
+
+#define DEBUG_ENET CYGPKG_DEVS_ETH_FREESCALE_ENET_DEBUG_LEVEL
+
+#if DEBUG_ENET >= 3
+# define debug3_printf(args...) diag_printf(args)
+#else
+# define debug3_printf(args...)
+#endif
+
+#if DEBUG_ENET >= 2
+# define debug2_printf(args...) diag_printf(args)
+#else
+# define debug2_printf(args...)
+#endif
+
+#if DEBUG_ENET >= 1
+# define debug1_printf(args...) diag_printf(args)
+#else
+# define debug1_printf(args...)
+#endif
+
+
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+#define enet_eth_send enet_eth_send_nocopy
+#define enet_eth_deliver enet_eth_deliver_nocopy
+#else // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+#define enet_eth_send enet_eth_send_copying
+#define enet_eth_deliver enet_eth_deliver_copying
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+
+// Some delay macros ------------------------------------------------------
+// Busy waiting delay
+#define ENET_WAIT_US(__us) HAL_DELAY_US(__us)
+// Delays / Timeouts
+#define FREESCALE_ENET_RESET_DELAY   1      // Enet reset [us]
+#define FREESCALE_ENET_ENABLE_DELAY  1      // Enet eneble [us]
+
+#define FREESCALE_ENET_PHY_INIT_TOUT 100    // Phy start up [ms]
+#define FREESCALE_ENET_MII_WRITE_TOUT 2000  // Phy write timeout [us]
+#define FREESCALE_ENET_MII_READ_TOUT  2000  // Phy read timeout [us]
+
+#ifndef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+// If kernel is available ENET_ETH_WAIT should be a normal,
+// not a busy-waiting delay.
+# ifdef CYGFUN_KERNEL_API_C
+#  define ENET_ETH_WAIT(__tick)  cyg_thread_delay(__tick)
+# elif !defined(CYGPKG_KERNEL)
+#  define ENET_ETH_WAIT(__ms)  HAL_DELAY_US(__ms * 1000)
+# else
+#  error Can not define ENET_ETH_WAIT().
+# endif
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+// Resources provided by HAL ==============================================
+// Ethernet RAM and DMA configuration --------------------------------------
+
+// Buffer descriptor memory section
+#ifdef CYGHWR_HAL_ENET_TCD_SECTION
+# define ENET_RAM_TCD_SECTION CYGBLD_ATTRIB_SECTION(CYGHWR_HAL_ENET_TCD_SECTION)
+#else
+# define ENET_RAM_TCD_SECTION
+#endif // CYGHWR_HAL_ENET_TCD_SECTION
+
+// Buffer memory section
+#ifdef CYGHWR_HAL_ENET_BUF_SECTION
+# define ENET_RAM_BUF_SECTION CYGBLD_ATTRIB_SECTION(CYGHWR_HAL_ENET_BUF_SECTION)
+#else
+# define ENET_RAM_BUF_SECTION
+#endif // CYGHWR_HAL_ENET_BUF_SECTION
+
+// IRQ masking --------------------------------------------------------------
+//
+
+#define FREESCALE_ENET_EIR_MASK_M (FREESCALE_ENET_EIR_TXF_M |     \
+            FREESCALE_ENET_EIR_TXB_M | FREESCALE_ENET_EIR_RXF_M | \
+                                   FREESCALE_ENET_EIR_RXB_M)
+
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+# define FREESCALE_ENET_EIMR_MASK_M  (FREESCALE_ENET_EIMR_RXF_M | \
+                                     FREESCALE_ENET_EIMR_TXF_M)
+#else // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+# define FREESCALE_ENET_EIMR_MASK_M  FREESCALE_ENET_EIMR_RXF_M
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+
+// Buffer configuration macros ----------------------------------------------------
+//
+
+#define ENET_RXBD_ALIGN \
+            CYGBLD_ATTRIB_ALIGN(CYGNUM_DEVS_ETH_FREESCALE_ENET_RXBD_ALIGN)
+#define ENET_TXBD_ALIGN \
+            CYGBLD_ATTRIB_ALIGN(CYGNUM_DEVS_ETH_FREESCALE_ENET_TXBD_ALIGN)
+#define ENET_RXBUF_ALIGN \
+            CYGBLD_ATTRIB_ALIGN(CYGNUM_DEVS_ETH_FREESCALE_ENET_RXBUF_ALIGN)
+#define ENET_TXBUF_ALIGN \
+            CYGBLD_ATTRIB_ALIGN(CYGNUM_DEVS_ETH_FREESCALE_ENET_TXBUF_ALIGN)
+
+#ifdef  CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+# define ENET_TXKEY_FLAG  ENET_TXBD_TO2
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+
+// ENET statistics ----------------------------------------------------
+//
+
+#ifdef CYGOPT_DEVS_ETH_FREESCALE_ENET_STATS_DEBUG
+# define ENET_STAT_PRINTF(args...) diag_printf(args)
+#else //CYGOPT_DEVS_ETH_FREESCALE_ENET_STATS_DEBUG
+# define ENET_STAT_PRINTF(args...)
+#endif // CYGOPT_DEVS_ETH_FREESCALE_ENET_STATS_DEBUG
+
+#ifdef CYGOPT_DEVS_ETH_FREESCALE_ENET_STATS
+typedef struct freescale_enet_stats_s {
+    cyg_uint32 TR;     // Truncated
+    cyg_uint32 CR;     // CRC or frame error
+    cyg_uint32 OV;     // Overrun
+    cyg_uint32 LG;     // Frame length violation
+    cyg_uint32 NO;     // Non octet aligned frame
+#ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+    cyg_uint32 ME;     // MAC error
+    cyg_uint32 CE;     // Receive CRC error
+    cyg_uint32 PE;     // PHY error
+    cyg_uint32 FRAG;   // IPv4 Fragment
+    cyg_uint32 ICE;    // IP header chechsum error
+    cyg_uint32 PCR;    // Protocol checksum error
+#endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+} freescale_enet_stats_t;
+
+void freescale_enet_stats_init(freescale_enet_stats_t *stats_p) {
+    stats_p->TR = 0;
+    stats_p->CR = 0;
+    stats_p->OV = 0;
+    stats_p->LG = 0;
+    stats_p->NO = 0;
+#ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+    stats_p->ME = 0;
+    stats_p->CE = 0;
+    stats_p->PE = 0;
+    stats_p->FRAG = 0;
+    stats_p->ICE = 0;
+    stats_p->PCR = 0;
+#endif //CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+}
+
+# define FREESCALE_ENET_STATS_INIT(__poin) freescale_enet_stats_init(__poin)
+# define FREESCALE_ENET_STAT_COUNT(__poin,__val) (__poin->enet_stats.__val++)
+
+# define FREESCALE_ENET_STAT_DO(__ctrl,__poin,__val)                \
+CYG_MACRO_START                                                     \
+    if(__ctrl & ENET_RXBD_##__val){                                 \
+        FREESCALE_ENET_STAT_COUNT(__poin,__val);                    \
+        ENET_STAT_PRINTF(#__val "(%d) ", __poin->enet_stats.__val); \
+    }                                                               \
+CYG_MACRO_END
+
+#else
+
+# define FREESCALE_ENET_STATS_INIT(__poin)
+# define FREESCALE_ENET_STAT_COUNT(_poin,_val)
+# define FREESCALE_ENET_STAT_DO(__ctrl,__poin,__val)
+
+#endif // CYGOPT_DEVS_ETH_FREESCALE_ENET_STATS
+
+// --------------------------------------------------------------
+// RedBoot configuration options for managing ESAs for us
+
+// Decide whether to have redboot config vars for it...
+#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYGPKG_REDBOOT_NETWORKING)
+#include <redboot.h>
+#include <flash_config.h>
+
+#ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA_ETH0
+RedBoot_config_option("Network hardware address [MAC] for eth0",
+                      eth0_esa_data,
+                      ALWAYS_ENABLED, true,
+                      CONFIG_ESA, 0);
+#endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA_ETH0
+#endif  // CYGPKG_REDBOOT_NETWORKING && CYGSEM_REDBOOT_FLASH_CONFIG
+
+// and initialization code to read them
+// - independent of whether we are building RedBoot right now:
+#ifdef CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA
+#include <cyg/hal/hal_if.h>
+#ifndef CONFIG_ESA
+    #define CONFIG_ESA (6)
+#endif
+
+#define CYGHWR_DEVS_ETH_FREESCALE_ENET_GET_ESA( mac_address, ok )        \
+  CYG_MACRO_START                                                     \
+  ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,     \
+                                    "eth0_esa_data",                  \
+                                    mac_address,                      \
+                                    CONFIG_ESA);                      \
+  CYG_MACRO_END
+#endif // CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA
+
+
+// ENET device ===============================================================
+// Freescale ENET driver private data ----------------------------------------
+
+typedef struct freescale_enet_priv_t {
+    CYG_ADDRWORD enet_base;               // ENET base address
+    eth_phy_access_t *phy_p;              // PHY access
+    cyg_uint16 max_frame_len;             // Maximal frame length
+    cyg_uint8 rxbd_num;                   // Number of Rx buffer descriptors
+    cyg_uint8 txbd_num;                   // Number of Tx buffer descriptors
+    cyg_uint8 pins_n;                     // Number of (R)MII pins
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    cyg_uint8 txbd_avail;                 // Avalable Tx buffer descriptors
+    cyg_uint8 txkey_num;                  // Number of Tx key entries
+    cyg_uint8 txbd_can_send_min;          // Minimal number of avail
+#else // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    cyg_uint8 res0;                       // Reserved
+    cyg_uint16 txbuf_size;                // Tx buffer size
+    cyg_uint8  *txbuf_p;                  // Tx buffer pool
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    cyg_uint16 rxbuf_size;                // Rx buffer size
+    cyg_uint8 fc_pause;                   // Flow control pause length
+    cyg_uint8 flags;                      // Various flags
+    cyg_uint8 *rxbuf_p;                   // Rx buffer pool
+    enet_bd_t *rxbd_pool_p;               // Rx buffer descriptor pool
+    enet_bd_t *txbd_pool_p;               // TX buffer descriptor poll
+    enet_bd_t *rxbd_p;                    // Current Rx BD
+    enet_bd_t *txbd_head_p;               // Current Tx BD head
+    enet_bd_t *txbd_tail_p;               // Current Tx BD tail
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    cyg_uint32 *txkey_pool_p;             // Tx key queue pool
+    cyg_uint32 *txkey_head_p;             // Last Txkey entry
+    cyg_uint32 *txkey_tail_p;             // Last Txkey released
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    cyg_uint32 clock;                     // Clock gating
+    const cyg_uint32 *pins_p;             // (R)MII pin configuration data
+    cyg_uint8 *enaddr;                    // Default ethernet (MAC) address
+    cyg_uint32 rx_intr_vector;
+    cyg_uint32 rx_intr_prio;
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    cyg_interrupt rx_interrupt;
+    cyg_handle_t  rx_interrupt_handle;
+#endif // CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    cyg_uint32 tx_intr_vector;
+    cyg_uint32 tx_intr_prio;
+# ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    cyg_interrupt tx_interrupt;
+    cyg_handle_t  tx_interrupt_handle;
+# endif // CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+#ifdef CYGOPT_DEVS_ETH_FREESCALE_ENET_STATS
+    freescale_enet_stats_t enet_stats;
+#endif // CYGOPT_DEVS_ETH_FREESCALE_ENET_STATS
+} freescale_enet_priv_t;
+
+// Forward declarations ======================================================
+
+static void enet_write_phy(int reg_addr, int phy_addr, unsigned short data);
+static bool enet_read_phy(int reg_addr, int phy_addr, unsigned short *data_p);
+static void enet_init_phy(void);
+static void enet_eth_phy_set(freescale_enet_priv_t *enet_priv_p);
+static bool eth_phy_init_wait(eth_phy_access_t *phy_p, cyg_uint32 ms);
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+static cyg_uint32 enet_eth_isr(cyg_vector_t vector, cyg_addrword_t data);
+#endif
+
+// Device instances ===========================================================
+//
+
+// ENET0 ======================================================================
+// (R)MII pins - Provided by HAL ----------------------------------------------
+
+static const cyg_uint32 const enet0_pins[] = {
+    // Both RMII and MII interface
+    CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDIO,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDC,
+#ifdef CYGOPT_DEVS_ETH_FREESCALE_ENET_PHY_RXER_USE
+    CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXER,
+#endif
+    CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD1,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD0,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXEN,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD0,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD1,
+#ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_PHY_RMII
+    // RMII interface only
+    CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_CRS_DV
+#else
+    // MII interface only
+    CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD3,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD2,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXCLK,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD2,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXCLK,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD3,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_CRS,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_MIIO_TXER,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_COL
+#endif
+#ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+    ,
+    // IEEE 1588 timers
+    CYGHWR_IO_FREESCALE_ENET0_PIN_1588_CLKIN,
+
+    CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3,
+
+    CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2,
+    CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3
+#endif
+};
+
+// Buffer and buffer descriptor memory --------------------------------------
+
+// Buffer descriptors
+enet_bd_t enet0_rxbd_pool[CYGNUM_DEVS_ETH_FREESCALE_ENET0_RX_BUFS]
+ENET_RAM_TCD_SECTION ENET_RXBD_ALIGN;
+enet_bd_t enet0_txbd_pool[CYGNUM_DEVS_ETH_FREESCALE_ENET0_TX_BUFS]
+                         ENET_RAM_TCD_SECTION ENET_TXBD_ALIGN;
+
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+// Tx key queue
+cyg_uint32 enet0_txkey_pool[CYGNUM_DEVS_ETH_FREESCALE_ENET0_TX_BUFS]
+                         ENET_RAM_TCD_SECTION;
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+// Buffers
+cyg_uint8 enet0_rxbuf[CYGNUM_DEVS_ETH_FREESCALE_ENET0_RX_BUFS *
+                      CYGNUM_DEVS_ETH_FREESCALE_ENET0_RXBUF_SIZE]
+                      ENET_RXBUF_ALIGN ENET_RAM_BUF_SECTION;
+#ifndef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+cyg_uint8 enet0_txbuf[CYGNUM_DEVS_ETH_FREESCALE_ENET0_TX_BUFS *
+                      CYGNUM_DEVS_ETH_FREESCALE_ENET0_TXBUF_SIZE]
+                      ENET_TXBUF_ALIGN ENET_RAM_BUF_SECTION;
+#endif //  CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+#ifdef  CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+# if CYGNUM_DEVS_ETH_FREESCALE_ENET0_TX_BUFS >= 8
+#  define ENET0_TXBD_CAN_SEND_MIN 3
+# elif CYGNUM_DEVS_ETH_FREESCALE_ENET0_TX_BUFS >= 6
+#  define ENET0_TXBD_CAN_SEND_MIN 2
+# else
+#  define ENET0_TXBD_CAN_SEND_MIN 1
+# endif
+#endif
+
+// PHY interface entry -----------------------------------------------------
+static cyg_uint8 enet0_macaddr[16] =
+                           {CYGPKG_DEVS_ETH_FREESCALE_ENET0_MACADDR};
+
+//
+
+ETH_PHY_REG_LEVEL_ACCESS_FUNS(freescale_enet0_phy,
+                              enet_init_phy,
+                              NULL,
+                              enet_write_phy,
+                              enet_read_phy);
+
+// ENET0 device private data -------------------------------------------------
+freescale_enet_priv_t enet0_eth0_priv = {
+    .enet_base = CYGADDR_IO_ETH_FREESCALE_ENET0_BASE,
+    .phy_p       = &freescale_enet0_phy,
+    .max_frame_len = CYGNUM_DEVS_ETH_FREESCALE_ENET0_MAX_FRAME_LEN,
+    .rxbd_num    = CYGNUM_DEVS_ETH_FREESCALE_ENET0_RX_BUFS,
+    .rxbuf_size  = CYGNUM_DEVS_ETH_FREESCALE_ENET0_RXBUF_SIZE,
+    .rxbuf_p     = enet0_rxbuf,
+    .txbd_num    = CYGNUM_DEVS_ETH_FREESCALE_ENET0_TX_BUFS,
+    .rxbd_pool_p = enet0_rxbd_pool,
+    .txbd_pool_p = enet0_txbd_pool,
+    .rxbd_p      = NULL,
+    .txbd_head_p = NULL,
+    .txbd_tail_p = NULL,
+    .fc_pause    = CYGNUM_ETH_FREESCALE_ENET0_OPD_PAUSE_DUR,
+    .flags       = CYGSEM_ETH_FREESCALE_ENET0_RCR_FCE,
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    .txbd_avail  = CYGNUM_DEVS_ETH_FREESCALE_ENET0_TX_BUFS,
+    .txkey_pool_p = enet0_txkey_pool,
+    .txkey_num    = CYGNUM_DEVS_ETH_FREESCALE_ENET0_TX_BUFS,
+    .txbd_can_send_min = ENET0_TXBD_CAN_SEND_MIN,
+    .txkey_head_p = NULL,
+    .txkey_tail_p = NULL,
+#else
+    .txbuf_size   = CYGNUM_DEVS_ETH_FREESCALE_ENET0_TXBUF_SIZE,
+    .txbuf_p      = enet0_txbuf,
+#endif //  CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    .clock       = CYGHWR_IO_FREESCALE_ENET0_CLOCK,
+    .pins_p      = enet0_pins,
+    .pins_n      = sizeof(enet0_pins)/sizeof(enet0_pins[0]),
+    .enaddr   = enet0_macaddr,
+    .rx_intr_vector = CYGNUM_FREESCALE_ENET0_RECEIVE_INT_VECTOR,
+    .rx_intr_prio = CYGPKG_DEVS_ETH_FREESCALE_ENET0_INTPRIO
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    , .tx_intr_vector = CYGNUM_FREESCALE_ENET0_TRANSMIT_INT_VECTOR,
+    .tx_intr_prio = CYGPKG_DEVS_ETH_FREESCALE_ENET0_INTPRIO
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+};
+
+// Ethernet interface entry -------------------------------------------------
+ETH_DRV_SC(enet0_eth0_sc,
+           &enet0_eth0_priv,                      // Driver specific data
+           CYGDAT_IO_ETH_IF_FREESCALE_ENET0_NAME, // Name for this interface
+           enet_eth_start,
+           enet_eth_stop,
+           enet_eth_control,
+           enet_eth_can_send,
+           enet_eth_send,
+           enet_eth_recv,
+           enet_eth_deliver,
+           enet_eth_poll,
+           enet_eth_int_vector);
+
+NETDEVTAB_ENTRY(enet0_netdev,
+                "enet0_eth",
+                enet_eth_init,
+                &enet0_eth0_sc);
+
+// End ENET0 =================================================================
+
+
+// Driver code ===============================================================
+//
+
+// Buffer and buffer descriptor (BD) macros ==================================
+// BD Iterators --------------------------------------------------------------
+
+// Generic BD iterator template used by Rx and Tx iterators
+#define ENET_NEXT_BD(__bd_p,__priv_p,__wrap,__pool)    \
+CYG_MACRO_START                                        \
+        __bd_p = __bd_p->ctrl & __wrap ?               \
+              __priv_p->__pool##_pool_p : __bd_p + 1;  \
+CYG_MACRO_END
+
+// Rx BD Iterator ------------------------------------------
+#define ENET_RXBD_NEXT(__bd_p,__priv_p) \
+        ENET_NEXT_BD(__bd_p, __priv_p, ENET_RXBD_W, rxbd)
+
+// Tx BD Iterator
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+// Tx BD Iterator - NoCopy option --------------------------
+# define ENET_BD_AVAIL_INC(__priv_p) (__priv_p->txbd_avail++)
+# define ENET_BD_AVAIL_DEC(__priv_p) (__priv_p->txbd_avail--)
+
+# define ENET_TXBD_ALLOC(__bd_p,__priv_p) \
+CYG_MACRO_START \
+    ENET_NEXT_BD(__bd_p, __priv_p, ENET_TXBD_W, txbd); \
+    ENET_BD_AVAIL_DEC(__priv_p); \
+CYG_MACRO_END
+
+# define ENET_TXBD_FREE(__bd_p,__priv_p) \
+CYG_MACRO_START \
+    ENET_NEXT_BD(__bd_p, __priv_p, ENET_TXBD_W, txbd); \
+    ENET_BD_AVAIL_INC(__priv_p); \
+CYG_MACRO_END
+
+# define ENET_TXBD_TRYFREE(__bd_p,__priv_p) \
+CYG_MACRO_START \
+    ENET_NEXT_BD(__bd_p, __priv_p, ENET_TXBD_W, txbd); \
+CYG_MACRO_END
+
+// Tx key iterator -----------------------------------------
+# define ENET_TXKEY_NEXT(__bd_p,__priv_p)                                   \
+CYG_MACRO_START                                                             \
+    __bd_p = (__bd_p == (__priv_p->txkey_pool_p + __priv_p->txkey_num-1)) ? \
+    __priv_p->txkey_pool_p : __bd_p + 1;                                    \
+CYG_MACRO_END
+
+#else // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+// Tx BD Iterator - Copying option -------------------------
+# define ENET_TXBD_NEXT(__bd_p,__priv_p) \
+        ENET_NEXT_BD(__bd_p, __priv_p, ENET_TXBD_W, txbd)
+
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+// Buffer descriptor initialization functions ================================
+//
+
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+# define ENET_RESET_BD_TX(__priv_p) \
+CYG_MACRO_START \
+    __priv_p->txbd_head_p = __priv_p->txbd_pool_p + __priv_p->txbd_num - 1; \
+    __priv_p->txbd_tail_p = __priv_p->txbd_head_p; \
+    __priv_p->txbd_avail = __priv_p->txbd_num; \
+    __priv_p->txkey_head_p = __priv_p->txkey_pool_p + __priv_p->txkey_num - 1; \
+    __priv_p->txkey_tail_p = __priv_p->txkey_head_p; \
+CYG_MACRO_END
+#else // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+# define ENET_RESET_BD_TX(__priv_p) \
+CYG_MACRO_START \
+    __priv_p->txbd_head_p = __priv_p->txbd_pool_p + __priv_p->txbd_num - 1; \
+    __priv_p->txbd_tail_p = __priv_p->txbd_head_p; \
+CYG_MACRO_END
+#endif //
+
+#define ENET_INIT_BD_TX(__priv_p) ENET_RESET_BD_TX(__priv_p)
+
+
+// Initialize a buffer descriptor --------------------------------------------
+// Generic function for initialization of a buffer descriptor
+
+static void
+enet_init_bd(enet_bd_t *bd_p, cyg_uint32 bd_size, cyg_uint16 cntrl_init,
+             cyg_uint16 cntrl_wrap, cyg_uint8 *buff_p, cyg_uint32 buf_size
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+             , cyg_uint32 *key_p
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+#ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+             , cyg_uint32 ebd_ctrl
+#endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+             )
+{
+    enet_bd_t *bd_end;
+    debug1_printf("ENET: Inint_bd:\n");
+    for(bd_end = bd_p + bd_size; bd_p < bd_end; bd_p++){
+        debug1_printf("ENET:    %p -> ", bd_p);
+        bd_p->ctrl = cntrl_init;
+        bd_p->len = 0;
+        bd_p->buffer_p = (cyg_uint8 *)CYG_CPU_TO_BE32((cyg_uint32)buff_p);
+        debug1_printf("cntrl=0x%04x len=%d buffer=%p[%p]",
+                      bd_p->ctrl, bd_p->len, bd_p->buffer_p, buff_p);
+        buff_p += (buf_size);
+#ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+        bd_p->ebd_ctrl = ebd_ctrl;
+        bd_p->hlen_proto = 0;
+        bd_p->payload_csum = 0;
+        bd_p->bdu = ENET_TXBD_BDU;
+        bd_p->timestamp_1588 = 0;
+        bd_p->reserved[0] = 0;
+        bd_p->reserved[1] = 0;
+#endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+        if(key_p) {
+            *key_p = 0;
+            debug1_printf(" tx_key[%p]=%x", key_p, *key_p);
+            key_p++;
+        }
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+        debug1_printf("\n");
+    }
+    debug1_printf("ENET: end, bd_p=%p\n", bd_p);
+    bd_p--;
+    bd_p->ctrl |=  cntrl_wrap;
+    debug1_printf("ENET:    %p -> ", bd_p);
+    debug1_printf("cntrl=0x%04x len=%d buffer=%p\n",
+                  bd_p->ctrl, bd_p->len, bd_p->buffer_p);
+}
+
+
+// Initialize buffer descriptors and buffers --------------------------------
+//
+
+static void
+enet_init_buffers(freescale_enet_priv_t *enet_priv_p)
+{
+    CYG_ADDRWORD enet_base = enet_priv_p->enet_base;
+
+    // Initialize receive descriptor ring
+    enet_priv_p->rxbd_p = enet_priv_p->rxbd_pool_p;
+    enet_init_bd(enet_priv_p->rxbd_pool_p, enet_priv_p->rxbd_num,
+                 ENET_RXBD_E, ENET_RXBD_W, enet_priv_p->rxbuf_p, enet_priv_p->rxbuf_size
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+                 , NULL
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+#ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+                 , ENET_RXBD_INT
+#endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+                 );
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_RDSR,
+                     (cyg_uint32)enet_priv_p->rxbd_pool_p);
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_MRBR, enet_priv_p->rxbuf_size);
+
+    // Initialize transmit descriptor ring
+    ENET_INIT_BD_TX(enet_priv_p);
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    enet_init_bd(enet_priv_p->txbd_pool_p, enet_priv_p->txbd_num, 0, ENET_TXBD_W,
+                 NULL, 0, enet_priv_p->txkey_pool_p
+#else // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    enet_init_bd(enet_priv_p->txbd_pool_p, enet_priv_p->txbd_num, 0, ENET_TXBD_W,
+                 enet_priv_p->txbuf_p, enet_priv_p->txbuf_size
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+#ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+                 , ENET_TXBD_INT
+# ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_TX_IP
+                 | ENET_TXBD_IINS
+# endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_TX_IP
+# ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_TX_PROT
+                 | ENET_TXBD_PINS
+# endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_TX_PROT
+# ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+                 | ENET_TXBD_TS
+# endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+#endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+                 );
+
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_TDSR,
+                     (cyg_uint32)enet_priv_p->txbd_pool_p);
+    enet_priv_p->txbd_tail_p = enet_priv_p->txbd_head_p;
+#ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_TFWR,
+                     FREESCALE_ENET_TFWR_STRFWD_M);
+#else //CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_TFWR,
+                     FREESCALE_ENET_TFWR_TFWR(FREESCALE_ENET_TFWR_TFWR_192));
+#endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+
+}
+
+// Hardware initialization functions =========================================
+
+// Configure ENET (R)MII pins ------------------------------------------------
+// Note: pin acces uses services from HAL.
+
+static void
+enet_cfg_pins(freescale_enet_priv_t *enet_priv_p)
+{
+    const cyg_uint32 *pin_p;
+
+    if((pin_p = enet_priv_p->pins_p)) {
+        for(;
+            pin_p < enet_priv_p->pins_p + enet_priv_p->pins_n;
+            CYGHWR_IO_FREESCALE_ENET_PIN(*pin_p++));
+    }
+}
+
+// Set a MAC address match. -------------------------------------------------
+// Packets received which match this address will be passed on.
+
+void
+enet_set_mac_addr (CYG_ADDRWORD enet_base, const cyg_uint8 *addr_p)
+{
+    cyg_uint32 regval;
+
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_PALR,
+                     (cyg_uint32)((addr_p[0]<<24) + (addr_p[1]<<16) +
+                                  (addr_p[2]<<8) + addr_p[3]));
+    HAL_READ_UINT32(enet_base + FREESCALE_ENET_REG_PAUR, regval);
+    regval &= 0x0000ffff;
+    regval |= (cyg_uint32)((addr_p[4]<<24) + (addr_p[5]<<16));
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_PAUR, regval);
+}
+
+
+// Initialize ENET device ----------------------------------------------------
+//
+
+static bool
+enet_eth_init(struct cyg_netdevtab_entry *tab)
+{
+    struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
+    freescale_enet_priv_t *enet_priv_p =
+          (freescale_enet_priv_t *) sc->driver_private;
+    CYG_ADDRWORD enet_base = enet_priv_p->enet_base;
+#ifdef CYGHWR_DEVS_ETH_FREESCALE_ENET_GET_ESA
+    bool esa_ok = false;
+#endif
+    // Bring clock to the sevice
+    CYGHWR_IO_CLOCK_ENABLE(enet_priv_p->clock);
+    // Assign pins
+    enet_cfg_pins(enet_priv_p);
+
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIMR, 0);
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIR, 0xFFFFFFFF);
+
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_ECR,
+                     FREESCALE_ENET_ECR_RESET_M);
+    ENET_WAIT_US(FREESCALE_ENET_RESET_DELAY);
+
+#ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_ECR,
+                     FREESCALE_ENET_ECR_EN1588_M);
+#else // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_ECR, 0);
+#endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    cyg_drv_interrupt_create(enet_priv_p->rx_intr_vector,
+                             enet_priv_p->rx_intr_prio,
+                             (cyg_addrword_t)sc,
+                             (cyg_ISR_t *)enet_eth_isr,
+                             (cyg_DSR_t *)eth_drv_dsr,
+                             &enet_priv_p->rx_interrupt_handle,
+                             &enet_priv_p->rx_interrupt);
+    cyg_drv_interrupt_attach(enet_priv_p->rx_interrupt_handle);
+# ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    cyg_drv_interrupt_create(enet_priv_p->tx_intr_vector,
+                             enet_priv_p->tx_intr_prio,
+                             (cyg_addrword_t)sc,
+                             (cyg_ISR_t *)enet_eth_isr,
+                             (cyg_DSR_t *)eth_drv_dsr,
+                             &enet_priv_p->tx_interrupt_handle,
+                             &enet_priv_p->tx_interrupt);
+    cyg_drv_interrupt_attach(enet_priv_p->tx_interrupt_handle);
+# endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+#endif // CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+
+#ifdef CYGHWR_DEVS_ETH_FREESCALE_ENET_GET_ESA
+    // Get MAC address from RedBoot configuration variables
+    CYGHWR_DEVS_ETH_FREESCALE_ENET_GET_ESA(&enet_priv_p->enaddr[0], esa_ok);
+    // If this call fails myMacAddr is unchanged and MAC address from
+    // CDL is used
+    if (!esa_ok) {
+       // Can't figure out ESA
+       debug1_printf("Freescale ENET - Warning! ESA unknown\n");
+    }
+#endif
+    // Set the source address for the controller
+    enet_set_mac_addr (enet_base, enet_priv_p->enaddr);
+
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_IALR, 0x00000000);
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_IAUR, 0x00000000);
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_GALR, 0x00000000);
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_GAUR, 0x00000000);
+
+    if(eth_phy_init_wait(enet_priv_p->phy_p, FREESCALE_ENET_PHY_INIT_TOUT)) {
+        //   Initialize upper level driver.
+        (sc->funs->eth_drv->init)(sc, (cyg_uint8 *)enet_priv_p->enaddr);
+        return true;
+    } else {
+        return false;
+    }
+}
+
+// Start ENET ----------------------------------------------------------------
+
+static void
+enet_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr_p, int flags)
+{
+    freescale_enet_priv_t *enet_priv_p =
+          (freescale_enet_priv_t *)sc->driver_private;
+    CYG_ADDRWORD enet_base = enet_priv_p->enet_base;
+    cyg_uint32 enet_reg;
+
+
+    HAL_READ_UINT32(enet_base + FREESCALE_ENET_REG_ECR, enet_reg);
+    if(!(enet_reg & FREESCALE_ENET_ECR_ETHEREN_M)) {
+        // Set Speed, duplex, etc.
+        enet_eth_phy_set(enet_priv_p);
+
+        // Init Buffers
+        enet_init_buffers(enet_priv_p);
+
+        // Enable the device!
+
+        HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIR,
+                         FREESCALE_ENET_EIR_MASK_M);
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+        cyg_drv_interrupt_unmask(enet_priv_p->rx_intr_vector);
+# ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+        cyg_drv_interrupt_unmask(enet_priv_p->tx_intr_vector);
+# endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+        HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIMR,
+                         FREESCALE_ENET_EIMR_MASK_M);
+#endif // CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+
+        // Flow controll
+        if(enet_priv_p->flags & CYGSEM_ETH_FREESCALE_ENET0_RCR_FCE) {
+            debug1_printf("ENET: Flow control: RCR enabled.\n");
+            HAL_READ_UINT32(enet_base + FREESCALE_ENET_REG_RCR, enet_reg);
+            enet_reg |= FREESCALE_ENET_RCR_FCE_M;
+            HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_RCR, enet_reg);
+        } else {
+            debug1_printf("ENET: Flow control: RCR disabled.\n");
+            HAL_READ_UINT32(enet_base + FREESCALE_ENET_REG_RCR, enet_reg);
+            enet_reg &= ~FREESCALE_ENET_RCR_FCE_M;
+            HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_RCR, enet_reg);
+        }
+        debug1_printf("ENET: Flow control: RCR 0x%08x.\n", enet_reg);
+
+        // Flow controll pause duration
+        HAL_READ_UINT32(enet_base + FREESCALE_ENET_REG_OPD, enet_reg);
+        enet_reg &= 0xffff000;
+        enet_reg |= enet_priv_p->fc_pause;
+        HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_OPD, enet_reg);
+        debug1_printf("ENET: Flow control: pause %08x\n", enet_reg);
+
+        // Enable ENET...
+        HAL_READ_UINT32(enet_base + FREESCALE_ENET_REG_ECR, enet_reg);
+        enet_reg |= FREESCALE_ENET_ECR_ETHEREN_M;
+        HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_ECR, enet_reg);
+        // ...and wait a bit to settle
+        ENET_WAIT_US(FREESCALE_ENET_ENABLE_DELAY);
+        HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_RDAR,
+                         FREESCALE_ENET_RDAR_RDAR_M);
+#ifdef CYGOPT_DEVS_ETH_FREESCALE_ENET_STATS
+        FREESCALE_ENET_STATS_INIT(&enet_priv_p->enet_stats);
+#endif // CYGOPT_DEVS_ETH_FREESCALE_ENET_STATS
+    }
+}
+
+// Stop ENET ----------------------------------------------------------------
+
+static void
+enet_eth_stop(struct eth_drv_sc *sc)
+{
+    freescale_enet_priv_t *enet_priv_p =
+          (freescale_enet_priv_t *)sc->driver_private;
+    CYG_ADDRWORD enet_base = enet_priv_p->enet_base;
+    cyg_uint32 ecr;
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    enet_bd_t *tx_bd_head_p, *tx_bd_tail_p;
+    cyg_uint32 *tx_key_tail_p;
+    void (*tx_done)(struct eth_drv_sc *sc, CYG_ADDRESS key, int status);
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    cyg_drv_interrupt_mask(enet_priv_p->rx_intr_vector);
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    cyg_drv_interrupt_mask(enet_priv_p->tx_intr_vector);
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIMR, 0x00000000);
+#endif // CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIR,
+                         FREESCALE_ENET_EIR_MASK_M);
+
+    HAL_READ_UINT32(enet_base + FREESCALE_ENET_REG_ECR, ecr);
+    ecr &= ~FREESCALE_ENET_ECR_ETHEREN_M;
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_ECR, ecr);
+
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    // Free eventual unsent buffers.
+    tx_bd_head_p = enet_priv_p->txbd_head_p;
+    tx_bd_tail_p = enet_priv_p->txbd_tail_p;
+    tx_key_tail_p = enet_priv_p->txkey_tail_p;
+    tx_done = sc->funs->eth_drv->tx_done;
+    while(tx_bd_tail_p != tx_bd_head_p) {
+        ENET_TXBD_FREE(tx_bd_tail_p, enet_priv_p);
+        if(tx_bd_tail_p->ctrl & ENET_TXKEY_FLAG) {
+            tx_bd_tail_p->ctrl &= ~ENET_TXKEY_FLAG;
+            (tx_done)(sc, *tx_key_tail_p, 0);
+            *tx_key_tail_p = 0;
+            ENET_TXKEY_NEXT(tx_key_tail_p, enet_priv_p);
+        }
+    }
+    enet_priv_p->txbd_tail_p = tx_bd_tail_p;
+    enet_priv_p->txkey_tail_p = tx_key_tail_p;
+#endif //CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+}
+
+// ENET processing functions =================================================
+// ENET control function -----------------------------------------------------
+
+static int
+enet_eth_control(struct eth_drv_sc *sc, unsigned long key,
+                  void *data_p, int length)
+{
+    freescale_enet_priv_t *enet_priv_p =
+          (freescale_enet_priv_t *)sc->driver_private;
+    CYG_ADDRWORD enet_base = enet_priv_p->enet_base;
+    int retcode = 1;
+
+    switch (key) {
+    case ETH_DRV_SET_MAC_ADDRESS:
+        if(length >= ETHER_ADDR_LEN) {
+            enet_eth_stop(sc);
+            enet_set_mac_addr(enet_base, (cyg_uint8 *)data_p);
+            enet_eth_start(sc, (cyg_uint8 *)data_p, 0);
+            retcode = 0;
+        }
+        break;
+    default:
+        break;
+    }
+    return retcode;
+}
+
+// Can send ------------------------------------------------------------------
+//     NoCopy: returns number of free Tx buffer descriprors
+//     Copying: returns 1 if there is at least 1 free Tx buffer descriotor
+
+static int
+enet_eth_can_send(struct eth_drv_sc *sc)
+{
+    freescale_enet_priv_t *enet_priv_p =
+          (freescale_enet_priv_t *)sc->driver_private;
+#ifdef  CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    cyg_int32 avail = enet_priv_p->txbd_avail;
+# if DEBUG_ENET >= 2
+    if(avail < enet_priv_p->txbd_can_send_min)
+        diag_printf("ENET can_send: available = %d buffer descriptors.\n",
+                      avail);
+# endif // DEBUG_ENET
+    return (int) avail < enet_priv_p->txbd_can_send_min ? 0 : avail;
+#else // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+    enet_bd_t *tx_bd_p = enet_priv_p->txbd_head_p;
+
+    ENET_TXBD_NEXT(tx_bd_p, enet_priv_p);
+    debug2_printf("ENET: can send: %d\n", !(tx_bd_p->ctrl & ENET_TXBD_R));
+    if(!(tx_bd_p->ctrl & ENET_TXBD_R))
+        return 1;
+    else
+        return 0;
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+}
+
+// Send ----------------------------------------------------------------------
+//
+// Trigger ENET for sending --------------------------------------------------
+
+static void inline
+enet_eth_send_trigger(freescale_enet_priv_t *enet_priv_p)
+{
+    cyg_uint32 tdar;
+
+    do {
+        HAL_READ_UINT32(enet_priv_p->enet_base + FREESCALE_ENET_REG_TDAR, tdar);
+    } while(tdar & FREESCALE_ENET_TDAR_TDAR_M);
+    tdar = FREESCALE_ENET_TDAR_TDAR_M;
+    HAL_WRITE_UINT32(enet_priv_p->enet_base + FREESCALE_ENET_REG_TDAR, tdar);
+}
+
+#define ENET_ETH_SEND_RDY(__bd_p,_ad_flag) \
+CYG_MACRO_START \
+    cyg_uint16 ctrl; \
+    ctrl = __bd_p->ctrl & ENET_TXBD_W; \
+    ctrl |= ENET_TXBD_R | ENET_TXBD_TC | (_ad_flag); \
+    __bd_p->ctrl = ctrl; \
+CYG_MACRO_END
+
+// There different send functios for NoCopy and Copying driver options.
+#ifdef  CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+// Send - NoCopy version.
+//      This version does not copy SG buffer but writes SG buf pointer
+//      in ENET BD.
+//      Note: ENET requires that buf pointer is evenly divisible by 8.
+
+static void
+enet_eth_send_nocopy(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list,
+                     int sg_len, int total_len, unsigned long key)
+{
+    freescale_enet_priv_t *enet_priv_p =
+          (freescale_enet_priv_t *)sc->driver_private;
+    enet_bd_t *tx_bd_p;
+    enet_bd_t *tx_bd0_p=NULL;
+    cyg_uint32 *tx_key_p;
+    struct eth_drv_sg *sg_list_z;
+
+    if(enet_priv_p->txbd_avail < sg_len) {
+        debug1_printf("ENET Send: Error! sg_len %d avail %d\n", sg_len, enet_priv_p->txbd_avail);
+        (sc->funs->eth_drv->tx_done)(sc, key, 0);
+        return;
+    }
+    debug3_printf("ENET Send: sg_len %d avail %d\n", sg_len, enet_priv_p->txbd_avail);
+    tx_bd_p=enet_priv_p->txbd_head_p;
+    for(sg_list_z=sg_list+sg_len; sg_list<sg_list_z; sg_list++) {
+        ENET_TXBD_ALLOC(tx_bd_p, enet_priv_p);
+        tx_bd_p->buffer_p=(cyg_uint8 *)CYG_CPU_TO_BE32(sg_list->buf);
+        tx_bd_p->len=CYG_CPU_TO_BE16(sg_list->len);
+# ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+        tx_bd_p->bdu = 0;
+# endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+        if(tx_bd0_p) {
+            ENET_ETH_SEND_RDY(tx_bd_p, 0);
+        } else {
+            tx_bd0_p=tx_bd_p;
+        }
+    }
+    tx_key_p=enet_priv_p->txkey_head_p;
+    *tx_key_p = key;
+    ENET_TXKEY_NEXT(tx_key_p, enet_priv_p);
+    if(tx_bd_p != tx_bd0_p) {
+        debug3_printf("ENET Send2: Key[%p] = 0x%x\n", tx_key_p, key);
+        tx_bd_p->ctrl |= (ENET_TXBD_L | ENET_TXKEY_FLAG); // is last and has key
+        ENET_ETH_SEND_RDY(tx_bd0_p, 0);
+    } else {
+        debug3_printf("ENET Send1: Key[%p] = 0x%x\n", tx_key_p, key);
+        ENET_ETH_SEND_RDY(tx_bd0_p, ENET_TXBD_L | ENET_TXKEY_FLAG);
+    }
+    enet_priv_p->txkey_head_p = tx_key_p;
+    enet_priv_p->txbd_head_p = tx_bd_p;
+    enet_eth_send_trigger(enet_priv_p);
+}
+
+#else // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+// Send - Copying version.
+//      This version physically copies SG buf(s) in private ENET  buffer(s).
+//      This version is usefull if upper layer stack does not guarantee
+//      buffers aligned to 8 byte boundary.
+//      Also requires no Tx interrupts.
+
+static void
+enet_eth_send_copying(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list,
+                      int sg_len, int total_len, unsigned long key)
+{
+    freescale_enet_priv_t *enet_priv_p =
+          (freescale_enet_priv_t *)sc->driver_private;
+    enet_bd_t *tx_bd_p;
+    struct eth_drv_sg *sg_list_z;
+    cyg_uint16 ctrl;
+    cyg_uint8* txbuf_p;
+    cyg_uint32 txbuf_k;
+    enet_bd_t *tx_bd_save_p;
+
+    tx_bd_p=enet_priv_p->txbd_head_p;
+# ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+    while(!(tx_bd_p->bdu & ENET_TXBD_BDU)){
+        debug1_printf("ENET Send: Waiting for BDU %p\n", tx_bd_p);
+    }
+# endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+    debug2_printf("ENET Send: sg_len %d total_len %d\n", sg_len, total_len);
+    tx_bd_save_p=tx_bd_p;
+    ENET_TXBD_NEXT(tx_bd_p, enet_priv_p);
+    txbuf_p = (cyg_uint8 *)CYG_CPU_TO_BE32((cyg_uint32)tx_bd_p->buffer_p);
+    txbuf_k = 0;
+    for(sg_list_z=sg_list+sg_len; sg_list<sg_list_z; sg_list++) {
+        if((txbuf_k += sg_list->len) > enet_priv_p->txbuf_size) {
+            debug1_printf("ENET Send: Buffer overflow: %d (max = %d)\n", txbuf_k,
+                          enet_priv_p->txbuf_size);
+            enet_priv_p->txbd_head_p = tx_bd_save_p;
+            (sc->funs->eth_drv->tx_done)(sc, key, 0);
+            return;
+        }
+        memcpy(txbuf_p, (cyg_uint8 *)sg_list->buf, sg_list->len);
+        txbuf_p += sg_list->len;
+    }
+    tx_bd_p->len=CYG_CPU_TO_BE16(total_len);
+    ctrl = tx_bd_p->ctrl & ENET_TXBD_W;
+    ctrl |= ENET_TXBD_R | ENET_TXBD_TC | ENET_TXBD_L;
+# ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+    tx_bd_p->bdu = 0;
+# endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+    tx_bd_p->ctrl = ctrl;
+    enet_priv_p->txbd_head_p = tx_bd_p;
+    debug2_printf("ENET Send: trigger, done.\n");
+    enet_eth_send_trigger(enet_priv_p);
+    (sc->funs->eth_drv->tx_done)(sc, key, 0);
+}
+
+#endif //  CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+// Receive ------------------------------------------------------------------
+
+static void
+enet_eth_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
+{
+    freescale_enet_priv_t *enet_priv_p =
+          (freescale_enet_priv_t *)sc->driver_private;
+    cyg_uint8 *rxbuffer_p;
+    struct eth_drv_sg *sg_list_z;
+    enet_bd_t *rx_bd_p;
+
+    debug3_printf("ENET recv: sg_len=%d first len=%d\n", sg_len, sg_list->len);
+    rx_bd_p=enet_priv_p->rxbd_p;
+    rxbuffer_p=(cyg_uint8 *)CYG_CPU_TO_BE32((cyg_uint32)rx_bd_p->buffer_p);
+    for(sg_list_z=sg_list+sg_len; sg_list<sg_list_z; sg_list++) {
+        if(sg_list->buf) {
+            memcpy((cyg_uint8 *)sg_list->buf, rxbuffer_p, sg_list->len);
+            rxbuffer_p+=sg_list->len;
+        }
+    }
+}
+
+// Reception error check -----------------------------------------------------
+
+static inline bool
+enet_eth_recv_error(enet_bd_t *rx_bd_p, freescale_enet_priv_t *enet_priv_p)
+{
+    bool errcod=false;
+    cyg_uint32 ctrl = rx_bd_p->ctrl;
+
+    if(ctrl & ENET_RXBD_TR) {
+        ENET_STAT_PRINTF("ENET: Ethernet trunc error ctrl = 0x%04x\n",
+                         rx_bd_p->ctrl);
+        FREESCALE_ENET_STAT_DO(ctrl, enet_priv_p, TR);
+        errcod = true;
+    } else if(ctrl & ENET_RXBD_L) {
+        if(ctrl & (ENET_RXBD_CR | ENET_RXBD_OV | ENET_RXBD_LG | ENET_RXBD_NO))
+        {
+            // Ethernet fault processing
+            ENET_STAT_PRINTF("ENET: Ethernet error ctrl = 0x%04x => ",
+                             rx_bd_p->ctrl);
+            FREESCALE_ENET_STAT_DO(ctrl, enet_priv_p, CR);
+            FREESCALE_ENET_STAT_DO(ctrl, enet_priv_p, OV);
+            FREESCALE_ENET_STAT_DO(ctrl, enet_priv_p, LG);
+            FREESCALE_ENET_STAT_DO(ctrl, enet_priv_p, NO);
+            ENET_STAT_PRINTF("\n");
+            errcod = true;
+        }
+
+#ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+        ctrl = rx_bd_p->ebd_ctrl;
+        if(ctrl & (ENET_RXBD_ME | ENET_RXBD_PE | ENET_RXBD_CE | ENET_RXBD_FRAG
+# ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_RX_IP
+                   | ENET_RXBD_ICE
+#  ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_RX_PROT
+                   | ENET_RXBD_PCR
+#  endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_RX_PROT
+# endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_ACCEL_RX_IP
+                   ))
+        {
+            cyg_uint32 head_len = (rx_bd_p->hlen_proto >> 11) & 0x1f;
+            if(head_len || (ctrl & (ENET_RXBD_ME | ENET_RXBD_PE |
+                                    ENET_RXBD_CE | ENET_RXBD_FRAG )))
+            {
+                // Enhanced bd fault processing
+                ENET_STAT_PRINTF("ENET: Enhanced bd error ctrl = 0x%08x => ",
+                                 rx_bd_p->ebd_ctrl);
+                FREESCALE_ENET_STAT_DO(ctrl, enet_priv_p, ME);
+                FREESCALE_ENET_STAT_DO(ctrl, enet_priv_p, PE);
+                FREESCALE_ENET_STAT_DO(ctrl, enet_priv_p, CE);
+                FREESCALE_ENET_STAT_DO(ctrl, enet_priv_p, FRAG);
+                FREESCALE_ENET_STAT_DO(ctrl, enet_priv_p, ICE);
+                FREESCALE_ENET_STAT_DO(ctrl, enet_priv_p, PCR);
+                ENET_STAT_PRINTF("\n");
+                ENET_STAT_PRINTF("ENET:   HeadLen=%d[0x%x] Proto=%d[0x%x]\n",
+                                 head_len, head_len,
+                                 rx_bd_p->hlen_proto & 0xff,
+                                 rx_bd_p->hlen_proto & 0xff);
+                errcod = true;
+            }
+        }
+#endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+    }
+    if(errcod) {
+#ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+        debug2_printf("ENET: Bad msg ctrl = 0x%04x ebd_ctrl = 0x%08x\n",
+                      rx_bd_p->ctrl, rx_bd_p->ebd_ctrl);
+#else // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+        debug2_printf("ENET: Bad msg ctrl = 0x%04x\n", rx_bd_p->ctrl);
+#endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+    }
+    return errcod;
+}
+
+// Deliver -------------------------------------------------------------------
+#define ENET_DELIVER_NEED_SERVICE_RX FREESCALE_ENET_EIMR_RXF_M
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+# define ENET_DELIVER_NEED_SERVICE_TX FREESCALE_ENET_EIMR_TXF_M
+# define ENET_DELIVER_NEED_SERVICE (ENET_DELIVER_NEED_SERVICE_RX | \
+                                    ENET_DELIVER_NEED_SERVICE_TX)
+#else // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+# define ENET_DELIVER_NEED_SERVICE (ENET_DELIVER_NEED_SERVICE_RX)
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+#define ENET_DELIVER_NEED_SERVICE_SET(__var,__rt) \
+CYG_MACRO_START \
+    __var |= ENET_DELIVER_NEED_SERVICE_##__rt; \
+CYG_MACRO_END
+
+#define ENET_DELIVER_NEED_SERVICE_CLEAR(__var,__rt) \
+CYG_MACRO_START \
+    __var &= ~ENET_DELIVER_NEED_SERVICE_##__rt; \
+CYG_MACRO_END
+
+// There different deliver functios for NoCopy and Copying driver options.
+
+#ifdef CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+// Deliver - NoCopy varsion
+//      This deliver vresion is compatible with NoCopy send version.
+
+static void
+enet_eth_deliver_nocopy(struct eth_drv_sc * sc)
+{
+    freescale_enet_priv_t *enet_priv_p =
+          (freescale_enet_priv_t *)sc->driver_private;
+    CYG_ADDRWORD enet_base = enet_priv_p->enet_base;
+    enet_bd_t *tx_bd_tail_p, *tx_bd_tail_save_p;
+    cyg_uint32 *tx_key_tail_p;
+    enet_bd_t *rx_bd_p;
+    cyg_uint16 ctrl;
+    cyg_uint32 eir;
+    cyg_uint32 need_service;
+    void (*recv)(struct eth_drv_sc *sc, int total_len);
+    void (*tx_done)(struct eth_drv_sc *sc, CYG_ADDRESS key, int status);
+
+    recv = sc->funs->eth_drv->recv;
+    tx_done = sc->funs->eth_drv->tx_done;
+
+    tx_bd_tail_p = enet_priv_p->txbd_tail_p;
+    HAL_READ_UINT32(enet_base + FREESCALE_ENET_REG_EIR, eir);
+    need_service = eir & ENET_DELIVER_NEED_SERVICE;
+    do {
+        //Clear all ENET Interrupt events
+        HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIR,
+                         FREESCALE_ENET_EIR_MASK_M);
+        if(eir & FREESCALE_ENET_EIR_ERROR) {
+            debug2_printf("ENET: EIR Error 0x%08x\n",
+                          eir & FREESCALE_ENET_EIR_ERROR);
+            HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIR,
+                             FREESCALE_ENET_EIR_ERROR);
+        }
+
+        // RX Event processing
+        if(need_service & ENET_DELIVER_NEED_SERVICE_RX) {
+            rx_bd_p=enet_priv_p->rxbd_p;
+            ctrl=rx_bd_p->ctrl;
+            if(ctrl & ENET_RXBD_E) {
+                ENET_DELIVER_NEED_SERVICE_CLEAR(need_service, RX);
+            } else {
+                if(!enet_eth_recv_error(rx_bd_p, enet_priv_p)) {
+                    (recv)(sc, CYG_CPU_TO_BE16(rx_bd_p->len));
+                }
+                ctrl &= ENET_RXBD_W;
+                ctrl |= ENET_RXBD_E;
+                rx_bd_p->ctrl = ctrl;
+# ifdef  CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+                rx_bd_p->bdu = 0;
+# endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+                // Inform ENET that free Rx buffers have beeen freed.
+                HAL_WRITE_UINT32(enet_priv_p->enet_base +
+                                 FREESCALE_ENET_REG_RDAR,
+                                 FREESCALE_ENET_RDAR_RDAR_M);
+
+                ENET_RXBD_NEXT(rx_bd_p, enet_priv_p);
+                enet_priv_p->rxbd_p=rx_bd_p;
+
+                if(rx_bd_p->ctrl & ENET_RXBD_E) {
+                    ENET_DELIVER_NEED_SERVICE_CLEAR(need_service, RX);
+                }
+            }
+        }
+
+        // TX Event processing
+        if(need_service & ENET_DELIVER_NEED_SERVICE_TX) {
+            if(enet_priv_p->txbd_num == enet_priv_p->txbd_avail) {
+                debug2_printf("ENET: Tx nothing to send\n");
+                ENET_DELIVER_NEED_SERVICE_CLEAR(need_service, TX);
+            } else {
+                tx_bd_tail_save_p=tx_bd_tail_p;
+                ENET_TXBD_TRYFREE(tx_bd_tail_p, enet_priv_p);
+                ctrl = tx_bd_tail_p->ctrl;
+                if(ctrl & ENET_TXBD_R){
+                    tx_bd_tail_p=tx_bd_tail_save_p;
+                    ENET_DELIVER_NEED_SERVICE_CLEAR(need_service, TX);
+                } else {
+                    ENET_BD_AVAIL_INC(enet_priv_p);
+                    if(ctrl & ENET_TXKEY_FLAG){
+# ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+                        while(!(tx_bd_tail_p->bdu & ENET_TXBD_BDU)){
+                            debug1_printf("ENET Send: Waiting for BDU %p\n", tx_bd_tail_p);
+                        }
+# endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+                        tx_key_tail_p = enet_priv_p->txkey_tail_p;
+                        debug3_printf("ENET Deliver: Key[%p] = 0x%x\n",
+                                      tx_key_tail_p, *tx_key_tail_p);
+                        ENET_TXKEY_NEXT(tx_key_tail_p, enet_priv_p);
+                        enet_priv_p->txkey_tail_p = tx_key_tail_p;
+                        ctrl &= ~ENET_TXKEY_FLAG;
+                        tx_bd_tail_p->ctrl = ctrl;
+                        (tx_done)(sc, *tx_key_tail_p, 0);
+                    }
+                    if(enet_priv_p->txbd_avail == enet_priv_p->txbd_num) {
+                        debug3_printf("ENET: Tx All sent.\n");
+                        ENET_DELIVER_NEED_SERVICE_CLEAR(need_service, TX);
+                    }
+                }
+            }
+        }
+
+        // Check if Interrupt had arrived in meantime
+        HAL_READ_UINT32(enet_base + FREESCALE_ENET_REG_EIR, eir);
+        need_service |= eir & ENET_DELIVER_NEED_SERVICE;
+    } while(need_service);
+    debug3_printf("ENET: Delivered.\n");
+    enet_priv_p->txbd_tail_p = tx_bd_tail_p;
+# ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+#  ifdef CYGOPT_DEVS_ETH_FREESCALE_ENET_IRQ_FASTMASK
+    //Unmask all ENET interrupts
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIMR,
+                     FREESCALE_ENET_EIMR_MASK_M);
+#  else // CYGOPT_DEVS_ETH_FREESCALE_ENET_IRQ_FASTMASK
+    cyg_drv_interrupt_unmask(enet_priv_p->tx_intr_vector);
+    cyg_drv_interrupt_unmask(enet_priv_p->rx_intr_vector);
+#  endif // CYGOPT_DEVS_ETH_FREESCALE_ENET_IRQ_FASTMASK
+# endif //CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+}
+
+#else // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+// Deliver - Copying varsion
+//      This deliver vresion is compatible with Copying send version.
+
+static void
+enet_eth_deliver_copying(struct eth_drv_sc * sc)
+{
+    freescale_enet_priv_t *enet_priv_p =
+          (freescale_enet_priv_t *)sc->driver_private;
+    CYG_ADDRWORD enet_base = enet_priv_p->enet_base;
+    enet_bd_t *rx_bd_p;
+    cyg_uint16 ctrl;
+    cyg_uint32 eir;
+    cyg_uint32 need_service;
+    void (*recv)(struct eth_drv_sc *sc, int total_len);
+
+    recv = sc->funs->eth_drv->recv;
+    HAL_READ_UINT32(enet_base + FREESCALE_ENET_REG_EIR, eir);
+    need_service = eir & ENET_DELIVER_NEED_SERVICE;
+    do {
+        //Clear all ENET Interrupt events
+        HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIR,
+                         FREESCALE_ENET_EIR_MASK_M);
+        if(eir & FREESCALE_ENET_EIR_ERROR) {
+            debug2_printf("ENET: EIR Error 0x%08x\n",
+                          eir & FREESCALE_ENET_EIR_ERROR);
+            HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIR,
+                             FREESCALE_ENET_EIR_ERROR);
+        }
+
+        // RX Event processing
+        if(need_service & ENET_DELIVER_NEED_SERVICE_RX) {
+            rx_bd_p=enet_priv_p->rxbd_p;
+            ctrl=rx_bd_p->ctrl;
+            if(ctrl & ENET_RXBD_E) {
+                ENET_DELIVER_NEED_SERVICE_CLEAR(need_service, RX);
+            } else {
+                if(!enet_eth_recv_error(rx_bd_p, enet_priv_p)) {
+                    (recv)(sc, CYG_CPU_TO_BE16(rx_bd_p->len));
+                }
+                ctrl &= ENET_RXBD_W;
+                ctrl |= ENET_RXBD_E;
+                rx_bd_p->ctrl = ctrl;
+# ifdef  CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+                rx_bd_p->bdu = 0;
+# endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_BD_ENHANCED
+                // Inform ENET that Rx buffers have been freed.
+                HAL_WRITE_UINT32(enet_priv_p->enet_base +
+                                 FREESCALE_ENET_REG_RDAR,
+                                 FREESCALE_ENET_RDAR_RDAR_M);
+
+                ENET_RXBD_NEXT(rx_bd_p, enet_priv_p);
+                enet_priv_p->rxbd_p=rx_bd_p;
+
+                if(rx_bd_p->ctrl & ENET_RXBD_E) {
+                    ENET_DELIVER_NEED_SERVICE_CLEAR(need_service, RX);
+                }
+            }
+        }
+
+        // Check if Interrupt had arrived in meantime
+        HAL_READ_UINT32(enet_base + FREESCALE_ENET_REG_EIR, eir);
+        need_service |= eir & ENET_DELIVER_NEED_SERVICE;
+    } while(need_service);
+
+# ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+#  ifdef CYGOPT_DEVS_ETH_FREESCALE_ENET_IRQ_FASTMASK
+    //Unmask all ENET interrupts
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIMR,
+                     FREESCALE_ENET_EIMR_MASK_M);
+#  else // CYGOPT_DEVS_ETH_FREESCALE_ENET_IRQ_FASTMASK
+//    cyg_drv_interrupt_unmask(enet_priv_p->tx_intr_vector);
+    cyg_drv_interrupt_unmask(enet_priv_p->rx_intr_vector);
+#  endif // CYGOPT_DEVS_ETH_FREESCALE_ENET_IRQ_FASTMASK
+# endif //CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+}
+
+#endif // CYGOPT_ETH_FREESCALE_ENET_TX_NOCOPY
+
+// Poll ---------------------------------------------------------------------
+static void
+enet_eth_poll(struct eth_drv_sc *sc)
+{
+    enet_eth_deliver(sc);
+}
+
+// ISR ----------------------------------------------------------------------
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+static cyg_uint32
+enet_eth_isr(cyg_vector_t vector, cyg_addrword_t data)
+{
+#ifdef CYGOPT_DEVS_ETH_FREESCALE_ENET_IRQ_FASTMASK
+    struct eth_drv_sc *sc = (struct eth_drv_sc *)data;
+    freescale_enet_priv_t *enet_priv_p =
+          (freescale_enet_priv_t *)sc->driver_private;
+    CYG_ADDRWORD enet_base = enet_priv_p->enet_base;
+
+    //Mask ENET Interrupts
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIMR, 0x00000000);
+#else // CYGOPT_DEVS_ETH_FREESCALE_ENET_IRQ_FASTMASK
+    cyg_drv_interrupt_mask(vector);
+#endif // CYGOPT_DEVS_ETH_FREESCALE_ENET_IRQ_FASTMASK
+    cyg_drv_interrupt_acknowledge(vector);
+
+    return CYG_ISR_CALL_DSR;
+}
+
+#endif //CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+
+static int
+enet_eth_int_vector(struct eth_drv_sc *sc)
+{
+    return CYGNUM_FREESCALE_ENET0_RECEIVE_INT_VECTOR;
+}
+
+// PHY related stuff =========================================================
+// MDIO interface
+
+// Polling based waiting function for MDIO transactions
+static bool
+freescale_enet_busywait_mii(CYG_ADDRWORD enet_base, cyg_uint32 counter)
+{
+    cyg_uint32 eir;
+    bool done=0;
+
+    for(; counter; counter--) {
+        ENET_WAIT_US(2);
+        HAL_READ_UINT32(enet_base + FREESCALE_ENET_REG_EIR, eir);
+        if(eir & FREESCALE_ENET_EIR_MII_M) {
+            eir |= FREESCALE_ENET_EIR_MII_M;
+            HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIR, eir);
+            done=1;
+            break;
+        }
+    }
+    return done;
+}
+
+// Write a PHY register via the MDIO interface -------------------------------
+
+static void
+enet_write_phy(int reg_addr, int phy_addr, unsigned short data)
+{
+    CYG_ADDRWORD enet_base = enet0_eth0_priv.enet_base;
+    cyg_uint32 eir;
+
+    HAL_READ_UINT32(enet_base + FREESCALE_ENET_REG_EIR, eir);
+    eir |= FREESCALE_ENET_EIR_MII_M;
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIR, eir);
+
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_MMFR,
+                     FREESCALE_ENET_MMFR_ST(01)       |
+                     FREESCALE_ENET_MMFR_OP(01)       |
+                     FREESCALE_ENET_MMFR_PA(phy_addr) |
+                     FREESCALE_ENET_MMFR_RA(reg_addr) |
+                     FREESCALE_ENET_MMFR_TA(02)       |
+                     FREESCALE_ENET_MMFR_DATA(data));
+    freescale_enet_busywait_mii(enet_base, FREESCALE_ENET_MII_WRITE_TOUT);
+}
+
+// Read a PHY register via the MDIO interface --------------------------------
+
+static bool
+enet_read_phy(int reg_addr, int phy_addr, unsigned short *data_p)
+{
+    bool done = 0;
+    volatile cyg_uint32 mmfr;
+    CYG_ADDRWORD enet_base = enet0_eth0_priv.enet_base;
+    cyg_uint32 eir;
+
+    HAL_READ_UINT32(enet_base + FREESCALE_ENET_REG_EIR, eir);
+    eir |= FREESCALE_ENET_EIR_MII_M;
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_EIR, eir);
+
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_MMFR,
+                     FREESCALE_ENET_MMFR_ST(01)       |
+                     FREESCALE_ENET_MMFR_OP(02)       |
+                     FREESCALE_ENET_MMFR_PA(phy_addr) |
+                     FREESCALE_ENET_MMFR_RA(reg_addr) |
+                     FREESCALE_ENET_MMFR_TA(02));
+    if((done = freescale_enet_busywait_mii(enet_base,
+                                           FREESCALE_ENET_MII_READ_TOUT))) {
+        HAL_READ_UINT32(enet_base + FREESCALE_ENET_REG_MMFR, mmfr);
+        *data_p = (unsigned short)(mmfr & FREESCALE_ENET_MMFR_DATA_M);
+    }
+    return done;
+}
+
+
+// PHY initialization functions ----------------------------------------------
+// Init ENET device for phy access -------------------------------------------
+//
+static void
+enet_init_phy(void)
+{
+    CYG_ADDRWORD enet_base = enet0_eth0_priv.enet_base;
+    cyg_uint32 mii_speed;
+
+    mii_speed = (2 * CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK / 5000000 + 1);
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_MSCR,
+                     FREESCALE_ENET_MSCR_MII_SPEED(mii_speed) |
+                     FREESCALE_ENET_MSCR_HOLDTIME(0)
+                     );
+}
+
+// Set ENET device according to PHY stat -------------------------------------
+//
+static void
+enet_eth_phy_set(freescale_enet_priv_t *enet_priv_p)
+{
+    CYG_ADDRWORD enet_base = enet_priv_p->enet_base;
+    unsigned short phy_state = 0;
+    cyg_uint32 regval;
+
+    phy_state=_eth_phy_state(enet_priv_p->phy_p);
+#ifdef CYGSEM_DEVS_ETH_FREESCALE_ENET_PHY_RMII
+    regval = FREESCALE_ENET_RCR_MAX_FL(enet_priv_p->max_frame_len)
+          | FREESCALE_ENET_RCR_RMII_MODE_M | FREESCALE_ENET_RCR_MII_MODE_M;
+    if((phy_state & ETH_PHY_STAT_LINK) && !(phy_state & ETH_PHY_STAT_100MB)) {
+        // Operate in 10MB mode
+        regval |= FREESCALE_ENET_RCR_RMII_10T_M;
+    }
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_RCR, regval);
+#else // CYGSEM_DEVS_ETH_FREESCALE_ENET_PHY_RMII
+    HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_RCR,
+                     FREESCALE_ENET_RCR_MAX_FL(enet_priv_p->max_frame_len) |
+                     FREESCALE_ENET_RCR_MII_MODE_M);
+#endif // CYGSEM_DEVS_ETH_FREESCALE_ENET_PHY_RMII
+    if(phy_state & ETH_PHY_STAT_FDX) { // Operate in full-duplex mode
+        HAL_WRITE_UINT32(enet_base + FREESCALE_ENET_REG_TCR,
+                         FREESCALE_ENET_TCR_FDEN_M);
+    }
+}
+
+
+// PHY may need some start-up time -------------------------------------------
+//
+
+static bool
+eth_phy_init_wait(eth_phy_access_t *phy_p, cyg_uint32 ms)
+{
+    cyg_uint32 cnt;
+
+    for(cnt=0; cnt<ms; cnt++) {
+        if(_eth_phy_init(phy_p))
+            return true;
+        ENET_WAIT_US(1000);
+    }
+    return false;
+}
+
+//----------------------------------------------------------------------------
+// EOF if_freescale_enet.c
diff --git a/packages/devs/eth/microchip/enc424j600/current/ChangeLog b/packages/devs/eth/microchip/enc424j600/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/microchip/enc424j600/current/ChangeLog
@@ -0,0 +1,33 @@
+2012-04-20  Ilija Stanislevik  <ilijas@siva.mk>
+
+	* cdl/enc424j600_eth_drivers.cdl:
+	* host/enc424j600_eth_drivers.cdl:
+	* include/enc424j600_eth.h:
+	* src/enc424j600_spi.h:
+	* src/enc424j600_spi.c:
+	* tests/netconn_test_server.c:
+	New package [Bugzilla ID #1000910].
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/packages/devs/eth/microchip/enc424j600/current/cdl/enc424j600_eth_drivers.cdl b/packages/devs/eth/microchip/enc424j600/current/cdl/enc424j600_eth_drivers.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/microchip/enc424j600/current/cdl/enc424j600_eth_drivers.cdl
@@ -0,0 +1,271 @@
+# ====================================================================
+#
+#      enc424j600_eth_drivers.cdl
+#
+#      Ethernet driver for Microchip ENC424J600 controller
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 2009, 2010 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later
+## version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with eCos; if not, write to the Free Software Foundation, Inc.,
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+##
+## As a special exception, if other files instantiate templates or use
+## macros or inline functions from this file, or you compile this file
+## and link it with other works to produce a work based on this file,
+## this file does not by itself cause the resulting work to be covered by
+## the GNU General Public License. However the source code for this file
+## must still be made available in accordance with section (3) of the GNU
+## General Public License v2.
+##
+## This exception does not invalidate any other reasons why a work based
+## on this file might be covered by the GNU General Public License.
+## -------------------------------------------
+## ####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      Ilija Stanislevik
+# Contributors:
+# Date:           2010-11-23
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_ENC424J600 {
+    display       "Microchip ENC424J600 / ENC624J600 ethernet controller"
+
+    parent        CYGPKG_IO_ETH_DRIVERS
+    active_if     CYGPKG_IO_ETH_DRIVERS
+
+    implements    CYGHWR_NET_DRIVERS
+    implements    CYGHWR_NET_DRIVER_ETH0
+    implements    CYGINT_IO_ETH_MULTICAST
+
+    active_if     CYGPKG_IO_SPI
+
+    requires { CYGINT_IO_ETH_INT_SUPPORT_REQUIRED implies
+               (CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_VECTOR != "")
+             }
+
+    requires { CYGINT_IO_ETH_INT_SUPPORT_REQUIRED implies
+               (CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_PRIORITY != "")
+             }
+
+    include_dir   cyg/io/eth
+    description   "
+        Driver for Microchip ENC424J600 and ENC624J600 Ethernet controllers,
+        connected to the platform with an SPI interface."
+
+    compile       -library=libextras.a enc424j600_spi.c
+
+    define_proc {
+        puts $::cdl_header "#include <pkgconf/system.h>"
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_ENC424J600_OPTIONS {
+        display     "Microchip ENC424J600 driver build options"
+        flavor      none
+        no_define
+
+        cdl_option CYGPKG_DEVS_ETH_ENC424J600_CFLAGS_ADD {
+            display       "Additional compiler flags"
+            flavor        data
+            no_define
+            default_value { "-D_KERNEL -D__ECOS" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the ENC424J600 ethernet driver package.
+                These flags are used in addition
+                to the set of global flags."
+        }
+
+    }
+
+    cdl_option CYGDAT_IO_ETH_ENC424J600_NAME {
+        display       "Ethernet device name"
+        flavor        data
+        default_value { "\"eth0\"" }
+    }
+
+    cdl_component CYGSEM_DEVS_ETH_ENC424J600_NO_AUTO_NEGOTIATION {
+        display       "No auto negotiation of speed and duplex"
+        default_value 0
+        description   "
+            Enable this component in order to manually configure the link speed
+            and duplex configuration. Otherwise the chip will automatically
+            negotiate them with the peer."
+
+        cdl_option CYGNUM_DEVS_ETH_ENC424J600_SPEED {
+            display       "Ethernet speed in megabit per second"
+            flavor        data
+            legal_values  { 100 10 }
+            default_value 100
+        }
+
+        cdl_option CYGSEM_DEVS_ETH_ENC424J600_FULL_DUPLEX {
+            display       "Full duplex"
+            default_value 1
+        }
+    }
+
+    cdl_component CYGSEM_DEVS_ETH_ENC424J600_SET_ESA {
+        display       "Set the Ethernet station address"
+        flavor        bool
+        default_value 0
+        description   "
+            Enabling this option will override the ENC424J600
+            factory set ethernet station address (MAC address)."
+
+        cdl_option CYGDAT_DEVS_ETH_ENC424J600_ESA {
+            display       "Ethernet station address"
+            flavor        data
+            default_value { " { 0x00, 0x04, 0xa3, 0x10, 0x08, 0x3e } "}
+            description   "The ethernet station address"
+        }
+    }
+
+    cdl_option CYGNUM_DEVS_ETH_ENC424J600_ACCEPTABLE_PACKET_SIZE {
+        display       "Largest acceptable packet size"
+        flavor        data
+        legal_values  60 to 9600
+        default_value 1518
+        description "
+            This option configures the size in bytes of the largest
+            packet expected to be sent or received. The chip will
+            truncate any received or transmitted packet to this
+            size. This size excludes any space required for the
+            Preamble, Start of Frame Delimiter and the Frame Check
+            Sequence (CRC)."
+    }
+
+    cdl_option CYGNUM_DEVS_ETH_ENC424J600_TXBUF_SIZE {
+        display       "Size of transmit buffer"
+        flavor        data
+        legal_values  CYGNUM_DEVS_ETH_ENC424J600_ACCEPTABLE_PACKET_SIZE to (0x6000 - CYGNUM_DEVS_ETH_ENC424J600_ACCEPTABLE_PACKET_SIZE -2)
+        default_value CYGNUM_DEVS_ETH_ENC424J600_ACCEPTABLE_PACKET_SIZE
+        description "
+            The 0x6000 bytes of on-chip RAM are divided between transmit
+            buffer and receive buffer. This parameter impacts the sizes of
+            both. The transmit buffer must be large enough to hold one
+            transmit packet."
+    }
+
+    cdl_option CYGSEM_DEVS_ETH_ENC424J600_FLOWC {
+        display       "Flow control"
+        flavor        data
+        default_value { "None" }
+        legal_values  { "None" "OnChip" }
+        description   "
+            Enabling flow control prevents overflow of the input buffer if
+            received packets are not processed fast enough."
+    }
+
+    cdl_component CYGNUM_DEVS_ETH_ENC424J600_FLOW_CONTROL_PARAMETERS {
+        display       "Flow control parameters"
+        active_if     { CYGSEM_DEVS_ETH_ENC424J600_FLOWC != "None" }
+        flavor        none
+
+        cdl_option CYGNUM_DEVS_ETH_ENC424J600_FLOWC_UPPER_WATERMARK {
+            display       "Upper threshold for flow control"
+            flavor        data
+            default_value 16
+            legal_values  2 to 255
+            description   "
+                This threshold is measured in multiples of blocks of
+                96 bytes. When this number of blocks have been used
+                in the on-chip receive buffer, the device considers its
+                receive buffer full and initiates flow control."
+        }
+
+        cdl_option CYGNUM_DEVS_ETH_ENC424J600_FLOWC_LOWER_WATERMARK {
+            display       "Lower threshold for flow control"
+            flavor        data
+            default_value 15
+            legal_values  1 to (CYGNUM_DEVS_ETH_ENC424J600_FLOWC_UPPER_WATERMARK - 1)
+            description   "
+                This threshold is measured in multiples of blocks of
+                96 bytes. If flow control has been activated, then
+                when the number of occupied blocks in the on-chip
+                receive buffer falls below this level, the device
+                considers the buffer to be empty enough to receive
+                more data and therefore disengages flow control."
+        }
+
+        cdl_option CYGNUM_DEVS_ETH_ENC424J600_FLOWC_PAUSE {
+            display       "Duration of flow control pause"
+            flavor        data
+            default_value { 0x1000 }
+            legal_values  0 to 0xffff
+            description   "
+                Duration of flow control pause in units of 512 bit times. Valid for full-duplex
+                operation only."
+        }
+    }
+
+    cdl_option CYGNUM_DEVS_ETH_ENC424J600_CLOCKOUT_FREQUENCY {
+        display       "Frequency of clock output at the CLKOUT pin"
+        flavor        data
+        default_value { "0" }
+        legal_values  {
+            "0" "33M33" "25M00"
+            "20M00" "16M67" "12M50" "10M00"
+            "8M333" "8M000" "6M250" "5M000"
+            "4M000" "3M125"
+            "0M0" "100K" "50K"
+        }
+        description   "
+            The ENC424J600 has a clock output which can be used by
+            other parts of the system.  M stands for megahertz, K for
+            kilohertz, and where these letters are used stands for the
+            position of a decimal point.  Values 0 and 0M0 both mean
+            DC output, or, in other words, no clock output.  This
+            driver does not make use of the clock output facility
+            itself. Control of the clock output frequency is provided
+            here as a convenience."
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_ENC424J600_INTERRUPT {
+        display       "Interrupt configuration"
+        flavor        none
+        no_define
+        active_if     CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+        description   "
+            Configuration options related to interrupt handling."
+
+        cdl_option CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_PRIORITY {
+            display       "Interrupt priority"
+            flavor        data
+            default_value { is_active(CYGNUM_HAL_SPIETH_INTERRUPT_PRIORITY) ? CYGNUM_HAL_SPIETH_INTERRUPT_PRIORITY : "\"\"" }
+            description   "
+                Interrupt priority for the ENC424J600. The default value
+                is typically set by the platform HAL."
+        }
+
+        cdl_option CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_VECTOR {
+            display       "Interrupt vector"
+            flavor data
+            default_value { is_active(CYGNUM_ETH_SPIETH_HAL_INTERRUPT_VECTOR) ? CYGNUM_ETH_SPIETH_HAL_INTERRUPT_VECTOR : "\"\"" }
+            description   "
+                Interrupt vector for the ENC424J600. The default value is
+                typically set by the platform HAL."
+        }
+    }
+}
+
+# End of enc424j600_eth_drivers.cdl
diff --git a/packages/devs/eth/microchip/enc424j600/current/host/test_tcp_client.c b/packages/devs/eth/microchip/enc424j600/current/host/test_tcp_client.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/microchip/enc424j600/current/host/test_tcp_client.c
@@ -0,0 +1,198 @@
+//=================================================================
+//
+//        test_tcp_client.c
+//
+//        TCP/Ethernet testing - host-side
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Stanislevik
+// Date:          2010-02-10
+//####DESCRIPTIONEND####
+//==========================================================================
+
+/*
+ The target hardware runs a listener/server application. The server
+ calculates checksum on recived packets for the whole duration of 
+ connection. Once conection ends, it displays the checksum.
+ 
+ The host client generates pseudorandom data and sends it to the target.
+ Before sending, it calculates checksum. Once data sent, it dispalys
+ the checksum for comparison with the checksum at target side.
+ 
+ For now, no attempts has been made to employ a host other than Linux.
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include <sys/socket.h>
+#include <netinet/in.h>
+#include <arpa/inet.h>
+#include <netdb.h>
+
+#define NUM_ARG 4
+
+struct addrinfo * hostaddr_p;
+int socket_d;
+struct sockaddr serv_addr;
+
+void print_syntax(char *name)
+{
+    printf("Syntax: %s ip_address port bytes_to_send\n", name);
+    printf("        Format ip_address as d1.d2.d3.d4, where dx is integer 0-255\n\n");
+}
+
+int main(int argc, char *argv[])
+{
+    int retval;
+    struct addrinfo hint_s;
+    struct addrinfo *p;
+    char ipstr[INET6_ADDRSTRLEN];
+    unsigned long int msg_len;
+    unsigned long int left_to_send;
+    unsigned long int i;
+    unsigned long int csum;
+    char *msg_p = NULL;
+    char *fill_p;
+    unsigned char value;
+
+    if(NUM_ARG != argc)
+    {
+        printf("\nError:  Wrong number of arguments %d instead of %d.\n", argc-1, NUM_ARG-1);
+        print_syntax(argv[0]);
+        return EXIT_FAILURE;
+    }
+
+    memset(&hint_s, 0, sizeof(struct addrinfo));
+    hint_s.ai_family = AF_INET;
+    hint_s.ai_socktype = SOCK_STREAM;
+    hint_s.ai_flags = AI_NUMERICSERV;
+    hint_s.ai_protocol = 0;          /* Any protocol */
+    hint_s.ai_canonname = NULL;
+    hint_s.ai_addr = NULL;
+    hint_s.ai_next = NULL;
+    retval = getaddrinfo(argv[1], argv[2], &hint_s, &hostaddr_p);
+    if(0 != retval)
+    {
+        printf("\nError:  %s\n", gai_strerror(retval));
+        print_syntax(argv[0]);
+        return EXIT_FAILURE;
+    }
+
+    printf("IP addresses for %s:\n", argv[1]);
+
+    for(p = hostaddr_p; p != NULL; p = p->ai_next)
+    {
+        void *addr;
+        char *ipver;
+        // get the pointer to the address itself,
+        // different fields in IPv4 and IPv6:
+        if (p->ai_family == AF_INET)
+        { // IPv4
+            struct sockaddr_in *ipv4 = (struct sockaddr_in *)p->ai_addr;
+            addr = &(ipv4->sin_addr);
+            ipver = "IPv4";
+        }
+        else
+        { // IPv6
+            struct sockaddr_in6 *ipv6 = (struct sockaddr_in6 *)p->ai_addr;
+            addr = &(ipv6->sin6_addr);
+            ipver = "IPv6";
+        }
+        // convert the IP to a string and print it:
+        inet_ntop(p->ai_family, addr, ipstr, sizeof ipstr);
+        printf(" %s: %s\n", ipver, ipstr);
+    }
+
+    socket_d = socket(hostaddr_p->ai_family, hostaddr_p->ai_socktype, hostaddr_p->ai_protocol);
+    if(-1 == socket_d)
+    {
+        printf("Error:  Can't get socket. errno %d\n", errno);
+        return EXIT_FAILURE;
+    }
+
+    retval = connect(socket_d, hostaddr_p->ai_addr, hostaddr_p->ai_addrlen);
+    if(0 != retval)
+    {
+        perror("\nError:  Failed connect()\n");
+        return EXIT_FAILURE;
+    }
+
+    // Prepare message to send
+    msg_len = strtoul(argv[3], NULL, 0);
+    msg_len &= ~0x3;
+    if (0 == msg_len)
+    {
+        printf("Nothing to do (bytes_to_send == 0). Exiting.\n");
+        return EXIT_SUCCESS;
+    }
+    else
+    {
+        printf("Preparing to send %lu bytes.\n", msg_len);
+    }
+
+    msg_p = malloc(msg_len);
+    if(NULL == msg_p)
+    {
+        printf("Error:  Can't allocate %lu bytes.\n", msg_len);
+        return EXIT_FAILURE;
+    }
+
+    fill_p = msg_p;
+    csum = 0;
+
+    for(i=0; i<msg_len; i++)
+    {
+        value = random() & 0xff;
+        *fill_p++ = value;
+        csum += value;
+    }
+
+    left_to_send = msg_len;
+    do
+    {
+        retval = send(socket_d, msg_p, msg_len, 0);
+        left_to_send -= retval;
+        printf("%d bytes sent.\n", retval);
+    } while(left_to_send);
+    printf("Checksum %08lx\n", csum);
+
+    freeaddrinfo(hostaddr_p); // free the linked list
+
+    return EXIT_SUCCESS;
+}
diff --git a/packages/devs/eth/microchip/enc424j600/current/include/enc424j600_eth.h b/packages/devs/eth/microchip/enc424j600/current/include/enc424j600_eth.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/microchip/enc424j600/current/include/enc424j600_eth.h
@@ -0,0 +1,100 @@
+#ifndef CYGONCE_DEVS_ETH_ENC424J600_ETH_H_
+#define CYGONCE_DEVS_ETH_ENC424J600_ETH_H_
+
+//==========================================================================
+//
+//      enc424j600_eth.h
+//
+//      Microchip enc424j600 Ethernet chip
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2010, 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija Stanislevik
+// Contributors:
+// Date:         2010-11-23
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/devs_eth_enc424j600.h>
+
+// Ethernet flow control options
+enum enc424j600_flow_control_e
+{
+    ENC424J600_NO_FC,            // No flow control
+    ENC424J600_ONCHIP_AUTO_FC    // On-chip automatic flow control. Not tested yet.
+};
+
+// enc424j600 clock out frequencies
+enum enc424j600_clkout_e
+{
+    ENC424J600_CLKO_0,    // DC
+    ENC424J600_CLKO_33M33, ENC424J600_CLKO_25M00, ENC424J600_CLKO_20M00,
+    ENC424J600_CLKO_16M67, ENC424J600_CLKO_12M50, ENC424J600_CLKO_10M00,
+    ENC424J600_CLKO_8M333, ENC424J600_CLKO_8M000, ENC424J600_CLKO_6M250,
+    ENC424J600_CLKO_5M000, ENC424J600_CLKO_4M000, ENC424J600_CLKO_3M125,
+    ENC424J600_CLKO_0M0,  // DC
+    ENC424J600_CLKO_100K, ENC424J600_CLKO_50K
+};
+
+struct enc424j600_priv_data_s;
+typedef cyg_bool (*provide_esa_t)(struct enc424j600_priv_data_s*);
+
+typedef struct enc424j600_priv_data_s
+{
+    // Configurable data
+    cyg_spi_device            *spi_service_device; // SPI device used to communicate
+                                                   // with the Ethernet chip
+    provide_esa_t              provide_esa;
+    bool                       hardwired_esa;
+    unsigned char              esa[ETHER_ADDR_LEN];
+    cyg_handle_t               interrupt_handle;
+    cyg_interrupt              interrupt_object;
+    struct cyg_netdevtab_entry *tab;
+
+    // Really private data
+    cyg_uint16                 NextPacketPointer;
+    enum { ENC424J600_LINK_OFF, ENC424J600_LINK_ON } link_status;
+    bool                       txbusy;
+    unsigned long              txkey;
+} enc424j600_priv_data_t;
+
+#endif /* CYGONCE_DEVS_ETH_ENC424J600_ETH_H_ */
+
+// End of enc424j600_eth.h
diff --git a/packages/devs/eth/microchip/enc424j600/current/src/enc424j600_spi.c b/packages/devs/eth/microchip/enc424j600/current/src/enc424j600_spi.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/microchip/enc424j600/current/src/enc424j600_spi.c
@@ -0,0 +1,1340 @@
+//==========================================================================
+//
+//      enc424j600_spi.c
+//
+//      Microchip enc424j600 Ethernet chip
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2010, 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija Stanislevik
+// Contributors:
+// Date:         2010-11-23
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_if.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/cyg_trac.h>
+#include <cyg/infra/diag.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/io/eth/netdev.h>
+#include <cyg/io/eth/eth_drv.h>
+
+#include <cyg/io/spi.h>                 // Common SPI API
+
+#include "enc424j600_spi.h"
+#include <cyg/io/eth/enc424j600_eth.h>
+
+// Set ENC424J600_DEBUG to:
+// 0 to suppress all printout
+// 1 to print error reports
+// 2 to print interrupt tracing
+// 4 printout _init() progress
+// 8 to print progress tracing data
+// 0x10  for test with dummy stack
+// 0x20  to printout status registers
+#define ENC424J600_DEBUG (0)
+
+#define ENC424J600_DONT_DROP_CS    (0)
+#define ENC424J600_DO_DROP_CS      (1)
+#define ENC424J600_TXBUF_START     (0)
+
+#define ENC424J600_RXBUF_START (ENC424J600_TXBUF_START + CYGNUM_DEVS_ETH_ENC424J600_TXBUF_SIZE)
+
+#ifndef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+#   define SPI_POLLING true
+#else
+#   define SPI_POLLING false
+#endif
+
+static enc424j600_priv_data_t eth0_enc424j600_priv_data;
+
+ETH_DRV_SC(eth0_spi_sc,
+           &eth0_enc424j600_priv_data,  // Driver specific data.
+           CYGDAT_IO_ETH_ENC424J600_NAME,
+           enc424j600_spi_start,
+           enc424j600_spi_stop,
+           enc424j600_spi_control,
+           enc424j600_spi_can_send,
+           enc424j600_spi_send,
+           enc424j600_spi_recv,
+           enc424j600_spi_deliver,
+           enc424j600_spi_poll,
+           enc424j600_spi_int_vector
+);
+
+NETDEVTAB_ENTRY(eth0_spi_netdev,
+                "eth_spi",
+                enc424j600_spi_init,
+                &eth0_spi_sc);
+
+// Local service functions
+
+// Interface for enc424j600 "single byte instruction".
+static void
+simple_operation(enc424j600_priv_data_t *dpd, enum enc424j600_spi_opcode_1_e opcode)
+{
+    cyg_spi_transaction_begin(dpd->spi_service_device);
+    cyg_spi_transaction_transfer(dpd->spi_service_device,
+            SPI_POLLING,
+            1,
+            & opcode,
+            NULL,           // not interested in answer
+            ENC424J600_DO_DROP_CS);
+    cyg_spi_transaction_end(dpd->spi_service_device);
+
+    return;
+}
+
+// Interface for enc424j600 "banked N-byte instructions".
+// Banked read, write, bit set or bit clear operation with control register
+static int
+banked_register_operation(enc424j600_priv_data_t *cpd,
+    enum enc424j600_spi_opcode_e opcode,
+    cyg_uint8 address,
+    cyg_uint16 length,
+    cyg_uint8 *buffer)
+{
+    if ((NULL == buffer) || (0 == length))
+    {
+#if ENC424J600_DEBUG & 1
+        diag_printf("Wrong parm buffer=0x%x or length=%d.\n", (int)buffer, length);
+#endif
+        return -1;
+    }
+
+    if ((ENC424J600_ECON1H < address) || (opcode & ENC424J600_ECON1H))
+    {
+#if ENC424J600_DEBUG & 1
+        diag_printf("Wrong address=0x%02x or opcode=0x%02x for banked operation.\n",
+            address, opcode);
+#endif
+        return -1;
+    }
+
+    address |= opcode;  // combine them in single byte
+    cyg_spi_transaction_begin(cpd->spi_service_device);
+    // Send the opcode and address,
+    cyg_spi_transaction_transfer(cpd->spi_service_device,
+        SPI_POLLING,
+        1,
+        & address,
+        NULL,           // not interested in answer
+        ENC424J600_DONT_DROP_CS);
+    // then the data.
+    cyg_spi_transaction_transfer(cpd->spi_service_device,
+        SPI_POLLING,
+        length,
+        (ENC424J600_READCR == opcode) ? NULL : buffer,
+        (ENC424J600_READCR == opcode) ? buffer : NULL,
+        ENC424J600_DO_DROP_CS);
+    cyg_spi_transaction_end(cpd->spi_service_device);
+
+    return 0;
+}
+
+// Interface for enc424j600 "unbanked N-byte instructions".
+// Unbanked read, write, bit set or bit clear operation with control register
+static int
+unbanked_register_operation(enc424j600_priv_data_t *cpd,
+    enum enc424j600_spi_opcode_u_e opcode,
+    cyg_uint8 address,
+    cyg_uint16 length,
+    cyg_uint8 *buffer)
+{
+    if ((NULL == buffer) || (0 == length))
+    {
+#if ENC424J600_DEBUG & 1
+        diag_printf("Wrong parm buffer=0x%x or length=%d.\n", (int)buffer, length);
+#endif
+        return -1;
+    }
+
+    cyg_spi_transaction_begin(cpd->spi_service_device);
+    // Send the opcode,
+    cyg_spi_transaction_transfer(cpd->spi_service_device,
+        SPI_POLLING,
+        1,
+        & opcode,
+        NULL,           // not interested in answer
+        ENC424J600_DONT_DROP_CS);
+    // then the address
+    cyg_spi_transaction_transfer(cpd->spi_service_device,
+        SPI_POLLING,
+        1,
+        & address,
+        NULL,           // not interested in answer
+        ENC424J600_DONT_DROP_CS);
+    // and finally the data.
+    cyg_spi_transaction_transfer(cpd->spi_service_device,
+        SPI_POLLING,
+        length,
+        (ENC424J600_READCRU == opcode) ? NULL : buffer,
+        (ENC424J600_READCRU == opcode) ? buffer : NULL,
+        ENC424J600_DO_DROP_CS);
+    cyg_spi_transaction_end(cpd->spi_service_device);
+
+    return 0;
+}
+
+// Get ESA from the Ethernet chip, unbanked
+static int
+read_esa_u(enc424j600_priv_data_t *cpd, cyg_uint8 *esa_buf)
+{
+    int retval = -1;
+    cyg_uint8 response_msg[ETHER_ADDR_LEN];
+
+#if ENC424J600_DEBUG & 8
+    diag_printf("read_esa_u()...\n");
+#endif
+    if (NULL == esa_buf)
+    {
+        return -1;
+    }
+
+    retval = unbanked_register_operation(cpd, ENC424J600_READCRU, ENC424J600_MAADR3_U, ETHER_ADDR_LEN,
+                                         &response_msg[0]);
+    if (0 != retval)
+    {
+        return retval;
+    }
+    *esa_buf++ = response_msg[4];
+    *esa_buf++ = response_msg[5];
+    *esa_buf++ = response_msg[2];
+    *esa_buf++ = response_msg[3];
+    *esa_buf++ = response_msg[0];
+    *esa_buf   = response_msg[1];
+
+    return 0;
+}
+
+// Set ESA into Ethernet chip, unbanked
+static int
+write_esa_u(enc424j600_priv_data_t *dpd, cyg_uint8 *esa_buf)
+{
+    int retval = -1;
+    cyg_uint8 msg[8];
+
+#if ENC424J600_DEBUG & 8
+    diag_printf("write_esa_u()...1...\n");
+#endif
+    if (NULL == esa_buf)
+    {
+        return -1;
+    }
+
+    msg[4] = *esa_buf++;
+    msg[5] = *esa_buf++;
+    msg[2] = *esa_buf++;
+    msg[3] = *esa_buf++;
+    msg[0] = *esa_buf++;
+    msg[1] = *esa_buf;
+
+    retval = unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_MAADR3_U, 6, &msg[0]);
+    if (0 != retval)
+    {
+#if ENC424J600_DEBUG & 1
+    diag_printf("Writing ESA into chip failed.\n");
+#endif
+        return retval;
+    }
+
+    return 0;
+}
+
+#if ENC424J600_DEBUG & 0x20
+// Read data from PHY register
+static void
+read_phy(enc424j600_priv_data_t *dpd,
+    const enum enc424j600_pr_address_e pr_address,
+    cyg_uint16 *retval_p)
+{
+    cyg_uint8 aux[2] = {pr_address, 0x01};
+    cyg_uint8 status;
+
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_MIREGADR_U, 2, &aux[0]);
+    unbanked_register_operation(dpd, ENC424J600_READCRU, ENC424J600_MICMD_U, 2, &aux[0]);
+    aux[0] |= ENC424J600_MIIRD;
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_MICMD_U, 2, &aux[0]);
+    CYGACC_CALL_IF_DELAY_US(26);
+    do
+    {   // Check and busy wait for read operation to complete
+        unbanked_register_operation(dpd, ENC424J600_READCRU, ENC424J600_MISTAT_U, 1, &status);
+    } while(0 != (status & ENC424J600_MISTAT_BUSY));
+
+    aux[0] &= !ENC424J600_MIIRD; // Clear ENC424J600_MIIRD bit
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_MICMD_U, 2, &aux[0]);
+
+    unbanked_register_operation(dpd, ENC424J600_READCRU, ENC424J600_MIRD_U, 2, &aux[0]);
+    *retval_p = aux[0] + 256 * aux[1];
+
+    return;
+}
+#endif
+
+// Write data to PHY register
+static void
+write_phy(enc424j600_priv_data_t *dpd,
+    const enum enc424j600_pr_address_e pr_address,
+    const cyg_uint16 value)
+{
+    cyg_uint8 aux[2] = {pr_address, 0x01};
+
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_MIREGADR_U, 2, &aux[0]);
+    aux[0] = value & 0xff;
+    aux[1] = (value >> 8) & 0xff;
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_MIWR_U, 2, &aux[0]);
+
+    return;
+    // There must be no other MIIM operation in the following 25.6 us!
+}
+
+// Write value for on-chip pointer.
+static void
+set_pointer(enc424j600_priv_data_t *dpd,
+    enum enc424j600_spi_bufferp_e oc_pointer,
+    cyg_uint16 value
+    )
+{
+    cyg_spi_transaction_begin(dpd->spi_service_device);
+    cyg_spi_transaction_transfer(dpd->spi_service_device,
+        SPI_POLLING,
+        1,
+        & oc_pointer,
+        NULL,           // not interested in answer
+        ENC424J600_DONT_DROP_CS);
+    cyg_spi_transaction_transfer(dpd->spi_service_device,
+        SPI_POLLING,
+        2,
+        (cyg_uint8 *) & value,
+        NULL,           // not interested in answer
+        ENC424J600_DO_DROP_CS);
+    cyg_spi_transaction_end(dpd->spi_service_device);
+    return;
+}
+
+static inline void
+write_to_tx_buffer(enc424j600_priv_data_t *dpd,
+    cyg_uint16 length,
+    cyg_uint8 *buffer)
+{
+    cyg_uint8 oc_pointer = ENC424J600_WGPDATA; // We use General Purpose Buffer
+
+    cyg_spi_transaction_begin(dpd->spi_service_device);
+    cyg_spi_transaction_transfer(dpd->spi_service_device,
+        SPI_POLLING,
+        1,
+        & oc_pointer,
+        NULL,           // not interested in answer
+        ENC424J600_DONT_DROP_CS);
+    cyg_spi_transaction_transfer(dpd->spi_service_device,
+        SPI_POLLING,
+        length,
+        buffer,
+        NULL,
+        ENC424J600_DO_DROP_CS);
+    cyg_spi_transaction_end(dpd->spi_service_device);
+
+    return;
+}
+
+static int
+read_from_rx_buffer(enc424j600_priv_data_t *dpd,
+    cyg_uint16 length,
+    cyg_uint8 *buffer)
+{
+    cyg_uint8 oc_pointer = ENC424J600_RRXDATA;
+
+//    if ((0 == length) || (NULL == buffer))
+    if (0 == length)
+    {
+        return -1;
+    }
+    cyg_spi_transaction_begin(dpd->spi_service_device);
+    cyg_spi_transaction_transfer(dpd->spi_service_device,
+        SPI_POLLING,
+        1,
+        & oc_pointer,
+        NULL,           // not interested in answer
+        ENC424J600_DONT_DROP_CS);
+    cyg_spi_transaction_transfer(dpd->spi_service_device,
+        SPI_POLLING,
+        length,
+        NULL,
+        buffer,
+        ENC424J600_DO_DROP_CS);
+    cyg_spi_transaction_end(dpd->spi_service_device);
+
+    return 0;
+}
+
+static void
+set_MAC(enc424j600_priv_data_t *dpd,
+    cyg_uint8 ethernet_status   // As read from upper byte of ESTAT register
+    )
+{
+    cyg_uint8 aux[2];
+
+    if (0 != (ethernet_status & ENC424J600_PHYDPX))
+    {   // Full duplex
+#if ENC424J600_DEBUG & 0x20
+        diag_printf("Full duplex\n");
+#endif
+        unbanked_register_operation(dpd, ENC424J600_READCRU, ENC424J600_MACON2_U, 2, &aux[0]);
+        aux[0] |= ENC424J600_FULDPX;    // Set MAC to full duplex
+        unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_MACON2_U, 2, &aux[0]);
+
+        aux[1] = 0;
+        aux[0] = 0x15;  // Inter-packet gap
+        unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_MABBIPG_U, 2, &aux[0]);
+    }
+    else
+    {   // Half duplex
+#if ENC424J600_DEBUG & 0x20
+        diag_printf("Half duplex\n");
+#endif
+        unbanked_register_operation(dpd, ENC424J600_READCRU, ENC424J600_MACON2_U, 2, &aux[0]);
+        aux[0] &= !ENC424J600_FULDPX; // Set MAC to half duplex
+        unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_MACON2_U, 2, &aux[0]);
+
+        aux[1] = 0;
+        aux[0] = 0x12;  // Inter-packet gap
+        unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_MABBIPG_U, 2, &aux[0]);
+    }
+
+    return;
+}
+
+static void
+enc424j600_spi_LINKevent(struct eth_drv_sc *sc)
+{
+    enc424j600_priv_data_t *dpd = (enc424j600_priv_data_t *)sc->driver_private;
+    cyg_uint8 iflag = ENC424J600_LINKIF;
+    cyg_uint8 aux[2];
+
+#if ENC424J600_DEBUG & 8
+    diag_printf("enc424j600_spi_LINKevent()....\n");
+#endif
+
+    banked_register_operation(dpd, ENC424J600_READCR, ENC424J600_ESTATL, 2, &aux[0]);
+#if ENC424J600_DEBUG & 0x20
+    diag_printf("ESTAT %02x%02x Link ", aux[1], aux[0]);
+#endif
+    if (0 != (aux[1] & ENC424J600_PHYLNK))
+    {
+        dpd->link_status = ENC424J600_LINK_ON;
+
+#if ENC424J600_DEBUG & 0x20
+        diag_printf("ON\n");
+#endif
+        // Link is just established. Set up the MAC
+        set_MAC(dpd, aux[1]);
+    }
+    else
+    {
+        dpd->link_status = ENC424J600_LINK_OFF;
+
+#if ENC424J600_DEBUG & 0x20
+        diag_printf("OFF\n");
+#endif
+    }
+#if ENC424J600_DEBUG & 0x20
+    unbanked_register_operation(dpd, ENC424J600_READCRU, ENC424J600_MACON1_U, 2, &aux[0]);
+    diag_printf("MACON1 %02x%02x\n", aux[1], aux[0]);
+    unbanked_register_operation(dpd, ENC424J600_READCRU, ENC424J600_MACON2_U, 2, &aux[0]);
+    diag_printf("MACON2 %02x%02x\n", aux[1], aux[0]);
+    read_phy(dpd, ENC424J600_PHSTAT1, (cyg_uint16 *) &aux[0]);
+    diag_printf("PHSTAT1 %02x%02x\n", aux[1], aux[0]);
+    read_phy(dpd, ENC424J600_PHSTAT3, (cyg_uint16 *) &aux[0]);
+    diag_printf("PHSTAT3 %02x%02x\n", aux[1], aux[0]);
+    read_phy(dpd, ENC424J600_PHANLPA, (cyg_uint16 *) &aux[0]);
+    diag_printf("PHANLPA %02x%02x\n", aux[1], aux[0]);
+    read_phy(dpd, ENC424J600_PHANA, (cyg_uint16 *) &aux[0]);
+    diag_printf("PHANA %02x%02x\n", aux[1], aux[0]);
+    banked_register_operation(dpd, ENC424J600_READCR, ENC424J600_ECON1L, 2, &aux[0]);
+    diag_printf("ECON1 %02x%02x\n", aux[1], aux[0]);
+    unbanked_register_operation(dpd, ENC424J600_READCRU, ENC424J600_ECON2_U, 2, &aux[0]);
+    diag_printf("ECON2 %02x%02x\n", aux[1], aux[0]);
+
+#endif
+
+    // Clear Link interrupt flag
+    banked_register_operation(dpd, ENC424J600_BITFIELDCLEAR, ENC424J600_EIRH, 1, &iflag);
+}
+
+static void
+enc424j600_spi_PCFULevent(struct eth_drv_sc *sc)
+{
+    enc424j600_priv_data_t *dpd = (enc424j600_priv_data_t *)sc->driver_private;
+    cyg_uint8 flags = ENC424J600_PCFULIF;
+
+#if ENC424J600_DEBUG & 8
+    diag_printf("\nenc424j600_spi_PCFULevent()....\n\n");
+#endif
+    simple_operation(dpd, ENC424J600_SETPKTDEC);   // Decrement received packet counter
+    banked_register_operation(dpd, ENC424J600_BITFIELDCLEAR, ENC424J600_EIRL, 1, &flags);
+}
+
+static void
+enc424j600_spi_RXABTevent(struct eth_drv_sc *sc)
+{
+    enc424j600_priv_data_t *dpd = (enc424j600_priv_data_t *)sc->driver_private;
+    cyg_uint8 flags = ENC424J600_RXABTIF;
+
+#if ENC424J600_DEBUG & 8
+    diag_printf("\nenc424j600_spi_RXABTevent()....\n\n");
+#endif
+    banked_register_operation(dpd, ENC424J600_BITFIELDCLEAR, ENC424J600_EIRL, 1, &flags);
+}
+
+static void
+enc424j600_spi_TXevent(struct eth_drv_sc *sc)
+{
+    enc424j600_priv_data_t *dpd = (enc424j600_priv_data_t *)sc->driver_private;
+    cyg_uint8 iflag = ENC424J600_TXIF;
+
+#if ENC424J600_DEBUG & 8
+    diag_printf("TX event.\n");
+#endif
+
+    dpd->txbusy = false;
+    banked_register_operation(dpd, ENC424J600_BITFIELDCLEAR, ENC424J600_EIRL, 1, &iflag);
+}
+
+static void
+enc424j600_spi_TXABTevent(struct eth_drv_sc *sc)
+{
+    enc424j600_priv_data_t *dpd = (enc424j600_priv_data_t *)sc->driver_private;
+    cyg_uint8 iflag = ENC424J600_TXABTIF;
+
+#if ENC424J600_DEBUG & 8
+    diag_printf("TXABT event.\n");
+#endif
+
+    dpd->txbusy = false;
+    banked_register_operation(dpd, ENC424J600_BITFIELDCLEAR, ENC424J600_EIRL, 1, &iflag);
+}
+
+static void
+enc424j600_spi_RXevent(struct eth_drv_sc *sc)
+{
+    enc424j600_priv_data_t *dpd = (enc424j600_priv_data_t *)sc->driver_private;
+    cyg_uint8 pkcnt;    // Local copy of the packet counter
+    cyg_uint8 rsv[2];
+    cyg_uint16 packet_length;
+
+#if ENC424J600_DEBUG & 8
+    diag_printf("enc424j600_spi_RXevent()....\n");
+#endif
+
+    // Take info on single received packet
+    banked_register_operation(dpd, ENC424J600_READCR, ENC424J600_ESTATL, 1, &pkcnt);
+    if (0 != pkcnt)
+    {
+#if ENC424J600_DEBUG & 8
+        diag_printf("There are %u packets pending in receive buffer.\n", pkcnt);
+#endif
+        // Prepare on-chip read pointer
+        set_pointer(dpd, ENC424J600_RXRDPT, dpd->NextPacketPointer);
+        // The two bytes to read next point to the next packet
+        read_from_rx_buffer(dpd, 2, (cyg_uint8 *) & dpd->NextPacketPointer);
+
+        // Next 6 bytes to read are the Read Status Vector. We need only the first two.
+        read_from_rx_buffer(dpd, 2, & rsv[0]);
+        read_from_rx_buffer(dpd, 4, NULL);
+        packet_length = rsv[0] + rsv[1] * 256;
+        sc->funs->eth_drv->recv(sc, packet_length);
+    }
+
+    return;
+}
+
+// - End of local service functions -------------------------
+
+// - Higher level interface functions -----------------------
+
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+// This ISR is called when the Ethernet interrupt occurs
+static cyg_uint32
+enc424j600_spi_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
+{
+    cyg_drv_interrupt_mask(CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_VECTOR);
+    cyg_drv_interrupt_acknowledge(CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_VECTOR);
+
+    return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR);  // Run the DSR
+}
+
+static void
+enc424j600_spi_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
+{
+    enc424j600_priv_data_t *dpd = (enc424j600_priv_data_t *)data;
+    struct cyg_netdevtab_entry *ndp = (struct cyg_netdevtab_entry *)(dpd->tab);
+    struct eth_drv_sc *sc = (struct eth_drv_sc *)(ndp->device_instance);
+#if (ENC424J600_DEBUG & 2)
+    diag_printf("DSR: Interrupt! count %u\n", count);
+#endif
+
+#if (ENC424J600_DEBUG & 0x10)
+    extern void fake_eth_drv_dsr(cyg_vector_t vector,
+                            cyg_ucount32 count,
+                            cyg_addrword_t data);
+
+    fake_eth_drv_dsr( vector, count, (cyg_addrword_t)sc );
+#else
+    eth_drv_dsr( vector, count, (cyg_addrword_t)sc );
+#endif
+
+    return;
+}
+#endif // #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+
+// Initialization of driver and chip
+
+#define ENC424J600_INIT_SPI_READY_RETRY 100
+#define ENC424J600_INIT_CLK_READY_RETRY 100
+#define ENC424J600_INIT_RETRY_PERIOD_US 100
+
+static bool
+enc424j600_spi_init(struct cyg_netdevtab_entry *tab)
+{
+    int retval;
+    cyg_uint8 aux_8[2];
+    cyg_bool esa_configured = false;
+#ifdef CYGSEM_DEVS_ETH_ENC424J600_SET_ESA
+    cyg_uint8 esa_from_cdl[ETHER_ADDR_LEN] = CYGDAT_DEVS_ETH_ENC424J600_ESA;
+#endif
+    unsigned int i;  // loop counter
+
+    struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
+    enc424j600_priv_data_t *dpd = (enc424j600_priv_data_t *)sc->driver_private;
+
+    dpd->tab = tab;
+
+    CYG_DEVS_ETH_ENC424J600_PLF_INIT(tab);  // Platform HAL should define this macro
+
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    // Install interrupt handler.
+    cyg_drv_interrupt_create(CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_VECTOR,
+         CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_PRIORITY,
+         (cyg_addrword_t)dpd, //  Data item passed to interrupt handler
+         (cyg_ISR_t *)enc424j600_spi_isr,
+         (cyg_DSR_t *)enc424j600_spi_dsr,
+         &dpd->interrupt_handle,
+         &dpd->interrupt_object);
+    cyg_drv_interrupt_attach(dpd->interrupt_handle);
+    cyg_drv_interrupt_configure(CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_VECTOR,
+            ENC424J600_ETH_INTERRUPT_LEVEL_LOW, ENC424J600_ETH_INTERRUPT_EDGE_FALLING);
+    cyg_drv_interrupt_acknowledge(CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_VECTOR);
+    cyg_drv_interrupt_unmask(CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_VECTOR);
+#if ENC424J600_DEBUG & 4
+    diag_printf("%s(): Interrupt handler is installed.\n", __FUNCTION__);
+#endif
+#endif  //  #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+
+    // Check if the Ethernet chip is connected and listening
+    for (i=0; i <= ENC424J600_INIT_SPI_READY_RETRY; i++)
+    {
+        aux_8[1] = (cyg_uint8)0x12;   // Test pattern
+        aux_8[0] = (cyg_uint8)0x34;
+        banked_register_operation(dpd, ENC424J600_WRITECR, ENC424J600_EUDASTL, 2, &aux_8[0]);
+        banked_register_operation(dpd, ENC424J600_READCR, ENC424J600_EUDASTL, 2, &aux_8[0]);
+        // Verify the test pattern
+        if ((0x12 == aux_8[1]) && (0x34 == aux_8[0]))
+        {   // verified
+            break;
+        }
+        CYGACC_CALL_IF_DELAY_US(ENC424J600_INIT_RETRY_PERIOD_US);
+    }
+
+    if (i > ENC424J600_INIT_SPI_READY_RETRY)
+    {
+        CYG_FAIL("enc424j600 SPI is not ready!\n");
+        return false;
+    }
+
+#if ENC424J600_DEBUG & 4
+        diag_printf("enc424j600 SPI is there.\n");
+#endif
+
+    // Check if ENC424J600_CLKRDY flag is set
+    for (i=0; i <= ENC424J600_INIT_CLK_READY_RETRY; i++)
+    {
+        banked_register_operation(dpd, ENC424J600_READCR, ENC424J600_ESTATL, 2, &aux_8[0]);
+        if (0 == (aux_8[1] & ENC424J600_CLKRDY))
+        {
+            i++;
+        }
+        else
+        {   // clock is ready
+            break;
+        }
+        CYGACC_CALL_IF_DELAY_US(ENC424J600_INIT_RETRY_PERIOD_US);
+    }
+    if (i > ENC424J600_INIT_CLK_READY_RETRY)
+    {
+        CYG_FAIL("enc424j600 clock is not ready!\n");
+        return false;
+    }
+
+#if ENC424J600_DEBUG & 4
+        diag_printf("enc424j600 clock is ready.\n");
+#endif
+
+    // Issue a System Reset for Ethernet chip
+    aux_8[0] = ENC424J600_ETHRST;
+    unbanked_register_operation(dpd, ENC424J600_BITFIELDSETU, ENC424J600_ECON2_U, 1, &aux_8[0]);
+    CYGACC_CALL_IF_DELAY_US(25);
+    // Check if the reset really happened
+    banked_register_operation(dpd, ENC424J600_READCR, ENC424J600_EUDASTL, 2, &aux_8[0]);
+    if ((0 != aux_8[0]) || (0 != aux_8[1]))
+    {
+        CYG_FAIL("enc424j600 is not reset!\n");
+        return false;
+    }
+#if ENC424J600_DEBUG & 4
+    diag_printf("Successful reset of the Ethernet chip.\n");
+#endif
+
+    CYGACC_CALL_IF_DELAY_US(256);
+
+#define CLOCKOUT_CODE(_freq_) CLOCKOUT_LABEL(_freq_)
+#define CLOCKOUT_LABEL(_freq_) (ENC424J600_CLKO_##_freq_)
+
+    // Set clock output frequency. External hardware may need it.
+    unbanked_register_operation(dpd, ENC424J600_READCRU, ENC424J600_ECON2_U + 1, 1, &aux_8[1]);
+    aux_8[1] &= 0xf0;
+    aux_8[1] |= (cyg_uint8)CLOCKOUT_CODE(CYGNUM_DEVS_ETH_ENC424J600_CLOCKOUT_FREQUENCY);
+#if ENC424J600_DEBUG & 4
+    diag_printf("Setting clock out, ECON2H 0x%02x\n", aux_8[1]);
+#endif
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_ECON2_U + 1, 1, &aux_8[1]);
+
+
+    // Find ESA - check possible sources in sequence and stop when
+    // one provides the ESA:
+    //   RedBoot option (via provide_esa)
+    //   Set by application
+    //   Set by configuration option
+    //   Ethernet chip (manufacture-time set)
+
+    if (NULL != dpd->provide_esa)
+    {
+        esa_configured = dpd->provide_esa(dpd);
+# if ENC424J600_DEBUG & 4
+        if (esa_configured)
+            diag_printf("Got ESA from RedBoot option\n");
+# endif
+    }
+    if (!esa_configured && dpd->hardwired_esa)
+    {
+        // ESA is already set in dpd->esa[]
+#if ENC424J600_DEBUG & 4
+        diag_printf("Got hardcoded ESA\n");
+#endif
+        esa_configured = true;
+    }
+#ifdef CYGSEM_DEVS_ETH_ENC424J600_SET_ESA
+    else
+    {
+        memcpy(dpd->esa, esa_from_cdl, ETHER_ADDR_LEN);
+        esa_configured = true;
+# if ENC424J600_DEBUG & 4
+        diag_printf("Got ESA from CDL.\n");
+# endif
+    }
+#endif  //  #ifdef CYGSEM_DEVS_ETH_ENC424J600_SET_ESA
+
+    if (!esa_configured)
+    {
+# if ENC424J600_DEBUG & 4
+        diag_printf("ESA is not provided. Getting it from the chip.\n");
+# endif
+        retval = read_esa_u(dpd, &(dpd->esa[0]));
+        if (0 != retval)
+        {
+            CYG_FAIL("Reading ESA from chip failed.\n");
+            return false;
+        }
+    }
+    else
+    {
+# if ENC424J600_DEBUG & 4
+        diag_printf("Setting ESA into chip. Will last till next reset.\n");
+# endif
+        retval = write_esa_u(dpd, &(dpd->esa[0]));
+        if (0 != retval)
+        {
+            CYG_FAIL("Writing ESA into chip failed.\n");
+            return false;
+        }
+    }
+
+# if ENC424J600_DEBUG & 4
+    cyg_uint8 cesa[ETHER_ADDR_LEN] = {0,0,0,0,0,0};
+    diag_printf("ESA %02x:%02x:%02x:%02x:%02x:%02x\n",
+                dpd->esa[0], dpd->esa[1], dpd->esa[2],
+                dpd->esa[3], dpd->esa[4], dpd->esa[5]);
+    retval = read_esa_u(dpd, &cesa[0]);
+    if (0 != retval)
+    {
+        diag_printf("Reading ESA from chip failed.\n");
+    }
+    diag_printf("Control reading from chip: ");
+    diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
+        cesa[0], cesa[1], cesa[2],
+        cesa[3], cesa[4], cesa[5]);
+# endif
+
+    // Set receive filters
+    aux_8[0] = ENC424J600_BCEN | ENC424J600_UCEN | ENC424J600_RUNTEN | ENC424J600_CRCEN;
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_ERXFCON_U, 1, &aux_8[0]);
+
+#ifdef CYGSEM_DEVS_ETH_ENC424J600_FLOWC_OnChip
+#if ENC424J600_DEBUG & 4
+    diag_printf("eth_spi_enc424j600_init() Setting auto flow control\n");
+#endif
+    // Duration of pause
+    aux_8[0] = CYGNUM_DEVS_ETH_ENC424J600_FLOWC_PAUSE & 0xff;
+    aux_8[1] = (CYGNUM_DEVS_ETH_ENC424J600_FLOWC_PAUSE >> 8 ) & 0xff;
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_EPAUS_U, 2, &aux_8[0]);
+
+    // Thresholds for flow control
+    aux_8[0] = CYGNUM_DEVS_ETH_ENC424J600_FLOWC_LOWER_WATERMARK;
+    aux_8[1] = CYGNUM_DEVS_ETH_ENC424J600_FLOWC_UPPER_WATERMARK;
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_ERXWM_U, 2, &aux_8[0]);
+
+    aux_8[0] = ENC424J600_AUTOFC;  // Enable automatic flow control
+    unbanked_register_operation(dpd, ENC424J600_BITFIELDSETU, ENC424J600_ECON2_U, 1, &aux_8[0]);
+
+#else
+    // No flow control
+    simple_operation(dpd, ENC424J600_FCDISABLE);
+#endif
+
+    // Set PHY speed and duplex
+    aux_8[0] = aux_8[1] = 0;
+#ifndef CYGNUM_DEVS_ETH_ENC424J600_NO_AUTO_NEGOTIATION
+    aux_8[1] = ENC424J600_ANEN;  // Enable auto negotiation
+#else
+#   if(CYGNUM_DEVS_ETH_ENC424J600_SPEED == 100)
+        aux_8[1] |= ENC424J600_SPD100;
+#   endif
+#   ifdef CYGSEM_DEVS_ETH_ENC424J600_FULL_DUPLEX
+        aux_8[1] |= ENC424J600_PFULDPX;
+#   endif
+#endif
+#if ENC424J600_DEBUG & 4
+    diag_printf("Writing PHCON1 0x%02x%02x\n", aux_8[1], aux_8[0]);
+#endif
+    write_phy(dpd, ENC424J600_PHCON1, (aux_8[1] << 8) + aux_8[0]);
+    CYGACC_CALL_IF_DELAY_US(26);
+
+    // Compose and set PHY capabilities advertisement register
+    aux_8[1] = 0;
+    aux_8[0] = ENC424J600_IEEE802_3STD;
+#ifdef CYGNUM_DEVS_ETH_ENC424J600_FLOWC_ENC424J600_ONCHIP_AUTO_FC
+    aux_8[1] |= ENC424J600_ADPAUS_SYMM;
+#endif
+
+#ifdef CYGNUM_DEVS_ETH_ENC424J600_NO_AUTO_NEGOTIATION
+#   ifdef CYGSEM_DEVS_ETH_ENC424J600_FULL_DUPLEX
+#      if(CYGNUM_DEVS_ETH_ENC424J600_SPEED == 100)
+           aux_8[1] |= ENC424J600_AD100FD;
+#      else
+           aux_8[0] |= ENC424J600_AD10FD;
+#      endif
+#   else
+#      if(CYGNUM_DEVS_ETH_ENC424J600_SPEED == 100)
+           aux_8[0] |= ENC424J600_AD100;
+#      else
+           aux_8[0] |= ENC424J600_AD10;
+#      endif
+#   endif
+#else
+    aux_8[1] |= ENC424J600_AD100FD;
+    aux_8[0] |= ENC424J600_AD100 | ENC424J600_AD10FD | ENC424J600_AD10;
+#endif
+
+    write_phy(dpd, ENC424J600_PHANA, (aux_8[1] << 8) + aux_8[0]);
+
+#if ENC424J600_DEBUG & 4
+    diag_printf("Setting CRC generation\n");
+#endif
+
+    // Set ENC424J600_TXCRCEN, PADCFG
+    unbanked_register_operation(dpd, ENC424J600_READCRU, ENC424J600_MACON2_U, 2, &aux_8[0]);
+    aux_8[0] = 0xa0;      // Pad VLAN frames to 64bytes, others to 60
+    aux_8[0] |= ENC424J600_TXCRCEN;  // Calculate and append CRC in transmit frames
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_MACON2_U, 2, &aux_8[0]);
+
+#if ENC424J600_DEBUG & 4
+    diag_printf("Setting acceptable packet size\n");
+#endif
+    // Set acceptable packet size
+    aux_8[0] = CYGNUM_DEVS_ETH_ENC424J600_ACCEPTABLE_PACKET_SIZE & 0xff;
+    aux_8[1] = (CYGNUM_DEVS_ETH_ENC424J600_ACCEPTABLE_PACKET_SIZE >> 8) & 0xff;
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_MAMXFL_U, 2, &aux_8[0]);
+
+#if ENC424J600_DEBUG & 2
+    diag_printf("Initializing upper level driver\n");
+#endif
+    (sc->funs->eth_drv->init)(sc, dpd->esa);
+
+#if ENC424J600_DEBUG & 4
+    diag_printf("End of _init().\n");
+#endif
+
+    return true;
+}
+
+//
+// This function is called to "start up" the interface.  It may be called
+// multiple times, even when the hardware is already running.  It will be
+// called whenever something "hardware oriented" changes and should leave
+// the hardware ready to send/receive packets.
+//
+static void
+enc424j600_spi_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
+{
+    enc424j600_priv_data_t *dpd = (enc424j600_priv_data_t *)sc->driver_private;
+    cyg_uint8 aux[2];
+    cyg_uint8 pkcnt;
+
+#if ENC424J600_DEBUG & 8
+    diag_printf("enc424j600_spi_start() begin.\n");
+#endif
+    // Disable packet reception
+    simple_operation(dpd, ENC424J600_DISABLERX);
+
+    // Enable interrupts in Ethernet chip
+    simple_operation(dpd, ENC424J600_CLREIE); // First disable interrupts globally
+
+    aux[0] = ENC424J600_PKTIE | ENC424J600_TXIE | ENC424J600_TXABTIE | ENC424J600_RXABTIE | ENC424J600_PCFULIE; // then set the desired ones
+    aux[1] = ENC424J600_LINKIE;
+    unbanked_register_operation(dpd, ENC424J600_BITFIELDSETU, ENC424J600_EIE_U, 2, &aux[0]);
+
+    // Are there any packets left in receive buffer?
+    banked_register_operation(dpd, ENC424J600_READCR, ENC424J600_ESTATL, 1, &pkcnt);
+
+    while (0 < pkcnt--)
+    {
+        simple_operation(dpd, ENC424J600_SETPKTDEC);   // Decrement on-chip packet counter
+    }                                       // This clears ENC424J600_PKTIF, if set.
+
+    // Set the chip's receive buffer start address and buffer head.
+    aux[0] = ENC424J600_RXBUF_START & 0xfe;          // make it even, just in case it's not
+    aux[1] = (ENC424J600_RXBUF_START >> 8) & 0x7f;   // clear the MSB
+#if ENC424J600_DEBUG & 8
+    diag_printf("Setting receive buffer start address, ERXST 0x%02x%02x.\n",
+                aux[1], aux[0]);
+#endif
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_ERXST_U, 2, &aux[0]);
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_ERXHEAD_U, 2, &aux[0]);
+
+    // Next packet will be received at the buffer start address
+    *(cyg_uint8 *) & dpd->NextPacketPointer = ENC424J600_RXBUF_START & 0xff;
+    *(((cyg_uint8 *)&dpd->NextPacketPointer) + 1) = (ENC424J600_RXBUF_START >> 8 ) & 0xff;
+
+    // Set receive buffer tail
+    aux[1] = 0x5f;  // just bellow the end of on-chip SRAM
+    aux[0] = 0xfe;
+#if ENC424J600_DEBUG & 8
+    diag_printf("Setting receive buffer tail, ERXTAIL 0x%02x%02x.\n",
+                aux[1], aux[0]);
+#endif
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_ERXTAIL_U, 2, &aux[0]);
+
+    // Abort any pending transmission
+    aux[0] = ENC424J600_TXRTS;
+    banked_register_operation(dpd, ENC424J600_BITFIELDCLEAR, ENC424J600_ECON1L, 1, &aux[0]);
+    dpd->txbusy = false;
+
+    // Set start of transmit buffer
+    aux[0] = ENC424J600_TXBUF_START & 0xff;
+    aux[1] = (ENC424J600_TXBUF_START >> 8 ) & 0xff;
+#if ENC424J600_DEBUG & 8
+    diag_printf("Writing ETXST 0x%02x%02x.\n", aux[1], aux[0]);
+#endif
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_ETXST_U, 2, &aux[0]);
+
+    // Clear any remaining interrupt flags
+    aux[0] = ENC424J600_TXIF | ENC424J600_TXABTIF | ENC424J600_RXABTIF | ENC424J600_PCFULIF;
+    aux[1] = ENC424J600_LINKIF;
+    banked_register_operation(dpd, ENC424J600_BITFIELDCLEAR, ENC424J600_EIRL, 2, &aux[0]);
+
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    simple_operation(dpd, ENC424J600_SETEIE);  // Enable interrupts
+#endif
+
+    // Enable packet reception
+    simple_operation(dpd, ENC424J600_ENABLERX);
+
+    banked_register_operation(dpd, ENC424J600_READCR, ENC424J600_ESTATL, 2, &aux[0]);
+    if (0 != (aux[1] & ENC424J600_PHYLNK))
+    {
+        if (ENC424J600_LINK_ON != dpd->link_status)
+        {
+            dpd->link_status = ENC424J600_LINK_ON;
+            set_MAC(dpd, aux[1]);
+        }
+    }
+    else
+    {
+        dpd->link_status = ENC424J600_LINK_OFF;
+    }
+
+#if ENC424J600_DEBUG & 8
+    diag_printf("enc424j600_spi_start() end.\n");
+#endif
+
+    return;
+}
+
+// Stop receiving and sending packets
+static void
+enc424j600_spi_stop(struct eth_drv_sc *sc)
+{
+    enc424j600_priv_data_t *dpd = (enc424j600_priv_data_t *)sc->driver_private;
+    cyg_uint8 aux[2];
+
+#if ENC424J600_DEBUG & 8
+    diag_printf("enc424j600_spi_stop() begin.\n");
+#endif
+    // Disable packet reception
+    simple_operation(dpd, ENC424J600_DISABLERX);
+
+    // Disable interrupts in Ethernet chip
+    aux[1] = ENC424J600_INTIE;
+    aux[0] = ENC424J600_PKTIE | ENC424J600_TXIE | ENC424J600_TXABTIE | ENC424J600_RXABTIE | ENC424J600_PCFULIE;
+    unbanked_register_operation(dpd, ENC424J600_BITFIELDCLEARU, ENC424J600_EIE_U, 2, &aux[0]);
+
+    return;
+}
+
+static void
+enc424j600_spi_deliver(struct eth_drv_sc *sc)
+{
+
+    enc424j600_spi_poll(sc);
+
+    return;
+}
+
+// Special control operations
+static int
+enc424j600_spi_control(struct eth_drv_sc *sc, unsigned long key, void *data,
+        int data_length)
+{
+    enc424j600_priv_data_t *dpd;
+    unsigned char *esa;
+    struct eth_drv_mc_list *mc_list;
+    cyg_uint8 aux;
+
+    if ((NULL == sc) || (NULL == data))
+    {
+#if ENC424J600_DEBUG & 1
+        diag_printf("Wrong parameter(s) for enc424j600_spi_control().\n");
+#endif
+        return -1;
+    }
+    dpd = (enc424j600_priv_data_t *)sc->driver_private;
+    switch (key)
+    {
+        case ETH_DRV_SET_MAC_ADDRESS:
+            if (ETHER_ADDR_LEN != data_length)
+            {
+#if ENC424J600_DEBUG & 1
+                diag_printf("Wrong data length for ETH_DRV_SET_MAC_ADDRESS.\n");
+#endif
+                return -1;
+            }
+            esa = (unsigned char *)data;
+            // Write ESA in the chip. Will last till the next reset.
+            return write_esa_u(dpd, esa);
+
+#ifdef ETH_DRV_GET_MAC_ADDRESS
+        case ETH_DRV_GET_MAC_ADDRESS:
+            if (ETHER_ADDR_LEN > data_length)
+            {
+#if ENC424J600_DEBUG & 1
+                diag_printf("Too small data length for ETH_DRV_GET_MAC_ADDRESS.\n");
+#endif
+                return -1;
+            }
+            esa = (unsigned char *)data;
+            // Get ESA from the chip
+            return read_esa_u(dpd, esa);
+#endif
+
+        case ETH_DRV_SET_MC_LIST:
+        case ETH_DRV_SET_MC_ALL:
+            // Note: this code always affects all multicast addresses if any
+            // are desired.
+            mc_list = data;
+            simple_operation(dpd, ENC424J600_DISABLERX);
+            aux = ENC424J600_MCEN;
+            if (0 == mc_list->len)
+            {   // Disable reception of multicast packets
+                unbanked_register_operation(dpd,
+                    ENC424J600_BITFIELDCLEARU, ENC424J600_ERXFCON_U, 1, &aux);
+            }
+            else
+            {   // Enable reception of multicast packets
+                unbanked_register_operation(dpd,
+                    ENC424J600_BITFIELDSETU, ENC424J600_ERXFCON_U, 1, &aux);
+            }
+            simple_operation(dpd, ENC424J600_ENABLERX);
+
+            return 0;
+
+        default:
+#if ENC424J600_DEBUG & 1
+            diag_printf("Unsupported key %lx for enc424j600_spi_control().\n", key);
+#endif
+            return -1;
+    }
+}
+
+// Continue transfer from chip's buffer where the enc424j600_spi_RXevent() stopped.
+// Take one packet.
+static void
+enc424j600_spi_recv(struct eth_drv_sc *sc,
+    struct eth_drv_sg *sg_list,
+    int chunks)
+{
+    int chunk;
+    enc424j600_priv_data_t *dpd = (enc424j600_priv_data_t *)sc->driver_private;
+    cyg_uint16 rbuf_tail;
+    cyg_uint8 * aux_p;
+    cyg_uint8 aux[2];
+
+#if ENC424J600_DEBUG & 8
+    diag_printf("enc424j600_spi_recv()...\n");
+#endif
+
+    for(chunk = 0; chunk < chunks; chunk++)
+    {
+        read_from_rx_buffer(dpd, (*sg_list).len, (cyg_uint8 *)(*sg_list).buf);
+        sg_list++;
+    }
+    aux_p = (cyg_uint8 *) & dpd->NextPacketPointer;
+    rbuf_tail = *aux_p + *(aux_p+1) * (cyg_uint16)256 ;
+    rbuf_tail -= 2;
+    if (rbuf_tail == ENC424J600_RXBUF_START)
+    {   // Wrap over
+        rbuf_tail = 0x5ffe;
+    }
+    aux[0] = rbuf_tail & 0xff;
+    aux[1] = (rbuf_tail >> 8) & 0xff;
+#if ENC424J600_DEBUG & 8
+    diag_printf("Setting receive buffer tail, ERXTAIL 0x%02x%02x.\n",
+        aux[1], aux[0]);
+#endif
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_ERXTAIL_U, 2, &aux[0]);
+
+    simple_operation(dpd, ENC424J600_SETPKTDEC);   // Decrement packet count. If zeroed,
+                                        // ENC424J600_PKTIF interrupt flag will be reset.
+
+    return;
+}
+
+// This routine is called to see if it is possible to send another packet.
+// It will return non-zero if a transmit is possible, zero otherwise.
+static int
+enc424j600_spi_can_send(struct eth_drv_sc *sc)
+{
+    if (((enc424j600_priv_data_t *)sc->driver_private)->txbusy)
+    {
+        return 0;
+    }
+    else
+    {
+        return 1;
+    }
+}
+
+// This routine is called to send data to the hardware.
+static void
+enc424j600_spi_send(struct eth_drv_sc *sc,
+    struct eth_drv_sg *sg_list,
+    int sg_len,
+    int total,
+    unsigned long key)
+{
+    enc424j600_priv_data_t *dpd = (enc424j600_priv_data_t *)sc->driver_private;
+    int block;
+    cyg_uint8 aux[2];
+    cyg_uint8 opcode = ENC424J600_WGPDATA;
+
+    if (0 >= sg_len) return;
+
+    // Check if there is enough room in transmit buffer
+    if (total > ENC424J600_RXBUF_START - ENC424J600_TXBUF_START)
+    {
+      sc->funs->eth_drv->tx_done(sc, (CYG_ADDRESS)key, 0);
+#if ENC424J600_DEBUG & 1
+      diag_printf("enc424j600_spi_send(): Packet to send is too large (%d bytes).\n",
+            total);
+#endif
+        return;
+    }
+
+    dpd->txbusy = true;
+    dpd->txkey = key;
+
+    aux[0] = ENC424J600_TXBUF_START & 0xff;
+    aux[1] = (((cyg_uint8)ENC424J600_TXBUF_START) >> 8) & 0xff;
+    set_pointer(dpd, ENC424J600_GPBWRPT, (aux[1] << 8) + aux[0]);
+
+#if ENC424J600_DEBUG & 8
+    diag_printf("Starting SPI transaction to send a packet.\n");
+#endif
+    cyg_spi_transaction_begin(dpd->spi_service_device);
+    cyg_spi_transaction_transfer(dpd->spi_service_device,
+        SPI_POLLING,
+        1,
+        & opcode,
+        NULL,
+        ENC424J600_DONT_DROP_CS);
+
+    for (block = 0; block < sg_len; block++)
+    {
+        cyg_spi_transaction_transfer(dpd->spi_service_device,
+            SPI_POLLING,
+            sg_list->len,
+            (cyg_uint8 *)sg_list->buf,
+            NULL,
+            (block == sg_len) ? ENC424J600_DO_DROP_CS : ENC424J600_DONT_DROP_CS );
+        sg_list++;
+    }
+    cyg_spi_transaction_end(dpd->spi_service_device);
+
+    aux[0] = total & 0xff;
+    aux[1] = (total >> 8 ) & 0xff;
+#if ENC424J600_DEBUG & 8
+    diag_printf("Writing ETXLEN 0x%02x%02x.\n", aux[1], aux[0]);
+#endif
+    unbanked_register_operation(dpd, ENC424J600_WRITECRU, ENC424J600_ETXLEN_U, 2, &aux[0]);
+
+#if ENC424J600_DEBUG & 8
+    diag_printf("Setting request to send.\n");
+#endif
+    simple_operation(dpd, ENC424J600_SETTXRTS);
+
+    sc->funs->eth_drv->tx_done(sc, (CYG_ADDRESS)key, 0);
+
+    return;
+}
+
+static void
+enc424j600_spi_poll(struct eth_drv_sc *sc)
+{
+    enc424j600_priv_data_t *dpd = (enc424j600_priv_data_t *)sc->driver_private;
+    cyg_uint8   aux[2];
+    cyg_uint16  iflags;
+
+#if ENC424J600_DEBUG & 8
+    diag_printf("enc424j600_spi_poll(%x)...\n", (cyg_uint32)sc);
+#endif
+
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    // Globally disable interrupt source in Ethernet chip
+    simple_operation(dpd, ENC424J600_CLREIE);
+#endif
+    do
+    {
+        // Figure out what caused the interrupt
+        banked_register_operation(dpd, ENC424J600_READCR, ENC424J600_EIRL, 2, &aux[0]);
+        aux[1] &= ENC424J600_LINKIF;
+        aux[0] &= (ENC424J600_PKTIF | ENC424J600_TXIF | ENC424J600_TXABTIF | ENC424J600_RXABTIF | ENC424J600_PCFULIF);
+        iflags = aux[0] + (cyg_uint16)256 * aux[1];
+        if (0 != (aux[0] & ENC424J600_PKTIF))
+        {   // Packets are pending in chip's receive buffer
+            enc424j600_spi_RXevent(sc);
+        }
+        if ( 0 != (aux[1] & ENC424J600_LINKIF))
+        {   // Link status changed
+            enc424j600_spi_LINKevent(sc);
+        }
+        if (0 != (aux[0] & ENC424J600_TXIF))
+        {   // Packet has been sent
+            enc424j600_spi_TXevent(sc);
+        }
+        if (0 != (aux[0] & ENC424J600_TXABTIF))
+        {   // Packet send has been aborted
+            enc424j600_spi_TXABTevent(sc);
+        }
+        if ( 0 != (aux[0] & ENC424J600_PCFULIF))
+        {   // Packet counter overflow
+            enc424j600_spi_PCFULevent(sc);
+        }
+        if ( 0 != (aux[0] & ENC424J600_RXABTIF))
+        {   // Incoming packet rejected due to buffer or counter overflow
+            enc424j600_spi_RXABTevent(sc);
+        }
+    } while(0 != iflags);
+
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    cyg_drv_interrupt_unmask(CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_VECTOR);
+
+    // Globally enable interrupt source in Ethernet chip
+    simple_operation(dpd, ENC424J600_SETEIE);
+#endif
+
+    return;
+}
+
+static int
+enc424j600_spi_int_vector(struct eth_drv_sc *sc)
+{
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    return CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_VECTOR;
+#else
+    return 0;
+#endif
+}
+
+// - End of higher level interface -----------------------------
+
+// End of enc424j600_spi.c
diff --git a/packages/devs/eth/microchip/enc424j600/current/src/enc424j600_spi.h b/packages/devs/eth/microchip/enc424j600/current/src/enc424j600_spi.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/microchip/enc424j600/current/src/enc424j600_spi.h
@@ -0,0 +1,344 @@
+#ifndef CYGONCE_DEVS_ETH_ENC424J600_SPI_H_
+#define CYGONCE_DEVS_ETH_ENC424J600_SPI_H_
+//==========================================================================
+//
+//      enc424j600_spi.h
+//
+//      Microchip enc424j600 Ethernet chip
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2010 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija Stanislevik
+// Contributors:
+// Date:         2010-11-23
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+// Addresses of enc424j600 registers, banked access
+// Banks 0, 1, 2 & 3
+#define ENC424J600_EUDASTL      (0X16)
+#define ENC424J600_EUDASTH      (0X17)
+#define ENC424J600_EUDANDL      (0X18)
+#define ENC424J600_EUDANDH      (0X19)
+#define ENC424J600_ESTATL       (0x1a)
+#define ENC424J600_ESTATH       (0x1b)
+#define ENC424J600_EIRL         (0x1c)
+#define ENC424J600_EIRH         (0x1d)
+#define ENC424J600_ECON1L       (0x1e)
+#define ENC424J600_ECON1H       (0x1f)
+
+// Only bank 0
+#define ENC424J600_ETXSTL       (0x00)
+#define ENC424J600_ETXSTH       (0x01)
+#define ENC424J600_ETXLENL      (0x02)
+#define ENC424J600_ETXLENH      (0x03)
+#define ENC424J600_ERXSTL       (0x04)
+#define ENC424J600_ERXSTH       (0x05)
+#define ENC424J600_ERXTAILL     (0x06)
+#define ENC424J600_ERXTAILH     (0x07)
+#define ENC424J600_ERXHEADL     (0x08)
+#define ENC424J600_ERXHEADH     (0x09)
+
+// Only bank 1
+#define ENC424J600_ERXFCONL     (0x14)
+#define ENC424J600_ERXFCONH     (0x15)
+
+// Only bank 2
+#define ENC424J600_MACON1L      (0x00)
+#define ENC424J600_MACON1H      (0x01)
+#define ENC424J600_MACON2L      (0x02)
+#define ENC424J600_MACON2H      (0x03)
+#define ENC424J600_MABBIPGL     (0x04)
+#define ENC424J600_MABBIPGH     (0x05)
+#define ENC424J600_MAMXFLL      (0x0a)
+#define ENC424J600_MAMXFLH      (0x0b)
+#define ENC424J600_MICMDL       (0x12)
+#define ENC424J600_MICMDH       (0x13)
+#define ENC424J600_MIREGADRL    (0x14)
+#define ENC424J600_MIREGADRH    (0x15)
+#define ENC424J600_EIRL         (0x1c)
+#define ENC424J600_EIRH         (0x1d)
+#define ENC424J600_ECON1L       (0x1e)
+#define ENC424J600_ECON1H       (0x1f)
+
+// Only bank 3
+#define ENC424J600_MAADR3L      (0x00)
+#define ENC424J600_MIWRL        (0x06)
+#define ENC424J600_MIWRH        (0x07)
+#define ENC424J600_MIRDL        (0x08)
+#define ENC424J600_MIRDH        (0x09)
+#define ENC424J600_MISTATL      (0x0a)
+#define ENC424J600_MISTATH      (0x0b)
+#define ENC424J600_EPAUSL       (0x0c)
+#define ENC424J600_EPAUSH       (0x0d)
+#define ENC424J600_ECON2L       (0x0e)
+#define ENC424J600_ECON2H       (0x0f)
+#define ENC424J600_ERXWML       (0x10)
+#define ENC424J600_ERXWMH       (0x11)
+#define ENC424J600_EIEL         (0x12)
+#define ENC424J600_EIEH         (0x13)
+
+// Addresses of enc424j600 registers, unbanked access
+// Bank 0
+#define ENC424J600_BANK0_Of     (0)
+#define ENC424J600_ETXST_U      (ENC424J600_ETXSTL       + ENC424J600_BANK0_Of)
+#define ENC424J600_ETXLEN_U     (ENC424J600_ETXLENL      + ENC424J600_BANK0_Of)
+#define ENC424J600_EUDAST_U     (ENC424J600_EUDASTL      + ENC424J600_BANK0_Of)
+#define ENC424J600_EUDAND_U     (ENC424J600_EUDANDL      + ENC424J600_BANK0_Of)
+#define ENC424J600_ESTAT_U      (ENC424J600_ESTATL       + ENC424J600_BANK0_Of)
+#define ENC424J600_ERXST_U      (ENC424J600_ERXSTL       + ENC424J600_BANK0_Of)
+#define ENC424J600_ERXTAIL_U    (ENC424J600_ERXTAILL     + ENC424J600_BANK0_Of)
+#define ENC424J600_ERXHEAD_U    (ENC424J600_ERXHEADL     + ENC424J600_BANK0_Of)
+
+// Bank 1
+#define ENC424J600_BANK1_Of     (0x20)
+#define ENC424J600_ERXFCON_U   ( ENC424J600_ERXFCONL     + ENC424J600_BANK1_Of)
+
+// Bank 2
+#define ENC424J600_BANK2_Of     (0x40)
+#define ENC424J600_MACON1_U     (ENC424J600_MACON1L      + ENC424J600_BANK2_Of)
+#define ENC424J600_MACON2_U     (ENC424J600_MACON2L      + ENC424J600_BANK2_Of)
+#define ENC424J600_MABBIPG_U    (ENC424J600_MABBIPGL     + ENC424J600_BANK2_Of)
+#define ENC424J600_MAMXFL_U     (ENC424J600_MAMXFLL      + ENC424J600_BANK2_Of)
+#define ENC424J600_MICMD_U      (ENC424J600_MICMDL       + ENC424J600_BANK2_Of)
+#define ENC424J600_MIREGADR_U   (ENC424J600_MIREGADRL    + ENC424J600_BANK2_Of)
+#define ENC424J600_EIR_U        (ENC424J600_EIRL         + ENC424J600_BANK2_Of)
+#define ENC424J600_ECON1_U      (ENC424J600_ECON1L       + ENC424J600_BANK2_Of)
+
+// Bank 3
+#define ENC424J600_BANK3_Of     (0x60)
+#define ENC424J600_MAADR3_U     (ENC424J600_MAADR3L      + ENC424J600_BANK3_Of)
+#define ENC424J600_MIWR_U       (ENC424J600_MIWRL        + ENC424J600_BANK3_Of)
+#define ENC424J600_MIRD_U       (ENC424J600_MIRDL        + ENC424J600_BANK3_Of)
+#define ENC424J600_MISTAT_U     (ENC424J600_MISTATL      + ENC424J600_BANK3_Of)
+#define ENC424J600_EPAUS_U      (ENC424J600_EPAUSL       + ENC424J600_BANK3_Of)
+#define ENC424J600_ECON2_U      (ENC424J600_ECON2L       + ENC424J600_BANK3_Of)
+#define ENC424J600_ERXWM_U      (ENC424J600_ERXWML       + ENC424J600_BANK3_Of)
+#define ENC424J600_EIE_U        (ENC424J600_EIEL         + ENC424J600_BANK3_Of)
+
+// Addresses of enc424j600 PHY registers, special access
+
+enum enc424j600_pr_address_e
+{
+    ENC424J600_PHCON1  = 0,
+    ENC424J600_PHSTAT1 = 1,
+    ENC424J600_PHANA   = 4,
+    ENC424J600_PHANLPA = 5,
+    ENC424J600_PHANE   = 6,
+    ENC424J600_PHCON2  = 0x11,
+    ENC424J600_PHSTST2 = 0x1b,
+    ENC424J600_PHSTAT3 = 0x1f
+};
+
+//---------- end of register addresses --------------------------------------------------
+
+//---------- definitions of bits in control registers -----------------------------------
+
+// Interrupt flags (EIR register) higher byte
+#define ENC424J600_MODEXIF (0x40)
+#define ENC424J600_HASHIF  (0x20)
+#define ENC424J600_AESIF   (0x10)
+#define ENC424J600_LINKIF  (0x08)    // PHY status has changed
+
+// Interrupt flags (EIR register) lower byte
+#define ENC424J600_PKTIF   (0x40)    // RX packet(s) pending
+#define ENC424J600_DMAIF   (0x20)
+#define ENC424J600_TXIF    (0x08)    // Transmit done
+#define ENC424J600_TXABTIF (0x04)    // Packet transmission aborted due to an error
+#define ENC424J600_RXABTIF (0x02)    // RX packet rejected due to lack of space / to many
+                                     // pending packets
+#define ENC424J600_PCFULIF (0x01)    // To many pending packets
+
+// Interrupt enable bits (EIE register) higher byte
+#define ENC424J600_INTIE   (0x80)    // Global interrupt enable
+#define ENC424J600_MODEXIE (0x40)
+#define ENC424J600_HASHIE  (0x20)
+#define ENC424J600_AESIE   (0x10)
+#define ENC424J600_LINKIE  (0x08)    // PHY status has changed
+
+// Interrupt enable bits (EIE register) lower byte
+#define ENC424J600_PKTIE   (0x40)    // RX packet(s) pending
+#define ENC424J600_DMAIE   (0x20)
+#define ENC424J600_TXIE    (0x08)    // Transmit done
+#define ENC424J600_TXABTIE (0x04)    // Packet transmission aborted due to an error
+#define ENC424J600_RXABTIE (0x02)    // RX packet rejected due to lack of space / too many
+                                     // pending packets
+#define ENC424J600_PCFULIE (0x01)    // Too many pending packets
+
+// MICMD
+#define ENC424J600_MIIRD       (0x01)
+#define ENC424J600_MIISCAN     (0x02)
+
+// MISTAT
+#define ENC424J600_MISTAT_BUSY     (0x01)
+#define ENC424J600_MISTAT_SCAN     (0x02)
+#define ENC424J600_MISTAT_NVALID   (0x04)
+
+//ESTAT upper byte
+#define ENC424J600_PHYLNK      (0x01)
+#define ENC424J600_PHYDPX      (0x04)
+#define ENC424J600_CLKRDY      (0x10)
+#define ENC424J600_RXBUSY      (0x20)
+#define ENC424J600_FCIDLE      (0x40)
+#define ENC424J600_INT         (0x80)
+
+// ECON1 lower byte
+#define ENC424J600_TXRTS       (0x02)
+
+//ECON2 upper byte
+#define ENC424J600_STRCH       (0x40)
+#define ENC424J600_ETHEN       (0x80)
+
+// ECON2 lower byte
+#define ENC424J600_ETHRST      (0x10)
+#define ENC424J600_AUTOFC      (0x80)
+
+// MACON2 upper byte
+#define ENC424J600_NOBKOFF     (0x10)
+#define ENC424J600_BPEN        (0x20)
+#define ENC424J600_DEFER       (0x40)
+
+// MACON2 lower byte
+#define ENC424J600_FULDPX      (0x01)
+#define ENC424J600_HFRMEN      (0x04)
+#define ENC424J600_PHDREN      (0x08)
+#define ENC424J600_TXCRCEN     (0x10)
+
+// ERXFCON lower byte
+#define ENC424J600_BCEN        (0x01)    // accept broadcast packets
+#define ENC424J600_MCEN        (0x02)    // accept multicast packets
+#define ENC424J600_UCEN        (0x08)    // accept packets destined for local MAC address
+#define ENC424J600_RUNTEN      (0x10)    // discard runt packets
+#define ENC424J600_CRCEN       (0x40)    // discard packets with invalid CRC
+
+// PHCON1 upper byte
+#define ENC424J600_PFULDPX     (0x01)    // full duplex
+#define ENC424J600_RENEG       (0x02)    // restart negotiation
+#define ENC424J600_ANEN        (0x10)    // auto negotiation enable
+#define ENC424J600_SPD100      (0x20)    // 100Mb/s
+
+// PHANA upper byte
+#define ENC424J600_ADPAUS_BOTH     (0x0c)    // both symmetric and asymmetric flow control
+#define ENC424J600_ADPAUS_ASYM     (0x08)    // asymmetric flow control towards link partner
+#define ENC424J600_ADPAUS_SYMM     (0x04)    // symmetric flow control
+#define ENC424J600_ADPAUS_NONE     (0x00)    // no flow control
+#define ENC424J600_AD100FD         (0x01)
+
+// PHANA lower byte
+#define ENC424J600_AD100           (0x80)
+#define ENC424J600_AD10FD          (0x40)
+#define ENC424J600_AD10            (0x20)
+#define ENC424J600_IEEE802_3STD    (0x01)    //  IEEE Standard Selector Field bits
+
+//---------- end of definitions of bits in control registers -------------------------
+
+// enc424j600 SPI instructions opcodes
+
+// Single byte instructions
+enum enc424j600_spi_opcode_1_e
+{
+    ENC424J600_SETETHRST   = 0xca, // Issue System Reset
+    ENC424J600_SETPKTDEC   = 0xcc, // Decrement packet counter
+    ENC424J600_SETTXRTS    = 0xd4, // Send a packet
+    ENC424J600_FCDISABLE   = 0xe0, // Disable flow control
+    ENC424J600_FCSINGLE    = 0xe2, // Send a single pause frame
+    ENC424J600_FCMULTIPLE  = 0xe4, // Keep sending pause frames
+    ENC424J600_FCCLEAR     = 0xe6, // Send the final pause frame
+    ENC424J600_ENABLERX    = 0xe8, // Enable receiver
+    ENC424J600_DISABLERX   = 0xea, // Disable receiver
+    ENC424J600_SETEIE      = 0xec, // Enable interrupts
+    ENC424J600_CLREIE      = 0xee, // Disable interrupts
+};
+
+// Pointer definitions for 3-byte instructions
+enum enc424j600_spi_bufferp_e
+{
+    ENC424J600_GPBRDPT     = 0x60, // General purpose buffer read pointer
+    ENC424J600_RXRDPT      = 0x64, // Receive buffer read pointer
+    ENC424J600_UDARDPT     = 0x68, // User-defined area read pointer
+    ENC424J600_GPBWRPT     = 0x6c, // General purpose buffer write pointer
+    ENC424J600_RXWRPT      = 0x70, // Receive buffer write pointer
+    ENC424J600_UDAWRPT     = 0x74, // User-defined area write pointer
+
+};
+
+enum enc424j600_spi_opcode_3_e
+{
+    ENC424J600_WRITE3     = 0x00, // Pointer writing
+    ENC424J600_READ3      = 0x02  // Pointer reading
+
+};
+
+// N-byte unbanked SFR instructions
+enum enc424j600_spi_opcode_u_e
+{
+    ENC424J600_READCRU         = 0x20, // Read Control Register, Unbanked
+    ENC424J600_WRITECRU        = 0x22, // Write Control Register, Unbanked
+    ENC424J600_BITFIELDSETU    = 0x24, // Bit Field Set, Unbanked
+    ENC424J600_BITFIELDCLEARU  = 0x26 // Bit Field Clear, Unbanked
+};
+
+// N-byte banked SFR instructions
+enum enc424j600_spi_opcode_e
+{
+    ENC424J600_READCR          = 0x00, // Read Control Register, Banked
+    ENC424J600_WRITECR         = 0x40, // Write Control Register, Banked
+    ENC424J600_BITFIELDSET     = 0x80, // Bit Field Set, Banked
+    ENC424J600_BITFIELDCLEAR   = 0xa0 // Bit Field Clear, Banked
+};
+
+// N-byte SRAM instructions
+enum enc424j600_spi_opcode_sram_e
+{
+    ENC424J600_RGPDATA = 0x28,  // Read from General Purpose buffer
+    ENC424J600_WGPDATA = 0x2a,  // Write to General Purpose buffer
+    ENC424J600_RRXDATA = 0x2c,  // Read from Rx buffer
+    ENC424J600_WRXDATA = 0x2e   // Write to Rx buffer
+};
+
+#define ENC424J600_ETH_INTERRUPT_LEVEL_HIGH    (true)
+#define ENC424J600_ETH_INTERRUPT_LEVEL_LOW     (false)
+#define ENC424J600_ETH_INTERRUPT_EDGE_RISING   (true)
+#define ENC424J600_ETH_INTERRUPT_EDGE_FALLING  (false)
+
+//#define ETH_DRV_GET_MAC_ADDRESS (0x1100)
+
+#endif /* ifndef CYGONCE_DEVS_ETH_ENC424J600_SPI_H_ */
+// End of enc424j600_spi.h
diff --git a/packages/devs/eth/microchip/enc424j600/current/tests/netconn_test_server.c b/packages/devs/eth/microchip/enc424j600/current/tests/netconn_test_server.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/microchip/enc424j600/current/tests/netconn_test_server.c
@@ -0,0 +1,354 @@
+//==========================================================================
+//
+//      netconn_test_server.c
+//
+//      Utility to test enc424j600 Ethernet driver
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2010 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija Stanislevik
+// Contributors:
+// Date:         2010-08-04
+// Purpose:
+// Description:  Utility to test enc424j600 (or any other) Ethernet driver
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/testcase.h>         // Test macros
+#include <cyg/infra/cyg_ass.h>          // Assertion macros
+#include <cyg/infra/diag.h>             // Diagnostic output
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_if.h>
+
+#include <cyg/hal/hal_arch.h>           // CYGNUM_HAL_STACK_SIZE_TYPICAL
+#include <cyg/kernel/kapi.h>
+
+#include <string.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <cyg/error/codes.h>
+#include <cyg/io/io.h>
+
+#include <cyg/io/spi.h>
+
+#include <cyg/io/eth/netdev.h>
+#include <network.h>
+
+#include <lwip/netif.h>
+#include <cyg/io/eth/eth_drv.h>
+
+#define PORTNUM 2000
+
+// Threads' data structures
+typedef struct thread_s
+{
+    cyg_uint8 stack [CYGNUM_HAL_STACK_SIZE_TYPICAL];
+    cyg_thread data;
+    cyg_handle_t handle;
+} thread_s_t;
+
+typedef struct
+{
+    struct netconn * connection_p;
+    cyg_uint32 id;
+} server_argument_t;
+
+//#define INIT_PRIORITY     5
+#define INIT_PRIORITY     12
+#define LISTENER_PRIORITY INIT_PRIORITY+1
+#define SERVER_PRIORITY   LISTENER_PRIORITY-1
+
+// Init thread
+
+thread_s_t init_thread;
+
+void run_init(void)
+{
+    diag_printf("i: Initializing network stack...\n");
+    cyg_lwip_sequential_init();
+}
+
+// Server thread
+
+void server(cyg_addrword_t arg_p)
+{
+    struct netconn *newconn = NULL;
+    struct netbuf *income_buffer = NULL;
+    struct ip_addr from_addr;
+    struct ip_addr my_addr;
+    cyg_uint16 from_port = 0;
+    cyg_uint16 my_port = 0;
+    cyg_uint8 *addr_byte_p = NULL;
+    cyg_uint16 total_len;
+    cyg_uint8 * data_buf = NULL;
+    cyg_int32 retval;
+    cyg_uint32 id;
+    cyg_uint32 csum;
+
+    newconn = ((server_argument_t *)arg_p) -> connection_p;
+    id = ((server_argument_t *)arg_p) -> id;
+
+    retval = netconn_addr(newconn, &my_addr, &my_port);
+    if(0 != retval)
+    {
+        diag_printf("%u: netconn_addr() return %d. Exiting.\n", id, retval);
+        netconn_delete(newconn);
+        cyg_thread_exit();
+    }
+
+    retval = netconn_peer(newconn, &from_addr, &from_port);
+    if(0 != retval)
+    {
+        diag_printf("%u: netconn_peer() return %d. Exiting.\n", id, retval);
+        netconn_delete(newconn);
+        cyg_thread_exit();
+    }
+
+    addr_byte_p = (cyg_uint8 *) & from_addr.addr;
+    diag_printf("%u: Connected to remote peer %u.%u.%u.%u port %u, at my port %u\n", id,
+        *addr_byte_p, *(addr_byte_p+1), *(addr_byte_p+2), *(addr_byte_p+3),
+        from_port, my_port);
+    diag_printf("newconn %x\n", (unsigned)newconn);
+
+    csum =0;
+
+    while((income_buffer = netconn_recv(newconn)) != NULL)
+    {
+        total_len = netbuf_len(income_buffer);
+        if(0 != total_len)
+        {
+            data_buf = malloc(total_len);
+            if(NULL == data_buf)
+            {
+                diag_printf("%u: Can not allocate %u bytes. Exiting.\n", id, total_len);
+                netconn_delete(newconn);
+                cyg_thread_exit();
+            }
+
+            cyg_uint8 *local_data_p = data_buf;
+            do
+            {
+                cyg_uint8 *in_data_p;
+                cyg_uint16 len;
+                int i;
+
+                netbuf_data(income_buffer, (void **)&in_data_p, &len);
+                for(i=0; i<len; i++)
+                {
+                    csum += *local_data_p++ = *in_data_p++;
+                }
+            } while(netbuf_next(income_buffer) >= 0);
+            diag_printf("\nReceived %u bytes\n", total_len);
+
+            free(data_buf);
+        }
+        netbuf_delete(income_buffer);
+    }
+
+    diag_printf("Checksum %08x\n", csum);
+
+    retval = netconn_close(newconn);
+    if( 0 != retval)
+    {
+        diag_printf("%u: netconn_close(%x) return %d.\n", id, (unsigned)newconn, retval);
+    }
+
+    retval = netconn_delete(newconn);
+    if( 0 != retval)
+    {
+        diag_printf("%u: netconn_delete(%x) return %d. Exiting.\n", id, (unsigned)newconn, retval);
+        cyg_thread_exit();
+    }
+
+    diag_printf("%u: TCP connection closed.\n", id);
+
+}
+
+// Listener thread
+
+thread_s_t listener_thread;
+
+void listener(void)
+{
+    struct netconn *conn = NULL;
+    struct netconn *newconn = NULL;
+    struct netif *mynetif = NULL;
+    server_argument_t server_launch_args_s;
+    cyg_uint32 server_id = 0;
+    thread_s_t * new_thread_data = NULL;
+    char server_name[20];
+    cyg_int32 retval;
+
+    // This large malloc is just for testing
+//    new_thread_data = malloc(150 * sizeof(thread_s_t));
+
+    cyg_thread_delay(500);     // Sleep over the initialization of network
+
+    mynetif = netif_find("et0");
+    diag_printf("l: netif_find(et0) return %x\n", (unsigned int)mynetif);
+    retval = netif_is_up(mynetif);
+    diag_printf("l: netif_is_up() return %u\n", retval);
+
+    diag_printf("l: Creating TCP connection...\n");
+    conn = netconn_new(NETCONN_TCP);
+    if (NULL == conn)
+    {
+        diag_printf("l: netconn_new() return NULL. Exiting.\n");
+        cyg_thread_exit();
+    }
+    diag_printf("l: Binding to port %d...\n", PORTNUM);
+    retval = netconn_bind(conn, NULL, PORTNUM);
+    if (0 != retval)
+    {
+        diag_printf("l: netconn_bind() return %d. Exiting.\n", retval);
+        cyg_thread_exit();
+    }
+
+    diag_printf("l: Setting up for listening...\n");
+    retval = netconn_listen(conn);
+    if( 0!= retval)
+    {
+        diag_printf("l: netconn_listen() return %d. Exiting.\n", retval);
+        cyg_thread_exit();
+    }
+
+    do
+    {
+        diag_printf("l: Waiting for a new connection...\n");
+        newconn = netconn_accept(conn);
+        if (NULL == newconn)
+        {
+            diag_printf("l: netconn_accept() return NULL. Exiting.\n");
+            cyg_thread_exit();
+        }
+
+        // It's time to start a server thread
+
+        new_thread_data = malloc(sizeof(thread_s_t));
+        if(NULL == new_thread_data)
+        {
+            diag_printf("l: Can't allocate memory for another server.\n");
+            netconn_close(newconn);
+            netconn_delete(newconn);
+            continue;
+        }
+        /*
+         * Thread data is never freed after the thread exit.
+         * After a number of connections made, it will be impossible to
+         * allocate memory for additional servers.
+         */
+
+        server_launch_args_s.connection_p = newconn;
+        server_launch_args_s.id = ++server_id;
+        sprintf(server_name, "s%u", server_id);
+
+        diag_printf("l: Starting %s...\n", server_name);
+
+        cyg_thread_create(
+            SERVER_PRIORITY,
+            (cyg_thread_entry_t*) server,
+            (cyg_addrword_t)&server_launch_args_s,
+            server_name,
+            &(new_thread_data->stack[0]),
+            CYGNUM_HAL_STACK_SIZE_TYPICAL,
+            &(new_thread_data->handle),
+            &(new_thread_data->data)
+        );
+        cyg_thread_resume(new_thread_data->handle);
+
+    } while(true);
+}
+
+//---------------------------------------------------------------------------
+void show_threads(void)
+{
+    cyg_handle_t thread = 0;
+    cyg_uint16 id = 0;
+
+    while( cyg_thread_get_next( &thread, &id ) )
+    {
+        cyg_thread_info info;
+
+        if( !cyg_thread_get_info( thread, id, &info ) )
+            break;
+
+        diag_printf("ID: %04x name: %10s pri: %d\n",
+                info.id, info.name?info.name:"----", info.set_pri );
+        diag_printf("  stack_base %x    stack_size %d\n", info.stack_base, info.stack_size);
+    }
+}
+
+void cyg_user_start(void)
+{
+    diag_printf("%u: Starting initializer...\n", __LINE__);
+    cyg_thread_create(
+        INIT_PRIORITY,
+        (cyg_thread_entry_t*) run_init,
+        0,
+        "initializer",
+        &init_thread.stack[0],
+        CYGNUM_HAL_STACK_SIZE_TYPICAL,
+        &init_thread.handle,
+        &init_thread.data
+    );
+    cyg_thread_resume(init_thread.handle);
+
+    diag_printf("%u: Starting listener...\n", __LINE__);
+
+    cyg_thread_create(
+        LISTENER_PRIORITY,
+        (cyg_thread_entry_t*) listener,
+        0,
+        "listener",
+        &listener_thread.stack[0],
+        CYGNUM_HAL_STACK_SIZE_TYPICAL,
+        &listener_thread.handle,
+        &listener_thread.data
+    );
+    cyg_thread_resume(listener_thread.handle);
+
+    show_threads();
+
+    diag_printf("%u: Starting scheduler...\n", __LINE__);
+    cyg_scheduler_start();
+}
+
+//=============================================================================
+
diff --git a/packages/devs/eth/phy/current/ChangeLog b/packages/devs/eth/phy/current/ChangeLog
--- a/packages/devs/eth/phy/current/ChangeLog
+++ b/packages/devs/eth/phy/current/ChangeLog
@@ -1,3 +1,23 @@
+2011-07-22  Christophe Coutand  <ecos@hotmail.co.uk>  and sergeig
+
+	* cdl/phy_eth_drivers.cdl: Use CYGHWR_DEVS_ETH_PHY_DP8384X name
+	instead CYGHWR_DEVS_ETH_PHY_DP83847
+	* src/DP83847.c: Renamed stat() function, add new PHY DP83848C
+	Update due renaming CYGHWR_DEVS_ETH_PHY_DP83847 to
+	CYGHWR_DEVS_ETH_PHY_DP8384X. [ Bugzilla 1001235 ]
+
+2011-07-02  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/KSZ8041.c: More silicon revisions.  [Bugzilla 1001274]
+
+2010-06-10  Christophe Coutand <ccoutand@stmi.com>
+
+	* doc/eth_phy.sgml, include/eth_phy.h: Add Ethernet Gigabit Mode
+	* cdl/phy_eth_drivers.cdl: Add new PHY support
+	* src/IP101A.c, src/IP101A.h: Contributed by Edgar Grimberg
+	* src/VSC8244.c, src/VSC8244.h: Contributed by Christophe Coutand
+	* src/VSC8641.c, src/VSC8641.h: Contributed by Sachin Sushil Chaddha
+
 2008-12-30  John Dallaway  <john@dallaway.org.uk>
 
 	* cdl/phy_eth_drivers.cdl: Reference per-package documentation.
@@ -80,7 +100,7 @@ 2003-08-19  Gary Thomas  <gary@mlbassoc.
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2010 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/devs/eth/phy/current/cdl/phy_eth_drivers.cdl b/packages/devs/eth/phy/current/cdl/phy_eth_drivers.cdl
--- a/packages/devs/eth/phy/current/cdl/phy_eth_drivers.cdl
+++ b/packages/devs/eth/phy/current/cdl/phy_eth_drivers.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 2003 Free Software Foundation, Inc.                        
+## Copyright (C) 2003, 2010 Free Software Foundation, Inc.                        
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -78,13 +78,13 @@ cdl_package CYGPKG_DEVS_ETH_PHY {
            before giving up and declaring the link dead/missing."
     }
 
-    cdl_option CYGHWR_DEVS_ETH_PHY_DP83847 {
-        display       "NSDP83847"
+    cdl_option CYGHWR_DEVS_ETH_PHY_DP8384X {
+        display       "NSDP8384X"
         flavor        bool
         default_value 0
         compile       -library=libextras.a DP83847.c
         description "
-          Include support for National Semiconductor DP83847 DsPHYTER II"
+          Include support for National Semiconductor DP8384X DsPHYTER II"
     }
 
     cdl_option CYGHWR_DEVS_ETH_PHY_AM79C874 {
@@ -168,4 +168,31 @@ cdl_package CYGPKG_DEVS_ETH_PHY {
           Include support for the Micrel KSZ8041 PHY"
     }
 
+    cdl_option CYGHWR_DEVS_ETH_PHY_IP101A {
+        display       "IC+ IP101A"
+        flavor        bool
+        default_value 0
+        compile       -library=libextras.a IP101A.c
+        description "
+          Include support for IC+ IP101A"
+    }
+
+    cdl_option CYGHWR_DEVS_ETH_PHY_VSC8641 {
+        display       "Vitesse VSC8641"
+        flavor        bool
+        default_value 0
+        compile       -library=libextras.a VSC8641.c
+        description "
+          Include support for Vitesse VSC8641"
+    }
+
+    cdl_option CYGHWR_DEVS_ETH_PHY_VSC8244 {
+        display       "Vitesse VSC8244"
+        flavor        bool
+        default_value 0
+        compile       -library=libextras.a VSC8244.c
+        description "
+          Include support for Vitesse VSC8244"
+    }
+
 }
diff --git a/packages/devs/eth/phy/current/doc/eth_phy.sgml b/packages/devs/eth/phy/current/doc/eth_phy.sgml
--- a/packages/devs/eth/phy/current/doc/eth_phy.sgml
+++ b/packages/devs/eth/phy/current/doc/eth_phy.sgml
@@ -9,7 +9,7 @@
 <!-- =============================================================== -->
 <!-- ####ECOSDOCCOPYRIGHTBEGIN####                                       -->
 <!-- ===============================================================     -->
-<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. -->
+<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2010 Free Software Foundation, Inc. -->
 <!-- This material may be distributed only subject to the terms          -->
 <!-- and conditions set forth in the Open Publication License, v1.0      -->
 <!-- or later (the latest version is presently available at              -->
@@ -157,9 +157,10 @@ this information may be useful to the MA
 provide data, etc.
 The status bitmask contains these bits:
 <programlisting>
-#define ETH_PHY_STAT_LINK  0x0001   // Link up/down
-#define ETH_PHY_STAT_100MB 0x0002   // Connection is 100Mb/10Mb
-#define ETH_PHY_STAT_FDX   0x0004   // Connection is full/half duplex
+#define ETH_PHY_STAT_LINK   0x0001   // Link up/down
+#define ETH_PHY_STAT_100MB  0x0002   // Connection is 100Mb/10Mb
+#define ETH_PHY_STAT_FDX    0x0004   // Connection is full/half duplex
+#define ETH_PHY_STAT_1000MB 0x0008   // Connection is 1Gb
 </programlisting>
 Note: the usage here is that if the bit is set, then the condition
 exists.  For example, if the 
diff --git a/packages/devs/eth/phy/current/include/eth_phy.h b/packages/devs/eth/phy/current/include/eth_phy.h
--- a/packages/devs/eth/phy/current/include/eth_phy.h
+++ b/packages/devs/eth/phy/current/include/eth_phy.h
@@ -10,7 +10,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2003 Free Software Foundation, Inc.                        
+// Copyright (C) 2003, 2010 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -84,9 +84,10 @@ static eth_phy_access_t _l = {PHY_BIT_LE
 static eth_phy_access_t _l = {PHY_REG_LEVEL_ACCESS_TYPE, false, _init, _reset, \
                               {.reg_level_ops = {_put_reg, _get_reg}}}
 
-#define ETH_PHY_STAT_LINK  0x0001   // Link up/down
-#define ETH_PHY_STAT_100MB 0x0002   // Connection is 100Mb/10Mb
-#define ETH_PHY_STAT_FDX   0x0004   // Connection is full/half duplex
+#define ETH_PHY_STAT_LINK   0x0001   // Link up/down
+#define ETH_PHY_STAT_100MB  0x0002   // Connection is 100Mb/10Mb
+#define ETH_PHY_STAT_FDX    0x0004   // Connection is full/half duplex
+#define ETH_PHY_STAT_1000MB 0x0008   // Connection is 1Gb
 
 externC bool _eth_phy_init(eth_phy_access_t *f);
 externC void _eth_phy_reset(eth_phy_access_t *f);
diff --git a/packages/devs/eth/phy/current/src/DP83847.c b/packages/devs/eth/phy/current/src/DP83847.c
--- a/packages/devs/eth/phy/current/src/DP83847.c
+++ b/packages/devs/eth/phy/current/src/DP83847.c
@@ -40,10 +40,10 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):    gthomas
-// Contributors: 
+// Contributors: ccoutand
 // Date:         2003-08-01
 // Purpose:      
-// Description:  Support for ethernet NS DP83847 PHY
+// Description:  Support for ethernet NS DP8384X PHY
 //              
 //
 //####DESCRIPTIONEND####
@@ -63,7 +63,7 @@
 #include <cyg/io/eth_phy.h>
 #include <cyg/io/eth_phy_dev.h>
 
-static bool dp83847_stat(eth_phy_access_t *f, int *state)
+static bool dp8384x_stat(eth_phy_access_t *f, int *state)
 {
     unsigned short phy_state;
     int tries;
@@ -94,4 +94,5 @@ static bool dp83847_stat(eth_phy_access_
     return false;
 }
 
-_eth_phy_dev("National Semiconductor DP83847", 0x20005c30, dp83847_stat)
+_eth_phy_dev("National Semiconductor DP83847", 0x20005c30, dp8384x_stat)
+_eth_phy_dev("National Semiconductor DP83848C", 0x20005c90, dp8384x_stat)
diff --git a/packages/devs/eth/phy/current/src/IP101A.c b/packages/devs/eth/phy/current/src/IP101A.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/phy/current/src/IP101A.c
@@ -0,0 +1,117 @@
+//==========================================================================
+//
+//      phy/ip101a.c
+//
+//      Ethernet PHY driver
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System. 
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 
+// 2008, 2009 Free Software Foundation, Inc. 
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Edgar Grimberg
+// Contributors: 
+// Date:         2009-11-01
+// Purpose:      
+// Description:  hardware driver for Ethernet PHY IC+ IP101A
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/devs_eth_phy.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/hal_tables.h>
+
+#include <cyg/io/eth_phy.h>
+#include <cyg/io/eth_phy_dev.h>
+
+#include "IP101A.h"
+
+static bool ip101a_stat(eth_phy_access_t *f, int *state)
+{
+    unsigned short phy_state;
+    int tries;
+    int auto_completed = 1;
+
+    // Read negotiated state from the Quick Poll Detailed Status Register
+    if (_eth_phy_read(f, MII_STAT_REG, f->phy_addr, &phy_state))
+    {
+        if ((phy_state & IP101A_AUTO_COMPLETED) == 0)
+        {
+            auto_completed = 0;
+            eth_phy_printf("... waiting for auto-negotiation");
+            for (tries = 0;  tries < CYGINT_DEVS_ETH_PHY_AUTO_NEGOTIATION_TIME;  tries++)
+            {
+                if (_eth_phy_read(f, MII_STAT_REG, f->phy_addr, &phy_state))
+                {
+                    if ((phy_state & IP101A_AUTO_COMPLETED) != 0)
+                    {
+                        auto_completed = 1;
+                        break;
+                    }
+                }
+                CYGACC_CALL_IF_DELAY_US(1000000);   // 1 second
+                eth_phy_printf(".");
+            }
+            eth_phy_printf("\n");
+        }  
+ 
+        if(auto_completed)
+        {
+          _eth_phy_read(f, MII_PHY_STAT_REG, f->phy_addr, &phy_state);
+
+          if(phy_state & IP101A_LINK_STATUS2) 
+            *state |= ETH_PHY_STAT_LINK;
+          if(phy_state & IP101A_SPEED_100MB)
+            *state |= ETH_PHY_STAT_100MB;
+          if(phy_state & IP101A_DUPLEX_MODE)
+            *state |= ETH_PHY_STAT_FDX;
+          return true;
+        }
+
+    }
+    return false;
+}
+
+
+_eth_phy_dev("IC+ IP101A", 0x02430c54, ip101a_stat)
+
diff --git a/packages/devs/eth/phy/current/src/IP101A.h b/packages/devs/eth/phy/current/src/IP101A.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/phy/current/src/IP101A.h
@@ -0,0 +1,92 @@
+#ifndef CYGONCE_PHY_IP101A_HEADER_
+#define CYGONCE_PHY_IP101A_HEADER_
+//==========================================================================
+//
+//      phy/ip101a.h
+//
+//      Ethernet PHY driver
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System. 
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 
+// 2008, 2009 Free Software Foundation, Inc. 
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Edgar Grimberg
+// Contributors: 
+// Date:         2009-11-01
+// Purpose:      
+// Description:  Hardware driver for Ethernet PHY IC+ IP101A
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#define MII_CTRL_REG                0x00
+#define MII_STAT_REG                0x01
+#define MII_PHY_ID1_REG             0x02
+#define MII_PHY_ID2_REG             0x03
+#define MII_AUTO_NEG_ADV_REG        0x04
+#define MII_AUTO_NEG_LPA_REG        0x05
+#define MII_AUTO_NEG_EXP_REG        0x06
+#define MII_PHY_CTRL_REG            0x10
+#define MII_PHY_IRQ_REG             0x11
+#define MII_PHY_STAT_REG            0x12
+#define MII_PHY_CTRL2_REG           0x1E
+
+#define MII_PHY_IRQ_INTR            0x8000
+#define MII_PHY_IRQ_ALL_MASK        0x0800
+#define MII_PHY_IRQ_SPEED_MASK      0x0400
+#define MII_PHY_IRQ_DUPLEX_MASK     0x0200
+#define MII_PHY_IRQ_LINK_MASK       0x0100
+#define MII_PHY_IRQ_ARBITER_MASK    0x0080
+#define MII_PHY_IRQ_ARBITER_CHANGE  0x0040
+#define MII_PHY_IRQ_SPEED_CHANGE    0x0004
+#define MII_PHY_IRQ_DUPLEX_CHANGE   0x0002
+#define MII_PHY_IRQ_LINK_CHANGE     0x0001
+
+#define IP101A_CTRL_DUPLEX          0x0100
+#define IP101A_CTRL_100MB           0x2000
+#define IP101A_CTRL_AUTO_NEG        0x1000
+#define IP101A_CTRL_AUTO_NEG_RST    0x0200
+
+#define IP101A_LINK_STATUS          0x0004
+#define IP101A_AUTO_COMPLETED       0x20
+
+#define IP101A_DUPLEX_MODE          0x2000
+#define IP101A_SPEED_100MB          0x4000
+#define IP101A_LINK_STATUS2         0x0400
+
+#endif // CYGONCE_PHY_IP101A_HEADER_
+
diff --git a/packages/devs/eth/phy/current/src/KSZ8041.c b/packages/devs/eth/phy/current/src/KSZ8041.c
--- a/packages/devs/eth/phy/current/src/KSZ8041.c
+++ b/packages/devs/eth/phy/current/src/KSZ8041.c
@@ -185,3 +185,4 @@ ksz8041_stat (eth_phy_access_t * f, int 
 }
 
 _eth_phy_dev ("Micrel KSZ8041", 0x00221512, ksz8041_stat)
+_eth_phy_dev ("Micrel KSZ8041", 0x00221513, ksz8041_stat)
diff --git a/packages/devs/eth/phy/current/src/VSC8244.c b/packages/devs/eth/phy/current/src/VSC8244.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/phy/current/src/VSC8244.c
@@ -0,0 +1,122 @@
+//==========================================================================
+//
+//      phy/VSC8244.c
+//
+//      Ethernet PHY driver
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System. 
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 
+// 2008, 2009 Free Software Foundation, Inc. 
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors: 
+// Date:         2009-11-01
+// Purpose:      
+// Description:  Hardware driver for Ethernet PHY Vitesse VSC8244
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/devs_eth_phy.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/hal_tables.h>
+
+#include <cyg/io/eth_phy.h>
+#include <cyg/io/eth_phy_dev.h>
+
+#include "VSC8244.h"
+
+static bool VSC8244_stat(eth_phy_access_t *f, int *state)
+{
+    unsigned short phy_state;
+    int tries;
+    int auto_completed = 1;
+    int link_up = 0;
+
+    // Read negotiated state from the Quick Poll Detailed Status Register
+    if (_eth_phy_read(f, VSC8244_MII_STAT_REG, f->phy_addr, &phy_state))
+    {
+
+        if ((phy_state & VSC8244_AUTO_COMPLETED) == 0)
+        { 
+            auto_completed = 0;
+            eth_phy_printf("... waiting for auto-negotiation");
+            for (tries = 0;  tries < CYGINT_DEVS_ETH_PHY_AUTO_NEGOTIATION_TIME;  tries++)
+            {
+                if (_eth_phy_read(f, VSC8244_MII_STAT_REG, f->phy_addr, &phy_state))
+                {
+                    if ((phy_state & VSC8244_AUTO_COMPLETED) != 0)
+                    {                        
+                        auto_completed = 1;
+                        break;
+                    }
+                }
+                CYGACC_CALL_IF_DELAY_US(1000000);   // 1 second
+                eth_phy_printf(".");
+            }
+            eth_phy_printf("\n");
+        }  
+
+        if(phy_state & VSC8244_MII_PHY_STAT_LINK_UP)
+          link_up = 1;
+      
+        if(auto_completed)
+        {
+          _eth_phy_read(f, VSC8244_MII_PHY_STAT_REG, f->phy_addr, &phy_state);
+
+          if(link_up) 
+            *state |= ETH_PHY_STAT_LINK;
+          if(phy_state & VSC8244_MII_PHY_STAT_1000MB )
+            *state |= ETH_PHY_STAT_1000MB;
+          if(phy_state & VSC8244_MII_PHY_STAT_100MB)
+            *state |= ETH_PHY_STAT_100MB;
+          if(phy_state & VSC8244_MII_PHY_STAT_DUPLEX_FULL)
+            *state |= ETH_PHY_STAT_FDX;
+          return true;
+        }
+
+    }
+    return false;
+}
+
+_eth_phy_dev("Vitesse VSC8244", 0x000FC6C2, VSC8244_stat)
diff --git a/packages/devs/eth/phy/current/src/VSC8244.h b/packages/devs/eth/phy/current/src/VSC8244.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/phy/current/src/VSC8244.h
@@ -0,0 +1,67 @@
+#ifndef CYGONCE_PHY_VSC8244_HEADER_
+#define CYGONCE_PHY_VSC8244_HEADER_
+//==========================================================================
+//
+//      phy/VSC8244.h
+//
+//      Ethernet PHY driver
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System. 
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 
+// 2008, 2009 Free Software Foundation, Inc. 
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors: 
+// Date:         2009-11-01
+// Purpose:      
+// Description:  Hardware driver for Ethernet PHY Vitesse VSC8244
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#define VSC8244_MII_PHY_STAT_DUPLEX_FULL  0x20
+#define VSC8244_MII_PHY_STAT_1000MB       0x10
+#define VSC8244_MII_PHY_STAT_100MB        0x08
+
+#define VSC8244_MII_PHY_STAT_LINK_UP      0x04
+
+#define VSC8244_MII_STAT_REG              0x01
+#define VSC8244_MII_PHY_STAT_REG          0x1C
+
+#define VSC8244_AUTO_COMPLETED            0x20
+
+#endif  // CYGONCE_PHY_VSC8244_HEADER_
diff --git a/packages/devs/eth/phy/current/src/VSC8641.c b/packages/devs/eth/phy/current/src/VSC8641.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/phy/current/src/VSC8641.c
@@ -0,0 +1,123 @@
+//==========================================================================
+//
+//      phy/VSC8641.c
+//
+//      Ethernet PHY driver
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System. 
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 
+// 2008, 2009 Free Software Foundation, Inc. 
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Sachin Sushil Chaddha
+// Contributors: 
+// Date:         2009-11-01
+// Purpose:      
+// Description:  Hardware driver for Ethernet PHY Vitesse VSC8641
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/devs_eth_phy.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/hal_tables.h>
+
+#include <cyg/io/eth_phy.h>
+#include <cyg/io/eth_phy_dev.h>
+
+#include "VSC8641.h"
+
+static bool VSC8641_stat(eth_phy_access_t *f, int *state)
+{
+    unsigned short phy_state;
+    int tries;
+    int auto_completed = 1;
+    int link_up = 0;
+
+    // Read negotiated state from the Quick Poll Detailed Status Register
+    if (_eth_phy_read(f, VSC8641_MII_STAT_REG, f->phy_addr, &phy_state))
+    {
+
+        if ((phy_state & VSC8641_AUTO_COMPLETED) == 0)
+        { 
+            auto_completed = 0;
+            eth_phy_printf("... waiting for auto-negotiation");
+            for (tries = 0;  tries < CYGINT_DEVS_ETH_PHY_AUTO_NEGOTIATION_TIME;  tries++)
+            {
+                if (_eth_phy_read(f, VSC8641_MII_STAT_REG, f->phy_addr, &phy_state))
+                {
+                    if ((phy_state & VSC8641_AUTO_COMPLETED) != 0)
+                    {                        
+                        auto_completed = 1;
+                        break;
+                    }
+                }
+                CYGACC_CALL_IF_DELAY_US(1000000);   // 1 second
+                eth_phy_printf(".");
+            }
+            eth_phy_printf("\n");
+        }  
+
+        if(phy_state & VSC8641_MII_PHY_STAT_LINK_UP)
+          link_up = 1;
+ 
+        if(auto_completed)
+        {
+          _eth_phy_read(f, VSC8641_MII_PHY_STAT_REG, f->phy_addr, &phy_state);
+
+          if(link_up) 
+            *state |= ETH_PHY_STAT_LINK;
+          if(phy_state & VSC8641_MII_PHY_STAT_1000MB )
+            *state |= ETH_PHY_STAT_1000MB;
+          if(phy_state & VSC8641_MII_PHY_STAT_100MB)
+            *state |= ETH_PHY_STAT_100MB;
+          if(phy_state & VSC8641_MII_PHY_STAT_DUPLEX_FULL)
+            *state |= ETH_PHY_STAT_FDX;
+          return true;
+        }
+
+    }
+    return false;
+}
+
+
+_eth_phy_dev("Vitesse VSC8641", 0x00070431, VSC8641_stat)
diff --git a/packages/devs/eth/phy/current/src/VSC8641.h b/packages/devs/eth/phy/current/src/VSC8641.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/eth/phy/current/src/VSC8641.h
@@ -0,0 +1,86 @@
+#ifndef CYGONCE_PHY_VSC8641_HEADER_
+#define CYGONCE_PHY_VSC8641_HEADER_
+//==========================================================================
+//
+//      phy/VSC8641.h
+//
+//      Ethernet PHY driver
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System. 
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 
+// 2008, 2009 Free Software Foundation, Inc. 
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors: 
+// Date:         2009-11-01
+// Purpose:      
+// Description:  Hardware driver for Ethernet PHY Vitesse VSC8641
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#define VSC8641_MII_MDE_CTRL_REG          0x00
+#define VSC8641_MII_STAT_REG              0x01
+#define VSC8641_MII_AUTO_NEG_ADV_REG      0x04
+#define VSC8641_MII_AUTO_NEG_NXT_REG      0x07
+#define VSC8641_MII_PHY_IRQ_MSK_REG       0x19
+
+#define VSC8641_MII_PHY_STAT_REG          0x1C
+#define VSC8641_MII_INT_STAT_REG          0x1A
+
+#define VSC8641_MII_PHY_EPA               0x1F
+#define VSC8641_MII_PHY_RGMII_SKEW        0x1C
+
+#define VSC8641_AUTO_COMPLETED            0x20
+
+#define VSC8641_CTRL_AUTO_NEG             0x1000
+#define VSC8641_CTRL_AUTO_NEG_RST         0x0200
+#define VSC8641_CTRL_1000MB               0x0040
+#define VSC8641_CTRL_100MB                0x2000
+#define VSC8641_CTRL_FULL_DUPLEX          0x0100
+
+#define VSC8641_IRQ_SPEED_CHANGE          0x4000
+#define VSC8641_IRQ_FDX_STATE_CHANGE      0x1000
+#define VSC8641_IRQ_LINK_CHANGE           0x2000
+
+#define VSC8641_MII_PHY_STAT_DUPLEX_FULL  0x20
+#define VSC8641_MII_PHY_STAT_1000MB       0x10
+#define VSC8641_MII_PHY_STAT_100MB        0x08
+
+#define VSC8641_MII_PHY_STAT_LINK_UP      0x04
+
+#endif // CYGONCE_PHY_VSC8641_HEADER_
diff --git a/packages/devs/eth/powerpc/moab/current/ChangeLog b/packages/devs/eth/powerpc/moab/current/ChangeLog
--- a/packages/devs/eth/powerpc/moab/current/ChangeLog
+++ b/packages/devs/eth/powerpc/moab/current/ChangeLog
@@ -1,3 +1,9 @@
+2011-07-22  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/moab_eth_drivers.cdl:
+	Update due renaming CYGHWR_DEVS_ETH_PHY_DP83847 to
+	CYGHWR_DEVS_ETH_PHY_DP8384X. [ Bugzilla 1001235 ]
+
 2005-07-18  David Vrabel  <dvrabel@arcom.com>
 
 	* include/moab_eth_dp83816.inl: Remove unneeded _h2le and _le2h
diff --git a/packages/devs/eth/powerpc/moab/current/cdl/moab_eth_drivers.cdl b/packages/devs/eth/powerpc/moab/current/cdl/moab_eth_drivers.cdl
--- a/packages/devs/eth/powerpc/moab/current/cdl/moab_eth_drivers.cdl
+++ b/packages/devs/eth/powerpc/moab/current/cdl/moab_eth_drivers.cdl
@@ -58,7 +58,7 @@ cdl_package CYGPKG_DEVS_ETH_POWERPC_MOAB
     active_if	  CYGPKG_HAL_POWERPC_PPC40x
 
     requires      CYGPKG_DEVS_ETH_POWERPC_PPC405
-    requires      CYGHWR_DEVS_ETH_PHY_DP83847
+    requires      CYGHWR_DEVS_ETH_PHY_DP8384X
     requires      CYGPKG_HAL_POWERPC_MOAB
 
     # FIXME: This really belongs in the NS DP83816 package
diff --git a/packages/devs/eth/via/rhine/current/ChangeLog b/packages/devs/eth/via/rhine/current/ChangeLog
--- a/packages/devs/eth/via/rhine/current/ChangeLog
+++ b/packages/devs/eth/via/rhine/current/ChangeLog
@@ -1,3 +1,10 @@
+2011-08-28  Stephen Polkowski  <stephen@centtech.com>
+            Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* src/via_rhine.h: Fix some compiler warning.
+	* src/if_rhine.c (via_rhine_init): Manage ESA with HAL_PCI_IO* macros.
+	[ Bugzilla 1001269 ]
+
 2004-08-12  Jani Monoses <jani@iv.ro>
 
 	* src/if_rhine.c: Fix builing with lwip.
diff --git a/packages/devs/eth/via/rhine/current/src/if_rhine.c b/packages/devs/eth/via/rhine/current/src/if_rhine.c
--- a/packages/devs/eth/via/rhine/current/src/if_rhine.c
+++ b/packages/devs/eth/via/rhine/current/src/if_rhine.c
@@ -538,14 +538,12 @@ via_rhine_init(struct cyg_netdevtab_entr
     // Prepare ESA
     if (cpd->hardwired_esa) {
         // Force the NIC to use the specified ESA
-        p = cpd->base + RHINE_PAR0;
         for (i = 0; i < 6; i++)
-            *p++ = cpd->esa[i];
+            HAL_PCI_IO_WRITE_UINT8(cpd->base + RHINE_PAR0 + i, cpd->esa[i]);
     } else {
         // Use the address from the serial EEPROM
-        p = cpd->base + RHINE_PAR0;
         for (i = 0; i < 6; i++)
-            cpd->esa[i] = *p++;
+            HAL_PCI_IO_READ_UINT8(cpd->base + RHINE_PAR0 + i, cpd->esa[i]);
     }
 #if DEBUG & 8
     diag_printf("RHINE - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n",
diff --git a/packages/devs/eth/via/rhine/current/src/via_rhine.h b/packages/devs/eth/via/rhine/current/src/via_rhine.h
--- a/packages/devs/eth/via/rhine/current/src/via_rhine.h
+++ b/packages/devs/eth/via/rhine/current/src/via_rhine.h
@@ -464,5 +464,5 @@ typedef struct rhine_priv_data {
 } rhine_priv_data;
 
 // ------------------------------------------------------------------------
-#endif CYGONCE_DEVS_ETH_VIA_RHINE_H
+#endif // CYGONCE_DEVS_ETH_VIA_RHINE_H
 // EOF via_rhine.h
diff --git a/packages/devs/flash/amd/am29xxxxx/current/ChangeLog b/packages/devs/flash/amd/am29xxxxx/current/ChangeLog
--- a/packages/devs/flash/amd/am29xxxxx/current/ChangeLog
+++ b/packages/devs/flash/amd/am29xxxxx/current/ChangeLog
@@ -1,3 +1,14 @@
+2010-07-14  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* include/flash_am29xxxxx_parts.inl [CYGHWR_DEVS_FLASH_AMD_AM29LV640M]:
+	* cdl/flash_amd_am29xxxxx.cdl: Add AM29LV640M part
+
+	* include/flash_am29xxxxx_parts.inl [CYGHWR_DEVS_FLASH_AMD_S29GL512P]:
+	* cdl/flash_amd_am29xxxxx.cdl: Add Spansion S29GL512P part
+
+	* include/flash_am29xxxxx_parts.inl [CYGHWR_DEVS_FLASH_AMD_S29GL01GP]:
+	* cdl/flash_amd_am29xxxxx.cdl: Add Spansion S29GL01GP part
+
 2009-02-17  Lars Povlsen  <lpovlsen@vitesse.com>
 
 	* include/flash_am29xxxxx_parts.inl:
diff --git a/packages/devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl b/packages/devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl
--- a/packages/devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl
+++ b/packages/devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl
@@ -237,6 +237,16 @@ cdl_package CYGPKG_DEVS_FLASH_AMD_AM29XX
             part in the family."
     }
 
+    cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV640M {
+        display       "AMD AM29LV640M flash memory support"
+        default_value 0
+        implements    CYGINT_DEVS_FLASH_AMD_VARIANTS
+        description   "
+            When this option is enabled, the AMD flash driver will be
+            able to recognize and handle the AM29LV640M
+            part in the family."
+    }
+
     cdl_option CYGHWR_DEVS_FLASH_AMD_AM29F800 {
         display       "AMD AM29F800 flash memory support"
         default_value 0
@@ -396,4 +406,24 @@ cdl_package CYGPKG_DEVS_FLASH_AMD_AM29XX
             part in the family."
     }
 
+   cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL512P {
+        display       "AMD/SPANSION S29GL512P flash memory support"
+        default_value 0
+        implements    CYGINT_DEVS_FLASH_AMD_VARIANTS
+        description   "
+            When this option is enabled, the AMD/SPANSION flash driver will be
+            able to recognize and handle the S29GL512P
+            part in the family."
+    }
+
+   cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL01GP {
+        display       "AMD/SPANSION S29GL01GP flash memory support"
+        default_value 0
+        implements    CYGINT_DEVS_FLASH_AMD_VARIANTS
+        description   "
+            When this option is enabled, the AMD/SPANSION flash driver will be
+            able to recognize and handle the S29GL01GP
+            part in the family."
+    }
+
 }
diff --git a/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl b/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl
--- a/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl
+++ b/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl
@@ -1245,6 +1245,18 @@
         bufsiz     : 1
     },
 #endif
+#ifdef CYGHWR_DEVS_FLASH_AMD_AM29LV640M
+    {   // MBM29LV640xx
+        device_id  : FLASHWORD(0x227e),
+        block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
+        block_count: 128,
+        device_size: 0x800000 * CYGNUM_FLASH_INTERLEAVE,
+        base_mask  : ~(0x800000 * CYGNUM_FLASH_INTERLEAVE - 1),
+        bootblock  : false,
+        banked     : false,
+        bufsiz     : 1
+    },
+#endif
 #ifdef CYGHWR_DEVS_FLASH_AMD_TC58FVB800
     {   // Toshiba TC58FVB800 (compatible with AM29LV800-B except for IDs.)
         device_id  : FLASHWORD(0xCE),
@@ -1499,6 +1511,36 @@
         bufsiz     : 16,
     },
 #endif
+#ifdef CYGHWR_DEVS_FLASH_AMD_S29GL512P
+    {   // AMD/SPANSION S29GL512P
+        long_device_id: true,
+        device_id  : FLASHWORD(0x227e),
+        device_id2 : FLASHWORD(0x2223),
+        device_id3 : FLASHWORD(0x2201),
+        block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
+        block_count: 512,
+        device_size: 0x4000000 * CYGNUM_FLASH_INTERLEAVE,
+        base_mask  : ~(0x4000000 * CYGNUM_FLASH_INTERLEAVE - 1),
+        bootblock  : false,
+        banked     : false,
+        bufsiz     : 32,
+    },
+#endif
+#ifdef CYGHWR_DEVS_FLASH_AMD_S29GL01GP
+    {   // AMD/SPANSION S29GL01GP
+        long_device_id: true,
+        device_id  : FLASHWORD(0x227e),
+        device_id2 : FLASHWORD(0x2228),
+        device_id3 : FLASHWORD(0x2201),
+        block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
+        block_count: 1024,
+        device_size: 0x8000000 * CYGNUM_FLASH_INTERLEAVE,
+        base_mask  : ~(0x8000000 * CYGNUM_FLASH_INTERLEAVE - 1),
+        bootblock  : false,
+        banked     : false,
+        bufsiz     : 32,
+    },
+#endif
 
 #endif // 16 bit devices
 
diff --git a/packages/devs/flash/arm/olpcx2294/current/ChangeLog b/packages/devs/flash/arm/olpcx2294/current/ChangeLog
--- a/packages/devs/flash/arm/olpcx2294/current/ChangeLog
+++ b/packages/devs/flash/arm/olpcx2294/current/ChangeLog
@@ -1,3 +1,7 @@
+2010-11-24  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/flash_olpcx2294.cdl: Add support for Olimex LPC-L2294-8M board.
+
 2008-08-31  Sergei Gavrikov <sergei.gavrikov@gmail.com>
 
 	* Flash driver for LPC-E2294, LPC-H2294, LPC-L2294-1M boards
diff --git a/packages/devs/flash/arm/olpcx2294/current/cdl/flash_olpcx2294.cdl b/packages/devs/flash/arm/olpcx2294/current/cdl/flash_olpcx2294.cdl
--- a/packages/devs/flash/arm/olpcx2294/current/cdl/flash_olpcx2294.cdl
+++ b/packages/devs/flash/arm/olpcx2294/current/cdl/flash_olpcx2294.cdl
@@ -67,16 +67,14 @@ cdl_package CYGPKG_DEVS_FLASH_ARM_OLPCX2
     cdl_option CYGSEM_DEVS_FLASH_INTEL_28F320C3_PARTS {
         display       "Intel 28F320C3 parts used"
         flavor        bool
-	calculated    1
-        active_if     (CYGPKG_HAL_ARM_LPC2XXX_OLPCE2294 || \
-		       CYGPKG_HAL_ARM_LPC2XXX_OLPCH2294)
+        calculated    { CYGPKG_HAL_ARM_LPC2XXX_OLPCE2294 || CYGPKG_HAL_ARM_LPC2XXX_OLPCH2294 || (CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_VARIANT == "OLPCL2294_8M") }
         requires      CYGHWR_DEVS_FLASH_INTEL_28F320C3
     }
 
     cdl_option CYGSEM_DEVS_FLASH_INTEL_28F160C3_PARTS {
         display       "Intel 28F160C3 parts used"
         flavor        bool
-	calculated    1
+        calculated    { (CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_VARIANT == "OLPCL2294_1M") }
         active_if     CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294
         requires      CYGHWR_DEVS_FLASH_INTEL_28F160C3B
     }
diff --git a/packages/devs/flash/arm/olpcx2294v2/current/ChangeLog b/packages/devs/flash/arm/olpcx2294v2/current/ChangeLog
--- a/packages/devs/flash/arm/olpcx2294v2/current/ChangeLog
+++ b/packages/devs/flash/arm/olpcx2294v2/current/ChangeLog
@@ -1,3 +1,7 @@
+2010-11-03  JF Argentino  <jf.argentino@osean.fr>
+
+	* src/arm_olpcx2294_flash.c: Add support for LPC-L2294-8M board.
+
 2008-11-22  Sergei Gavrikov <sergei.gavrikov@gmail.com>
 
 	* Flash driver v2 for LPC-E2294, LPC-H2294, LPC-L2294-1M boards
diff --git a/packages/devs/flash/arm/olpcx2294v2/current/src/arm_olpcx2294_flash.c b/packages/devs/flash/arm/olpcx2294v2/current/src/arm_olpcx2294_flash.c
--- a/packages/devs/flash/arm/olpcx2294v2/current/src/arm_olpcx2294_flash.c
+++ b/packages/devs/flash/arm/olpcx2294v2/current/src/arm_olpcx2294_flash.c
@@ -64,7 +64,8 @@
 
 // Olimex LPC-E2294 development board and Olimex LPC-H2294 header board both
 // have 28F320C3-B flash memory part, Olimex LPC-L2294-1M development board has
-// 28F160C3-B flash memory part. All boards have 16-bit access to it's flash
+// 28F160C3-B flash memory part and Olimex LPC-L2294-8M development board has
+// 28F320C3-B flash memory part. All boards have 16-bit access to it's flash
 // devices.
 static const CYG_FLASH_FUNS(hal_olpcx2294_flash_strata_funs,
     &cyg_strata_init_check_devid_16,
@@ -77,14 +78,14 @@ static const CYG_FLASH_FUNS(hal_olpcx229
 
 static const cyg_strata_dev hal_olpcx2294_flash_priv = {
     .manufacturer_code = CYG_FLASH_STRATA_MANUFACTURER_INTEL,
-#ifdef CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294 
+#if defined(CYGHWR_OLIMEX_BOARD_OLPCL2294_1M)
     .device_code = 0x88c3, /* 16-Mbit x 16-B, 28F160C3-B */
 #else
     .device_code = 0x88c5, /* 32-Mbit x 16-B, 28F320C3-B */
 #endif
     .bufsize    = 1,
     .block_info = {
-#ifdef CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294 
+#if defined(CYGHWR_OLIMEX_BOARD_OLPCL2294_1M)
         { 0x00002000,  8 },/* boot bottom 8 x 8K blocks */
         { 0x00010000, 31 } /* 31 x 64K blocks */
 #else
@@ -94,19 +95,27 @@ static const cyg_strata_dev hal_olpcx229
     }
 };
 
+#if defined(CYGHWR_OLIMEX_BOARD_OLPCL2294_1M)
 CYG_FLASH_DRIVER(hal_olpcx2294_flash,
                  &hal_olpcx2294_flash_strata_funs,
                  0,
                  0x80000000,
-#ifdef CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294 
                  0x801fffff,
-#else
-                 0x803fffff,
-#endif
                  2,
                  hal_olpcx2294_flash_priv.block_info,
                  &hal_olpcx2294_flash_priv
 );
+#else
+CYG_FLASH_DRIVER(hal_olpcx2294_flash,
+                 &hal_olpcx2294_flash_strata_funs,
+                 0,
+                 0x80000000,
+                 0x803fffff,
+                 2,
+                 hal_olpcx2294_flash_priv.block_info,
+                 &hal_olpcx2294_flash_priv
+);
+#endif
 
 #endif//CYGPKG_DEVS_FLASH_STRATA_V2
 // ------------------------------------------------------------------------
diff --git a/packages/devs/flash/cortexm/a2fxxx/a2f200_eval/current/ChangeLog b/packages/devs/flash/cortexm/a2fxxx/a2f200_eval/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/cortexm/a2fxxx/a2f200_eval/current/ChangeLog
@@ -0,0 +1,31 @@
+
+2011-04-13  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* cdl/flash_a2f200_eval.cdl: 
+	* src/flash_a2f200_eval.c: 
+	New package - Flash support for Actel Smartfusion evaluation board.
+	[Bugzilla 1001291]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/flash/cortexm/a2fxxx/a2f200_eval/current/cdl/flash_a2f200_eval.cdl b/packages/devs/flash/cortexm/a2fxxx/a2f200_eval/current/cdl/flash_a2f200_eval.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/cortexm/a2fxxx/a2f200_eval/current/cdl/flash_a2f200_eval.cdl
@@ -0,0 +1,62 @@
+# ====================================================================
+#
+#      flash_a2f200_eval.cdl
+#
+#      Flash programming for Atmel device on Actel SmartFusion Board
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      ccoutand
+# Date:           2011-05-05
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_FLASH_CORTEXM_A2F200_EVAL {
+    display       "Actel SmartFusion board FLASH memory support"
+    description   "FLASH memory device support for Actel SmartFusion board"
+
+    parent        CYGPKG_IO_FLASH
+    active_if     CYGPKG_IO_FLASH
+    requires      CYGPKG_HAL_CORTEXM_A2FXXX
+    requires      CYGHWR_DEVS_SPI_CORTEXM_A2FXXX_BUS1
+    implements    CYGHWR_DEVS_FLASH_SPI_AT25DFXXX_DEVICE
+
+    compile       -library=libextras.a  flash_a2f200_eval.c
+}
+
+# EOF flash_a2f200_eval.cdl
diff --git a/packages/devs/flash/cortexm/a2fxxx/a2f200_eval/current/src/flash_a2f200_eval.c b/packages/devs/flash/cortexm/a2fxxx/a2f200_eval/current/src/flash_a2f200_eval.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/cortexm/a2fxxx/a2f200_eval/current/src/flash_a2f200_eval.c
@@ -0,0 +1,78 @@
+//==========================================================================
+//
+//      flash_a2f200_eval.c
+//
+//      Flash programming for Atmel device on Actel SmartFusion Board
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Date:         2011-05-05
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+// ------------------------------------------------------------------------
+// There is an AT25DF161 DataFlash on the SPI bus
+
+#include <pkgconf/system.h>
+#include <pkgconf/devs_flash_cortexm_a2f200_eval.h>
+
+#if defined(CYGPKG_IO_SPI) && defined(CYGPKG_DEVS_FLASH_SPI_AT25DFXXX)
+
+#include <cyg/io/spi.h>
+#include <cyg/io/at25dfxxx.h>
+#include <cyg/io/spi_a2fxxx.h>
+
+// Declare Device on SPI bus 1, Use GPIO 19 for chip select, Motorola protocol (mode 0)
+CYG_DEVS_SPI_CORTEXM_A2FXXX_DEVICE (
+    at25dfxxx_spi_device, 1, 19, true, A2FXXX_SPI_MOTOROLA, 0, 0, 5000000, 1, 1, 1
+);
+
+//-----------------------------------------------------------------------------
+// Instantiate the AT25DFxxx device driver.
+
+CYG_DEVS_FLASH_SPI_AT25DFXXX_DRIVER (
+    at25dfxxx_flash_device, CYGNUM_DEVS_FLASH_SPI_AT25XXX_DEV0_MAP_ADDR, &at25dfxxx_spi_device
+);
+
+#endif
+
+// ------------------------------------------------------------------------
+// EOF flash_a2f200_eval.c
diff --git a/packages/devs/flash/cortexm/stm32/current/ChangeLog b/packages/devs/flash/cortexm/stm32/current/ChangeLog
--- a/packages/devs/flash/cortexm/stm32/current/ChangeLog
+++ b/packages/devs/flash/cortexm/stm32/current/ChangeLog
@@ -1,3 +1,33 @@
+2012-03-15  James Smith  <jsmith@ecoscentric.com>
+
+	* src/stm32_flash.c: Add support for F4 family devices, and
+	explicit flash size support for specific F4xxx[EG] devices.
+
+	* include/stm32_flash.h:
+	* cdl/flash_stm32.cdl (CYGNUM_DEVS_FLASH_STM32_PARALLELISM):
+	Support for F4 devices.
+
+2012-02-29  James Smith  <jsmith@ecoscentric.com>
+
+	* src/stm32_flash.c (stm32_flash_hw_program): Compilation fixes to
+	use renamed WAIT_FOR_FLASH_NOT_BUSY macro and to add missing
+	semi-colon
+
+2011-12-15  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/flash_stm32.cdl (CYGNUM_DEVS_FLASH_STM32_PARALLELISM): New
+	option. Configures program/erase width on F2 processors.
+	* include/stm32_flash.h: Make private device driver data const - it
+	doesn't change so shouldn't be in RAM. Support multiple flash regions
+	for F2.
+	* src/stm32_flash.c: Substantial changes to support F2 processors.
+	Also improve error checking, timeout detection and general robustness.
+
+2009-07-03  Nick Garnett  <nickg@ecoscentric.com>
+
+	* src/stm32_flash.c (stm32_flash_init): Add tests for connectivity
+	line devices.
+
 2009-04-06  Simon Kallweit  <simon.kallweit@intefo.ch>
 
 	* src/stm32_flash.c:
@@ -27,7 +57,7 @@ 2008-10-07  Nick Garnett  <nickg@ecoscen
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2009, 2011, 2012 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/devs/flash/cortexm/stm32/current/cdl/flash_stm32.cdl b/packages/devs/flash/cortexm/stm32/current/cdl/flash_stm32.cdl
--- a/packages/devs/flash/cortexm/stm32/current/cdl/flash_stm32.cdl
+++ b/packages/devs/flash/cortexm/stm32/current/cdl/flash_stm32.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 2008 Free Software Foundation, Inc.                        
+## Copyright (C) 2008, 2011 Free Software Foundation, Inc.
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -83,6 +83,20 @@ cdl_package CYGPKG_DEVS_FLASH_STM32 {
             times but reduce overhead."
     }
     
+    cdl_option CYGNUM_DEVS_FLASH_STM32_PARALLELISM {
+        display         "Program/erase parallelism"
+        flavor          data
+        legal_values    { 8 16 32 64 }
+        active_if       { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4")) }
+        default_value   32
+        description     "
+            The Flash interface of the STM32 F2 and F4 families can program or erase
+            multiple bits in one step. The maximum possible parallelism depends
+            on the supply voltage. The default value of this option (32)
+            corresponds to supply voltage of 2.7 - 3.6V, but another value
+            may be chosen if a different voltage is used."
+    }
+    
     cdl_component CYGPKG_DEVS_FLASH_STM32_OPTIONS {
         display "STM32 driver build options"
         flavor  none
diff --git a/packages/devs/flash/cortexm/stm32/current/include/stm32_flash.h b/packages/devs/flash/cortexm/stm32/current/include/stm32_flash.h
--- a/packages/devs/flash/cortexm/stm32/current/include/stm32_flash.h
+++ b/packages/devs/flash/cortexm/stm32/current/include/stm32_flash.h
@@ -10,7 +10,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2011, 2012 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -48,15 +48,28 @@
 //
 //========================================================================*/
 
+#include <pkgconf/hal_cortexm_stm32.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/io/flash.h>
+#include <cyg/io/flash_dev.h>
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+# define STM32_FLASH_MAXBLOCKINFOS 1
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+# define STM32_FLASH_MAXBLOCKINFOS 3
+#endif
+
 // The driver-specific data, pointed at by the priv field in a
 // a cyg_flash_dev structure.
 
 typedef struct cyg_stm32_dev
 {
-    cyg_flash_block_info_t      block_info[1];
-    
+    cyg_flash_block_info_t      block_info[STM32_FLASH_MAXBLOCKINFOS];
 } cyg_stm32_flash_dev;
 
+// The instantiation of that data.
+__externC const cyg_stm32_flash_dev hal_stm32_flash_priv;
+
 //========================================================================*/
 // Exported function pointers.
 
@@ -65,4 +78,4 @@ typedef struct cyg_stm32_dev
 
 //========================================================================*/
 #endif // CYGONCE_DEVS_FLASH_STM32_H
-// End
+// End of stm32_flash.h
diff --git a/packages/devs/flash/cortexm/stm32/current/src/stm32_flash.c b/packages/devs/flash/cortexm/stm32/current/src/stm32_flash.c
--- a/packages/devs/flash/cortexm/stm32/current/src/stm32_flash.c
+++ b/packages/devs/flash/cortexm/stm32/current/src/stm32_flash.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2009, 2011, 2012 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -68,9 +68,43 @@
 
 #include CYGHWR_MEMORY_LAYOUT_H
 
+// Does this look like an F1 or F2/F4 device? It makes a difference to sizing and operation.
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+# define F1STYLE 1
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+# define F2STYLE 1
+#endif
+
+// ----------------------------------------------------------------------------
+
+#if defined(F1STYLE)
+typedef cyg_uint16 STM32_TYPE;
+#elif defined(F2STYLE)
+// F2/F4's alignment requirements depend on parallelism config, so we treat as
+// bytes for now.
+typedef cyg_uint8 STM32_TYPE;
+#endif
+
 // ----------------------------------------------------------------------------
 
-typedef cyg_uint16 STM32_TYPE;
+// How many loops before we consider this a timeout.
+#define STM32_FLASH_TIMEOUT 1000000
+
+// A quick helper macro to avoid repetition.
+#define WAIT_FOR_FLASH_NOT_BUSY(_timeout_)                              \
+  CYG_MACRO_START                                                       \
+  (_timeout_) = STM32_FLASH_TIMEOUT;                                    \
+  do {                                                                  \
+      HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_SR, sr );            \
+  } while( (sr & CYGHWR_HAL_STM32_FLASH_SR_BSY) && (_timeout_)-- > 0 ); \
+  CYG_MACRO_END
+
+// ----------------------------------------------------------------------------
+
+// Note that although the F2/F4 parts need special treatment for the Flash's
+// built-in icache and dcache, that doesn't matter for suspend/resume
+// because no-one should expect any part of the Flash in the area being
+// erased/programmed to be any particular value.
 
 # define STM32_INTSCACHE_STATE     int _saved_ints_
 # define STM32_INTSCACHE_BEGIN()   HAL_DISABLE_INTERRUPTS(_saved_ints_)
@@ -85,8 +119,8 @@ typedef cyg_uint16 STM32_TYPE;
 
 static int stm32_enable_hsi(void);
 static void stm32_disable_hsi(void);
-static int stm32_flash_hw_erase(cyg_flashaddr_t addr) __attribute__((section (".2ram.stm32_flash_hw_erase")));
-static int stm32_flash_hw_program( volatile STM32_TYPE* addr, const cyg_uint16* buf, cyg_uint32 count) __attribute__((section (".2ram.stm32_flash_hw_program")));
+static int stm32_flash_hw_erase(cyg_flashaddr_t addr, cyg_uint16 block_num) __attribute__((section (".2ram.stm32_flash_hw_erase")));
+static int stm32_flash_hw_program( volatile STM32_TYPE* addr, const STM32_TYPE *buf, cyg_uint32 count) __attribute__((section (".2ram.stm32_flash_hw_program")));
     
 // ----------------------------------------------------------------------------
 // Diagnostic routines.
@@ -100,66 +134,203 @@ static int stm32_flash_hw_program( volat
 #endif
 
 // ----------------------------------------------------------------------------
+// Select Flash geometry
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32_F103RC) || \
+    defined(CYGHWR_HAL_CORTEXM_STM32_F103VC) || \
+    defined(CYGHWR_HAL_CORTEXM_STM32_F103ZC) || \
+    defined(CYGHWR_HAL_CORTEXM_STM32_F105RC) || \
+    defined(CYGHWR_HAL_CORTEXM_STM32_F105RC) || \
+    defined(CYGHWR_HAL_CORTEXM_STM32_F105VC) || \
+    defined(CYGHWR_HAL_CORTEXM_STM32_F107VC)
+    
+    // High-density device with 256K flash (2K blocks)
+#define STM32_FLASH_SIZE        0x40000
+    
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_F103RD) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F103VD) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F103ZD)
+    
+    // High-density device with 384K flash (2K blocks)
+#define STM32_FLASH_SIZE        0x60000
+    
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_F103RE) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F103VE) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F103ZE)
+    
+    // High-density device with 512K flash (2K blocks)
+#define STM32_FLASH_SIZE        0x80000
+
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_F205RB) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F205VB) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F205ZB) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F207VB) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F207ZB) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F207IB)
+// 128K
+#define STM32_FLASH_SIZE              (128*1024)
+#define xxxSTM32_FLASH_BLOCK_INFO        { { { 16*1024, 4 } , { 64*1024, 1 } } }   // guesswork at present - documentation is elusive
+#define STM32_FLASH_NUM_BLOCK_INFOS   2
+
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_F205RC) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F205VC) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F205ZC) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F207VC) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F207ZC) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F207IC)
+// 256K
+#define STM32_FLASH_SIZE              (256*1024)
+#define xxxSTM32_FLASH_BLOCK_INFO        { { { 16*1024, 4 } , { 64*1024, 1 }, { 128*1024, 1 } } }   // guesswork at present - documentation is elusive
+#define STM32_FLASH_NUM_BLOCK_INFOS   3
+
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_F205RE) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F205VE) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F205ZE) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F207VE) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F207ZE) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F207IE) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F407IE) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F407VE) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F407ZE) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F417IE) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F417VE) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F417ZE)
+// 512K
+#define STM32_FLASH_SIZE              (512*1024)
+#define xxxSTM32_FLASH_BLOCK_INFO        { { { 16*1024, 4 } , { 64*1024, 1 }, { 128*1024, 3 } } }   // guesswork at present - documentation is elusive
+#define STM32_FLASH_NUM_BLOCK_INFOS   3
+
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_F205RF) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F205VF) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F205ZF) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F207VF) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F207ZF) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F207IF)
+// 768K
+#define STM32_FLASH_SIZE              (768*1024)
+#define xxxSTM32_FLASH_BLOCK_INFO        { { { 16*1024, 4 } , { 64*1024, 1 }, { 128*1024, 5 } } }   // guesswork at present - documentation is elusive
+#define STM32_FLASH_NUM_BLOCK_INFOS   3
+
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_F205RG) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F205VG) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F205ZG) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F207VG) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F207ZG) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F207IG) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F405RG) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F405VG) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F405ZG) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F407IG) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F407VG) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F407ZG) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F417IG) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F417VG) || \
+      defined(CYGHWR_HAL_CORTEXM_STM32_F417ZG)
+
+// 1024K
+#define STM32_FLASH_SIZE              (1024*1024)
+#define STM32_FLASH_BLOCK_INFO        { { { 16*1024, 4 } , { 64*1024, 1 }, { 128*1024, 7 } } }
+#define STM32_FLASH_NUM_BLOCK_INFOS   3
+
+#else
+#error Unknown STM32 microprocessor variant.
+#endif
+    
+#ifdef F1STYLE
+// Always 2K blocks
+#define STM32_FLASH_BLOCK_SIZE  0x800
+#endif
+    
+// If there's just one block size, it's straightforward.
+#if defined(STM32_FLASH_BLOCK_SIZE)
+const cyg_stm32_flash_dev hal_stm32_flash_priv = { { STM32_FLASH_BLOCK_SIZE, STM32_FLASH_SIZE / STM32_FLASH_BLOCK_SIZE } };
+#elif defined(STM32_FLASH_BLOCK_INFO)
+const cyg_stm32_flash_dev hal_stm32_flash_priv = STM32_FLASH_BLOCK_INFO;
+#else
+# error Incomplete STM32 variant details. It needs filling in.
+#endif
+    
+// ----------------------------------------------------------------------------
+
+#ifdef CYGNUM_DEVS_FLASH_STM32_PARALLELISM
+# define CR_PSIZE_MAX        CYGHWR_HAL_STM32_FLASH_CR_PSIZE(CYGNUM_DEVS_FLASH_STM32_PARALLELISM)
+# define PARALLEL_BYTES      (CYGNUM_DEVS_FLASH_STM32_PARALLELISM/8)
+# define PARALLEL_ALIGN_MASK (PARALLEL_BYTES - 1)
+#endif
+
+// ----------------------------------------------------------------------------
+// Translate our error values into eCos flash driver error values
+
+// Some little helper macros for this function to make it shorter/simpler
+#define _SRBIT(_x_) CYGHWR_HAL_STM32_FLASH_SR_##_x_
+#define _FERR(_x_) CYG_FLASH_ERR_##_x_
+#define DECODE_SR_ERROR(_srbit_, _code_) if ( sr & _SRBIT(_srbit_) ) result = _FERR(_code_)
+
+static int
+stm32_flash_decode_error( int sr )
+{
+    int result = CYG_FLASH_ERR_OK;
+
+    // -1 can never be a valid sr value so we use it to indicate a timeout
+    if ( -1 == sr )
+        return CYG_FLASH_ERR_DRV_TIMEOUT;
+
+#if defined(F1STYLE)
+    DECODE_SR_ERROR( PGERR, PROGRAM );
+    DECODE_SR_ERROR( WRPRTERR, PROTECT );
+#elif defined(F2STYLE)
+    // OPERR is probably unnecessary really, but just in case.
+    // Do it before others though so they can override with a better value.
+    DECODE_SR_ERROR( OPERR, HWR );
+    DECODE_SR_ERROR( WRPERR, PROTECT );
+    DECODE_SR_ERROR( PGAERR, INVALID );
+    DECODE_SR_ERROR( PGPERR, PROTOCOL );
+    DECODE_SR_ERROR( PGSERR, PROTOCOL );
+#endif
+    return result;
+}
+
+static void stm32_flash_clear_sr_err(void)
+{
+    cyg_uint32 sr;
+#if defined(F1STYLE)
+    sr = CYGHWR_HAL_STM32_FLASH_SR_PGERR | CYGHWR_HAL_STM32_FLASH_SR_WRPRTERR;
+#elif defined(F2STYLE)
+    sr = CYGHWR_HAL_STM32_FLASH_SR_OPERR |
+      CYGHWR_HAL_STM32_FLASH_SR_WRPERR |
+      CYGHWR_HAL_STM32_FLASH_SR_PGAERR |
+      CYGHWR_HAL_STM32_FLASH_SR_PGPERR |
+      CYGHWR_HAL_STM32_FLASH_SR_PGSERR;
+#endif
+    HAL_WRITE_UINT32( CYGHWR_HAL_STM32_FLASH + CYGHWR_HAL_STM32_FLASH_SR, sr );
+}
+
+// ----------------------------------------------------------------------------
 // Initialize the flash.
 
 
 static int
 stm32_flash_init(struct cyg_flash_dev* dev)
 {
-    cyg_stm32_flash_dev *stm32_dev = (cyg_stm32_flash_dev *)dev->priv;
-    CYG_ADDRESS base = CYGHWR_HAL_STM32_FLASH;
-    cyg_uint32 flash_size, block_size = 0;
-    
     // Set up the block info entries.
 
-    dev->block_info                             = &stm32_dev->block_info[0];
-    dev->num_block_infos                        = 1;
+    dev->block_info                             = &hal_stm32_flash_priv.block_info[0];
+#if defined(STM32_FLASH_NUM_BLOCK_INFOS)
+    dev->num_block_infos                        = STM32_FLASH_NUM_BLOCK_INFOS;
+#else
+    dev->num_block_infos                        = sizeof(hal_stm32_flash_priv.block_info) / sizeof(hal_stm32_flash_priv.block_info[0]);
+#endif
 
     // As stated in the errata sheet, the debug register can only be read in
-    // debug mode and is therfore not accessible by user software.
+    // debug mode and is therefore not accessible by user software.
+
+    // Set end address
+    dev->end                                    = dev->start + STM32_FLASH_SIZE - 1;
 
-#if defined(CYGHWR_HAL_CORTEXM_STM32_F103RC) || \
-    defined(CYGHWR_HAL_CORTEXM_STM32_F103VC) || \
-    defined(CYGHWR_HAL_CORTEXM_STM32_F103ZC)
-    
-    // High-density device with 256K flash (2K blocks)
-    flash_size = 0x40000;
-    block_size = 0x800;
-    
-#elif defined(CYGHWR_HAL_CORTEXM_STM32_F103RD) || \
-      defined(CYGHWR_HAL_CORTEXM_STM32_F103VD) || \
-      defined(CYGHWR_HAL_CORTEXM_STM32_F103ZD)
-    
-    // High-density device with 384K flash (2K blocks)
-    flash_size = 0x60000;
-    block_size = 0x800;
-    
-#elif defined(CYGHWR_HAL_CORTEXM_STM32_F103RE) || \
-      defined(CYGHWR_HAL_CORTEXM_STM32_F103VE) || \
-      defined(CYGHWR_HAL_CORTEXM_STM32_F103ZE)
-    
-    // High-density device with 512K flash (2K blocks)
-    flash_size = 0x80000;
-    block_size = 0x800;
+    stf_diag("block_size %d size %08x end %08x\n", dev->block_info[0].block_size, STM32_FLASH_SIZE, dev->end );    
 
-#else
-
-#error Unknown STM32 microprocessor variant.
-    
-#endif
-    
-    stm32_dev->block_info[0].blocks             = flash_size/block_size;
-    stm32_dev->block_info[0].block_size         = block_size;
-    
-    // Set end address
-    dev->end                                    = dev->start+flash_size-1;
-
-    stf_diag("block_size %d size %08x end %08x\n", block_size, flash_size, dev->end );    
-
-    // Unlock the flash control registers
-
-    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_KEYR, CYGHWR_HAL_STM32_FLASH_KEYR_KEY1 );
-    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_KEYR, CYGHWR_HAL_STM32_FLASH_KEYR_KEY2 );
+    // Ensure there's nothing hanging over from before us.
+    stm32_flash_clear_sr_err();
     
     return CYG_FLASH_ERR_OK;
 }
@@ -178,31 +349,46 @@ stm32_flash_query(struct cyg_flash_dev* 
 // Get info about the current block, i.e. base and size.
 
 static void
-stm32_flash_get_block_info(struct cyg_flash_dev* dev, const cyg_flashaddr_t addr, cyg_flashaddr_t* block_start, size_t* block_size)
+stm32_flash_get_block_info(struct cyg_flash_dev* dev, const cyg_flashaddr_t addr, cyg_flashaddr_t* block_start,
+                           size_t* block_size, cyg_uint16 *block_num)
 {
     size_t          offset  = addr - dev->start;
+    cyg_ucount8  i;
+    cyg_uint32   bi_size_passed = 0;
+    cyg_uint16   blocks_passed = 0;
     
-    *block_start    = dev->start + (offset & ~(dev->block_info[0].block_size-1));
-    *block_size     = dev->block_info[0].block_size;
+    // This loop has the termination condition commented out to silence a
+    // warning. It should never be reached anyway, so that's fine, although
+    // that is checked with an assert.
+
+    for ( i=0; /* i < dev->num_block_info */ ; i++ )
+{
+        const cyg_flash_block_info_t *bi = &dev->block_info[i];
+        cyg_uint32 bi_size = bi->blocks * bi->block_size;
+
+        CYG_ASSERTC( i < dev->num_block_infos );
+    
+        if ( offset < bi_size)
+        {
+            *block_start = dev->start + bi_size_passed + (offset & ~(bi->block_size-1));
+            *block_size  = bi->block_size;
+            while (offset >= bi->block_size)
+            {
+                offset -= bi->block_size;
+                blocks_passed++;
+}
+            *block_num = blocks_passed;
+            break;
+        }
+        bi_size_passed += bi_size;
+        offset -= bi_size;
+        blocks_passed += bi->blocks;
+    }
 }
 
 // ----------------------------------------------------------------------------
 
 static int
-stm32_flash_decode_error( int sr )
-{
-    int result = CYG_FLASH_ERR_OK;
-
-    if( sr & CYGHWR_HAL_STM32_FLASH_SR_PGERR )
-        result = CYG_FLASH_ERR_PROGRAM;
-
-    if( sr & CYGHWR_HAL_STM32_FLASH_SR_WRPRTERR )
-        result = CYG_FLASH_ERR_PROTECT;
-    
-    return result;
-}
-
-static int
 stm32_enable_hsi(void)
 {
     CYG_ADDRESS rcc = CYGHWR_HAL_STM32_RCC;
@@ -239,61 +425,191 @@ stm32_disable_hsi(void)
 // points at the start of the sector.
 
 static int
-stm32_flash_hw_erase(cyg_flashaddr_t addr)
+stm32_flash_hw_erase(cyg_flashaddr_t addr, cyg_uint16 block_num)
 {
     cyg_uint32 base = CYGHWR_HAL_STM32_FLASH;
-    cyg_uint32 sr, cr = 0;
-    cyg_uint32 timeout = 100000;
+    cyg_uint32 sr, cr;
+    cyg_uint32 timeout;
 
-    cr |= CYGHWR_HAL_STM32_FLASH_CR_PER;
+#ifdef CYGDBG_USE_ASSERTS
+    HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_SR, sr );
+    CYG_ASSERT( 0 == (sr &  CYGHWR_HAL_STM32_FLASH_SR_BSY),
+                "Flash busy at start of erase, but it shouldn't be" );
+#endif
+
+    // Unlock the flash control registers
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_KEYR, CYGHWR_HAL_STM32_FLASH_KEYR_KEY1 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_KEYR, CYGHWR_HAL_STM32_FLASH_KEYR_KEY2 );
+
+#if defined(F1STYLE)
+    cr = CYGHWR_HAL_STM32_FLASH_CR_PER;
     HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_CR, cr );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_AR, addr );
+    cr |= CYGHWR_HAL_STM32_FLASH_CR_STRT;
+#elif defined(F2STYLE)
+    cr = CYGHWR_HAL_STM32_FLASH_CR_SER |
+      CR_PSIZE_MAX |
+      CYGHWR_HAL_STM32_FLASH_CR_SNB(block_num) |
+      CYGHWR_HAL_STM32_FLASH_CR_STRT;
+#endif
 
-    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_AR, addr );
-
-    cr |= CYGHWR_HAL_STM32_FLASH_CR_STRT;
     HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_CR, cr );
     
-    do
+    WAIT_FOR_FLASH_NOT_BUSY( timeout );
+
+    // Lock CR again (and clear other bits)
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_CR, CYGHWR_HAL_STM32_FLASH_CR_LOCK );
+    
+#ifdef F2STYLE
+    // For F2 parts, we need to disable and reset the icache and dcache in the ACR.
     {
-        HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_SR, sr );
-    } while( (sr & CYGHWR_HAL_STM32_FLASH_SR_BSY) && timeout-- > 0);
+        cyg_uint32 acr;
 
-    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_CR, 0 );
+        HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+        // disable
+        acr &= ~(CYGHWR_HAL_STM32_FLASH_ACR_DCEN|CYGHWR_HAL_STM32_FLASH_ACR_ICEN);
+        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+        // reset
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_DCRST|CYGHWR_HAL_STM32_FLASH_ACR_ICRST;
+        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+        // re-enable
+        acr &= ~(CYGHWR_HAL_STM32_FLASH_ACR_DCRST|CYGHWR_HAL_STM32_FLASH_ACR_ICRST);
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_DCEN|CYGHWR_HAL_STM32_FLASH_ACR_ICEN;
+        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+    }
+#endif
+
+    if (0 == timeout)
+        return -1;
     
     return sr;
 }
 
 // ----------------------------------------------------------------------------
-// Write data to flash, using individual word writes. The destination
-// address will be aligned in a way suitable for the bus. The source
-// address need not be aligned. The count is in STM32_TYPE's, not in
-// bytes.
+// Write data to flash, using individual word writes on F1, or something more
+// complicated on F2. On F1, the destination address will be aligned in a way suitable
+// for the bus. The source address need not be aligned. The count is in STM32_TYPE's on
+// F1, bytes on F2.
 
 static int
-stm32_flash_hw_program( volatile STM32_TYPE* addr, const cyg_uint16* buf, cyg_uint32 count)
+stm32_flash_hw_program( volatile STM32_TYPE* addr, const STM32_TYPE* buf, cyg_uint32 count)
 {
     cyg_uint32 base = CYGHWR_HAL_STM32_FLASH;
     cyg_uint32 sr = 0, cr = 0;
+    cyg_uint32 timeout = 1; // Have to set timeout to non-zero to avoid confusing tests later.
     
+#ifdef CYGDBG_USE_ASSERTS
+    HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_SR, sr );
+    CYG_ASSERT( 0 == (sr &  CYGHWR_HAL_STM32_FLASH_SR_BSY),
+                "Flash busy at start of program, but it shouldn't be" );
+#endif
+    
+    // Unlock the flash control registers
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_KEYR, CYGHWR_HAL_STM32_FLASH_KEYR_KEY1 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_KEYR, CYGHWR_HAL_STM32_FLASH_KEYR_KEY2 );
+
+#if defined(F1STYLE)
     cr |= CYGHWR_HAL_STM32_FLASH_CR_PG;
     HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_CR, cr );
 
     while( count-- )
     {
-        cyg_uint32 timeout = 100000;
-        
         HAL_WRITE_UINT16( addr, *buf );
-
         addr++;
         buf++;
 
-        do
-        {
-            HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_SR, sr );
-        } while( (sr & CYGHWR_HAL_STM32_FLASH_SR_BSY) && timeout-- > 0 );
+        WAIT_FOR_FLASH_NOT_BUSY(timeout);
+        if ( 0 == timeout )
+            break;
     }
 
-    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_CR, 0 );
+
+#elif defined(F2STYLE)
+    // F2 is more complicated because the alignment depends on the parallelism.
+    // So we "simplify" by writing bytes until we've reached the desired alignment.
+
+    {
+        CYG_ADDRESS addr_max = (CYG_ADDRESS)addr + PARALLEL_ALIGN_MASK;
+        addr_max &= ~PARALLEL_ALIGN_MASK;
+
+    byte_write:
+        cr = CYGHWR_HAL_STM32_FLASH_CR_PG | CYGHWR_HAL_STM32_FLASH_CR_PSIZE_8;
+        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_CR, cr );
+
+        while (count && ((CYG_ADDRESS)addr < addr_max))
+        {
+            HAL_WRITE_UINT8( addr, *buf );
+        addr++;
+        buf++;
+            count--;
+            WAIT_FOR_FLASH_NOT_BUSY(timeout);
+            if (0 == timeout)
+                break;
+        }
+
+        if ( count && timeout )
+        {
+            // Now we should be aligned to the required parallelism boundary
+            // But we have to make sure we stop at an aligned addr too.
+            addr_max += count;
+            addr_max &= ~PARALLEL_ALIGN_MASK;
+
+            cr = CYGHWR_HAL_STM32_FLASH_CR_PG | CR_PSIZE_MAX;
+            HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_CR, cr );
+            while ((CYG_ADDRESS)addr < addr_max)
+            {
+#if (CYGNUM_DEVS_FLASH_STM32_PARALLELISM == 8)
+                HAL_WRITE_UINT8( addr, *buf );
+#elif (CYGNUM_DEVS_FLASH_STM32_PARALLELISM == 16)
+                cyg_uint16 wbuf = *(cyg_uint16*)buf;
+                HAL_WRITE_UINT16( addr, wbuf );
+#elif (CYGNUM_DEVS_FLASH_STM32_PARALLELISM == 32)
+                cyg_uint32 wbuf = *(cyg_uint32*)buf;
+                HAL_WRITE_UINT32( addr, wbuf );
+#elif (CYGNUM_DEVS_FLASH_STM32_PARALLELISM == 64)
+                cyg_uint64 wbuf = *(cyg_uint64*)buf;
+                HAL_WRITE_UINT64( addr, wbuf );
+#endif
+                addr += PARALLEL_BYTES;
+                buf += PARALLEL_BYTES;
+                count -= PARALLEL_BYTES;
+                WAIT_FOR_FLASH_NOT_BUSY(timeout);
+                if (0 == timeout)
+                    break;
+            } // while
+        } // if
+
+        if ( count && timeout )
+        {
+            // Still have some bytes left to write. Take a shortcut with goto, to save code.
+            addr_max = (CYG_ADDRESS)addr+count;
+            goto byte_write;
+        } // if        
+    }
+
+    // For F2 parts, we need to disable and reset the icache and dcache in the ACR.
+    {
+        cyg_uint32 acr;
+
+        HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+        // disable
+        acr &= ~(CYGHWR_HAL_STM32_FLASH_ACR_DCEN|CYGHWR_HAL_STM32_FLASH_ACR_ICEN);
+        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+        // reset
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_DCRST|CYGHWR_HAL_STM32_FLASH_ACR_ICRST;
+        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+        // re-enable
+        acr &= ~(CYGHWR_HAL_STM32_FLASH_ACR_DCRST|CYGHWR_HAL_STM32_FLASH_ACR_ICRST);
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_DCEN|CYGHWR_HAL_STM32_FLASH_ACR_ICEN;
+        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+    }
+#endif // elif defined(F2STYLE)
+
+    // Lock CR again (and clear other bits)
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_CR, CYGHWR_HAL_STM32_FLASH_CR_LOCK );
+
+    if (0 == timeout)
+        return -1;
 
     return sr;    
 }
@@ -305,9 +621,10 @@ stm32_flash_hw_program( volatile STM32_T
 static int
 stm32_flash_erase(struct cyg_flash_dev* dev, cyg_flashaddr_t dest)
 {
-    int                     (*erase_fn)(cyg_uint32);
+    int                     (*erase_fn)(cyg_uint32, cyg_uint16);
     cyg_flashaddr_t         block_start;
     size_t                  block_size;
+    cyg_uint16              block_num;
     int                     result;
     int                     hsi;
     STM32_INTSCACHE_STATE;
@@ -316,18 +633,19 @@ stm32_flash_erase(struct cyg_flash_dev* 
     CYG_CHECK_DATA_PTR(dev, "valid flash device pointer required");
     CYG_ASSERT((dest >= dev->start) && (dest <= dev->end), "flash address out of device range");
     
-    stm32_flash_get_block_info(dev, dest, &block_start, &block_size);
+    stm32_flash_get_block_info(dev, dest, &block_start, &block_size, &block_num);
     stf_diag("block_start %p block_size %d\n", (void *) block_start, block_size);
     CYG_ASSERT(dest == block_start, "erase address should be the start of a flash block");
 
-    erase_fn    = (int (*)(cyg_uint32)) cyg_flash_anonymizer( & stm32_flash_hw_erase );
+    erase_fn    = (int (*)(cyg_uint32, cyg_uint16)) cyg_flash_anonymizer( & stm32_flash_hw_erase );
     
     hsi = stm32_enable_hsi();
     
     STM32_INTSCACHE_BEGIN();    
 
-    result = (*erase_fn)(block_start);
+    result = (*erase_fn)(block_start, block_num);
     result = stm32_flash_decode_error( result );
+    stm32_flash_clear_sr_err();
     
     STM32_INTSCACHE_END();
     
@@ -345,9 +663,9 @@ stm32_flash_erase(struct cyg_flash_dev* 
 int
 stm32_flash_program(struct cyg_flash_dev* dev, cyg_flashaddr_t dest, const void* src, size_t len)
 {
-    int                     (*program_fn)(volatile STM32_TYPE*, const cyg_uint16*, cyg_uint32);
+    int                     (*program_fn)(volatile STM32_TYPE*, const STM32_TYPE*, cyg_uint32);
     volatile STM32_TYPE*    uncached; 
-    const cyg_uint16*       data;
+    const STM32_TYPE*       data;
     size_t                  to_write;
     int                     result  = CYG_FLASH_ERR_OK;
     int                     hsi;
@@ -358,15 +676,17 @@ stm32_flash_program(struct cyg_flash_dev
     CYG_CHECK_DATA_PTR(dev, "valid flash device pointer required");
     CYG_ASSERT((dest >= dev->start) && ((CYG_ADDRESS)dest <= dev->end), "flash address out of device range");
 
+#ifdef F1STYLE
     // Source and destination must be 16-bit aligned.
     if( (0 != ((CYG_ADDRESS)dest & 1)) ||
         (0 != ((CYG_ADDRESS)src  & 1)) )
         return CYG_FLASH_ERR_INVALID;
+#endif
     
     uncached    = STM32_UNCACHED_ADDRESS(dest);
-    data        = (const cyg_uint16*) src;
-    to_write    = len / sizeof(STM32_TYPE);      // Number of words, not bytes
-    program_fn  = (int (*)(volatile STM32_TYPE*, const cyg_uint16*, cyg_uint32)) cyg_flash_anonymizer( & stm32_flash_hw_program );
+    data        = (const STM32_TYPE*) src;
+    to_write    = len / sizeof(STM32_TYPE);      // For F1: Number of words, not bytes. For F2: STM32_TYPE is a byte.
+    program_fn  = (int (*)(volatile STM32_TYPE*, const STM32_TYPE*, cyg_uint32)) cyg_flash_anonymizer( & stm32_flash_hw_program );
 
     hsi = stm32_enable_hsi();
 
@@ -393,6 +713,7 @@ stm32_flash_program(struct cyg_flash_dev
             STM32_INTSCACHE_RESUME();
         }
     }
+    stm32_flash_clear_sr_err();
     STM32_INTSCACHE_END();
     
     if (hsi)
diff --git a/packages/devs/flash/freescale/dspi/sst25xx/current/ChangeLog b/packages/devs/flash/freescale/dspi/sst25xx/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/freescale/dspi/sst25xx/current/ChangeLog
@@ -0,0 +1,35 @@
+2013-06-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/sst25_freescale_dspi.c:
+	Fix double-baud rate define. Bug spotted and patch provided by Mike Jones.
+	[ Bugzilla 1001855 ]
+
+2012-01-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/flash_sst25xx_freescale_dspi.cdl
+	* src/sst25_freescale_dspi.c:
+	New package -- Disk driver for Freescale DSPI [Bugzilla 1001450]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012, 2013 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/flash/freescale/dspi/sst25xx/current/cdl/flash_sst25xx_freescale_dspi.cdl b/packages/devs/flash/freescale/dspi/sst25xx/current/cdl/flash_sst25xx_freescale_dspi.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/freescale/dspi/sst25xx/current/cdl/flash_sst25xx_freescale_dspi.cdl
@@ -0,0 +1,100 @@
+##==========================================================================
+##
+##      flash_sst25xx_freescale_dspi.cdl
+##
+##      SST25XX FLASH instatntiation for Freescale DSPI
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-12-27
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_DEVS_FLASH_SST25XX_FREESCALE_DSPI {
+    display "Driver for SST25XX flash over Freescale DSPI"
+    parent CYGPKG_DEVS_FLASH_SPI_SST25XX
+    
+    cdl_component CYGHWR_DEVS_FLASH_SPI_SST25XX_DEV0 {
+        display "Use SST25XX flash device 0"
+        flavor bool
+        default_value 0
+        no_define
+        
+        requires CYGPKG_DEVS_FLASH_SPI_SST25XX
+        requires CYGPKG_DEVS_SPI_FREESCALE_DSPI
+        implements CYGHWR_DEVS_FLASH_SPI_SST25XX_DEVICE
+        
+        requires CYGHWR_DEVS_FLASH_SST25XX_DEV0_SPI_BUS
+        requires CYGHWR_DEVS_FLASH_SST25XX_DEV0_SPI_CS
+        requires CYGNUM_DEVS_FLASH_SPI_SST25XX_DEV0_MAP_ADDR
+        
+        compile -library=libextras.a sst25xx_freescale_dspi.c
+        
+        cdl_component CYGHWR_DEVS_FLASH_SST25XX_DEV0_SPEED {
+            display "Nominal clock speed Hz"
+            flavor data
+            default_value 25000000
+            
+            cdl_option CYGHWR_DEVS_FLASH_SST25XX_DEV0_SPI_USE_DBR {
+                display "Use double baud rate"
+                flavor bool
+                default_value 0
+                description "
+                    Double baud rate is a feature of Freescale DSPI
+                    that may provide higher baud rates but duty the cycle may be
+                    different than 50/50 depdent on scaler/prescaler setting
+                    for achieved baud rate."
+            }
+        }
+        
+        cdl_option CYGHWR_DEVS_FLASH_SST25XX_DEV0_CS_DLY {
+            display "Nominal chip select delays (units)"
+            flavor data
+            legal_values { 1 10 }
+            default_value 1
+        }
+        
+        cdl_option CYGHWR_DEVS_FLASH_SST25XX_DEV0_CS_DLY_UN {
+            display "Chip select delay unit (ns)"
+            flavor data
+            default_value 100
+            legal_values { 100 1000 }
+        }
+    }
+}
diff --git a/packages/devs/flash/freescale/dspi/sst25xx/current/src/sst25xx_freescale_dspi.c b/packages/devs/flash/freescale/dspi/sst25xx/current/src/sst25xx_freescale_dspi.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/freescale/dspi/sst25xx/current/src/sst25xx_freescale_dspi.c
@@ -0,0 +1,99 @@
+//==========================================================================
+//
+//      sst25xx_freescale_dspi.c
+//
+//      SST25XX FLASH device over Freescale DSPI
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2011-12-14
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+
+#include <pkgconf/system.h>
+#if defined(CYGPKG_IO_SPI) && defined(CYGPKG_DEVS_FLASH_SPI_SST25XX)
+// ------------------------------------------------------------------------
+// There is an SST25XX serial flash on the SPI bus
+//#include <cyg/infra/cyg_type.h>
+#include <cyg/io/spi.h>
+#include <cyg/io/sst25xx.h>
+#include <cyg/io/spi_freescale_dspi.h>
+#include <pkgconf/devs_flash_sst25xx_freescale_dspi.h>
+
+// SPI bus device configuration
+#define SST25XX_SPI_FRAME_SIZE      8
+#define SST25XX_SPI_CLOCK_POL       0
+#define SST25XX_SPI_CLOCK_PHASE     0
+
+#ifdef CYGHWR_DEVS_FLASH_SST25XX_DEV0_SPI_USE_DBR
+# define SST25XX_SPI_DBR_DEV0 1
+#else
+# define SST25XX_SPI_DBR_DEV0 0
+#endif
+
+// Underlaying Freescale DSPI device
+CYG_DEVS_SPI_FREESCALE_DSPI_DEVICE(
+    sst25xx_spi_dev0,                         // Device name
+    CYGHWR_DEVS_FLASH_SST25XX_DEV0_SPI_BUS,  // SPI bus
+    CYGHWR_DEVS_FLASH_SST25XX_DEV0_SPI_CS,   // Dev num (CS)
+    SST25XX_SPI_FRAME_SIZE,                  // Frame size
+    SST25XX_SPI_CLOCK_POL,                   // Clock pol
+    SST25XX_SPI_CLOCK_PHASE,                 // Clock phase
+    CYGHWR_DEVS_FLASH_SST25XX_DEV0_SPEED,    // Clock speed (Hz)
+    CYGHWR_DEVS_FLASH_SST25XX_DEV0_CS_DLY,   // CS assert delay
+    CYGHWR_DEVS_FLASH_SST25XX_DEV0_CS_DLY,   // CS negate delay
+    CYGHWR_DEVS_FLASH_SST25XX_DEV0_CS_DLY,   // Delay between transfers
+    CYGHWR_DEVS_FLASH_SST25XX_DEV0_CS_DLY_UN,// Delay unit (100 or 1000 ns)
+    SST25XX_SPI_DBR_DEV0                     // Use double baud rate
+);
+
+//-----------------------------------------------------------------------------
+// Instantiate the SST25xx device driver.
+
+CYG_DEVS_FLASH_SPI_SST25XX_DRIVER(sst25xx_flash_dev0,
+                                  CYGNUM_DEVS_FLASH_SPI_SST25XX_DEV0_MAP_ADDR,
+                                  &sst25xx_spi_dev0);
+
+#endif // defined(CYGPKG_IO_SPI) && defined(CYGPKG_DEVS_FLASH_SPI_SST25XX)
+
+//==========================================================================
+// EOF sst25xx_freescale_dspi.c
diff --git a/packages/devs/flash/freescale/kinetis/current/ChangeLog b/packages/devs/flash/freescale/kinetis/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/freescale/kinetis/current/ChangeLog
@@ -0,0 +1,30 @@
+2012-04-26  Nicolas Aujoux <nau@csm-instruments.com>
+
+	* cdl/kinetis_flash.cdl
+	* include/kinetis_flash.h
+	* src/kinetis_flash.c
+	New package : Freescale Kinetis flash driver.   [Bugzilla 1001561]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/packages/devs/flash/freescale/kinetis/current/cdl/kinetis_flash.cdl b/packages/devs/flash/freescale/kinetis/current/cdl/kinetis_flash.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/freescale/kinetis/current/cdl/kinetis_flash.cdl
@@ -0,0 +1,104 @@
+## ====================================================================
+##
+##      kinetis_flash.cdl
+##
+##      FLASH memory - Hardware support for kinetis on-chip flash
+##
+## ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2012 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+## ====================================================================
+######DESCRIPTIONBEGIN####
+##
+## Author(s):      Nicolas Aujoux
+## Date:           2012-03-19
+##
+#####DESCRIPTIONEND####
+##
+## ====================================================================
+
+cdl_package CYGPKG_DEVS_FLASH_KINETIS {
+    display       "Kinetis FLASH memory support"
+    parent        CYGPKG_IO_FLASH
+    active_if     CYGPKG_IO_FLASH
+    implements    CYGHWR_IO_FLASH_DEVICE
+
+    include_dir   cyg/io
+
+    description "
+        Flash memory support for kinetis"
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLASH {
+        display         "Use Kinetis Flash driver"
+        flavor          bool
+        default_value   1
+
+        compile   -library=libextras.a kinetis_flash.c
+
+        cdl_option CYGNUM_DEVS_KINETIS_FLASH_LOGIC_ERROR_BUG {
+            display     "Disable cache aliasing and speculation logic"
+            flavor           bool
+            default_value    { 1 }
+            description "
+                There is a logical error which prevent from accessing flash
+                properly if cache or prefetch options are enable in the Flash
+                Memory Controler register.
+                The prefetch option is not supported on program flash only or
+                program flash only with swap feature devices.
+                The cache aliasing is not supported on 512 KB and 384 KB
+                program flash. This option disables this two features."
+        }
+
+        cdl_option CYGNUM_DEVS_KINETIS_FLASH_BLOCK_SIZE {
+            display         "Block size"
+            flavor          data
+            legal_values    { 0 0x800 0x1000 }
+            default_value   0x800
+            description "
+                Size of a flash block (called sector in freescale datasheets) :
+                    0x800 (2KB for k60 with 100M clock and ?)
+                    0x1000 (4KB for k60 with 120M and 150M clock and ?)"
+        }
+
+        cdl_option CYGNUM_DEVS_KINETIS_FLASH_LONGWORD_SIZE {
+            display         "Longword/phrase size"
+            flavor          data
+            legal_values    { 4 8 }
+            default_value   4
+            description "
+                Size of a flash writing word, called LONGWORD (4 bytes)
+                or PHRASE (8 bytes) freescale datasheets."
+        }
+    }
+}
+
+# End of kinetis_flash.cdl
diff --git a/packages/devs/flash/freescale/kinetis/current/include/kinetis_flash.h b/packages/devs/flash/freescale/kinetis/current/include/kinetis_flash.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/freescale/kinetis/current/include/kinetis_flash.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_DEVS_FLASH_KINETIS_H
+#define CYGONCE_DEVS_FLASH_KINETIS_H
+
+//==========================================================================
+//
+//      kinetis_flash.h
+//
+//      kinetis internal flash driver definitions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Nicolas Aujoux
+// Date:         2012-03-19
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+// Required data structures.
+#include <cyg/io/flash_dev.h>
+
+
+// The driver-specific data, pointed at by the priv field in a
+// a cyg_flash_dev structure.
+
+typedef struct cyg_kinetis_dev
+{
+} cyg_kinetis_flash_dev;
+
+#endif //CYGONCE_DEVS_FLASH_KINETIS_H
diff --git a/packages/devs/flash/freescale/kinetis/current/src/kinetis_flash.c b/packages/devs/flash/freescale/kinetis/current/src/kinetis_flash.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/freescale/kinetis/current/src/kinetis_flash.c
@@ -0,0 +1,395 @@
+//=================================================================
+//
+//        kinetis_flash.c
+//
+//        kinetis internal flash driver
+//
+//=================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Nicolas Aujoux
+// Date:         2012-03-19
+//
+//####DESCRIPTIONEND####
+
+
+#include <pkgconf/devs_flash_kinetis.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+
+#include <cyg/io/kinetis_flash.h>
+
+#include <cyg/io/flash.h>
+#include <cyg/io/flash_dev.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/diag.h>
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/hal_tables.h>
+
+// Include memory access routines
+#include <cyg/hal/hal_io.h>
+
+// For tests
+#include <cyg/infra/testcase.h>
+
+#include <string.h>
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+#define LONGWORD_SIZE (CYGNUM_DEVS_KINETIS_FLASH_LONGWORD_SIZE)
+
+// Flash command parameters
+#define FLASH_ERASE_BLOCK           0x08
+#define FLASH_ERASE_ALL_BLOCKS      0X44
+#define FLASH_ERASE_SECTOR          0x09
+#define FLASH_PROGRAM_LONGWORD      0x06
+#define FLASH_PROGRAM_PHRASE        0x07
+
+cyg_uint32 defaultRegisterPFB0CR, defaultRegisterPFB1CR;
+
+static int __attribute__((__long_call__)) flash_command_sequence(void)
+        __attribute__((section(".2ram.flashing")));
+
+static void __attribute__((__long_call__)) enable_flash_acceleration (void)
+            __attribute__((section(".2ram.flashing")));
+static void __attribute__((__long_call__)) disable_flash_acceleration (void)
+            __attribute__((section(".2ram.flashing")));
+
+static void __attribute__((__long_call__)) cache_on(cyg_uint32 *cachestate) __attribute__((section(".2ram.flashing")));
+static void __attribute__((__long_call__)) cache_off(cyg_uint32 *cachestate) __attribute__((section(".2ram.flashing")));
+
+// ===================================================================
+// Flash API functions
+// ===================================================================
+
+static int kinetis_flash_init (struct cyg_flash_dev* dev)
+{
+    HAL_READ_UINT32(CYGHWR_HAL_KINETIS_FMC_PFB0CR, defaultRegisterPFB0CR);
+    HAL_READ_UINT32(CYGHWR_HAL_KINETIS_FMC_PFB1CR, defaultRegisterPFB1CR);
+
+    // SIM_SCGC6: FTFL=1
+    CYGHWR_HAL_KINETIS_SIM_P->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_M;
+
+    return CYG_FLASH_ERR_OK;
+}
+
+static size_t kinetis_flash_query (struct cyg_flash_dev* dev,
+                          void* data, size_t len)
+{
+    static const char query[] = "Kinetis Flash";
+    if (sizeof(query) < len)
+        len = sizeof(query);
+    memcpy( data, query, len);
+    return sizeof(query);
+}
+
+static int kinetis_flash_erase_sector (struct cyg_flash_dev* dev,
+                                cyg_flashaddr_t block_base)
+{
+    cyg_uint32 cachestate;
+    cyghwr_hal_kinetis_flash_t* flashRegister = CYGHWR_HAL_KINETIS_FLASH_P;
+    int returnValue = CYG_FLASH_ERR_OK;
+
+    // Check if the block_base is sector aligned
+    if((block_base % CYGNUM_DEVS_KINETIS_FLASH_BLOCK_SIZE) != 0)
+        return CYG_FLASH_ERR_INVALID;
+
+    // Check for valid range of the address
+    if(block_base < dev->start || (block_base +
+        CYGNUM_DEVS_KINETIS_FLASH_BLOCK_SIZE - 1) > dev->end)
+        return CYG_FLASH_ERR_INVALID;
+
+    cache_off(&cachestate);
+
+    // Create parameters to erase a flash sector
+    flashRegister->fccob0 = FLASH_ERASE_SECTOR;
+    flashRegister->fccob1 = (cyg_uint8)(block_base >> 16);
+    flashRegister->fccob2 = (cyg_uint8)((block_base >> 8) & 0xFF);
+    flashRegister->fccob3 = (cyg_uint8)(block_base & 0xFF);
+    returnValue = flash_command_sequence();
+
+    cache_on(&cachestate);
+
+    return returnValue;
+}
+
+static int kinetis_flash_program (struct cyg_flash_dev* dev,
+                            cyg_flashaddr_t _base,
+                            const void* _data,
+                            size_t _len)
+{
+    cyghwr_hal_kinetis_flash_t* flashRegister = CYGHWR_HAL_KINETIS_FLASH_P;
+    cyg_uint32 endAddress;
+    int returnValue = CYG_FLASH_ERR_OK;
+    cyg_flashaddr_t base = _base;
+    const cyg_uint32* data = _data;
+    size_t len = _len;
+    cyg_uint32 currentData;
+    cyg_uint8 fccob0;
+    cyg_uint32 cachestate;
+
+    endAddress = base + len;
+
+    // Base and data have to be 16-bit aligned
+    if( (((CYG_ADDRESS)base & 1) != 0) || (((CYG_ADDRESS)data  & 1) != 0))
+        return CYG_FLASH_ERR_INVALID;
+
+    // Check for valid range of the addresse
+    if((base < dev->start) || ((endAddress - 1) > dev->end))
+        return CYG_FLASH_ERR_INVALID;
+
+    cache_off(&cachestate);
+
+    while(len > 0)
+    {
+        flashRegister->fccob0 = fccob0 = (4 == LONGWORD_SIZE) ?
+                                         FLASH_PROGRAM_LONGWORD :
+                                         FLASH_PROGRAM_PHRASE;
+        flashRegister->fccob1 = (cyg_uint8)((base >> 16) & 0xFF);
+        flashRegister->fccob2 = (cyg_uint8)((base >> 8) & 0xFF);
+        flashRegister->fccob3 = (cyg_uint8)(base & 0xFF);
+
+        currentData = *data++;
+        flashRegister->fccob4 = (cyg_uint8)((currentData >> 24) & 0xFF);
+        flashRegister->fccob5 = (cyg_uint8)((currentData >> 16) & 0xFF);
+        flashRegister->fccob6 = (cyg_uint8)((currentData >> 8) & 0xFF);
+        flashRegister->fccob7 = (cyg_uint8)((currentData) & 0xFF);
+
+        if(FLASH_PROGRAM_PHRASE == fccob0)
+        {
+            currentData = *data++;
+            flashRegister->fccob8 = (cyg_uint8)((currentData >> 24) & 0xFF);
+            flashRegister->fccob9 = (cyg_uint8)((currentData >> 16) & 0xFF);
+            flashRegister->fccobA = (cyg_uint8)((currentData >> 8) & 0xFF);
+            flashRegister->fccobB = (cyg_uint8)((currentData) & 0xFF);
+        }
+
+        returnValue = flash_command_sequence();
+        if(returnValue != CYG_FLASH_ERR_OK)
+        {
+            break;
+        }
+        else
+        {
+            // Compute the next destination address
+            base += LONGWORD_SIZE;
+
+            // Compute size for the next command
+            len -= LONGWORD_SIZE;
+        }
+    }
+
+    cache_on(&cachestate);
+
+    return returnValue;
+}
+
+static int __attribute__((__long_call__)) flash_command_sequence(void)
+{
+    cyghwr_hal_kinetis_flash_t* flashRegister = CYGHWR_HAL_KINETIS_FLASH_P;
+    cyg_uint8 registerValue;
+    int returnValue;
+
+    while((flashRegister->fstat & CYGHWR_HAL_KINETIS_FLASH_FSTAT_CCIF_M)
+        == false)
+    {
+        // We wait for the end of the previous command ->CCIF bit=0 when finished
+    }
+
+    // clear RDCOLERR & ACCERR & FPVIOL flag in flash status register
+    flashRegister->fstat = (CYGHWR_HAL_KINETIS_FLASH_FSTAT_RDCOLERR_M |
+                            CYGHWR_HAL_KINETIS_FLASH_FSTAT_ACCERR_M |
+                            CYGHWR_HAL_KINETIS_FLASH_FSTAT_FPVIOL_M);
+
+    // Load FFCOB registers with command and paramaters for flash operations
+    // We clear the CCIF bit to start the command
+    HAL_REORDER_BARRIER();
+    flashRegister->fstat = CYGHWR_HAL_KINETIS_FLASH_FSTAT_CCIF_M;
+
+    // We wait the end of the process
+    while((flashRegister->fstat & CYGHWR_HAL_KINETIS_FLASH_FSTAT_CCIF_M)
+        == false){}
+
+    // Check if any error happened
+    // First we read the flash status register
+    registerValue = flashRegister->fstat;
+
+    // Access error
+    if((registerValue & CYGHWR_HAL_KINETIS_FLASH_FSTAT_ACCERR_M) != 0)
+        returnValue = CYG_FLASH_ERR_PROGRAM;
+    // Protection error
+    else if((registerValue & CYGHWR_HAL_KINETIS_FLASH_FSTAT_FPVIOL_M) != 0)
+        returnValue = CYG_FLASH_ERR_PROTECT;
+    // MGSTAT0 non-correctable error
+    else if ((registerValue & CYGHWR_HAL_KINETIS_FLASH_FSTAT_MGSTAT0_M) != 0)
+        returnValue = CYG_FLASH_ERR_PROTOCOL;
+    // No error detected
+    else
+        returnValue = CYG_FLASH_ERR_OK;
+
+    return returnValue;
+}
+
+#if 0
+
+static void kinetis_flash_read(struct cyg_flash_dev *dev,
+                        const cyg_flashaddr_t base,
+                        void *data,
+                        size_t len)
+{
+    memcpy(data, (void*)base, len);
+}
+
+# define KINETIS_FLASH_READ
+
+#endif
+
+// ===================================================================
+// Flash accelerator and cache control functions
+// ===================================================================
+
+
+static void __attribute__((__long_call__)) enable_flash_acceleration ()
+{
+    HAL_WRITE_UINT32(CYGHWR_HAL_KINETIS_FMC_PFB0CR, defaultRegisterPFB0CR);
+    HAL_WRITE_UINT32(CYGHWR_HAL_KINETIS_FMC_PFB1CR, defaultRegisterPFB1CR);
+    __asm__ volatile( "dsb" );
+    __asm__ volatile( "isb" );
+}
+
+static void __attribute__((__long_call__)) disable_flash_acceleration ()
+{
+    cyg_uint32 registerValue;
+
+    // Flash Bank 0 register
+    HAL_READ_UINT32(CYGHWR_HAL_KINETIS_FMC_PFB0CR, registerValue);
+    // We disable data and instruction prefetch
+    registerValue &= ~CYGHWR_HAL_KINETIS_FMC_PFBCR_BIPE;
+    registerValue &= ~CYGHWR_HAL_KINETIS_FMC_PFBCR_BDPE;
+    // We disable data and instruction cache and single entry buffer
+    registerValue &= ~CYGHWR_HAL_KINETIS_FMC_PFBCR_BSEBE;
+    registerValue &= ~CYGHWR_HAL_KINETIS_FMC_PFBCR_BICE;
+    registerValue &= ~CYGHWR_HAL_KINETIS_FMC_PFBCR_BDCE;
+    HAL_WRITE_UINT32(CYGHWR_HAL_KINETIS_FMC_PFB0CR, registerValue);
+    __asm__ volatile( "dsb" );
+    __asm__ volatile( "isb" );
+
+    // Flash Bank 1 register
+    HAL_READ_UINT32(CYGHWR_HAL_KINETIS_FMC_PFB1CR, registerValue);
+    // We disable data and instruction prefetch
+    registerValue &= ~CYGHWR_HAL_KINETIS_FMC_PFBCR_BIPE;
+    registerValue &= ~CYGHWR_HAL_KINETIS_FMC_PFBCR_BDPE;
+    // We disable data and instruction cache and single entry buffer
+    registerValue &= ~CYGHWR_HAL_KINETIS_FMC_PFBCR_BSEBE;
+    registerValue &= ~CYGHWR_HAL_KINETIS_FMC_PFBCR_BICE;
+    registerValue &= ~CYGHWR_HAL_KINETIS_FMC_PFBCR_BDCE;
+    HAL_WRITE_UINT32(CYGHWR_HAL_KINETIS_FMC_PFB1CR, registerValue);
+    __asm__ volatile( "dsb" );
+    __asm__ volatile( "isb" );
+}
+
+static void __attribute__((__long_call__))
+cache_off( cyg_uint32 *cachestate ) {
+    cyg_uint32 intstate, dcachestate, icachestate;
+
+    HAL_DISABLE_INTERRUPTS(intstate); 
+    HAL_DCACHE_IS_ENABLED(dcachestate);
+    HAL_ICACHE_IS_ENABLED(icachestate);
+    *cachestate = (dcachestate ? 1 : 0) | (icachestate ? 2 : 0);
+    if (dcachestate) {
+        HAL_DCACHE_SYNC();
+        HAL_DCACHE_DISABLE();
+    }
+    if (icachestate) {
+        HAL_ICACHE_DISABLE();
+    }
+#ifdef CYGNUM_DEVS_KINETIS_FLASH_LOGIC_ERROR_BUG
+    disable_flash_acceleration();
+#endif
+    HAL_RESTORE_INTERRUPTS(intstate);
+}
+
+static void __attribute__((__long_call__))
+cache_on( cyg_uint32 *cachestate ) {
+#ifdef CYGNUM_DEVS_KINETIS_FLASH_LOGIC_ERROR_BUG
+    enable_flash_acceleration();
+#endif
+    if (*cachestate & 1)
+        HAL_DCACHE_ENABLE();
+    if (*cachestate & 2)
+        HAL_ICACHE_ENABLE();
+}
+
+// ===================================================================
+// Function table
+// ===================================================================
+
+const CYG_FLASH_FUNS (
+                cyg_kinetis_flash_funs,
+                &kinetis_flash_init,
+                &kinetis_flash_query,
+                &kinetis_flash_erase_sector,
+                &kinetis_flash_program,
+#ifdef KINETIS_FLASH_READ
+                &kinetis_flash_read,
+#else
+                NULL,
+#endif
+                cyg_flash_devfn_lock_nop,
+                cyg_flash_devfn_unlock_nop);
+
+// Add the flash driver to the HAL TABLE cyg_flashdev
+
+cyg_kinetis_flash_dev hal_kinetis_flash_priv;
+static const cyg_flash_block_info_t cyg_flash_kinetis_block_info[1] = {{
+    CYGNUM_DEVS_KINETIS_FLASH_BLOCK_SIZE,
+    (CYGMEM_REGION_flash_SIZE) / CYGNUM_DEVS_KINETIS_FLASH_BLOCK_SIZE }};
+
+CYG_FLASH_DRIVER(hal_kinetis_flash,
+                 &cyg_kinetis_flash_funs,
+                 0,
+                 CYGMEM_REGION_flash,
+                 (CYGMEM_REGION_flash + CYGMEM_REGION_flash_SIZE - 1),
+                 1,                             //number of block info
+                 cyg_flash_kinetis_block_info,
+                 &hal_kinetis_flash_priv);
+
+// ----------------------------------------------------------------------------
+// End of kinetis_flash.c
diff --git a/packages/devs/flash/intel/stratav2/current/ChangeLog b/packages/devs/flash/intel/stratav2/current/ChangeLog
--- a/packages/devs/flash/intel/stratav2/current/ChangeLog
+++ b/packages/devs/flash/intel/stratav2/current/ChangeLog
@@ -1,3 +1,9 @@
+2012-03-21  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+            Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* src/strata_aux.c (strata_hw_cfi): Fix compiler warnings that
+	variable is set but not used. [ Bugzilla 1001541 ]
+
 2009-04-21  Bart Veer  <bartv@ecoscentric.com>
 
 	* src/strata.c: Added set of parentheses around macro parameters
diff --git a/packages/devs/flash/intel/stratav2/current/src/strata_aux.c b/packages/devs/flash/intel/stratav2/current/src/strata_aux.c
--- a/packages/devs/flash/intel/stratav2/current/src/strata_aux.c
+++ b/packages/devs/flash/intel/stratav2/current/src/strata_aux.c
@@ -163,7 +163,7 @@ STRATA_FNNAME(strata_hw_cfi)(struct cyg_
     int     dev_size;
     int     i;
     int     erase_regions;
-    cyg_uint8 writebuffer_lsb, writebuffer_msb;
+    cyg_uint8 writebuffer_lsb;
     cyg_uint32 writebuffer;
 
     sf_diag("addr %08x %d cmd %08x\n",addr, sizeof(STRATA_TYPE), STRATA_COMMAND_CFI);
@@ -210,7 +210,7 @@ STRATA_FNNAME(strata_hw_cfi)(struct cyg_
     }
 
     writebuffer_lsb = STRATA_UNSWAP(addr[STRATA_OFFSET_CFI_WRITE_BUFFER_LSB]) & 0x00FF;
-    writebuffer_msb = STRATA_UNSWAP(addr[STRATA_OFFSET_CFI_WRITE_BUFFER_MSB]) & 0x00FF;
+    /* No need to include MSB, it would never be as large as 2^256 ! */
     writebuffer = 1 << writebuffer_lsb;
 
     strata_dev->bufsize = writebuffer / sizeof(STRATA_TYPE);
diff --git a/packages/devs/flash/spi/at25dfxxx/current/ChangeLog b/packages/devs/flash/spi/at25dfxxx/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/spi/at25dfxxx/current/ChangeLog
@@ -0,0 +1,37 @@
+
+2012-01-05  Christophe Coutand  <ecos@hotmail.co.uk>
+	* cdl/at25dfxxx.cdl:
+	* tests/at25dfxxx_test.c: 
+	Added Atmel AT25DFxxx driver test application.
+	[Bugzilla 1001449]
+
+2011-04-13  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* cdl/at25dfxxx.cdl:
+	* include/at25dfxxx.h:
+	* src/at25dfxxx.c:
+	New package - SPI flash driver for Atmel AT25DFxxx devices.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/flash/spi/at25dfxxx/current/cdl/flash_at25dfxxx.cdl b/packages/devs/flash/spi/at25dfxxx/current/cdl/flash_at25dfxxx.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/spi/at25dfxxx/current/cdl/flash_at25dfxxx.cdl
@@ -0,0 +1,133 @@
+##=============================================================================
+##
+##      flash_at25dfxxx..cdl
+##
+##      AT25DFxxx SPI flash driver configuration options.
+##
+##=============================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##=============================================================================
+#######DESCRIPTIONBEGIN####
+##
+##
+## Author(s):   ccoutand, updated for Atmel AT95DFxxx flash
+## Original(s): Chris Holgate
+## Date:        2011-04-25
+## Purpose:     Configure AT95DFxxx SPI flash driver.
+##
+######DESCRIPTIONEND####
+##
+##=============================================================================
+
+cdl_package CYGPKG_DEVS_FLASH_SPI_AT25DFXXX {
+    display       "Atmel AT25DFxxx flash memory support"
+    parent        CYGPKG_IO_FLASH
+
+    active_if     { CYGPKG_IO_FLASH && CYGPKG_IO_SPI }
+    implements    CYGHWR_IO_FLASH_DEVICE
+    implements    CYGHWR_IO_FLASH_INDIRECT_READS
+    implements    CYGHWR_IO_FLASH_BLOCK_LOCKING
+
+    include_dir   cyg/io
+    compile       at25dfxxx.c
+
+    description   "
+        Flash memory support for Atmel AT95DFxxx SPI flash devices
+        and compatibles.  This driver implements the V2 flash driver API."
+
+    cdl_interface CYGHWR_DEVS_FLASH_SPI_AT25DFXXX_DEVICE {
+        display     "Hardware AT25DFxxx FLASH device drivers"
+        description "
+            This calculated option gives the number of AT25DFxxx flash
+            devices on the current platform."
+    }
+
+    cdl_option CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_BLOCK_SIZE {
+        display       "Flash block size in bytes"
+        legal_values  { 4096 32768 65536 }
+        flavor        data
+        default_value { 4096 }
+
+        description   "
+            Most Atmel AT95DFxxx SPI flash devices can use block size of
+            4KB, 32K or 64KB. This option allow users to select the flash
+            geometry to use. For device such as AT25F512 not supporting
+            64K, selecting a wrong geometry will force the driver to
+            abort the initialization process."
+    }
+
+    cdl_option CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_READ_MODE {
+        display       "Flash read transaction"
+        legal_values  { "FAST" "SLOW" "RAPIDS"}
+        flavor        data
+        default_value { "FAST" }
+
+        description   "
+            Atmel AT95DFxxx SPI flash devices differentiate read access
+            according to the throughput required for this operation. The
+            driver allows fast and slow reading operation. Some parts
+            also supports the Atmel RapidS protocol."
+    }
+
+    cdl_option CYGNUM_DEVS_FLASH_SPI_AT25DFXXX_READ_BLOCK_SIZE {
+        display       "Maximum read block size"
+        flavor        data
+        default_value 0
+
+        description   "
+            In theory it is possible to read back the entire flash
+            contents using a single SPI transaction.  However, some SPI
+            bus drivers have a maximum transaction size - for example
+            transactions may be limited to the length of a DMA bounce
+            buffer.  Setting this option to a non-zero value specifies
+            the maximum SPI bus transfer size which will be used when
+            reading back data.  Read requests for areas larger than
+            this block size will automatically be split into a series
+            of smaller SPI bus transactions."
+    }
+
+    cdl_option CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_TESTS {
+        display        "SPI flash driver tests for Atmel AT95DFxxx flash"
+        active_if      CYGPKG_KERNEL
+        active_if      CYGPKG_IO_SPI
+        requires       { CYGHWR_DEVS_FLASH_SPI_AT25DFXXX_DEVICE >= 1 }
+        flavor         data
+        no_define
+        calculated     { "tests/at25dfxxx_test.c" }
+        description    "
+            This option specifies the set of tests for the Atmel AT95DFxxx
+            SPI flash."
+    }
+}
+
+# EOF flash_at25dfxxx.cdl
diff --git a/packages/devs/flash/spi/at25dfxxx/current/include/at25dfxxx.h b/packages/devs/flash/spi/at25dfxxx/current/include/at25dfxxx.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/spi/at25dfxxx/current/include/at25dfxxx.h
@@ -0,0 +1,78 @@
+#ifndef CYGONCE_DEVS_FLASH_SPI_AT25DFXXX_H
+#define CYGONCE_DEVS_FLASH_SPI_AT25DFXXX_H
+
+//=============================================================================
+//
+//      at25dfxxx.h
+//
+//      SPI flash driver for Atmel AT95DFxxx devices and compatibles.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand, updated for Atmel AT95DFxxx flash
+// Original(s): Chris Holgate
+// Purpose:     Atmel AT95DFxxx SPI flash driver implementation
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+// Required data structures.
+#include <cyg/io/flash_dev.h>
+
+// Exported handle on the driver function table.
+externC struct cyg_flash_dev_funs cyg_devs_flash_spi_at25dfxxx_funs;
+
+//-----------------------------------------------------------------------------
+// Macro used to generate a flash device object with the default AT25DFXXX
+// settings.  Even though the block info data structure is declared here, the
+// details are not filled in until the device type is inferred during
+// initialization.  This also applies to the 'end' field which is calculated
+// using the _start_ address and the inferred size of the device.
+// _name_   is the root name of the instantiated data structures.
+// _start_  is the base address of the device - for SPI based devices this can
+//          have an arbitrary value, since the device is not memory mapped.
+// _spidev_ is a pointer to a SPI device object of type cyg_spi_device.  This
+//          is not typechecked during compilation so be careful!
+
+#define CYG_DEVS_FLASH_SPI_AT25DFXXX_DRIVER(_name_, _start_, _spidev_)  \
+struct cyg_flash_block_info _name_ ##_block_info;                       \
+CYG_FLASH_DRIVER(_name_, &cyg_devs_flash_spi_at25dfxxx_funs, 0,         \
+  _start_, _start_, 1, & _name_ ##_block_info, (void*) _spidev_)
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_DEVS_FLASH_SPI_AT25DFXXX_H
+// EOF atd25dfxxx.h
diff --git a/packages/devs/flash/spi/at25dfxxx/current/src/at25dfxxx.c b/packages/devs/flash/spi/at25dfxxx/current/src/at25dfxxx.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/spi/at25dfxxx/current/src/at25dfxxx.c
@@ -0,0 +1,648 @@
+//=============================================================================
+//
+//      at25dfxxx.c
+//
+//      SPI flash driver for Atmel AT25DFxxx devices and compatibles.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand, updated for Atmel AT95DFxxx flash
+// Original(s): Chris Holgate
+// Date:        2011-04-25
+// Purpose:     Atmel AT95DFxxx SPI flash driver implementation
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/io/spi.h>
+#include <cyg/io/flash.h>
+#include <cyg/io/flash_dev.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+
+#include <pkgconf/devs_flash_spi_at25dfxxx.h>
+
+#include <string.h>
+
+//-----------------------------------------------------------------------------
+// Enable polled SPI operation for non-kernel builds.
+
+#ifdef CYGPKG_KERNEL
+# define AT25DFXXX_POLLED false
+#else
+# define AT25DFXXX_POLLED true
+#endif
+
+//-----------------------------------------------------------------------------
+// Implement delay functions for kernel and non-kernel builds.  The kernel
+// build assumes that the API calls are made in the thread context.
+
+#ifdef CYGPKG_KERNEL
+# define AT25DFXXX_DELAY_MS(_msdelay_) cyg_thread_delay \
+  (1 + ((1000 * _msdelay_ * CYGNUM_HAL_RTC_DENOMINATOR) / (CYGNUM_HAL_RTC_NUMERATOR / 1000)))
+
+#else
+# define AT25DFXXX_DELAY_MS(_msdelay_) CYGACC_CALL_IF_DELAY_US (_msdelay_ * 1000)
+#endif
+
+//-----------------------------------------------------------------------------
+// Maintenance and debug macros.
+
+#define ASSERT_AT25DFXXX(_test_, _msg_) CYG_ASSERT(_test_, "FAIL (AT25DFXXX) : " _msg_)
+#define TRACE_AT25DFXXX(_msg_, _args_...) if (dev->pf) dev->pf ("AT25DFXXX : " _msg_, ##_args_)
+
+//=============================================================================
+// Define AT25DFxxx SPI protocol.
+//=============================================================================
+
+typedef enum at25dfxxx_cmd {
+    AT25DFXXX_CMD_WREN   = 0x06,       // Write enable.
+    AT25DFXXX_CMD_WDRI   = 0x04,       // Write disable.
+    AT25DFXXX_CMD_RDID   = 0x9F,       // Read identification.
+    AT25DFXXX_CMD_RDSR1  = 0x05,       // Read status register.
+    AT25DFXXX_CMD_RDSR2  = 0x31,       // Read status register.
+    AT25DFXXX_CMD_WRSR   = 0x01,       // Write status register.
+    AT25DFXXX_CMD_SREAD  = 0x03,       // Read data (slow transaction).
+    AT25DFXXX_CMD_READ   = 0x0B,       // Read data.
+    AT25DFXXX_CMD_FREAD  = 0x1B,       // Read data (fast transaction).
+    AT25DFXXX_CMD_PP     = 0x02,       // Page program.
+    AT25DFXXX_CMD_SE_4K  = 0x20,       // 4K sector erase.
+    AT25DFXXX_CMD_SE_32K = 0x52,       // 32K sector erase.
+    AT25DFXXX_CMD_SE_64K = 0xD8,       // 64K sector erase.
+    AT25DFXXX_CMD_BE     = 0xC7,       // Chip erase.
+    AT25DFXXX_CMD_LOCK   = 0x36,       // Protect sector
+    AT25DFXXX_CMD_UNLOCK = 0x39,       // Unprotect sector
+} at25dfxxx_cmd;
+
+// Status register bitfields.
+#define AT25DFXXX_STATUS_BSY  0x01     /* Operation in progress. */
+#define AT25DFXXX_STATUS_WEL  0x02     /* Write enable latch. */
+#define AT25DFXXX_STATUS_BP0  0x04     /* Global protect 0. */
+#define AT25DFXXX_STATUS_BP1  0x08     /* Global protect 1. */
+#define AT25DFXXX_STATUS_BP2  0x10     /* Global protect 2. */
+#define AT25DFXXX_STATUS_SPRL 0x80     /* Sector Protect Register Lock. */
+
+// Page size of 256 bytes appears to be common for all devices.
+#define AT25DFXXX_PAGE_SIZE   256
+
+// A few helper constants
+#ifndef SZ_1K
+# define SZ_1K           0x00000400
+# define SZ_2K           0x00000800
+# define SZ_4K           0x00001000
+# define SZ_8K           0x00002000
+# define SZ_16K          0x00004000
+# define SZ_32K          0x00008000
+# define SZ_64K          0x00010000
+#endif
+
+// Select read OPCODE
+#if defined(CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_READ_MODE_SLOW)
+# define AT25DFXXX_CMD_READ_LEN 4
+# define AT25DFXXX_CMD_READ_OPCODE AT25DFXXX_CMD_SREAD
+#elif defined(CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_READ_MODE_FAST)
+# define AT25DFXXX_CMD_READ_LEN 5
+# define AT25DFXXX_CMD_READ_OPCODE AT25DFXXX_CMD_READ
+#elif defined(CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_READ_MODE_RAPIDS)
+# define AT25DFXXX_CMD_READ_LEN 6
+# define AT25DFXXX_CMD_READ_OPCODE AT25DFXXX_CMD_FREAD
+#endif
+
+// Select sector size
+#if CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_BLOCK_SIZE == SZ_64K
+# define AT25DFXXX_CMD_SE AT25DFXXX_CMD_SE_64K
+#elif CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_BLOCK_SIZE == SZ_32K
+# define AT25DFXXX_CMD_SE AT25DFXXX_CMD_SE_32K
+#elif CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_BLOCK_SIZE == SZ_4K
+# define AT25DFXXX_CMD_SE AT25DFXXX_CMD_SE_4K
+#endif
+
+//=============================================================================
+// Array containing a list of supported devices.  This allows the device
+// parameters to be dynamically detected on initialization.
+//=============================================================================
+
+typedef struct at25dfxxx_params {
+    // Atmel AT25DFxxx SPI flash can be used with 4K, 32K or 64K sector size.
+    // sector_size, sector_count are defined as array, allowing
+    // to describe the geometry of the device for all supported sector size.
+    cyg_uint32      sector_size[4];       // Supported sector size(s) in Byte
+    cyg_uint16      sector_count[4];      // Number of sectors on device.
+    cyg_bool        support_rapids;       // Atmel RapidS protocol support
+    cyg_uint32      jedec_id;             // 3 byte JEDEC identifier
+} at25dfxxx_params;
+
+
+static const at25dfxxx_params at25dfxxx_supported_devices [] = {
+    // Some Atmel AT25DFxxx part (Atmel JEDEC code: 0x1f)
+    // Consider removing the revision number from the Manufacturer /
+    // Device ID for larger chip coverage.
+
+    { // Support for Atmel 64 MBit devices (AT25DF641).
+        sector_count        : {2048, 256, 128, 0},
+        sector_size         : {SZ_4K, SZ_32K, SZ_64K, 0},
+        support_rapids      : true,
+        jedec_id            : 0x001f4800
+    },
+    { // Support for Atmel 32 MBit devices (AT25DF321A).
+        sector_count        : {1024, 128, 64, 0},
+        sector_size         : {SZ_4K, SZ_32K, SZ_64K, 0},
+        support_rapids      : true,
+        jedec_id            : 0x001f4701
+    },
+    { // Support for Atmel 16 MBit devices (AT25DF161).
+        sector_count        : {512, 64, 32, 0},
+        sector_size         : {SZ_4K, SZ_32K, SZ_64K, 0},
+        support_rapids      : true,
+        jedec_id            : 0x001f4602
+    },
+    { // Support for Atmel 8 MBit devices (AT25DF081A).
+        sector_count        : {256, 32, 16, 0},
+        sector_size         : {SZ_4K, SZ_32K, SZ_64K, 0},
+        support_rapids      : true,
+        jedec_id            : 0x001f4501
+    },
+    { // Support for Atmel 4 MBit devices (AT25DF041A).
+        sector_count        : {128, 16, 8, 0},
+        sector_size         : {SZ_4K, SZ_32K, SZ_64K, 0},
+        support_rapids      : false,
+        jedec_id            : 0x001f4400
+    },
+    { // Support for Atmel 2 MBit devices (AT25DF021).
+        sector_count        : {64, 8, 4, 0},
+        sector_size         : {SZ_4K, SZ_32K, SZ_64K, 0},
+        support_rapids      : false,
+        jedec_id            : 0x001f4300
+    },
+    { // Support for Atmel 512 KBit devices (AT25F512B).
+        sector_count        : {8, 1, 0},
+        sector_size         : {SZ_4K, SZ_32K, 0},
+        support_rapids      : false,
+        jedec_id            : 0x001f6500
+    },
+    { // Null terminating entry.
+        sector_count        : {0},
+        sector_size         : {0},
+        support_rapids      : false,
+        jedec_id            : 0
+    }
+};
+//=============================================================================
+// Utility functions for address calculations.
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Strips out any device address offset to give address within device.
+
+static cyg_bool
+at25dfxxx_to_local_addr(struct cyg_flash_dev *dev, cyg_flashaddr_t * addr)
+{
+    cyg_bool        retval = false;
+
+    // Range check address before modifying it.
+    if ((*addr >= dev->start) && (*addr <= dev->end)) {
+        *addr -= dev->start;
+        retval = true;
+    }
+    return retval;
+}
+
+//=============================================================================
+// Wrapper functions for various SPI transactions.
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Read back the 3-byte JEDEC ID, returning it as a 32-bit integer.
+// This function is called during flash initialisation, which can often be
+// called from the startup/idle thread.  This means that we should always use
+// SPI polled mode in order to prevent the thread from attempting to sleep.
+
+static inline cyg_uint32
+at25dfxxx_spi_rdid(struct cyg_flash_dev *dev)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    const cyg_uint8 tx_buf[4] = { AT25DFXXX_CMD_RDID, 0x0, 0x0, 0x0 };
+    cyg_uint8       rx_buf[4];
+    cyg_uint32      retval = 0;
+
+    // Carry out SPI transfer.
+    cyg_spi_transfer(spi_device, true, 4, tx_buf, rx_buf);
+
+    // Convert 3-byte ID to 32-bit integer.
+    retval |= ((cyg_uint32)rx_buf[1]) << 16;
+    retval |= ((cyg_uint32)rx_buf[2]) << 8;
+    retval |= ((cyg_uint32)rx_buf[3]);
+
+    return retval;
+}
+
+//-----------------------------------------------------------------------------
+// Send write enable command.
+
+static inline void
+at25dfxxx_spi_wren(struct cyg_flash_dev *dev)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    const cyg_uint8 tx_buf[1] = { AT25DFXXX_CMD_WREN };
+    cyg_spi_transfer(spi_device, AT25DFXXX_POLLED, 1, tx_buf, NULL);
+}
+
+//-----------------------------------------------------------------------------
+// Send sector erase command.  The address parameter is a device local address
+// within the sector to be erased.
+
+static inline void
+at25dfxxx_spi_se(struct cyg_flash_dev *dev, cyg_flashaddr_t addr)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    cyg_uint8       tx_buf[4] = { AT25DFXXX_CMD_SE,
+        (cyg_uint8)(addr >> 16), (cyg_uint8)(addr >> 8), (cyg_uint8)(addr)
+    };
+    cyg_spi_transfer(spi_device, AT25DFXXX_POLLED, 4, tx_buf, NULL);
+}
+
+//-----------------------------------------------------------------------------
+// Send sector erase command.  The address parameter is a device local address
+// within the sector to be erased.
+
+static inline void
+at25dfxxx_spi_lock(struct cyg_flash_dev *dev, cyg_flashaddr_t addr)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    const cyg_uint8 tx_buf[4] = { AT25DFXXX_CMD_LOCK,
+        (cyg_uint8)(addr >> 16), (cyg_uint8)(addr >> 8), (cyg_uint8)(addr)
+    };
+    cyg_spi_transfer(spi_device, AT25DFXXX_POLLED, 4, tx_buf, NULL);
+}
+
+//-----------------------------------------------------------------------------
+// Send sector erase command.  The address parameter is a device local address
+// within the sector to be erased.
+
+static inline void
+at25dfxxx_spi_unlock(struct cyg_flash_dev *dev, cyg_flashaddr_t addr)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    const cyg_uint8 tx_buf[4] = { AT25DFXXX_CMD_UNLOCK,
+        (cyg_uint8)(addr >> 16), (cyg_uint8)(addr >> 8), (cyg_uint8)(addr)
+    };
+    cyg_spi_transfer(spi_device, AT25DFXXX_POLLED, 4, tx_buf, NULL);
+}
+
+//-----------------------------------------------------------------------------
+// Read and return the 8-bit device status register.
+
+static inline cyg_uint8
+at25dfxxx_spi_rdsr(struct cyg_flash_dev *dev)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    const cyg_uint8 tx_buf[2] = { AT25DFXXX_CMD_RDSR1, 0 };
+    cyg_uint8       rx_buf[2];
+
+    // Carry out SPI transfer and return the status byte.
+    cyg_spi_transfer(spi_device, AT25DFXXX_POLLED, 2, tx_buf, rx_buf);
+
+    return rx_buf[1];
+}
+
+//-----------------------------------------------------------------------------
+// Program a single page.
+
+static inline void
+at25dfxxx_spi_pp(struct cyg_flash_dev *dev, cyg_flashaddr_t addr,
+                 cyg_uint8 *wbuf, cyg_uint32 wbuf_len)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    const cyg_uint8 tx_buf[4] = { AT25DFXXX_CMD_PP,
+        (cyg_uint8)(addr >> 16), (cyg_uint8)(addr >> 8), (cyg_uint8)(addr)
+    };
+
+    // Implement the program operation as a multistage SPI transaction.
+    cyg_spi_transaction_begin(spi_device);
+    cyg_spi_transaction_transfer(spi_device, AT25DFXXX_POLLED, 4, tx_buf,
+                                 NULL, false);
+    cyg_spi_transaction_transfer(spi_device, AT25DFXXX_POLLED, wbuf_len, wbuf,
+                                 NULL, false);
+    cyg_spi_transaction_end(spi_device);
+}
+
+//-----------------------------------------------------------------------------
+// Implement reads to the specified buffer.
+
+static inline void
+at25dfxxx_spi_read(struct cyg_flash_dev *dev, cyg_flashaddr_t addr,
+                   cyg_uint8 *rbuf, cyg_uint32 rbuf_len)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    const cyg_uint8 tx_buf[6] = { AT25DFXXX_CMD_READ_OPCODE,
+        (cyg_uint8)(addr >> 16), (cyg_uint8)(addr >> 8), (cyg_uint8)(addr), 0,
+            0
+    };
+
+    // Implement the read operation as a multistage SPI transaction.
+    cyg_spi_transaction_begin(spi_device);
+    cyg_spi_transaction_transfer(spi_device, AT25DFXXX_POLLED,
+                                 AT25DFXXX_CMD_READ_LEN, tx_buf, NULL, false);
+    cyg_spi_transaction_transfer(spi_device, AT25DFXXX_POLLED, rbuf_len, NULL,
+                                 rbuf, false);
+    cyg_spi_transaction_end(spi_device);
+}
+
+//=============================================================================
+// Standard Flash device API.  All the following functions assume that a valid
+// SPI device handle is passed in the 'priv' reference of the flash device
+// data structure.
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Initialize the SPI flash, reading back the flash parameters.
+
+static int
+at25dfxxx_init(struct cyg_flash_dev *dev)
+{
+    at25dfxxx_params *dev_params =
+        (at25dfxxx_params *) at25dfxxx_supported_devices;
+    cyg_uint32      device_id;
+    int             retval = FLASH_ERR_INVALID;
+    cyg_uint8       i = 0;
+
+    // Find the device in the supported devices list.
+    device_id = at25dfxxx_spi_rdid(dev);
+    while ((dev_params->jedec_id != 0) && (dev_params->jedec_id != device_id)) {
+        dev_params++;
+    }
+
+    // Found supported device - update device parameters.  AT25DFXXX devices
+    // have a uniform sector distribution, so only 1 block info record is
+    // required.
+    if (dev_params->jedec_id != 0) {
+
+        while ((dev_params->sector_size[i] !=
+                CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_BLOCK_SIZE)
+               && (dev_params->sector_size[i] != 0))
+            i++;
+
+        // Verify that the device supports the wanted geometry
+        if (dev_params->sector_size[i] !=
+            CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_BLOCK_SIZE) {
+            TRACE_AT25DFXXX("Init device with JEDEC ID 0x%06X\n",
+                            dev_params->jedec_id);
+            TRACE_AT25DFXXX
+                ("SPI Flash Error, not supporting %dK sector size\n",
+                 CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_BLOCK_SIZE);
+            return retval;
+        }
+
+#if defined(CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_READ_MODE_RAPIDS)
+        if (dev_params->support_rapids != true) {
+            TRACE_AT25DFXXX("Init device with JEDEC ID 0x%06X\n",
+                            dev_params->jedec_id);
+            TRACE_AT25DFXXX
+                ("SPI Flash Error, not supporting RapidS Opcode\n");
+            return retval;
+        }
+#endif
+
+        ASSERT_AT25DFXXX(dev->num_block_infos == 1,
+                         "Only 1 block info record required.");
+        ASSERT_AT25DFXXX(dev->block_info != NULL,
+                         "Null pointer to block info record.");
+
+        if ((dev->num_block_infos == 1) && (dev->block_info != NULL)) {
+            TRACE_AT25DFXXX("Init device with JEDEC ID 0x%06X.\n", device_id);
+
+            dev->end =
+                dev->start +
+                ((cyg_flashaddr_t) dev_params->sector_size[i] *
+                 (cyg_flashaddr_t) (dev_params->sector_count[i])) - 1;
+
+            // Strictly speaking the block info fields are 'read only'.
+            // However, we have a legitimate reason for updating the contents
+            // here and can cast away the const.
+            ((cyg_flash_block_info_t *) dev->block_info)->block_size =
+                (size_t)(dev_params->sector_size[i]);
+            ((cyg_flash_block_info_t *) dev->block_info)->blocks =
+                (cyg_uint32)(dev_params->sector_count[i]);
+
+            retval = FLASH_ERR_OK;
+        }
+    }
+    return retval;
+}
+
+//-----------------------------------------------------------------------------
+// Erase a single sector of the flash.
+
+static int
+at25dfxxx_erase_block(struct cyg_flash_dev *dev, cyg_flashaddr_t block_base)
+{
+    cyg_flashaddr_t local_base = block_base;
+    int             retval = FLASH_ERR_INVALID;
+    cyg_uint8       dev_status;
+
+    // Fix up the block address and send the sector erase command.
+    if (at25dfxxx_to_local_addr(dev, &local_base)) {
+        at25dfxxx_spi_wren(dev);
+        at25dfxxx_spi_se(dev, local_base);
+
+        // Spin waiting for the erase to complete.
+        do {
+            AT25DFXXX_DELAY_MS(1);
+            dev_status = at25dfxxx_spi_rdsr(dev);
+        } while (dev_status & AT25DFXXX_STATUS_BSY);
+
+        retval = FLASH_ERR_OK;
+    }
+    return retval;
+}
+
+//-----------------------------------------------------------------------------
+// Program an arbitrary number of pages into flash and verify written data.
+
+static int
+at25dfxxx_program(struct cyg_flash_dev *dev, cyg_flashaddr_t base,
+                  const void *data, size_t len)
+{
+    cyg_flashaddr_t local_base = base;
+    int             retval = FLASH_ERR_OK;
+    cyg_uint8      *tx_ptr = (cyg_uint8 *)data;
+    cyg_uint32      tx_bytes_left = (cyg_uint32)len;
+    cyg_uint32      tx_bytes;
+    cyg_uint8       dev_status;
+
+    // Fix up the block address.
+    if (!at25dfxxx_to_local_addr(dev, &local_base)) {
+        retval = FLASH_ERR_INVALID;
+        goto out;
+    }
+    // The start of the transaction may not be page aligned, so we need to work
+    // out how many bytes to transmit before we hit the first page boundary.
+    tx_bytes =
+        AT25DFXXX_PAGE_SIZE -
+        (((cyg_uint32)local_base) & (AT25DFXXX_PAGE_SIZE - 1));
+    if (tx_bytes > tx_bytes_left)
+        tx_bytes = tx_bytes_left;
+
+    // Perform page program operations.
+    while (tx_bytes_left) {
+        at25dfxxx_spi_wren(dev);
+        at25dfxxx_spi_pp(dev, local_base, tx_ptr, tx_bytes);
+
+        // Spin waiting for write to complete.  This can take up to 5ms, so
+        // we use a polling interval of 1ms - which may get rounded up to the
+        // RTC tick granularity.
+        do {
+            AT25DFXXX_DELAY_MS(1);
+            dev_status = at25dfxxx_spi_rdsr(dev);
+        } while (dev_status & AT25DFXXX_STATUS_BSY);
+
+        // Update counters and data pointers for the next page.
+        tx_bytes_left -= tx_bytes;
+        tx_ptr += tx_bytes;
+        local_base += tx_bytes;
+        tx_bytes =
+            (tx_bytes_left >
+             AT25DFXXX_PAGE_SIZE) ? AT25DFXXX_PAGE_SIZE : tx_bytes_left;
+    }
+
+out:
+    return retval;
+}
+
+//-----------------------------------------------------------------------------
+// Read back an arbitrary amount of data from flash.
+
+static int
+at25dfxxx_read(struct cyg_flash_dev *dev, const cyg_flashaddr_t base,
+               void *data, size_t len)
+{
+    cyg_flashaddr_t local_base = base;
+    int             retval = FLASH_ERR_INVALID;
+    cyg_uint8      *rx_ptr = (cyg_uint8 *)data;
+    cyg_uint32      rx_bytes_left = (cyg_uint32)len;
+    cyg_uint32      rx_bytes;
+
+    // Determine the maximum transfer size to use.
+    cyg_uint32      rx_block_size =
+        (CYGNUM_DEVS_FLASH_SPI_AT25DFXXX_READ_BLOCK_SIZE ==
+         0) ? 0xFFFFFFFF : CYGNUM_DEVS_FLASH_SPI_AT25DFXXX_READ_BLOCK_SIZE;
+
+    // Fix up the block address and fill the read buffer.
+    if (at25dfxxx_to_local_addr(dev, &local_base)) {
+        while (rx_bytes_left) {
+            rx_bytes =
+                (rx_bytes_left <
+                 rx_block_size) ? rx_bytes_left : rx_block_size;
+            at25dfxxx_spi_read(dev, local_base, rx_ptr, rx_bytes);
+
+            // Update counters and data pointers for next read block.
+            rx_bytes_left -= rx_bytes;
+            rx_ptr += rx_bytes;
+            local_base += rx_bytes;
+        }
+        retval = FLASH_ERR_OK;
+    }
+    return retval;
+}
+
+//-----------------------------------------------------------------------------
+// Lock sector
+
+static int
+at25dfxxx_lock(struct cyg_flash_dev *dev, cyg_flashaddr_t base)
+{
+    cyg_flashaddr_t local_base = base;
+    int             retval = FLASH_ERR_INVALID;
+    cyg_uint8       dev_status;
+
+    // Fix up the block address and send the sector erase command.
+    if (at25dfxxx_to_local_addr(dev, &local_base)) {
+        at25dfxxx_spi_wren(dev);
+        at25dfxxx_spi_lock(dev, local_base);
+
+        // Spin waiting for the lock operation to complete.
+        do {
+            AT25DFXXX_DELAY_MS(1);
+            dev_status = at25dfxxx_spi_rdsr(dev);
+        } while (dev_status & AT25DFXXX_STATUS_BSY);
+        retval = FLASH_ERR_OK;
+    }
+    return retval;
+}
+
+//-----------------------------------------------------------------------------
+// Unlock sector
+
+static int
+at25dfxxx_unlock(struct cyg_flash_dev *dev, cyg_flashaddr_t base)
+{
+    cyg_flashaddr_t local_base = base;
+    int             retval = FLASH_ERR_INVALID;
+    cyg_uint8       dev_status;
+
+    // Fix up the block address and send the sector erase command.
+    if (at25dfxxx_to_local_addr(dev, &local_base)) {
+        at25dfxxx_spi_wren(dev);
+        at25dfxxx_spi_unlock(dev, local_base);
+
+        // Spin waiting for the unlock operation to complete.
+        do {
+            AT25DFXXX_DELAY_MS(1);
+            dev_status = at25dfxxx_spi_rdsr(dev);
+        } while (dev_status & AT25DFXXX_STATUS_BSY);
+        retval = FLASH_ERR_OK;
+    }
+    return retval;
+}
+
+//=============================================================================
+// Fill in the driver data structures.
+//=============================================================================
+
+CYG_FLASH_FUNS(
+        cyg_devs_flash_spi_at25dfxxx_funs, // Exported name of function pointers
+        at25dfxxx_init,                    // Flash initialization
+        cyg_flash_devfn_query_nop,         // Query operations not supported
+        at25dfxxx_erase_block,             // Sector erase
+        at25dfxxx_program,                 // Program multiple pages
+        at25dfxxx_read,                    // Read arbitrary amount of data
+        at25dfxxx_lock,                    // Locking
+        at25dfxxx_unlock);
+
+//-----------------------------------------------------------------------------
+// EOF at25dfxxx.c
diff --git a/packages/devs/flash/spi/at25dfxxx/current/tests/at25dfxxx_test.c b/packages/devs/flash/spi/at25dfxxx/current/tests/at25dfxxx_test.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/spi/at25dfxxx/current/tests/at25dfxxx_test.c
@@ -0,0 +1,398 @@
+//=============================================================================
+//
+//      at25dfxxx_test.c
+//
+//      SPI flash driver tests for Atmel AT95DFxxx flash
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand, updated for Atmel AT95DFxxx flash
+// Original(s): Chris Holgate
+// Date:        2011-04-25
+// Purpose:     Atmel AT95DFxxx SPI flash driver stress tests.
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/system.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/testcase.h>           // Test macros
+#include <cyg/infra/cyg_ass.h>            // Assertion macros
+#include <cyg/infra/diag.h>               // Diagnostic output
+
+#include <cyg/hal/hal_arch.h>             // CYGNUM_HAL_STACK_SIZE_TYPICAL
+#include <cyg/hal/hal_if.h>
+#include <cyg/kernel/kapi.h>
+
+#include <cyg/io/spi.h>
+#include <cyg/io/flash.h>
+#include <cyg/io/at25dfxxx.h>
+
+// Required data structures.
+#include <cyg/io/flash_dev.h>
+
+#include <string.h>
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+static cyg_flash_info_t at25dfxxx_flash_info;
+
+//-----------------------------------------------------------------------------
+// Thread data structures.
+
+static cyg_uint32 stack [CYGNUM_HAL_STACK_SIZE_TYPICAL / 4];
+static cyg_thread thread_data;
+static cyg_handle_t thread_handle;
+
+//-----------------------------------------------------------------------------
+// Data transfer buffers.
+
+#define BUF_SIZE 1024
+
+static cyg_uint8 wbuf [BUF_SIZE];
+static cyg_uint8 rbuf [BUF_SIZE];
+
+//-----------------------------------------------------------------------------
+// Print out version information.
+
+void do_version (void)
+{
+    char *version = CYGACC_CALL_IF_MONITOR_VERSION();
+    if (version != NULL) diag_printf("%s", version);
+#ifdef HAL_PLATFORM_CPU
+    diag_printf("\nPlatform: %s (%s) %s\n",
+                   HAL_PLATFORM_BOARD, HAL_PLATFORM_CPU, HAL_PLATFORM_EXTRA);
+#endif
+    diag_printf("RAM: %p-%p, ",
+      (void*)(CYGMEM_REGION_ram), (void*)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - 1));
+    diag_printf("(HEAP: %p-%p)\n",
+      (void*)(CYGMEM_SECTION_heap1), (void*)(CYGMEM_SECTION_heap1 + CYGMEM_SECTION_heap1_SIZE - 1));
+}
+
+//-----------------------------------------------------------------------------
+// Run checkerboard and inverse checkerboard writes over each sector in turn.
+
+cyg_uint32 run_test_1
+  (void)
+{
+    int status;
+    cyg_uint32 i, j;
+    cyg_uint32 errors = 0;
+    cyg_flashaddr_t base_addr, err_addr;
+
+    diag_printf ("Test 1 - write and verify checkerboard and inverse checkerboard.\n");
+
+    // Iterate over all flash sectors.
+    for (i = 0; i < at25dfxxx_flash_info.block_info->blocks; i++) {
+        base_addr =  at25dfxxx_flash_info.start +
+                            (i * at25dfxxx_flash_info.block_info->block_size);
+
+        // Unlock block.
+        status = cyg_flash_unlock (base_addr, 1, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash erase error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+
+        // Erase block.
+        status = cyg_flash_erase (base_addr, 1, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash erase error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+
+        // Set up buffer with checkerboard.
+        for (j = 0; j < BUF_SIZE;) {
+           wbuf [j++] = 0x55;
+           wbuf [j++] = 0xAA;
+        }
+
+        // Write the checkerboard to the entire sector.
+        for (j = 0; j < at25dfxxx_flash_info.block_info->block_size ; j += BUF_SIZE) {
+            status = cyg_flash_program (base_addr + j, wbuf, BUF_SIZE, &err_addr);
+            if (status != FLASH_ERR_OK) {
+                diag_printf ("Flash write error : %s\n", cyg_flash_errmsg (status));
+                errors ++;
+            }
+        }
+
+        // Read back the checkerboard and verify.
+        for (j = 0; j < at25dfxxx_flash_info.block_info->block_size; j += BUF_SIZE) {
+            status = cyg_flash_read (base_addr + j, rbuf, BUF_SIZE, &err_addr);
+            if (status != FLASH_ERR_OK) {
+                diag_printf ("Flash read error : %s\n", cyg_flash_errmsg (status));
+                errors ++;
+            }
+            else if (memcmp (rbuf, wbuf, BUF_SIZE) != 0) {
+                diag_printf ("Flash read data corruption (0x%08X - 0x%08X).\n",
+                                base_addr + j, base_addr + j + BUF_SIZE - 1);
+                errors ++;
+            }
+        }
+
+        // Erase block.
+        status = cyg_flash_erase (base_addr, 1, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash erase error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+
+        // Set up buffer with inverse checkerboard.
+        for (j = 0; j < BUF_SIZE;) {
+           wbuf [j++] = 0xAA;
+           wbuf [j++] = 0x55;
+        }
+
+        // Write the checkerboard to the entire sector.
+        for (j = 0; j < at25dfxxx_flash_info.block_info->block_size; j += BUF_SIZE) {
+            status = cyg_flash_program (base_addr + j, wbuf, BUF_SIZE, &err_addr);
+            if (status != FLASH_ERR_OK) {
+                diag_printf ("Flash write error : %s\n", cyg_flash_errmsg (status));
+                errors ++;
+            }
+        }
+
+        // Read back the checkerboard and verify.
+        for (j = 0; j < at25dfxxx_flash_info.block_info->block_size; j += BUF_SIZE) {
+            status = cyg_flash_read (base_addr + j, rbuf, BUF_SIZE, &err_addr);
+            if (status != FLASH_ERR_OK) {
+                diag_printf ("Flash read error : %s\n", cyg_flash_errmsg (status));
+                errors ++;
+            }
+            else if (memcmp (rbuf, wbuf, BUF_SIZE) != 0) {
+                diag_printf ("Flash read data corruption (0x%08X - 0x%08X).\n",
+                                base_addr + j, base_addr + j + BUF_SIZE - 1);
+                errors ++;
+            }
+        }
+    }
+    return errors;
+}
+
+//-----------------------------------------------------------------------------
+// Write and verify counting sequence over all device.
+
+cyg_uint32 run_test_2
+  (void)
+{
+    int status;
+    cyg_uint32 i, j;
+    cyg_uint32 errors = 0;
+    cyg_flashaddr_t base_addr, err_addr;
+
+    diag_printf ("Test 2 - write and verify counting sequence.\n");
+
+    // Erase all flash sectors.
+    for (i = 0; i < at25dfxxx_flash_info.block_info->blocks; i++) {
+        base_addr =  at25dfxxx_flash_info.start +
+                           (i * at25dfxxx_flash_info.block_info->block_size);
+
+        // Erase block.
+        status = cyg_flash_erase (base_addr, 1, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash erase error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+    }
+
+    // Write counting sequence.
+    base_addr =  at25dfxxx_flash_info.start;
+    for (i = 0; i < (at25dfxxx_flash_info.end - at25dfxxx_flash_info.start) / 4;) {
+        for (j = 0; j < BUF_SIZE;) {
+            wbuf [j++] = (cyg_uint8) ((i >> 0) & 0xFF);
+            wbuf [j++] = (cyg_uint8) ((i >> 8) & 0xFF);
+            wbuf [j++] = (cyg_uint8) ((i >> 16) & 0xFF);
+            wbuf [j++] = (cyg_uint8) ((i >> 24) & 0xFF);
+            i++;
+        }
+        status = cyg_flash_program (base_addr, wbuf, BUF_SIZE, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash write error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+        base_addr += BUF_SIZE;
+    }
+
+    // Verify counting sequence.
+    base_addr = at25dfxxx_flash_info.start;
+    for (i = 0; i < (at25dfxxx_flash_info.end - at25dfxxx_flash_info.start) / 4;) {
+        for (j = 0; j < BUF_SIZE;) {
+            wbuf [j++] = (cyg_uint8) ((i >> 0) & 0xFF);
+            wbuf [j++] = (cyg_uint8) ((i >> 8) & 0xFF);
+            wbuf [j++] = (cyg_uint8) ((i >> 16) & 0xFF);
+            wbuf [j++] = (cyg_uint8) ((i >> 24) & 0xFF);
+            i++;
+        }
+        status = cyg_flash_read (base_addr, rbuf, BUF_SIZE, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash read error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+        else if (memcmp (rbuf, wbuf, BUF_SIZE) != 0) {
+            diag_printf ("Flash read data corruption (0x%08X - 0x%08X).\n",
+                                        base_addr, base_addr + BUF_SIZE - 1);
+            errors ++;
+        }
+        base_addr += BUF_SIZE;
+    }
+    return errors;
+}
+
+//-----------------------------------------------------------------------------
+// Perform non-aligned buffer read/write tests, spanning sector boundaries.
+
+cyg_uint32 run_test_3
+  (void)
+{
+    int status;
+    cyg_uint32 i, count;
+    cyg_uint32 errors = 0;
+    cyg_flashaddr_t base_addr, err_addr;
+
+    diag_printf ("Test 3 - test non-aligned writes and reads.\n");
+
+    // Fill the write buffer with a basic counting sequence.
+    count = 0;
+    for (i = 0; i < BUF_SIZE;) {
+        wbuf [i++] = (cyg_uint8) ((count >> 0) & 0xFF);
+        wbuf [i++] = (cyg_uint8) ((count >> 8) & 0xFF);
+        count++;
+    }
+
+    // Assuming 256 byte pages gives 256 possible alignments.
+    base_addr = at25dfxxx_flash_info.start + at25dfxxx_flash_info.block_info->block_size;
+    for (i = 1; i <= 256; i++) {
+
+        // Erase sectors either side of sector boundary.
+        status = cyg_flash_erase (base_addr - 1, 1, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash erase error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+        status = cyg_flash_erase (base_addr, 1, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash erase error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+
+        // Write data spanning sector boundary.
+        status = cyg_flash_program (base_addr - i, wbuf, BUF_SIZE, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash write error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+
+        // Verify data spanning sector boundary.
+        status = cyg_flash_read (base_addr - i, rbuf, BUF_SIZE, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash read error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+        else if (memcmp (rbuf, wbuf, BUF_SIZE) != 0) {
+            diag_printf ("Flash read data corruption (0x%08X - 0x%08X).\n",
+                                 base_addr - i, base_addr - i + BUF_SIZE - 1);
+            errors ++;
+        }
+
+        // Use next sector boundary for next test.
+        base_addr += at25dfxxx_flash_info.block_info->block_size;
+        if (base_addr >= at25dfxxx_flash_info.end)
+            base_addr = at25dfxxx_flash_info.start + at25dfxxx_flash_info.block_info->block_size;
+    }
+    return errors;
+}
+
+//-----------------------------------------------------------------------------
+// Run all M25Pxx SPI interface loopback tests.
+
+void run_tests
+    (void)
+{
+    cyg_uint32 errors = 0;
+
+    do_version();
+
+    diag_printf ("----\nChecking for AT25DFxxx compatible devices.\n");
+    cyg_flash_set_global_printf((cyg_flash_printf *)&diag_printf);
+    cyg_flash_init(NULL);
+
+    cyg_flash_get_info_addr(CYGNUM_DEVS_FLASH_SPI_AT25XXX_DEV0_MAP_ADDR,
+                 &at25dfxxx_flash_info);
+
+    // Check that the device is intialised.
+    if (at25dfxxx_flash_info.start == at25dfxxx_flash_info.end) {
+        diag_printf ("AT25DFxxx device not initialised.\n");
+        errors ++;
+        goto out;
+    }
+
+    // Run the tests.
+    errors += run_test_1 ();
+    errors += run_test_2 ();
+    errors += run_test_3 ();
+
+out:
+    diag_printf ("----\nTests complete - detected %d errors in total.\n", errors);
+    if (errors == 0)
+        CYG_TEST_PASS_FINISH ("AT25DFxxx driver tests ran OK.");
+    else
+        CYG_TEST_FAIL_FINISH ("AT25DFxxx driver test FAILED.");
+}
+
+//-----------------------------------------------------------------------------
+// User startup - tests are run in their own thread.
+
+void cyg_user_start
+    (void)
+{
+    CYG_TEST_INIT();
+    cyg_thread_create(
+        10,                                   // Arbitrary priority
+        (cyg_thread_entry_t*) run_tests,      // Thread entry point
+        0,                                    //
+        "test_thread",                        // Thread name
+        (cyg_uint8*) stack,                   // Stack
+        CYGNUM_HAL_STACK_SIZE_TYPICAL,        // Stack size
+        &thread_handle,                       // Thread handle
+        &thread_data                          // Thread data structure
+    );
+    cyg_thread_resume(thread_handle);
+    cyg_scheduler_start();
+}
+
+//=============================================================================
diff --git a/packages/devs/flash/spi/m25pxx/current/ChangeLog b/packages/devs/flash/spi/m25pxx/current/ChangeLog
--- a/packages/devs/flash/spi/m25pxx/current/ChangeLog
+++ b/packages/devs/flash/spi/m25pxx/current/ChangeLog
@@ -1,3 +1,7 @@
+2011-05-25  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/flash_m25pxx.cdl: fix active_if goal expression.
+
 2009-02-20  Jonathan Larmour  <jifl@eCosCentric.com>
 
 	* test/m25pxx_test.c (cyg_user_start): Call cyg_flash_init() with
diff --git a/packages/devs/flash/spi/m25pxx/current/cdl/flash_m25pxx.cdl b/packages/devs/flash/spi/m25pxx/current/cdl/flash_m25pxx.cdl
--- a/packages/devs/flash/spi/m25pxx/current/cdl/flash_m25pxx.cdl
+++ b/packages/devs/flash/spi/m25pxx/current/cdl/flash_m25pxx.cdl
@@ -50,7 +50,7 @@
 cdl_package CYGPKG_DEVS_FLASH_SPI_M25PXX {
     display	"M25PXX flash memory support"
     parent	CYGPKG_IO_FLASH
-    active_if	CYGPKG_IO_FLASH CYGPKG_IO_SPI
+    active_if	{ CYGPKG_IO_FLASH && CYGPKG_IO_SPI }
     implements	CYGHWR_IO_FLASH_DEVICE
     implements  CYGHWR_IO_FLASH_INDIRECT_READS 
     include_dir	cyg/io
diff --git a/packages/devs/flash/spi/sst25xx/current/ChangeLog b/packages/devs/flash/spi/sst25xx/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/spi/sst25xx/current/ChangeLog
@@ -0,0 +1,38 @@
+2012-02-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+    * cdl/flash_sst25xx.cdl
+    * src/sst25xx.c:
+    * tests/flash_sst25xx_test.c: New file
+    Added tests  [Bugzilla 1001450]
+
+2011-04-13  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* cdl/sst25xx.cdl:
+	* include/sst25xx.h:
+	* src/sst25xx.c:
+	New package - SPI flash driver for Silicon Storage Technology,
+	SST25xx devices.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/flash/spi/sst25xx/current/cdl/flash_sst25xx.cdl b/packages/devs/flash/spi/sst25xx/current/cdl/flash_sst25xx.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/spi/sst25xx/current/cdl/flash_sst25xx.cdl
@@ -0,0 +1,145 @@
+##=============================================================================
+##
+##      flash_sst25xx.cdl
+##
+##      SST25xx SPI flash driver configuration options.
+##
+##=============================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##=============================================================================
+#######DESCRIPTIONBEGIN####
+##
+##
+## Author(s):   ccoutand, updated for Silicon Storage Technology
+##              SST25xx flash
+## Original(s): Chris Holgate
+## Date:        2011-04-25
+## Purpose:     Configure SST25xx SPI flash driver.
+##
+######DESCRIPTIONEND####
+##
+##=============================================================================
+
+cdl_package CYGPKG_DEVS_FLASH_SPI_SST25XX {
+    display      "Silicon Storage Technology SST25xx flash memory support"
+    parent        CYGPKG_IO_FLASH
+    active_if     { CYGPKG_IO_FLASH && CYGPKG_IO_SPI }
+    implements    CYGHWR_IO_FLASH_DEVICE
+    implements    CYGHWR_IO_FLASH_BLOCK_LOCKING
+    implements    CYGHWR_IO_FLASH_INDIRECT_READS
+
+    include_dir   cyg/io
+    compile       -library=libextras.a sst25xx.c
+
+    description   "
+        Flash memory support for the Silicon Storage Technology SST25xx
+        SPI flash devices and compatibles.  This driver implements the
+        V2 flash driver API"
+
+    cdl_interface CYGHWR_DEVS_FLASH_SPI_SST25XX_DEVICE {
+        display     "Hardware SST25xx FLASH device drivers"
+        description "
+            This calculated option gives the number of SST25xx flash
+            devices on the current platform."
+    }
+
+    cdl_option CYGPKG_DEVS_FLASH_SPI_SST25XX_SUPPORT_JEDECID {
+        display       "Device supports JEDEC ID"
+        flavor        bool
+        default_value 0
+
+        description   "
+            Allow probing of the SPI flash(s) on the bus using the
+            JededID Opcode. Some device do not support this command
+            (SST25VF010A, SST25VF512A etc.)."
+    }
+
+    cdl_option CYGPKG_DEVS_FLASH_SPI_SST25XX_BLOCK_SIZE {
+        display       "Flash block size in bytes"
+        flavor        data
+        legal_values  { 4096 32768 65536 }
+        default_value { 4096 }
+
+        description   "
+            Most SST25xx SPI flash devices can use block size of 4KB,
+            32K or 64KB. This option allow users to select which flash
+            geometry to use. For device such as AT25F512 not supporting
+            64K, selecting a wrong geometry will force the driver to
+            abort the initialization process."
+    }
+
+    cdl_option CYGPKG_DEVS_FLASH_SPI_SST25XX_READ_MODE {
+        display       "Flash read transaction"
+        flavor        data
+        legal_values  { "FAST" "SLOW" }
+        default_value { "FAST" }
+
+        description   "
+            The SST25xx SPI flash devices differentiate read access
+            according to the throughput required for this operation. The
+            driver allows both fast and slow reading operation. The
+            option requires the physical layer to use the appropriate
+            SPI bus clock frequency."
+    }
+
+    cdl_option CYGNUM_DEVS_FLASH_SPI_SST25XX_READ_BLOCK_SIZE {
+        display       "Maximum read block size"
+        flavor        data
+        default_value 0
+
+        description   "
+            In theory it is possible to read back the entire flash
+            contents using a single SPI transaction.  However, some SPI
+            bus drivers have a maximum transaction size - for example
+            transactions may be limited to the length of a DMA bounce
+            buffer.  Setting this option to a non-zero value specifies
+            the maximum SPI bus transfer size which will be used when
+            reading back data.  Read requests for areas larger than
+            this block size will automatically be split into a series
+            of smaller SPI bus transactions."
+    }
+    
+    cdl_component CYGPKG_DEVS_FLASH_SPI_SST25XX_TESTS {
+        display         "SST25xx tests"
+        flavor          data
+        active_if      CYGPKG_KERNEL
+        active_if      CYGPKG_IO_SPI
+        active_if       { CYGHWR_DEVS_FLASH_SPI_SST25XX_DEVICE >= 1 }
+        no_define
+        calculated      { "tests/flash_sst25xx_test.c" }
+        description     "
+            This option specifies the set of tests for sst25 driver."
+    }
+}
+
+# EOF flash_sst25xx.cdl
diff --git a/packages/devs/flash/spi/sst25xx/current/include/sst25xx.h b/packages/devs/flash/spi/sst25xx/current/include/sst25xx.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/spi/sst25xx/current/include/sst25xx.h
@@ -0,0 +1,83 @@
+#ifndef CYGONCE_DEVS_FLASH_SPI_SST25XX_H
+#define CYGONCE_DEVS_FLASH_SPI_SST25XX_H
+
+//=============================================================================
+//
+//      sst25xx.h
+//
+//      SPI flash driver for Silicon Storage Technology SST25xx devices
+//      and compatibles.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand, updated for Silicon Storage Technology SST25xx
+//              flash
+// Original(s): Chris Holgate
+// Purpose:     Silicon Storage Technology SST25xxx SPI flash driver
+//              implementation
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+// Required data structures.
+#include <cyg/io/flash_dev.h>
+
+// Exported handle on the driver function table.
+externC struct cyg_flash_dev_funs cyg_devs_flash_spi_sst25xx_funs;
+
+//-----------------------------------------------------------------------------
+// Macro used to generate a flash device object with the default SST25XX
+// settings.  Even though the block info data structure is declared here, the
+// details are not filled in until the device type is inferred during
+// initialization.  This also applies to the 'end' field which is calculated
+// using the _start_ address and the inferred size of the device.
+// _name_   is the root name of the instantiated data structures.
+// _start_  is the base address of the device - for SPI based devices this can
+//          have an arbitrary value, since the device is not memory mapped.
+// _spidev_ is a pointer to a SPI device object of type cyg_spi_device.  This
+//          is not typechecked during compilation so be careful!
+
+#define CYG_DEVS_FLASH_SPI_SST25XX_DRIVER(_name_, _start_, _spidev_)    \
+struct cyg_flash_block_info _name_ ##_block_info;                       \
+CYG_FLASH_DRIVER(_name_, &cyg_devs_flash_spi_sst25xx_funs, 0,           \
+    _start_, _start_, 1, & _name_ ##_block_info, (void*) _spidev_)
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_DEVS_FLASH_SPI_SST25XX_H
+// EOF sst25xx.h
diff --git a/packages/devs/flash/spi/sst25xx/current/src/sst25xx.c b/packages/devs/flash/spi/sst25xx/current/src/sst25xx.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/spi/sst25xx/current/src/sst25xx.c
@@ -0,0 +1,709 @@
+//=============================================================================
+//
+//      sst25xx.c
+//
+//      SPI flash driver for Silicon Storage Technology SST25xx devices
+//      and compatibles.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand, updated for Silicon Storage Technology SST25xx
+//              flash
+// Original(s): Chris Holgate
+// Date:        2011-04-25
+// Purpose:     Silicon Storage Technology SST25xx SPI flash driver
+//              implementation
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_diag.h>
+
+#include <cyg/io/spi.h>
+#include <cyg/io/flash.h>
+#include <cyg/io/flash_dev.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+
+#include <pkgconf/devs_flash_spi_sst25xx.h>
+
+#include <string.h>
+
+//-----------------------------------------------------------------------------
+// Enable polled SPI operation for non-kernel builds.
+
+#ifdef CYGPKG_KERNEL
+# define SST25XX_POLLED false
+#else
+# define SST25XX_POLLED true
+#endif
+
+//-----------------------------------------------------------------------------
+// Implement delay functions for kernel and non-kernel builds.  The kernel
+// build assumes that the API calls are made in the thread context.
+
+#ifdef CYGPKG_KERNEL
+#define SST25XX_DELAY_MS(_msdelay_) cyg_thread_delay \
+    (1 + ((1000 * _msdelay_ * CYGNUM_HAL_RTC_DENOMINATOR) / (CYGNUM_HAL_RTC_NUMERATOR / 1000)))
+
+#else
+#define SST25XX_DELAY_MS(_msdelay_) CYGACC_CALL_IF_DELAY_US (_msdelay_ * 1000)
+#endif
+
+// Byte / word programming takes 10 us max
+#define SST25XX_WAIT_CHIP_READY( dev )                  \
+{                                                       \
+    cyg_uint8 dev_status;                               \
+    do {                                                \
+        HAL_DELAY_US (10);                              \
+        dev_status = sst25xx_spi_rdsr ( dev );          \
+    } while ( dev_status & SST25XX_STATUS_BSY );        \
+}
+
+//-----------------------------------------------------------------------------
+// Maintenance and debug macros.
+
+#define ASSERT_SST25XX(_test_, _msg_) CYG_ASSERT(_test_, "FAIL (SST25XX) : " _msg_)
+#define TRACE_SST25XX(_msg_, _args_...) if (dev->pf) dev->pf ("SST25XX : " _msg_, ##_args_)
+
+//=============================================================================
+// Define SST25VFxxx SPI protocol.
+//=============================================================================
+
+typedef enum sst25xx_cmd {
+    SST25XX_CMD_WREN   = 0x06,     // Write enable.
+    SST25XX_CMD_WDRI   = 0x04,     // Write disable.
+    SST25XX_CMD_RDJID  = 0x9F,     // Read JEDEC identification.
+    SST25XX_CMD_RDID   = 0x90,     // Read Manufacturer / Device identification.
+    SST25XX_CMD_RDSR   = 0x05,     // Read status register.
+    SST25XX_CMD_WRSR   = 0x01,     // Write status register.
+    SST25XX_CMD_READ   = 0x03,     // Read data
+    SST25XX_CMD_FREAD  = 0x0B,     // Read data (fast).
+    SST25XX_CMD_BP     = 0x02,     // Byte program.
+    SST25XX_CMD_AAI    = 0xAD,     // Word program (with address increment).
+    SST25XX_CMD_SE_4K  = 0x20,     // 4K sector erase.
+    SST25XX_CMD_SE_32K = 0x52,     // 32K sector erase.
+    SST25XX_CMD_SE_64K = 0xD8,     // 64K sector erase.
+    SST25XX_CMD_BE     = 0xC7,     // Chip erase.
+} sst25xx_cmd;
+
+// Status register bitfields.
+#define SST25XX_STATUS_BSY  0x01   /* Operation in progress. */
+#define SST25XX_STATUS_WEL  0x02   /* Write enable latch. */
+#define SST25XX_STATUS_BP0  0x04   /* Block Write Protect 0. */
+#define SST25XX_STATUS_BP1  0x08   /* Block Write Protect 1. */
+#define SST25XX_STATUS_BP2  0x10   /* Block Write Protect 2. */
+#define SST25XX_STATUS_BP3  0x20   /* Block Write Protect 3. */
+#define SST25XX_STATUS_AAI  0x40   /* Auto Address Increment Programming Status */
+#define SST25XX_STATUS_SPRL 0x80   /* Sector Protect Register Bit Lock. */
+
+#define SST25XX_LOCK_BITS   ( SST25XX_STATUS_BP0 | SST25XX_STATUS_BP1 | \
+                              SST25XX_STATUS_BP2 | SST25XX_STATUS_BP3 )
+
+#define SST25XX_MEMORY_ID   0x25
+
+// A few helper constants
+#ifndef SZ_1K
+# define SZ_1K           0x00000400
+# define SZ_2K           0x00000800
+# define SZ_4K           0x00001000
+# define SZ_8K           0x00002000
+# define SZ_16K          0x00004000
+# define SZ_32K          0x00008000
+# define SZ_64K          0x00010000
+#endif
+
+// Select read OPCODE
+#if defined(CYGPKG_DEVS_FLASH_SPI_SST25XX_READ_MODE_SLOW)
+# define SST25XX_CMD_READ_LEN 4
+# define SST25XX_CMD_READ_OPCODE SST25XX_CMD_READ
+#elif defined(CYGPKG_DEVS_FLASH_SPI_SST25XX_READ_MODE_FAST)
+# define SST25XX_CMD_READ_LEN 5
+# define SST25XX_CMD_READ_OPCODE SST25XX_CMD_FREAD
+#endif
+
+// Select sector size
+#if CYGPKG_DEVS_FLASH_SPI_SST25XX_BLOCK_SIZE == SZ_64K
+# define SST25XX_CMD_SE SST25XX_CMD_SE_64K
+#elif CYGPKG_DEVS_FLASH_SPI_SST25XX_BLOCK_SIZE == SZ_32K
+# define SST25XX_CMD_SE SST25XX_CMD_SE_32K
+#elif CYGPKG_DEVS_FLASH_SPI_SST25XX_BLOCK_SIZE == SZ_4K
+# define SST25XX_CMD_SE SST25XX_CMD_SE_4K
+#endif
+
+//=============================================================================
+// Array containing a list of supported devices.  This allows the device
+// parameters to be dynamically detected on initialization.
+//=============================================================================
+
+typedef struct sst25xx_params {
+    cyg_uint16 sector_count[4];       // Number of sectors on device.
+    cyg_uint32 sector_size[4];        // Supported sector size(s) in Byte
+    cyg_uint32 jedec_id;              // 3 byte JEDEC identifier for this device.
+} sst25xx_params;
+
+
+static const sst25xx_params sst25xx_supported_devices [] = {
+    // Some Silicon Storage Technology parts.
+    // Note1: Some part do not support the Read Jedec ID Opcode, instead,
+    // the Read ID Opcode is used which is backward compatible with all
+    // parts
+    // Note2: Not all parts can support sector size of 4, 32 or 64 KBytes
+    { // Support for SST 64 MBit devices (SST25VF064C).
+        sector_count        : {2048, 256, 128, 0},
+        sector_size         : {SZ_4K, SZ_32K, SZ_64K, 0},
+        jedec_id            : 0x00bf254B
+    },
+    { // Support for SST 32 MBit devices (SST25VF032B).
+        sector_count        : {1024, 128, 64, 0},
+        sector_size         : {SZ_4K, SZ_32K, SZ_64K, 0},
+        jedec_id            : 0x00bf254a
+    },
+    { // Support for SST 16 MBit devices (SST25VF016B).
+        sector_count        : {512, 64, 32, 0},
+        sector_size         : {SZ_4K, SZ_32K, SZ_64K, 0},
+        jedec_id            : 0x00bf2541
+    },
+    { // Support for SST 8 MBit devices (SST25VF080B).
+        sector_count        : {256, 32, 16, 0},
+        sector_size         : {SZ_4K, SZ_32K, SZ_64K, 0},
+        jedec_id            : 0x00bf258E
+    },
+    { // Support for SST 4 MBit devices (SST25VF040B).
+        sector_count        : {128, 16, 8, 0},
+        sector_size         : {SZ_4K, SZ_32K, SZ_64K, 0},
+        jedec_id            : 0x00bf258D
+    },
+    { // Support for SST 2 MBit devices (SST25VF020B).
+        sector_count        : {64, 8, 4, 0},
+        sector_size         : {SZ_4K, SZ_32K, SZ_64K, 0},
+        jedec_id            : 0x00bf258C
+    },
+    { // Support for SST 2 MBit devices (SST25LF020A).
+        sector_count        : {64, 8, 0},
+        sector_size         : {SZ_4K, SZ_32K, 0},
+        // Constructed Jedec ID from ID (0xBF43)
+        jedec_id            : 0x00bf2543
+    },
+    { // Support for SST 1 MBit devices (SST25VF010A).
+        sector_count        : {32, 4, 0},
+        sector_size         : {SZ_4K, SZ_32K, 0},
+        // Constructed Jedec ID from ID (0xBF49)
+        jedec_id            : 0x00bf2549
+    },
+    { // Support for SST 512 KBit devices (SST25VF512A).
+        sector_count        : {16, 2, 0},
+        sector_size         : {SZ_4K, SZ_32K, 0},
+        // Constructed Jedec ID from ID (0xBF48)
+        jedec_id            : 0x00bf2548
+    },
+    { // Support for SST 512 KBit devices (SST25WF512).
+        sector_count        : {16, 2, 0},
+        sector_size         : {SZ_4K, SZ_32K, 0},
+        jedec_id            : 0x00bf2501
+    },
+    { // Support for SST 1 MBit devices (SST25WF010).
+        sector_count        : {32, 4, 0},
+        sector_size         : {SZ_4K, SZ_32K, 0},
+        jedec_id            : 0x00bf2502
+    },
+    { // Support for SST 2 MBit devices (SST25WF020).
+        sector_count        : {64, 8, 4},
+        sector_size         : {SZ_4K, SZ_32K, SZ_64K, 0},
+        jedec_id            : 0x00bf2503
+    },
+    { // Support for SST 4 MBit devices (SST25WF040).
+        sector_count        : {128, 16, 8, 0},
+        sector_size         : {SZ_4K, SZ_32K, SZ_64K, 0},
+        jedec_id            : 0x00bf2504
+    },
+    { // Support for SST 8 MBit devices (SST25WF080).
+        sector_count        : {256, 32, 16, 0},
+        sector_size         : {SZ_4K, SZ_32K, SZ_64K, 0},
+        jedec_id            : 0x00bf2505
+    },
+    { // Null terminating entry.
+        sector_count        : {0},
+        sector_size         : {0},
+        jedec_id            : 0
+    }
+};
+
+//=============================================================================
+// Utility functions for address calculations.
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Strips out any device address offset to give address within device.
+
+static cyg_bool
+sst25xx_to_local_addr(struct cyg_flash_dev *dev, cyg_flashaddr_t * addr)
+{
+    cyg_bool        retval = false;
+
+    // Range check address before modifying it.
+    if ((*addr >= dev->start) && (*addr <= dev->end)) {
+        *addr -= dev->start;
+        retval = true;
+    }
+    return retval;
+}
+
+//=============================================================================
+// Wrapper functions for various SPI transactions.
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Read back the 3-byte JEDEC ID, returning it as a 32-bit integer.
+// This function is called during flash initialization, which can often be
+// called from the startup/idle thread.  This means that we should always use
+// SPI polled mode in order to prevent the thread from attempting to sleep.
+
+#if defined(CYGPKG_DEVS_FLASH_SPI_SST25XX_SUPPORT_JEDECID)
+
+static inline cyg_uint32
+sst25xx_spi_rdid(struct cyg_flash_dev *dev)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    const cyg_uint8 tx_buf[4] = { SST25XX_CMD_RDJID, 0x0, 0x0, 0x0 };
+    cyg_uint8       rx_buf[4];
+    cyg_uint32      retval = 0;
+
+    // Carry out SPI transfer.
+    cyg_spi_transfer(spi_device, true, 4, tx_buf, rx_buf);
+
+    // Convert 3-byte ID to 32-bit integer.
+    retval |= ((cyg_uint32)rx_buf[1]) << 16;
+    retval |= ((cyg_uint32)rx_buf[2]) << 8;
+    retval |= ((cyg_uint32)rx_buf[3]);
+
+    return retval;
+}
+
+#else
+
+static inline cyg_uint32
+sst25xx_spi_rdid(struct cyg_flash_dev *dev)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    const cyg_uint8 tx_buf[6] = { SST25XX_CMD_RDID, 0x0, 0x0, 0x0, 0x0, 0x0 };
+    cyg_uint8       rx_buf[6];
+    cyg_uint32      retval = 0;
+
+    // Carry out SPI transfer.
+    cyg_spi_transfer(spi_device, true, 6, tx_buf, rx_buf);
+
+    // Convert 2-byte ID to 32-bit Jedec ID.
+    retval |= ((cyg_uint32)rx_buf[4]) << 16;
+    retval |= (SST25XX_MEMORY_ID << 8);
+    retval |= ((cyg_uint32)rx_buf[5]);
+
+    return retval;
+}
+
+#endif
+
+//-----------------------------------------------------------------------------
+// Send write enable command.
+
+static inline void
+sst25xx_spi_wren(struct cyg_flash_dev *dev)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    const cyg_uint8 tx_buf[1] = { SST25XX_CMD_WREN };
+    cyg_spi_transfer(spi_device, SST25XX_POLLED, 1, tx_buf, NULL);
+}
+
+//-----------------------------------------------------------------------------
+// Send write disable command.
+
+static inline void
+sst25xx_spi_wrdis(struct cyg_flash_dev *dev)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    const cyg_uint8 tx_buf[1] = { SST25XX_CMD_WDRI };
+    cyg_spi_transfer(spi_device, SST25XX_POLLED, 1, tx_buf, NULL);
+}
+
+//-----------------------------------------------------------------------------
+// Send sector erase command.  The address parameter is a device local address
+// within the sector to be erased.
+
+static inline void
+sst25xx_spi_se(struct cyg_flash_dev *dev, cyg_flashaddr_t addr)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    cyg_uint8       tx_buf[4] = { SST25XX_CMD_SE,
+        (cyg_uint8)(addr >> 16), (cyg_uint8)(addr >> 8), (cyg_uint8)(addr)
+    };
+    cyg_spi_transfer(spi_device, SST25XX_POLLED, 4, tx_buf, NULL);
+}
+
+//-----------------------------------------------------------------------------
+// Read and return the 8-bit device status register.
+
+static inline cyg_uint8
+sst25xx_spi_rdsr(struct cyg_flash_dev *dev)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    const cyg_uint8 tx_buf[2] = { SST25XX_CMD_RDSR, 0 };
+    cyg_uint8       rx_buf[2];
+
+    // Carry out SPI transfer and return the status byte.
+    cyg_spi_transfer(spi_device, SST25XX_POLLED, 2, tx_buf, rx_buf);
+
+    return rx_buf[1];
+}
+
+//-----------------------------------------------------------------------------
+// Program a single byte.
+
+static inline void
+sst25xx_spi_pbyte(struct cyg_flash_dev *dev, cyg_flashaddr_t addr,
+                  cyg_uint8 *wbuf)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    const cyg_uint8 tx_buf[4] = { SST25XX_CMD_BP,
+        (cyg_uint8)(addr >> 16), (cyg_uint8)(addr >> 8), (cyg_uint8)(addr)
+    };
+
+    // Implement the program operation as a multistage SPI transaction.
+    cyg_spi_transaction_begin(spi_device);
+    cyg_spi_transaction_transfer(spi_device, SST25XX_POLLED, 4, tx_buf, NULL,
+                                 false);
+    cyg_spi_transaction_transfer(spi_device, SST25XX_POLLED, 1, wbuf, NULL,
+                                 false);
+    cyg_spi_transaction_end(spi_device);
+}
+
+//-----------------------------------------------------------------------------
+// Program word with automatic address increment
+
+static inline void
+sst25xx_spi_pword(struct cyg_flash_dev *dev, cyg_flashaddr_t addr,
+                  cyg_uint8 *wbuf, cyg_bool first)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    const cyg_uint8 tx_buf[4] = { SST25XX_CMD_AAI,
+        (cyg_uint8)(addr >> 16), (cyg_uint8)(addr >> 8), (cyg_uint8)(addr)
+    };
+
+    // Implement the program operation as a multistage SPI transaction.
+    cyg_spi_transaction_begin(spi_device);
+    // Only convey the address with the first transaction. In the following
+    // transfers, address will be incremented internally by the SPI flash
+    if (first == true) {
+        cyg_spi_transaction_transfer(spi_device, SST25XX_POLLED, 4, tx_buf,
+                                     NULL, false);
+    } else {
+        cyg_spi_transaction_transfer(spi_device, SST25XX_POLLED, 1, tx_buf,
+                                     NULL, false);
+    }
+    cyg_spi_transaction_transfer(spi_device, SST25XX_POLLED, 2, wbuf, NULL,
+                                 false);
+    cyg_spi_transaction_end(spi_device);
+}
+
+//-----------------------------------------------------------------------------
+// Implement reads to the specified buffer.
+
+static inline void
+sst25xx_spi_read(struct cyg_flash_dev *dev, cyg_flashaddr_t addr,
+                 cyg_uint8 *rbuf, cyg_uint32 rbuf_len)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    const cyg_uint8 tx_buf[5] = { SST25XX_CMD_READ_OPCODE,
+        (cyg_uint8)(addr >> 16), (cyg_uint8)(addr >> 8), (cyg_uint8)(addr), 0
+    };
+
+    // Implement the read operation as a multistage SPI transaction.
+    cyg_spi_transaction_begin(spi_device);
+    cyg_spi_transaction_transfer(spi_device, SST25XX_POLLED,
+                                 SST25XX_CMD_READ_LEN, tx_buf, NULL, false);
+    cyg_spi_transaction_transfer(spi_device, SST25XX_POLLED, rbuf_len, NULL,
+                                 rbuf, false);
+    cyg_spi_transaction_end(spi_device);
+}
+
+
+//=============================================================================
+// Standard Flash device API.  All the following functions assume that a valid
+// SPI device handle is passed in the 'priv' reference of the flash device
+// data structure.
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Initialize the SPI flash, reading back the flash parameters.
+
+static int
+sst25xx_init(struct cyg_flash_dev *dev)
+{
+    sst25xx_params *dev_params = (sst25xx_params *) sst25xx_supported_devices;
+    cyg_uint32      device_id;
+    cyg_uint8       i = 0;
+    int             retval = FLASH_ERR_INVALID;
+
+    // Find the device in the supported devices list.
+    device_id = sst25xx_spi_rdid(dev);
+
+    while ((dev_params->jedec_id != 0) && (dev_params->jedec_id != device_id)) {
+        dev_params++;
+    }
+
+    // Found supported device - update device parameters.  SST25XX devices have
+    // a uniform sector distribution, so only 1 block info record is required.
+    if (dev_params->jedec_id != 0) {
+
+        // Find out is the wanted sector size is supported by the device
+        while ((dev_params->sector_size[i] !=
+                CYGPKG_DEVS_FLASH_SPI_SST25XX_BLOCK_SIZE)
+               && (dev_params->sector_size[i] != 0))
+            i++;
+
+        if (dev_params->sector_size[i] !=
+            CYGPKG_DEVS_FLASH_SPI_SST25XX_BLOCK_SIZE) {
+            TRACE_SST25XX("Init device with JEDEC ID 0x%06X\n",
+                          dev_params->jedec_id);
+            TRACE_SST25XX("SPI Flash Error, not supporting %dK sector size\n",
+                          CYGPKG_DEVS_FLASH_SPI_SST25XX_BLOCK_SIZE);
+            return retval;
+        }
+
+        ASSERT_SST25XX(dev->num_block_infos == 1,
+                       "Only 1 block info record required.");
+        ASSERT_SST25XX(dev->block_info != NULL,
+                       "Null pointer to block info record.");
+
+        if ((dev->num_block_infos == 1) && (dev->block_info != NULL)) {
+            TRACE_SST25XX("Init device with JEDEC ID 0x%06X.\n", device_id);
+            dev->end =
+                dev->start +
+                ((cyg_flashaddr_t) dev_params->sector_size[i] *
+                 (cyg_flashaddr_t) (dev_params->sector_count[i])) - 1;
+
+            // Strictly speaking the block info fields are 'read only'.
+            // However, we have a legitimate reason for updating the contents
+            // here and can cast away the const.
+            ((cyg_flash_block_info_t *) dev->block_info)->block_size =
+                (size_t)(dev_params->sector_size[i]);
+            ((cyg_flash_block_info_t *) dev->block_info)->blocks =
+                (cyg_uint32)(dev_params->sector_count[i]);
+
+            retval = FLASH_ERR_OK;
+        }
+
+    }
+    return retval;
+}
+
+//-----------------------------------------------------------------------------
+// Erase a single sector of the flash.
+
+static int
+sst25xx_erase_block(struct cyg_flash_dev *dev, cyg_flashaddr_t block_base)
+{
+    cyg_flashaddr_t local_base = block_base;
+    int             retval = FLASH_ERR_INVALID;
+    cyg_uint8       dev_status;
+
+    // Fix up the block address and send the sector erase command.
+    if (sst25xx_to_local_addr(dev, &local_base)) {
+        sst25xx_spi_wren(dev);
+        sst25xx_spi_se(dev, local_base);
+
+        // Spin waiting for the erase to complete. Erasing takes around
+        // 25 ms
+        do {
+            SST25XX_DELAY_MS(10);
+            dev_status = sst25xx_spi_rdsr(dev);
+        } while (dev_status & SST25XX_STATUS_BSY);
+
+        retval = FLASH_ERR_OK;
+    }
+    return retval;
+}
+
+//-----------------------------------------------------------------------------
+// Program an arbitrary number of pages into flash and verify written data.
+
+static int
+sst25xx_program(struct cyg_flash_dev *dev, cyg_flashaddr_t base,
+                const void *data, size_t len)
+{
+    cyg_uint8      *tx_ptr = (cyg_uint8 *)data;
+    cyg_flashaddr_t local_base = base;
+    cyg_flashaddr_t end;
+    size_t          tx_len = len;
+    cyg_bool        start_wxfer = true;
+    int             retval = FLASH_ERR_OK;
+
+    // Fix up the block address.
+    if (!sst25xx_to_local_addr(dev, &local_base)) {
+        retval = FLASH_ERR_INVALID;
+        goto out;
+    }
+    end = local_base + len - 1;
+
+    // Start with a byte programming if the destination is not
+    // 16 bits aligned
+    if (local_base & (cyg_flashaddr_t) 0x1) {
+        sst25xx_spi_wren(dev);
+        sst25xx_spi_pbyte(dev, local_base, tx_ptr);
+        SST25XX_WAIT_CHIP_READY(dev);
+        sst25xx_spi_wrdis(dev);
+        tx_ptr += 1;
+        tx_len -= 1;
+        local_base = local_base + 1;
+    }
+    // Write word(s)
+    if (tx_len > 1) {
+        sst25xx_spi_wren(dev);
+        while (tx_len > 1) {
+            sst25xx_spi_pword(dev, local_base, tx_ptr, start_wxfer);
+            tx_ptr += 2;
+            tx_len -= 2;
+            start_wxfer = false;
+            SST25XX_WAIT_CHIP_READY(dev);
+        }
+        sst25xx_spi_wrdis(dev);
+    }
+    // Write last byte
+    if (tx_len) {
+        sst25xx_spi_wren(dev);
+        sst25xx_spi_pbyte(dev, end, tx_ptr);
+        SST25XX_WAIT_CHIP_READY(dev);
+        sst25xx_spi_wrdis(dev);
+    }
+
+out:
+    return retval;
+}
+
+//-----------------------------------------------------------------------------
+// Read back an arbitrary amount of data from flash.
+
+static int
+sst25xx_read(struct cyg_flash_dev *dev, const cyg_flashaddr_t base,
+             void *data, size_t len)
+{
+    cyg_flashaddr_t local_base = base;
+    int             retval = FLASH_ERR_INVALID;
+    cyg_uint8      *rx_ptr = (cyg_uint8 *)data;
+    cyg_uint32      rx_bytes_left = (cyg_uint32)len;
+    cyg_uint32      rx_bytes;
+
+    // Determine the maximum transfer size to use.
+    cyg_uint32      rx_block_size =
+        (CYGNUM_DEVS_FLASH_SPI_SST25XX_READ_BLOCK_SIZE ==
+         0) ? 0xFFFFFFFF : CYGNUM_DEVS_FLASH_SPI_SST25XX_READ_BLOCK_SIZE;
+
+    // Fix up the block address and fill the read buffer.
+    if (sst25xx_to_local_addr(dev, &local_base)) {
+        while (rx_bytes_left) {
+            rx_bytes =
+                (rx_bytes_left <
+                 rx_block_size) ? rx_bytes_left : rx_block_size;
+            sst25xx_spi_read(dev, local_base, rx_ptr, rx_bytes);
+
+            // Update counters and data pointers for next read block.
+            rx_bytes_left -= rx_bytes;
+            rx_ptr += rx_bytes;
+            local_base += rx_bytes;
+        }
+        retval = FLASH_ERR_OK;
+    }
+    return retval;
+}
+
+//-----------------------------------------------------------------------------
+// Lock device
+
+static int
+sst25xx_lock(struct cyg_flash_dev *dev, cyg_flashaddr_t base)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    cyg_flashaddr_t local_base = base;
+    int             retval = FLASH_ERR_INVALID;
+    const cyg_uint8 tx_buf[2] = { SST25XX_CMD_WRSR, SST25XX_LOCK_BITS };
+
+    if (sst25xx_to_local_addr(dev, &local_base)) {
+        sst25xx_spi_wren(dev);
+        cyg_spi_transfer(spi_device, SST25XX_POLLED, 2, tx_buf, NULL);
+        retval = FLASH_ERR_OK;
+    }
+    return retval;
+}
+
+//-----------------------------------------------------------------------------
+// Unlock device
+
+static int
+sst25xx_unlock(struct cyg_flash_dev *dev, cyg_flashaddr_t base)
+{
+    cyg_spi_device *spi_device = (cyg_spi_device *) dev->priv;
+    cyg_flashaddr_t local_base = base;
+    int             retval = FLASH_ERR_INVALID;
+    const cyg_uint8 tx_buf[2] = { SST25XX_CMD_WRSR, 0x0 };
+
+    if (sst25xx_to_local_addr(dev, &local_base)) {
+        sst25xx_spi_wren(dev);
+        cyg_spi_transfer(spi_device, SST25XX_POLLED, 2, tx_buf, NULL);
+        retval = FLASH_ERR_OK;
+    }
+    return retval;
+}
+
+//=============================================================================
+// Fill in the driver data structures.
+//=============================================================================
+
+CYG_FLASH_FUNS (
+    cyg_devs_flash_spi_sst25xx_funs, // Exported name of function pointers.
+    sst25xx_init,                    // Flash initialization.
+    cyg_flash_devfn_query_nop,       // Query operations not supported.
+    sst25xx_erase_block,             // Sector erase.
+    sst25xx_program,                 // Program multiple pages.
+    sst25xx_read,                    // Read arbitrary amount of data.
+    sst25xx_lock,                    // Locking (lock the whole device).
+    sst25xx_unlock
+);
+
+//-----------------------------------------------------------------------------
+// EOF sst25xx.c
diff --git a/packages/devs/flash/spi/sst25xx/current/tests/flash_sst25xx_test.c b/packages/devs/flash/spi/sst25xx/current/tests/flash_sst25xx_test.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/flash/spi/sst25xx/current/tests/flash_sst25xx_test.c
@@ -0,0 +1,430 @@
+//=============================================================================
+//
+//      flash_sst25xx_test.c
+//
+//      SPI flash driver tests for SST25XX SPI FLASH
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak, updated for SST25xx flash
+// Original(s): Chris Holgate, Christian Coutand
+// Date:        2011-04-25
+// Purpose:     SST25xx SPI flash driver stress tests.
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/system.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/testcase.h>           // Test macros
+#include <cyg/infra/cyg_ass.h>            // Assertion macros
+#include <cyg/infra/diag.h>               // Diagnostic output
+
+#include <cyg/hal/hal_arch.h>             // CYGNUM_HAL_STACK_SIZE_TYPICAL
+#include <cyg/hal/hal_if.h>
+#include <cyg/kernel/kapi.h>
+
+#include <cyg/io/spi.h>
+#include <cyg/io/flash.h>
+#include <cyg/io/sst25xx.h>
+
+// Required data structures.
+#include <cyg/io/flash_dev.h>
+
+#include <string.h>
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+cyg_flash_info_t sst25xx_flash_info;
+//-----------------------------------------------------------------------------
+// Thread data structures.
+
+static cyg_uint32 stack [CYGNUM_HAL_STACK_SIZE_TYPICAL / 4];
+static cyg_thread thread_data;
+static cyg_handle_t thread_handle;
+
+//-----------------------------------------------------------------------------
+// Data transfer buffers.
+
+//#define BUF_SIZE 1024
+#define BUF_SIZE 128
+
+static cyg_uint8 wbuf [BUF_SIZE];
+static cyg_uint8 rbuf [BUF_SIZE];
+
+//-----------------------------------------------------------------------------
+// Print out version information.
+
+void do_version (void)
+{
+    char *version = CYGACC_CALL_IF_MONITOR_VERSION();
+    if (version != NULL) diag_printf("%s", version);
+#ifdef HAL_PLATFORM_CPU
+    diag_printf("\nPlatform: %s (%s) %s\n",
+                   HAL_PLATFORM_BOARD, HAL_PLATFORM_CPU, HAL_PLATFORM_EXTRA);
+#endif
+    diag_printf("RAM: %p-%p, ",
+                (void*)(CYGMEM_REGION_ram),
+                (void*)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - 1));
+    diag_printf("(HEAP: %p-%p)\n",
+                (void*)(CYGMEM_SECTION_heap1),
+                (void*)(CYGMEM_SECTION_heap1 + CYGMEM_SECTION_heap1_SIZE - 1));
+}
+
+//-----------------------------------------------------------------------------
+// Run checkerboard and inverse checkerboard writes over each sector in turn.
+
+cyg_uint32 run_test_1
+  (void)
+{
+    int status;
+    cyg_uint32 i, j;
+    cyg_uint32 errors = 0;
+    cyg_flashaddr_t base_addr, err_addr;
+
+    diag_printf ("Test 1 - write and verify checkerboard and inverse checkerboard.\n");
+    diag_printf (" Flash device at %p, block_info at %p start = 0x%08x, blocks = %d[0x%x]\n",
+                 &sst25xx_flash_info,
+                 sst25xx_flash_info.block_info, sst25xx_flash_info.start,
+                 sst25xx_flash_info.block_info->blocks,
+                 sst25xx_flash_info.block_info->blocks);
+
+    // Iterate over all flash sectors.
+    for (i = 0; i < sst25xx_flash_info.block_info->blocks; i++) {
+        base_addr =  sst25xx_flash_info.start +
+                            (i * sst25xx_flash_info.block_info->block_size);
+        if(!(i % 64))
+            diag_printf("\n%5d 0x%08x: ", i, base_addr-sst25xx_flash_info.start);
+        diag_printf(".");
+        // Unlock block.
+        status = cyg_flash_unlock (base_addr, 1, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash erase error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+
+        // Erase block.
+        status = cyg_flash_erase (base_addr, 1, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash erase error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+
+        // Set up buffer with checkerboard.
+        for (j = 0; j < BUF_SIZE;) {
+           wbuf [j++] = 0x55;
+           wbuf [j++] = 0xAA;
+        }
+
+        // Write the checkerboard to the entire sector.
+        for (j = 0; j < sst25xx_flash_info.block_info->block_size ; j += BUF_SIZE) {
+            status = cyg_flash_program (base_addr + j, wbuf, BUF_SIZE, &err_addr);
+            if (status != FLASH_ERR_OK) {
+                diag_printf ("Flash write error : %s\n", cyg_flash_errmsg (status));
+                errors ++;
+            }
+        }
+
+        // Read back the checkerboard and verify.
+        for (j = 0; j < sst25xx_flash_info.block_info->block_size; j += BUF_SIZE) {
+            status = cyg_flash_read (base_addr + j, rbuf, BUF_SIZE, &err_addr);
+            if (status != FLASH_ERR_OK) {
+                diag_printf ("Flash read error : %s\n", cyg_flash_errmsg (status));
+                errors ++;
+            }
+            else if (memcmp (rbuf, wbuf, BUF_SIZE) != 0) {
+                diag_printf ("Flash read data corruption (0x%08X - 0x%08X).\n",
+                                base_addr + j, base_addr + j + BUF_SIZE - 1);
+                errors ++;
+            }
+        }
+        
+        // Erase block.
+        status = cyg_flash_erase (base_addr, 1, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash erase error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+
+        // Set up buffer with inverse checkerboard.
+        for (j = 0; j < BUF_SIZE;) {
+           wbuf [j++] = 0xAA;
+           wbuf [j++] = 0x55;
+        }
+
+        // Write the checkerboard to the entire sector.
+        for (j = 0; j < sst25xx_flash_info.block_info->block_size; j += BUF_SIZE) {
+            status = cyg_flash_program (base_addr + j, wbuf, BUF_SIZE, &err_addr);
+            if (status != FLASH_ERR_OK) {
+                diag_printf ("Flash write error : %s\n", cyg_flash_errmsg (status));
+                errors ++;
+            }
+        }
+
+        // Read back the checkerboard and verify.
+        for (j = 0; j < sst25xx_flash_info.block_info->block_size; j += BUF_SIZE) {
+            status = cyg_flash_read (base_addr + j, rbuf, BUF_SIZE, &err_addr);
+            if (status != FLASH_ERR_OK) {
+                diag_printf ("Flash read error : %s\n", cyg_flash_errmsg (status));
+                errors ++;
+            }
+            else if (memcmp (rbuf, wbuf, BUF_SIZE) != 0) {
+                diag_printf ("Flash read data corruption (0x%08X - 0x%08X).\n",
+                                base_addr + j, base_addr + j + BUF_SIZE - 1);
+                errors ++;
+            }
+        }
+    }
+    diag_printf("\n");
+    return errors;
+}
+
+//-----------------------------------------------------------------------------
+// Write and verify counting sequence over all device.
+
+cyg_uint32 run_test_2
+  (void)
+{
+    int status;
+    cyg_uint32 i, j;
+    cyg_uint32 errors = 0;
+    cyg_flashaddr_t base_addr, err_addr;
+
+    diag_printf ("Test 2 - write and verify counting sequence.\n");
+
+    // Erase all flash sectors.
+    diag_printf("Erase all flash sectors\n");
+    for (i = 0; i < sst25xx_flash_info.block_info->blocks; i++) {
+        base_addr =  sst25xx_flash_info.start +
+                           (i * sst25xx_flash_info.block_info->block_size);
+        if(!(i % 64))
+            diag_printf("\n%5d: ", i);
+        diag_printf(".");
+
+        // Erase block.
+        status = cyg_flash_erase (base_addr, 1, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash erase error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+    }
+    diag_printf("\n");
+
+    // Write counting sequence.
+    diag_printf("Writing counting sequence\n");
+    base_addr =  sst25xx_flash_info.start;
+    for (i = 0; i < (sst25xx_flash_info.end - sst25xx_flash_info.start) / 4;) {
+        if(!(i % (64*1024)))
+            diag_printf("\n%7d: ", i);
+        if(!(i % (32*64)))
+            diag_printf(".");
+        for (j = 0; j < BUF_SIZE;) {
+            wbuf [j++] = (cyg_uint8) ((i >> 0) & 0xFF);
+            wbuf [j++] = (cyg_uint8) ((i >> 8) & 0xFF);
+            wbuf [j++] = (cyg_uint8) ((i >> 16) & 0xFF);
+            wbuf [j++] = (cyg_uint8) ((i >> 24) & 0xFF);
+            i++;
+        }
+        status = cyg_flash_program (base_addr, wbuf, BUF_SIZE, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash write error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+        base_addr += BUF_SIZE;
+    }
+    diag_printf("\n");
+
+    // Verify counting sequence.
+    diag_printf("Verifying counting sequence\n");
+    base_addr = sst25xx_flash_info.start;
+    for (i = 0; i < (sst25xx_flash_info.end - sst25xx_flash_info.start) / 4;) {
+        if(!(i % (64*1024)))
+            diag_printf("\n%7d: ", i);
+        if(!(i % (32*64)))
+            diag_printf(".");
+        for (j = 0; j < BUF_SIZE;) {
+            wbuf [j++] = (cyg_uint8) ((i >> 0) & 0xFF);
+            wbuf [j++] = (cyg_uint8) ((i >> 8) & 0xFF);
+            wbuf [j++] = (cyg_uint8) ((i >> 16) & 0xFF);
+            wbuf [j++] = (cyg_uint8) ((i >> 24) & 0xFF);
+            i++;
+        }
+        status = cyg_flash_read (base_addr, rbuf, BUF_SIZE, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash read error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+        else if (memcmp (rbuf, wbuf, BUF_SIZE) != 0) {
+            diag_printf ("Flash read data corruption (0x%08X - 0x%08X).\n",
+                                        base_addr, base_addr + BUF_SIZE - 1);
+            errors ++;
+        }
+        base_addr += BUF_SIZE;
+    }
+    diag_printf("\n");
+    return errors;
+}
+
+//-----------------------------------------------------------------------------
+// Perform non-aligned buffer read/write tests, spanning sector boundaries.
+
+cyg_uint32 run_test_3
+  (void)
+{
+    int status;
+    cyg_uint32 i, count;
+    cyg_uint32 errors = 0;
+    cyg_flashaddr_t base_addr, err_addr;
+
+    diag_printf ("Test 3 - test non-aligned writes and reads.\n");
+
+    // Fill the write buffer with a basic counting sequence.
+    count = 0;
+    for (i = 0; i < BUF_SIZE;) {
+        wbuf [i++] = (cyg_uint8) ((count >> 0) & 0xFF);
+        wbuf [i++] = (cyg_uint8) ((count >> 8) & 0xFF);
+        count++;
+    }
+    // Assuming 256 byte pages gives 256 possible alignments.
+    base_addr = sst25xx_flash_info.start + sst25xx_flash_info.block_info->block_size;
+    for (i = 1; i <= 256; i++) {
+        if(!(i % 32))
+            diag_printf("\n%5d: ", i);
+        diag_printf(".");
+
+        // Erase sectors either side of sector boundary.
+        status = cyg_flash_erase (base_addr - 1, 1, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash erase error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+        status = cyg_flash_erase (base_addr, 1, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash erase error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+
+        // Write data spanning sector boundary.
+        status = cyg_flash_program (base_addr - i, wbuf, BUF_SIZE, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash write error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+
+        // Verify data spanning sector boundary.
+        status = cyg_flash_read (base_addr - i, rbuf, BUF_SIZE, &err_addr);
+        if (status != FLASH_ERR_OK) {
+            diag_printf ("Flash read error : %s\n", cyg_flash_errmsg (status));
+            errors ++;
+        }
+        else if (memcmp (rbuf, wbuf, BUF_SIZE) != 0) {
+            diag_printf ("Flash read data corruption (0x%08X - 0x%08X).\n",
+                                 base_addr - i, base_addr - i + BUF_SIZE - 1);
+            diag_printf ("Flash read data corruption %d.\n", i);
+            errors ++;
+        }
+
+        // Use next sector boundary for next test.
+        base_addr += sst25xx_flash_info.block_info->block_size;
+        if (base_addr >= sst25xx_flash_info.end)
+            base_addr = sst25xx_flash_info.start + sst25xx_flash_info.block_info->block_size;
+    }
+    diag_printf("\n\n");
+    return errors;
+}
+
+//-----------------------------------------------------------------------------
+// Run all SST25xx SPI interface loopback tests.
+
+void run_tests
+    (void)
+{
+    cyg_uint32 errors = 0;
+
+    do_version();
+
+    //    diag_printf ("----\nChecking for SST25xx compatible devices at %p\n", &sst25xx_flash_device);
+    diag_printf ("----\nChecking for SST25xx compatible devices.\n");
+    cyg_flash_set_global_printf((cyg_flash_printf *)&diag_printf);
+    cyg_flash_init(NULL);
+
+    cyg_flash_get_info_addr(CYGNUM_DEVS_FLASH_SPI_SST25XX_DEV0_MAP_ADDR, &sst25xx_flash_info);
+
+    // Check that the device is intialised.
+    if (sst25xx_flash_info.start == sst25xx_flash_info.end) {
+        diag_printf ("SST25xx device not initialised.\n");
+        errors ++;
+        goto out;
+    }
+
+    // Run the tests.
+    errors += run_test_1 ();
+    errors += run_test_2 ();
+//    errors += run_test_3 ();
+
+out:
+    diag_printf ("----\nTests complete - detected %d errors in total.\n", errors);
+    if (errors == 0)
+        CYG_TEST_PASS_FINISH ("SST25xx driver tests ran OK.");
+    else
+        CYG_TEST_FAIL_FINISH ("SST25xx driver test FAILED.");
+}
+
+//-----------------------------------------------------------------------------
+// User startup - tests are run in their own thread.
+
+void cyg_user_start
+    (void)
+{
+    CYG_TEST_INIT();
+    cyg_thread_create(
+        10,                                   // Arbitrary priority
+        (cyg_thread_entry_t*) run_tests,      // Thread entry point
+        0,                                    //
+        "test_thread",                        // Thread name
+        (cyg_uint8*) stack,                   // Stack
+        CYGNUM_HAL_STACK_SIZE_TYPICAL,        // Stack size
+        &thread_handle,                       // Thread handle
+        &thread_data                          // Thread data structure
+    );
+    cyg_thread_resume(thread_handle);
+    cyg_scheduler_start();
+}
+
+//=============================================================================
+
diff --git a/packages/devs/i2c/cortexm/a2fxxx/current/ChangeLog b/packages/devs/i2c/cortexm/a2fxxx/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/i2c/cortexm/a2fxxx/current/ChangeLog
@@ -0,0 +1,31 @@
+2011-04-01  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* cdl/i2c_a2fxxx.cdl:
+	* include/i2c_a2fxxx.h:
+	* src/i2c_a2fxxx.c:
+	New package -- Smartfusion Cortex-M3 I2C driver package.
+	[Bugzilla 1001291]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/i2c/cortexm/a2fxxx/current/cdl/i2c_a2fxxx.cdl b/packages/devs/i2c/cortexm/a2fxxx/current/cdl/i2c_a2fxxx.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/i2c/cortexm/a2fxxx/current/cdl/i2c_a2fxxx.cdl
@@ -0,0 +1,113 @@
+# ====================================================================
+#
+#      i2c_a2fxxx.cdl
+#
+#      eCos Smartfusion Cortex-M3 I2C configuration data
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      ccoutand
+# Contributors:
+# Date:           2011-01-18
+#
+#####DESCRIPTIONEND####
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_I2C_CORTEXM_A2FXXX  {
+    display       "Actel Smartfusion I2C driver"
+    parent        CYGPKG_IO_I2C
+    active_if     CYGPKG_IO_I2C
+    active_if     CYGPKG_HAL_CORTEXM_A2FXXX
+    include_dir   cyg/io
+    description   "
+        This package provides a generic I2C device driver for the on-chip
+        I2C modules in Smartfusion Cortex-M3 microcontroller."
+
+    compile       -library=libextras.a i2c_a2fxxx.c
+
+    cdl_option CYGNUM_HAL_CORTEXM_A2FXXX_I2C_CLK_DIV {
+        display       "I2C channel clock divider"
+        flavor        data
+        default_value { 256 }
+        legal_values  { 8 60 120 160 192 960 224 256 960}
+        description   "
+            Set the I2C clock divider."
+    }
+
+    cdl_option CYGDBG_DEVS_I2C_CORTEXM_A2FXXX_TRACE {
+        display       "Display status messages during I2C operations"
+        flavor        bool
+        default_value 0
+        description   "
+           Selecting this option will cause the I2C driver to print status
+           messages as various I2C operations are undertaken."
+    }
+
+    cdl_component CYGPKG_DEVS_I2C_CORTEXM_A2FXXX_OPTIONS {
+        display      "I2C driver build options"
+        flavor        none
+        active_if     { CYGINT_DEVS_I2C_CORTEXM_A2FXXX_BUS_DEVICES > 0 }
+        description   "
+            Package specific build options including control over
+            compiler flags used only in building the Smartfusion Cortex-M3
+            I2C bus driver."
+
+        cdl_option CYGPKG_DEVS_I2C_CORTEXM_A2FXXX_CFLAGS_ADD {
+            display       "Additional compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the Smartfusion Cortex-M3 I2C bus driver. These
+                flags are used in addition to the set of global flags."
+        }
+
+        cdl_option CYGPKG_DEVS_I2C_CORTEXM_A2FXXX_CFLAGS_REMOVE {
+            display       "Suppressed compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the Smartfusion Cortex-M3 I2C bus driver. These
+                flags are removed from the set of global flags if
+                present."
+        }
+    }
+}
+
+# EOF i2c_a2fxxx.cdl
diff --git a/packages/devs/i2c/cortexm/a2fxxx/current/include/i2c_a2fxxx.h b/packages/devs/i2c/cortexm/a2fxxx/current/include/i2c_a2fxxx.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/i2c/cortexm/a2fxxx/current/include/i2c_a2fxxx.h
@@ -0,0 +1,128 @@
+//==========================================================================
+//
+//      i2c_a2fxxx.h
+//
+//      I2C driver for Smartfusion Cortex M3 microcontroller
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ccoutand
+// Contributors:
+// Date:          2011-01-18
+// Original:      Bart Veer
+//                I2C driver for motorola coldfire processor
+// Description:   I2C driver for Smartfusion Cortex M3 microcontroller
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#ifndef CYGONCE_I2C_A2FXXX_H
+# define CYGONCE_I2C_A2FXXX_H
+
+# include <pkgconf/devs_i2c_cortexm_a2fxxx.h>
+# include <cyg/infra/cyg_type.h>
+# include <cyg/hal/drv_api.h>
+
+typedef enum a2fxxx_i2c_xfer_mode {
+    A2FXXX_I2C_XFER_MODE_INVALID = 0x00,
+    A2FXXX_I2C_XFER_MODE_TX = 0x01,
+    A2FXXX_I2C_XFER_MODE_RX = 0x02
+} a2fxxx_i2c_xfer_mode;
+
+typedef struct a2fxxx_i2c_extra {
+    cyg_uint32      i2c_base;          // I2C base address
+    cyg_uint32      i2c_base_bb;       // I2C base address (Bit-band)
+    cyg_uint32      i2c_periph;        // I2C peripheral bit mask
+    cyg_uint8       i2c_owner;         // We have bus ownership
+    cyg_uint8       i2c_lost_arb;      // Error condition leading to loss of
+    // bus ownership
+    cyg_uint8       i2c_send_nack;     // As per rx send_nack argument
+    cyg_uint8       i2c_got_nack;      // The last tx resulted in a nack
+    cyg_uint8       i2c_completed;     // Set by DSR, checked by thread
+
+    union {
+        const cyg_uint8 *i2c_tx_data;
+        cyg_uint8      *i2c_rx_data;
+    } i2c_data;                        // The current buffer for rx or tx
+    cyg_uint32      i2c_count;         // Number of bytes left in buffer
+    a2fxxx_i2c_xfer_mode i2c_mode;     // TX, RX, ...
+
+    cyg_bool        send_stop;
+    cyg_bool        send_start;
+    cyg_uint8       slave_addr;
+    cyg_drv_mutex_t i2c_lock;          // For synchronizing between DSR and
+    // foreground
+    cyg_drv_cond_t  i2c_wait;
+    // For initializing the interrupt
+    cyg_handle_t    i2c_interrupt_handle;
+    cyg_interrupt   i2c_interrupt_data;
+    cyg_uint32      i2c_isr_id;
+    cyg_uint32      i2c_isr_pri;
+    cyg_uint32      i2c_isr_mask;
+} a2fxxx_i2c_extra;
+
+externC void    a2fxxx_i2c_init(struct cyg_i2c_bus *);
+externC cyg_uint32 a2fxxx_i2c_tx(const cyg_i2c_device *, cyg_bool,
+                                 const cyg_uint8 *, cyg_uint32, cyg_bool);
+externC cyg_uint32 a2fxxx_i2c_rx(const cyg_i2c_device *, cyg_bool,
+                                 cyg_uint8 *, cyg_uint32, cyg_bool, cyg_bool);
+externC void    a2fxxx_i2c_stop(const cyg_i2c_device *);
+
+# define CYG_A2FXXX_I2C_BUS(                            \
+        _name_,                                         \
+        _init_fn_,                                      \
+        _base_,                                         \
+        _base_bb_,                                      \
+        _periph_,                                       \
+        _isr_vec_,                                      \
+        _isr_pri_)                                      \
+    static a2fxxx_i2c_extra _name_ ## _extra = {        \
+       .i2c_base    = _base_,                           \
+       .i2c_base_bb = _base_bb_,                        \
+       .i2c_periph  = _periph_,                         \
+       .i2c_isr_id  = _isr_vec_,                        \
+       .i2c_isr_pri = _isr_pri_                         \
+    };                                                  \
+    CYG_I2C_BUS(_name_,                                 \
+                _init_fn_,                              \
+                a2fxxx_i2c_tx,                          \
+                a2fxxx_i2c_rx,                          \
+                a2fxxx_i2c_stop,                        \
+                (void*) & ( _name_ ## _extra)) ;
+
+#endif // CYGONCE_I2C_A2FXXX_H
+
+// -------------------------------------------------------------------------
+// EOF i2c_a2fxxx.h
diff --git a/packages/devs/i2c/cortexm/a2fxxx/current/src/i2c_a2fxxx.c b/packages/devs/i2c/cortexm/a2fxxx/current/src/i2c_a2fxxx.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/i2c/cortexm/a2fxxx/current/src/i2c_a2fxxx.c
@@ -0,0 +1,450 @@
+//==========================================================================
+//
+//      i2c_a2fxxx.c
+//
+//      I2C driver for Smartfusion Cortex M3 microcontroller
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ccoutand
+// Contributors:
+// Date:          2011-01-18
+// Original:      Uwe Kindler, Bart Veer
+//                I2C driver for motorola coldfire processor
+// Description:   I2C driver for Smartfusion Cortex M3 microcontroller
+//                The RX part of the driver has not been tested.
+//
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#include <pkgconf/system.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/diag.h>
+#include <cyg/io/i2c.h>
+#include <cyg/io/i2c_a2fxxx.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/drv_api.h>
+
+#ifdef CYGDBG_DEVS_I2C_CORTEXM_A2FXXX_TRACE
+# define I2C_TRACE(args...) diag_printf(args)
+#else
+# define I2C_TRACE(args...)
+#endif
+
+#define I2C_DAT(_base_)       (_base_ + CYGHWR_HAL_A2FXXX_I2C_DATA)
+#define I2C_ADR(_base_)       (_base_ + CYGHWR_HAL_A2FXXX_I2C_ADDR)
+#define I2C_SR(_base_)        (_base_ + CYGHWR_HAL_A2FXXX_I2C_STATUS)
+#define I2C_CR(_base_)        (_base_ + CYGHWR_HAL_A2FXXX_I2C_CTRL)
+#define I2C_FREQ(_base_)      (_base_ + CYGHWR_HAL_A2FXXX_I2C_FREQ)
+#define I2C_SMBUS(_base_)     (_base_ + CYGHWR_HAL_A2FXXX_I2C_SMBUS)
+#define I2C_GLITCH(_base_)    (_base_ + CYGHWR_HAL_A2FXXX_I2C_GLITCH)
+
+// Bit-band definition
+#define I2C_CR_CR0(_base_)    (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) +  \
+                               ( 0*sizeof(cyg_uint32) ) )
+#define I2C_CR_CR1(_base_)    (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) +  \
+                               ( 1*sizeof(cyg_uint32) ) )
+#define I2C_CR_AA(_base_)     (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) +  \
+                               ( 2*sizeof(cyg_uint32) ) )
+#define I2C_CR_SI(_base_)     (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) +  \
+                               ( 3*sizeof(cyg_uint32) ) )
+#define I2C_CR_STO(_base_)    (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) +  \
+                               ( 4*sizeof(cyg_uint32) ) )
+#define I2C_CR_STA(_base_)    (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) +  \
+                               ( 5*sizeof(cyg_uint32) ) )
+#define I2C_CR_ENS1(_base_)   (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) +  \
+                               ( 6*sizeof(cyg_uint32) ) )
+#define I2C_CR_CR2(_base_)    (_base_ + ( CYGHWR_HAL_A2FXXX_I2C_CTRL << 5 ) +  \
+                               ( 7*sizeof(cyg_uint32) ) )
+
+#define I2C_MTX_STATE(x)      CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_##x
+#define I2C_MRX_STATE(x)      CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_##x
+
+// Divider coefficient
+static const unsigned int i2c_div[] = {
+    256,
+    224,
+    192,
+    160,
+    960,
+    120,
+    60,
+    8,
+    0
+};
+
+static cyg_uint32
+a2fxxx_i2c_isr(cyg_vector_t vec, cyg_addrword_t data)
+{
+    a2fxxx_i2c_extra *extra = (a2fxxx_i2c_extra *) data;
+    cyg_uint32      result = CYG_ISR_HANDLED;
+    cyg_uint32      sr,
+                    dr;
+    cyg_uint8       tx_data = *extra->i2c_data.i2c_tx_data;
+    cyg_uint32      cr = 0;
+
+    // Read the current status of the I2C
+    HAL_READ_UINT32(I2C_SR(extra->i2c_base), sr);
+    HAL_READ_UINT32(I2C_CR(extra->i2c_base), cr);
+
+    // What to do next depends on the current transfer mode.
+    if (A2FXXX_I2C_XFER_MODE_TX == extra->i2c_mode) {
+        I2C_TRACE("I2C: TX IRQ handling -> 0x%x\n", sr);
+        switch (sr) {
+        // Start/Repeated start, write the slave address and clear the
+        // START and SI bits
+        case I2C_MTX_STATE(START):
+        case I2C_MTX_STATE(REPEAT_START):
+            HAL_WRITE_UINT32(I2C_DAT(extra->i2c_base), extra->slave_addr);
+            cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_STA;
+            cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
+            break;
+        // ACK is received for the address or data, keep sending
+        // START and SI bits
+        case I2C_MTX_STATE(ADDR_ACK):
+        case I2C_MTX_STATE(DATA_ACK):
+            if (0 == extra->i2c_count) {
+                if (extra->send_stop) {
+                    cr |= CYGHWR_HAL_A2FXXX_I2C_CTRL_STO;
+                    cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
+                } else {
+                    // For repeated start, we must disable interrupt
+                    extra->i2c_isr_mask = true;
+                }
+                // No more bytes to send.
+                result |= CYG_ISR_CALL_DSR;
+            } else {
+                // Send byte
+                HAL_WRITE_UINT32(I2C_DAT(extra->i2c_base),
+                                 (cyg_uint32)tx_data);
+                extra->i2c_data.i2c_tx_data += 1;
+                extra->i2c_count -= 1;
+                cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
+            }
+            break;
+        case I2C_MTX_STATE(ARBLOST):
+        case I2C_MTX_STATE(DATA_NACK):
+            // Lost the bus, abort the transfer. count has already been
+            // decremented. Assume the byte did not actually arrive.
+            extra->i2c_count += 1;
+        case I2C_MTX_STATE(ADDR_NACK):
+            // For all error type, clear interrupt and send stop bit
+            cr |= CYGHWR_HAL_A2FXXX_I2C_CTRL_STO;
+            cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
+            extra->i2c_got_nack = 1;
+            result |= CYG_ISR_CALL_DSR;
+            break;
+        default:
+            HAL_INTERRUPT_ACKNOWLEDGE(extra->i2c_isr_id);
+            return result;
+        }
+    } else if (A2FXXX_I2C_XFER_MODE_RX == extra->i2c_mode) {
+        I2C_TRACE("I2C: RX IRQ handling -> 0x%x\n", sr);
+        cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_AA;
+        switch (sr) {
+        // Start/Repeated start, write the slave address and clear the
+        // START and SI bits
+        case I2C_MRX_STATE(START):
+        case I2C_MRX_STATE(REPEAT_START):
+            HAL_WRITE_UINT32(I2C_DAT(extra->i2c_base), extra->slave_addr);
+            cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_STA;
+            cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
+            break;
+        // ACK is received for the address
+        case I2C_MRX_STATE(ADDR_ACK):
+            if (extra->i2c_count > 1) {
+                cr |= CYGHWR_HAL_A2FXXX_I2C_CTRL_AA;
+            }
+            cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
+            break;
+        // Receive data
+        case I2C_MRX_STATE(DATA_ACK):
+        case I2C_MRX_STATE(DATA_NACK):
+            cr &= ~CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
+            if (extra->i2c_count > 2) {
+                cr |= CYGHWR_HAL_A2FXXX_I2C_CTRL_AA;
+            }
+            if (1 == extra->i2c_count) {
+                if (extra->send_stop) {
+                    cr |= CYGHWR_HAL_A2FXXX_I2C_CTRL_STO;
+                } else {
+                    // For repeated start, we must disable interrupt
+                    cr |= CYGHWR_HAL_A2FXXX_I2C_CTRL_SI;
+                    extra->i2c_isr_mask = true;
+                }
+                // Received the last byte.
+                result |= CYG_ISR_CALL_DSR;
+            }
+            HAL_READ_UINT32(I2C_DAT(extra->i2c_base), dr);
+            *(extra->i2c_data.i2c_rx_data) = (cyg_uint8)dr;
+            extra->i2c_data.i2c_rx_data += 1;
+            extra->i2c_count -= 1;
+            break;
+        case I2C_MRX_STATE(ARBLOST):
+        case I2C_MRX_STATE(ADDR_NACK):
+            // Lost the bus? Maybe a spurious stop
+            cr |= CYGHWR_HAL_A2FXXX_I2C_CTRL_STO;
+            result |= CYG_ISR_CALL_DSR;
+            break;
+        default:
+            HAL_INTERRUPT_ACKNOWLEDGE(extra->i2c_isr_id);
+            return result;
+        }
+    } else {
+        // Invalid state? Some kind of spurious interrupt?
+        // Just ignore it.
+        I2C_TRACE("I2C spurious interrupt\n");
+    }
+
+    HAL_WRITE_UINT32(I2C_CR(extra->i2c_base), cr);
+
+    HAL_INTERRUPT_ACKNOWLEDGE(extra->i2c_isr_id);
+
+    if (extra->i2c_isr_mask)
+        HAL_INTERRUPT_MASK(extra->i2c_isr_id);
+
+    return result;
+}
+
+
+static void
+a2fxxx_i2c_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data)
+{
+    a2fxxx_i2c_extra *extra = (a2fxxx_i2c_extra *) data;
+    extra->i2c_completed = 1;
+    cyg_drv_cond_signal(&(extra->i2c_wait));
+}
+
+
+// A transfer has been started. Wait for completion
+static inline void
+a2fxxx_i2c_doit(a2fxxx_i2c_extra * extra)
+{
+    cyg_drv_mutex_lock(&(extra->i2c_lock));
+    cyg_drv_dsr_lock();
+    while (!extra->i2c_completed) {
+        cyg_drv_cond_wait(&(extra->i2c_wait));
+    }
+    cyg_drv_dsr_unlock();
+    cyg_drv_mutex_unlock(&(extra->i2c_lock));
+}
+
+
+static inline void
+a2fxxx_i2c_stopit(a2fxxx_i2c_extra * extra)
+{
+    extra->i2c_lost_arb = 0;
+    extra->i2c_owner = 0;
+    extra->i2c_mode = A2FXXX_I2C_XFER_MODE_INVALID;
+}
+
+
+void
+a2fxxx_i2c_stop(const cyg_i2c_device * dev)
+{
+    a2fxxx_i2c_extra *extra = (a2fxxx_i2c_extra *) dev->i2c_bus->i2c_extra;
+    a2fxxx_i2c_stopit(extra);
+}
+
+
+cyg_uint32
+a2fxxx_i2c_tx(const cyg_i2c_device * dev, cyg_bool send_start,
+              const cyg_uint8 *tx_data, cyg_uint32 count, cyg_bool send_stop)
+{
+    a2fxxx_i2c_extra *extra = (a2fxxx_i2c_extra *) dev->i2c_bus->i2c_extra;
+    extra->send_stop = send_stop;
+    extra->send_start = send_start;
+    extra->i2c_count = count;
+    extra->slave_addr = ((dev->i2c_address << 1) | 0x00);
+    cyg_uint32      si = 0;
+
+    if (!extra->i2c_lost_arb) {
+        extra->i2c_completed = 0;
+        extra->i2c_mode = A2FXXX_I2C_XFER_MODE_TX;
+
+        if (send_start || !extra->i2c_got_nack) {
+            I2C_TRACE
+                ("I2C: TX to %2x, data %2x, count: %4d, START flag: %s, STOP flag: %s\n",
+                 dev->i2c_address, *tx_data, count,
+                 (send_start == true) ? "true" : "false",
+                 (send_stop == true) ? "true" : "false");
+            extra->i2c_data.i2c_tx_data = tx_data;
+            HAL_READ_UINT32(I2C_CR_SI(extra->i2c_base_bb), si);
+            // Set start bit
+            HAL_WRITE_UINT32(I2C_CR_STA(extra->i2c_base_bb),
+                             CYGHWR_HAL_A2FXXX_BITSET);
+            // For repeated start, we need to clear the interrupt
+            if (si != 0) {
+                HAL_WRITE_UINT32(I2C_CR_SI(extra->i2c_base_bb),
+                                 CYGHWR_HAL_A2FXXX_BITCLEAR);
+                HAL_INTERRUPT_ACKNOWLEDGE(extra->i2c_isr_id);
+            }
+            // For repeated start, we need to un-mask the interrupt
+            if (extra->i2c_isr_mask) {
+                extra->i2c_isr_mask = false;
+                HAL_INTERRUPT_UNMASK(extra->i2c_isr_id);
+            }
+            a2fxxx_i2c_doit(extra);
+        }
+
+    }
+    if (send_stop) {
+        I2C_TRACE("I2C: TX send stop\n");
+        a2fxxx_i2c_stopit(extra);
+    }
+
+    I2C_TRACE("I2C: TX count %d\n", extra->i2c_count);
+
+    // tx() should return the number of bytes actually transmitted.
+    // ISR() increments extra->count after a failure, which leads to
+    // an edge condition when send_start and there is no acknowledgment
+    // of the address byte.
+    if (extra->i2c_count > count) {
+        return 0;
+    }
+
+    return count - extra->i2c_count;
+}
+
+
+cyg_uint32
+a2fxxx_i2c_rx(const cyg_i2c_device * dev, cyg_bool send_start,
+              cyg_uint8 *rx_data, cyg_uint32 count, cyg_bool send_nack,
+              cyg_bool send_stop)
+{
+    a2fxxx_i2c_extra *extra = (a2fxxx_i2c_extra *) dev->i2c_bus->i2c_extra;
+    extra->i2c_send_nack = send_nack;
+    extra->i2c_count = count;
+    extra->send_stop = send_stop;
+    extra->send_start = send_start;
+    extra->slave_addr = ((dev->i2c_address << 1) | 0x01);
+    cyg_uint32      si = 0;
+
+    if (!extra->i2c_lost_arb) {
+        extra->i2c_completed = 0;
+        extra->i2c_data.i2c_rx_data = rx_data;
+        extra->i2c_mode = A2FXXX_I2C_XFER_MODE_RX;
+        I2C_TRACE
+            ("I2C: RX to %2x, count: %4d, START flag: %s, STOP flag: %s\n",
+             dev->i2c_address, count, (send_start == true) ? "true" : "false",
+             (send_stop == true) ? "true" : "false");
+        HAL_READ_UINT32(I2C_CR_SI(extra->i2c_base_bb), si);
+        // Set start bit
+        HAL_WRITE_UINT32(I2C_CR_STA(extra->i2c_base_bb),
+                         CYGHWR_HAL_A2FXXX_BITSET);
+        // For repeated start, we need to clear the interrupt
+        if (si != 0) {
+            HAL_WRITE_UINT32(I2C_CR_SI(extra->i2c_base_bb),
+                             CYGHWR_HAL_A2FXXX_BITCLEAR);
+            HAL_INTERRUPT_ACKNOWLEDGE(extra->i2c_isr_id);
+        }
+        // For repeated start, we need to un-mask the interrupt
+        if (extra->i2c_isr_mask) {
+            extra->i2c_isr_mask = false;
+            HAL_INTERRUPT_UNMASK(extra->i2c_isr_id);
+        }
+        a2fxxx_i2c_doit(extra);
+    }
+
+    if (send_stop) {
+        I2C_TRACE("I2C: RX send stop\n");
+        a2fxxx_i2c_stopit(extra);
+    }
+
+    return count - extra->i2c_count;
+}
+
+
+// ----------------------------------------------------------------------------
+// The functions needed for all I2C devices.
+
+void
+a2fxxx_i2c_init(struct cyg_i2c_bus *bus)
+{
+    a2fxxx_i2c_extra *extra = (a2fxxx_i2c_extra *) bus->i2c_extra;
+    cyg_uint8       div = 0;
+#ifdef CYGDBG_DEVS_I2C_CORTEXM_A2FXXX_TRACE
+    cyg_uint32      i2c_freq =
+        ((hal_a2fxxx_i2c_clock(extra->i2c_base) /
+          CYGNUM_HAL_CORTEXM_A2FXXX_I2C_CLK_DIV));
+#endif
+
+    while ((i2c_div[div] != CYGNUM_HAL_CORTEXM_A2FXXX_I2C_CLK_DIV) &&
+           i2c_div[div] != 0) {
+        div++;
+    }
+
+    I2C_TRACE("\nI2C INIT, divider: %d(%d), frequency: %d\n", i2c_div[div],
+              div, i2c_freq);
+
+    cyg_drv_mutex_init(&extra->i2c_lock);
+    cyg_drv_cond_init(&extra->i2c_wait, &extra->i2c_lock);
+    cyg_drv_interrupt_create(extra->i2c_isr_id,
+                             extra->i2c_isr_pri,
+                             (cyg_addrword_t)extra,
+                             &a2fxxx_i2c_isr,
+                             &a2fxxx_i2c_dsr,
+                             &(extra->i2c_interrupt_handle),
+                             &(extra->i2c_interrupt_data));
+    cyg_drv_interrupt_attach(extra->i2c_interrupt_handle);
+
+    // Enable I2C peripheral
+    CYGHWR_HAL_A2FXXX_PERIPH_RELEASE(extra->i2c_periph);
+
+    // Set I2C bus speed
+    HAL_WRITE_UINT32(I2C_CR_ENS1(extra->i2c_base_bb),
+                     CYGHWR_HAL_A2FXXX_BITSET);
+
+    HAL_WRITE_UINT32(I2C_CR_CR0(extra->i2c_base_bb),
+                     ((div & 0x1) ? CYGHWR_HAL_A2FXXX_BITSET :
+                      CYGHWR_HAL_A2FXXX_BITCLEAR));
+    HAL_WRITE_UINT32(I2C_CR_CR1(extra->i2c_base_bb),
+                     ((div & 0x2) ? CYGHWR_HAL_A2FXXX_BITSET :
+                      CYGHWR_HAL_A2FXXX_BITCLEAR));
+    HAL_WRITE_UINT32(I2C_CR_CR2(extra->i2c_base_bb),
+                     ((div & 0x4) ? CYGHWR_HAL_A2FXXX_BITSET :
+                      CYGHWR_HAL_A2FXXX_BITCLEAR));
+
+    // Interrupts can now be safely unmasked
+    HAL_INTERRUPT_UNMASK(extra->i2c_isr_id);
+}
+
+//---------------------------------------------------------------------------
+// EOF i2c_a2fxxx.c
diff --git a/packages/devs/i2c/cortexm/lm3s/current/ChangeLog b/packages/devs/i2c/cortexm/lm3s/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/i2c/cortexm/lm3s/current/ChangeLog
@@ -0,0 +1,30 @@
+2011-01-18  Christophe Coutand  <ccoutand@stmi.com>
+
+	* cdl/i2c_lm3s.cdl:
+	* include/i2c_lm3s.h:
+	* src/i2c_lm3s.c:
+	New package -- Stellaris Cortex M3 I2C driver package.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/i2c/cortexm/lm3s/current/cdl/i2c_lm3s.cdl b/packages/devs/i2c/cortexm/lm3s/current/cdl/i2c_lm3s.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/i2c/cortexm/lm3s/current/cdl/i2c_lm3s.cdl
@@ -0,0 +1,113 @@
+# ====================================================================
+#
+#      i2c_lm3s.cdl
+#
+#      eCos Stellaris Cortex M3 I2C configuration data
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      ccoutand
+# Contributors:
+# Date:           2011-01-18
+#
+#####DESCRIPTIONEND####
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_I2C_CORTEXM_LM3S {
+    display       "I2C driver for Stellaris Cortex M3 microcontroller family"
+    parent        CYGPKG_IO_I2C
+    active_if     CYGPKG_IO_I2C
+    active_if     CYGPKG_HAL_CORTEXM_LM3S
+    include_dir   cyg/io
+    description   "
+        This package provides a generic I2C device driver for the on-chip
+        I2C modules in Stellaris Cortex M3 microcontroller."
+
+    compile       -library=libextras.a i2c_lm3s.c
+
+    cdl_option CYGNUM_HAL_CORTEXM_LM3S_I2C_CLK_SPEED {
+        display       "I2C channel clock"
+        flavor        data
+        default_value { 100000 }
+        legal_values  { 100000 400000 }
+        description   "
+            Set the I2C clock speed. Slow mode (100KHz) or fast mode
+            (400KHz)"
+    }
+
+    cdl_option CYGPKG_DEVS_I2C_CORTEXM_LM3S_TRACE {
+        display       "I2C trace"
+        flavor        bool
+        default_value 0
+        description   "
+            Enable I2C transaction trace. Select to debug the driver."
+    }
+
+    cdl_component CYGPKG_DEVS_I2C_CORTEXM_LM3S_OPTIONS {
+        display      "I2C driver build options"
+        flavor        none
+        active_if     { CYGINT_DEVS_I2C_CORTEXM_LM3S_BUS_DEVICES > 0 }
+        description   "
+            Package specific build options including control over
+            compiler flags used only in building the Stellaris Cortex M3
+            I2C bus driver."
+
+        cdl_option CYGPKG_DEVS_I2C_CORTEXM_LM3S_CFLAGS_ADD {
+            display       "Additional compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the Stellaris Cortex M3 I2C bus driver. These
+                flags are used in addition to the set of global flags."
+        }
+
+        cdl_option CYGPKG_DEVS_I2C_CORTEXM_LM3S_CFLAGS_REMOVE {
+            display       "Suppressed compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the Stellaris Cortex M3 I2C bus driver. These
+                flags are removed from the set of global flags if
+                present."
+        }
+    }
+}
+
+# EOF i2c_lm3s.cdl
diff --git a/packages/devs/i2c/cortexm/lm3s/current/include/i2c_lm3s.h b/packages/devs/i2c/cortexm/lm3s/current/include/i2c_lm3s.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/i2c/cortexm/lm3s/current/include/i2c_lm3s.h
@@ -0,0 +1,124 @@
+//==========================================================================
+//
+//      i2c_lm3s8xx.h
+//
+//      I2C driver for Stellaris Cortex M3 microcontroller
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ccoutand
+// Contributors:  
+// Date:          2011-01-18
+// Original:      Bart Veer
+//                I2C driver for motorola coldfire processor
+// Description:   I2C driver for Stellaris Cortex M3 microcontroller
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#ifndef CYGONCE_I2C_LM3S_H
+#define CYGONCE_I2C_LM3S_H
+
+#include <pkgconf/devs_i2c_cortexm_lm3s.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/drv_api.h>
+
+typedef enum lm3s_i2c_xfer_mode {
+    LM3S_I2C_XFER_MODE_INVALID = 0x00,
+    LM3S_I2C_XFER_MODE_TX = 0x01,
+    LM3S_I2C_XFER_MODE_RX = 0x02
+} lm3s_i2c_xfer_mode;
+
+typedef struct lm3s_i2c_extra {
+    cyg_uint32      i2c_base;          // I2C base address
+    cyg_uint32      i2c_periph;        // I2C peripheral bit mask
+    cyg_uint8       i2c_owner;         // We have bus ownership
+    cyg_uint8       i2c_lost_arb;      // Error condition leading to loss of
+                                       // bus ownership
+    cyg_uint8       i2c_send_nack;     // As per rx send_nack argument
+    cyg_uint8       i2c_got_nack;      // The last tx resulted in a nack
+    cyg_uint8       i2c_completed;     // Set by DSR, checked by thread
+
+    union {
+        const cyg_uint8 *i2c_tx_data;
+        cyg_uint8      *i2c_rx_data;
+    } i2c_data;                        // The current buffer for rx or tx
+    cyg_uint32      i2c_count;         // Number of bytes left in buffer
+    lm3s_i2c_xfer_mode i2c_mode;       // TX, RX, ...
+
+    cyg_bool        send_stop;
+    cyg_bool        send_start;
+    cyg_drv_mutex_t i2c_lock;          // For synchronizing between DSR and
+                                       // foreground
+    cyg_drv_cond_t  i2c_wait;
+    // For initializing the interrupt
+    cyg_handle_t    i2c_interrupt_handle;
+    cyg_interrupt   i2c_interrupt_data;
+    cyg_uint32      i2c_isr_id;
+    cyg_uint32      i2c_isr_pri;
+} lm3s_i2c_extra;
+
+externC void    lm3s_i2c_init(struct cyg_i2c_bus *);
+externC cyg_uint32 lm3s_i2c_tx(const cyg_i2c_device *, cyg_bool,
+                               const cyg_uint8 *, cyg_uint32, cyg_bool);
+externC cyg_uint32 lm3s_i2c_rx(const cyg_i2c_device *, cyg_bool, cyg_uint8 *,
+                               cyg_uint32, cyg_bool, cyg_bool);
+externC void    lm3s_i2c_stop(const cyg_i2c_device *);
+
+#define CYG_LM3S_I2C_BUS(                               \
+        _name_,                                         \
+        _init_fn_,                                      \
+        _base_,                                         \
+        _periph_,                                       \
+        _isr_vec_,                                      \
+        _isr_pri_,                                      \
+        _fdr_)                                          \
+    static lm3s_i2c_extra _name_ ## _extra = {          \
+       .i2c_base = _base_,                              \
+       .i2c_periph = _periph_,                          \
+       .i2c_isr_id = _isr_vec_,                         \
+       .i2c_isr_pri= _isr_pri_                          \
+    };                                                  \
+    CYG_I2C_BUS(_name_,                                 \
+                _init_fn_,                              \
+                lm3s_i2c_tx,                            \
+                lm3s_i2c_rx,                            \
+                lm3s_i2c_stop,                          \
+                (void*) & ( _name_ ## _extra)) ;
+
+#endif // CYGONCE_I2C_LM3S_H
+
+// -------------------------------------------------------------------------
+// EOF i2c_lm3s.h
diff --git a/packages/devs/i2c/cortexm/lm3s/current/src/i2c_lm3s.c b/packages/devs/i2c/cortexm/lm3s/current/src/i2c_lm3s.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/i2c/cortexm/lm3s/current/src/i2c_lm3s.c
@@ -0,0 +1,389 @@
+//==========================================================================
+//
+//      i2c_lm3s.c
+//
+//      I2C driver for Stellaris Cortex M3 microcontroller
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ccoutand
+// Contributors:  
+// Date:          2011-01-18
+// Original:      Uwe Kindler, Bart Veer
+//                I2C driver for motorola coldfire processor
+// Description:   I2C driver for Stellaris Cortex M3 microcontroller
+//                The RX part of the driver has not been tested.
+//
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#include <pkgconf/system.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/diag.h>
+#include <cyg/io/i2c.h>
+#include <cyg/io/i2c_lm3s.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/drv_api.h>
+
+#ifdef CYGPKG_DEVS_I2C_CORTEXM_LM3S_TRACE
+# define I2C_TRACE(args...) diag_printf(args)
+#else
+# define I2C_TRACE(args...)
+#endif
+
+#define I2C_DAT(_extra_)     (_extra_ + CYGHWR_HAL_LM3S_I2C_MDR)
+#define I2C_ADR(_extra_)     (_extra_ + CYGHWR_HAL_LM3S_I2C_MSA)
+#define I2C_SR(_extra_)      (_extra_ + CYGHWR_HAL_LM3S_I2C_MCS)
+#define I2C_CR(_extra_)      (_extra_ + CYGHWR_HAL_LM3S_I2C_MCS)
+#define I2C_MCR(_extra_)     (_extra_ + CYGHWR_HAL_LM3S_I2C_MCR)
+#define I2C_MTPR(_extra_)    (_extra_ + CYGHWR_HAL_LM3S_I2C_MTPR)
+#define I2C_MCR(_extra_)     (_extra_ + CYGHWR_HAL_LM3S_I2C_MCR)
+#define I2C_IMR(_extra_)     (_extra_ + CYGHWR_HAL_LM3S_I2C_MIMR)
+#define I2C_ICR(_extra_)     (_extra_ + CYGHWR_HAL_LM3S_I2C_MICR)
+
+#define WAIT_BUS_READY( __sr__, __extra__ )                     \
+{                                                               \
+    if (!__extra__->i2c_owner) {                                \
+        __extra__->i2c_got_nack = 0;                            \
+        __extra__->i2c_owner = 1;                               \
+        HAL_READ_UINT32(I2C_SR(__extra__->i2c_base), __sr__);   \
+        while (__sr__ & CYGHWR_HAL_LM3S_I2C_MCS_BUSBSY) {       \
+          HAL_READ_UINT32(I2C_SR(__extra__->i2c_base),__sr__);  \
+        }                                                       \
+    }                                                           \
+}
+
+
+static cyg_uint32
+lm3s_i2c_isr(cyg_vector_t vec, cyg_addrword_t data)
+{
+    lm3s_i2c_extra *extra = (lm3s_i2c_extra *) data;
+    cyg_uint32      sr,
+                    dr;
+    cyg_uint32      result = CYG_ISR_HANDLED;
+    cyg_uint32      reg = CYGHWR_HAL_LM3S_I2C_MCS_RUN;
+    cyg_uint8       tx_data = *extra->i2c_data.i2c_tx_data;
+
+    // Read the current status, then clear the interrupt
+    HAL_READ_UINT32(I2C_SR(extra->i2c_base), sr);
+    HAL_WRITE_UINT32(I2C_ICR(extra->i2c_base), 1);
+
+    // What to do next depends on the current transfer mode.
+    if (LM3S_I2C_XFER_MODE_TX == extra->i2c_mode) {
+        I2C_TRACE("I2C: TX IRQ handling\n");
+        if (sr & CYGHWR_HAL_LM3S_I2C_MCS_ERR) {
+            // Lost the bus, abort the transfer. count has already been
+            // decremented. Assume the byte did not actually arrive.
+            extra->i2c_count += 1;
+            // Arbitration  lost, stop
+            if (sr & CYGHWR_HAL_LM3S_I2C_MCS_ARBLST) {
+                reg = CYGHWR_HAL_LM3S_I2C_MCS_STOP;
+                HAL_WRITE_UINT32(I2C_CR(extra->i2c_base), reg);
+            }
+            // This byte has been sent but the device cannot accept
+            // any more. The nack must be remembered. Otherwise if
+            // we got a nack for the last byte in a tx then the
+            // calling code will think the entire tx succeeded,
+            // and there will be problems if the next call is
+            // another tx without a repeated start.
+            if ((sr & CYGHWR_HAL_LM3S_I2C_MCS_ADRACK) |
+                (sr & CYGHWR_HAL_LM3S_I2C_MCS_DATACK)) {
+                extra->i2c_got_nack = 1;
+            }
+            result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
+            I2C_TRACE("I2C TX, bus arbitration error\n");
+        } else if (0 == extra->i2c_count) {
+            // No more bytes to send.
+            result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
+        } else {
+            // Send byte
+            HAL_WRITE_UINT32(I2C_DAT(extra->i2c_base), (cyg_uint32)tx_data);
+            extra->i2c_data.i2c_tx_data += 1;
+            extra->i2c_count -= 1;
+            // Last byte
+            if ((0 == extra->i2c_count) && extra->send_stop) {
+                reg |= CYGHWR_HAL_LM3S_I2C_MCS_STOP;
+            }
+            HAL_WRITE_UINT32(I2C_CR(extra->i2c_base), reg);
+        }
+    } else if (LM3S_I2C_XFER_MODE_RX == extra->i2c_mode) {
+        I2C_TRACE("I2C: RX IRQ handling\n");
+        if (sr & CYGHWR_HAL_LM3S_I2C_MCS_ERR) {
+            // Lost the bus? Maybe a spurious stop
+            result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
+        } else {
+            if (2 == extra->i2c_count) {
+                // Received one, one more to go,
+                // and that one should be nacked.
+                if (!extra->i2c_send_nack) {
+                    reg |= CYGHWR_HAL_LM3S_I2C_MCS_ACK;
+                }
+                if (extra->send_stop) {
+                    reg |= CYGHWR_HAL_LM3S_I2C_MCS_STOP;
+                }
+                HAL_WRITE_UINT32(I2C_CR(extra->i2c_base), reg);
+            } else if (1 == extra->i2c_count) {
+                // Received the last byte.
+                result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
+            }
+            HAL_READ_UINT32(I2C_DAT(extra->i2c_base), dr);
+            *(extra->i2c_data.i2c_rx_data) = (cyg_uint8)dr;
+            extra->i2c_data.i2c_rx_data += 1;
+            extra->i2c_count -= 1;
+        }
+    } else {
+        // Invalid state? Some kind of spurious interrupt?
+        // Just ignore it.
+        I2C_TRACE("I2C spurious interrupt\n");
+    }
+
+    HAL_INTERRUPT_ACKNOWLEDGE(extra->i2c_isr_id);
+
+    return result;
+}
+
+
+static void
+lm3s_i2c_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data)
+{
+    lm3s_i2c_extra *extra = (lm3s_i2c_extra *) data;
+    extra->i2c_completed = 1;
+    cyg_drv_cond_signal(&(extra->i2c_wait));
+}
+
+
+// A transfer has been started. Wait for completion
+static inline void
+lm3s_i2c_doit(lm3s_i2c_extra * extra)
+{
+    cyg_drv_mutex_lock(&(extra->i2c_lock));
+    cyg_drv_dsr_lock();
+    while (!extra->i2c_completed) {
+        cyg_drv_cond_wait(&(extra->i2c_wait));
+    }
+    cyg_drv_dsr_unlock();
+    cyg_drv_mutex_unlock(&(extra->i2c_lock));
+}
+
+
+static inline void
+lm3s_i2c_stopit(lm3s_i2c_extra * extra)
+{
+    extra->i2c_lost_arb = 0;
+    extra->i2c_owner = 0;
+    extra->i2c_mode = LM3S_I2C_XFER_MODE_INVALID;
+}
+
+
+void
+lm3s_i2c_stop(const cyg_i2c_device * dev)
+{
+    lm3s_i2c_extra *extra = (lm3s_i2c_extra *) dev->i2c_bus->i2c_extra;
+    lm3s_i2c_stopit(extra);
+}
+
+
+static cyg_bool
+lm3s_i2c_handle_xfer(lm3s_i2c_extra * extra, int address)
+{
+    cyg_uint32      sr;
+    cyg_uint8       data = *extra->i2c_data.i2c_tx_data;
+    cyg_uint32      reg = CYGHWR_HAL_LM3S_I2C_MCS_RUN;
+
+    // Nothing to send or receive
+    if (extra->i2c_count == 0)
+        return 0;
+
+    // Take the bus ownership
+    WAIT_BUS_READY(sr, extra);
+
+    // This can be a start or repeated start
+    if (extra->send_start) {
+        reg |= CYGHWR_HAL_LM3S_I2C_MCS_START;
+        HAL_WRITE_UINT32(I2C_ADR(extra->i2c_base), address);
+    }
+    // TX transfer
+    if (extra->i2c_mode == LM3S_I2C_XFER_MODE_TX) {
+        extra->i2c_data.i2c_tx_data += 1;
+        extra->i2c_count -= 1;
+        HAL_WRITE_UINT32(I2C_DAT(extra->i2c_base), (cyg_uint32)data);
+
+        // Single byte transfer
+        if (extra->send_stop && (extra->i2c_count == 0)) {
+            reg |= CYGHWR_HAL_LM3S_I2C_MCS_STOP;
+        }
+    } else {
+        // Single byte transfer, set the STOP bit
+        if (extra->send_stop && (extra->i2c_count == 1)) {
+            reg |= CYGHWR_HAL_LM3S_I2C_MCS_STOP;
+        }
+        // Do not ACK last byte per user request
+        if (!extra->i2c_send_nack || !(extra->i2c_count == 1)) {
+            reg |= CYGHWR_HAL_LM3S_I2C_MCS_ACK;
+        }
+    }
+
+    HAL_WRITE_UINT32(I2C_CR(extra->i2c_base), reg);
+
+    return 1;
+}
+
+
+cyg_uint32
+lm3s_i2c_tx(const cyg_i2c_device * dev, cyg_bool send_start,
+            const cyg_uint8 *tx_data, cyg_uint32 count, cyg_bool send_stop)
+{
+    lm3s_i2c_extra *extra = (lm3s_i2c_extra *) dev->i2c_bus->i2c_extra;
+    extra->send_stop = send_stop;
+    extra->send_start = send_start;
+    extra->i2c_count = count;
+
+    if (!extra->i2c_lost_arb) {
+        extra->i2c_completed = 0;
+        extra->i2c_mode = LM3S_I2C_XFER_MODE_TX;
+
+        if (send_start || !extra->i2c_got_nack) {
+            I2C_TRACE
+                ("I2C: TX to %2x, data %2x, count: %4d, START flag: %s\n",
+                 dev->i2c_address, *tx_data, count,
+                 (send_start == true) ? "true" : "false");
+            extra->i2c_data.i2c_tx_data = tx_data;
+            if (!lm3s_i2c_handle_xfer(extra, (dev->i2c_address << 1) | 0x00)) {
+                return 0;
+            }
+            lm3s_i2c_doit(extra);
+        }
+
+    }
+    if (send_stop) {
+        I2C_TRACE("I2C: TX send stop\n");
+        lm3s_i2c_stopit(extra);
+    }
+
+    I2C_TRACE("I2C: TX count %d\n", extra->i2c_count);
+
+    // tx() should return the number of bytes actually transmitted.
+    // ISR() increments extra->count after a failure, which leads to
+    // an edge condition when send_start and there is no acknowledgment
+    // of the address byte.
+    if (extra->i2c_count > count) {
+        return 0;
+    }
+
+    return count - extra->i2c_count;
+}
+
+
+cyg_uint32
+lm3s_i2c_rx(const cyg_i2c_device * dev, cyg_bool send_start,
+            cyg_uint8 *rx_data, cyg_uint32 count, cyg_bool send_nack,
+            cyg_bool send_stop)
+{
+    lm3s_i2c_extra *extra = (lm3s_i2c_extra *) dev->i2c_bus->i2c_extra;
+    extra->i2c_count = count;
+    extra->i2c_send_nack = send_nack;
+    extra->send_stop = send_stop;
+    extra->send_start = send_start;
+
+    if (!extra->i2c_lost_arb) {
+        extra->i2c_completed = 0;
+        extra->i2c_data.i2c_rx_data = rx_data;
+        extra->i2c_mode = LM3S_I2C_XFER_MODE_RX;
+        I2C_TRACE("I2C: RX to %2x, count: %4d, START flag: %s\n",
+                  dev->i2c_address, count,
+                  (send_start == true) ? "true" : "false");
+        if (!lm3s_i2c_handle_xfer(extra, (dev->i2c_address << 1) | 0x01)) {
+            return 0;
+        }
+        lm3s_i2c_doit(extra);
+    }
+
+    if (send_stop) {
+        I2C_TRACE("I2C: RX send stop\n");
+        lm3s_i2c_stopit(extra);
+    }
+
+    return count - extra->i2c_count;
+}
+
+
+// ----------------------------------------------------------------------------
+// The functions needed for all I2C devices.
+
+void
+lm3s_i2c_init(struct cyg_i2c_bus *bus)
+{
+    lm3s_i2c_extra *extra = (lm3s_i2c_extra *) bus->i2c_extra;
+    cyg_uint32      tpr =
+        ((hal_lm3s_i2c_clock() /
+          (20 * CYGNUM_HAL_CORTEXM_LM3S_I2C_CLK_SPEED)) - 1);
+
+    I2C_TRACE("I2C INIT, TPR register: %d\n", tpr);
+
+    cyg_drv_mutex_init(&extra->i2c_lock);
+    cyg_drv_cond_init(&extra->i2c_wait, &extra->i2c_lock);
+    cyg_drv_interrupt_create(extra->i2c_isr_id,
+                             extra->i2c_isr_pri,
+                             (cyg_addrword_t)extra,
+                             &lm3s_i2c_isr,
+                             &lm3s_i2c_dsr,
+                             &(extra->i2c_interrupt_handle),
+                             &(extra->i2c_interrupt_data));
+    cyg_drv_interrupt_attach(extra->i2c_interrupt_handle);
+
+    // Enable I2C peripheral, it is left to the variant/platform HAL to
+    // configure the SDA and SCL IOs.
+    CYGHWR_HAL_LM3S_PERIPH_SET(extra->i2c_periph, 1);
+
+    // Enable Master mode
+    HAL_WRITE_UINT32(I2C_MCR(extra->i2c_base), CYGHWR_HAL_LM3S_I2C_MCR_MFE);
+
+    // Set I2C bus speed
+    HAL_WRITE_UINT32(I2C_MTPR(extra->i2c_base), tpr);
+
+    // Enable Interrupt
+    HAL_WRITE_UINT32(I2C_IMR(extra->i2c_base), 1);
+
+    // Interrupts can now be safely unmasked
+    HAL_INTERRUPT_UNMASK(extra->i2c_isr_id);
+}
+
+//---------------------------------------------------------------------------
+// EOF i2c_lm3s.c
diff --git a/packages/devs/i2c/freescale/i2c/current/ChangeLog b/packages/devs/i2c/freescale/i2c/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/i2c/freescale/i2c/current/ChangeLog
@@ -0,0 +1,39 @@
+2013-04-30  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/i2c_freescale.cdl: Add requirement of CYGPKG_KERNEL.
+	[ Bugzilla 1001397 ]
+
+2011-11-20  Tomas Frydrych <tomas@sleepfive.com>
+2013-03-21  Mike Jones <mike@proclivis.com>
+
+	* cdl/i2c_freescale.cdl:
+	* include/i2c_freescale.h:
+	* src/i2c_freescale.c:
+	Tomas: New package -- Freescale I2C driver package. [Bugzilla 1001397]
+	Mike: Made adjustments to state machine behavior to prevent race conditions
+	that led to lockup. Debugged data rate code provided by Ilija Kocho.
+	Fully tested with large PMBus application and verified clock rates.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/packages/devs/i2c/freescale/i2c/current/cdl/i2c_freescale.cdl b/packages/devs/i2c/freescale/i2c/current/cdl/i2c_freescale.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/i2c/freescale/i2c/current/cdl/i2c_freescale.cdl
@@ -0,0 +1,183 @@
+# ====================================================================
+#
+#      i2c_freescale.cdl
+#
+#      eCos Freescale Kinetis and ColdFire+ I2C configuration data
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 2011 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later
+## version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with eCos; if not, write to the Free Software Foundation, Inc.,
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+##
+## As a special exception, if other files instantiate templates or use
+## macros or inline functions from this file, or you compile this file
+## and link it with other works to produce a work based on this file,
+## this file does not by itself cause the resulting work to be covered by
+## the GNU General Public License. However the source code for this file
+## must still be made available in accordance with section (3) of the GNU
+## General Public License v2.
+##
+## This exception does not invalidate any other reasons why a work based
+## on this file might be covered by the GNU General Public License.
+## -------------------------------------------
+## ####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      Tomas Frydrych
+# Contributors:
+# Date:           2011-11-20
+#
+#####DESCRIPTIONEND####
+# ====================================================================
+
+cdl_interface CYGINT_IO_FREESCALE_I2C_BUS {
+    display      "Number of I2C buses"
+}
+
+cdl_package CYGPKG_DEVS_I2C_FREESCALE_I2C {
+    display       "Freescale I2C driver"
+    parent        CYGPKG_IO_I2C
+    requires      CYGPKG_IO_I2C
+    active_if     CYGPKG_KERNEL
+    requires      CYGPKG_HAL_CORTEXM_KINETIS
+    include_dir   cyg/io
+    description   "
+        This package provides a generic I2C device driver for the on-chip
+        I2C modules in Freescale Kinetis and ColdFire+ chips."
+
+    compile       -library=libextras.a i2c_freescale.c
+
+    for { set ::bus 0 } { $::bus < 2 } { incr ::bus } {
+
+        cdl_interface CYGINT_IO_FREESCALE_I2C[set ::bus] {
+            display "I2C bus [set ::bus] is present"
+        }
+
+        cdl_component CYGHWR_DEVS_FREESCALE_I2C[set ::bus] {
+            display       "I2C bus [set ::bus]"
+            flavor        bool
+            description   "Enable I2C bus [set ::bus]"
+            requires      CYGPKG_DEVS_I2C_FREESCALE_I2C
+            active_if     CYGINT_IO_FREESCALE_I2C[set ::bus]
+            implements    CYGINT_IO_FREESCALE_I2C_BUS
+            default_value 0
+
+            cdl_component CYGNUM_DEVS_FREESCALE_I2C[set ::bus]_CLOCK {
+                display       "Default I2C bus frequency"
+                flavor        data
+                description   "
+                    The default frequency setting for I2C[set ::bus].
+                    If bit 31 is set then the least significant byte contains
+                    pre-calculeted frequency divider register setting.
+                    Otherwise other bits contain frequency setpoint in \[Hz\]."
+
+                    requires (CYGNUM_DEVS_FREESCALE_I2C[set ::bus]_CLOCK > 0 &&            \
+                             CYGNUM_DEVS_FREESCALE_I2C[set ::bus]_CLOCK <= 268435455) ||   \
+                             (CYGNUM_DEVS_FREESCALE_I2C[set ::bus]_CLOCK >= 0x80000000 &&  \
+                             CYGNUM_DEVS_FREESCALE_I2C[set ::bus]_CLOCK <= 0x800000FF)
+
+                default_value 100000
+
+                cdl_option CYGNUM_DEVS_FREESCALE_I2C[set ::bus]_CLOCK_FIT {
+                    display       "Fit"
+                    flavor        data
+                    legal_values  1 2 3
+                    default_value 1
+                    description   "
+                        For a given clock frequency there are several divider
+                        register that fit. This option is hints on which fit to end lookup"
+                    }
+
+                cdl_option CYGNUM_DEVS_FREESCALE_I2C[set ::bus]_CLOCK_AGR {
+                    display       "Aggressive clocking"
+                    flavor        data
+                    legal_values  0 1
+                    default_value 0
+                    description   "
+                        If the setpoint bus frequency is not available, then if
+                        this option is 1 the closest available frequency is
+                        picked even if it overclocks. If 0 the closest available
+                        frequency frequency not higher than setpoint is picked."
+                }
+            }
+
+            cdl_component CYGOPT_DEVS_FREESCALE_I2C[set ::bus]_C2 {
+                display        "C2 register options"
+                flavor         data
+                calculated 0x0 |                                     \
+                      CYGOPT_DEVS_FREESCALE_I2C[set ::bus]_C2_HDRS << 5
+
+                cdl_option CYGOPT_DEVS_FREESCALE_I2C[set ::bus]_C2_HDRS {
+                    display       "High drive select"
+                    flavor        bool
+                    no_define
+                    default_value 0
+                }
+            }
+
+            cdl_option CYGNUM_DEVS_FREESCALE_I2C[set ::bus]_FLT {
+                display         "Glitch filter"
+                flavor          data
+                default_value   0
+                legal_values    { 0 to 31 }
+            }
+        }
+    }
+
+    cdl_option CYGPKG_DEVS_I2C_FREESCALE_I2C_TRACE {
+        display       "I2C trace"
+        flavor        bool
+        default_value 0
+        description   "
+            Enable I2C transaction trace. Select to debug the driver."
+    }
+
+    cdl_component CYGPKG_DEVS_I2C_FREESCALE_I2C_OPTIONS {
+        display      "I2C driver build options"
+        flavor        none
+        description   "
+            Package specific build options including control over
+            compiler flags used only in building the Freescale I2C bus driver."
+
+        cdl_option CYGPKG_DEVS_I2C_FREESCALE_I2C_CFLAGS_ADD {
+            display       "Additional compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the Freescale I2C bus driver. These
+                flags are used in addition to the set of global flags."
+        }
+
+        cdl_option CYGPKG_DEVS_I2C_FREESCALE_I2C_CFLAGS_REMOVE {
+            display       "Suppressed compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the Freescale I2C bus driver. These
+                flags are removed from the set of global flags if
+                present."
+        }
+    }
+}
+
+# EOF i2c_freescale.cdl
diff --git a/packages/devs/i2c/freescale/i2c/current/include/i2c_freescale.h b/packages/devs/i2c/freescale/i2c/current/include/i2c_freescale.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/i2c/freescale/i2c/current/include/i2c_freescale.h
@@ -0,0 +1,254 @@
+//==========================================================================
+//
+//      i2c_freescale.h
+//
+//      I2C driver for Freescale Kinetis and ColdFire+ microcontrollers
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2010, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Tomas Frydrych <tomas@sleepfive.com>
+// Contributors:
+// Date:          2011-11-20
+// Original:      ccoutand
+//                I2C driver for Stellaris Cortex M3 microcontroller
+// Description:   I2C driver for Freescale Kinetis and ColdFire+
+//                microcontrollers
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#ifndef CYGONCE_I2C_FREESCALE_H
+#define CYGONCE_I2C_FREESCALE_H
+
+#include <pkgconf/devs_i2c_freescale_i2c.h>
+#include <cyg/io/i2c.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/drv_api.h>
+
+//---------------------------------------------------------------------------
+// i2c memory structure
+typedef volatile struct freescale_i2c_s {
+    cyg_uint8 a1;
+    cyg_uint8 f;
+    cyg_uint8 c1;
+    cyg_uint8 s;
+    cyg_uint8 d;
+    cyg_uint8 c2;
+    cyg_uint8 flt;
+    cyg_uint8 ra;
+    cyg_uint8 smb;
+    cyg_uint8 a2;
+    cyg_uint8 slth;
+    cyg_uint8 sltl;
+} freescale_i2c_t;
+
+// I2C register base pointers
+#define FREESCALE_I2C_P(__base)  ((freescale_i2c_t*)(__base))
+
+// Modes
+// Master write
+#define FREESCALE_I2C_MODE_MW 0x0u
+// Master read
+#define FREESCALE_I2C_MODE_MR 0x1u
+
+// Bit Fields
+#define FREESCALE_I2C_A1_AD_M  0xFEu
+#define FREESCALE_I2C_A1_AD_S  1
+// adress register from address and mode
+#define FREESCALE_I2C_A1_AD(__a, __m)                                   \
+  ((((cyg_uint8)(((cyg_uint8)(__a))<<FREESCALE_I2C_A1_AD_S)) &          \
+    FREESCALE_I2C_A1_AD_M)|(__m & 0x1u))
+
+#define FREESCALE_I2C_F_ICR_M  0x3Fu
+#define FREESCALE_I2C_F_ICR_S  0
+#define FREESCALE_I2C_F_ICR(x)                                          \
+  (((cyg_uint8)(((cyg_uint8)(x))<<FREESCALE_I2C_F_ICR_S)) &             \
+   FREESCALE_I2C_F_ICR_M)
+#define FREESCALE_I2C_F_MULT_M 0xC0u
+#define FREESCALE_I2C_F_MULT_S 6
+#define FREESCALE_I2C_F_MULT(x)                                         \
+  (((cyg_uint8)(((cyg_uint8)(x))<<FREESCALE_I2C_F_MULT_S)) &            \
+   FREESCALE_I2C_F_MULT_M)
+#define FREESCALE_I2C_F(__mult, __icr) \
+  (FREESCALE_I2C_F_MULT (__mult) |     \
+   FREESCALE_I2C_F_ICR (__icr))
+
+#define FREESCALE_I2C_C1_DMAEN_M 0x1u
+#define FREESCALE_I2C_C1_WUEN_M  0x2u
+#define FREESCALE_I2C_C1_RSTA_M  0x4u
+#define FREESCALE_I2C_C1_TXAK_M  0x8u
+#define FREESCALE_I2C_C1_TX_M    0x10u
+#define FREESCALE_I2C_C1_MST_M   0x20u
+#define FREESCALE_I2C_C1_IICIE_M 0x40u
+#define FREESCALE_I2C_C1_IICEN_M 0x80u
+
+#define FREESCALE_I2C_S_RXAK_M   0x1u
+#define FREESCALE_I2C_S_IICIF_M  0x2u
+#define FREESCALE_I2C_S_SRW_M    0x4u
+#define FREESCALE_I2C_S_RAM_M    0x8u
+#define FREESCALE_I2C_S_ARBL_M   0x10u
+#define FREESCALE_I2C_S_BUSY_M   0x20u
+#define FREESCALE_I2C_S_IAAS_M   0x40u
+#define FREESCALE_I2C_S_TCF_M    0x80u
+
+#define FREESCALE_I2C_C2_AD_M    0x7u
+#define FREESCALE_I2C_C2_AD_S    0
+#define FREESCALE_I2C_C2_AD(x)                                          \
+  (((cyg_uint8)(((cyg_uint8)(x))<<FREESCALE_I2C_C2_AD_S)) &             \
+   FREESCALE_I2C_C2_AD_M)
+#define FREESCALE_I2C_C2_RMEN_M  0x8u
+#define FREESCALE_I2C_C2_SBRC_M  0x10u
+#define FREESCALE_I2C_C2_HDRS_M  0x20u
+#define FREESCALE_I2C_C2_ADEXT_M 0x40u
+#define FREESCALE_I2C_C2_GCAEN_M 0x80u
+
+#define FREESCALE_I2C_FLT_FLT_M  0x1Fu
+#define FREESCALE_I2C_FLT_FLT_S  0
+#define FREESCALE_I2C_FLT_FLT(x)                                        \
+  (((cyg_uint8)(((cyg_uint8)(x))<<FREESCALE_I2C_FLT_FLT_S)) &           \
+   FREESCALE_I2C_FLT_FLT_M)
+
+#define FREESCALE_I2C_RA_RAD_M   0xFEu
+#define FREESCALE_I2C_RA_RAD_S   1
+#define FREESCALE_I2C_RA_RAD(x)                                         \
+  (((cyg_uint8)(((cyg_uint8)(x))<<FREESCALE_I2C_RA_RAD_S)) &            \
+   FREESCALE_I2C_RA_RAD_M)
+
+#define FREESCALE_I2C_SMB_SHTF2IE_M 0x1u
+#define FREESCALE_I2C_SMB_SHTF2_M   0x2u
+#define FREESCALE_I2C_SMB_SHTF1_M   0x4u
+#define FREESCALE_I2C_SMB_SLTF_M    0x8u
+#define FREESCALE_I2C_SMB_TCKSEL_M  0x10u
+#define FREESCALE_I2C_SMB_SIICAEN_M 0x20u
+#define FREESCALE_I2C_SMB_ALERTEN_M 0x40u
+#define FREESCALE_I2C_SMB_FACK_M    0x80u
+
+#define FREESCALE_I2C_A2_SAD_M      0xFEu
+#define FREESCALE_I2C_A2_SAD_S      1
+#define FREESCALE_I2C_A2_SAD(x)                                         \
+  (((cyg_uint8)(((cyg_uint8)(x))<<FREESCALE_I2C_A2_SAD_S)) &            \
+   FREESCALE_I2C_A2_SAD_M)
+
+#define FREESCALE_I2C_SLTH_SSLT_M   0xFFu
+#define FREESCALE_I2C_SLTH_SSLT_S   0
+#define FREESCALE_I2C_SLTH_SSLT(x)                                      \
+  (((cyg_uint8)(((cyg_uint8)(x))<<FREESCALE_I2C_SLTH_SSLT_S)) &         \
+   FREESCALE_I2C_SLTH_SSLT_M)
+
+#define FREESCALE_I2C_SLTL_SSLT_M   0xFFu
+#define FREESCALE_I2C_SLTL_SSLT_S   0
+#define FREESCALE_I2C_SLTL_SSLT(x)                                      \
+  (((cyg_uint8)(((cyg_uint8)(x))<<FREESCALE_I2C_SLTL_SSLT_S)) &         \
+   FREESCALE_I2C_SLTL_SSLT_M)
+
+#define FREESCALE_I2C_DELAY_F_CACHED_S    31
+#define FREESCALE_I2C_DELAY_FIT_S         29
+#define FREESCALE_I2C_DELAY_AGR_S         28
+
+#define FREESCALE_I2C_DELAY_F_IS_CACHED_M BIT_(FREESCALE_I2C_DELAY_F_CACHED_S)
+#define FREESCALE_I2C_DELAY_F_CACHE_M     0xFF
+#define FREESCALE_I2C_DELAY_M             0x0FFFFFFF
+
+#define FREESCALE_I2C_DELAY_CFG(__delay, __fit, __agr)                    \
+            ((__delay) + (((__fit) & 0x3) << FREESCALE_I2C_DELAY_FIT_S) + \
+            (((__agr) & 0x1) << FREESCALE_I2C_DELAY_AGR_S))
+
+#define FREEDCALE_I2C_DELAY_IS_AGRESIVE(__delay) \
+            ((__delay) & (1 << FREESCALE_I2C_DELAY_AGR_S))
+
+typedef enum freescale_i2c_xfer_mode {
+    FREESCALE_I2C_XFER_MODE_INVALID = 0x00,
+    FREESCALE_I2C_XFER_MODE_TX = 0x01,
+    FREESCALE_I2C_XFER_MODE_RX = 0x02
+} freescale_i2c_xfer_mode;
+
+// Resources borrowed from HAL
+typedef struct freescale_i2c_extra_hal_s {
+    cyg_uint32 pin_sda;                // Data pin
+    cyg_uint32 pin_scl;                // Clock pin
+    cyg_uint32 clock;                  // Clock gate
+} freescale_i2c_extra_hal_t;
+
+/*
+ * Extra data for the i2c bus
+ */
+typedef struct freescale_i2c_extra {
+    cyg_uint32      i2c_base;          // I2C base address
+    cyg_uint32      i2c_delay;
+    cyg_uint8       i2c_bus_number;    // bus number
+    cyg_uint8       i2c_owner;         // We have bus ownership
+    cyg_uint8       i2c_lost_arb;      // Error condition leading to loss of
+                                       // bus ownership
+    cyg_uint8       i2c_send_nack;     // As per rx send_nack argument
+    cyg_uint8       i2c_got_nack;      // The last tx resulted in a nack
+    cyg_uint8       i2c_completed;     // Set by DSR, checked by thread
+
+    cyg_uint8       c2_cfg;             // C2 register default settings
+    cyg_uint8       flt_cfg;            // Glitch filter setting
+
+    union {
+        const cyg_uint8 *i2c_tx_data;
+        cyg_uint8       *i2c_rx_data;
+    } i2c_data;                        // The current buffer for rx or tx
+    cyg_uint32      i2c_count;         // Number of bytes left in buffer
+
+    freescale_i2c_xfer_mode i2c_mode;       // TX, RX, ...
+
+    cyg_bool        send_stop;
+    cyg_bool        send_start;
+    cyg_drv_mutex_t i2c_lock;          // For synchronizing between DSR and
+                                       // foreground
+    cyg_drv_cond_t  i2c_wait;
+    // For initializing the interrupt
+    cyg_handle_t    i2c_interrupt_handle;
+    cyg_interrupt   i2c_interrupt_data;
+    cyg_uint32      i2c_isr_id;
+    cyg_uint32      i2c_isr_pri;
+    const freescale_i2c_extra_hal_t *hal_p;         // Resources borrowed from HAL
+} freescale_i2c_extra;
+
+externC void freescale_i2c_init(struct cyg_i2c_bus *);
+externC cyg_uint32 freescale_i2c_tx(cyg_i2c_device *, cyg_bool,
+                                    const cyg_uint8 *, cyg_uint32, cyg_bool);
+externC cyg_uint32 freescale_i2c_rx(cyg_i2c_device *,
+                                    cyg_bool, cyg_uint8 *, cyg_uint32,
+                                    cyg_bool, cyg_bool);
+externC void freescale_i2c_stop(const cyg_i2c_device *);
+externC void freescale_i2c_set_frequency (cyg_i2c_device * dev,
+                                          cyg_uint8 premul);
+
+#endif // CYGONCE_I2C_FREESCALE_H
+// -------------------------------------------------------------------------
+// EOF i2c_freescale.h
diff --git a/packages/devs/i2c/freescale/i2c/current/include/i2c_freescale_buses.inl b/packages/devs/i2c/freescale/i2c/current/include/i2c_freescale_buses.inl
new file mode 100644
--- /dev/null
+++ b/packages/devs/i2c/freescale/i2c/current/include/i2c_freescale_buses.inl
@@ -0,0 +1,108 @@
+#ifndef CYGONCE_I2C_FREESCALE_BUSES_INL
+#define CYGONCE_I2C_FREESCALE_BUSES_INL
+//==========================================================================
+//
+//      i2c_freescale_buses.inl
+//
+//      Freescale I2C bus instances
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ilijak
+// Contributors:
+// Date:          2011-11-20
+// Description:   Freescale I2C bus instances
+//
+//####DESCRIPTIONEND####
+//==========================================================================
+
+// I2C bus definition macros
+// HAL should provide following macros per _bus_:
+//  -I2C controller base address
+//    CYGADDR_IO_I2C_FREESCALE_I2C<_bus_>_BASE
+//  -Interrupt vector number and priority
+//    CYGNUM_DEVS_INTERRUPT_I2C<_bus_>
+//    CYGNUM_DEVS_FREESCALE_I2C<_bus_>_IRQ_PRIORITY
+//  -I2C pin configuration:
+//    CYGHWR_IO_I2C_FREESCALE_I2C<_bus_>_PIN_SDA
+//    CYGHWR_IO_I2C_FREESCALE_I2C<_bus_>_PIN_SCL
+//  -Clock gating
+//    CYGHWR_IO_FREESCALE_I2C<_bus_>_CLK
+
+#define CYG_FREESCALE_I2C_BUS(_bus_)                                              \
+static const freescale_i2c_extra_hal_t cyg_i2c ## _bus_ ## _extra_hal = {         \
+    .pin_sda = CYGHWR_IO_I2C_FREESCALE_I2C ## _bus_ ## _PIN_SDA,                  \
+    .pin_scl = CYGHWR_IO_I2C_FREESCALE_I2C ## _bus_ ## _PIN_SCL,                  \
+    .clock   = CYGHWR_IO_FREESCALE_I2C ## _bus_ ## _CLK                           \
+};                                                                                \
+                                                                                  \
+static freescale_i2c_extra cyg_i2c ## _bus_ ## _bus_extra = {                     \
+    .i2c_base       = CYGADDR_IO_I2C_FREESCALE_I2C ## _bus_ ## _BASE,             \
+    .i2c_bus_number = _bus_,                                                      \
+    .i2c_delay      = CYGNUM_DEVS_FREESCALE_I2C ## _bus_ ## _CLOCK & 0x80000000 ? \
+                      CYGNUM_DEVS_FREESCALE_I2C ## _bus_ ## _CLOCK :              \
+                      FREESCALE_I2C_DELAY_CFG(1000000000 /                        \
+                          CYGNUM_DEVS_FREESCALE_I2C ## _bus_ ## _CLOCK,           \
+                          CYGNUM_DEVS_FREESCALE_I2C ## _bus_ ## _CLOCK_FIT - 1,   \
+                          CYGNUM_DEVS_FREESCALE_I2C ## _bus_ ## _CLOCK_AGR),      \
+    .i2c_isr_id     = CYGNUM_HAL_INTERRUPT_I2C ## _bus_,                          \
+    .i2c_isr_pri    = CYGNUM_DEVS_FREESCALE_I2C ## _bus_ ## _IRQ_PRIORITY,        \
+    .c2_cfg         = CYGOPT_DEVS_FREESCALE_I2C ## _bus_ ## _C2,                  \
+    .flt_cfg        = CYGNUM_DEVS_FREESCALE_I2C ## _bus_ ## _FLT,                 \
+    .hal_p          = &(cyg_i2c ## _bus_ ## _extra_hal)                           \
+};                                                                                \
+                                                                                  \
+CYG_I2C_BUS(cyg_i2c ## _bus_ ## _bus,                                             \
+            freescale_i2c_init,                                                   \
+            freescale_i2c_tx,                                                     \
+            freescale_i2c_rx,                                                     \
+            freescale_i2c_stop,                                                   \
+            (void*) & (cyg_i2c ## _bus_ ## _bus_extra)) ;
+
+#endif // CYGONCE_I2C_FREESCALE_BUSES_INL
+
+//-----------------------------------------------------------------------------
+// I2C bus instances
+//
+#ifdef CYGHWR_DEVS_FREESCALE_I2C0
+CYG_FREESCALE_I2C_BUS(0);
+#endif
+
+#ifdef CYGHWR_DEVS_FREESCALE_I2C1
+CYG_FREESCALE_I2C_BUS(1);
+#endif
+// -------------------------------------------------------------------------
+// EOF i2c_freescale_buses.inl
diff --git a/packages/devs/i2c/freescale/i2c/current/src/i2c_freescale.c b/packages/devs/i2c/freescale/i2c/current/src/i2c_freescale.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/i2c/freescale/i2c/current/src/i2c_freescale.c
@@ -0,0 +1,839 @@
+//==========================================================================
+//
+//      i2c_freescale.c
+//
+//      I2C driver for Freescale Kinetis and ColdFire+ microcontrollers
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Tomas Frydrych <tomas@sleepfive.com>
+// Contributors:  Mike Jones <mike@proclivis.com>
+//                Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2011-11-20
+// Original:      ccoutand
+//                I2C driver for Stellaris Cortex M3 microcontroller
+// Description:   Driver for Freescale I2C controller
+//
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#include <pkgconf/system.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/diag.h>
+#define CYGBLD_I2C_DEVICE_CONST
+#include <cyg/io/i2c.h>
+#include <cyg/io/i2c_freescale.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/kernel/kapi.h>
+
+#ifdef CYGPKG_DEVS_I2C_FREESCALE_I2C_TRACE
+# define I2C_TRACE(args...) diag_printf(args)
+#else
+# define I2C_TRACE(args...)
+#endif
+
+#ifndef CYGNUM_DEV_I2C_SPIN_PRIO
+#define CYGNUM_DEV_I2C_SPIN_PRIO (CYGNUM_KERNEL_SCHED_PRIORITIES - 2)
+#endif
+
+#ifndef CYGNUM_DEV_I2C_SPIN_TIMEOUT
+#define CYGNUM_DEV_I2C_SPIN_TIMEOUT 30
+#endif
+
+#define CYGOPT_FREESCALE_I2C_FREQ_FAST_EXIT 0
+
+#define I2C_STOP(__i2c)                   \
+CYG_MACRO_START                           \
+    __i2c->c1 &= ~FREESCALE_I2C_C1_MST_M; \
+    __i2c->c1 &= ~FREESCALE_I2C_C1_TX_M;  \
+CYG_MACRO_END
+
+#define I2C_START(__i2c)                 \
+CYG_MACRO_START                          \
+    __i2c->c1 |= FREESCALE_I2C_C1_TX_M;  \
+    __i2c->c1 |= FREESCALE_I2C_C1_MST_M; \
+CYG_MACRO_END
+
+#define I2C_REPEAT_START(__i2c)           \
+CYG_MACRO_START                           \
+    __i2c->c1 |= FREESCALE_I2C_C1_RSTA_M; \
+CYG_MACRO_END
+
+
+#define I2C_CLEAR(__i2c, __mask) \
+CYG_MACRO_START                  \
+    __i2c->s |= __mask;          \
+CYG_MACRO_END
+
+// Clock rate calculator
+
+#define I2C_DEBUG_CLOCK 0
+
+#define I2C_CLOCK_NORM 1000
+#define I2C_CLOCK_NORMLL 1000LL
+
+// dev_i2c_freescale_freq_table[] entries and
+// dev_i2c_freescale_frequency_entry_t (typedef of cyg_uint16 or cyg_uint32)
+// type are provided be provided by HAL
+static const dev_i2c_freescale_frequency_entry_t dev_i2c_freescale_freq_table[]
+                 = { CYGHWR_IO_FREESCALE_I2C_FREQUENCY_TABLE };
+static const cyg_uint32 dev_i2c_freescale_freq_table_size =
+                 sizeof(dev_i2c_freescale_freq_table) /
+                 sizeof(dev_i2c_freescale_freq_table[0]);
+
+// Frequency divider setting calculator
+// Calculate F register setting. The input parameter period_sp is encodded:
+// If most significant bit (31) is 1, than the least significant byte contains
+// explicit F refister value. If most significant bit (31) is 0 then:
+//    - bits 27-0: clock period in [ns];
+//    - bits 30,29: fit (see CDL)
+//    - bit 28:
+//          1) aggressive look up - closest matching period
+//          0) consrvative look up - closest matching period not shorter than setpoint
+
+static cyg_uint8
+freescale_i2c_freq_div_calc(cyg_uint32 period_sp)
+{
+    cyg_uint32 sys_clk_per;
+    cyg_uint32 period, the_period = 0xffffffff, agr;
+    cyg_uint32 mult, the_mult = 4;
+    cyg_int32 icr_i, the_icr_i = dev_i2c_freescale_freq_table_size - 1;
+    cyg_uint16 icr;
+    cyg_uint8 i2cf = 0xff;
+
+    cyg_uint32 fit;
+
+#if I2C_DEBUG_CLOCK
+        I2C_TRACE("Period setpont: 0x%08x\n", period_sp);
+#endif
+    // Extract period and fit
+    fit = period_sp >> FREESCALE_I2C_DELAY_FIT_S;
+    agr = FREEDCALE_I2C_DELAY_IS_AGRESIVE(period_sp);
+    period_sp &= FREESCALE_I2C_DELAY_M;
+    sys_clk_per = ((1000000000 * I2C_CLOCK_NORMLL) / CYGHWR_IO_I2C_FREESCALE_I2C_CLOCK);
+    period_sp *= I2C_CLOCK_NORM;
+
+#if I2C_DEBUG_CLOCK
+    I2C_TRACE("Period %d.%d[ns] [0x%08x] fit %d agr 0x%08x\n", period_sp/I2C_CLOCK_NORM,
+              period_sp%I2C_CLOCK_NORM, period_sp, fit, agr);
+#endif
+
+    for(mult = 4; mult > 0; mult /= 2) {
+
+#if I2C_DEBUG_CLOCK >= 3
+        I2C_TRACE("mult = %d icr_n=%d\n", mult, dev_i2c_freescale_freq_table_size);
+#endif
+
+        for(icr_i = dev_i2c_freescale_freq_table_size - 1; icr_i >= 0; icr_i--) {
+            icr = dev_i2c_freescale_freq_table[icr_i];
+            period = sys_clk_per * (icr * mult);
+
+#if I2C_DEBUG_CLOCK >= 3
+            I2C_TRACE("sys_clk_per=%d the_mult = %d icr[0x%02x]=%d, period = %d.%d (sp = %d.%d)\n",
+                      sys_clk_per, the_mult, icr_i, icr,
+                      period/I2C_CLOCK_NORM, period%I2C_CLOCK_NORM,
+                      period_sp/I2C_CLOCK_NORM, period_sp%I2C_CLOCK_NORM);
+#endif
+
+            if (period == period_sp) {
+
+                I2C_TRACE ("FreqDiv EQ: [0x%02x] the_mult = %d, icr[0x%02x] = %d\n",
+                           i2cf, the_mult, the_icr_i, dev_i2c_freescale_freq_table[the_icr_i]);
+
+                return FREESCALE_I2C_F(mult / 2, icr_i);
+            } else if (period < period_sp) {
+                if(0 == fit) {
+                    if(agr && ((period_sp - period) < period - the_period )) {
+                        the_mult = mult;
+                        the_icr_i = icr_i;
+                        the_period = period;
+                    }
+                    i2cf = FREESCALE_I2C_F(the_mult / 2, the_icr_i);
+
+#ifdef CYGPKG_DEVS_I2C_FREESCALE_I2C_TRACE
+                    I2C_TRACE ("FreqDiv LT: [0x%02x] the_mult = %d, icr[0x%02x] = %d\n",
+                               i2cf, the_mult, the_icr_i, dev_i2c_freescale_freq_table[the_icr_i]);
+                    icr = dev_i2c_freescale_freq_table[the_icr_i];
+                    period = (sys_clk_per * (icr * the_mult));
+                    I2C_TRACE ("    Actual: period = %d.%d[ns], frequency = %d[Hz]\n",
+                               period/I2C_CLOCK_NORM, period%I2C_CLOCK_NORM,
+                               (cyg_uint32)((1000000000 * I2C_CLOCK_NORMLL) / period));
+#endif
+
+                    return i2cf;
+                    break;
+                } else {
+
+#if I2C_DEBUG_CLOCK >= 1
+                    icr = dev_i2c_freescale_freq_table[the_icr_i];
+                    period = (sys_clk_per * (icr * mult));
+
+                    I2C_TRACE ("    Fits left %d: period = %d.%d[ns], frequency = %d[Hz]\n",
+                               fit, period/I2C_CLOCK_NORM, period%I2C_CLOCK_NORM,
+                               (cyg_uint32)((1000000000 * I2C_CLOCK_NORMLL) / period));
+#endif
+
+                    fit --;
+                    break;
+                }
+            } else { // period > period_sp
+                the_period = period;
+                the_mult = mult;
+                the_icr_i = icr_i;
+                i2cf = FREESCALE_I2C_F(mult / 2, the_icr_i);
+
+#if I2C_DEBUG_CLOCK >= 2
+                I2C_TRACE ("FreqDiv FIT %d: [0x%02x] the_mult = %d, icr[0x%02x] = %d\n", 3-fit,
+                           i2cf, the_mult, the_icr_i, dev_i2c_freescale_freq_table[the_icr_i]);
+#endif
+
+            }
+        }
+    }
+
+    I2C_TRACE ("FreqDiv EX: [0x%02x] the_mult = %d, icr[0x%02x] = %d\n",
+               i2cf, the_mult, the_icr_i, dev_i2c_freescale_freq_table[the_icr_i]);
+
+#ifdef CYGPKG_DEVS_I2C_FREESCALE_I2C_TRACE
+                icr = dev_i2c_freescale_freq_table[the_icr_i];
+                period = (sys_clk_per * (icr * the_mult));
+                I2C_TRACE ("    Actual: period = %d[ns], frequency = %d[Hz]\n",
+                           period, (cyg_uint32)((1000000000 * I2C_CLOCK_NORMLL) / period));
+#endif
+
+    return i2cf;
+}
+
+// Set frequency divider.
+// If frequency divider setting is cached simply return the value else
+// calculate one by means of freescale_i2c_freq_div_calc() and cache it.
+
+static inline cyg_uint8
+freescale_i2c_freq_div(cyg_uint32 *period_p)
+{
+    cyg_uint32 period;
+    cyg_uint8 freq;
+
+    if((period = *period_p) & FREESCALE_I2C_DELAY_F_IS_CACHED_M) {
+#if I2C_DEBUG_CLOCK
+        I2C_TRACE("Cached/pre-calculated divider setting: 0x%08x\n", period);
+#endif
+        freq = period & FREESCALE_I2C_DELAY_F_CACHE_M;
+    } else {
+        freq = freescale_i2c_freq_div_calc(period);
+        *period_p = freq | FREESCALE_I2C_DELAY_F_IS_CACHED_M;
+    }
+    return freq;
+}
+
+// Wait untill the bus is free or timeout expires
+// This function performes busy-wait In order to prevent blocking
+// other processes it lowers thread priority prior to entering the spin loop.
+// After the spin loop the original thread priority is restored.
+
+static bool
+wait_bus_ready(freescale_i2c_extra* extra)
+{
+    freescale_i2c_t *i2c_s;
+    bool bus_ready;
+    cyg_priority_t i2c_prio;
+    cyg_tick_count_t time;
+    cyg_handle_t i2c_thread;
+#ifdef CYGPKG_DEVS_I2C_FREESCALE_I2C_TRACE
+    cyg_priority_t i2c_cur_prio;
+    cyg_uint8 __sr;
+
+#endif
+
+    if (!extra->i2c_owner) {
+        I2C_TRACE ("I2C bus ready: 0:\n");
+        i2c_s = FREESCALE_I2C_P (extra->i2c_base);
+        if((
+#ifdef CYGPKG_DEVS_I2C_FREESCALE_I2C_TRACE
+            __sr =
+#endif
+            i2c_s->s) & FREESCALE_I2C_S_BUSY_M)
+        {
+            bus_ready = false;
+            // Decrease priority before busy-waiting.
+            i2c_thread = cyg_thread_self();
+            i2c_prio = cyg_thread_get_priority(i2c_thread);
+#ifdef CYGPKG_DEVS_I2C_FREESCALE_I2C_TRACE
+            i2c_cur_prio = cyg_thread_get_current_priority(i2c_thread);
+#endif
+            I2C_TRACE ("I2C bus ready: 1: priority %d, current priority %d\n",
+                       i2c_prio, i2c_cur_prio);
+            // FIXME: What about current thread priority?
+            I2C_TRACE ("I2C bus ready: 2: sr 0x%02x, cr 0x%02x\n", __sr, i2c_s->c1);
+
+            cyg_thread_set_priority(i2c_thread, CYGNUM_DEV_I2C_SPIN_PRIO);
+
+            I2C_TRACE ("I2C bus ready: 3: priority %d, current priority %d\n",
+                       cyg_thread_get_priority(i2c_thread),
+                       cyg_thread_get_current_priority(i2c_thread));
+            for (time = cyg_current_time();
+                 (cyg_current_time() - time) < CYGNUM_DEV_I2C_SPIN_TIMEOUT;)
+            {
+                if(!(i2c_s->s & FREESCALE_I2C_S_BUSY_M)) {
+                    bus_ready = true;
+                    break;
+                }
+            }
+            cyg_thread_set_priority(i2c_thread, i2c_prio);
+
+            I2C_TRACE ("I2C bus ready: 4: priority %d, current priority %d\n",
+                       cyg_thread_get_priority(i2c_thread),
+                       cyg_thread_get_current_priority(i2c_thread));
+        } else {
+            bus_ready = true;
+        }
+        if(bus_ready) {
+            extra->i2c_got_nack = 0;
+            extra->i2c_owner = 1;
+        }
+    } else {
+        bus_ready = true;
+    }
+
+    I2C_TRACE ("I2C bus ready: Z bus_ready = %d\n", bus_ready);
+
+    return bus_ready;
+}
+
+// Interrupt service routine
+static cyg_uint32
+freescale_i2c_isr(cyg_vector_t vec, cyg_addrword_t data)
+{
+    freescale_i2c_extra *extra = (freescale_i2c_extra *) data;
+    freescale_i2c_t     *i2c_s = FREESCALE_I2C_P (extra->i2c_base);
+    cyg_uint8            sr;
+    cyg_uint32           result = CYG_ISR_HANDLED;
+    cyg_uint8            tx_data = *extra->i2c_data.i2c_tx_data;
+
+    I2C_TRACE ("I2C ISR\n");
+
+    // Read current status
+    sr = i2c_s->s;
+
+    // clear interrupt
+    i2c_s->s |= FREESCALE_I2C_S_IICIF_M;
+
+    if (FREESCALE_I2C_XFER_MODE_TX == extra->i2c_mode) {
+        I2C_TRACE("I2C: TX IRQ handling, sr 0x%02x\n", sr);
+
+        // check for error conditions
+        if (sr & FREESCALE_I2C_S_ARBL_M) {
+            /*
+             * Arbitration lost
+             *
+             * Lost the bus, abort the transfer. count has already been
+             * decremented. Assume the byte did not actually arrive.
+             */
+            extra->i2c_count += 1;
+
+            I2C_STOP(i2c_s);
+            I2C_CLEAR(i2c_s, FREESCALE_I2C_S_ARBL_M);
+
+            result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
+            I2C_TRACE("I2C: TX, bus arbitration error\n");
+        } else if (sr & FREESCALE_I2C_S_RXAK_M) {
+            /*
+             * NACK
+             * Transfer failed. Handled upon exit from the dsr.
+             */
+            extra->i2c_got_nack = 1;
+            I2C_STOP(i2c_s);
+            result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
+            I2C_TRACE("I2C: TX, got NACK\n");
+        } else if (0 == extra->i2c_count) {
+            // No more bytes to send.
+            I2C_TRACE("I2C: TX, no more bytes\n");
+
+            // Last byte
+            if ((0 == extra->i2c_count) && extra->send_stop)
+                I2C_STOP(i2c_s);
+            result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
+        } else {
+            // Send byte
+            I2C_TRACE("I2C: TX, sending 0x%02x\n", tx_data);
+            i2c_s->d = tx_data;
+            extra->i2c_data.i2c_tx_data += 1;
+            extra->i2c_count -= 1;
+
+        }
+    } else if (FREESCALE_I2C_XFER_MODE_RX == extra->i2c_mode) {
+        I2C_TRACE("I2C: RX IRQ handling, sr 0x%02x\n", sr);
+
+        /*
+         * check the actual bus mode, RX transaction starts with initial TX
+         * to transmit the slave address.
+         */
+        if (i2c_s->c1 & FREESCALE_I2C_C1_TX_M) {
+            /*
+             * In TX mode, should be getting an acknowledgement of the slave
+             * address write
+             */
+            if (sr & FREESCALE_I2C_S_ARBL_M) {
+                // Arbitration  lost, stop
+                I2C_STOP(i2c_s);
+                I2C_CLEAR(i2c_s, FREESCALE_I2C_S_ARBL_M);
+
+                result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
+                I2C_TRACE("I2C: RX, initial bus arbitration error\n");
+            } else if (sr & FREESCALE_I2C_S_RXAK_M) {
+                // nack
+                extra->i2c_got_nack = 1;
+                I2C_STOP(i2c_s);
+                result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
+                I2C_TRACE("I2C: RX, got initial NACK\n");
+            } else {
+                /*
+                 * The slave address was transmitted successfully, now switch
+                 * the bus to RX
+                 */
+                volatile cyg_uint8 dummy_read __attribute__((unused));
+
+                I2C_TRACE("I2C: RX, switching bus to RX\n");
+                i2c_s->c1 &= ~FREESCALE_I2C_C1_TX_M;
+
+                // ACK if more bytes
+                if (extra->i2c_count != 1)
+                    i2c_s->c1 &= ~FREESCALE_I2C_C1_TXAK_M;
+                // NACK if asked to
+                else if (extra->i2c_send_nack)
+                    i2c_s->c1 |= FREESCALE_I2C_C1_TXAK_M;
+                // ACK if last btye but not asked to NACK,
+                // meaning there will be another read
+                else
+                    i2c_s->c1 &= ~FREESCALE_I2C_C1_TXAK_M;
+
+                // do a dummy read to get things going
+                dummy_read = i2c_s->d;
+            }
+        }
+        /*
+         * Already in RX mode ...
+         */
+        else if (sr & FREESCALE_I2C_S_ARBL_M) {
+            // Lost the bus? Maybe a spurious stop
+            I2C_CLEAR(i2c_s, FREESCALE_I2C_S_ARBL_M);
+            I2C_TRACE("I2C: RX, bus arbitration error\n");
+            result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
+        } else {
+            I2C_TRACE("I2C: RX, got some data, count %d\n", extra->i2c_count);
+            if (2 == extra->i2c_count) {
+                // One more byte to go, and it should be NACKed.
+                I2C_TRACE("I2C: RX, penultimate byte\n");
+                if (extra->i2c_send_nack)
+                    i2c_s->c1 |= FREESCALE_I2C_C1_TXAK_M;
+            } else if (1 == extra->i2c_count) {
+                // Received the last byte.
+                I2C_TRACE("I2C: RX, last byte\n");
+
+                if (extra->send_stop)
+                    I2C_STOP(i2c_s);
+
+                result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
+            } else if (0 == extra->i2c_count) {
+                /*
+                 * Data beyond last byte ... this should never happen, but see
+                 * the comment in freescale_i2c_handle_xfer()
+                 */
+                CYG_FAIL("I2C: RX sender sending data beyond last byte\n");
+
+                // Forcefully stop the bus and quit
+                I2C_STOP(i2c_s);
+
+                result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
+
+                HAL_INTERRUPT_ACKNOWLEDGE (extra->i2c_isr_id);
+
+                return result;
+            }
+
+            // extract data
+            *(extra->i2c_data.i2c_rx_data) = i2c_s->d;
+            I2C_TRACE("I2C: RX, data: 0x%02x\n",
+                      *(extra->i2c_data.i2c_rx_data));
+
+            extra->i2c_data.i2c_rx_data += 1;
+            extra->i2c_count -= 1;
+        }
+    } else {
+        /*
+         * Invalid state? Some kind of spurious interrupt? Ignore it.
+         */
+        I2C_TRACE("I2C spurious interrupt\n");
+    }
+
+    HAL_INTERRUPT_ACKNOWLEDGE (extra->i2c_isr_id);
+
+    return result;
+}
+
+// Deferred interrupt service routine
+static void
+freescale_i2c_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data)
+{
+    freescale_i2c_extra *extra = (freescale_i2c_extra *) data;
+
+    I2C_TRACE ("I2C DSR -- finishing off\n");
+
+    extra->i2c_completed = 1;
+    cyg_drv_cond_signal(&(extra->i2c_wait));
+}
+
+// A transfer has been started. Wait for completion
+static inline void
+freescale_i2c_doit(freescale_i2c_extra * extra)
+{
+    cyg_drv_mutex_lock(&(extra->i2c_lock));
+    cyg_drv_dsr_lock();
+
+    while (!extra->i2c_completed) {
+        I2C_TRACE ("Waiting ...\n");
+        cyg_drv_cond_wait(&(extra->i2c_wait));
+    }
+
+    cyg_drv_dsr_unlock();
+    cyg_drv_mutex_unlock(&(extra->i2c_lock));
+}
+
+static inline void
+freescale_i2c_stopit(freescale_i2c_extra * extra)
+{
+    extra->i2c_lost_arb = 0;
+    extra->i2c_owner = 0;
+    extra->i2c_mode = FREESCALE_I2C_XFER_MODE_INVALID;
+}
+
+void
+freescale_i2c_stop(const cyg_i2c_device * dev)
+{
+    freescale_i2c_extra *extra = (freescale_i2c_extra *) dev->i2c_bus->i2c_extra;
+    freescale_i2c_t     *i2c_s = FREESCALE_I2C_P (extra->i2c_base);
+
+    I2C_STOP(i2c_s);
+
+    freescale_i2c_stopit(extra);
+}
+
+static cyg_bool
+freescale_i2c_handle_xfer(cyg_i2c_device * dev, int address)
+{
+    freescale_i2c_extra  *extra = (freescale_i2c_extra *) dev->i2c_bus->i2c_extra;
+    cyg_uint8             data = *extra->i2c_data.i2c_tx_data;
+    freescale_i2c_t      *i2c_s = FREESCALE_I2C_P (extra->i2c_base);
+    cyg_uint8 freq;
+
+    // Nothing to do
+    if (extra->i2c_count == 0)
+        return false;
+
+    // Take the bus ownership
+    if(!wait_bus_ready (extra))
+        return false;
+
+    // set the bus frequency
+    freq = freescale_i2c_freq_div(dev->i2c_delay ?
+                                  &dev->i2c_delay :
+                                  &extra->i2c_delay);
+
+    i2c_s->f = freq;
+    I2C_TRACE("Set f = 0x%02x\n", i2c_s->f);
+
+    if (extra->send_start) {
+        I2C_TRACE ("Doing start: restart: %s\n",
+                   i2c_s->c1 & FREESCALE_I2C_C1_MST_M ? "yes" : "no");
+
+        /*
+         * If we are the current master, use repeat start
+         */
+        if (i2c_s->c1 & FREESCALE_I2C_C1_MST_M) {
+            I2C_REPEAT_START(i2c_s);
+        } else {
+#if 0
+            i2c_s->c1 &= ~0x3fu;
+#endif
+            I2C_START(i2c_s);
+        }
+
+        I2C_TRACE ("STATUS: sr 0x%02x, cr 0x%02x\n", i2c_s->s, i2c_s->c1);
+
+        /*
+         * Write the address out and wait for interrupt
+         */
+        I2C_TRACE ("Address: %d [0x%x]\n", address, address);
+        i2c_s->d = address;
+        return true;
+    } else if (extra->i2c_mode == FREESCALE_I2C_XFER_MODE_TX) {
+        // TX transfer without a start
+        I2C_TRACE ("TX transfer without start\n");
+
+        extra->i2c_data.i2c_tx_data += 1;
+        extra->i2c_count -= 1;
+        i2c_s->d = data;
+
+        // Single byte transfer
+        if (extra->send_stop && (extra->i2c_count == 0))
+            I2C_STOP(i2c_s);
+    } else {
+        // RX transfer without a start
+#if 0
+        /*
+         * This is how it would be done in theory; in practice, because the
+         * actual reading is IRQ driven, we are stuck in the isr handler until
+         * such time the sender will stop sending data, but since the sender
+         * will continue sending data until it receives the stop signal from us,
+         * if someone makes an RX call with the 'don't send stop' flag, the
+         * incoming data stream will never stop (until there is an error).
+         *
+         * And since we can never allow an RX call with the 'don't send stop'
+         * flag, we can never do send without explicit start either.
+         */
+        I2C_TRACE ("RX transfer without start\n");
+        // Single byte transfer, set the STOP bit
+        if (extra->send_stop && (extra->i2c_count == 1))
+            I2C_STOP(i2c_s);
+
+        // Do not ACK last byte per user request
+        if (!extra->i2c_send_nack && (extra->i2c_count == 1)) {
+            I2C_TRACE ("RX: NACK for last byte in single byte transfer\n");
+            i2c_s->c1 |= FREESCALE_I2C_C1_TXAK_M;
+        }
+#else
+        CYG_FAIL( "I2C driver does not support piecemeal RX\n" );
+#endif
+    }
+
+    return true;
+}
+
+cyg_uint32
+freescale_i2c_tx(cyg_i2c_device * dev, cyg_bool send_start,
+                 const cyg_uint8 *tx_data, cyg_uint32 count, cyg_bool send_stop)
+{
+    freescale_i2c_extra *extra = (freescale_i2c_extra *) dev->i2c_bus->i2c_extra;
+    extra->send_stop = send_stop;
+    extra->send_start = send_start;
+    extra->i2c_count = count;
+
+    if (!extra->i2c_lost_arb) {
+        extra->i2c_completed = 0;
+        extra->i2c_mode = FREESCALE_I2C_XFER_MODE_TX;
+
+        if (send_start || !extra->i2c_got_nack) {
+            I2C_TRACE
+                  ("I2C: TX to %2x, data %2x, count: %4d, START flag: %s\n",
+                   dev->i2c_address, *tx_data, count,
+                   (send_start == true) ? "true" : "false");
+            extra->i2c_data.i2c_tx_data = tx_data;
+            if (!freescale_i2c_handle_xfer (dev, FREESCALE_I2C_A1_AD (dev->i2c_address,
+                                                                      FREESCALE_I2C_MODE_MW))
+                )
+            {
+                return 0;
+            }
+
+            /*
+             * Now block till we are done
+             */
+            freescale_i2c_doit(extra);
+        }
+
+    }
+
+    if (send_stop) {
+        I2C_TRACE("I2C: TX send stop\n");
+        freescale_i2c_stopit(extra);
+    }
+
+    I2C_TRACE("I2C: TX count %d\n", extra->i2c_count);
+
+    /*
+     * tx() should return the number of bytes actually transmitted.
+     * ISR() increments extra->count after a failure, which leads to
+     * an edge condition when send_start and there is no acknowledgment
+     * of the address byte.
+     */
+    if (extra->i2c_count > count)
+        return 0;
+
+    return count - extra->i2c_count;
+}
+
+cyg_uint32
+freescale_i2c_rx(cyg_i2c_device * dev, cyg_bool send_start,
+                 cyg_uint8 *rx_data, cyg_uint32 count, cyg_bool send_nack,
+                 cyg_bool send_stop)
+{
+    freescale_i2c_extra *extra = (freescale_i2c_extra *) dev->i2c_bus->i2c_extra;
+
+    /*
+     * see comments in freescale_i2c_handle_xfer() as to why this assert.
+     */
+    CYG_ASSERT( send_start && send_stop,
+                "I2C driver does not support piecemeal RX, i.e., the "
+                "send_start and send_stop parameters must always be set to "
+                "true\n");
+
+    extra->i2c_count = count;
+    extra->i2c_send_nack = send_nack;
+    extra->send_stop = send_stop;
+    extra->send_start = send_start;
+
+    if (!extra->i2c_lost_arb) {
+        extra->i2c_completed = 0;
+        extra->i2c_data.i2c_rx_data = rx_data;
+        extra->i2c_mode = FREESCALE_I2C_XFER_MODE_RX;
+        I2C_TRACE("I2C: RX to %2x, count: %4d, START flag: %s\n",
+                  dev->i2c_address, count,
+                  (send_start == true) ? "true" : "false");
+
+        if (!freescale_i2c_handle_xfer (dev, FREESCALE_I2C_A1_AD (dev->i2c_address,
+                                                                  FREESCALE_I2C_MODE_MR))
+            )
+        {
+            return 0;
+        }
+
+        /*
+         * Now block till we are done
+         */
+        freescale_i2c_doit(extra);
+    }
+
+    if (send_stop) {
+        I2C_TRACE("I2C: RX send stop\n");
+        freescale_i2c_stopit(extra);
+    }
+
+    return count - extra->i2c_count;
+}
+
+// ----------------------------------------------------------------------------
+// The functions needed for all I2C devices.
+
+void
+freescale_i2c_init(struct cyg_i2c_bus *bus)
+{
+    freescale_i2c_extra *extra = (freescale_i2c_extra *) bus->i2c_extra;
+    freescale_i2c_t     *i2c_s = FREESCALE_I2C_P (extra->i2c_base);
+    cyg_uint32 freq;
+
+    I2C_TRACE("I2C INIT0 bus base 0x%08x Pins: 0x%08x, 0x%08x Clock 0x%08x\n",
+              extra->i2c_base, extra->hal_p->pin_sda, extra->hal_p->pin_scl,
+              extra->hal_p->clock);
+
+    // Bring clock to the sevice
+    CYGHWR_IO_CLOCK_ENABLE(extra->hal_p->clock);
+    // setup SDA/SCL pins, the I2C driver to take care of the rest.
+    CYGHWR_IO_FREESCALE_I2C_PIN(extra->hal_p->pin_sda);
+    CYGHWR_IO_FREESCALE_I2C_PIN(extra->hal_p->pin_scl);
+
+    cyg_drv_mutex_init(&extra->i2c_lock);
+    cyg_drv_cond_init(&extra->i2c_wait, &extra->i2c_lock);
+    cyg_drv_interrupt_create(extra->i2c_isr_id,
+                             extra->i2c_isr_pri,
+                             (cyg_addrword_t)extra,
+                             &freescale_i2c_isr,
+                             &freescale_i2c_dsr,
+                             &(extra->i2c_interrupt_handle),
+                             &(extra->i2c_interrupt_data));
+    cyg_drv_interrupt_attach(extra->i2c_interrupt_handle);
+
+    if (!extra->i2c_owner) {
+#ifdef CYGPKG_DEVS_I2C_FREESCALE_I2C_TRACE
+        cyg_uint8 cr;
+#endif
+        cyg_uint8 sr;
+
+        extra->i2c_got_nack = 0;
+        extra->i2c_owner = 1;
+        sr = i2c_s->s;
+#ifdef CYGPKG_DEVS_I2C_FREESCALE_I2C_TRACE
+        cr = i2c_s->c1;
+#endif
+
+        I2C_TRACE ("BUS: INIT sr 0x%02x, cr 0x%02x\n", sr, cr);
+
+        while (sr & FREESCALE_I2C_S_BUSY_M) {
+            sr = i2c_s->s;
+        }
+    }
+
+#if 1
+    i2c_s->c2 = extra->c2_cfg;    // some options set in CDL
+    i2c_s->flt = extra->flt_cfg;  // glitch filter
+#endif
+
+    /*
+     * bus speed: set the frequency divider
+     *
+     * The bus can run up to clock/20, but can only achieve full loads
+     * under 100kHz
+     */
+    I2C_TRACE("I2C INIT1: extra->i2c_delay = %d\n", extra->i2c_delay);
+
+    freq = freescale_i2c_freq_div(&extra->i2c_delay);
+
+    I2C_TRACE("I2C INIT2: -> extra->i2c_delay = 0x%08x\n", extra->i2c_delay);
+
+    i2c_s->f = freq;
+
+    /*
+     * Signal start -- selects master mode
+     * Enable I2C
+     * Enable Interrupt
+     */
+    i2c_s->c1 |= (FREESCALE_I2C_C1_IICEN_M | FREESCALE_I2C_C1_IICIE_M);
+
+    // Interrupts can now be safely unmasked
+    HAL_INTERRUPT_UNMASK(extra->i2c_isr_id);
+}
+
+//-----------------------------------------------------------------------------
+// Bus instances.
+
+#include <cyg/io/i2c_freescale_buses.inl>
+
+//---------------------------------------------------------------------------
+// EOF i2c_freescale.c
diff --git a/packages/devs/serial/arm/lpc24xx/current/ChangeLog b/packages/devs/serial/arm/lpc24xx/current/ChangeLog
--- a/packages/devs/serial/arm/lpc24xx/current/ChangeLog
+++ b/packages/devs/serial/arm/lpc24xx/current/ChangeLog
@@ -1,3 +1,14 @@
+2011-12-21  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/ser_arm_lpc24xx.cdl:
+	Fixed interrupt priority. [ Bugzilla 1001432 ]
+	
+2010-12-29  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/ser_arm_lpc24xx.cdl:
+	* include/arm_lpc24xx_ser.inl:
+	Added support for LPC17XX CPUs.
+
 2008-07-07 Uwe Kindler <uwe_kindler@web.de>
 
 	* include/arm_lpc24xx_ser.inl: 
diff --git a/packages/devs/serial/arm/lpc24xx/current/cdl/ser_arm_lpc24xx.cdl b/packages/devs/serial/arm/lpc24xx/current/cdl/ser_arm_lpc24xx.cdl
--- a/packages/devs/serial/arm/lpc24xx/current/cdl/ser_arm_lpc24xx.cdl
+++ b/packages/devs/serial/arm/lpc24xx/current/cdl/ser_arm_lpc24xx.cdl
@@ -2,13 +2,13 @@
 #
 #      ser_arm_lpc24xx.cdl
 #
-#      eCos serial ARM/LPC24XX configuration data
+#      eCos serial ARM LPC24XX / Cortex-M LPC17XX configuration data
 #
 # ====================================================================
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Free Software Foundation, Inc.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2011 Free Software Foundation, Inc.
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -39,9 +39,9 @@
 # ====================================================================
 ######DESCRIPTIONBEGIN####
 #
-# Author(s):      Uwe Kindler  
+# Author(s):      Uwe Kindler
 # Original data:  gthomas, jskov
-# Contributors:
+# Contributors:   ilijak
 # Date:           2008-07-06
 #
 #####DESCRIPTIONEND####
@@ -49,18 +49,18 @@
 # ====================================================================
 
 cdl_package CYGPKG_IO_SERIAL_ARM_LPC24XX {
-    display       "ARM LPC24xx serial device drivers"
+    display       "ARM LPC24XX / Cortex-M LPC17XX serial device drivers"
 
     parent        CYGPKG_IO_SERIAL_DEVICES
     active_if     CYGPKG_IO_SERIAL
-    active_if     CYGPKG_HAL_ARM_LPC24XX
+    active_if     ( CYGPKG_HAL_ARM_LPC24XX || CYGPKG_HAL_CORTEXM_LPC17XX )
     implements    CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO
     requires      CYGPKG_ERROR
     include_dir   cyg/io
 
     description   "
-           This option enables the serial device drivers for the
-           ARM LPC24xx."
+           This option enables the serial device drivers for the ARM
+           LPC24XX and Cortex-M LPC17XX."
 
     # FIXME: This really belongs in the GENERIC_16X5X package
     cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED {
@@ -70,6 +70,10 @@ cdl_package CYGPKG_IO_SERIAL_ARM_LPC24XX
         puts $::cdl_header "#define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 4"
     }
 
+    requires {
+        is_active(CYGPKG_HAL_CORTEXM_LPC17XX)
+        implies CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME == "1"
+    }
 
     define_proc {
         puts $::cdl_system_header "/***** serial driver proc output start *****/"
@@ -77,53 +81,64 @@ cdl_package CYGPKG_IO_SERIAL_ARM_LPC24XX
         puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_arm_lpc24xx.h>"
         puts $::cdl_system_header "/*****  serial driver proc output end  *****/"
     }
-    
+
+    # For backward compatibility with LPC24XX platforms
+    cdl_option CYGNUM_IO_SERIAL_IRQ_PRIORITY_MIN {
+        display       "Interrupt priority levels"
+        flavor        data
+        calculated    { CYGNUM_HAL_IRQ_PRIORITY_MIN ? CYGNUM_HAL_IRQ_PRIORITY_MIN : 15 }
+        description   "
+            For backward compatibility with LPC 24XX plarforms that
+            do not have CYGNUM_HAL_IRQ_PRIORITY_MIN defined."
+    }
+
     # Support up to 4 on-chip UART modules. The number may vary between
     # processor variants so it is easy to update this here
     for { set ::channel 0 } { $::channel < 4 } { incr ::channel } {
-    
+
         cdl_interface CYGINT_IO_SERIAL_LPC24XX_UART[set ::channel] {
-            display     "Platform provides UART [set ::channel]"
-            flavor      bool
-            description "
-                This interface will be implemented if the specific LPC24xx
-                processor being used has on-chip UART [set ::channel], and if
-                that UART is accessible on the target hardware."
+            display       "Platform provides UART [set ::channel]"
+            flavor        bool
+            description   "
+                This interface will be implemented if the specific
+                LPC24XX / LPC17XX processor being used has on-chip UART
+                [set ::channel], and if that UART is accessible on the
+                target hardware."
         }
 
         cdl_component CYGPKG_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel] {
-            display       "ARM LPC24cxx UART [set ::channel] driver"
+            display       "ARM LPC24XX / Cortex LPC17XX UART [set ::channel] driver"
             flavor        bool
             active_if     CYGINT_IO_SERIAL_LPC24XX_UART[set ::channel]
             default_value 1
 
-           implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED
-           implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW
-           implements CYGINT_IO_SERIAL_LINE_STATUS_HW
+            implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED
+            implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW
+            implements CYGINT_IO_SERIAL_LINE_STATUS_HW
 
-           description   "
-                This option includes the serial device driver for the ARM
-                LPC24xx UART [set ::channel]."
+            description   "
+                This option includes the serial device driver for the
+                ARM LPC24XX / LPC17XX UART [set ::channel]."
 
             cdl_option CYGDAT_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel]_NAME {
                 display       "Device name for UART [set ::channel]"
                 flavor        data
-                default_value   [format {"\"/dev/ser%d\""} $::channel]
+                default_value [format {"\"/dev/ser%d\""} $::channel]
                 description   "
                     This option specifies the name of the serial device
-                    for the ARM LPC24xx UART [set ::channel]."
+                    for the ARM LPC24XX / LPC17XX UART [set ::channel]."
             }
 
             cdl_option CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel]_BAUD {
                 display       "Baud rate for UART [set ::channel]"
                 flavor        data
-                legal_values  { 50 75 110 "134_5" 150 200 300 600 1200 1800 
+                legal_values  { 50 75 110 "134_5" 150 200 300 600 1200 1800
                                 2400 3600 4800 7200 9600 14400 19200 38400
                                 57600 115200 230400 }
                 default_value 38400
                 description   "
                     This option specifies the default baud rate (speed)
-                    for the ARM LPC24xx UART [set ::channel]."
+                    for the ARM LPC24XX / LPC17XX UART [set ::channel]."
             }
 
             cdl_option CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel]_BUFSIZE {
@@ -133,28 +148,25 @@ cdl_package CYGPKG_IO_SERIAL_ARM_LPC24XX
                 default_value 128
                 description   "
                     This option specifies the size of the internal buffers
-                    used for the ARM LPC24xx UART [set ::channel]."
+                    used for the ARM LPC24XX / LPC17XX UART [set ::channel]."
             }
-            
+
             cdl_option CYGNUM_IO_SERIAL_ARM_LPC24XX_SERIAL[set ::channel]_INTPRIO {
                 display       "Interrupt priority of UART [set ::channel]"
                 flavor        data
-                legal_values  0 to 15
-                default_value 15
+                legal_values  0 to CYGNUM_IO_SERIAL_IRQ_PRIORITY_MIN
+                default_value CYGNUM_IO_SERIAL_IRQ_PRIORITY_MIN
                 description   "
-                    This option selects the interupt priority for the
-                    UART [set ::channel] interrupts. There are 16
-                    priority levels corresponding to the values 0
-                    through 15 decimal, of which 15 is the lowest
-                    priority. The reset value of these registers
-                    defaults all interrupt to the lowest priority,
-                    allowing a single write to elevate the priority of
-                    an individual interrupt."
+                    This option selects the interupt priority for
+                    the UART [set ::channel] interrupts. The
+                    reset value of these registers defaults all interrupt
+                    to the lowest priority, allowing a single write to
+                    elevate the priority of an individual interrupt."
             }
         }
     }
 
-     cdl_component CYGPKG_IO_SERIAL_ARM_LPC24XX_TESTING {
+    cdl_component CYGPKG_IO_SERIAL_ARM_LPC24XX_TESTING {
         display    "Testing parameters"
         flavor     bool
         calculated 1
@@ -163,7 +175,7 @@ cdl_package CYGPKG_IO_SERIAL_ARM_LPC24XX
         implements CYGINT_IO_SERIAL_TEST_SKIP_9600
         implements CYGINT_IO_SERIAL_TEST_SKIP_115200
         implements CYGINT_IO_SERIAL_TEST_SKIP_PARITY_EVEN
-        
+
         cdl_option CYGPRI_SER_TEST_SER_DEV {
             display       "Serial device used for testing"
             flavor        data
diff --git a/packages/devs/serial/arm/lpc24xx/current/include/arm_lpc24xx_ser.inl b/packages/devs/serial/arm/lpc24xx/current/include/arm_lpc24xx_ser.inl
--- a/packages/devs/serial/arm/lpc24xx/current/include/arm_lpc24xx_ser.inl
+++ b/packages/devs/serial/arm/lpc24xx/current/include/arm_lpc24xx_ser.inl
@@ -2,7 +2,7 @@
 //
 //      io/serial/arm/arm_lpc24xx_ser.inl
 //
-//      ARM LPC24XX Serial I/O definitions
+//      ARM LPC24XX / Cortex-M LPC17XX Serial I/O definitions
 //
 //==========================================================================
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
@@ -40,10 +40,10 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):    Uwe Kindler
-// Contributors: gthomas, jlarmour
+// Contributors: gthomas, jlarmour, ilijak
 // Date:         2008-06-07
-// Purpose:      LPC24XX Serial I/O module (interrupt driven version)
-// Description: 
+// Purpose:      LPC24XX and LPC17XX Serial I/O module (interrupt driven version)
+// Description:
 //
 //####DESCRIPTIONEND####
 //
@@ -54,8 +54,12 @@
 //                               INCLUDES
 //==========================================================================
 #include <cyg/hal/hal_intr.h>
-#include <cyg/hal/lpc24xx_misc.h>
 
+#ifdef CYGPKG_HAL_CORTEXM_LPC17XX
+# include <cyg/hal/lpc17xx_misc.h>
+#else
+# include <cyg/hal/lpc24xx_misc.h>
+#endif
 
 //==========================================================================
 //                              STATIC DATA
diff --git a/packages/devs/serial/cortexm/a2fxxx/current/ChangeLog b/packages/devs/serial/cortexm/a2fxxx/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/cortexm/a2fxxx/current/ChangeLog
@@ -0,0 +1,30 @@
+2011-03-20  Christophe Coutand  <ecos@hotmail.co.uk>
+
+    * cdl/ser_cortexm_a2fxxx.cdl
+    * include/ser_cortexm_a2fxxx.inl
+    New package -- Actel smartfusion Serial Driver
+    [Bugzilla 1001291]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/serial/cortexm/a2fxxx/current/cdl/ser_cortexm_a2fxxx.cdl b/packages/devs/serial/cortexm/a2fxxx/current/cdl/ser_cortexm_a2fxxx.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/cortexm/a2fxxx/current/cdl/ser_cortexm_a2fxxx.cdl
@@ -0,0 +1,219 @@
+# ====================================================================
+#
+#      ser_cortexm_a2fxxx.cdl
+#
+#      eCos serial Cortex-M3/Actel Smartfusion configuration data
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      ccoutand
+# Original data:  gthomas
+# Contributors:
+# Date:           2011-03-20
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_IO_SERIAL_CORTEXM_A2FXXX {
+    display       "Cortex-M3/Actel Smartfusion serial device drivers"
+
+    parent        CYGPKG_IO_SERIAL_DEVICES
+    active_if     CYGPKG_IO_SERIAL
+    active_if     CYGPKG_HAL_CORTEXM_A2FXXX
+    implements    CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO
+
+
+    requires      CYGPKG_ERROR
+    include_dir   cyg/io
+
+    description   "
+           This option enables the serial device drivers for the
+           Cortex-M3/Actel Smartfusion."
+
+    # FIXME: This really belongs in the GENERIC_16X5X package
+    cdl_interface CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED {
+        display   "Generic 16x5x serial driver required"
+    }
+    define_proc {
+        puts $::cdl_header "#define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 4"
+    }
+
+    requires { CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME == "1" }
+
+    define_proc {
+        puts $::cdl_system_header "/***** serial driver proc output start *****/"
+        puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_INL <cyg/io/ser_cortexm_a2fxxx.inl>"
+        puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_GENERIC_16X5X_CFG <pkgconf/io_serial_cortexm_a2fxxx.h>"
+        puts $::cdl_system_header "/*****  serial driver proc output end  *****/"
+    }
+
+    cdl_component CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0 {
+        display       "Cortex-M3/Actel Smartfusion serial port 0 driver"
+        flavor        bool
+        default_value 1
+
+        implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED
+        implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW
+        implements CYGINT_IO_SERIAL_LINE_STATUS_HW
+
+        description   "
+            This option includes the serial device driver for the
+            Cortex-M3/Actel Smartfusion port 0."
+
+        cdl_option CYGDAT_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_NAME {
+            display       "Device name for the serial port 0 driver"
+            flavor         data
+            default_value {"\"/dev/ser0\""}
+            description   "
+                This option specifies the name of the serial device
+                for the Cortex-M3/Actel Smartfusion port 0."
+        }
+
+        cdl_option CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_BAUD {
+            display       "Baud rate for the serial port 0 driver"
+            flavor         data
+            legal_values  { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400
+                            3600 4800 7200 9600 14400 19200 38400
+                            57600 115200 230400 }
+            default_value 38400
+            description   "
+                This option specifies the default baud rate (speed)
+                for the Cortex-M3/Actel Smartfusion port 0."
+        }
+
+        cdl_option CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_BUFSIZE {
+            display       "Buffer size for the serial port 0 driver"
+            flavor         data
+            legal_values   0 to 8192
+            default_value  128
+            description   "
+                This option specifies the size of the internal buffers
+                used for the Cortex-M3/Actel Smartfusion port 0."
+        }
+
+        cdl_option CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_INTPRIO {
+            display       "Interrupt priority of the serial port 0 ISR"
+            flavor         data
+            default_value { CYGNUM_DEVS_SERIAL_CORTEXM_A2FXXX_SERIAL0_ISR_SP }
+            requires { is_active(CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_INTPRIO)
+                           implies CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_INTPRIO !=
+                           CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_INTPRIO }
+            description "
+                  This option specifies the interrupt priority of the
+                  ISR of the serial port 1 interrupt in the NVIC."
+        }
+
+    }
+
+    cdl_component CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1 {
+        display       "Cortex-M3/Actel Smartfusion serial port 1 driver"
+        flavor        bool
+        default_value 0
+
+        implements CYGINT_IO_SERIAL_GENERIC_16X5X_REQUIRED
+        implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW
+        implements CYGINT_IO_SERIAL_LINE_STATUS_HW
+
+        description   "
+            This option includes the serial device driver for the
+            Cortex-M3/Actel Smartfusion port 1."
+
+        cdl_option CYGDAT_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_NAME {
+            display       "Device name for the serial port 1 driver"
+            flavor         data
+            default_value {"\"/dev/ser1\""}
+            description   "
+                This option specifies the name of the serial device
+                for the Cortex-M3/Actel Smartfusion port 1."
+        }
+
+        cdl_option CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_BAUD {
+            display       "Baud rate for the serial port 1 driver"
+            flavor         data
+            legal_values  { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400
+                            3600 4800 7200 9600 14400 19200 38400
+                            57600 115200 230400 }
+            default_value 38400
+            description   "
+                This option specifies the default baud rate (speed)
+                for the Cortex-M3/Actel Smartfusion port 1."
+         }
+
+         cdl_option CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_BUFSIZE {
+             display       "Buffer size for the serial port 1 driver"
+             flavor         data
+             legal_values   0 to 8192
+             default_value  128
+             description   "
+                 This option specifies the size of the internal
+                 buffers used for the Cortex-M3/Actel Smartfusion port 1."
+         }
+
+         cdl_option CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_INTPRIO {
+              display      "Interrupt priority of the serial port 1 ISR"
+              flavor        data
+              default_value { CYGNUM_DEVS_SERIAL_CORTEXM_A2FXXX_SERIAL0_ISR_SP }
+              description "
+                  This option specifies the interrupt priority of the
+                  ISR of the serial port 1 interrupt in the NVIC."
+         }
+    }
+
+    cdl_component CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_TESTING {
+        display    "Testing parameters"
+        flavor     bool
+        calculated 1
+        active_if  CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0
+
+        implements CYGINT_IO_SERIAL_TEST_SKIP_9600
+        implements CYGINT_IO_SERIAL_TEST_SKIP_115200
+        implements CYGINT_IO_SERIAL_TEST_SKIP_PARITY_EVEN
+
+        cdl_option CYGPRI_SER_TEST_SER_DEV {
+            display       "Serial device used for testing"
+            flavor        data
+            default_value { CYGDAT_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_NAME }
+        }
+
+        define_proc {
+            puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"a2fxxx\""
+            puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV  \"/dev/tty0\""
+        }
+    }
+}
+
+# EOF ser_cortexm_a2fxx.cdl
diff --git a/packages/devs/serial/cortexm/a2fxxx/current/include/ser_cortexm_a2fxxx.inl b/packages/devs/serial/cortexm/a2fxxx/current/include/ser_cortexm_a2fxxx.inl
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/cortexm/a2fxxx/current/include/ser_cortexm_a2fxxx.inl
@@ -0,0 +1,210 @@
+//==========================================================================
+//
+//      ser_cortexm_a2fxxx.inl
+//
+//      eCos serial Cortex-M3/Actel Smartfusion I/O definitions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors:
+// Date:         2011-03-20
+// Purpose:      Cortex-M3/Actel Smartfusion Serial I/O module (interrupt driven version)
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/hal_intr.h>
+
+//-----------------------------------------------------------------------------
+// Baud rate specification
+
+// Baud rate specification
+static const unsigned int select_baud[] =
+{
+    9999,    // Unused
+    50,
+    75,
+    110,
+    134.5,
+    150,
+    200,
+    300,
+    600,
+    1200,
+    1800,
+    2400,
+    3600,
+    4800,
+    7200,
+    9600,
+    14400,
+    19200,
+    38400,
+    57600,
+    115200,
+    230400
+};
+
+
+//-----------------------------------------------------------------------------
+// Return baudrate devisor for certain baudrate
+
+unsigned short a2fxxx_baud_generator(pc_serial_info *ser_chan,
+                                      cyg_serial_baud_rate_t  baud)
+{
+    cyg_uint8 pclk_id = 0;
+    switch (ser_chan->base)
+    {
+        case CYGHWR_HAL_A2FXXX_UART0:
+             pclk_id = 0;
+             break;
+
+        case CYGHWR_HAL_A2FXXX_UART1:
+             pclk_id = 1;
+             break;
+        default:
+            CYG_FAIL("Invalid UART base address");
+    } // (ser_chan->base)
+
+    return CYG_HAL_CORTEXM_A2FXXX_BAUD_GENERATOR(pclk_id, select_baud[baud]);
+}
+
+
+#define CYG_IO_SERIAL_GENERIC_16X5X_CHAN_BAUD_GENERATOR(_ser_chan_, _baud_) \
+        a2fxxx_baud_generator((_ser_chan_), (_baud_))
+
+
+#ifdef CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0
+static pc_serial_info a2fxxx_serial_info0 =
+  { CYGHWR_HAL_A2FXXX_UART0,
+    CYGNUM_HAL_INTERRUPT_UART0,
+    CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_INTPRIO
+  };
+
+#if CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_BUFSIZE > 0
+static unsigned char
+a2fxxx_serial_out_buf0[CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_BUFSIZE];
+static unsigned char
+a2fxxx_serial_in_buf0[CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_BUFSIZE];
+
+static SERIAL_CHANNEL_USING_INTERRUPTS(a2fxxx_serial_channel0,
+                                       pc_serial_funs,
+                                       a2fxxx_serial_info0,
+                                       CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_BAUD),
+                                       CYG_SERIAL_STOP_DEFAULT,
+                                       CYG_SERIAL_PARITY_DEFAULT,
+                                       CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                                       CYG_SERIAL_FLAGS_DEFAULT,
+                                       &a2fxxx_serial_out_buf0[0],
+                                       sizeof(a2fxxx_serial_out_buf0),
+                                       &a2fxxx_serial_in_buf0[0],
+                                       sizeof(a2fxxx_serial_in_buf0)
+    );
+#else
+static SERIAL_CHANNEL(a2fxxx_serial_channel0,
+                      pc_serial_funs,
+                      a2fxxx_serial_info0,
+                      CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_BAUD),
+                      CYG_SERIAL_STOP_DEFAULT,
+                      CYG_SERIAL_PARITY_DEFAULT,
+                      CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                      CYG_SERIAL_FLAGS_DEFAULT
+    );
+#endif
+
+DEVTAB_ENTRY(a2fxxx_serial_io0,
+             CYGDAT_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0_NAME,
+             0,                     // Does not depend on a lower
+                                    // level interface
+             &cyg_io_serial_devio,
+             pc_serial_init,
+             pc_serial_lookup,     // Serial driver may need initializing
+             &a2fxxx_serial_channel0
+    );
+#endif //  CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0
+
+#ifdef CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1
+static pc_serial_info a2fxxx_serial_info1 =
+  { CYGHWR_HAL_A2FXXX_UART1,
+    CYGNUM_HAL_INTERRUPT_UART1,
+    CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_INTPRIO
+  };
+#if CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_BUFSIZE > 0
+static unsigned char
+a2fxxx_serial_out_buf1[CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_BUFSIZE];
+static unsigned char
+a2fxxx_serial_in_buf1[CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_BUFSIZE];
+
+static SERIAL_CHANNEL_USING_INTERRUPTS(a2fxxx_serial_channel1,
+                                       pc_serial_funs,
+                                       a2fxxx_serial_info1,
+                                       CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_BAUD),
+                                       CYG_SERIAL_STOP_DEFAULT,
+                                       CYG_SERIAL_PARITY_DEFAULT,
+                                       CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                                       CYG_SERIAL_FLAGS_DEFAULT,
+                                       &a2fxxx_serial_out_buf1[0],
+                                       sizeof(a2fxxx_serial_out_buf1),
+                                       &a2fxxx_serial_in_buf1[0],
+                                       sizeof(a2fxxx_serial_in_buf1)
+    );
+#else
+static SERIAL_CHANNEL(a2fxxx_serial_channel1,
+                      pc_serial_funs,
+                      a2fxxx_serial_info1,
+                      CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_BAUD),
+                      CYG_SERIAL_STOP_DEFAULT,
+                      CYG_SERIAL_PARITY_DEFAULT,
+                      CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                      CYG_SERIAL_FLAGS_DEFAULT
+    );
+#endif
+
+DEVTAB_ENTRY(a2fxxx_serial_io1,
+             CYGDAT_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1_NAME,
+             0,                     // Does not depend on a lower
+                                    // level interface
+             &cyg_io_serial_devio,
+             pc_serial_init,
+             pc_serial_lookup,     // Serial driver may need initializing
+             &a2fxxx_serial_channel1
+    );
+#endif //  CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1
+
+// EOF ser_cortexm_a2fxxx.inl
diff --git a/packages/devs/serial/cortexm/stm32/current/ChangeLog b/packages/devs/serial/cortexm/stm32/current/ChangeLog
--- a/packages/devs/serial/cortexm/stm32/current/ChangeLog
+++ b/packages/devs/serial/cortexm/stm32/current/ChangeLog
@@ -1,3 +1,42 @@
+2012-04-02  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* src/stm32_serial.h: Revert unnecessary change in previous
+	commit, reinstating previous code.
+	* src/stm32_serial.c (stm32_serial_config_port): Ditto.
+
+2011-12-15  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/ser_cortexm_stm32.cdl: Default baud rates to the HAL
+	diag console channel. Add support for serial port 5
+	(USART6 in STM32 speak). Select serial/tty test devices better
+	according to the configuration.
+	* src/stm32_serial.c: Support serial port 5. Make use of AFIO
+	remap specific to F1 processors.
+
+2010-12-31  John Dallaway  <john@dallaway.org.uk>
+
+	* src/stm32_serial.c, src/stm32_serial.h: Set the M bit when
+	configuring for 8 data bits + parity bit. [ Bugzilla 1001068 ]
+
+2009-12-03  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/ser_cortexm_stm32.cdl:
+	* src/stm32_serial.c (stm32_serial_info, stm32_serial_info0)
+	(stm32_serial_info1, stm32_serial_info2, stm32_serial_info3)
+	(stm32_serial_info4, stm32_serial_init):
+	Add configuration options to set serial ISR interrupt priorities.
+
+2009-07-02  Nick Garnett  <nickg@ecoscentric.com>
+
+	* src/stm32_serial.c (stm32_serial_info)
+	(stm32_serial_config_port): Add support for UART pin remap.
+
+2009-06-29  Nick Garnett  <nickg@ecoscentric.com>
+
+	* src/stm32_serial.c (stm32_serial_info)
+	(stm32_serial_config_port): Add support for individual clock
+	enable on each UART.
+
 2008-10-07  Nick Garnett  <nickg@ecoscentric.com>
 
 	* cdl/ser_cortexm_stm32.cdl: 
@@ -10,7 +49,7 @@ 2008-10-07  Nick Garnett  <nickg@ecoscen
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/devs/serial/cortexm/stm32/current/cdl/ser_cortexm_stm32.cdl b/packages/devs/serial/cortexm/stm32/current/cdl/ser_cortexm_stm32.cdl
--- a/packages/devs/serial/cortexm/stm32/current/cdl/ser_cortexm_stm32.cdl
+++ b/packages/devs/serial/cortexm/stm32/current/cdl/ser_cortexm_stm32.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 2008 Free Software Foundation, Inc.                        
+## Copyright (C) 2008, 2011 Free Software Foundation, Inc.
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -91,7 +91,7 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S
         legal_values  { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
                       4800 7200 9600 14400 19200 38400 57600 115200 230400
         }
-        default_value { 38400 }
+        default_value { CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }
         description   "
             This option specifies the default baud rate (speed) for the 
             ST STM32 port 0."
@@ -106,6 +106,13 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S
             This option specifies the size of the internal buffers used 
             for the ST STM32 port 0."
     }
+
+    cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_INT_PRI {
+        display       "Interrupt priority for STM32 serial port 0"
+        flavor        data
+        default_value 128
+        legal_values  0 to 255
+    }
 }
 
 cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1 {
@@ -131,7 +138,7 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S
         legal_values  { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
                       4800 7200 9600 14400 19200 38400 57600 115200 230400
         }
-        default_value 38400
+        default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
         description   "
             This option specifies the default baud rate (speed) for the
             ST STM32 port 1."
@@ -146,6 +153,13 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S
             This option specifies the size of the internal buffers used 
             for the ST STM32 port 1."
     }
+
+    cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_INT_PRI {
+        display       "Interrupt priority for STM32 serial port 1"
+        flavor        data
+        default_value 128
+        legal_values  0 to 255
+    }
 }
 
 cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2 {
@@ -171,7 +185,7 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S
         legal_values  { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
                       4800 7200 9600 14400 19200 38400 57600 115200 230400
         }
-        default_value 38400
+        default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
         description   "
             This option specifies the default baud rate (speed) for the
             ST STM32 port 2."
@@ -186,6 +200,13 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S
             This option specifies the size of the internal buffers used 
             for the ST STM32 port 2."
     }
+
+    cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_INT_PRI {
+        display       "Interrupt priority for STM32 serial port 2"
+        flavor        data
+        default_value 128
+        legal_values  0 to 255
+    }
 }
 
 cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3 {
@@ -211,7 +232,7 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S
         legal_values  { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
                       4800 7200 9600 14400 19200 38400 57600 115200 230400
         }
-        default_value 38400
+        default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
         description   "
             This option specifies the default baud rate (speed) for the
             ST STM32 port 3."
@@ -226,6 +247,13 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S
             This option specifies the size of the internal buffers used 
             for the ST STM32 port 3."
     }
+
+    cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_INT_PRI {
+        display       "Interrupt priority for STM32 serial port 3"
+        flavor        data
+        default_value 128
+        legal_values  0 to 255
+    }
 }
 
 cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4 {
@@ -251,7 +279,7 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S
         legal_values  { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
                       4800 7200 9600 14400 19200 38400 57600 115200 230400
         }
-        default_value 38400
+        default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
         description   "
             This option specifies the default baud rate (speed) for the
             ST STM32 port 4."
@@ -266,6 +294,60 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S
             This option specifies the size of the internal buffers used 
             for the ST STM32 port 4."
     }
+
+    cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_INT_PRI {
+        display       "Interrupt priority for STM32 serial port 4"
+        flavor        data
+        default_value 128
+        legal_values  0 to 255
+    }
+}
+
+cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5 {
+    display       "ST STM32 serial port 5 driver"
+    flavor        bool
+    default_value CYGINT_HAL_STM32_UART5>0
+    description   "
+        This option includes the serial device driver for the ST STM32 
+        port 5."
+
+    cdl_option CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL5_NAME {
+        display       "Device name for ST STM32 serial port 5 driver"
+        flavor        data
+        default_value {"\"/dev/ser5\""}
+        description   "
+            This option specifies the name of the serial device for the 
+            ST STM32 port 5."
+    }
+
+    cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BAUD {
+        display       "Baud rate for the ST STM32 serial port 5 driver"
+        flavor        data
+        legal_values  { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
+                      4800 7200 9600 14400 19200 38400 57600 115200 230400
+        }
+        default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
+        description   "
+            This option specifies the default baud rate (speed) for the
+            ST STM32 port 5."
+    }
+
+    cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE {
+        display       "Buffer size for the ST STM32 serial port 5 driver"
+        flavor        data
+        legal_values  0 to 8192
+        default_value 128
+        description   "
+            This option specifies the size of the internal buffers used 
+            for the ST STM32 port 5."
+    }
+
+    cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_INT_PRI {
+        display       "Interrupt priority for STM32 serial port 5"
+        flavor        data
+        default_value 128
+        legal_values  0 to 255
+    }
 }
 
 
@@ -312,13 +394,23 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S
         cdl_option CYGPRI_SER_TEST_SER_DEV {
             display       "Serial device used for testing"
             flavor        data
-            default_value { "\"/dev/ser1\"" }
+            default_value { CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL0 ? CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL0_NAME : \
+                            CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1 ? CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL1_NAME : \
+                            CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2 ? CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL2_NAME : \
+                            CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3 ? CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL3_NAME : \
+                            CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4 ? CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL4_NAME : \
+                            CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL5_NAME }
         }
 
         cdl_option CYGPRI_SER_TEST_TTY_DEV {
             display       "TTY-mode serial device used for testing"
             flavor        data
-            default_value { "\"/dev/tty1\"" }
+            default_value { CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL0 ? "\"/dev/tty0\"" : \
+                            CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1 ? "\"/dev/tty1\"" : \
+                            CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2 ? "\"/dev/tty2\"" : \
+                            CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3 ? "\"/dev/tty3\"" : \
+                            CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4 ? "\"/dev/tty4\"" : \
+                            "\"/dev/tty5\"" }
         }
 
         define_proc {
diff --git a/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.c b/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.c
--- a/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.c
+++ b/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
+// Copyright (C) 1998-2002, 2004-2006, 2008-2012 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -79,10 +79,15 @@ typedef struct stm32_serial_info
     CYG_WORD            uart;
     CYG_ADDRWORD        base;
     CYG_WORD            int_num;
+    cyg_int32           int_pri;
     cyg_int32           rx_pin;
     cyg_int32           tx_pin;
     cyg_int32           rts_pin;
     cyg_int32           cts_pin;
+    cyg_int32           clk_enable;
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+    cyg_int32           remap;
+#endif
 
     cyg_bool            tx_active;
     
@@ -102,7 +107,8 @@ static bool stm32_serial_putc_interrupt(
  || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE == 0) \
  || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE == 0) \
  || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE == 0) \
- || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE == 0)
+ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE == 0) \
+ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE == 0)
 static bool stm32_serial_putc_polled(serial_channel *chan, unsigned char c);
 #endif
 static Cyg_ErrNo stm32_serial_lookup(struct cyg_devtab_entry **tab, 
@@ -113,7 +119,8 @@ static unsigned char stm32_serial_getc_i
  || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE == 0) \
  || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE == 0) \
  || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE == 0) \
- || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE == 0)
+ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE == 0) \
+ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE == 0)
 static unsigned char stm32_serial_getc_polled(serial_channel *chan);
 #endif
 static Cyg_ErrNo stm32_serial_set_config(serial_channel *chan, cyg_uint32 key,
@@ -130,7 +137,8 @@ static void       stm32_serial_DSR(cyg_v
  || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE > 0) \
  || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE > 0) \
  || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE > 0) \
- || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE > 0)
+ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE > 0) \
+ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE > 0)
 static SERIAL_FUNS(stm32_serial_funs_interrupt, 
                    stm32_serial_putc_interrupt, 
                    stm32_serial_getc_interrupt,
@@ -144,7 +152,8 @@ static SERIAL_FUNS(stm32_serial_funs_int
  || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE == 0) \
  || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE == 0) \
  || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE == 0) \
- || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE == 0)
+ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE == 0) \
+ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE == 0)
 static SERIAL_FUNS(stm32_serial_funs_polled, 
                    stm32_serial_putc_polled, 
                    stm32_serial_getc_polled,
@@ -161,10 +170,15 @@ static stm32_serial_info stm32_serial_in
     uart            : 0,
     base            : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART1,
     int_num         : CYGNUM_HAL_INTERRUPT_UART1,
+    int_pri         : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_INT_PRI,
     rx_pin          : CYGHWR_HAL_STM32_UART1_RX,
     tx_pin          : CYGHWR_HAL_STM32_UART1_TX,
     rts_pin         : CYGHWR_HAL_STM32_UART1_RTS,
     cts_pin         : CYGHWR_HAL_STM32_UART1_CTS,
+    clk_enable      : CYGHWR_HAL_STM32_UART1_CLOCK,
+#ifdef CYGHWR_HAL_STM32_UART1_REMAP_CONFIG
+    remap           : CYGHWR_HAL_STM32_UART1_REMAP_CONFIG,
+#endif
 };
 
 #if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_BUFSIZE > 0
@@ -211,10 +225,15 @@ static stm32_serial_info stm32_serial_in
     uart            : 1,
     base            : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART2,
     int_num         : CYGNUM_HAL_INTERRUPT_UART2,
+    int_pri         : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_INT_PRI,
     rx_pin          : CYGHWR_HAL_STM32_UART2_RX,
     tx_pin          : CYGHWR_HAL_STM32_UART2_TX,
     rts_pin         : CYGHWR_HAL_STM32_UART2_RTS,
     cts_pin         : CYGHWR_HAL_STM32_UART2_CTS,
+    clk_enable      : CYGHWR_HAL_STM32_UART2_CLOCK,
+#ifdef CYGHWR_HAL_STM32_UART2_REMAP_CONFIG
+    remap           : CYGHWR_HAL_STM32_UART2_REMAP_CONFIG,    
+#endif
 };
 
 #if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE > 0
@@ -261,10 +280,15 @@ static stm32_serial_info stm32_serial_in
     uart            : 2,
     base            : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART3,
     int_num         : CYGNUM_HAL_INTERRUPT_UART3,
+    int_pri         : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_INT_PRI,
     rx_pin          : CYGHWR_HAL_STM32_UART3_RX,
     tx_pin          : CYGHWR_HAL_STM32_UART3_TX,
     rts_pin         : CYGHWR_HAL_STM32_UART3_RTS,
     cts_pin         : CYGHWR_HAL_STM32_UART3_CTS,
+    clk_enable      : CYGHWR_HAL_STM32_UART3_CLOCK,
+#ifdef CYGHWR_HAL_STM32_UART3_REMAP_CONFIG
+    remap           : CYGHWR_HAL_STM32_UART3_REMAP_CONFIG,    
+#endif
 };
 
 #if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE > 0
@@ -311,10 +335,15 @@ static stm32_serial_info stm32_serial_in
     uart            : 3,
     base            : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART4,
     int_num         : CYGNUM_HAL_INTERRUPT_UART4,
+    int_pri         : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_INT_PRI,
     rx_pin          : CYGHWR_HAL_STM32_UART4_RX,
     tx_pin          : CYGHWR_HAL_STM32_UART4_TX,
     rts_pin         : CYGHWR_HAL_STM32_UART4_RTS,
     cts_pin         : CYGHWR_HAL_STM32_UART4_CTS,
+    clk_enable      : CYGHWR_HAL_STM32_UART4_CLOCK,
+#ifdef CYGHWR_HAL_STM32_UART4_REMAP_CONFIG
+    remap           : CYGHWR_HAL_STM32_UART4_REMAP_CONFIG,    
+#endif
 };
 
 #if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE > 0
@@ -361,10 +390,15 @@ static stm32_serial_info stm32_serial_in
     uart            : 4,
     base            : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART5,
     int_num         : CYGNUM_HAL_INTERRUPT_UART5,
+    int_pri         : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_INT_PRI,
     rx_pin          : CYGHWR_HAL_STM32_UART5_RX,
     tx_pin          : CYGHWR_HAL_STM32_UART5_TX,
     rts_pin         : CYGHWR_HAL_STM32_UART5_RTS,
     cts_pin         : CYGHWR_HAL_STM32_UART5_CTS,
+    clk_enable      : CYGHWR_HAL_STM32_UART5_CLOCK,
+#ifdef CYGHWR_HAL_STM32_UART5_REMAP_CONFIG
+    remap           : CYGHWR_HAL_STM32_UART5_REMAP_CONFIG,    
+#endif
 };
 
 #if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE > 0
@@ -406,6 +440,62 @@ DEVTAB_ENTRY(stm32_serial_io4,
 
 
 //==========================================================================
+
+#ifdef CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5
+static stm32_serial_info stm32_serial_info5 = {
+    uart            : 5,
+    base            : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART6,
+    int_num         : CYGNUM_HAL_INTERRUPT_UART6,
+    int_pri         : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_INT_PRI,
+    rx_pin          : CYGHWR_HAL_STM32_UART6_RX,
+    tx_pin          : CYGHWR_HAL_STM32_UART6_TX,
+    rts_pin         : CYGHWR_HAL_STM32_UART6_RTS,
+    cts_pin         : CYGHWR_HAL_STM32_UART6_CTS,
+    clk_enable      : CYGHWR_HAL_STM32_UART6_CLOCK,
+#ifdef CYGHWR_HAL_STM32_UART6_REMAP_CONFIG
+    remap           : CYGHWR_HAL_STM32_UART6_REMAP_CONFIG,    
+#endif
+};
+
+#if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE > 0
+static unsigned char stm32_serial_out_buf5[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE];
+static unsigned char stm32_serial_in_buf5[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE];
+
+static SERIAL_CHANNEL_USING_INTERRUPTS(stm32_serial_channel5,
+                                       stm32_serial_funs_interrupt, 
+                                       stm32_serial_info5,
+                                       CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BAUD),
+                                       CYG_SERIAL_STOP_DEFAULT,
+                                       CYG_SERIAL_PARITY_DEFAULT,
+                                       CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                                       CYG_SERIAL_FLAGS_DEFAULT,
+                                       &stm32_serial_out_buf5[0], sizeof(stm32_serial_out_buf5),
+                                       &stm32_serial_in_buf5[0], sizeof(stm32_serial_in_buf5)
+    );
+#else
+static SERIAL_CHANNEL(stm32_serial_channel5,
+                      stm32_serial_funs_polled, 
+                      stm32_serial_info5,
+                      CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BAUD),
+                      CYG_SERIAL_STOP_DEFAULT,
+                      CYG_SERIAL_PARITY_DEFAULT,
+                      CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                      CYG_SERIAL_FLAGS_DEFAULT
+    );
+#endif
+
+DEVTAB_ENTRY(stm32_serial_io5, 
+             CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL5_NAME,
+             0,                     // Does not depend on a lower level interface
+             &cyg_io_serial_devio, 
+             stm32_serial_init, 
+             stm32_serial_lookup,     // Serial driver may need initializing
+             &stm32_serial_channel5
+    );
+#endif //  CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5
+
+
+//==========================================================================
 // Internal function to actually configure the hardware to desired baud
 // rate, etc.
 
@@ -415,7 +505,9 @@ stm32_serial_config_port(serial_channel 
     stm32_serial_info * const stm32_chan = (stm32_serial_info *)chan->dev_priv;
     const CYG_ADDRWORD base = stm32_chan->base;
     cyg_uint32 parity = select_parity[new_config->parity];
-    cyg_uint32 word_length = select_word_length[new_config->word_length-CYGNUM_SERIAL_WORD_LENGTH_5];
+    cyg_uint32 word_length = ((new_config->word_length == CYGNUM_SERIAL_WORD_LENGTH_8) &&
+        (new_config->parity != CYGNUM_SERIAL_PARITY_NONE)) ?
+        CYGHWR_HAL_STM32_UART_CR1_M_9 : CYGHWR_HAL_STM32_UART_CR1_M_8;
     cyg_uint32 stop_bits = select_stop_bits[new_config->stop];
     cyg_uint32 cr1 = 0;
     cyg_uint32 cr2 = 0;
@@ -430,6 +522,22 @@ stm32_serial_config_port(serial_channel 
     CYGHWR_HAL_STM32_GPIO_SET( stm32_chan->rts_pin );
     CYGHWR_HAL_STM32_GPIO_SET( stm32_chan->cts_pin );
 
+    // Enable clock
+    CYGHWR_HAL_STM32_CLOCK_ENABLE( stm32_chan->clk_enable );
+
+    // Handle any pin remapping
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+    if( stm32_chan->remap != 0 )
+    {
+        CYG_ADDRESS afio = CYGHWR_HAL_STM32_AFIO;
+        cyg_uint32 mapr;
+        CYGHWR_HAL_STM32_CLOCK_ENABLE( CYGHWR_HAL_STM32_AFIO_CLOCK );
+        HAL_READ_UINT32( afio+CYGHWR_HAL_STM32_AFIO_MAPR, mapr );
+        mapr |= stm32_chan->remap;
+        HAL_WRITE_UINT32( afio+CYGHWR_HAL_STM32_AFIO_MAPR, mapr );
+    }
+#endif
+    
     // Select line parameters
     cr1 |= parity|word_length;
     cr2 |= stop_bits;
@@ -488,7 +596,7 @@ stm32_serial_init(struct cyg_devtab_entr
     (chan->callbacks->serial_init)(chan);  // Really only required for interrupt driven devices
     if (chan->out_cbuf.len != 0) {
         cyg_drv_interrupt_create(stm32_chan->int_num,
-                                 0x80,
+                                 stm32_chan->int_pri,
                                  (cyg_addrword_t)chan,
                                  stm32_serial_ISR,
                                  stm32_serial_DSR,
diff --git a/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.h b/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.h
--- a/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.h
+++ b/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.h
@@ -54,16 +54,6 @@
 #include <cyg/hal/hal_io.h>  // Register definitions
 
 // ====================================================================
-// Translate system word length selector into local values.
-
-static cyg_uint32 select_word_length[] = {
-    0,
-    0,
-    0,
-    CYGHWR_HAL_STM32_UART_CR1_M_8
-};
-
-// ====================================================================
 // Translate system stop bit selector into control register bits.
 
 static cyg_uint32 select_stop_bits[] = {
diff --git a/packages/devs/serial/freescale/uart/drv/current/ChangeLog b/packages/devs/serial/freescale/uart/drv/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/freescale/uart/drv/current/ChangeLog
@@ -0,0 +1,43 @@
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/ser_freescale_uart_chan.inl. include/ser_freescale_uart.c:
+	Add clock gating enable. [ Bugzilla 1001814 ]
+
+2012-02-07  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/ser_freescale_uart.cdl:
+	Add consolidated Interrupt Priority Scheme [Bugzilla 1001450]
+	
+2011-03-26  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/ser_freescale_uart.cdl:
+	* src/ser_freescale_uart.c:
+	* include/ser_freescale_uart_chan.inl:
+	* include/ser_freescale_uart_tty_add.inl:
+	* include/ser_freescale_uart_termiostty_add.inl:
+
+	New package -- Freescale UART driver.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/packages/devs/serial/freescale/uart/drv/current/cdl/ser_freescale_uart.cdl b/packages/devs/serial/freescale/uart/drv/current/cdl/ser_freescale_uart.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/freescale/uart/drv/current/cdl/ser_freescale_uart.cdl
@@ -0,0 +1,269 @@
+# ====================================================================
+#
+#      ser_freescale_uart.cdl
+#
+#      eCos serial Freescale UART configuration data
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      Ilija Kocho <ilijak@siva.com.mk>
+# Original data:
+# Contributors:
+# Date:           2011-02-12
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_IO_SERIAL_FREESCALE_UART {
+    display       "Freescale UART device driver"
+
+    parent        CYGPKG_IO_SERIAL_DEVICES
+    active_if     CYGPKG_IO_SERIAL
+    requires      CYGPKG_IO_SERIAL_FREESCALE_UART_HDR
+    requires      CYGPKG_ERROR
+
+    include_dir   cyg/io
+
+    description   "
+        This option enables the serial device drivers for the
+        Freescale UART, an on-chip serial controller found on some
+        freescale microcontrollers such as Kinetis, etc."
+
+    compile       -library=libextras.a   ser_freescale_uart.c
+
+    define_proc {
+        puts $::cdl_system_header "/***** serial driver proc output start *****/"
+        puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_freescale_uart.h>"
+        puts $::cdl_system_header "/*****  serial driver proc output end  *****/"
+    }
+
+    # Support up to 6 on-chip UART modules. The number may vary between
+    # processor variants so it is easy to update this here
+    for { set ::channel 0 } { $::channel < 6 } { incr ::channel } {
+
+        cdl_interface CYGINT_IO_SERIAL_FREESCALE_UART[set ::channel] {
+            display     "Platform provides UART [set ::channel]"
+            flavor      bool
+            description "
+                This interface will be implemented if the specific
+                controller being used has on-chip UART [set ::channel], and if
+                that UART is accessible on the target hardware."
+        }
+
+        cdl_component CYGPKG_IO_SERIAL_FREESCALE_UART[set ::channel] {
+            display       "Freescale UART port [set ::channel] driver"
+            flavor        bool
+            active_if     CYGINT_IO_SERIAL_FREESCALE_UART[set ::channel]
+            default_value CYGINT_IO_SERIAL_FREESCALE_UART[set ::channel]
+            implements    CYGINT_IO_SERIAL_TTY_TTY[set ::channel]
+            description   "
+                This option includes the serial device driver for Freescale
+                UART port [set ::channel]."
+
+            cdl_option CYGDAT_IO_SERIAL_FREESCALE_UART[set ::channel]_NAME {
+                display       "Device name for Freescale UART port [set ::channel]"
+                flavor        data
+                default_value [ format {"\"/dev/ser%d\""} $::channel ]
+                description   "
+                    This option specifies the device name for
+                    Freescale UART port [set ::channel]."
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART[set ::channel]_BAUD {
+                display       "Baud rate for the Freescale UART port [set ::channel] driver"
+                flavor        data
+                legal_values  { 300 600 1200 2400 4800 9600 14400 19200 38400
+                    57600 115200 230400 }
+                default_value 38400
+                description "
+                    This option specifies the default baud rate for the
+                    UART port [set ::channel]."
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART[set ::channel]_BUFSIZE {
+                display       "Buffer size for the Freescale UART port [set ::channel] driver"
+                flavor        data
+                legal_values  0 to 8192
+                default_value 128
+                description   "
+                    This option specifies the size of the internal buffers used
+                    for Freescale UART port [set ::channel]."
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART[set ::channel]_INT_PRIORITY {
+                display      "Freescale UART port [set ::channel] interrupt priority"
+                flavor       data
+                default_value CYGNUM_IO_SERIAL_FREESCALE_UART[set ::channel]_INT_PRIORITY_SP
+                description   "
+                    This option selects the interupt priority for the
+                    UART [set ::channel] interrupts."
+            }
+        }
+    }
+
+    cdl_component CYGDAT_IO_SERIAL_TTY_ADD_INL {
+        display "Freescale TTY devices beyond #3"
+        parent CYGPKG_IO_SERIAL
+        active_if CYGPKG_IO_SERIAL_TTY
+        flavor data
+        calculated { "<cyg/io/ser_freescale_uart_tty_add.inl>" }
+
+
+        cdl_component CYGPKG_IO_SERIAL_TTY_TTY4 {
+            display       "TTY mode channel #4"
+            flavor        bool
+            parent        CYGPKG_IO_SERIAL_TTY
+            active_if     CYGPKG_IO_SERIAL_TTY
+            default_value 0
+            description   "
+                This option causes '/dev/tty4', which is provided by Freescale
+                UART, to be included in the standard drivers."
+
+            cdl_option CYGDAT_IO_SERIAL_TTY_TTY4_DEV {
+                display       "TTY mode channel #4 device"
+                flavor        data
+                default_value { "\"/dev/ser4\"" }
+                description   "
+                    This option selects the physical device to use for
+                    '/dev/tty4'."
+            }
+        }
+
+        cdl_component CYGPKG_IO_SERIAL_TTY_TTY5 {
+            display       "TTY mode channel #5"
+            flavor        bool
+            parent        CYGPKG_IO_SERIAL_TTY
+            active_if     CYGPKG_IO_SERIAL_TTY
+            default_value 0
+            description   "
+                This option causes '/dev/tty5', which is provided by Freescale
+                UART, to be included in the standard drivers."
+
+            cdl_option CYGDAT_IO_SERIAL_TTY_TTY5_DEV {
+                display       "TTY mode channel #5 device"
+                flavor        data
+                default_value { "\"/dev/ser5\"" }
+                description   "
+                    This option selects the physical device to use for
+                    '/dev/tty5'."
+            }
+        }
+    }
+
+    cdl_component CYGDAT_IO_SERIAL_TERMIOS_ADD_INL {
+        display "Freescale TERMIOS devices beyond #3"
+        parent CYGPKG_IO_SERIAL
+        active_if CYGPKG_IO_SERIAL_TERMIOS
+        flavor data
+        calculated { "<cyg/io/ser_freescale_uart_termiostty_add.inl>" }
+
+        cdl_component CYGPKG_IO_SERIAL_TERMIOS_TERMIOS4 {
+            display       "Termios TTY channel #4"
+            flavor        bool
+            default_value 0
+            implements    CYGINT_IO_SERIAL_TERMIOS_TERMIOS_TTY
+            parent        CYGPKG_IO_SERIAL_TERMIOS
+            active_if     CYGPKG_IO_SERIAL_TERMIOS
+            description   "
+                This option causes '/dev/termios4' to be included in the
+                standard drivers."
+
+            cdl_option CYGDAT_IO_SERIAL_TERMIOS_TERMIOS4_DEV {
+                display       "Termios TTY channel #4 device"
+                flavor        data
+                default_value {"\"/dev/ser4\""}
+                description   "
+                    This option selects the physical device to use for
+                    '/dev/termios4'."
+            }
+        }
+
+        cdl_component CYGPKG_IO_SERIAL_TERMIOS_TERMIOS5 {
+            display       "Termios TTY channel #5"
+            flavor        bool
+            default_value 0
+            implements    CYGINT_IO_SERIAL_TERMIOS_TERMIOS_TTY
+            parent        CYGPKG_IO_SERIAL_TERMIOS
+            active_if     CYGPKG_IO_SERIAL_TERMIOS
+            description   "
+                This option causes '/dev/termios5' to be included in the
+                standard drivers."
+
+            cdl_option CYGDAT_IO_SERIAL_TERMIOS_TERMIOS5_DEV {
+                display       "Termios TTY channel #5 device"
+                flavor        data
+                default_value {"\"/dev/ser5\""}
+                description   "
+                    This option selects the physical device to use for
+                    '/dev/termios5'."
+            }
+        }
+    }
+
+    cdl_component CYGPKG_IO_SERIAL_FREESCALE_UART_OPTIONS {
+        display "Serial device driver build options"
+        flavor  none
+        description   "
+            Package specific build options including control over
+            compiler flags used only in building this package,
+            and details of which tests are built."
+
+        cdl_option CYGPKG_IO_SERIAL_FREESCALE_UART_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building these serial device drivers. These flags are
+                used in addition to the set of global flags."
+        }
+
+        cdl_option CYGPKG_IO_SERIAL_FREESCALE_UART_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building these serial device drivers. These flags are
+                removed from the set of global flags if present."
+        }
+    }
+}
+
+# EOF ser_freescale_uart.cdl
diff --git a/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_chan.inl b/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_chan.inl
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_chan.inl
@@ -0,0 +1,378 @@
+//==========================================================================
+//
+//      ser_freescale_uart.inl
+//
+//      Freescale UART Serial channel definitions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Ilija Kocho <ilijak@siva.com.mk>
+// Contributors:
+// Date:        2011-02-10
+// Purpose:     Freescale UART Serial I/O module (interrupt driven version)
+// Description:
+//
+//
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#if defined CYGPKG_IO_SERIAL_FREESCALE_UART0
+static const uart_pins_t uart0_pins = {
+    rx  : CYGHWR_IO_FREESCALE_UART0_PIN_RX,
+    tx  : CYGHWR_IO_FREESCALE_UART0_PIN_TX,
+    rts : CYGHWR_IO_FREESCALE_UART0_PIN_RTS,
+    cts : CYGHWR_IO_FREESCALE_UART0_PIN_CTS
+};
+static uart_serial_info uart_serial_info0 = {
+    uart_base          : CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE,
+    interrupt_num      : CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_VECTOR,
+    interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_PRIORITY,
+    clock              : CYGHWR_IO_FREESCALE_UART0_CLOCK,
+    pins_p             : &uart0_pins
+};
+#if CYGNUM_IO_SERIAL_FREESCALE_UART0_BUFSIZE > 0
+static unsigned char
+    uart_serial_out_buf0[CYGNUM_IO_SERIAL_FREESCALE_UART0_BUFSIZE];
+static unsigned char
+    uart_serial_in_buf0[CYGNUM_IO_SERIAL_FREESCALE_UART0_BUFSIZE];
+
+static
+SERIAL_CHANNEL_USING_INTERRUPTS(
+                                uart_serial_channel0,
+                                uart_serial_funs,
+                                uart_serial_info0,
+                                CYG_SERIAL_BAUD_RATE(
+                                     CYGNUM_IO_SERIAL_FREESCALE_UART0_BAUD),
+                                CYG_SERIAL_STOP_DEFAULT,
+                                CYG_SERIAL_PARITY_DEFAULT,
+                                CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                                CYG_SERIAL_FLAGS_DEFAULT,
+                                &uart_serial_out_buf0[0],
+                                sizeof(uart_serial_out_buf0),
+                                &uart_serial_in_buf0[0],
+                                sizeof(uart_serial_in_buf0));
+#else
+static
+SERIAL_CHANNEL(uart_serial_channel0,
+               uart_serial_funs,
+               uart_serial_info0,
+               CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART0_BAUD),
+               CYG_SERIAL_STOP_DEFAULT,
+               CYG_SERIAL_PARITY_DEFAULT,
+               CYG_SERIAL_WORD_LENGTH_DEFAULT,
+               CYG_SERIAL_FLAGS_DEFAULT);
+#endif
+DEVTAB_ENTRY(uart_serial_io0,
+             CYGDAT_IO_SERIAL_FREESCALE_UART0_NAME,
+             0, // does not depend on a lower level device driver
+             &cyg_io_serial_devio,
+             uart_serial_init,
+             uart_serial_lookup,
+             &uart_serial_channel0);
+#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART0
+
+#if defined CYGPKG_IO_SERIAL_FREESCALE_UART1
+static const uart_pins_t uart1_pins = {
+    rx  : CYGHWR_IO_FREESCALE_UART1_PIN_RX,
+    tx  : CYGHWR_IO_FREESCALE_UART1_PIN_TX,
+    rts : CYGHWR_IO_FREESCALE_UART1_PIN_RTS,
+    cts : CYGHWR_IO_FREESCALE_UART1_PIN_CTS
+};
+static uart_serial_info uart_serial_info1 = {
+    uart_base          : CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE,
+    interrupt_num      : CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_VECTOR,
+    interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_PRIORITY,
+    clock              : CYGHWR_IO_FREESCALE_UART1_CLOCK,
+    pins_p             : &uart1_pins
+};
+#if CYGNUM_IO_SERIAL_FREESCALE_UART1_BUFSIZE > 0
+static unsigned char
+    uart_serial_out_buf1[CYGNUM_IO_SERIAL_FREESCALE_UART1_BUFSIZE];
+static unsigned char
+    uart_serial_in_buf1[CYGNUM_IO_SERIAL_FREESCALE_UART1_BUFSIZE];
+
+static
+SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel1,
+                                uart_serial_funs,
+                                uart_serial_info1,
+                                CYG_SERIAL_BAUD_RATE(
+                                     CYGNUM_IO_SERIAL_FREESCALE_UART1_BAUD),
+                                CYG_SERIAL_STOP_DEFAULT,
+                                CYG_SERIAL_PARITY_DEFAULT,
+                                CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                                CYG_SERIAL_FLAGS_DEFAULT,
+                                &uart_serial_out_buf1[0],
+                                sizeof(uart_serial_out_buf1),
+                                &uart_serial_in_buf1[0],
+                                sizeof(uart_serial_in_buf1));
+#else
+static
+SERIAL_CHANNEL(uart_serial_channel1,
+               uart_serial_funs,
+               uart_serial_info1,
+               CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART1_BAUD),
+               CYG_SERIAL_STOP_DEFAULT,
+               CYG_SERIAL_PARITY_DEFAULT,
+               CYG_SERIAL_WORD_LENGTH_DEFAULT,
+               CYG_SERIAL_FLAGS_DEFAULT);
+#endif
+DEVTAB_ENTRY(uart_serial_io1,
+             CYGDAT_IO_SERIAL_FREESCALE_UART1_NAME,
+             0, // does not depend on a lower level device driver
+             &cyg_io_serial_devio,
+             uart_serial_init,
+             uart_serial_lookup,
+             &uart_serial_channel1);
+#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART1
+
+#if defined CYGPKG_IO_SERIAL_FREESCALE_UART2
+static const uart_pins_t uart2_pins = {
+    rx  : CYGHWR_IO_FREESCALE_UART2_PIN_RX,
+    tx  : CYGHWR_IO_FREESCALE_UART2_PIN_TX,
+    rts : CYGHWR_IO_FREESCALE_UART2_PIN_RTS,
+    cts : CYGHWR_IO_FREESCALE_UART2_PIN_CTS
+};
+static uart_serial_info uart_serial_info2 = {
+    uart_base          : CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE,
+    interrupt_num      : CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_VECTOR,
+    interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_PRIORITY,
+    clock              : CYGHWR_IO_FREESCALE_UART2_CLOCK,
+    pins_p             : &uart2_pins
+};
+#if CYGNUM_IO_SERIAL_FREESCALE_UART2_BUFSIZE > 0
+static unsigned char
+    uart_serial_out_buf2[CYGNUM_IO_SERIAL_FREESCALE_UART2_BUFSIZE];
+static unsigned char
+    uart_serial_in_buf2[CYGNUM_IO_SERIAL_FREESCALE_UART2_BUFSIZE];
+
+static
+SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel2,
+                                uart_serial_funs,
+                                uart_serial_info2,
+                                CYG_SERIAL_BAUD_RATE(
+                                     CYGNUM_IO_SERIAL_FREESCALE_UART2_BAUD),
+                                CYG_SERIAL_STOP_DEFAULT,
+                                CYG_SERIAL_PARITY_DEFAULT,
+                                CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                                CYG_SERIAL_FLAGS_DEFAULT,
+                                &uart_serial_out_buf2[0],
+                                sizeof(uart_serial_out_buf2),
+                                &uart_serial_in_buf2[0],
+                                sizeof(uart_serial_in_buf2));
+#else
+static
+SERIAL_CHANNEL(uart_serial_channel2,
+               uart_serial_funs,
+               uart_serial_info2,
+               CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART2_BAUD),
+               CYG_SERIAL_STOP_DEFAULT,
+               CYG_SERIAL_PARITY_DEFAULT,
+               CYG_SERIAL_WORD_LENGTH_DEFAULT,
+               CYG_SERIAL_FLAGS_DEFAULT);
+#endif
+DEVTAB_ENTRY(uart_serial_io2,
+             CYGDAT_IO_SERIAL_FREESCALE_UART2_NAME,
+             0, // does not depend on a lower level device driver
+             &cyg_io_serial_devio,
+             uart_serial_init,
+             uart_serial_lookup,
+             &uart_serial_channel2);
+#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART2
+
+
+#if defined CYGPKG_IO_SERIAL_FREESCALE_UART3
+static const uart_pins_t uart3_pins = {
+    rx  : CYGHWR_IO_FREESCALE_UART3_PIN_RX,
+    tx  : CYGHWR_IO_FREESCALE_UART3_PIN_TX,
+    rts : CYGHWR_IO_FREESCALE_UART3_PIN_RTS,
+    cts : CYGHWR_IO_FREESCALE_UART3_PIN_CTS
+};
+static uart_serial_info uart_serial_info3 = {
+    uart_base          : CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE,
+    interrupt_num      : CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_VECTOR,
+    interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_PRIORITY,
+    clock              : CYGHWR_IO_FREESCALE_UART3_CLOCK,
+    pins_p             : &uart3_pins
+};
+#if CYGNUM_IO_SERIAL_FREESCALE_UART3_BUFSIZE > 0
+static unsigned char
+    uart_serial_out_buf3[CYGNUM_IO_SERIAL_FREESCALE_UART3_BUFSIZE];
+static unsigned char
+    uart_serial_in_buf3[CYGNUM_IO_SERIAL_FREESCALE_UART3_BUFSIZE];
+
+static
+SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel3,
+                                uart_serial_funs,
+                                uart_serial_info3,
+                                CYG_SERIAL_BAUD_RATE(
+                                     CYGNUM_IO_SERIAL_FREESCALE_UART3_BAUD),
+                                CYG_SERIAL_STOP_DEFAULT,
+                                CYG_SERIAL_PARITY_DEFAULT,
+                                CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                                CYG_SERIAL_FLAGS_DEFAULT,
+                                &uart_serial_out_buf3[0],
+                                sizeof(uart_serial_out_buf3),
+                                &uart_serial_in_buf3[0],
+                                sizeof(uart_serial_in_buf3));
+#else
+static
+SERIAL_CHANNEL(uart_serial_channel3,
+               uart_serial_funs,
+               uart_serial_info3,
+               CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART3_BAUD),
+               CYG_SERIAL_STOP_DEFAULT,
+               CYG_SERIAL_PARITY_DEFAULT,
+               CYG_SERIAL_WORD_LENGTH_DEFAULT,
+               CYG_SERIAL_FLAGS_DEFAULT);
+#endif
+DEVTAB_ENTRY(uart_serial_io3,
+             CYGDAT_IO_SERIAL_FREESCALE_UART3_NAME,
+             0, // does not depend on a lower level device driver
+             &cyg_io_serial_devio,
+             uart_serial_init,
+             uart_serial_lookup,
+             &uart_serial_channel3);
+#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART3
+
+
+#if defined CYGPKG_IO_SERIAL_FREESCALE_UART4
+static const uart_pins_t uart4_pins = {
+    rx  : CYGHWR_IO_FREESCALE_UART4_PIN_RX,
+    tx  : CYGHWR_IO_FREESCALE_UART4_PIN_TX,
+    rts : CYGHWR_IO_FREESCALE_UART4_PIN_RTS,
+    cts : CYGHWR_IO_FREESCALE_UART4_PIN_CTS
+};
+static uart_serial_info uart_serial_info4 = {
+    uart_base          : CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE,
+    interrupt_num      : CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_VECTOR,
+    interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_PRIORITY,
+    clock              : CYGHWR_IO_FREESCALE_UART4_CLOCK,
+    pins_p             : &uart4_pins
+};
+#if CYGNUM_IO_SERIAL_FREESCALE_UART4_BUFSIZE > 0
+static unsigned char
+    uart_serial_out_buf4[CYGNUM_IO_SERIAL_FREESCALE_UART4_BUFSIZE];
+static unsigned char
+    uart_serial_in_buf4[CYGNUM_IO_SERIAL_FREESCALE_UART4_BUFSIZE];
+
+static
+SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel4,
+                                uart_serial_funs,
+                                uart_serial_info4,
+                                CYG_SERIAL_BAUD_RATE(
+                                     CYGNUM_IO_SERIAL_FREESCALE_UART4_BAUD),
+                                CYG_SERIAL_STOP_DEFAULT,
+                                CYG_SERIAL_PARITY_DEFAULT,
+                                CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                                CYG_SERIAL_FLAGS_DEFAULT,
+                                &uart_serial_out_buf4[0],
+                                sizeof(uart_serial_out_buf4),
+                                &uart_serial_in_buf4[0],
+                                sizeof(uart_serial_in_buf4));
+#else
+static
+SERIAL_CHANNEL(uart_serial_channel4,
+               uart_serial_funs,
+               uart_serial_info4,
+               CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART4_BAUD),
+               CYG_SERIAL_STOP_DEFAULT,
+               CYG_SERIAL_PARITY_DEFAULT,
+               CYG_SERIAL_WORD_LENGTH_DEFAULT,
+               CYG_SERIAL_FLAGS_DEFAULT);
+#endif
+DEVTAB_ENTRY(uart_serial_io4,
+             CYGDAT_IO_SERIAL_FREESCALE_UART4_NAME,
+             0, // does not depend on a lower level device driver
+             &cyg_io_serial_devio,
+             uart_serial_init,
+             uart_serial_lookup,
+             &uart_serial_channel4);
+#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART4
+
+
+#if defined CYGPKG_IO_SERIAL_FREESCALE_UART5
+static const uart_pins_t uart5_pins = {
+    rx  : CYGHWR_IO_FREESCALE_UART5_PIN_RX,
+    tx  : CYGHWR_IO_FREESCALE_UART5_PIN_TX,
+    rts : CYGHWR_IO_FREESCALE_UART5_PIN_RTS,
+    cts : CYGHWR_IO_FREESCALE_UART5_PIN_CTS
+};
+static uart_serial_info uart_serial_info5 = {
+    uart_base          : CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE,
+    interrupt_num      : CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_VECTOR,
+    interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_PRIORITY,
+    clock              : CYGHWR_IO_FREESCALE_UART5_CLOCK,
+    pins_p             : &uart5_pins
+};
+#if CYGNUM_IO_SERIAL_FREESCALE_UART5_BUFSIZE > 0
+static unsigned char
+    uart_serial_out_buf5[CYGNUM_IO_SERIAL_FREESCALE_UART5_BUFSIZE];
+static unsigned char
+    uart_serial_in_buf5[CYGNUM_IO_SERIAL_FREESCALE_UART5_BUFSIZE];
+
+static
+SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel5,
+                                uart_serial_funs,
+                                uart_serial_info5,
+                                CYG_SERIAL_BAUD_RATE(
+                                     CYGNUM_IO_SERIAL_FREESCALE_UART5_BAUD),
+                                CYG_SERIAL_STOP_DEFAULT,
+                                CYG_SERIAL_PARITY_DEFAULT,
+                                CYG_SERIAL_WORD_LENGTH_DEFAULT,
+                                CYG_SERIAL_FLAGS_DEFAULT,
+                                &uart_serial_out_buf5[0],
+                                sizeof(uart_serial_out_buf5),
+                                &uart_serial_in_buf5[0],
+                                sizeof(uart_serial_in_buf5));
+#else
+static
+SERIAL_CHANNEL(uart_serial_channel5,
+               uart_serial_funs,
+               uart_serial_info5,
+               CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART5_BAUD),
+               CYG_SERIAL_STOP_DEFAULT,
+               CYG_SERIAL_PARITY_DEFAULT,
+               CYG_SERIAL_WORD_LENGTH_DEFAULT,
+               CYG_SERIAL_FLAGS_DEFAULT);
+#endif
+DEVTAB_ENTRY(uart_serial_io5,
+             CYGDAT_IO_SERIAL_FREESCALE_UART5_NAME,
+             0, // does not depend on a lower level device driver
+             &cyg_io_serial_devio,
+             uart_serial_init,
+             uart_serial_lookup,
+             &uart_serial_channel5);
+#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART5
diff --git a/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_termiostty_add.inl b/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_termiostty_add.inl
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_termiostty_add.inl
@@ -0,0 +1,79 @@
+#ifndef CYGONCE_SER_FREESCALE_UART_TERMIOS_ADD_INL
+#define CYGONCE_SER_FREESCALE_UART_TERMIOS_ADD_INL
+//=============================================================================
+//
+//      ser_freescale_uart_termiostty_add.inl
+//
+//      Termios definitions beyond #3.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2011-03-28
+// Purpose:        Termios definitions beyond #3.
+// Description: 
+// Usage:          This file is included by pkgconf/io/serial.h
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+
+#ifdef CYGPKG_IO_SERIAL_TERMIOS_TERMIOS4
+static struct termios_private_info termios_private_info4;
+DEVTAB_ENTRY(termios_io4,
+             "/dev/termios4",
+             CYGDAT_IO_SERIAL_TERMIOS_TERMIOS4_DEV,
+             &termios_devio,
+             termios_init,
+             termios_lookup,
+             &termios_private_info4);
+#endif
+
+#ifdef CYGPKG_IO_SERIAL_TERMIOS_TERMIOS5
+static struct termios_private_info termios_private_info5;
+DEVTAB_ENTRY(termios_io5,
+             "/dev/termios5",
+             CYGDAT_IO_SERIAL_TERMIOS_TERMIOS5_DEV,
+             &termios_devio,
+             termios_init,
+             termios_lookup,
+             &termios_private_info5);
+#endif
+//-----------------------------------------------------------------------------
+// end of ser_freescale_uart_termiostty_add.inl
+#endif // CYGONCE_SER_FREESCALE_UART_TERMIOS_ADD_INL
diff --git a/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_tty_add.inl b/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_tty_add.inl
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_tty_add.inl
@@ -0,0 +1,79 @@
+#ifndef CYGONCE_SER_FREESCALE_UART_TTY_ADD_INL
+#define CYGONCE_SER_FREESCALE_UART_TTY_ADD_INL
+//=============================================================================
+//
+//      ser_freescale_uart_tty_add.inl
+//
+//      TTY definitions beyond #3.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2011-03-28
+// Purpose:        TTY definitions beyond 3.
+// Description: 
+// Usage:          This file is included by pkgconf/io/serial.h
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+
+#ifdef CYGPKG_IO_SERIAL_TTY_TTY4
+static struct tty_private_info tty_private_info4;
+DEVTAB_ENTRY(tty_io4,
+             "/dev/tty4",
+             CYGDAT_IO_SERIAL_TTY_TTY4_DEV,
+             &tty_devio,
+             tty_init,
+             tty_lookup,      // Execute this when device is being looked up
+             &tty_private_info4);
+#endif
+
+#ifdef CYGPKG_IO_SERIAL_TTY_TTY5
+static struct tty_private_info tty_private_info5;
+DEVTAB_ENTRY(tty_io5,
+             "/dev/tty5",
+             CYGDAT_IO_SERIAL_TTY_TTY5_DEV,
+             &tty_devio,
+             tty_init,
+             tty_lookup,      // Execute this when device is being looked up
+             &tty_private_info5);
+#endif
+//-----------------------------------------------------------------------------
+// end of ser_freescale_uart_tty_add.inl
+#endif // CYGONCE_SER_FREESCALE_UART_TTY_ADD_INL
diff --git a/packages/devs/serial/freescale/uart/drv/current/src/ser_freescale_uart.c b/packages/devs/serial/freescale/uart/drv/current/src/ser_freescale_uart.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/freescale/uart/drv/current/src/ser_freescale_uart.c
@@ -0,0 +1,397 @@
+//==========================================================================
+//
+//      ser_freescale_uart.c
+//
+//      Freescale UART Serial I/O Interface Module (interrupt driven)
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Ilija Kocho <ilijak@siva.com.mk>
+// Contributors:
+// Date:        2011-02-10
+// Purpose:     Freescale UART Serial I/O module (interrupt driven version)
+// Description:
+//
+//
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#include <pkgconf/io_serial.h>
+#include <pkgconf/io.h>
+
+#include <cyg/io/io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_arbiter.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/io/devtab.h>
+#include <cyg/infra/diag.h>
+#include <cyg/io/serial.h>
+#include <cyg/io/ser_freescale_uart.h>
+
+// Only build this driver for if Freescale UART is needed.
+#ifdef CYGPKG_IO_SERIAL_FREESCALE_UART
+
+typedef struct uart_pins_s {
+    cyg_uint32 rx;
+    cyg_uint32 tx;
+    cyg_uint32 rts;
+    cyg_uint32 cts;
+} uart_pins_t;
+
+
+typedef struct uart_serial_info {
+    CYG_ADDRWORD   uart_base;          // Base address of the uart port
+    CYG_WORD       interrupt_num;      // NVIC interrupt vector
+    cyg_priority_t interrupt_priority; // NVIC interupt priority
+    const uart_pins_t *pins_p;         // Rx, Tx, etc.
+    cyg_uint32     clock;              // Clock gate
+    cyg_bool tx_active;
+    cyg_interrupt  interrupt_obj;      // Interrupt object
+    cyg_handle_t   interrupt_handle;   // Interrupt handle
+} uart_serial_info;
+
+static bool uart_serial_init(struct cyg_devtab_entry * tab);
+static bool uart_serial_putc(serial_channel * chan, unsigned char c);
+static Cyg_ErrNo uart_serial_lookup(struct cyg_devtab_entry ** tab,
+                                    struct cyg_devtab_entry * sub_tab,
+                                    const char * name);
+static unsigned char uart_serial_getc(serial_channel *chan);
+static Cyg_ErrNo uart_serial_set_config(serial_channel *chan, cyg_uint32 key,
+                                        const void *xbuf, cyg_uint32 *len);
+static void uart_serial_start_xmit(serial_channel *chan);
+static void uart_serial_stop_xmit(serial_channel *chan);
+
+// Interrupt servers
+static cyg_uint32 uart_serial_ISR(cyg_vector_t vector, cyg_addrword_t data);
+static void       uart_serial_DSR(cyg_vector_t vector, cyg_ucount32 count,
+                                  cyg_addrword_t data);
+
+static SERIAL_FUNS(uart_serial_funs,
+                   uart_serial_putc,
+                   uart_serial_getc,
+                   uart_serial_set_config,
+                   uart_serial_start_xmit,
+                   uart_serial_stop_xmit);
+
+// Available baud rates
+static cyg_int32 select_baud[] = {
+    0,      // Unused
+    50,     // 50
+    75,     // 75
+    110,    // 110
+    0,      // 134.5
+    150,    // 150
+    200,    // 200
+    300,    // 300
+    600,    // 600
+    1200,   // 1200
+    1800,   // 1800
+    2400,   // 2400
+    3600,   // 3600
+    4800,   // 4800
+    7200,   // 7200
+    9600,   // 9600
+    14400,  // 14400
+    19200,  // 19200
+    38400,  // 38400
+    57600,  // 57600
+    115200, // 115200
+    230400, // 230400
+};
+
+#include <cyg/io/ser_freescale_uart_chan.inl>
+
+//----------------------------------------------------------------------------
+// Internal function to actually configure the hardware to desired
+// baud rate, etc.
+//----------------------------------------------------------------------------
+static bool
+uart_serial_config_port(serial_channel * chan, cyg_serial_info_t * new_config,
+                        bool init)
+{
+    cyg_uint32 regval;
+    uart_serial_info * uart_chan = (uart_serial_info *)(chan->dev_priv);
+    cyg_addrword_t uart_base = uart_chan->uart_base;
+    cyg_uint32 baud_rate = select_baud[new_config->baud];
+
+    if(!baud_rate) return false;    // Invalid baud rate selected
+    
+    // Bring clock to the sevice
+    CYGHWR_IO_CLOCK_ENABLE(uart_chan->clock);
+    // Configure PORT pins
+    CYGHWR_IO_FREESCALE_UART_PIN(uart_chan->pins_p->rx);
+    CYGHWR_IO_FREESCALE_UART_PIN(uart_chan->pins_p->tx);
+
+    CYGHWR_IO_FREESCALE_UART_BAUD_SET(uart_base, baud_rate);
+
+    if(new_config->word_length != 8)
+        return false;
+
+    switch(new_config->parity) {
+    case CYGNUM_SERIAL_PARITY_NONE:
+        regval = 0;
+        break;
+    case CYGNUM_SERIAL_PARITY_EVEN:
+        regval = CYGHWR_DEV_FREESCALE_UART_C1_PE;
+        break;
+    case CYGNUM_SERIAL_PARITY_ODD:
+        regval = CYGHWR_DEV_FREESCALE_UART_C1_PE |
+                 CYGHWR_DEV_FREESCALE_UART_C1_PT;
+        break;
+    default: return false;
+    }
+
+    HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C1, regval);
+
+    if(init) { // Enable the receiver interrupt
+        regval = CYGHWR_DEV_FREESCALE_UART_C2_RIE;
+    } else {    // Restore the old interrupt state
+        HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, regval);
+    }
+
+    // Enable the device
+    regval |= CYGHWR_DEV_FREESCALE_UART_C2_TE |
+              CYGHWR_DEV_FREESCALE_UART_C2_RE;
+
+    HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, regval);
+
+    uart_chan->tx_active = false;
+
+    if(new_config != &chan->config)
+        chan->config = *new_config;
+
+    return true;
+}
+
+//--------------------------------------------------------------
+// Function to initialize the device.  Called at bootstrap time.
+//--------------------------------------------------------------
+static bool
+uart_serial_init(struct cyg_devtab_entry * tab)
+{
+    serial_channel * chan = (serial_channel *)tab->priv;
+    uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv;
+
+    // Really only required for interrupt driven devices
+    (chan->callbacks->serial_init)(chan);
+    if(chan->out_cbuf.len != 0) {
+        cyg_drv_interrupt_create(uart_chan->interrupt_num,
+                                 uart_chan->interrupt_priority,
+                                 // Data item passed to interrupt handler
+                                 (cyg_addrword_t)chan,
+                                 uart_serial_ISR,
+                                 uart_serial_DSR,
+                                 &uart_chan->interrupt_handle,
+                                 &uart_chan->interrupt_obj);
+
+        cyg_drv_interrupt_attach(uart_chan->interrupt_handle);
+        cyg_drv_interrupt_unmask(uart_chan->interrupt_num);
+    }
+    return uart_serial_config_port(chan, &chan->config, true);
+}
+
+//----------------------------------------------------------------------
+// This routine is called when the device is "looked" up (i.e. attached)
+//----------------------------------------------------------------------
+static Cyg_ErrNo
+uart_serial_lookup(struct cyg_devtab_entry ** tab,
+                   struct cyg_devtab_entry * sub_tab, const char * name)
+{
+    serial_channel * chan = (serial_channel *)(*tab)->priv;
+    // Really only required for interrupt driven devices
+    (chan->callbacks->serial_init)(chan);
+
+    return ENOERR;
+}
+
+//-----------------------------------------------------------------
+// Send a character to Tx
+//-----------------------------------------------------------------
+static bool
+uart_serial_putc(serial_channel * chan, unsigned char ch_out)
+{
+    uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv;
+    cyg_addrword_t uart_base = uart_chan->uart_base;
+    cyg_uint32 uart_sr;
+
+    HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_S1, uart_sr);
+    if(uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_TDRE) {
+        HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_D, ch_out);
+        return true;
+    } else {
+        return false;
+    }
+}
+
+
+//---------------------------------------------------------------------
+// Fetch a character Rx (for polled operation only)
+//---------------------------------------------------------------------
+static unsigned char
+uart_serial_getc(serial_channel * chan)
+{
+    cyg_uint8 ch_in;
+    uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv;
+    cyg_addrword_t uart_base = uart_chan->uart_base;
+
+    cyg_uint32 uart_sr;
+
+    do {
+        HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_S1, uart_sr);
+    } while(uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_RDRF);
+
+    HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_D, ch_in);
+
+    return ch_in;
+}
+
+
+//---------------------------------------------------
+// Set up the device characteristics; baud rate, etc.
+//---------------------------------------------------
+static bool
+uart_serial_set_config(serial_channel * chan, cyg_uint32 key,
+                       const void *xbuf, cyg_uint32 * len)
+{
+    switch(key) {
+    case CYG_IO_SET_CONFIG_SERIAL_INFO: {
+            cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf;
+            if(*len < sizeof(cyg_serial_info_t)) {
+                return -EINVAL;
+            }
+            *len = sizeof(cyg_serial_info_t);
+            if(true != uart_serial_config_port(chan, config, false))
+            return -EINVAL;
+        }
+        break;
+    default:
+        return -EINVAL;
+    }
+    return ENOERR;
+}
+
+//-------------------------------------
+// Enable the transmitter on the device
+//-------------------------------------
+static void uart_serial_start_xmit(serial_channel * chan)
+{
+    uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv;
+    cyg_addrword_t uart_base = uart_chan->uart_base;
+    cyg_uint32 uart_cr12;
+
+    if(!uart_chan->tx_active) {
+        uart_chan->tx_active = true;
+        HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12);
+        uart_cr12 |= CYGHWR_DEV_FREESCALE_UART_C2_TIE;
+        HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12);
+    }
+}
+
+//--------------------------------------
+// Disable the transmitter on the device
+//--------------------------------------
+static void uart_serial_stop_xmit(serial_channel * chan)
+{
+    uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv;
+
+    cyg_addrword_t uart_base = uart_chan->uart_base;
+    cyg_uint32 uart_cr12;
+
+    if(uart_chan->tx_active) {
+        uart_chan->tx_active = false;
+        HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12);
+        uart_cr12 &= ~CYGHWR_DEV_FREESCALE_UART_C2_TIE;
+        HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12);
+    }
+}
+
+//-----------------------------------------
+// The low level interrupt handler
+//-----------------------------------------
+static
+cyg_uint32 uart_serial_ISR(cyg_vector_t vector, cyg_addrword_t data)
+{
+    serial_channel * chan = (serial_channel *)data;
+    uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv;
+
+    cyg_drv_interrupt_mask(uart_chan->interrupt_num);
+    cyg_drv_interrupt_acknowledge(uart_chan->interrupt_num);
+
+    return CYG_ISR_CALL_DSR; // cause the DSR to run
+}
+
+
+//------------------------------------------
+// The high level interrupt handler
+//------------------------------------------
+
+#define CYGHWR_DEV_FREESCALE_UART_S1_ERRORS \
+                                 (CYGHWR_DEV_FREESCALE_UART_S1_OR | \
+                                  CYGHWR_DEV_FREESCALE_UART_S1_NF | \
+                                  CYGHWR_DEV_FREESCALE_UART_S1_FE | \
+                                  CYGHWR_DEV_FREESCALE_UART_S1_PF)
+
+static void
+uart_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
+{
+    serial_channel * chan = (serial_channel *)data;
+    uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv;
+    cyg_addrword_t uart_base = uart_chan->uart_base;
+    volatile cyg_uint32 uart_sr;
+    cyg_uint8 uart_dr;
+
+    HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_S1, uart_sr);
+    if(uart_sr & (CYGHWR_DEV_FREESCALE_UART_S1_RDRF |
+                  CYGHWR_DEV_FREESCALE_UART_S1_ERRORS)) {
+        // Receiver full or errors
+        HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_D, uart_dr);
+        if(uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_ERRORS) {
+            // Check for receive error
+        } else { // No errors, get the character
+            (chan->callbacks->rcv_char)(chan, (cyg_uint8)uart_dr);
+        }
+    }
+
+    if(uart_chan->tx_active && (uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_TDRE)){
+        //Transmitter empty
+        (chan->callbacks->xmt_char)(chan);
+    }
+
+    cyg_drv_interrupt_unmask(uart_chan->interrupt_num);
+}
+
+#endif // CYGPKG_IO_SERIAL_FREESCALE_UART
+// EOF ser_freescale_uart.c
diff --git a/packages/devs/serial/freescale/uart/hdr/current/ChangeLog b/packages/devs/serial/freescale/uart/hdr/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/freescale/uart/hdr/current/ChangeLog
@@ -0,0 +1,34 @@
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/ser_freescale_uart.h: Add clock gating comment.
+	[ Bugzilla 1001814 ]
+
+2011-03-26  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/ser_freescale_uart_hdr.cdl:
+	* include/ser_freescale_uart.h:
+	New package -- Freescale UART header.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/serial/freescale/uart/hdr/current/cdl/ser_freescale_uart_hdr.cdl b/packages/devs/serial/freescale/uart/hdr/current/cdl/ser_freescale_uart_hdr.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/freescale/uart/hdr/current/cdl/ser_freescale_uart_hdr.cdl
@@ -0,0 +1,68 @@
+# ====================================================================
+#
+#      ser_freescale_uart_h.cdl
+#
+#      eCos serial Freescale UART configuration data
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2006 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      Ilija Kocho <ilijak@siva.com.mk>
+# Original data:
+# Contributors:
+# Date:           2011-02-05
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_IO_SERIAL_FREESCALE_UART_HDR {
+    display       "Freescale UART header"
+
+    include_dir   cyg/io
+    description   "
+    This pacckage provides header file with definitions and macros for
+    Freescale UART. Same header is used by Freescale UART serial driver
+    as well as by HAL. Freescale UART is on-chip serial controller found
+    on some Freescale micro-controllers such as Kinetis familly, etc."
+
+    define_proc {
+        puts $::cdl_system_header "/***** serial driver proc output start *****/"
+        puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HDR_HEADER <pkgconf/io_serial_freescale_uart_hdr.h>"
+        puts $::cdl_system_header "/*****  serial driver proc output end  *****/"
+    }
+}
+
+# EOF ser_freescale_uart_h.cdl
diff --git a/packages/devs/serial/freescale/uart/hdr/current/include/ser_freescale_uart.h b/packages/devs/serial/freescale/uart/hdr/current/include/ser_freescale_uart.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/freescale/uart/hdr/current/include/ser_freescale_uart.h
@@ -0,0 +1,144 @@
+#ifndef CYGONCE_DEVS_SERIAL_FREESCALE_UART_H
+#define CYGONCE_DEVS_SERIAL_FREESCALE_UART_H
+//==========================================================================
+//
+//      ser_freescale_uart.h
+//
+//      Freescale UART I/O definitions.
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Ilija Kocho <ilijak@siva.com.mk>
+// Contributors:
+// Date:        2011-02-05
+// Purpose:     Freescale UART I/O definitions.
+// Description:
+//
+//
+//####DESCRIPTIONEND####
+//==========================================================================
+
+enum {
+    CYGHWR_DEV_FREESCALE_UART_BDH,         // UART Baud Rate Register High
+    CYGHWR_DEV_FREESCALE_UART_BDL,         // UART Baud Rate Register Low
+    CYGHWR_DEV_FREESCALE_UART_C1,          // UART Control Register 1
+    CYGHWR_DEV_FREESCALE_UART_C2,          // UART Control Register 2
+    CYGHWR_DEV_FREESCALE_UART_S1,          // UART Status Register 1
+    CYGHWR_DEV_FREESCALE_UART_S2,          // UART Status Register 2
+    CYGHWR_DEV_FREESCALE_UART_C3,          // UART Control Register 3
+    CYGHWR_DEV_FREESCALE_UART_D,           // UART Data Register
+    CYGHWR_DEV_FREESCALE_UART_MA1,         // UART Match Address Registers 1
+    CYGHWR_DEV_FREESCALE_UART_MA2,         // UART Match Address Registers 2
+    CYGHWR_DEV_FREESCALE_UART_C4,          // UART Control Register 4
+    CYGHWR_DEV_FREESCALE_UART_C5,          // UART Control Register 5
+    CYGHWR_DEV_FREESCALE_UART_ED,          // UART Extended Data Register
+    CYGHWR_DEV_FREESCALE_UART_MODEM,       // UART Modem Register
+    CYGHWR_DEV_FREESCALE_UART_IR,          // UART Infrared Register
+    CYGHWR_DEV_FREESCALE_UART_Res_0,
+    CYGHWR_DEV_FREESCALE_UART_PFIFO,       // UART FIFO Parameters
+    CYGHWR_DEV_FREESCALE_UART_CFIFO,       // UART FIFO Control Register
+    CYGHWR_DEV_FREESCALE_UART_SFIFO,       // UART FIFO Status Register
+    CYGHWR_DEV_FREESCALE_UART_TWFIFO,      // UART FIFO Transmit Watermark
+    CYGHWR_DEV_FREESCALE_UART_TCFIFO,      // UART FIFO Transmit Count
+    CYGHWR_DEV_FREESCALE_UART_RWFIFO,      // UART FIFO Receive Watermark
+    CYGHWR_DEV_FREESCALE_UART_RCFIFO,      // UART FIFO Receive Count
+    CYGHWR_DEV_FREESCALE_UART_Res_1,
+    CYGHWR_DEV_FREESCALE_UART_C7816,       // UART 7816 Control Register
+    CYGHWR_DEV_FREESCALE_UART_IE7816,      // UART 7816 Interrupt Enable Register
+    CYGHWR_DEV_FREESCALE_UART_IS7816,      // UART 7816 Interrupt Status Register
+    CYGHWR_DEV_FREESCALE_UART_WP7816_T0T1, // UART 7816 Wait Parameter Register
+    CYGHWR_DEV_FREESCALE_UART_WN7816,      // UART 7816 Wait N Register
+    CYGHWR_DEV_FREESCALE_UART_WF7816,      // UART 7816 Wait FD Register
+    CYGHWR_DEV_FREESCALE_UART_ET7816,      // UART 7816 Error Threshold Register
+    CYGHWR_DEV_FREESCALE_UART_TL7816       // UART 7816 Transmit Length Register
+};
+
+// CYGHWR_IO_FREESCALE_UART_BAUD_SET(__uart_p, _baud_) should be provided by HAL.
+// CYGHWR_IO_FREESCALE_UART_PIN(__pin) should be provided by HAL.
+// CYGHWR_IO_FREESCALE_UARTn_CLOCK should be provided by HAL.
+// CYGHWR_IO_FREESCALE_UARTn_PIN_RX should be provided by HAL.
+// CYGHWR_IO_FREESCALE_UARTn_PIN_TX should be provided by HAL.
+// CYGHWR_IO_FREESCALE_UARTn_PIN_RTS should be provided by HAL.
+// CYGHWR_IO_FREESCALE_UARTn_PIN_CTS should be provided by HAL.
+
+
+#define CYGHWR_DEV_FREESCALE_UART_C1_LOOPS     (0x80)
+#define CYGHWR_DEV_FREESCALE_UART_C1_UARTSWAI  (0x40)
+#define CYGHWR_DEV_FREESCALE_UART_C1_RSRC      (0x20)
+#define CYGHWR_DEV_FREESCALE_UART_C1_M         (0x10)
+#define CYGHWR_DEV_FREESCALE_UART_C1_WAKE      (0x08)
+#define CYGHWR_DEV_FREESCALE_UART_C1_ILT       (0x04)
+#define CYGHWR_DEV_FREESCALE_UART_C1_PE        (0x02)
+#define CYGHWR_DEV_FREESCALE_UART_C1_PT        (0x01)
+
+#define CYGHWR_DEV_FREESCALE_UART_C2_TIE       (0x80)
+#define CYGHWR_DEV_FREESCALE_UART_C2_TCIE      (0x40)
+#define CYGHWR_DEV_FREESCALE_UART_C2_RIE       (0x20)
+#define CYGHWR_DEV_FREESCALE_UART_C2_ILIE      (0x10)
+#define CYGHWR_DEV_FREESCALE_UART_C2_TE        (0x08)
+#define CYGHWR_DEV_FREESCALE_UART_C2_RE        (0x04)
+#define CYGHWR_DEV_FREESCALE_UART_C2_RWU       (0x02)
+#define CYGHWR_DEV_FREESCALE_UART_C2_SBK       (0x01)
+
+#define CYGHWR_DEV_FREESCALE_UART_S1_TDRE      (0x80)
+#define CYGHWR_DEV_FREESCALE_UART_S1_TC        (0x40)
+#define CYGHWR_DEV_FREESCALE_UART_S1_RDRF      (0x20)
+#define CYGHWR_DEV_FREESCALE_UART_S1_IDLE      (0x10)
+#define CYGHWR_DEV_FREESCALE_UART_S1_OR        (0x08)
+#define CYGHWR_DEV_FREESCALE_UART_S1_NF        (0x04)
+#define CYGHWR_DEV_FREESCALE_UART_S1_FE        (0x02)
+#define CYGHWR_DEV_FREESCALE_UART_S1_PF        (0x01)
+
+#define CYGHWR_DEV_FREESCALE_UART_S2_LBKDIF    (0x80)
+#define CYGHWR_DEV_FREESCALE_UART_S2_RXEDGIF   (0x40)
+#define CYGHWR_DEV_FREESCALE_UART_S2_MSBF      (0x20)
+#define CYGHWR_DEV_FREESCALE_UART_S2_RXINV     (0x10)
+#define CYGHWR_DEV_FREESCALE_UART_S2_RWUID     (0x08)
+#define CYGHWR_DEV_FREESCALE_UART_S2_BRK13     (0x04)
+#define CYGHWR_DEV_FREESCALE_UART_S2_LBKDE     (0x02)
+#define CYGHWR_DEV_FREESCALE_UART_S2_RAF       (0x01)
+
+#define CYGHWR_DEV_FREESCALE_UART_C3_R8        (0x80)
+#define CYGHWR_DEV_FREESCALE_UART_C3_T8        (0x40)
+#define CYGHWR_DEV_FREESCALE_UART_C3_TXDIR     (0x20)
+#define CYGHWR_DEV_FREESCALE_UART_C3_TXINV     (0x10)
+#define CYGHWR_DEV_FREESCALE_UART_C3_ORIE      (0x08)
+#define CYGHWR_DEV_FREESCALE_UART_C3_NEIE      (0x04)
+#define CYGHWR_DEV_FREESCALE_UART_C3_FEIE      (0x02)
+#define CYGHWR_DEV_FREESCALE_UART_C3_PEIE      (0x01)
+
+
+#endif // CYGONCE_DEVS_SERIAL_FREESCALE_UART_H
diff --git a/packages/devs/serial/generic/16x5x/current/ChangeLog b/packages/devs/serial/generic/16x5x/current/ChangeLog
--- a/packages/devs/serial/generic/16x5x/current/ChangeLog
+++ b/packages/devs/serial/generic/16x5x/current/ChangeLog
@@ -1,3 +1,8 @@
+2012-02-07  Bernard Fouché <bernard.fouche@kuantic.com>
+
+	* src/ser_16x5x.c (serial_config_port): Clear potential Overrun Error
+	condition at init by always reading RHR.
+
 2009-02-17  Rene Schipp von Branitz Nielsen <rbn@vitesse.com>
 
 	* src/ser_16x5x.c:
diff --git a/packages/devs/serial/generic/16x5x/current/src/ser_16x5x.c b/packages/devs/serial/generic/16x5x/current/src/ser_16x5x.c
--- a/packages/devs/serial/generic/16x5x/current/src/ser_16x5x.c
+++ b/packages/devs/serial/generic/16x5x/current/src/ser_16x5x.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2006 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2006, 2012 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -332,6 +332,8 @@ serial_config_port(serial_channel *chan,
               CYGNUM_IO_SERIAL_GENERIC_16X5X_FIFO_TX_SIZE;
             // Enable and clear FIFO
             HAL_WRITE_UINT8(base+REG_fcr, _fcr_thresh); 
+            // Read RHR to clear potential Overrun Error
+            HAL_READ_UINT8(base+REG_rhr, b);
         }
         else {
             ser_chan->tx_fifo_size = 1;
diff --git a/packages/devs/serial/powerpc/quicc/current/ChangeLog b/packages/devs/serial/powerpc/quicc/current/ChangeLog
--- a/packages/devs/serial/powerpc/quicc/current/ChangeLog
+++ b/packages/devs/serial/powerpc/quicc/current/ChangeLog
@@ -1,3 +1,8 @@
+2010-12-06 Mark Retallack <mark.retallack@siemens.com>
+
+	* src/quicc_smc_serial.c: Wait for CPM Busy Flag to clear on write to
+	CP Command Register
+
 2006-01-27 Will Wagner <willw@carallon.com>
 
         * src/quicc_smc_serial.h: Removed unused structure
diff --git a/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c b/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
--- a/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
+++ b/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
@@ -339,6 +339,11 @@ quicc_smc_serial_config_port(serial_chan
     volatile struct smc_regs *ctl = (volatile struct smc_regs *)smc_chan->ctl;
 
     if (baud_divisor == 0) return false;
+    // Stop transmitter while changing baud rate
+    eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_StopTx;
+    while (eppc->cp_cr & QUICC_SMC_CMD_Go )
+        continue;
+    HAL_IO_BARRIER();  // Inforce I/O ordering
     // Disable channel during setup
     ctl->smc_smcmr = QUICC_SMCMR_UART;  // Disabled, UART mode
     HAL_IO_BARRIER();  // Inforce I/O ordering
@@ -346,8 +351,6 @@ quicc_smc_serial_config_port(serial_chan
     _lcr = QUICC_SMCMR_CLEN(new_config->word_length + ((new_config->parity == CYGNUM_SERIAL_PARITY_NONE)? 0: 1) + ((new_config->stop == CYGNUM_SERIAL_STOP_2)? 2: 1)) |
         smc_select_stop_bits[new_config->stop] |
         smc_select_parity[new_config->parity];
-    // Stop transmitter while changing baud rate
-    eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_StopTx;
     HAL_IO_BARRIER();  // Inforce I/O ordering
     // Set baud rate generator
     *smc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1);
@@ -356,6 +359,8 @@ quicc_smc_serial_config_port(serial_chan
     ctl->smc_smcmr = QUICC_SMCMR_UART|QUICC_SMCMR_TEN|QUICC_SMCMR_REN|_lcr;
     HAL_IO_BARRIER();  // Inforce I/O ordering
     eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_RestartTx;
+    while (eppc->cp_cr & QUICC_SMC_CMD_Go )
+        continue;
     if (new_config != &chan->config) {
         chan->config = *new_config;
     }
@@ -453,6 +458,8 @@ quicc_smc_serial_init_info(quicc_sxx_ser
      */
     HAL_IO_BARRIER();  // Inforce I/O ordering
     eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx;
+    while (eppc->cp_cr & QUICC_SMC_CMD_Go )
+        continue;
     HAL_IO_BARRIER();  // Inforce I/O ordering
     /*
      *  Clear any previous events. Enable interrupts.
@@ -491,7 +498,8 @@ quicc_scc_serial_config_port(serial_chan
      */
     HAL_IO_BARRIER();  // Inforce I/O ordering
     eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | scc_chan->channel | QUICC_CPM_CR_BUSY;
-
+    while (eppc->cp_cr & QUICC_CPM_CR_BUSY )
+        continue;
     HAL_IO_BARRIER();  // Inforce I/O ordering
     regs->scc_gsmr_l |= (QUICC_SCC_GSMR_L_Tx | QUICC_SCC_GSMR_L_Rx);  // Enable Rx, Tx
     if (new_config != &chan->config) {
@@ -603,6 +611,8 @@ quicc_scc_serial_init_info(quicc_sxx_ser
      */
     HAL_IO_BARRIER();  // Inforce I/O ordering
     eppc->cp_cr = scc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx;
+    while (eppc->cp_cr & QUICC_SMC_CMD_Go )
+        continue;
     /*
      *  Clear any previous events. Enable interrupts.
      *  (Section 16.15.7.14 and 16.15.7.15)
diff --git a/packages/devs/spi/cortexm/a2fxxx/current/ChangeLog b/packages/devs/spi/cortexm/a2fxxx/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/spi/cortexm/a2fxxx/current/ChangeLog
@@ -0,0 +1,35 @@
+2012-01-04  Christophe Coutand  <ecos@hotmail.co.uk>
+	* src/spi_a2fxxx.c:
+	Fix compiler warning, used uninitialized variable in a2fxxx_spi_set_ss().
+
+2011-04-13  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* cdl/spi_a2fxxx.cdl:
+	* include/spi_a2fxxx.h:
+	* src/spi_a2fxxx.c:
+	New package -- Smartfusion Cortex-M3 SPI driver package.
+	[Bugzilla 1001291]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/spi/cortexm/a2fxxx/current/cdl/spi_a2fxxx.cdl b/packages/devs/spi/cortexm/a2fxxx/current/cdl/spi_a2fxxx.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/spi/cortexm/a2fxxx/current/cdl/spi_a2fxxx.cdl
@@ -0,0 +1,175 @@
+##=============================================================================
+##
+##      spi_a2fxxx.cdl
+##
+##      Smartfusion Cortex-M3 SPI driver configuration options.
+##
+##=============================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##=============================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):   ccoutand, updated for Smartfusion Cortex-M3
+## Original(s): Chris Holgate
+## Date:        2011-04-25
+## Purpose:     Configure Smartfusion Cortex-M3 SPI driver.
+##
+######DESCRIPTIONEND####
+##
+##=============================================================================
+
+cdl_package CYGPKG_DEVS_SPI_CORTEXM_A2FXXX {
+    display       "Actel Smartfusion SPI driver"
+    description   "
+        This package provides SPI driver support for the Smartfusion Cortex-M3
+        series of microcontrollers.
+    "
+    parent        CYGPKG_IO_SPI
+    active_if     CYGPKG_IO_SPI
+    requires      CYGPKG_HAL_CORTEXM_A2FXXX
+    hardware
+    include_dir   cyg/io
+    compile       -library=libextras.a spi_a2fxxx.c
+
+    cdl_option CYGDBG_DEVS_SPI_CORTEXM_A2FXXX_TRACE {
+        display       "Display status messages during SPI operations"
+        flavor        bool
+        default_value 0
+        description   "
+           Selecting this option will cause the SPI driver to print status
+           messages as various SPI operations are undertaken."
+    }
+
+    cdl_component CYGHWR_DEVS_SPI_CORTEXM_A2FXXX_BUS1 {
+        display       "Actel Smartfusion SPI bus 1"
+        description   "
+            Enable SPI bus 1 on the A2FXXX device.
+            "
+        flavor        bool
+        default_value false
+
+        cdl_option CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS1_TX_DMA {
+            display       "Transmit DMA channel number"
+            flavor        data
+            default_value 0
+        }
+
+        cdl_option CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS1_RX_DMA {
+            display       "Receive DMA channel number"
+            flavor        data
+            default_value 1
+        }
+
+        cdl_option CYGDAT_DEVS_SPI_CORTEXM_A2FXXX_BUS1_TX_DMA_PRI {
+            display       "Transmit DMA channel priority"
+            legal_values  { "HIGH" "LOW" }
+            flavor        data
+            default_value { "HIGH" }
+        }
+
+        cdl_option CYGDAT_DEVS_SPI_CORTEXM_A2FXXX_BUS1_RX_DMA_PRI {
+            display       "Receive DMA channel priority"
+            legal_values  { "HIGH" "LOW" }
+            flavor        data
+            default_value { "HIGH" }
+        }
+    }
+
+    cdl_component CYGHWR_DEVS_SPI_CORTEXM_A2FXXX_BUS2 {
+        display       "Actel Smartfusion SPI bus 2"
+        description   "
+            Enable SPI bus 2 on the A2FXXX device.
+        "
+        flavor        bool
+        default_value false
+
+        cdl_option CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS2_TX_DMA {
+            display       "Transmit DMA channel number"
+            flavor        data
+            default_value 2
+        }
+
+        cdl_option CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS2_RX_DMA {
+            display       "Receive DMA channel number"
+            flavor        data
+            default_value 3
+        }
+
+        cdl_option CYGDAT_DEVS_SPI_CORTEXM_A2FXXX_BUS2_TX_DMA_PRI {
+            display       "Transmit DMA channel priority"
+            legal_values  { "HIGH" "LOW" }
+            flavor        data
+            default_value { "HIGH" }
+        }
+
+        cdl_option CYGDAT_DEVS_SPI_CORTEXM_A2FXXX_BUS2_RX_DMA_PRI {
+            display       "Receive DMA channel priority"
+            legal_values  { "HIGH" "LOW" }
+            flavor        data
+            default_value { "HIGH" }
+        }
+    }
+
+    cdl_component CYGPKG_DEVS_SPI_CORTEXM_A2FXXX_OPTIONS {
+        display "Actel Smartfusion SPI driver build options"
+        flavor  none
+        description   "
+        Package specific build options including control over
+        compiler flags used only in building this package,
+        and details of which tests are built."
+
+        cdl_option CYGPKG_DEVS_SPI_CORTEXM_A2FXXX_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the A2FXXX SPI driver. These flags are used in addition
+                to the set of global flags."
+        }
+
+        cdl_option CYGPKG_DEVS_SPI_CORTEXM_A2FXXX_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the A2FXXX SPI driver. These flags are removed from
+                the set of global flags if present."
+        }
+    }
+
+}
+# EOF spi_a2fxxx.cdl
diff --git a/packages/devs/spi/cortexm/a2fxxx/current/include/spi_a2fxxx.h b/packages/devs/spi/cortexm/a2fxxx/current/include/spi_a2fxxx.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/spi/cortexm/a2fxxx/current/include/spi_a2fxxx.h
@@ -0,0 +1,195 @@
+#ifndef CYGONCE_DEVS_SPI_CORTEXM_STM32_H
+# define CYGONCE_DEVS_SPI_CORTEXM_STM32_H
+//=============================================================================
+//
+//      spi_a2fxxx.h
+//
+//      Header definitions for Smartfusion Cortex-M3 SPI driver.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand, updated for Smartfusion Cortex-M3
+// Original(s): Chris Holgate
+// Date:        2011-04-25
+// Purpose:     Smartfusion Cortex-M3 SPI driver definitions.
+// Description:
+// Usage:       #include <cyg/io/spi_a2fxxx.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+# include <pkgconf/hal.h>
+# include <pkgconf/io_spi.h>
+# include <pkgconf/devs_spi_cortexm_a2fxxx.h>
+
+# include <cyg/infra/cyg_type.h>
+# include <cyg/hal/drv_api.h>
+# include <cyg/io/spi.h>
+
+__externC cyg_uint32 a2fxxx_dma_ch_attach(cyg_uint8, cyg_ISR_t *, cyg_DSR_t *,
+                                          cyg_addrword_t);
+
+typedef enum a2fxxx_spi_mode {
+    A2FXXX_SPI_MOTOROLA       = 0x00,
+    A2FXXX_SPI_TI_SYNC_SERIAL = 0x01,
+    A2FXXX_SPI_NS_MICROWIRE   = 0x02
+} a2fxxx_spi_mode;
+
+//-----------------------------------------------------------------------------
+// Macro for defining a SPI device and attaching it to the appropriate bus.
+//
+// _name_     is the name of the SPI device.  This will be used to reference a
+//            data structure of type cyg_spi_device which can be passed to the
+//            SPI driver API without needing a cast.
+// _bus_      is the bus number to which this device is attached (1, 2 or 3).
+// _csnum_    when _csgpio_ is set to false : is the chip select line used for
+//            this device, numbered from 0.
+//            when _csgpio_ is set to true : is the GPIO number used to drive the
+//            device chip select line.
+// _csgpio_   when set to false, the device chip select line is controlled by the
+//            SPI controller.
+//            when set to true, the device chip select line is a GPIO of the processor
+//            control by the SPI driver.
+// _proto_    is the SPI bus protocol:
+//              0 -> Motorola SPI Protocol (_clpol_ and _clpha_ are valid in this mode)
+//              1 -> National Semiconductor MICROWIRE Protocol
+//              2 -> Texas Instruments (TI) Synchronous Serial Protocol
+// _clpol_    is the SPI bus clock polarity used by the device.  This must be
+//            set to 1 if a clock line pullup resistor is used and 0 if a
+//            clock line pulldown resistor is used.
+// _clpha_    is the SPI bus clock phase used by the device.
+// _brate_    is the SPI bus clock baud rate used by the device, measured in Hz.
+// _csup_dly_ is the minimum delay between chip select assert and transfer
+//            start, measured in microseconds.
+// _csdw_dly_ is the minimum delay between transfer end and chip select deassert,
+//            measured in microseconds.
+// _trbt_dly_ is the minimum delay between consecutive transfers.
+
+# define CYG_DEVS_SPI_CORTEXM_A2FXXX_DEVICE( \
+  _name_, _bus_, _csnum_, _csgpio_, _proto_, _clpol_, _clpha_, _brate_, _csup_dly_, _csdw_dly_, _trbt_dly_\
+) \
+cyg_spi_cortexm_a2fxxx_device_t _name_ ##_a2fxxx CYG_SPI_DEVICE_ON_BUS(_bus_) = { \
+{ .spi_bus    = (cyg_spi_bus*) &cyg_spi_a2fxxx_bus## _bus_ }, \
+  .dev_num    = _csnum_,     \
+  .cs_gpio    = _csgpio_,    \
+  .cs_gpio_n  = _csnum_,     \
+  .proto      = _proto_,     \
+  .cl_pol     = _clpol_,     \
+  .cl_pha     = _clpha_,     \
+  .cl_brate   = _brate_,     \
+  .cs_up_udly = _csup_dly_,  \
+  .cs_dw_udly = _csdw_dly_,  \
+  .tr_bt_udly = _trbt_dly_,  \
+  .spi_cr_val = 0,           \
+}; \
+extern cyg_spi_device _name_ __attribute__((alias ( #_name_ "_a2fxxx" )));
+
+//-----------------------------------------------------------------------------
+// A2FXXX SPI bus configuration and state.
+
+typedef struct cyg_spi_cortexm_a2fxxx_bus_setup_s {
+    cyg_uint32      apb_freq;          // Peripheral bus frequency (fp).
+    cyg_haladdress  spi_reg_base;      // Base address of SPI register block.
+    cyg_haladdress  dma_reg_base;      // Base address of DMA register block.
+    cyg_uint8       dma_tx_channel;    // TX DMA channel for this bus.
+    cyg_uint8       dma_rx_channel;    // RX DMA channel for this bus.
+    cyg_uint8       cs_gpio_num;       // Number of chip selects for this bus.
+    const cyg_uint8 *cs_gpio_list;     // List of GPIOs used as chip selects.
+    const cyg_uint8 *spi_gpio_list;    // List of GPIOs used by the SPI interface.
+    cyg_bool        dma_tx_pri;        // Priority for DMA transmit.
+    cyg_bool        dma_rx_pri;        // Priority for DMA receive.
+    cyg_haladdress  *rx_dma_null;
+    cyg_haladdress  *tx_dma_null;
+} cyg_spi_cortexm_a2fxxx_bus_setup_t;
+
+typedef struct cyg_spi_cortexm_a2fxxx_bus_s {
+    // ---- Upper layer data ----
+    cyg_spi_bus     spi_bus;           // Upper layer SPI bus data.
+
+    // ---- Bus configuration constants ----
+    const cyg_spi_cortexm_a2fxxx_bus_setup_t *setup;
+
+    // ---- Driver state (private) ----
+    cyg_interrupt   tx_intr_data;      // DMA interrupt data (TX).
+    cyg_interrupt   rx_intr_data;      // DMA interrupt data (RX).
+    cyg_handle_t    tx_intr_handle;    // DMA interrupt handle (TX).
+    cyg_handle_t    rx_intr_handle;    // DMA interrupt handle (RX).
+    cyg_drv_mutex_t mutex;             // Transfer mutex.
+    cyg_drv_cond_t  condvar;           // Transfer condition variable.
+    cyg_bool        tx_dma_done;       // Flags used to signal completion.
+    cyg_bool        rx_dma_done;       // Flags used to signal completion.
+    cyg_bool        cs_up;             // Chip select asserted flag.
+
+} cyg_spi_cortexm_a2fxxx_bus_t;
+
+//-----------------------------------------------------------------------------
+// A2FXXX SPI device.
+
+typedef struct cyg_spi_cortexm_a2fxxx_device_s {
+    // ---- Upper layer data ----
+    cyg_spi_device  spi_device;        // Upper layer SPI device data.
+
+    // ---- Device setup (user configurable) ----
+    cyg_uint8       dev_num;           // Device number.
+    a2fxxx_spi_mode proto;             // Protocol
+    cyg_bool        cs_gpio;           // True = use GPIO to control CS line
+    cyg_uint32      cs_gpio_n;         // GPIO #
+    cyg_uint8       cl_pol;            // Clock polarity (0 or 1).
+    cyg_uint8       cl_pha;            // Clock phase    (0 or 1).
+    cyg_uint32      cl_brate;          // Clock baud rate.
+    cyg_uint16      cs_up_udly;        // Minimum delay in us between CS up and transfer start.
+    cyg_uint16      cs_dw_udly;        // Minimum delay in us between transfer end and CS down.
+    cyg_uint16      tr_bt_udly;        // Minimum delay in us between two transfers.
+
+    // ---- Device state (private) ----
+    cyg_uint32      spi_cr_val;        // SPI configuration register (initialised to 0).
+
+} cyg_spi_cortexm_a2fxxx_device_t;
+
+//-----------------------------------------------------------------------------
+// Exported bus data structures.
+
+# ifdef CYGHWR_DEVS_SPI_CORTEXM_A2FXXX_BUS1
+externC cyg_spi_cortexm_a2fxxx_bus_t cyg_spi_a2fxxx_bus1;
+# endif
+
+# ifdef CYGHWR_DEVS_SPI_CORTEXM_A2FXXX_BUS2
+externC cyg_spi_cortexm_a2fxxx_bus_t cyg_spi_a2fxxx_bus2;
+# endif
+
+//=============================================================================
+#endif // CYGONCE_DEVS_SPI_CORTEXM_A2FXXX_H
diff --git a/packages/devs/spi/cortexm/a2fxxx/current/src/spi_a2fxxx.c b/packages/devs/spi/cortexm/a2fxxx/current/src/spi_a2fxxx.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/spi/cortexm/a2fxxx/current/src/spi_a2fxxx.c
@@ -0,0 +1,638 @@
+//=============================================================================
+//
+//      spi_a2fxxx.c
+//
+//      SPI driver implementation for Smartfusion Cortex-M3
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand, updated for Smartfusion Cortex-M3
+// Original(s): Chris Holgate
+// Date:        2011-04-25
+// Purpose:     Smartfusion Cortex-M3 SPI driver implementation
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/drv_api.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/diag.h>
+
+#include <cyg/io/spi.h>
+#include <cyg/io/spi_a2fxxx.h>
+
+#include <pkgconf/devs_spi_cortexm_a2fxxx.h>
+
+#include <string.h>
+
+#if defined(CYGHWR_DEVS_SPI_CORTEXM_A2FXXX_BUS1) || \
+      defined(CYGHWR_DEVS_SPI_CORTEXM_A2FXXX_BUS2)
+
+#ifdef CYGDBG_DEVS_SPI_CORTEXM_A2FXXX_TRACE
+# define SPI_TRACE(args...) diag_printf(args)
+#else
+# define SPI_TRACE(args...)
+#endif
+
+//-----------------------------------------------------------------------------
+// API function call forward references.
+
+static void a2fxxx_transaction_begin    (cyg_spi_device*);
+static void a2fxxx_transaction_transfer (cyg_spi_device*, cyg_bool, cyg_uint32, const cyg_uint8*, cyg_uint8*, cyg_bool);
+static void a2fxxx_transaction_tick     (cyg_spi_device*, cyg_bool, cyg_uint32);
+static void a2fxxx_transaction_end      (cyg_spi_device*);
+static int  a2fxxx_get_config           (cyg_spi_device*, cyg_uint32, void*, cyg_uint32*);
+static int  a2fxxx_set_config           (cyg_spi_device*, cyg_uint32, const void*, cyg_uint32*);
+
+//-----------------------------------------------------------------------------
+// Instantiate the bus state data structures.
+
+#ifdef CYGHWR_DEVS_SPI_CORTEXM_A2FXXX_BUS1
+
+static cyg_haladdress rx1_dma_null = 0x0;
+static cyg_haladdress tx1_dma_null = 0x0;
+
+static const cyg_spi_cortexm_a2fxxx_bus_setup_t bus1_setup = {
+    .spi_reg_base                     = CYGHWR_HAL_A2FXXX_SPI0,
+    .dma_reg_base                     = CYGHWR_HAL_A2FXXX_DMA,
+    .dma_tx_channel                   = CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS1_TX_DMA,
+    .dma_rx_channel                   = CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS1_RX_DMA,
+#ifdef CYGDAT_DEVS_SPI_CORTEXM_A2FXXX_BUS1_TX_DMA_PRI_HIGH
+    .dma_tx_pri                       = true,
+#else
+    .dma_tx_pri                       = false,
+#endif
+#ifdef CYGDAT_DEVS_SPI_CORTEXM_A2FXXX_BUS1_RX_DMA_PRI_HIGH
+    .dma_rx_pri                       = true,
+#else
+    .dma_rx_pri                       = false,
+#endif
+    .rx_dma_null                      = &rx1_dma_null,
+    .tx_dma_null                      = &tx1_dma_null,
+};
+
+cyg_spi_cortexm_a2fxxx_bus_t cyg_spi_a2fxxx_bus1 = {
+    .spi_bus.spi_transaction_begin    = a2fxxx_transaction_begin,
+    .spi_bus.spi_transaction_transfer = a2fxxx_transaction_transfer,
+    .spi_bus.spi_transaction_tick     = a2fxxx_transaction_tick,
+    .spi_bus.spi_transaction_end      = a2fxxx_transaction_end,
+    .spi_bus.spi_get_config           = a2fxxx_get_config,
+    .spi_bus.spi_set_config           = a2fxxx_set_config,
+    .setup                            = &bus1_setup,
+    .cs_up                            = false
+};
+#endif
+
+#ifdef CYGHWR_DEVS_SPI_CORTEXM_A2FXXX_BUS2
+
+static cyg_haladdress rx2_dma_null = 0x0;
+static cyg_haladdress tx2_dma_null = 0x0;
+
+static const cyg_spi_cortexm_a2fxxx_bus_setup_t bus2_setup = {
+    .spi_reg_base                     = CYGHWR_HAL_A2FXXX_SPI1,
+    .dma_reg_base                     = CYGHWR_HAL_A2FXXX_DMA,
+    .dma_tx_channel                   = CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS2_TX_DMA,
+    .dma_rx_channel                   = CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS2_RX_DMA,
+#ifdef CYGDAT_DEVS_SPI_CORTEXM_A2FXXX_BUS2_TX_DMA_PRI_HIGH
+    .dma_tx_pri                       = true,
+#else
+    .dma_tx_pri                       = false,
+#endif
+#ifdef CYGDAT_DEVS_SPI_CORTEXM_A2FXXX_BUS2_RX_DMA_PRI_HIGH
+    .dma_rx_pri                       = true,
+#else
+    .dma_rx_pri                       = false,
+#endif
+    .rx_dma_null                      = &rx2_dma_null,
+    .tx_dma_null                      = &tx2_dma_null,
+};
+
+cyg_spi_cortexm_a2fxxx_bus_t cyg_spi_a2fxxx_bus2 = {
+    .spi_bus.spi_transaction_begin    = a2fxxx_transaction_begin,
+    .spi_bus.spi_transaction_transfer = a2fxxx_transaction_transfer,
+    .spi_bus.spi_transaction_tick     = a2fxxx_transaction_tick,
+    .spi_bus.spi_transaction_end      = a2fxxx_transaction_end,
+    .spi_bus.spi_get_config           = a2fxxx_get_config,
+    .spi_bus.spi_set_config           = a2fxxx_set_config,
+    .setup                            = &bus2_setup,
+    .cs_up                            = false
+};
+#endif
+
+
+//-----------------------------------------------------------------------------
+// Implement DMA ISRs.  These clear the DMA channel interrupts and
+// schedule their respective DSRs.
+
+static cyg_uint32 a2fxxx_tx_ISR
+  (cyg_vector_t vector, cyg_addrword_t data)
+{
+    cyg_spi_cortexm_a2fxxx_bus_t* a2fxxx_bus =
+                                  (cyg_spi_cortexm_a2fxxx_bus_t*) data;
+    cyg_uint8 chan = a2fxxx_bus->setup->dma_tx_channel;
+    SPI_TRACE("SPI : Handle TX ISR\n");
+    a2fxxx_dma_clear_interrupt ( chan );
+    return (CYG_ISR_CALL_DSR | CYG_ISR_HANDLED);
+}
+
+static cyg_uint32 a2fxxx_rx_ISR
+  (cyg_vector_t vector, cyg_addrword_t data)
+{
+    cyg_spi_cortexm_a2fxxx_bus_t* a2fxxx_bus =
+                                  (cyg_spi_cortexm_a2fxxx_bus_t*) data;
+    cyg_uint8 chan = a2fxxx_bus->setup->dma_rx_channel;
+    SPI_TRACE("SPI : Handle RX ISR\n");
+    a2fxxx_dma_clear_interrupt ( chan );
+    return (CYG_ISR_CALL_DSR | CYG_ISR_HANDLED);
+}
+
+//-----------------------------------------------------------------------------
+// Implement DMA DSRs.  These clear down the interrupt conditions and assert
+// their respective 'transaction complete' flags.
+
+static void a2fxxx_tx_DSR
+  (cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
+{
+    cyg_spi_cortexm_a2fxxx_bus_t* a2fxxx_bus =
+                                  (cyg_spi_cortexm_a2fxxx_bus_t*) data;
+    SPI_TRACE("SPI : Handle TX DSR\n");
+    cyg_drv_dsr_lock ();
+    a2fxxx_bus->tx_dma_done = true;
+    cyg_drv_cond_signal (&a2fxxx_bus->condvar);
+    cyg_drv_dsr_unlock ();
+}
+
+static void a2fxxx_rx_DSR
+  (cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
+{
+    cyg_spi_cortexm_a2fxxx_bus_t* a2fxxx_bus =
+                                  (cyg_spi_cortexm_a2fxxx_bus_t*) data;
+    SPI_TRACE("SPI : Handle RX DSR\n");
+    cyg_drv_dsr_lock ();
+    a2fxxx_bus->rx_dma_done = true;
+    cyg_drv_cond_signal (&a2fxxx_bus->condvar);
+    cyg_drv_dsr_unlock ();
+}
+
+//-----------------------------------------------------------------------------
+// Set up a new SPI bus on initialization.
+
+static void a2fxxx_spi_bus_setup
+  (cyg_spi_cortexm_a2fxxx_bus_t* a2fxxx_bus)
+{
+    cyg_uint8 dma_tx_type, dma_rx_type;
+
+    if( a2fxxx_bus->setup->spi_reg_base == CYGHWR_HAL_A2FXXX_SPI1 ){
+        CYGHWR_HAL_A2FXXX_GPIO_SET( CYGHWR_HAL_A2FXXX_SPI1_DO );
+        CYGHWR_HAL_A2FXXX_GPIO_SET( CYGHWR_HAL_A2FXXX_SPI1_DI );
+        CYGHWR_HAL_A2FXXX_GPIO_SET( CYGHWR_HAL_A2FXXX_SPI1_CLK );
+        dma_tx_type = CYGHWR_HAL_A2FXXX_DMA_XFER(TO_SPI1);
+        dma_rx_type = CYGHWR_HAL_A2FXXX_DMA_XFER(FROM_SPI1);
+    }
+    else {
+        CYGHWR_HAL_A2FXXX_GPIO_SET( CYGHWR_HAL_A2FXXX_SPI0_DO );
+        CYGHWR_HAL_A2FXXX_GPIO_SET( CYGHWR_HAL_A2FXXX_SPI0_DI );
+        CYGHWR_HAL_A2FXXX_GPIO_SET( CYGHWR_HAL_A2FXXX_SPI0_CLK );
+        dma_tx_type = CYGHWR_HAL_A2FXXX_DMA_XFER(TO_SPI0);
+        dma_rx_type = CYGHWR_HAL_A2FXXX_DMA_XFER(FROM_SPI0);
+    }
+
+    // Initialize the synchronization primitives.
+    cyg_drv_mutex_init (&a2fxxx_bus->mutex);
+    cyg_drv_cond_init (&a2fxxx_bus->condvar, &a2fxxx_bus->mutex);
+
+    // Setup DMA channel
+    a2fxxx_dma_ch_setup(a2fxxx_bus->setup->dma_tx_channel, dma_tx_type,
+             CYGHWR_HAL_A2FXXX_DMA_OUTBOUND, sizeof(cyg_uint8), 0,
+             a2fxxx_bus->setup->dma_tx_pri, 9);
+    a2fxxx_dma_ch_setup(a2fxxx_bus->setup->dma_rx_channel, dma_rx_type,
+             CYGHWR_HAL_A2FXXX_DMA_INBOUND, 0, sizeof(cyg_uint8),
+             a2fxxx_bus->setup->dma_rx_pri, 9);
+
+    // Register ISR /DSR
+    a2fxxx_dma_ch_attach(a2fxxx_bus->setup->dma_tx_channel,
+              a2fxxx_tx_ISR, a2fxxx_tx_DSR, (cyg_addrword_t) a2fxxx_bus);
+
+    a2fxxx_dma_ch_attach(a2fxxx_bus->setup->dma_rx_channel,
+              a2fxxx_rx_ISR, a2fxxx_rx_DSR, (cyg_addrword_t) a2fxxx_bus);
+
+    // Call upper layer bus init.
+    CYG_SPI_BUS_COMMON_INIT(&a2fxxx_bus->spi_bus);
+}
+
+//-----------------------------------------------------------------------------
+// Drive a GPIO pin as a SPI chip select line.
+
+static inline void a2fxxx_spi_chip_select
+  (cyg_spi_device* device, cyg_bool assert)
+{
+    cyg_spi_cortexm_a2fxxx_device_t* a2fxxx_device =
+                  (cyg_spi_cortexm_a2fxxx_device_t*) device;
+    cyg_spi_cortexm_a2fxxx_bus_t* a2fxxx_bus =
+                  (cyg_spi_cortexm_a2fxxx_bus_t*) device->spi_bus;
+
+    // CS is driven from GPIO
+    if( a2fxxx_device->cs_gpio == true) {
+        if (assert == true)
+            CYGHWR_HAL_A2FXXX_GPIO_OUT( a2fxxx_device->cs_gpio_n, 0 );
+        else
+            CYGHWR_HAL_A2FXXX_GPIO_OUT( a2fxxx_device->cs_gpio_n, 1 );
+    }
+    // CS is driven from controller
+    else {
+        cyg_uint32 reg_addr = a2fxxx_bus->setup->spi_reg_base +
+                                        CYGHWR_HAL_A2FXXX_SPI_SLAVE_SEL;
+        cyg_uint32 reg_data;
+        HAL_READ_UINT32 (reg_addr, reg_data);
+        if (assert == true)
+            reg_data |= CYGHWR_HAL_A2FXXX_SPI_CS_SEL(a2fxxx_device->dev_num);
+        else
+            reg_data &= ~CYGHWR_HAL_A2FXXX_SPI_CS_SEL(a2fxxx_device->dev_num);
+        HAL_WRITE_UINT32 (reg_addr, reg_data);
+    }
+}
+
+//-----------------------------------------------------------------------------
+// Configure build-in SPI chip select line
+
+static inline void a2fxxx_spi_set_ss
+  (cyg_spi_cortexm_a2fxxx_bus_t* a2fxxx_bus, cyg_uint8 ss_num)
+{
+    cyg_uint32 ss;
+
+    if( a2fxxx_bus->setup->spi_reg_base == CYGHWR_HAL_A2FXXX_SPI0 ){
+        if ( ss_num == 0 ) {
+            ss = CYGHWR_HAL_A2FXXX_SPI0_SS0;
+        } else if( ss_num == 1 ) {
+            ss = CYGHWR_HAL_A2FXXX_SPI0_SS1;
+        } else if( ss_num == 2 ) {
+            ss = CYGHWR_HAL_A2FXXX_SPI0_SS2;
+        } else if( ss_num == 3 ) {
+            ss = CYGHWR_HAL_A2FXXX_SPI0_SS3;
+        } else {
+            CYG_ASSERT (ss < 4, "SPI : SPI0 SS out of range.");
+            return;
+        }
+    }
+    else {
+        if ( ss_num == 0 ) {
+            ss = CYGHWR_HAL_A2FXXX_SPI1_SS0;
+        } else if( ss_num == 1 ) {
+            ss = CYGHWR_HAL_A2FXXX_SPI1_SS1;
+        } else if( ss_num == 2 ) {
+            ss = CYGHWR_HAL_A2FXXX_SPI1_SS2;
+        } else if( ss_num == 3 ) {
+            ss = CYGHWR_HAL_A2FXXX_SPI1_SS3;
+        } else if( ss_num == 4 ) {
+            ss = CYGHWR_HAL_A2FXXX_SPI1_SS4;
+        } else if( ss_num == 5 ) {
+            ss = CYGHWR_HAL_A2FXXX_SPI1_SS5;
+        } else if( ss_num == 6 ) {
+            ss = CYGHWR_HAL_A2FXXX_SPI1_SS6;
+        } else if( ss_num == 7 ) {
+            ss = CYGHWR_HAL_A2FXXX_SPI1_SS7;
+        } else {
+            CYG_ASSERT (ss < 8, "SPI : SPI1 SS out of range.");
+            return;
+        }
+    }
+
+    CYGHWR_HAL_A2FXXX_GPIO_SET( ss );
+}
+
+//-----------------------------------------------------------------------------
+// Initiate a DMA transfer over the SPI interface.
+
+static void spi_transaction_dma
+  (cyg_spi_device* device, cyg_bool tick_only, cyg_bool polled, cyg_uint32 count,
+  const cyg_uint8* tx_data, cyg_uint8* rx_data, cyg_bool drop_cs)
+{
+    cyg_spi_cortexm_a2fxxx_bus_t* a2fxxx_bus =
+                (cyg_spi_cortexm_a2fxxx_bus_t*) device->spi_bus;
+    cyg_spi_cortexm_a2fxxx_device_t* a2fxxx_device =
+                (cyg_spi_cortexm_a2fxxx_device_t*) device;
+    cyg_haladdress reg_addr;
+    cyg_uint32 spi_cr_val = a2fxxx_device->spi_cr_val;
+    cyg_haladdress spi_reg_base = a2fxxx_bus->setup->spi_reg_base;
+
+    SPI_TRACE("SPI : Transfer start\n");
+
+    // Drive chip select low, either from GPIO or build in SS signal
+    if( !a2fxxx_bus->cs_up && !tick_only ){
+        SPI_TRACE("SPI : Setup CS\n");
+        CYGACC_CALL_IF_DELAY_US (a2fxxx_device->tr_bt_udly);
+        a2fxxx_spi_chip_select (device, true);
+        CYGACC_CALL_IF_DELAY_US (a2fxxx_device->cs_up_udly);
+        a2fxxx_bus->cs_up = true;
+    }
+
+    // Disable the SPI controller.
+    reg_addr = spi_reg_base + CYGHWR_HAL_A2FXXX_SPI_CTRL;
+    HAL_WRITE_UINT32 (reg_addr, a2fxxx_device->spi_cr_val);
+
+    // Write down transfer count
+    spi_cr_val |= CYGHWR_HAL_A2FXXX_SPI_CTRL_COUNT( count );
+    reg_addr = spi_reg_base + CYGHWR_HAL_A2FXXX_SPI_CTRL;
+    HAL_WRITE_UINT32 (reg_addr, spi_cr_val);
+
+    //
+    // Setup DMA channels
+    // For null source or destination pointer, replace the buffer with the SPI driver
+    // dummy buffer and set the DMA address increment to 0
+    //
+    if(tx_data == NULL)
+        a2fxxx_dma_update_incr(a2fxxx_bus->setup->dma_tx_channel, false, 0);
+    else
+        a2fxxx_dma_update_incr(a2fxxx_bus->setup->dma_tx_channel, false,
+                                                          sizeof(cyg_uint8));
+
+    if(rx_data == NULL)
+        a2fxxx_dma_update_incr(a2fxxx_bus->setup->dma_rx_channel, true, 0);
+    else
+        a2fxxx_dma_update_incr(a2fxxx_bus->setup->dma_rx_channel, true,
+                                                          sizeof(cyg_uint8));
+
+    a2fxxx_bus->tx_dma_done = false;
+    a2fxxx_dma_xfer (a2fxxx_bus->setup->dma_tx_channel, polled, count,
+         ((tx_data == NULL) ? (cyg_uint8*) a2fxxx_bus->setup->tx_dma_null :
+          (cyg_uint8*) tx_data),
+          (cyg_uint8*)(a2fxxx_bus->setup->spi_reg_base + CYGHWR_HAL_A2FXXX_SPI_TX));
+
+    a2fxxx_bus->rx_dma_done = false;
+    a2fxxx_dma_xfer (a2fxxx_bus->setup->dma_rx_channel, polled, count,
+          (cyg_uint8*)(a2fxxx_bus->setup->spi_reg_base + CYGHWR_HAL_A2FXXX_SPI_RX),
+         ((rx_data == NULL) ? (cyg_uint8*) a2fxxx_bus->setup->rx_dma_null :
+          (cyg_uint8*) rx_data));
+
+    //
+    // Run the DMA (polling for completion).
+    //
+    if (polled)
+    {
+        // Enable the SPI controller.
+        SPI_TRACE("SPI : Control Register 0x%x, 0x%x, %d\n", reg_addr,
+                   spi_cr_val, count);
+        HAL_WRITE_UINT32 (reg_addr, spi_cr_val | CYGHWR_HAL_A2FXXX_SPI_CTRL_EN);
+
+        // Wait transfer completed.
+        do {
+            if(a2fxxx_dma_get_comp_flag(a2fxxx_bus->setup->dma_rx_channel))
+                a2fxxx_bus->rx_dma_done = true;
+            if(a2fxxx_dma_get_comp_flag(a2fxxx_bus->setup->dma_tx_channel))
+                a2fxxx_bus->tx_dma_done = true;
+        } while ( !(a2fxxx_bus->tx_dma_done && a2fxxx_bus->rx_dma_done) );
+
+        // Acknowledge transfer
+        a2fxxx_dma_clear_interrupt (a2fxxx_bus->setup->dma_rx_channel);
+        a2fxxx_dma_clear_interrupt (a2fxxx_bus->setup->dma_tx_channel);
+
+    } else {
+        cyg_drv_mutex_lock (&a2fxxx_bus->mutex);
+        cyg_drv_dsr_lock ();
+
+        // Enable the SPI controller.
+        SPI_TRACE("SPI : Control Register 0x%x, 0x%x, %d\n", reg_addr,
+                   spi_cr_val, count);
+        HAL_WRITE_UINT32 (reg_addr, spi_cr_val | CYGHWR_HAL_A2FXXX_SPI_CTRL_EN);
+
+        // Sit back and wait for the ISR/DSRs to signal completion.
+        do {
+            cyg_drv_cond_wait (&a2fxxx_bus->condvar);
+        } while (!(a2fxxx_bus->tx_dma_done && a2fxxx_bus->rx_dma_done));
+
+        cyg_drv_dsr_unlock ();
+        cyg_drv_mutex_unlock (&a2fxxx_bus->mutex);
+    }
+
+    SPI_TRACE("SPI : Transfer completed\n");
+
+    if (drop_cs && !tick_only) {
+        SPI_TRACE("SPI : Release chip select\n");
+        CYGACC_CALL_IF_DELAY_US (a2fxxx_device->cs_dw_udly);
+        a2fxxx_spi_chip_select (device, false);
+        a2fxxx_bus->cs_up = false;
+    }
+}
+
+//-----------------------------------------------------------------------------
+// Initialize SPI interfaces on startup.
+
+static void CYGBLD_ATTRIB_C_INIT_PRI(CYG_INIT_BUS_SPI)
+a2fxxx_spi_init(void)
+{
+    hal_dma_init();
+
+#ifdef CYGHWR_DEVS_SPI_CORTEXM_A2FXXX_BUS1
+    CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(SPI0) );
+    a2fxxx_spi_bus_setup (&cyg_spi_a2fxxx_bus1);
+#endif
+
+#ifdef CYGHWR_DEVS_SPI_CORTEXM_A2FXXX_BUS2
+    CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(SPI1) );
+    a2fxxx_spi_bus_setup (&cyg_spi_a2fxxx_bus2);
+#endif
+}
+
+//-----------------------------------------------------------------------------
+// Start a SPI transaction.
+
+static void a2fxxx_transaction_begin
+  (cyg_spi_device* device)
+{
+    cyg_spi_cortexm_a2fxxx_bus_t* a2fxxx_bus =
+                  (cyg_spi_cortexm_a2fxxx_bus_t*) device->spi_bus;
+    cyg_spi_cortexm_a2fxxx_device_t* a2fxxx_device =
+                  (cyg_spi_cortexm_a2fxxx_device_t*) device;
+
+    cyg_haladdress reg_addr;
+    cyg_uint32 reg_data, divided_clk, br, cs_gpio_n;
+
+    SPI_TRACE("SPI : Transfer begin\n");
+    SPI_TRACE("SPI : Device baud rate = %d\n",      a2fxxx_device->cl_brate);
+    SPI_TRACE("SPI : Device clock polarity = %d\n", a2fxxx_device->cl_pol);
+    SPI_TRACE("SPI : Device clock phase = %d\n",    a2fxxx_device->cl_pha);
+
+    // On the first transaction, generate the values to be programmed into the
+    // SPI configuration registers for this device and cache them.  This avoids
+    // having to recalculate the values for every transaction.
+    if (!a2fxxx_device->spi_cr_val) {
+
+        // SPI bus protocol
+        switch( a2fxxx_device->proto ) {
+        case A2FXXX_SPI_TI_SYNC_SERIAL:
+            reg_data = CYGHWR_HAL_A2FXXX_SPI_CTRL_PROTO_TI;
+            break;
+        case A2FXXX_SPI_NS_MICROWIRE:
+            reg_data = CYGHWR_HAL_A2FXXX_SPI_CTRL_PROTO_NS;
+            break;
+        default:
+            reg_data = CYGHWR_HAL_A2FXXX_SPI_CTRL_PROTO_MOTOROLA;
+            break;
+        }
+
+        // Bus polarity
+        if (a2fxxx_device->cl_pol)
+            reg_data |= CYGHWR_HAL_A2FXXX_SPI_CTRL_SPO;
+        if (a2fxxx_device->cl_pha)
+            reg_data |= CYGHWR_HAL_A2FXXX_SPI_CTRL_SPH;
+
+        // Master mode
+        reg_data |= CYGHWR_HAL_A2FXXX_SPI_CTRL_MASTER;
+
+        // Calculate the maximum viable bus speed.
+        divided_clk = hal_a2fxxx_spi_clock(a2fxxx_bus->setup->spi_reg_base) >> 1;
+        for (br = 0; (br < 7) && (divided_clk > a2fxxx_device->cl_brate); br++)
+            divided_clk >>= 1;
+
+        CYG_ASSERT (divided_clk <= a2fxxx_device->cl_brate,
+            "A2FXXX SPI : Cannot run bus slowly enough for peripheral.");
+
+        SPI_TRACE("SPI : Clock divider = %d\n", divided_clk);
+
+        reg_addr = a2fxxx_bus->setup->spi_reg_base +
+                   CYGHWR_HAL_A2FXXX_SPI_CLK_GEN;
+        HAL_WRITE_UINT32 (reg_addr, br);
+
+        // Set transfer size (byte mode)
+        reg_addr = a2fxxx_bus->setup->spi_reg_base +
+                   CYGHWR_HAL_A2FXXX_SPI_TXRXDF_SIZE;
+        HAL_WRITE_UINT32 (reg_addr, 8);
+
+        // Cache the configuration register settings.
+        a2fxxx_device->spi_cr_val = reg_data;
+
+        // Configure GPIO as chip select
+        if(a2fxxx_device->cs_gpio == true) {
+            cs_gpio_n = a2fxxx_device->cs_gpio_n;
+            SPI_TRACE("SPI : Setup GPIO for CS => %d\n", cs_gpio_n);
+            a2fxxx_device->cs_gpio_n =
+                CYGHWR_HAL_A2FXXX_CS_GPIO( cs_gpio_n,  OUT, cs_gpio_n, DISABLE );
+            CYGHWR_HAL_A2FXXX_GPIO_SET( a2fxxx_device->cs_gpio_n );
+            CYGHWR_HAL_A2FXXX_GPIO_OUT( a2fxxx_device->cs_gpio_n, 1);
+        }
+        // Configure build-in SPI chip select line
+        else {
+           SPI_TRACE("SPI : Setup SPI SS => %d\n", a2fxxx_device->dev_num);
+           a2fxxx_spi_set_ss(a2fxxx_bus, a2fxxx_device->dev_num);
+        }
+    }
+
+    // Set up the SPI controller.
+    reg_addr = a2fxxx_bus->setup->spi_reg_base + CYGHWR_HAL_A2FXXX_SPI_CTRL;
+    HAL_WRITE_UINT32 (reg_addr, a2fxxx_device->spi_cr_val);
+}
+
+//-----------------------------------------------------------------------------
+// Run a transaction transfer.
+
+static void a2fxxx_transaction_transfer
+  (cyg_spi_device* device, cyg_bool polled, cyg_uint32 count,
+  const cyg_uint8* tx_data, cyg_uint8* rx_data, cyg_bool drop_cs)
+{
+    // Check for unsupported transactions.
+    CYG_ASSERT (count > 0, "A2FXXX SPI : Null transfer requested.");
+
+    // Perform transfer
+    spi_transaction_dma (device, false, polled, count, tx_data, rx_data, drop_cs);
+}
+
+//-----------------------------------------------------------------------------
+// Carry out a bus tick operation - this just pushes the required number of
+// zeros onto the bus, leaving the chip select in its current state.
+
+static void a2fxxx_transaction_tick
+  (cyg_spi_device* device, cyg_bool polled, cyg_uint32 count)
+{
+    // Check for unsupported transactions.
+    CYG_ASSERT (count > 0, "A2FXXX SPI : Null transfer requested.");
+
+    SPI_TRACE("SPI : Transfer tick\n");
+
+    // Perform null transfer.
+    spi_transaction_dma (device, true, polled, count, NULL, NULL, false);
+}
+
+//-----------------------------------------------------------------------------
+// Terminate a SPI transaction, disabling the SPI controller.
+
+static void a2fxxx_transaction_end
+  (cyg_spi_device* device)
+{
+    cyg_spi_cortexm_a2fxxx_bus_t* a2fxxx_bus =
+                             (cyg_spi_cortexm_a2fxxx_bus_t*) device->spi_bus;
+    cyg_spi_cortexm_a2fxxx_device_t* a2fxxx_device =
+                                   (cyg_spi_cortexm_a2fxxx_device_t*) device;
+    cyg_haladdress reg_addr;
+
+    SPI_TRACE("SPI : Transfer end\n");
+
+    // De-assert chip select
+    if( a2fxxx_bus->cs_up == true ){
+        SPI_TRACE("SPI : Release chip select\n");
+        CYGACC_CALL_IF_DELAY_US (a2fxxx_device->cs_dw_udly);
+        a2fxxx_spi_chip_select (device, false);
+        a2fxxx_bus->cs_up = false;
+    }
+
+    // Disable controller
+    reg_addr = a2fxxx_bus->setup->spi_reg_base + CYGHWR_HAL_A2FXXX_SPI_CTRL;
+    HAL_WRITE_UINT32 (reg_addr, a2fxxx_device->spi_cr_val);
+}
+
+//-----------------------------------------------------------------------------
+// Note that no dynamic configuration options are currently defined.
+
+static int a2fxxx_get_config
+  (cyg_spi_device* dev, cyg_uint32 key, void* buf, cyg_uint32* len)
+{
+    return -1;
+}
+
+static int a2fxxx_set_config
+  (cyg_spi_device* dev, cyg_uint32 key, const void* buf, cyg_uint32* len)
+{
+    return -1;
+}
+
+#endif
+
+//=============================================================================
diff --git a/packages/devs/spi/cortexm/stm32/current/ChangeLog b/packages/devs/spi/cortexm/stm32/current/ChangeLog
--- a/packages/devs/spi/cortexm/stm32/current/ChangeLog
+++ b/packages/devs/spi/cortexm/stm32/current/ChangeLog
@@ -1,8 +1,84 @@
+2012-03-28  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* src/spi_stm32.c (bus3_rx_bbuf): Fix typo in attribute.
+
+2012-03-23  James Smith  <jsmith@ecoscentric.com>
+
+	* src/spi_stm32.c (CYGHWR_HAL_STM32_GPIO_MODE_OUT_SPEED_SPI):
+	Rename CYGHWR_HAL_STM32_GPIO_MODE_OUT_SPI to allow the same
+	SPEED_SPI value to be used for F1 and F2/F4 targets.
+	(SPI_CS): Use new wrapper macros to provide a single common SPI_CS
+	manifest.
+
+2012-03-15  James Smith  <jsmith@ecoscentric.com>
+
+	* src/spi_stm32.c: Use HIPERFORMANCE manifest to allow F2 and F4
+	device GPIO initialisation support.
+	(dma_channel_setup): Avoid compiler pointer type warning.
+
+2012-03-05  James Smith  <jsmith@ecoscentric.com>
+
+	* src/spi_stm32.c (spi_transaction_dma): Avoid race condition by
+	seting the TX and RX DMA done flags to false prior to configuring
+	(and starting) the DMA transfer.
+
+2012-01-12  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/spi_stm32.cdl: Select pin toggle rate based on STM32
+	family. Define interrupt priorities to include DMA channel
+	priorities. Undo 2011-12-09 change, F2 now supported.
+
+	* include/spi_stm32.h (cyg_spi_cortexm_stm32_bus_s):
+	* src/spi_stm32.c: Substantial reorganization to use DMA API.
+	NOTE: Currently only fully tested on F2 parts.
+
+2011-12-09  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/spi_stm32.cdl: For now, only allow this package to be
+	active with F1 family processors.
+
+2011-09-27  Ilija Stanislevik  <ilijas@siva.mk>
+
+	* src/spi_stm32.c: Add support for CYG_IO_GET_CONFIG_SPI_CLOCKRATE and
+	CYG_IO_SET_CONFIG_SPI_CLOCKRATE (possibility to retrieve and to set
+	the SPI clockrate).
+
+2011-03-10  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/spi_stm32.cdl: Add build options for CFLAGS and loopback test.
+
+2009-10-22  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/spi_stm32.cdl: Fix descriptions for chip select
+	options. Only build local test if SPI bus 1 is active.
+
+	* include/spi_stm32.h (cyg_spi_cortexm_stm32_bus_setup_s): Add
+	spi_gpio_remap field.
+
+	* src/spi_stm32.c (bus1_setup, bus2_setup, bus3_setup): Fix CS
+	number calculation, add remap to each bus.
+	(stm32_spi_bus_setup): Move enables to correct place. Add code to
+	remap SPI pins if defined.
+
 2009-08-24  Simon Kallweit  <simon.kallweit@intefo.ch>
 
 	* cdl/spi_stm32.cdl: added testcase.
 	* include/spi_stm32.h: initializing spi_cr1_val with zero.
 
+2009-06-29  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/spi_stm32.cdl: 
+	* include/spi_stm32.h (cyg_spi_cortexm_stm32_bus_setup_s):
+	* src/spi_stm32.c: Add support for individual device clock
+	enables. Also change mechanism for specifying CS lines that is
+	more in keeping with other devices.
+
+2009-03-23  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/spi_stm32.cdl: Fix up a few oddities.
+
+	* src/spi_stm32.c (spi_diag): Add some diagnostics.
+
 2009-02-10  Bart Veer  <bartv@ecoscentric.com>
 
 	* src/spi_stm32.c (cyg_spi_cortexm_stm32_init): mark as
@@ -43,7 +119,7 @@ 2009-01-30  Nick Garnett  <nickg@ecoscen
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008, 2009 Free Software Foundation, Inc.
+// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/devs/spi/cortexm/stm32/current/cdl/spi_stm32.cdl b/packages/devs/spi/cortexm/stm32/current/cdl/spi_stm32.cdl
--- a/packages/devs/spi/cortexm/stm32/current/cdl/spi_stm32.cdl
+++ b/packages/devs/spi/cortexm/stm32/current/cdl/spi_stm32.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 2008, 2009 Free Software Foundation, Inc.
+## Copyright (C) 2008, 2009, 2011, 2012 Free Software Foundation, Inc.
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -40,6 +40,7 @@
 #######DESCRIPTIONBEGIN####
 ##
 ## Author(s):   Chris Holgate
+## Contributor: jld
 ## Date:        2008-11-27
 ## Purpose:     Configure STM32 SPI driver.
 ##
@@ -64,11 +65,11 @@ cdl_option CYGNUM_DEVS_SPI_CORTEXM_STM32
     display       "Pin toggle rate"
     description   "
         Selects the pin toggle rate in MHz to be used for the SPI interfaces.  Higher toggle
-        rates allow increased baud rates at the expense of power and EMI.
-    "
+        rates allow increased baud rates at the expense of power and EMI. Only certain rates
+        are valid on different STM32 families, check part documentation for which may be used."
     flavor        data
-    default_value { 2 }
-    legal_values  { 2 10 50 }
+    default_value { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F1") ? 10 : 25 }
+    legal_values  { 2 10 25 50 80 100 }
 }
 
 cdl_component CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1 {
@@ -77,18 +78,17 @@ cdl_component CYGHWR_DEVS_SPI_CORTEXM_ST
         Enable SPI bus 1 on the STM32 device.
     "
     flavor        bool
-    default_value false
+    default_value 0
 
     cdl_option CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1_CS_GPIOS {
         display       "SPI chip selects"
         description   "
             This is a comma separated list of GPIOs which are to be used as chip
-            select lines for the SPI bus.  For the purposes of specifying
-            which GPIOs to use, they are numbered consecutively from 0 (A0)
-            through 16 (B0) to 111 (G15).
+            select lines for the SPI bus. Each GPIO is defined by the SPI_CS()
+            macro which gives the port and pin number.
         "
         flavor        data
-        default_value { "4" }
+        default_value { "SPI_CS(A, 4)" }
     }
 
     cdl_option CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE {
@@ -106,13 +106,13 @@ cdl_component CYGHWR_DEVS_SPI_CORTEXM_ST
     cdl_option CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_TXINTR_PRI {
         display       "Transmit DMA interrupt priority"
         flavor        data
-        default_value 5
+        default_value 64+5
     }
 
     cdl_option CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_RXINTR_PRI {
         display       "Receive DMA interrupt priority"
         flavor        data
-        default_value 6
+        default_value 128+6
     }
 }
 
@@ -122,18 +122,17 @@ cdl_component CYGHWR_DEVS_SPI_CORTEXM_ST
         Enable SPI bus 2 on the STM32 device.
     "
     flavor        bool
-    default_value false
+    default_value 0
 
     cdl_option CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2_CS_GPIOS {
         display       "SPI chip selects"
         description   "
             This is a comma separated list of GPIOs which are to be used as chip
-            select lines for the SPI bus.  For the purposes of specifying
-            which GPIOs to use, they are numbered consecutively from 0 (A0)
-            through 16 (B0) to 111 (G15).
+            select lines for the SPI bus. Each GPIO is defined by the SPI_CS()
+            macro which gives the port and pin number.
         "
         flavor        data
-        default_value { "28" }
+        default_value { "SPI_CS(B, 12)" }
     }
 
     cdl_option CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE {
@@ -151,13 +150,13 @@ cdl_component CYGHWR_DEVS_SPI_CORTEXM_ST
     cdl_option CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_TXINTR_PRI {
         display       "Transmit DMA interrupt priority"
         flavor        data
-        default_value 7
+        default_value 64+7
     }
 
     cdl_option CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_RXINTR_PRI {
         display       "Receive DMA interrupt priority"
         flavor        data
-        default_value 8
+        default_value 128+8
     }
 }
 
@@ -170,7 +169,7 @@ cdl_component CYGHWR_DEVS_SPI_CORTEXM_ST
         SPI bus initialisation instead.
     "
     flavor        bool
-    default_value false
+    default_value 0
 
     cdl_option CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_DISABLE_DEBUG_PORT {
         display       "Disable debug port"
@@ -179,19 +178,18 @@ cdl_component CYGHWR_DEVS_SPI_CORTEXM_ST
             initialising SPI bus 3, freeing up the SPI interface pins.
         "
         flavor        bool
-        default_value false
+        default_value 0
     }
 
     cdl_option CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_CS_GPIOS {
         display       "SPI chip selects"
         description   "
             This is a comma separated list of GPIOs which are to be used as chip
-            select lines for the SPI bus.  For the purposes of specifying
-            which GPIOs to use, they are numbered consecutively from 0 (A0)
-            through 16 (B0) to 111 (G15).
+            select lines for the SPI bus. Each GPIO is defined by the SPI_CS()
+            macro which gives the port and pin number.
         "
         flavor        data
-        default_value { "15" }
+        default_value { "SPI_CS(A, 15)" }
     }
 
     cdl_option CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE {
@@ -209,21 +207,65 @@ cdl_component CYGHWR_DEVS_SPI_CORTEXM_ST
     cdl_option CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_TXINTR_PRI {
         display       "Transmit DMA interrupt priority"
         flavor        data
-        default_value 9
+        default_value 64+9
     }
 
     cdl_option CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_RXINTR_PRI {
         display       "Receive DMA interrupt priority"
         flavor        data
-        default_value 10
+        default_value 128+10
     }
 }
 
-cdl_option CYGPKG_DEVS_SPI_CORTEXM_STM32_TESTS {
-    display         "SPI tests"
-    flavor          data
-    no_define
-    calculated      { "tests/loopback" } 
+cdl_component CYGPKG_DEVS_SPI_CORTEXM_STM32_OPTIONS {
+    display "ST STM32 SPI driver build options"
+    flavor  none
+    description   "
+	Package specific build options including control over
+	compiler flags used only in building this package,
+	and details of which tests are built."
+
+    cdl_option CYGPKG_DEVS_SPI_CORTEXM_STM32_CFLAGS_ADD {
+        display "Additional compiler flags"
+        flavor  data
+        no_define
+        default_value { "" }
+        description   "
+            This option modifies the set of compiler flags for
+            building the STM32 SPI driver. These flags are used in addition
+            to the set of global flags."
+    }
+
+    cdl_option CYGPKG_DEVS_SPI_CORTEXM_STM32_CFLAGS_REMOVE {
+        display "Suppressed compiler flags"
+        flavor  data
+        no_define
+        default_value { "" }
+        description   "
+            This option modifies the set of compiler flags for
+            building the STM32 SPI driver. These flags are removed from
+            the set of global flags if present."
+    }
+
+    cdl_option CYGBLD_DEVS_SPI_CORTEXM_STM32_LOOPBACK_TEST {
+        display       "Build STM32 SPI loopback test"
+        flavor        bool
+        no_define
+        default_value 0
+        requires      CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1
+        description   "
+            This option enables the building of the STM32 SPI loopback test.
+            Refer to the comments in tests/loopback.c for details of how to
+            use this test."
+    }
+
+    cdl_option CYGPKG_DEVS_SPI_CORTEXM_STM32_TESTS {
+        display         "SPI tests"
+        active_if       CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1
+        flavor          data
+        no_define
+        calculated      { CYGBLD_DEVS_SPI_CORTEXM_STM32_LOOPBACK_TEST ? "tests/loopback" : "" } 
+    }
 }
 
 }
diff --git a/packages/devs/spi/cortexm/stm32/current/include/spi_stm32.h b/packages/devs/spi/cortexm/stm32/current/include/spi_stm32.h
--- a/packages/devs/spi/cortexm/stm32/current/include/spi_stm32.h
+++ b/packages/devs/spi/cortexm/stm32/current/include/spi_stm32.h
@@ -10,7 +10,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008, 2009 Free Software Foundation, Inc.
+// Copyright (C) 2008, 2009, 2012 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -41,7 +41,7 @@
 //=============================================================================
 //#####DESCRIPTIONBEGIN####
 //
-// Author(s):   Chris Holgate
+// Author(s):   Chris Holgate, nickg
 // Date:        2008-11-27
 // Purpose:     STM32 SPI driver definitions.
 // Description: 
@@ -59,6 +59,8 @@
 #include <cyg/hal/drv_api.h>
 #include <cyg/io/spi.h>
 
+#include <cyg/hal/var_dma.h>
+
 //-----------------------------------------------------------------------------
 // Macro for defining a SPI device and attaching it to the appropriate bus.
 //
@@ -102,16 +104,14 @@ extern cyg_spi_device _name_ __attribute
 
 typedef struct cyg_spi_cortexm_stm32_bus_setup_s
 {
-    cyg_uint32        apb_freq;        // Peripheral bus frequency (fp).
+    cyg_uint32        *apb_freq;       // Peripheral bus frequency.
     cyg_haladdress    spi_reg_base;    // Base address of SPI register block.
-    cyg_haladdress    dma_reg_base;    // Base address of DMA register block.
-    cyg_uint8         dma_tx_channel;  // TX DMA channel for this bus.
-    cyg_uint8         dma_rx_channel;  // RX DMA channel for this bus.
+
+    cyg_uint32        spi_enable;      // SPI bus clock enable
     cyg_uint8         cs_gpio_num;     // Number of chip selects for this bus.
-    const cyg_uint8*  cs_gpio_list;    // List of GPIOs used as chip selects.
-    const cyg_uint8*  spi_gpio_list;   // List of GPIOs used by the SPI interface.
-    cyg_vector_t      dma_tx_intr;     // Interrupt used for DMA transmit.
-    cyg_vector_t      dma_rx_intr;     // Interrupt used for DMA receive.
+    const cyg_uint32* cs_gpio_list;    // List of GPIOs used as chip selects.
+    const cyg_uint32* spi_gpio_list;   // List of GPIOs used by the SPI interface.
+    cyg_uint32        spi_gpio_remap;  // Remap GPIO lines to alternate pins.
     cyg_priority_t    dma_tx_intr_pri; // Interrupt priority for DMA transmit.
     cyg_priority_t    dma_rx_intr_pri; // Interrupt priority for DMA receive.
     cyg_uint32        bbuf_size;       // Size of bounce buffers.
@@ -129,10 +129,9 @@ typedef struct cyg_spi_cortexm_stm32_bus
     const cyg_spi_cortexm_stm32_bus_setup_t* setup;
 
     // ---- Driver state (private) ----
-    cyg_interrupt     tx_intr_data;    // DMA interrupt data (TX).
-    cyg_interrupt     rx_intr_data;    // DMA interrupt data (RX).
-    cyg_handle_t      tx_intr_handle;  // DMA interrupt handle (TX).
-    cyg_handle_t      rx_intr_handle;  // DMA interrupt handle (RX).
+
+    hal_stm32_dma_stream dma_tx_stream;  // TX DMA stream for this bus.
+    hal_stm32_dma_stream dma_rx_stream;  // RX DMA stream for this bus.
     cyg_drv_mutex_t   mutex;           // Transfer mutex.
     cyg_drv_cond_t    condvar;         // Transfer condition variable.
     cyg_bool          tx_dma_done;     // Flags used to signal completion.
diff --git a/packages/devs/spi/cortexm/stm32/current/src/spi_stm32.c b/packages/devs/spi/cortexm/stm32/current/src/spi_stm32.c
--- a/packages/devs/spi/cortexm/stm32/current/src/spi_stm32.c
+++ b/packages/devs/spi/cortexm/stm32/current/src/spi_stm32.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008, 2009 Free Software Foundation, Inc.
+// Copyright (C) 2008, 2009, 2011, 2012 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -39,7 +39,7 @@
 //=============================================================================
 //#####DESCRIPTIONBEGIN####
 //
-// Author(s):   Chris Holgate
+// Author(s):   Chris Holgate, nickg
 // Date:        2008-11-27
 // Purpose:     STM32 SPI driver implementation
 //
@@ -64,12 +64,21 @@
 #include <string.h>
 
 //-----------------------------------------------------------------------------
-// Work out the bus clock frequencies.
+// Diagnostics
 
-#define APB1_FREQ ((CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK * CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL) / \
-  (CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV * CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV)) 
-#define APB2_FREQ ((CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK * CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL) / \
-  (CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV * CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV)) 
+#if 0
+#define spi_diag( __fmt, ... ) diag_printf("SPI: %30s[%3d]: " __fmt, __FUNCTION__, __LINE__, ## __VA_ARGS__ );
+#define spi_dump_buf( __addr, __size ) diag_dump_buf( __addr, __size )
+#else
+#define spi_diag( __fmt, ... )
+#define spi_dump_buf( __addr, __size )
+#endif
+
+//-----------------------------------------------------------------------------
+// Bus frequencies
+
+__externC cyg_uint32 hal_stm32_pclk1;
+__externC cyg_uint32 hal_stm32_pclk2;
 
 //-----------------------------------------------------------------------------
 // API function call forward references.
@@ -82,6 +91,12 @@ static int  stm32_get_config           (
 static int  stm32_set_config           (cyg_spi_device*, cyg_uint32, const void*, cyg_uint32*);
 
 //-----------------------------------------------------------------------------
+// DMA callbacks
+
+static void stm32_dma_tx_callback( hal_stm32_dma_stream *stream, cyg_uint32 count, CYG_ADDRWORD data );
+static void stm32_dma_rx_callback( hal_stm32_dma_stream *stream, cyg_uint32 count, CYG_ADDRWORD data );
+
+//-----------------------------------------------------------------------------
 // Null data source and sink must be placed in the on-chip SRAM.  This is
 // either done explicitly (bounce buffers instantiated) or implicitly (no
 // bounce buffers implies that the data area is already on SRAM).
@@ -98,11 +113,61 @@ static cyg_uint16 dma_rx_null = 0xFFFF;
 #endif
 
 //-----------------------------------------------------------------------------
+// Useful GPIO macros for 'dynamic' pin setup.
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE == 2)
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_SPEED_SPI CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ
+
+#elif (CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE == 10)
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_SPEED_SPI CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ
+
+#elif (CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE == 50)
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_SPEED_SPI CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ
+
+#else
+#error "Invalid SPI bus toggle rate."
+#endif
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE == 2)
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_SPEED_SPI CYGHWR_HAL_STM32_GPIO_OSPEED_2MHZ
+
+#elif (CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE == 25)
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_SPEED_SPI CYGHWR_HAL_STM32_GPIO_OSPEED_25MHZ
+
+#elif (CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE == 50)
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_SPEED_SPI CYGHWR_HAL_STM32_GPIO_OSPEED_50MHZ
+
+#elif (CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE == 80)
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_SPEED_SPI CYGHWR_HAL_STM32_GPIO_OSPEED_HIGH
+
+#elif (CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE == 100)
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_SPEED_SPI CYGHWR_HAL_STM32_GPIO_OSPEED_HIGH
+
+#else
+#error "Invalid SPI bus toggle rate."
+#endif
+
+#else
+
+#error "Unknown STM32 family"
+
+#endif
+
+#define SPI_CS( __port, __bit )         CYGHWR_HAL_STM32_PIN_OUT( __port, __bit, PUSHPULL, NONE, SPEED_SPI )
+
+//-----------------------------------------------------------------------------
+
 // Instantiate the bus state data structures.
 
 #ifdef CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1
-static const cyg_uint8 bus1_cs_gpio_list[] = { CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1_CS_GPIOS };
-static const cyg_uint8 bus1_spi_gpio_list[] = { 0x05, 0x06, 0x07 };
+static const cyg_uint32 bus1_cs_gpio_list[] = { CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1_CS_GPIOS };
+static const cyg_uint32 bus1_spi_gpio_list[] = { CYGHWR_HAL_STM32_SPI1_SCK,
+                                                 CYGHWR_HAL_STM32_SPI1_MISO,
+                                                 CYGHWR_HAL_STM32_SPI1_MOSI };
 
 #if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE > 0)
 static cyg_uint8 bus1_tx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE] 
@@ -112,18 +177,16 @@ static cyg_uint8 bus1_rx_bbuf [CYGNUM_DE
 #endif
 
 static const cyg_spi_cortexm_stm32_bus_setup_t bus1_setup = {
-  .apb_freq                         = APB2_FREQ,
+  .apb_freq                         = &hal_stm32_pclk2,
   .spi_reg_base                     = CYGHWR_HAL_STM32_SPI1,
-  .dma_reg_base                     = CYGHWR_HAL_STM32_DMA1,
-  .dma_tx_channel                   = 3,
-  .dma_rx_channel                   = 2,
-  .cs_gpio_num                      = sizeof (bus1_cs_gpio_list),
+  .spi_enable                       = CYGHWR_HAL_STM32_SPI1_CLOCK,
+  .cs_gpio_num                      = sizeof (bus1_cs_gpio_list)/sizeof(cyg_uint32),
   .cs_gpio_list                     = bus1_cs_gpio_list,
   .spi_gpio_list                    = bus1_spi_gpio_list,
-  .dma_tx_intr                      = CYGNUM_HAL_INTERRUPT_DMA1_CH3,
-  .dma_rx_intr                      = CYGNUM_HAL_INTERRUPT_DMA1_CH2,
+  .spi_gpio_remap                   = CYGHWR_HAL_STM32_SPI1_REMAP_CONFIG,
   .dma_tx_intr_pri                  = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_TXINTR_PRI,
   .dma_rx_intr_pri                  = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_RXINTR_PRI,
+
 #if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE > 0)
   .bbuf_size                        = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE,
   .bbuf_tx                          = bus1_tx_bbuf,
@@ -141,13 +204,26 @@ cyg_spi_cortexm_stm32_bus_t cyg_spi_stm3
   .spi_bus.spi_get_config           = stm32_get_config,
   .spi_bus.spi_set_config           = stm32_set_config,
   .setup                            = &bus1_setup,
-  .cs_up                            = false
+  .cs_up                            = false,
+
+  .dma_tx_stream.desc                 = CYGHWR_HAL_STM32_SPI1_DMA_TX,
+  .dma_tx_stream.callback             = stm32_dma_tx_callback,
+  .dma_tx_stream.data                 = (CYG_ADDRWORD)&cyg_spi_stm32_bus1,
+
+  .dma_rx_stream.desc                 = CYGHWR_HAL_STM32_SPI1_DMA_RX,
+  .dma_rx_stream.callback             = stm32_dma_rx_callback,
+  .dma_rx_stream.data                 = (CYG_ADDRWORD)&cyg_spi_stm32_bus1,
+  
+  
+  
 };
 #endif
 
 #ifdef CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2
-static const cyg_uint8 bus2_cs_gpio_list[] = { CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2_CS_GPIOS };
-static const cyg_uint8 bus2_spi_gpio_list[] = { 0x1D, 0x1E, 0x1F };
+static const cyg_uint32 bus2_cs_gpio_list[] = { CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2_CS_GPIOS };
+static const cyg_uint32 bus2_spi_gpio_list[] = { CYGHWR_HAL_STM32_SPI2_SCK,
+                                                 CYGHWR_HAL_STM32_SPI2_MISO,
+                                                 CYGHWR_HAL_STM32_SPI2_MOSI };
 
 #if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE > 0)
 static cyg_uint8 bus2_tx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE] 
@@ -157,18 +233,16 @@ static cyg_uint8 bus2_rx_bbuf [CYGNUM_DE
 #endif
 
 static const cyg_spi_cortexm_stm32_bus_setup_t bus2_setup = {
-  .apb_freq                         = APB1_FREQ,
+  .apb_freq                         = &hal_stm32_pclk1,
   .spi_reg_base                     = CYGHWR_HAL_STM32_SPI2,
-  .dma_reg_base                     = CYGHWR_HAL_STM32_DMA1,
-  .dma_tx_channel                   = 5,
-  .dma_rx_channel                   = 4,
-  .cs_gpio_num                      = sizeof (bus2_cs_gpio_list),
+  .spi_enable                       = CYGHWR_HAL_STM32_SPI2_CLOCK,
+  .cs_gpio_num                      = sizeof (bus2_cs_gpio_list)/sizeof(cyg_uint32),
   .cs_gpio_list                     = bus2_cs_gpio_list,
   .spi_gpio_list                    = bus2_spi_gpio_list,
-  .dma_tx_intr                      = CYGNUM_HAL_INTERRUPT_DMA1_CH5,
-  .dma_rx_intr                      = CYGNUM_HAL_INTERRUPT_DMA1_CH4,
+  .spi_gpio_remap                   = CYGHWR_HAL_STM32_SPI2_REMAP_CONFIG,  
   .dma_tx_intr_pri                  = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_TXINTR_PRI,
   .dma_rx_intr_pri                  = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_RXINTR_PRI,
+
 #if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE > 0)
   .bbuf_size                        = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE,
   .bbuf_tx                          = bus2_tx_bbuf,
@@ -186,34 +260,44 @@ cyg_spi_cortexm_stm32_bus_t cyg_spi_stm3
   .spi_bus.spi_get_config           = stm32_get_config,
   .spi_bus.spi_set_config           = stm32_set_config,
   .setup                            = &bus2_setup,
-  .cs_up                            = false
+  .cs_up                            = false,
+
+  .dma_tx_stream.desc                 = CYGHWR_HAL_STM32_SPI2_DMA_TX,
+  .dma_tx_stream.callback             = stm32_dma_tx_callback,
+  .dma_tx_stream.data                 = (CYG_ADDRWORD)&cyg_spi_stm32_bus2,
+
+  .dma_rx_stream.desc                 = CYGHWR_HAL_STM32_SPI2_DMA_RX,
+  .dma_rx_stream.callback             = stm32_dma_rx_callback,
+  .dma_rx_stream.data                 = (CYG_ADDRWORD)&cyg_spi_stm32_bus2,
+  
+  
 };
 #endif
 
 #ifdef CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3
-static const cyg_uint8 bus3_cs_gpio_list[] = { CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_CS_GPIOS };
-static const cyg_uint8 bus3_spi_gpio_list[] = { 0x13, 0x14, 0x15 };
+static const cyg_uint32 bus3_cs_gpio_list[] = { CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_CS_GPIOS };
+static const cyg_uint32 bus3_spi_gpio_list[] = { CYGHWR_HAL_STM32_SPI3_SCK,
+                                                 CYGHWR_HAL_STM32_SPI3_MISO,
+                                                 CYGHWR_HAL_STM32_SPI3_MOSI };
 
 #if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE > 0)
 static cyg_uint8 bus3_tx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE] 
   __attribute__((aligned (2), section (".sram"))) = { 0 };
 static cyg_uint8 bus3_rx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE] 
-  __attribute__((alugned (2), section (".sram"))) = { 0 };
+  __attribute__((aligned (2), section (".sram"))) = { 0 };
 #endif
 
 static const cyg_spi_cortexm_stm32_bus_setup_t bus3_setup = {
-  .apb_freq                         = APB1_FREQ,
+  .apb_freq                         = &hal_stm32_pclk1,
   .spi_reg_base                     = CYGHWR_HAL_STM32_SPI3,
-  .dma_reg_base                     = CYGHWR_HAL_STM32_DMA2,
-  .dma_tx_channel                   = 2,
-  .dma_rx_channel                   = 1,
-  .cs_gpio_num                      = sizeof (bus3_cs_gpio_list),
+  .spi_enable                       = CYGHWR_HAL_STM32_SPI3_CLOCK,
+  .cs_gpio_num                      = sizeof (bus3_cs_gpio_list)/sizeof(cyg_uint32),
   .cs_gpio_list                     = bus3_cs_gpio_list,
   .spi_gpio_list                    = bus3_spi_gpio_list,
-  .dma_tx_intr                      = CYGNUM_HAL_INTERRUPT_DMA2_CH2,
-  .dma_rx_intr                      = CYGNUM_HAL_INTERRUPT_DMA2_CH1,
+  .spi_gpio_remap                   = CYGHWR_HAL_STM32_SPI3_REMAP_CONFIG,  
   .dma_tx_intr_pri                  = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_TXINTR_PRI,
   .dma_rx_intr_pri                  = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_RXINTR_PRI,
+
 #if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE > 0)
   .bbuf_size                        = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE,
   .bbuf_tx                          = bus3_tx_bbuf,
@@ -231,39 +315,18 @@ cyg_spi_cortexm_stm32_bus_t cyg_spi_stm3
   .spi_bus.spi_get_config           = stm32_get_config,
   .spi_bus.spi_set_config           = stm32_set_config,
   .setup                            = &bus3_setup,
-  .cs_up                            = false
-};
-#endif
-
-//-----------------------------------------------------------------------------
-// Useful GPIO macros for 'dynamic' pin setup.
+  .cs_up                            = false,
 
-static const cyg_uint32 stm32_gpio_port_offsets[] = {
-  CYGHWR_HAL_STM32_GPIOA - CYGHWR_HAL_STM32_GPIOA,
-  CYGHWR_HAL_STM32_GPIOB - CYGHWR_HAL_STM32_GPIOA,
-  CYGHWR_HAL_STM32_GPIOC - CYGHWR_HAL_STM32_GPIOA,
-  CYGHWR_HAL_STM32_GPIOD - CYGHWR_HAL_STM32_GPIOA,
-  CYGHWR_HAL_STM32_GPIOE - CYGHWR_HAL_STM32_GPIOA,
-  CYGHWR_HAL_STM32_GPIOF - CYGHWR_HAL_STM32_GPIOA,
-  CYGHWR_HAL_STM32_GPIOG - CYGHWR_HAL_STM32_GPIOA
-};
+  .dma_tx_stream.desc                 = CYGHWR_HAL_STM32_SPI3_DMA_TX,
+  .dma_tx_stream.callback             = stm32_dma_tx_callback,
+  .dma_tx_stream.data                 = (CYG_ADDRWORD)&cyg_spi_stm32_bus3,
 
-#define STM32_GPIO_PINSPEC(__port, __bit, __mode, __cnf )          \
-  (stm32_gpio_port_offsets[__port] | (__bit<<16) |                 \
-  (CYGHWR_HAL_STM32_GPIO_MODE_##__mode) |                          \
-  (CYGHWR_HAL_STM32_GPIO_CNF_##__cnf))
-
-#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE == 2)
-#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_SPI CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ
+  .dma_rx_stream.desc                 = CYGHWR_HAL_STM32_SPI3_DMA_RX,
+  .dma_rx_stream.callback             = stm32_dma_rx_callback,
+  .dma_rx_stream.data                 = (CYG_ADDRWORD)&cyg_spi_stm32_bus3,
 
-#elif (CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE == 10)
-#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_SPI CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ
 
-#elif (CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE == 50)
-#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_SPI CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ
-
-#else
-#error "Invalid SPI bus toggle rate."
+};
 #endif
 
 //-----------------------------------------------------------------------------
@@ -272,17 +335,8 @@ static const cyg_uint32 stm32_gpio_port_
 static inline void stm32_spi_gpio_cs_setup
   (cyg_uint32 gpio_num)
 {
-  cyg_uint32 port, pin, pinspec;
-
-  // Check that the pin number is in range (16 pins per port).
-  pin = gpio_num & 0xF;
-  port = gpio_num >> 4;
-  CYG_ASSERT (port < 7, "STM32 SPI : Invalid GPIO number in chip select list."); 
-
-  // Generate the pin setup specification and configure it.
-  pinspec = STM32_GPIO_PINSPEC (port, pin, OUT_SPI, OUT_PUSHPULL);
-  CYGHWR_HAL_STM32_GPIO_SET (pinspec);
-  CYGHWR_HAL_STM32_GPIO_OUT (pinspec, 1);
+  CYGHWR_HAL_STM32_GPIO_SET (gpio_num);
+  CYGHWR_HAL_STM32_GPIO_OUT (gpio_num, 1);
 }
 
 //-----------------------------------------------------------------------------
@@ -291,74 +345,15 @@ static inline void stm32_spi_gpio_cs_set
 static inline void stm32_spi_chip_select
   (cyg_uint32 gpio_num, cyg_bool assert)
 {
-  cyg_uint32 port, pin, pinspec;
-
-  // Check that the pin number is in range (16 pins per port).
-  pin = gpio_num & 0xF;
-  port = gpio_num >> 4;
-  CYG_ASSERT (port < 7, "STM32 SPI : Invalid GPIO number in chip select list."); 
-
-  // Generate the pin setup specification and drive it.
-  pinspec = STM32_GPIO_PINSPEC (port, pin, OUT_SPI, OUT_PUSHPULL);
-  CYGHWR_HAL_STM32_GPIO_OUT (pinspec, assert ? 0 : 1);
+  CYGHWR_HAL_STM32_GPIO_OUT( gpio_num, assert ? 0 : 1);
 }
 
 //-----------------------------------------------------------------------------
-// Implement DMA ISRs.  These disable the DMA channel, mask the interrupt 
-// condition and schedule their respective DSRs.
-
-static cyg_uint32 stm32_tx_ISR 
-  (cyg_vector_t vector, cyg_addrword_t data)
-{
-  cyg_spi_cortexm_stm32_bus_t* stm32_bus = (cyg_spi_cortexm_stm32_bus_t*) data;
-  cyg_uint32 chan = stm32_bus->setup->dma_tx_channel;
-  cyg_haladdress reg_addr;
-
-  // Disable the DMA channel.
-  cyg_drv_isr_lock ();
-  reg_addr = stm32_bus->setup->dma_reg_base + CYGHWR_HAL_STM32_DMA_CCR (chan);
-  HAL_WRITE_UINT32 (reg_addr, 0);
-
-  // Clear down the interrupts.
-  reg_addr = stm32_bus->setup->dma_reg_base + CYGHWR_HAL_STM32_DMA_IFCR;
-  HAL_WRITE_UINT32 (reg_addr, CYGHWR_HAL_STM32_DMA_IFCR_MASK (chan));
-
-  cyg_drv_interrupt_acknowledge (vector);
-  cyg_drv_interrupt_mask (vector);
-  cyg_drv_isr_unlock ();
-
-  return (CYG_ISR_CALL_DSR | CYG_ISR_HANDLED);
-}
+// DMA Callbacks. The DMA driver has disabled the DMA channel and
+// masked the interrupt condition, here we need to wake up the client
+// thread.
 
-static cyg_uint32 stm32_rx_ISR 
-  (cyg_vector_t vector, cyg_addrword_t data)
-{
-  cyg_spi_cortexm_stm32_bus_t* stm32_bus = (cyg_spi_cortexm_stm32_bus_t*) data;
-  cyg_uint32 chan = stm32_bus->setup->dma_rx_channel;
-  cyg_haladdress reg_addr;
-
-  // Disable the DMA channel.
-  cyg_drv_isr_lock ();
-  reg_addr = stm32_bus->setup->dma_reg_base + CYGHWR_HAL_STM32_DMA_CCR (chan);
-  HAL_WRITE_UINT32 (reg_addr, 0);
-
-  // Clear down the interrupts.
-  reg_addr = stm32_bus->setup->dma_reg_base + CYGHWR_HAL_STM32_DMA_IFCR;
-  HAL_WRITE_UINT32 (reg_addr, CYGHWR_HAL_STM32_DMA_IFCR_MASK (chan));
-
-  cyg_drv_interrupt_acknowledge (vector);
-  cyg_drv_interrupt_mask (vector);
-  cyg_drv_isr_unlock ();
-
-  return (CYG_ISR_CALL_DSR | CYG_ISR_HANDLED);
-}
-
-//-----------------------------------------------------------------------------
-// Implement DMA DSRs.  These clear down the interrupt conditions and assert 
-// their respective 'transaction complete' flags.
-
-static void stm32_tx_DSR 
-  (cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
+static void stm32_dma_tx_callback( hal_stm32_dma_stream *stream, cyg_uint32 count, CYG_ADDRWORD data )
 {
   cyg_spi_cortexm_stm32_bus_t* stm32_bus = (cyg_spi_cortexm_stm32_bus_t*) data;
 
@@ -368,8 +363,7 @@ static void stm32_tx_DSR
   cyg_drv_dsr_unlock ();
 }
 
-static void stm32_rx_DSR 
-  (cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
+static void stm32_dma_rx_callback( hal_stm32_dma_stream *stream, cyg_uint32 count, CYG_ADDRWORD data )
 {
   cyg_spi_cortexm_stm32_bus_t* stm32_bus = (cyg_spi_cortexm_stm32_bus_t*) data;
  
@@ -387,56 +381,47 @@ static void stm32_spi_bus_setup
 {
   int i;
   cyg_haladdress reg_addr;
-  cyg_uint32 pin, pinspec, reg_data;
+  cyg_uint32 reg_data;  
 
+  spi_diag("bus %p\n", stm32_bus );  
   // Set up the GPIOs for use as chip select lines.
   for (i = 0; i < stm32_bus->setup->cs_gpio_num; i ++) {
     stm32_spi_gpio_cs_setup (stm32_bus->setup->cs_gpio_list[i]);
   }
 
-  // Configure the SPI clock output pin.
-  pin = stm32_bus->setup->spi_gpio_list[0];
-  pinspec = STM32_GPIO_PINSPEC ((pin >> 4), (pin & 0xF), OUT_SPI, ALT_PUSHPULL);
-  CYGHWR_HAL_STM32_GPIO_SET (pinspec);
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+  // Remap GPIO pins if required
+  if( stm32_bus->setup->spi_gpio_remap )
+  {
+      CYG_ADDRESS afio = CYGHWR_HAL_STM32_AFIO;
+      cyg_uint32 mapr;
+      spi_diag("remap %08x\n", stm32_bus->setup->spi_gpio_remap );
+      CYGHWR_HAL_STM32_CLOCK_ENABLE( CYGHWR_HAL_STM32_AFIO_CLOCK );
+      HAL_READ_UINT32( afio+CYGHWR_HAL_STM32_AFIO_MAPR, mapr );
+      mapr |= stm32_bus->setup->spi_gpio_remap;
+      HAL_WRITE_UINT32( afio+CYGHWR_HAL_STM32_AFIO_MAPR, mapr );
+  }
+#endif
+  
+  CYGHWR_HAL_STM32_GPIO_SET( stm32_bus->setup->spi_gpio_list[0] );
+  CYGHWR_HAL_STM32_GPIO_SET( stm32_bus->setup->spi_gpio_list[1] );
+  CYGHWR_HAL_STM32_GPIO_SET( stm32_bus->setup->spi_gpio_list[2] );
 
-  // Configure the SPI MISO input.
-  pin = stm32_bus->setup->spi_gpio_list[1];
-  pinspec = STM32_GPIO_PINSPEC ((pin >> 4), (pin & 0xF), IN, PULLUP);
-  CYGHWR_HAL_STM32_GPIO_SET (pinspec);
-
-  // Configure the SPI MOSI output.  
-  pin = stm32_bus->setup->spi_gpio_list[2];
-  pinspec = STM32_GPIO_PINSPEC ((pin >> 4), (pin & 0xF), OUT_SPI, ALT_PUSHPULL);
-  CYGHWR_HAL_STM32_GPIO_SET (pinspec);
+  CYGHWR_HAL_STM32_CLOCK_ENABLE( stm32_bus->setup->spi_enable );
+  //CYGHWR_HAL_STM32_CLOCK_ENABLE( stm32_bus->setup->dma_enable );
 
   // Set up SPI default configuration.
   reg_addr = stm32_bus->setup->spi_reg_base + CYGHWR_HAL_STM32_SPI_CR2;
   reg_data = CYGHWR_HAL_STM32_SPI_CR2_TXDMAEN | CYGHWR_HAL_STM32_SPI_CR2_RXDMAEN;
   HAL_WRITE_UINT32 (reg_addr, reg_data);
 
-  // Ensure that the DMA clocks are enabled.
-  reg_addr = CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_AHBENR;
-  HAL_READ_UINT32 (reg_addr, reg_data);
-  if (stm32_bus->setup->dma_reg_base == CYGHWR_HAL_STM32_DMA1)
-    reg_data |= CYGHWR_HAL_STM32_RCC_AHBENR_DMA1;
-  else
-    reg_data |= CYGHWR_HAL_STM32_RCC_AHBENR_DMA2;
-  HAL_WRITE_UINT32 (reg_addr, reg_data);
-
   // Initialise the synchronisation primitivies.
   cyg_drv_mutex_init (&stm32_bus->mutex);
   cyg_drv_cond_init (&stm32_bus->condvar, &stm32_bus->mutex);
 
-  // Hook up the ISRs and DSRs.
-  cyg_drv_interrupt_create (stm32_bus->setup->dma_tx_intr, stm32_bus->setup->dma_tx_intr_pri, 
-    (cyg_addrword_t) stm32_bus, stm32_tx_ISR, stm32_tx_DSR, &stm32_bus->tx_intr_handle, 
-    &stm32_bus->tx_intr_data);
-  cyg_drv_interrupt_attach (stm32_bus->tx_intr_handle);
-
-  cyg_drv_interrupt_create (stm32_bus->setup->dma_rx_intr, stm32_bus->setup->dma_rx_intr_pri, 
-    (cyg_addrword_t) stm32_bus, stm32_rx_ISR, stm32_rx_DSR, &stm32_bus->rx_intr_handle, 
-    &stm32_bus->rx_intr_data);
-  cyg_drv_interrupt_attach (stm32_bus->rx_intr_handle);
+  // Initialize DMA streams
+  hal_stm32_dma_init( &stm32_bus->dma_tx_stream, stm32_bus->setup->dma_tx_intr_pri );
+  hal_stm32_dma_init( &stm32_bus->dma_rx_stream, stm32_bus->setup->dma_rx_intr_pri );
 
   // Call upper layer bus init.
   CYG_SPI_BUS_COMMON_INIT(&stm32_bus->spi_bus);
@@ -450,59 +435,22 @@ static void dma_channel_setup
 {
   cyg_spi_cortexm_stm32_bus_t* stm32_bus = (cyg_spi_cortexm_stm32_bus_t*) device->spi_bus;
   cyg_spi_cortexm_stm32_device_t* stm32_device = (cyg_spi_cortexm_stm32_device_t*) device;
-
-  cyg_uint32 chan, reg_data;
-  cyg_haladdress dma_reg_base, spi_reg_base, dma_addr, reg_addr;
+    hal_stm32_dma_stream *stream = is_tx ? &stm32_bus->dma_tx_stream : &stm32_bus->dma_rx_stream;
 
-  // Extract address and channel information.
-  dma_reg_base = stm32_bus->setup->dma_reg_base;
-  spi_reg_base = stm32_bus->setup->spi_reg_base;
-  chan = is_tx ? stm32_bus->setup->dma_tx_channel : stm32_bus->setup->dma_rx_channel;
+    hal_stm32_dma_configure( stream,
+                             stm32_device->bus_16bit ? 16 : 8,
+                             (data_buf==NULL),
+                             polled );
 
-  // Default options for the DMA channel.
-  reg_data = CYGHWR_HAL_STM32_DMA_CCR_EN;
-
-  // Do not enable interrupts in polled mode.
-  if (!polled)
-    reg_data |= CYGHWR_HAL_STM32_DMA_CCR_TCIE | CYGHWR_HAL_STM32_DMA_CCR_TEIE;
-
-  // Set DMA channel direction and priority level.  The receive channel has higher
-  // priority so that the inbound buffer is always cleared first.
-  if (is_tx) 
-    reg_data |= CYGHWR_HAL_STM32_DMA_CCR_DIR | CYGHWR_HAL_STM32_DMA_CCR_PLMEDIUM;
-  else 
-    reg_data |= CYGHWR_HAL_STM32_DMA_CCR_PLHIGH;
+    if( data_buf == NULL )
+        data_buf = (cyg_uint8 *)(is_tx ? &dma_tx_null : &dma_rx_null);
+    
+    hal_stm32_dma_start( stream,
+                         data_buf,
+                         stm32_bus->setup->spi_reg_base+CYGHWR_HAL_STM32_SPI_DR,
+                         count );
  
-  // Set the correct transfer size.
-  if (stm32_device->bus_16bit)
-    reg_data |= CYGHWR_HAL_STM32_DMA_CCR_PSIZE16 | CYGHWR_HAL_STM32_DMA_CCR_MSIZE16;
-  else 
-    reg_data |= CYGHWR_HAL_STM32_DMA_CCR_PSIZE8 | CYGHWR_HAL_STM32_DMA_CCR_MSIZE8;
-
-  // Do not use memory address incrementing for dummy data.
-  if (data_buf != NULL) {
-    reg_data |= CYGHWR_HAL_STM32_DMA_CCR_MINC;
-    dma_addr = (cyg_haladdress) data_buf;
-  }
-  else 
-    dma_addr = (cyg_haladdress) (is_tx ? &dma_tx_null : &dma_rx_null);
-
-  // Program up the DMA memory address.
-  reg_addr = dma_reg_base + CYGHWR_HAL_STM32_DMA_CMAR (chan);
-  HAL_WRITE_UINT32 (reg_addr, dma_addr);
-  
-  // Program up the peripheral memory address.
-  dma_addr = spi_reg_base + CYGHWR_HAL_STM32_SPI_DR;
-  reg_addr = dma_reg_base + CYGHWR_HAL_STM32_DMA_CPAR (chan);
-  HAL_WRITE_UINT32 (reg_addr, dma_addr);
-
-  // Program up the data buffer size.
-  reg_addr = dma_reg_base + CYGHWR_HAL_STM32_DMA_CNDTR (chan);
-  HAL_WRITE_UINT32 (reg_addr, count);
-
-  // Enable the DMA via the configuration register.
-  reg_addr = dma_reg_base + CYGHWR_HAL_STM32_DMA_CCR (chan);
-  HAL_WRITE_UINT32 (reg_addr, reg_data);
+    hal_stm32_dma_show( stream );
 }
 
 //-----------------------------------------------------------------------------
@@ -516,11 +464,10 @@ static void spi_transaction_dma
   cyg_spi_cortexm_stm32_device_t* stm32_device = (cyg_spi_cortexm_stm32_device_t*) device;
 
   cyg_haladdress reg_addr;
-  cyg_uint32 chan, reg_data;
 
-  cyg_haladdress dma_reg_base = stm32_bus->setup->dma_reg_base;
   cyg_haladdress spi_reg_base = stm32_bus->setup->spi_reg_base;
 
+  spi_diag("device %p\n", device );    
   // Ensure the chip select is asserted, inserting inter-transaction guard 
   // time if required.  Note that when ticking the device we do not touch the CS.
   if (!stm32_bus->cs_up && !tick_only) {
@@ -530,58 +477,30 @@ static void spi_transaction_dma
     CYGACC_CALL_IF_DELAY_US (stm32_device->cs_up_udly);
   }
 
+  // Clear done flags prior to configuring DMA:
+  stm32_bus->tx_dma_done = false;
+  stm32_bus->rx_dma_done = false;
+
   // Set up the DMA channels.
   dma_channel_setup (device, (cyg_uint8*) tx_data, count, true, polled);
   dma_channel_setup (device, rx_data, count, false, polled);
 
   // Run the DMA (polling for completion).
   if (polled) {
-    cyg_bool transfer_done = false;
-
     // Enable the SPI controller.
     reg_addr = spi_reg_base + CYGHWR_HAL_STM32_SPI_CR1;
     HAL_WRITE_UINT32 (reg_addr, stm32_device->spi_cr1_val | CYGHWR_HAL_STM32_SPI_CR1_SPE);
 
-    // Spin waiting on both DMA status flags.  Trap bus errors and assert in
-    // debug builds or return garbage in production builds.
-    reg_addr = dma_reg_base + CYGHWR_HAL_STM32_DMA_ISR;
-    do {
-      HAL_READ_UINT32 (reg_addr, reg_data);
-      if ((reg_data & CYGHWR_HAL_STM32_DMA_ISR_TEIF (stm32_bus->setup->dma_tx_channel)) ||
-          (reg_data & CYGHWR_HAL_STM32_DMA_ISR_TEIF (stm32_bus->setup->dma_rx_channel))) {
-        CYG_ASSERT (false, "STM32 SPI : DMA bus fault - enable bounce buffers.");
-        transfer_done = true;
-      }
-      if ((reg_data & CYGHWR_HAL_STM32_DMA_ISR_TCIF (stm32_bus->setup->dma_tx_channel)) &&
-          (reg_data & CYGHWR_HAL_STM32_DMA_ISR_TCIF (stm32_bus->setup->dma_rx_channel))) {
-        transfer_done = true;
-      }
-    } while (!transfer_done);
-
-    // Disable the DMA channels on completion and clear the status flags.
-    chan = stm32_bus->setup->dma_tx_channel;
-    reg_data = CYGHWR_HAL_STM32_DMA_IFCR_MASK (chan);
-    reg_addr = dma_reg_base + CYGHWR_HAL_STM32_DMA_CCR (chan);
-    HAL_WRITE_UINT32 (reg_addr, 0);
-
-    chan = stm32_bus->setup->dma_rx_channel;
-    reg_data |= CYGHWR_HAL_STM32_DMA_IFCR_MASK (chan);
-    reg_addr = dma_reg_base + CYGHWR_HAL_STM32_DMA_CCR (chan);
-    HAL_WRITE_UINT32 (reg_addr, 0);
-
-    reg_addr = dma_reg_base + CYGHWR_HAL_STM32_DMA_IFCR;
-    HAL_WRITE_UINT32 (reg_addr, reg_data);
+    while( !(stm32_bus->tx_dma_done && stm32_bus->rx_dma_done) )
+    {
+        hal_stm32_dma_poll( &stm32_bus->dma_tx_stream );
+        hal_stm32_dma_poll( &stm32_bus->dma_rx_stream );
+    }
   }
-
   // Run the DMA (interrupt driven).
   else {
     cyg_drv_mutex_lock (&stm32_bus->mutex);
     cyg_drv_dsr_lock ();
-    stm32_bus->tx_dma_done = false;
-    stm32_bus->rx_dma_done = false;
-
-    cyg_drv_interrupt_unmask (stm32_bus->setup->dma_tx_intr);
-    cyg_drv_interrupt_unmask (stm32_bus->setup->dma_rx_intr);
 
     // Enable the SPI controller.
     reg_addr = spi_reg_base + CYGHWR_HAL_STM32_SPI_CR1;
@@ -596,6 +515,7 @@ static void spi_transaction_dma
     cyg_drv_mutex_unlock (&stm32_bus->mutex);
   }
 
+  
   // Disable the SPI controller.
   reg_addr = spi_reg_base + CYGHWR_HAL_STM32_SPI_CR1;
   HAL_WRITE_UINT32 (reg_addr, stm32_device->spi_cr1_val);
@@ -609,11 +529,30 @@ static void spi_transaction_dma
 }
 
 //-----------------------------------------------------------------------------
+// Calculate BR bits for SPI_CR1.
+static int calculate_br_bits
+  (cyg_spi_cortexm_stm32_bus_t* bus, cyg_uint32 *target_clockrate, cyg_uint32 *br)
+{
+  cyg_uint32 divided_clk;
+
+  // Calculate the maximum viable bus speed.
+  divided_clk = *bus->setup->apb_freq / 2;
+  for (*br = 0; (*br < 7) && (divided_clk > *target_clockrate); (*br)++)
+    divided_clk >>= 1;
+
+  if ( divided_clk <= *target_clockrate )
+    return 0;
+
+  return -1;
+}
+
+//-----------------------------------------------------------------------------
 // Initialise SPI interfaces on startup.
 
 static void CYGBLD_ATTRIB_C_INIT_PRI(CYG_INIT_BUS_SPI)
 stm32_spi_init(void)
 {
+  spi_diag("\n");      
 #if defined(CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3) && \
     defined(CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_DISABLE_DEBUG_PORT)
   // Disable debug port, freeing up SPI bus 3 pins.
@@ -647,8 +586,9 @@ static void stm32_transaction_begin
   cyg_spi_cortexm_stm32_device_t* stm32_device = (cyg_spi_cortexm_stm32_device_t*) device;
 
   cyg_haladdress reg_addr;
-  cyg_uint32 reg_data, divided_clk, br;
+  cyg_uint32 reg_data, br;
 
+  spi_diag("\n");
   // On the first transaction, generate the values to be programmed into the
   // SPI configuration registers for this device and cache them.  This avoids
   // having to recalculate the prescaler for every transaction.
@@ -662,12 +602,10 @@ static void stm32_transaction_begin
     if (stm32_device->bus_16bit)
       reg_data |= CYGHWR_HAL_STM32_SPI_CR1_DFF;
 
-    // Calculate the maximum viable bus speed.
-    divided_clk = stm32_bus->setup->apb_freq / 2;
-    for (br = 0; (br < 7) && (divided_clk > stm32_device->cl_brate); br++)
-      divided_clk >>= 1;
-    CYG_ASSERT (divided_clk <= stm32_device->cl_brate, 
-      "STM32 SPI : Cannot run bus slowly enough for peripheral.");
+    // Get divider bits
+    if ( 0 != calculate_br_bits(stm32_bus, (cyg_uint32 *)&(stm32_device->cl_brate), &br) )
+      CYG_ASSERT (false, "STM32 SPI : Cannot run bus slowly enough for peripheral.");
+
     reg_data |= CYGHWR_HAL_STM32_SPI_CR1_BR (br);
 
     // Cache the configuration register settings.
@@ -692,6 +630,9 @@ static void stm32_transaction_transfer
   // Check for unsupported transactions.
   CYG_ASSERT (count > 0, "STM32 SPI : Null transfer requested.");
 
+  spi_diag("count %d\n", count);
+  if( tx_data ) spi_dump_buf(tx_data, count );
+  
   // We check that the buffers are half-word aligned and that count is a 
   // multiple of two in order to carry out the 16-bit transfer.
   if (stm32_device->bus_16bit) {
@@ -727,6 +668,10 @@ static void stm32_transaction_transfer
   else {
     spi_transaction_dma (device, false, polled, count, tx_data, rx_data, drop_cs);
   }
+
+  spi_diag("done\n");
+  if( rx_data ) spi_dump_buf(rx_data, count );
+  
 }
 
 //-----------------------------------------------------------------------------
@@ -741,6 +686,8 @@ static void stm32_transaction_tick
   // Check for unsupported transactions.
   CYG_ASSERT (count > 0, "STM32 SPI : Null transfer requested.");
 
+  spi_diag("count %d\n", count);
+
   // We check that count is a multiple of two in order to carry out the 16-bit transfer.
   if (stm32_device->bus_16bit) {
     CYG_ASSERT (!(count & 1),   
@@ -762,6 +709,7 @@ static void stm32_transaction_end
 
   cyg_haladdress reg_addr;
 
+  spi_diag("\n");  
   // Ensure that the chip select is deasserted.
   if (stm32_bus->cs_up) {
     CYGACC_CALL_IF_DELAY_US (stm32_device->cs_dw_udly);
@@ -775,18 +723,83 @@ static void stm32_transaction_end
 }
 
 //-----------------------------------------------------------------------------
-// Note that no dynamic configuration options are currently defined.
+static int stm32_get_config 
+  (cyg_spi_device* device, cyg_uint32 key, void* buf, cyg_uint32* len)
+{
+  cyg_spi_cortexm_stm32_bus_t* stm32_bus = (cyg_spi_cortexm_stm32_bus_t*) device->spi_bus;
+  cyg_spi_cortexm_stm32_device_t* stm32_device = (cyg_spi_cortexm_stm32_device_t*) device;
+  cyg_uint32* data_p = buf;
 
-static int stm32_get_config 
-  (cyg_spi_device* dev, cyg_uint32 key, void* buf, cyg_uint32* len)
-{
-    return -1;
+  switch (key)
+  {
+  case CYG_IO_GET_CONFIG_SPI_CLOCKRATE :
+    // Sanity check
+    if (NULL == len) {
+        CYG_ASSERT (false, "STM32 SPI : Null pointer as len argument for stm32_get_config().");
+        return -1;
+    }
+    if (sizeof(cyg_uint32) != *len) {
+        CYG_ASSERT (false, "STM32 SPI : Invalid length with stm32_get_config().");
+        return -1;
+    }
+    if (NULL == buf) {
+        CYG_ASSERT (false, "STM32 SPI : Null poiter as buf argument for stm32_get_config().");
+        return -1;
+    }
+
+    *data_p = *stm32_bus->setup->apb_freq >> ((( stm32_device->spi_cr1_val >> 3 ) & 7) + 1 ) ;
+    return 0;
+
+  default :
+    break;
+  }
+
+  return -1;
 }
 
-static int stm32_set_config 
-  (cyg_spi_device* dev, cyg_uint32 key, const void* buf, cyg_uint32* len)
+//-----------------------------------------------------------------------------
+static int stm32_set_config
+  (cyg_spi_device* device, cyg_uint32 key, const void* buf, cyg_uint32* len)
 {
-    return -1;
+  cyg_spi_cortexm_stm32_bus_t* stm32_bus = (cyg_spi_cortexm_stm32_bus_t*) device->spi_bus;
+  cyg_spi_cortexm_stm32_device_t* stm32_device = (cyg_spi_cortexm_stm32_device_t*) device;
+
+  cyg_uint32 br;
+
+  switch (key)
+  {
+  case CYG_IO_SET_CONFIG_SPI_CLOCKRATE :
+    // Sanity check
+    if (NULL == len) {
+      CYG_ASSERT (false, "STM32 SPI : Null pointer as len argument for stm32_set_config().");
+      return -1;
+    }
+    if (sizeof(cyg_uint32) != *len) {
+      CYG_ASSERT (false, "STM32 SPI : Invalid length with stm32_set_config().");
+      return -1;
+    }
+    if (NULL == buf) {
+      CYG_ASSERT (false, "STM32 SPI : Null pointer as buf argument for stm32_set_config().");
+      return -1;
+    }
+
+    // Get divider bits
+    if ( 0 != calculate_br_bits(stm32_bus, (cyg_uint32 *)buf, &br) ) {
+      CYG_ASSERT (false, "STM32 SPI : Cannot run bus as slowly as requested.");
+      return -1;
+    }
+
+    // Update the cache of the configuration register settings.
+    stm32_device->spi_cr1_val &= ~CYGHWR_HAL_STM32_SPI_CR1_BR(7);
+    stm32_device->spi_cr1_val |= CYGHWR_HAL_STM32_SPI_CR1_BR(br);
+
+    return 0;
+
+  default :
+    break;
+  }
+
+  return -1;
 }
 
 //=============================================================================
diff --git a/packages/devs/spi/freescale/dspi/current/ChangeLog b/packages/devs/spi/freescale/dspi/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/spi/freescale/dspi/current/ChangeLog
@@ -0,0 +1,79 @@
+2013-07-09  Mike Jones <mjones@proclivis.com>
+
+	* src/spi_freescale_dspi.c: Fix: Kinetis DSPI infinite polling
+	[ Bugzilla 10011879 ]
+
+2013-05-08  Ilija Kocho <ilijak@siva.com.mk>
+
+	* src/spi_freescale_dspi.cdl: Add CYGINT_DEVS_SPI_DMA_USE
+	* src/spi_freescale_dspi.c: Fix: Disable DMA requests for transfers
+	that don't use DMA. [ Bugzilla 1001815 ]
+
+2013-04-01  Ilija Kocho <ilijak@siva.com.mk>
+
+	* include/spi_freescale_dspi.h, include/spi_freescale_busses.inl
+	* include/spi_freescale_dspi_io.h, src/spi_freescale_dspi.c:
+	Optimised receiving of messages that fit in FIFO. Add clock gating.
+	Fix race condition bug in dspi_transaction_end(). [ Bugzilla 1001815 ]
+
+2013-02-06  Stefan Singer <stefan.singer@freescale.com>
+		    Ilija Kocho <ilijak@siva.com.mk>
+
+	* include/spi_freescale_dspi.h, include/spi_freescale_busses.inl
+	* include/spi_freescale_dspi_io.h, include/spi_freescale_dspi_bd.h,
+	* src/spi_freescale_dspi.c:
+	enhanced endianness support for devices with big and little endian
+	added support for MPC5xxx in addition to Kinetis
+	extended support for up to 8 DSPIs
+	(see Bugzilla 1001752).
+
+2012-12-28  Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/spi_freescale_dspi.cdl, src/spi_freescale_dspi.c:
+	Tick-only now has option to beehive like other drivers
+	rather than RM (see Bugzilla 1001676).
+	Fixed bug with dropping CS. Chip select options consolidated in a for loop.
+
+	* tests/spi_loopback.c: New file. Add looback test.
+	[Bugzilla 1001719]
+
+2012-05-04  Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/spi_freescale_dspi.cdl: 
+	* include/spi_freescale_dspi_buses.inl
+	* src/spi_freescale_dspi.c:
+	Add: support for 32 channel eDMA, support for cached memory.
+	[Bugzilla 1001579]
+
+2012-01-06  Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/spi_freescale_dspi.cdl: 
+	* include/spi_freescale_dspi.h
+	* include/spi_freescale_dspi_io.h:
+	* include/spi_freescale_dspi_buses.inl
+	* src/spi_freescale_dspi.c: 
+	New package -- Freescale DSPI SPI driver.  [Bugzilla 1001450]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/spi/freescale/dspi/current/cdl/spi_freescale_dspi.cdl b/packages/devs/spi/freescale/dspi/current/cdl/spi_freescale_dspi.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/spi/freescale/dspi/current/cdl/spi_freescale_dspi.cdl
@@ -0,0 +1,387 @@
+##=============================================================================
+##
+##      spi_freescale_dspi.cdl
+##
+##      Freescale DSPI driver configuration options.
+##
+##=============================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##=============================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):     Ilija Kocho
+## Date:          2011-11-03
+## Purpose:       Configure Freescale DSPI driver.
+##
+######DESCRIPTIONEND####
+##
+##=============================================================================
+
+cdl_package CYGPKG_DEVS_SPI_FREESCALE_DSPI {
+    display       "Freescale DSPI driver"
+    description   "
+        This package provides SPI driver support for the Freescale
+        microcontrollers that employ DSPI interface."
+
+    parent        CYGPKG_IO_SPI
+    active_if     CYGPKG_IO_SPI
+    requires      CYGPKG_HAL_CORTEXM_KINETIS || CYGPKG_HAL_POWERPC_MPC5xxx
+
+    hardware
+    include_dir   cyg/io
+    compile       spi_freescale_dspi.c
+
+    cdl_option CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE {
+        display "DSPI FIFO size"
+        flavor data
+        default_value 4
+        legal_values { 4 5 6 7 8 }
+    }
+
+    cdl_component CYGHWR_DEVS_SPI_FREESCALE_DSPI_CTAR_NUM {
+        display "CTAR registers"
+        flavor data
+        calculated 2
+
+        description "DSPI can have from 2 to 8 CTAR registers that keep
+            transfer communication settings. In eCos CTAR0 is used for
+            all normal transfers while CTAR1 is used as auxiliary for
+            'transaction end' (non)transfer."
+
+        cdl_component CYGHWR_DEVS_SPI_FREESCALEDSPI_DSPI_CTAR1_AUX {
+            display "CTAR1 Aux settings"
+            flavor none
+            no_define
+
+            cdl_component CYGHWR_DEVS_FREESCALEDSPI_DSPI_CTAR1_AUX_SPEED {
+                display "Nominal clock speed Hz"
+                flavor data
+                default_value 25000000
+
+                cdl_option CYGHWR_DEVS_FREESCALEDSPI_DSPI_CTAR1_AUX_USE_DBR {
+                    display "Use double baud rate"
+                    flavor bool
+                    default_value 1
+                    description "Double baud rate is a feature of Freescale DSPI
+                    that may provide higher baud rates but duty the cycle may be
+                    different than 50/50 depdent on scaler/prescaler setting
+                    for achieved baud rate."
+                }
+            }
+
+            cdl_option CYGHWR_DEVS_FREESCALEDSPI_DSPI_CTAR1_AUX_CS_DELAY {
+                display "Nominal chip select delay (units)"
+                flavor data
+                legal_values { 1 to 1000 }
+                default_value 1
+            }
+
+            cdl_option CYGHWR_DEVS_FREESCALE_DSPI_DSPI_CTAR1_AUX_DELAY_UNIT {
+                display "Chip select delay unit (ns)"
+                flavor data
+                calculated 100
+            }
+        }
+    }
+
+    cdl_interface CYGINT_DEVS_SPI_DSPI_DMA_USE {
+        display  "DSPI DMA use"
+        flavor   data
+        description "Number of DMA channels used by DSPI buses."
+    }
+
+    for { set ::spibus 0 } { $::spibus < 8 } { incr ::spibus } {
+
+        cdl_interface CYGINT_DEVS_SPI_FREESCALE_DSPI[set ::spibus] {
+            display "Number of devices using DSPI bus [set ::spibus]"
+        }
+
+        cdl_component CYGHWR_DEVS_SPI_FREESCALE_DSPI[set ::spibus] {
+            display "Freescale DSPI bus [set ::spibus]"
+            description "Enable DSPI bus [set :: spibus]."
+            flavor bool
+            default_value CYGINT_DEVS_SPI_FREESCALE_DSPI[set ::spibus]
+            active_if CYGINT_DEVS_SPI_FREESCALE_DSPI[set ::spibus]
+
+            implements CYGINT_HAL_DMA
+            requires   CYGPKG_HAL_FREESCALE_EDMA
+
+            cdl_component CYGHWR_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_CS {
+                display "Chip-selects"
+                flavor none
+                no_define
+                cdl_option CYHGWR_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_PCSS {
+                    display "Chip-select Strobe enable"
+                    flavor bool
+                    default_value 0
+
+                    requires CYHGWR_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_PCSS == 1 \
+                        implies CYGHWR_FREESCALE_DSPI[set ::spibus]_CS5 == 0
+                }
+
+                for { set ::spics 0 } { $::spics < 5 } { incr ::spics } {
+                    cdl_interface CYGINT_FREESCALE_DSPI[set ::spibus]_CS[set ::spics] {
+                        flavor bool
+                        requires CYGHWR_FREESCALE_DSPI[set ::spibus]_CS[set ::spics] == 1
+                        display "Use CS[set ::spics]"
+                    }
+
+                    cdl_component CYGHWR_FREESCALE_DSPI[set ::spibus]_CS[set ::spics] {
+                        display "CS[set ::spics]"
+                        flavor bool
+                        default_value 0
+                        cdl_option CYGHWR_FREESCALE_DSPI[set ::spibus]_CS[set ::spics]_IS {
+                            display "CS[set ::spics] Inactive state Hi(1) Lo(0)"
+                            flavor data
+                            no_define
+                            default_value { 1 }
+                            legal_values { 0 1 }
+                        }
+                    }
+                }
+
+                cdl_component CYGHWR_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_PCSIS {
+                    display "Peripheral CS inactive states"
+                    flavor data
+                    calculated (0x0 + \
+                        (get_data(CYGHWR_FREESCALE_DSPI[set ::spibus]_CS0_IS) == 1 ? 1 : 0) +      \
+                        (get_data(CYGHWR_FREESCALE_DSPI[set ::spibus]_CS1_IS) == 1 ? 2 : 0) +      \
+                        (get_data(CYGHWR_FREESCALE_DSPI[set ::spibus]_CS2_IS) == 1 ? 4 : 0) +      \
+                        (get_data(CYGHWR_FREESCALE_DSPI[set ::spibus]_CS3_IS) == 1 ? 8 : 0) +      \
+                        (get_data(CYGHWR_FREESCALE_DSPI[set ::spibus]_CS4_IS) == 1 ? 16 : 0) +     \
+                        (get_data(CYGHWR_FREESCALE_DSPI[set ::spibus]_CS5_IS) == 1 ? 32 : 0))
+                }
+            }
+
+            cdl_interface CYGINT_FREESCALE_DSPI[set ::spibus]_HAS_MASS {
+                description "SPI bus serves mass data device(s)."
+            }
+
+            cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_PUSHQUE_SIZE {
+                display "Queue buffer size"
+                description "
+                    DSPI requires a command for every transfer so output
+                    data must be re-packed in additional buffer prior to
+                    being submitted to DMA.
+                    If Queue capacity is same as DSPI FIFO size, the minimal
+                    legal value, the DMA is not needed so no buffer memory
+                    is allocated. Note: For every entry, byte (8 bit transfer)
+                    or half word (16 bit transfer) a whole 32 bit word
+                    is being allocated."
+
+                legal_values { CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE to 2048 }
+                flavor data
+                default_value  CYGINT_FREESCALE_DSPI[set ::spibus]_HAS_MASS ? 128 : \
+                    CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE
+            }
+
+            cdl_interface CYGINT_DEVS_SPI_DSPI[set ::spibus]_USES_DMA {
+                flavor bool
+            }
+
+            cdl_component CYGHWR_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_TX_DMA_CHAN {
+                display "TX DMA channel"
+                flavor data
+                implements CYGINT_DEVS_SPI_DSPI_DMA_USE
+                implements CYGINT_DEVS_SPI_DSPI[set ::spibus]_USES_DMA
+
+                active_if CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_PUSHQUE_SIZE > \
+                    CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE
+                default_value 4 + [set ::spibus] * 2
+                legal_values { 0 to (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM-1) }
+                description "DMA channel assigned to the trasmitter of SPI bus"
+
+                cdl_component CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_TX_DMA_PRI {
+                    display "Transmit DMA channel priority"
+                    flavor data
+                    legal_values  { 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 255 }
+                    default_value 255
+                    description "
+                    DMA can work in either round robin or preeptve arbitration
+                    mode. In preemptive mode, DMA each channel has unique priority,
+                    lower number meaning lower priority.
+                    255 is a phony meaning \"default channel priority\"."
+
+                    cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_TX_DMA_ECP {
+                        display "Enable channel preemption"
+                        flavor data
+                        legal_values { 0 1 }
+                        default_value 0
+                    }
+
+                    cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_TX_DMA_DPA {
+                        display "Disable preempt ability"
+                        flavor data
+                        legal_values { 0 1 }
+                        default_value 0
+                    }
+
+                }
+
+                cdl_option CYGOPT_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_TCD_SECTION {
+                    display "DMA TCD section"
+                    flavor data
+                    default_value CYGHWR_HAL_EDMA_TCD_SECTION
+
+                    description "
+                    Section in which will be DMA Transfer Control
+                    Descriptors shall reside"
+                }
+            }
+
+            cdl_component CYGHWR_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_RX_DMA_CHAN {
+                display "RX DMA channel"
+                flavor data
+                implements CYGINT_DEVS_SPI_DSPI_DMA_USE
+                implements CYGINT_DEVS_SPI_DSPI[set ::spibus]_USES_DMA
+
+                active_if CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_PUSHQUE_SIZE > \
+                    CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE
+                default_value 5 + [set ::spibus] * 2
+                legal_values { 0 to (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM-1) }
+                description "DMA channel assigned to the receiver of SPI bus"
+
+                cdl_component CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_RX_DMA_PRI {
+                    display "Receive DMA channel priority"
+                    flavor data
+                    legal_values { 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 255 }
+                    default_value 255
+                    description "
+                    DMA can work in either round robin or preeptve arbitration
+                    mode. In preemptive mode, DMA each channel has unique priority,
+                    lower number meaning lower priority.
+                    255 is a phony meaning \"default channel priority\"."
+
+                    cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_RX_DMA_ECP {
+                        display "Enable channel preemption"
+                        flavor data
+                        legal_values { 0 1 }
+                        default_value 0
+                    }
+
+                    cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_RX_DMA_DPA {
+                        display "Disable preempt ability"
+                        flavor data
+                        legal_values { 0 1 }
+                        default_value 0
+                    }
+                }
+            }
+
+            cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_ISR_PRI {
+                display "Interrupt priority"
+                flavor data
+                requires CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_ISR_PRI_SP
+                calculated CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_ISR_PRI_SP
+                description "Interrupt priority set-point is provided by HAL"
+            }
+        }
+    }
+
+    cdl_option CYGOPT_DEVS_SPI_FREESCALE_DSPI_TICK_ONLY_DROPS_CS {
+        display "Tick-only drops CS"
+        default_value 0
+
+        description "
+            eCos Reference Manual states that CS should drop prior to sending ticks,
+            but other drivers (so far) do not touch the CS. This option selects
+            between conformance with manual or compatibility with other drivers."
+    }
+
+    cdl_option CYGPKG_DEVS_SPI_FREESCALE_DSPI_DEBUG_LEVEL {
+        display "Driver debug output level"
+        flavor  data
+        legal_values { 0 1 2 3 }
+        default_value 0
+        description   "
+        This option specifies the level of debug data output by
+        the Freescale DSPI device driver. A value of 0 signifies
+        no debug data output; 1 signifies normal debug data
+        output; and 2 signifies maximum debug data output."
+    }
+
+
+    cdl_component CYGPKG_DEVS_SPI_FREESCALE_DSPI_OPTIONS {
+        display "Freescale DSPI driver build options"
+        flavor  none
+        description   "
+        Package specific build options including control over
+        compiler flags used only in building this package,
+        and details of which tests are built."
+
+        cdl_option CYGPKG_DEVS_SPI_FREESCALE_DSPI_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor data
+            no_define
+            default_value { "" }
+            description   "
+            This option modifies the set of compiler flags for
+            building the Freescale DSPI driver. These flags are used in addition
+            to the set of global flags."
+        }
+
+        cdl_option CYGPKG_DEVS_SPI_FREESCALE_DSPI_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor data
+            no_define
+            default_value { "" }
+            description   "
+            This option modifies the set of compiler flags for
+            building the Freescale DSPI driver. These flags are removed from
+            the set of global flags if present."
+        }
+
+    }
+
+    cdl_component CYGPKG_DEVS_SPI_FREESCALE_DSPI_TESTS {
+        display "Freescale DSPI tests"
+        flavor data
+        no_define
+        calculated { CYGBLD_DEVS_SPI_FREESCALE_DSPI_LOOPBACK_TEST ? "tests/spi_loopback" : "" }
+
+        cdl_option CYGBLD_DEVS_SPI_FREESCALE_DSPI_LOOPBACK_TEST {
+            display "Build Freescale DSPI loopback test"
+            flavor bool
+            no_define
+            default_value 0
+            requires  { CYGHWR_DEVS_SPI_FREESCALE_DSPI0 ||
+                CYGHWR_DEVS_SPI_FREESCALE_DSPI1 ||
+                CYGHWR_DEVS_SPI_FREESCALE_DSPI2 }
+            description  "
+                This option enables the building of the Freescale DSPI loopback test.
+                Refer to the comments in tests/loopback.c for details of how to
+                use this test."
+        }
+    }
+}
+# EOF spi_freescale_dspi.cdl
diff --git a/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi.h b/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi.h
@@ -0,0 +1,207 @@
+#ifndef CYGONCE_DEVS_SPI_FREESCALE_DSPI_H
+#define CYGONCE_DEVS_SPI_FREESCALE_DSPI_H
+//=============================================================================
+//
+//      spi_freescale_dspi.h
+//
+//      Header definitions for Freescale DSPI driver.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-11-03
+// Purpose:     Freescale DSPI driver definitions.
+// Description:
+// Usage:       #include <cyg/io/spi_freescale_dspi.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/io_spi.h>
+#include <pkgconf/devs_spi_freescale_dspi.h>
+#include <pkgconf/hal_freescale_edma.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/io/spi.h>
+#include <cyg/hal/freescale_edma.h>
+#include <cyg/io/spi_freescale_dspi_io.h>
+
+//-----------------------------------------------------------------------------
+// Macro for defining a SPI device and attaching it to the appropriate bus.
+//
+// _name_     is the name of the SPI device.  This will be used to reference a
+//              data structure of type cyg_spi_device which can be passed to the
+//              SPI driver API without needing a cast.
+// _bus_      is the bus number to which this device is attached (0, 1 or 2).
+// _csnum_    is the chip select line used for this device, numbered from 0.
+// _fmsz_     is set device SPI frame size (bits)
+// _clpol_    is the SPI bus clock polarity used by the device.  This must be
+//               set to 1 if clock inactive state is high, 0 if clock inactive
+//               state is low.
+// _clpha_    is the SPI bus clock phase used by the device.
+// _brate_    is the SPI bus clock baud rate used by the device, measured in Hz.
+// _csup_dly_ is the minimum delay between chip select assert and transfer
+//              start, measured in microseconds.
+// _csdw_dly_ is the minimum delay between transfer end and chip select deassert,
+//              measured in delay units.
+// _trbt_dly_ is the minimum delay between consecutive transfers.
+// _dlu_      is delay unit in ns
+// _dbr_      is enabling double baud rate feature
+
+
+#define CYGNUM_DSPI_DELAY_UNIT(__val) (__val/10)
+
+#define CYG_SPI_BUS_NAME(_b_) cyg_spi_dspi_bus ## _b_
+
+#define CYG_DEVS_SPI_FREESCALE_DSPI_DEVICE( \
+  _name_, _bus_, _csnum_, _fmsz_, _clpol_, _clpha_, _brate_, _csup_dly_, _csdw_dly_, _trbt_dly_, _dlu_, _dbr_ \
+) \
+ cyg_spi_freescale_dspi_device_t _name_ ##_fs_dspi CYG_SPI_DEVICE_ON_BUS(_bus_) = { \
+{ .spi_bus    = (cyg_spi_bus*) &CYG_SPI_BUS_NAME(_bus_) }, \
+  .dev_num    = _csnum_, \
+  .clocking.bus_16bit  = _fmsz_ > 8 ? 1 : 0, \
+  .clocking.frame_size = _fmsz_, \
+  .clocking.cl_pol     = _clpol_, \
+  .clocking.cl_pha     = _clpha_, \
+  .clocking.cl_brate   = _brate_, \
+  .clocking.cs_up_udly = _csup_dly_, \
+  .clocking.cs_dw_udly = _csdw_dly_, \
+  .clocking.tr_bt_udly = _trbt_dly_, \
+  .clocking.dl_unit    = CYGNUM_DSPI_DELAY_UNIT(_dlu_), \
+  .clocking.cl_dbr     = _dbr_, \
+  .clocking.dspi_ctar  = 0 \
+}; \
+extern cyg_spi_device _name_ __attribute__((alias ( #_name_ "_fs_dspi" )))
+
+enum { SPI_DMA_CHAN_TX_I, SPI_DMA_CHAN_RX_I };
+
+//-----------------------------------------------------------------------------
+// Freescale DSPI bus configuration and state.
+
+typedef struct cyg_spi_freescale_dspi_bus_setup_s
+{
+    cyghwr_devs_freescale_dspi_t*   dspi_p;    // Base address of SPI register block.
+    cyghwr_hal_freescale_dma_set_t* dma_set_p; // DMA configuration block.
+    cyg_vector_t                    intr_num;        // DSPI interrupt vector
+    cyg_priority_t                  intr_prio;       // Interrupt priority
+    cyg_uint32                      mcr_opt ;        // Module Configuratyon Register options
+    const cyg_uint32*               spi_pin_list_p;  // List of GPIOs used by the SPI interface.
+    const cyg_uint32*               cs_pin_list_p;   // List of GPIOs used as chip selects.
+    cyg_uint16                      clk_gate;        // Clock gate
+    cyg_uint8                       cs_pin_num;      // Number of chip selects for this bus.
+} cyg_spi_freescale_dspi_bus_setup_t;
+
+#define SPI_DMA_CHAN_I(__dma_set,__rt) (__dma_set->chan_p[SPI_DMA_CHAN_ ## __rt ## _I].dma_chan_i)
+
+typedef struct cyg_spi_freescale_dspi_bus_s
+{
+    // ---- Upper layer data ----
+    cyg_spi_bus       spi_bus;         // Upper layer SPI bus data.
+
+    // ---- Bus configuration constants ----
+    const cyg_spi_freescale_dspi_bus_setup_t* setup_p;
+    // ---- Driver state (private) ----
+    // DMA transfer control descriptors
+    const cyghwr_hal_freescale_edma_tcd_t* tx_dma_tcd_ini_p; // TCD init.
+    const cyghwr_hal_freescale_edma_tcd_t* rx_dma_tcd_ini_p; //     data
+    volatile cyghwr_hal_freescale_edma_tcd_t* rx_dma_tcd_p; // DMA TCD (RX)
+    volatile cyghwr_hal_freescale_edma_tcd_t* tx_dma_tcd_p; // DMA TCD (TX)
+    volatile cyg_uint32*   pushque_p;             // Tx command queue
+    cyg_uint16             pushque_n;             // Tx command buffer size
+    cyg_uint8              txfifo_n;              // TxFIFO size
+    cyg_uint8              rxfifo_n;              // RxFIFO size
+    cyg_interrupt          intr_data;       // Interrupt state
+    cyg_handle_t           intr_handle;     // Interrupt handle
+    cyg_drv_mutex_t        transfer_mutex;  // Transfer mutex.
+    cyg_drv_cond_t         transfer_done;   // Transfer condition variable.
+    cyg_uint32             clock_freq;      // Clock provided by hal
+} cyg_spi_freescale_dspi_bus_t;
+
+//-----------------------------------------------------------------------------
+// Freescale DSPI device.
+
+typedef struct cyg_freescale_dspi_clocking_s {
+    cyg_uint32 dspi_ctar;  // DSPI Clock and Transfer Attributes Rregister shadow.
+    cyg_uint32 cl_brate;   // Clock baud rate.
+    cyg_uint8  bus_16bit;  // Use 16 bit (1) or 8 bit (0) transfers.
+    cyg_uint8  cl_pol;     // Clock polarity (0 or 1).
+    cyg_uint8  cl_pha;     // Clock phase    (0 or 1).
+    cyg_uint8  cl_dbr;     // Use double baud-rate feature if needed
+    cyg_uint8  cs_up_udly; // Minimum delay in us/ns between CS up and transfer start.
+    cyg_uint8  cs_dw_udly; // Minimum delay in us/ns between transfer end and CS down.
+    cyg_uint8  tr_bt_udly; // Minimum delay in us/ns between two transfers.
+    cyg_uint8  dl_unit;    // Delay unit (1/10 * ns)
+    cyg_uint8  lsb_first;  // LSbit shifted first.
+    cyg_uint8  frame_size; // Device SPI frame size (bits).
+} cyg_freescale_dspi_clocking_t;;
+
+typedef struct cyg_spi_freescale_dspi_device_s
+{
+    // ---- Upper layer data ----
+    cyg_spi_device spi_device;  // Upper layer SPI device data.
+
+    // ---- Device setup (user configurable) ----
+    cyg_freescale_dspi_clocking_t clocking;
+    cyg_uint8  dev_num;   // Device SPI select.
+    cyg_uint8  chip_sel;
+    // ---- Device state (private) ----
+} cyg_spi_freescale_dspi_device_t;
+
+//-----------------------------------------------------------------------------
+// Exported bus data structures.
+
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI0
+externC cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus0;
+#endif
+
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI1
+externC cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus1;
+#endif
+
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI2
+externC cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus2;
+#endif
+
+__externC void cyghwr_devs_freescale_dspi_diag(cyg_spi_freescale_dspi_bus_t* spi_bus_p);
+__externC void cyghwr_devs_freescale_dspi_diag_array(char* name_p,
+                                                     volatile cyg_uint32* fifo_p,
+                                                     cyg_uint32 fifo_n);
+
+//=============================================================================
+#endif // CYGONCE_DEVS_SPI_FREESCALE_DSPI_H
diff --git a/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi_buses.inl b/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi_buses.inl
new file mode 100644
--- /dev/null
+++ b/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi_buses.inl
@@ -0,0 +1,586 @@
+#ifndef SPI_FREESCALE_DSPI_BUSES_INL
+#define SPI_FREESCALE_DSPI_BUSES_INL
+//=============================================================================
+//
+//      spi_freescale_dspi_buses.inl
+//
+//      SPI bus instantiation for Freescale DSPI
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-11-09
+// Purpose:     Freescale DSPI DSPI bus instantiation
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#define PUSHQUE_ALIGN CYGBLD_ATTRIB_ALIGN(4)
+
+#define DSPI_DMA_BANDWIDTH FREESCALE_EDMA_CSR_BWC_0
+
+//-----------------------------------------------------------------------------
+// Instantiate the bus state data structures.
+
+// Some auxiliary macros
+
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+#define EDMA_TCD_SADDR(__bus) \
+        .saddr = (void *)(((unsigned int)&CYGADDR_IO_SPI_FREESCALE_DSPI ## __bus ## _P->popr) + 3)
+#else // AKA Little endian
+#define EDMA_TCD_SADDR(__bus) \
+        .saddr = (cyg_uint32 *)&CYGADDR_IO_SPI_FREESCALE_DSPI ## __bus ## _P->popr
+#endif
+
+#define DSPI_EDMA_CHAN_SET(__bus) \
+static volatile cyg_uint32 \
+dspi ## __bus ## _pushque[CYGNUM_DEVS_SPI_FREESCALE_DSPI ## __bus ## _PUSHQUE_SIZE+4] \
+PUSHQUE_ALIGN EDMA_RAM_BUF_SECTION;                                                   \
+                                                                                      \
+static const cyghwr_hal_freescale_dma_chan_set_t dspi ## __bus ## _dma_chan[2] = \
+{                                                                                \
+    {                                                                            \
+        .dma_src = FREESCALE_DMAMUX_SRC_SPI ## __bus ## _TX                      \
+        | FREESCALE_DMAMUX_CHCFG_ENBL_M,                                         \
+        .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI ## __bus ## _TX_DMA_CHAN,   \
+        .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI ## __bus ## _TX_DMA_PRI,      \
+    },                                                                           \
+    {                                                                            \
+        .dma_src = FREESCALE_DMAMUX_SRC_SPI ## __bus ## _RX                      \
+        | FREESCALE_DMAMUX_CHCFG_ENBL_M,                                         \
+        .dma_chan_i = CYGHWR_DEVS_SPI_FREESCALE_DSPI ## __bus ## _RX_DMA_CHAN,   \
+        .dma_prio = CYGNUM_DEVS_SPI_FREESCALE_DSPI ## __bus ## _RX_DMA_PRI,      \
+    }                                                                            \
+};                                                                               \
+                                                                                 \
+static cyghwr_hal_freescale_dma_set_t dspi ## __bus ## _dma_set = {              \
+    .chan_p = dspi ## __bus ## _dma_chan,                                        \
+    .chan_n = 2                                                                  \
+};                                                                               \
+                                                                                 \
+static const cyghwr_hal_freescale_edma_tcd_t dspi ## __bus ## _dma_tcd_tx_ini =  \
+{                                                                                \
+        .saddr =  (cyg_uint32 *) dspi ## __bus ## _pushque,                      \
+        .soff = 4,                                                               \
+        .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |         \
+                FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |         \
+                FREESCALE_EDMA_ATTR_SMOD(0) |                                    \
+                FREESCALE_EDMA_ATTR_DMOD(0),                                     \
+        .daddr = (cyg_uint32 *)                                                  \
+                 &CYGADDR_IO_SPI_FREESCALE_DSPI ## __bus ## _P->pushr,           \
+        .doff = 0,                                                               \
+        .nbytes.mlno = 4,                                                        \
+        .slast = 0,                                                              \
+        .citer.elinkno = 1,                                                      \
+        .dlast_sga.dlast = 0,                                                    \
+        .biter.elinkno = 1,                                                      \
+        .csr = DSPI_DMA_BANDWIDTH                                                \
+};                                                                               \
+                                                                                 \
+static const cyghwr_hal_freescale_edma_tcd_t dspi ## __bus ## _dma_tcd_rx_ini =  \
+{                                                                                \
+       EDMA_TCD_SADDR(__bus),                                                    \
+        .soff = 0,                                                               \
+        .attr = FREESCALE_EDMA_ATTR_SSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |         \
+                FREESCALE_EDMA_ATTR_DSIZE(FREESCALE_EDMA_ATTR_SIZE_32) |         \
+                FREESCALE_EDMA_ATTR_SMOD(0) |                                    \
+                FREESCALE_EDMA_ATTR_DMOD(0),                                     \
+        .daddr = NULL,                                                           \
+        .doff = 4,                                                               \
+        .nbytes.mlno = 4,                                                        \
+        .slast = 0,                                                              \
+        .citer.elinkno = 1,                                                      \
+        .dlast_sga.dlast = 0,                                                    \
+        .biter.elinkno = 1,                                                      \
+        .csr = DSPI_DMA_BANDWIDTH                                                \
+}
+
+#define DSPI_EDMA_SET_P_YES(__bus)  .dma_set_p = &dspi ## __bus ## _dma_set
+#define DSPI_EDMA_SET_P_NULL(__bus)  .dma_set_p = NULL
+
+#define DSPI_EDMA_TCD_YES(__bus)                                      \
+    .tx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P->                    \
+        tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI ## __bus ## _TX_DMA_CHAN], \
+    .rx_dma_tcd_p = &CYGHWR_IO_FREESCALE_EDMA0_P->                    \
+    tcd[CYGHWR_DEVS_SPI_FREESCALE_DSPI ## __bus ## _RX_DMA_CHAN],     \
+    .tx_dma_tcd_ini_p = &dspi ## __bus ## _dma_tcd_tx_ini,            \
+    .rx_dma_tcd_ini_p = &dspi ## __bus ## _dma_tcd_rx_ini,            \
+    .pushque_p = dspi ## __bus ## _pushque
+
+#define DSPI_EDMA_TCD_NULL(__bus) \
+    .tx_dma_tcd_p = NULL,         \
+    .rx_dma_tcd_p = NULL,         \
+    .tx_dma_tcd_ini_p = NULL,     \
+    .rx_dma_tcd_ini_p = NULL,     \
+    .pushque_p = NULL
+
+// End DSPI_EDMA
+
+#define DSPI_BUS_SETUP(__bus) \
+static const cyg_spi_freescale_dspi_bus_setup_t dspi ## __bus ## _setup = {   \
+    .dspi_p          = CYGADDR_IO_SPI_FREESCALE_DSPI ## __bus ## _P,          \
+    .intr_num        = CYGNUM_HAL_INTERRUPT_SPI ## __bus,                     \
+    .intr_prio       = CYGNUM_DEVS_SPI_FREESCALE_DSPI ## __bus ## _ISR_PRI,   \
+    .spi_pin_list_p  = spi ## __bus ## _pins,                                 \
+    .cs_pin_list_p   = spi ## __bus ## _cs_pins,                              \
+    .clk_gate        = CYGHWR_IO_FREESCALE_DSPI ## __bus ## _CLK,             \
+    .cs_pin_num      = sizeof(spi ## __bus ## _cs_pins)/                      \
+                       sizeof(spi ## __bus ## _cs_pins[0]),                   \
+    .mcr_opt         = CYGHWR_FREESCALE_DSPI ## __bus ## _MCR_PCSSE |         \
+                       FREESCALE_DSPI_MCR_PCSIS(                              \
+                          CYGHWR_DEVS_SPI_FREESCALE_DSPI ## __bus ## _PCSIS), \
+    DSPI ## __bus ## _EDMA_SET_P                                              \
+}
+
+#define DSPI_BUS(__bus) \
+cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus ## __bus = {                 \
+    .spi_bus.spi_transaction_begin    = dspi_transaction_begin,            \
+    .spi_bus.spi_transaction_transfer = dspi_transaction_transfer,         \
+    .spi_bus.spi_transaction_tick     = dspi_transaction_tick,             \
+    .spi_bus.spi_transaction_end      = dspi_transaction_end,              \
+    .spi_bus.spi_get_config           = dspi_get_config,                   \
+    .spi_bus.spi_set_config           = dspi_set_config,                   \
+    .setup_p                          = &dspi ## __bus ## _setup,          \
+    DSPI ## __bus ## _EDMA_TCD,                                            \
+    .pushque_n = CYGNUM_DEVS_SPI_FREESCALE_DSPI ## __bus ## _PUSHQUE_SIZE, \
+    .txfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE,                  \
+    .rxfifo_n = CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE                   \
+}
+
+#define DSPI_BUS_PINS(__bus) \
+static const cyg_uint32 spi ## __bus ## _pins[] = { \
+    CYGHWR_IO_FREESCALE_SPI ## __bus ## _PIN_SIN,   \
+    CYGHWR_IO_FREESCALE_SPI ## __bus ## _PIN_SOUT,  \
+    CYGHWR_IO_FREESCALE_SPI ## __bus ## _PIN_SCK    \
+}
+
+// DSPI BUS Instances =======================================================
+
+// DSPI BUS 0 ================================================================
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI0
+
+#define  CYGBLD_DSPI0_TCD_SECTION \
+    CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI0_TCD_SECTION)
+
+#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI0_PCSS
+#define CYGHWR_FREESCALE_DSPI0_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
+#else
+#define CYGHWR_FREESCALE_DSPI0_MCR_PCSSE 0
+#endif
+
+// SPI chip select pins.
+static const cyg_uint32 spi0_cs_pins[] = {
+#ifdef CYGHWR_FREESCALE_DSPI0_CS0
+    CYGHWR_IO_FREESCALE_SPI0_PIN_CS0,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI0_CS1
+    CYGHWR_IO_FREESCALE_SPI0_PIN_CS1,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI0_CS2
+    CYGHWR_IO_FREESCALE_SPI0_PIN_CS2,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI0_CS3
+    CYGHWR_IO_FREESCALE_SPI0_PIN_CS3,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI0_CS4
+    CYGHWR_IO_FREESCALE_SPI0_PIN_CS4,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI0_CS5
+    CYGHWR_IO_FREESCALE_SPI0_PIN_CS5
+#endif
+};
+
+#ifdef CYGINT_DEVS_SPI_DSPI0_USES_DMA
+  DSPI_EDMA_CHAN_SET(0);
+# define DSPI0_EDMA_SET_P DSPI_EDMA_SET_P_YES(0)
+# define DSPI0_EDMA_TCD DSPI_EDMA_TCD_YES(0)
+#else
+# define DSPI0_EDMA_SET_P DSPI_EDMA_SET_P_NULL(0)
+# define DSPI0_EDMA_TCD DSPI_EDMA_TCD_NULL(0)
+#endif // CYGINT_DEVS_SPI_DSPI0_USES_DMA
+
+DSPI_BUS_PINS(0);
+DSPI_BUS_SETUP(0);
+DSPI_BUS(0);
+
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI0
+
+// DSPI BUS 1 ================================================================
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI1
+
+#define  CYGBLD_DSPI1_TCD_SECTION \
+    CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI1_TCD_SECTION)
+
+#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI1_PCSS
+#define CYGHWR_FREESCALE_DSPI1_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
+#else
+#define CYGHWR_FREESCALE_DSPI1_MCR_PCSSE 0
+#endif
+
+// SPI chip select pins.
+static const cyg_uint32 spi1_cs_pins[] = {
+#ifdef CYGHWR_FREESCALE_DSPI1_CS0
+    CYGHWR_IO_FREESCALE_SPI1_PIN_CS0,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI1_CS1
+    CYGHWR_IO_FREESCALE_SPI1_PIN_CS1,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI1_CS2
+    CYGHWR_IO_FREESCALE_SPI1_PIN_CS2,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI1_CS3
+    CYGHWR_IO_FREESCALE_SPI1_PIN_CS3,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI1_CS4
+    CYGHWR_IO_FREESCALE_SPI1_PIN_CS4,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI1_CS5
+    CYGHWR_IO_FREESCALE_SPI1_PIN_CS5
+#endif
+};
+
+#ifdef CYGINT_DEVS_SPI_DSPI1_USES_DMA
+  DSPI_EDMA_CHAN_SET(1);
+# define DSPI1_EDMA_SET_P DSPI_EDMA_SET_P_YES(1)
+# define DSPI1_EDMA_TCD DSPI_EDMA_TCD_YES(1)
+#else
+# define DSPI1_EDMA_SET_P DSPI_EDMA_SET_P_NULL(1)
+# define DSPI1_EDMA_TCD DSPI_EDMA_TCD_NULL(1)
+#endif // CYGINT_DEVS_SPI_DSPI1_USES_DMA
+
+DSPI_BUS_PINS(1);
+DSPI_BUS_SETUP(1);
+DSPI_BUS(1);
+
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI1
+
+// DSPI BUS 2 ================================================================
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI2
+
+#define  CYGBLD_DSPI2_TCD_SECTION \
+    CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI2_TCD_SECTION)
+
+#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI2_PCSS
+#define CYGHWR_FREESCALE_DSPI2_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
+#else
+#define CYGHWR_FREESCALE_DSPI2_MCR_PCSSE 0
+#endif
+
+// SPI chip select pins.
+static const cyg_uint32 spi2_cs_pins[] = {
+#ifdef CYGHWR_FREESCALE_DSPI2_CS0
+    CYGHWR_IO_FREESCALE_SPI2_PIN_CS0,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI2_CS1
+    CYGHWR_IO_FREESCALE_SPI2_PIN_CS1,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI2_CS2
+    CYGHWR_IO_FREESCALE_SPI2_PIN_CS2,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI2_CS3
+    CYGHWR_IO_FREESCALE_SPI2_PIN_CS3,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI2_CS4
+    CYGHWR_IO_FREESCALE_SPI2_PIN_CS4,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI2_CS5
+    CYGHWR_IO_FREESCALE_SPI2_PIN_CS5
+#endif
+};
+
+#ifdef CYGINT_DEVS_SPI_DSPI2_USES_DMA
+  DSPI_EDMA_CHAN_SET(2);
+# define DSPI2_EDMA_SET_P DSPI_EDMA_SET_P_YES(2)
+# define DSPI2_EDMA_TCD DSPI_EDMA_TCD_YES(2)
+#else
+# define DSPI2_EDMA_SET_P DSPI_EDMA_SET_P_NULL(2)
+# define DSPI2_EDMA_TCD DSPI_EDMA_TCD_NULL(2)
+#endif // CYGINT_DEVS_SPI_DSPI2_USES_DMA
+
+DSPI_BUS_PINS(2);
+DSPI_BUS_SETUP(2);
+DSPI_BUS(2);
+
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI2
+
+// DSPI BUS 3 ================================================================
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI3
+
+#define  CYGBLD_DSPI3_TCD_SECTION \
+    CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI3_TCD_SECTION)
+
+#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI3_PCSS
+#define CYGHWR_FREESCALE_DSPI3_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
+#else
+#define CYGHWR_FREESCALE_DSPI3_MCR_PCSSE 0
+#endif
+
+// SPI chip select pins.
+static const cyg_uint32 spi3_cs_pins[] = {
+#ifdef CYGHWR_FREESCALE_DSPI3_CS0
+    CYGHWR_IO_FREESCALE_SPI3_PIN_CS0,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI3_CS1
+    CYGHWR_IO_FREESCALE_SPI3_PIN_CS1,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI3_CS2
+    CYGHWR_IO_FREESCALE_SPI3_PIN_CS2,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI3_CS3
+    CYGHWR_IO_FREESCALE_SPI3_PIN_CS3,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI3_CS4
+    CYGHWR_IO_FREESCALE_SPI3_PIN_CS4,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI3_CS5
+    CYGHWR_IO_FREESCALE_SPI3_PIN_CS5
+#endif
+};
+
+#ifdef CYGINT_DEVS_SPI_DSPI3_USES_DMA
+  DSPI_EDMA_CHAN_SET(3);
+# define DSPI3_EDMA_SET_P DSPI_EDMA_SET_P_YES(3)
+# define DSPI3_EDMA_TCD DSPI_EDMA_TCD_YES(3)
+#else
+# define DSPI3_EDMA_SET_P DSPI_EDMA_SET_P_NULL(3)
+# define DSPI3_EDMA_TCD DSPI_EDMA_TCD_NULL(3)
+#endif // CYGINT_DEVS_SPI_DSPI3_USES_DMA
+
+DSPI_BUS_PINS(3);
+DSPI_BUS_SETUP(3);
+DSPI_BUS(3);
+
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI3
+
+// DSPI BUS 4 ================================================================
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI4
+
+#define  CYGBLD_DSPI4_TCD_SECTION \
+    CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI4_TCD_SECTION)
+
+#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI4_PCSS
+#define CYGHWR_FREESCALE_DSPI4_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
+#else
+#define CYGHWR_FREESCALE_DSPI4_MCR_PCSSE 0
+#endif
+
+// SPI chip select pins.
+static const cyg_uint32 spi4_cs_pins[] = {
+#ifdef CYGHWR_FREESCALE_DSPI4_CS0
+    CYGHWR_IO_FREESCALE_SPI4_PIN_CS0,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI4_CS1
+    CYGHWR_IO_FREESCALE_SPI4_PIN_CS1,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI4_CS2
+    CYGHWR_IO_FREESCALE_SPI4_PIN_CS2,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI4_CS3
+    CYGHWR_IO_FREESCALE_SPI4_PIN_CS3,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI4_CS4
+    CYGHWR_IO_FREESCALE_SPI4_PIN_CS4,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI4_CS5
+    CYGHWR_IO_FREESCALE_SPI4_PIN_CS5
+#endif
+};
+
+#ifdef CYGINT_DEVS_SPI_DSPI4_USES_DMA
+  DSPI_EDMA_CHAN_SET(4);
+# define DSPI4_EDMA_SET_P DSPI_EDMA_SET_P_YES(4)
+# define DSPI4_EDMA_TCD DSPI_EDMA_TCD_YES(4)
+#else
+# define DSPI4_EDMA_SET_P DSPI_EDMA_SET_P_NULL(4)
+# define DSPI4_EDMA_TCD DSPI_EDMA_TCD_NULL(4)
+#endif // CYGINT_DEVS_SPI_DSPI4_USES_DMA
+
+DSPI_BUS_PINS(4);
+DSPI_BUS_SETUP(4);
+DSPI_BUS(4);
+
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI4
+
+// DSPI BUS 5 ================================================================
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI5
+
+#define  CYGBLD_DSPI5_TCD_SECTION \
+    CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI5_TCD_SECTION)
+
+#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI5_PCSS
+#define CYGHWR_FREESCALE_DSPI5_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
+#else
+#define CYGHWR_FREESCALE_DSPI5_MCR_PCSSE 0
+#endif
+
+// SPI chip select pins.
+static const cyg_uint32 spi5_cs_pins[] = {
+#ifdef CYGHWR_FREESCALE_DSPI5_CS0
+    CYGHWR_IO_FREESCALE_SPI5_PIN_CS0,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI5_CS1
+    CYGHWR_IO_FREESCALE_SPI5_PIN_CS1,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI5_CS2
+    CYGHWR_IO_FREESCALE_SPI5_PIN_CS2,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI5_CS3
+    CYGHWR_IO_FREESCALE_SPI5_PIN_CS3,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI5_CS4
+    CYGHWR_IO_FREESCALE_SPI5_PIN_CS4,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI5_CS5
+    CYGHWR_IO_FREESCALE_SPI5_PIN_CS5
+#endif
+};
+
+#ifdef CYGINT_DEVS_SPI_DSPI5_USES_DMA
+  DSPI_EDMA_CHAN_SET(5);
+# define DSPI5_EDMA_SET_P DSPI_EDMA_SET_P_YES(5)
+# define DSPI5_EDMA_TCD DSPI_EDMA_TCD_YES(5)
+#else
+# define DSPI5_EDMA_SET_P DSPI_EDMA_SET_P_NULL(5)
+# define DSPI5_EDMA_TCD DSPI_EDMA_TCD_NULL(5)
+#endif // CYGINT_DEVS_SPI_DSPI5_USES_DMA
+
+DSPI_BUS_PINS(5);
+DSPI_BUS_SETUP(5);
+DSPI_BUS(5);
+
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI5
+
+// DSPI BUS 6 ================================================================
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI6
+
+#define  CYGBLD_DSPI6_TCD_SECTION \
+    CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI6_TCD_SECTION)
+
+#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI6_PCSS
+#define CYGHWR_FREESCALE_DSPI6_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
+#else
+#define CYGHWR_FREESCALE_DSPI6_MCR_PCSSE 0
+#endif
+
+// SPI chip select pins.
+static const cyg_uint32 spi6_cs_pins[] = {
+#ifdef CYGHWR_FREESCALE_DSPI6_CS0
+    CYGHWR_IO_FREESCALE_SPI6_PIN_CS0,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI6_CS1
+    CYGHWR_IO_FREESCALE_SPI6_PIN_CS1,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI6_CS2
+    CYGHWR_IO_FREESCALE_SPI6_PIN_CS2,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI6_CS3
+    CYGHWR_IO_FREESCALE_SPI6_PIN_CS3,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI6_CS4
+    CYGHWR_IO_FREESCALE_SPI6_PIN_CS4,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI6_CS5
+    CYGHWR_IO_FREESCALE_SPI6_PIN_CS5
+#endif
+};
+
+#ifdef CYGINT_DEVS_SPI_DSPI6_USES_DMA
+  DSPI_EDMA_CHAN_SET(6);
+# define DSPI6_EDMA_SET_P DSPI_EDMA_SET_P_YES(6)
+# define DSPI6_EDMA_TCD DSPI_EDMA_TCD_YES(6)
+#else
+# define DSPI6_EDMA_SET_P DSPI_EDMA_SET_P_NULL(6)
+# define DSPI6_EDMA_TCD DSPI_EDMA_TCD_NULL(6)
+#endif // CYGINT_DEVS_SPI_DSPI6_USES_DMA
+
+DSPI_BUS_PINS(6);
+DSPI_BUS_SETUP(6);
+DSPI_BUS(6);
+
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI6
+
+// DSPI BUS 7 ================================================================
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI7
+
+#define  CYGBLD_DSPI7_TCD_SECTION \
+    CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI7_TCD_SECTION)
+
+#ifdef CYHGWR_DEVS_SPI_FREESCALE_DSPI7_PCSS
+#define CYGHWR_FREESCALE_DSPI7_MCR_PCSSE FREESCALE_DSPI_MCR_PCSSE_M
+#else
+#define CYGHWR_FREESCALE_DSPI7_MCR_PCSSE 0
+#endif
+
+// SPI chip select pins.
+static const cyg_uint32 spi7_cs_pins[] = {
+#ifdef CYGHWR_FREESCALE_DSPI7_CS0
+    CYGHWR_IO_FREESCALE_SPI7_PIN_CS0,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI7_CS1
+    CYGHWR_IO_FREESCALE_SPI7_PIN_CS1,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI7_CS2
+    CYGHWR_IO_FREESCALE_SPI7_PIN_CS2,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI7_CS3
+    CYGHWR_IO_FREESCALE_SPI7_PIN_CS3,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI7_CS4
+    CYGHWR_IO_FREESCALE_SPI7_PIN_CS4,
+#endif
+#ifdef CYGHWR_FREESCALE_DSPI7_CS5
+    CYGHWR_IO_FREESCALE_SPI7_PIN_CS5
+#endif
+};
+
+#ifdef CYGINT_DEVS_SPI_DSPI7_USES_DMA
+  DSPI_EDMA_CHAN_SET(7);
+# define DSPI7_EDMA_SET_P DSPI_EDMA_SET_P_YES(7)
+# define DSPI7_EDMA_TCD DSPI_EDMA_TCD_YES(7)
+#else
+# define DSPI7_EDMA_SET_P DSPI_EDMA_SET_P_NULL(7)
+# define DSPI7_EDMA_TCD DSPI_EDMA_TCD_NULL(7)
+#endif // CYGINT_DEVS_SPI_DSPI7_USES_DMA
+
+DSPI_BUS_PINS(7);
+DSPI_BUS_SETUP(7);
+DSPI_BUS(7);
+
+#endif // CYGHWR_DEVS_SPI_FREESCALE_DSPI7
+
+//=============================================================================
+#endif // SPI_FREESCALE_DSPI_BUSES_INL
diff --git a/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi_io.h b/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi_io.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi_io.h
@@ -0,0 +1,292 @@
+#ifndef CYGONCE_DEVS_SPI_FREESCALE_DSPI_IO_H
+#define CYGONCE_DEVS_SPI_FREESCALE_DSPI_IO_H
+//=============================================================================
+//
+//      spi_freescale_dspi_io.h
+//
+//      IO definitions for Freescale DSPI.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-11-03
+// Purpose:     Freescale DSPI I/O definitions.
+// Description:
+// Usage:       #include <cyg/io/spi_freescale_dspi_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+
+// ----------------------------------------------------------------------------
+// DSPI
+
+typedef volatile struct cyghwr_devs_freescale_dspi_s {
+    cyg_uint32 mcr;    // Module Configuration Register
+    cyg_uint32 reserved_0;
+    cyg_uint32 tcr;    // Transfer Count Register
+     // Clock and Transfer Attributes Register
+    cyg_uint32 ctar[CYGHWR_DEVS_SPI_FREESCALE_DSPI_CTAR_NUM];
+#if CYGHWR_DEVS_SPI_FREESCALE_DSPI_CTAR_NUM < 8
+    cyg_uint32 reserved_1[8-CYGHWR_DEVS_SPI_FREESCALE_DSPI_CTAR_NUM];
+#endif
+    cyg_uint32 sr;     // Status Register
+    cyg_uint32 rser;   // DMA/IRQ Request Select and Enable Register
+    cyg_uint32 pushr;  // TX FIFO PUSH Register
+    cyg_uint32 popr;   // RX FIFO POP Register
+     // Transmit FIFO Registers
+    cyg_uint32 txfr[CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE];
+#if CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE < 16
+    cyg_uint32 reserved_2[16-CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE];
+#endif
+    // Receive FIFO Registers
+    cyg_uint32 rxfr[CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE];
+#if CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE < 16
+    cyg_uint32 reserved_3[16-CYGHWR_DEVS_SPI_FREESCALE_DSPI_FIFO_SIZE];
+#endif
+} cyghwr_devs_freescale_dspi_t;
+
+// MCR Bit Fields
+#define FREESCALE_DSPI_MCR_HALT_M                       0x1
+#define FREESCALE_DSPI_MCR_HALT_S                       0
+#define FREESCALE_DSPI_MCR_SMPL_PT_M                    0x300
+#define FREESCALE_DSPI_MCR_SMPL_PT_S                    8
+#define FREESCALE_DSPI_MCR_SMPL_PT(__val)               \
+        VALUE_(FREESCALE_DSPI_MCR_SMPL_PT_S, __val)
+#define FREESCALE_DSPI_MCR_CLR_RXF_M                    0x400
+#define FREESCALE_DSPI_MCR_CLR_RXF_S                    10
+#define FREESCALE_DSPI_MCR_CLR_TXF_M                    0x800
+#define FREESCALE_DSPI_MCR_CLR_TXF_S                    11
+#define FREESCALE_DSPI_MCR_DIS_RXF_M                    0x1000
+#define FREESCALE_DSPI_MCR_DIS_RXF_S                    12
+#define FREESCALE_DSPI_MCR_DIS_TXF_M                    0x2000
+#define FREESCALE_DSPI_MCR_DIS_TXF_S                    13
+#define FREESCALE_DSPI_MCR_MDIS_M                       0x4000
+#define FREESCALE_DSPI_MCR_MDIS_S                       14
+#define FREESCALE_DSPI_MCR_DOZE_M                       0x8000
+#define FREESCALE_DSPI_MCR_DOZE_S                       15
+#define FREESCALE_DSPI_MCR_PCSIS_M                      0x3F0000
+#define FREESCALE_DSPI_MCR_PCSIS_S                      16
+#define FREESCALE_DSPI_MCR_PCSIS(__val)                 \
+        VALUE_(FREESCALE_DSPI_MCR_PCSIS_S, __val)
+#define FREESCALE_DSPI_MCR_ROOE_M                       0x1000000
+#define FREESCALE_DSPI_MCR_ROOE_S                       24
+#define FREESCALE_DSPI_MCR_PCSSE_M                      0x2000000
+#define FREESCALE_DSPI_MCR_PCSSE_S                      25
+#define FREESCALE_DSPI_MCR_MTFE_M                       0x4000000
+#define FREESCALE_DSPI_MCR_MTFE_S                       26
+#define FREESCALE_DSPI_MCR_FRZ_M                        0x8000000
+#define FREESCALE_DSPI_MCR_FRZ_S                        27
+#define FREESCALE_DSPI_MCR_DCONF_M                      0x30000000
+#define FREESCALE_DSPI_MCR_DCONF_S                      28
+#define FREESCALE_DSPI_MCR_DCONF(__val)                 \
+        VALUE_(FREESCALE_DSPI_MCR_DCONF_S, __val)
+#define FREESCALE_DSPI_MCR_CONT_SCKE_M                  0x40000000
+#define FREESCALE_DSPI_MCR_CONT_SCKE_S                  30
+#define FREESCALE_DSPI_MCR_MSTR_M                       0x80000000
+#define FREESCALE_DSPI_MCR_MSTR_S                       31
+// TCR Bit Fields
+#define FREESCALE_DSPI_TCR_DSPI_TCNT_M                  0xFFFF0000
+#define FREESCALE_DSPI_TCR_DSPI_TCNT_S                  16
+#define FREESCALE_DSPI_TCR_DSPI_TCNT(__val)             \
+        VALUE_(FREESCALE_DSPI_TCR_DSPI_TCNT_S, __val)
+// CTAR Bit Fields
+#define FREESCALE_DSPI_CTAR_BR_M                        0xF
+#define FREESCALE_DSPI_CTAR_BR_S                        0
+#define FREESCALE_DSPI_CTAR_BR(__val)                   \
+        VALUE_(FREESCALE_DSPI_CTAR_BR_S, __val)
+#define FREESCALE_DSPI_CTAR_DT_M                        0xF0
+#define FREESCALE_DSPI_CTAR_DT_S                        4
+#define FREESCALE_DSPI_CTAR_DT(__val)                   \
+        VALUE_(FREESCALE_DSPI_CTAR_DT_S, __val)
+#define FREESCALE_DSPI_CTAR_ASC_M                       0xF00
+#define FREESCALE_DSPI_CTAR_ASC_S                       8
+#define FREESCALE_DSPI_CTAR_ASC(__val)                  \
+        VALUE_(FREESCALE_DSPI_CTAR_ASC_S, __val)
+#define FREESCALE_DSPI_CTAR_CSSCK_M                     0xF000
+#define FREESCALE_DSPI_CTAR_CSSCK_S                     12
+#define FREESCALE_DSPI_CTAR_CSSCK(__val)                \
+        VALUE_(FREESCALE_DSPI_CTAR_CSSCK_S, __val)
+#define FREESCALE_DSPI_CTAR_PBR_M                       0x30000
+#define FREESCALE_DSPI_CTAR_PBR_S                       16
+#define FREESCALE_DSPI_CTAR_PBR(__val)                  \
+        VALUE_(FREESCALE_DSPI_CTAR_PBR_S, __val)
+#define FREESCALE_DSPI_CTAR_PDT_M                       0xC0000
+#define FREESCALE_DSPI_CTAR_PDT_S                       18
+#define FREESCALE_DSPI_CTAR_PDT(__val)                  \
+        VALUE_(FREESCALE_DSPI_CTAR_PDT_S, __val)
+#define FREESCALE_DSPI_CTAR_PASC_M                      0x300000
+#define FREESCALE_DSPI_CTAR_PASC_S                      20
+#define FREESCALE_DSPI_CTAR_PASC(__val)                 \
+        VALUE_(FREESCALE_DSPI_CTAR_PASC_S, __val)
+#define FREESCALE_DSPI_CTAR_PCSSCK_S                    22
+#define FREESCALE_DSPI_CTAR_PCSSCK(__val)               \
+        VALUE_(FREESCALE_DSPI_CTAR_PCSSCK_S, __val)
+#define FREESCALE_DSPI_CTAR_LSBFE_S                     24
+#define FREESCALE_DSPI_CTAR_LSBFE_M                     0x1000000
+
+#define FREESCALE_DSPI_CTAR_FMSZ_M                      0x78000000
+#define FREESCALE_DSPI_CTAR_FMSZ_S                      27
+#define FREESCALE_DSPI_CTAR_FMSZ(__val)                 \
+        VALUE_(FREESCALE_DSPI_CTAR_FMSZ_S, __val)
+#define FREESCALE_DSPI_CTAR_DBR_M                       0x80000000
+#define FREESCALE_DSPI_CTAR_DBR_S                       31
+// CTAR_SLAVE Bit Fields
+#define FREESCALE_DSPI_CTAR_SLAVE_CPHA_M                0x2000000
+#define FREESCALE_DSPI_CTAR_SLAVE_CPHA_S                25
+#define FREESCALE_DSPI_CTAR_SLAVE_CPOL_M                0x4000000
+#define FREESCALE_DSPI_CTAR_SLAVE_CPOL_S                26
+#define FREESCALE_DSPI_CTAR_SLAVE_FMSZ_M                0xF8000000
+#define FREESCALE_DSPI_CTAR_SLAVE_FMSZ_S                27
+#define FREESCALE_DSPI_CTAR_SLAVE_FMSZ(__val)           \
+        VALUE_(FREESCALE_DSPI_CTAR_SLAVE_FMSZ_S, __val)
+// SR Bit Fields
+#define FREESCALE_DSPI_SR_POPNXTPTR_M                   0xF
+#define FREESCALE_DSPI_SR_POPNXTPTR_S                   0
+#define FREESCALE_DSPI_SR_POPNXTPTR(__val)              \
+        VALUE_(FREESCALE_DSPI_SR_POPNXTPTR_S, __val)
+#define FREESCALE_DSPI_SR_RXCTR_M                       0xF0
+#define FREESCALE_DSPI_SR_RXCTR_S                       4
+#define FREESCALE_DSPI_SR_RXCTR(__val)                  \
+        VALUE_(FREESCALE_DSPI_SR_RXCTR_S, __val)
+#define FREESCALE_DSPI_SR_TXNXTPTR_M                    0xF00
+#define FREESCALE_DSPI_SR_TXNXTPTR_S                    8
+#define FREESCALE_DSPI_SR_TXNXTPTR(__val)               \
+        VALUE_(FREESCALE_DSPI_SR_TXNXTPTR_S, __val)
+#define FREESCALE_DSPI_SR_TXCTR_M                       0xF000
+#define FREESCALE_DSPI_SR_TXCTR_S                       12
+#define FREESCALE_DSPI_SR_TXCTR(__val)                  \
+        VALUE_(FREESCALE_DSPI_SR_TXCTR_S, __val)
+#define FREESCALE_DSPI_SR_RFDF_M                        0x20000
+#define FREESCALE_DSPI_SR_RFDF_S                        17
+#define FREESCALE_DSPI_SR_RFOF_M                        0x80000
+#define FREESCALE_DSPI_SR_RFOF_S                        19
+#define FREESCALE_DSPI_SR_TFFF_M                        0x2000000
+#define FREESCALE_DSPI_SR_TFFF_S                        25
+#define FREESCALE_DSPI_SR_TFUF_M                        0x8000000
+#define FREESCALE_DSPI_SR_TFUF_S                        27
+#define FREESCALE_DSPI_SR_EOQF_M                        0x10000000
+#define FREESCALE_DSPI_SR_EOQF_S                        28
+#define FREESCALE_DSPI_SR_TXRXS_M                       0x40000000
+#define FREESCALE_DSPI_SR_TXRXS_S                       30
+#define FREESCALE_DSPI_SR_TCF_M                         0x80000000
+#define FREESCALE_DSPI_SR_TCF_S                         31
+
+#define FREESCALE_DSPI_CLEAR_FIFOS (FREESCALE_DSPI_SR_TFUF_M |\
+                                    FREESCALE_DSPI_SR_RFOF_M)
+
+// RSER Bit Fields
+#define FREESCALE_DSPI_RSER_RFDF_DIRS_M                 0x10000
+#define FREESCALE_DSPI_RSER_RFDF_DIRS_S                 16
+#define FREESCALE_DSPI_RSER_RFDF_RE_M                   0x20000
+#define FREESCALE_DSPI_RSER_RFDF_RE_S                   17
+#define FREESCALE_DSPI_RSER_RFOF_RE_M                   0x80000
+#define FREESCALE_DSPI_RSER_RFOF_RE_S                   19
+#define FREESCALE_DSPI_RSER_TFFF_DIRS_M                 0x1000000
+#define FREESCALE_DSPI_RSER_TFFF_DIRS_S                 24
+#define FREESCALE_DSPI_RSER_TFFF_RE_M                   0x2000000
+#define FREESCALE_DSPI_RSER_TFFF_RE_S                   25
+#define FREESCALE_DSPI_RSER_TFUF_RE_M                   0x8000000
+#define FREESCALE_DSPI_RSER_TFUF_RE_S                   27
+#define FREESCALE_DSPI_RSER_EOQF_RE_M                   0x10000000
+#define FREESCALE_DSPI_RSER_EOQF_RE_S                   28
+#define FREESCALE_DSPI_RSER_TCF_RE_M                    0x80000000
+#define FREESCALE_DSPI_RSER_TCF_RE_S                    31
+// PUSHR Bit Fields
+#define FREESCALE_DSPI_PUSHR_TXDATA_M                   0xFFFF
+#define FREESCALE_DSPI_PUSHR_TXDATA_S                   0
+#define FREESCALE_DSPI_PUSHR_TXDATA(__val)              \
+        VALUE_(FREESCALE_DSPI_PUSHR_TXDATA_S, __val)
+#define FREESCALE_DSPI_PUSHR_PCS_M                      0x3F0000
+#define FREESCALE_DSPI_PUSHR_PCS_S                      16
+#define FREESCALE_DSPI_PUSHR_PCS(__val)                 VALUE_(FREESCALE_DSPI_PUSHR_PCS_S, __val)
+#define FREESCALE_DSPI_PUSHR_CTCNT_M                    0x4000000
+#define FREESCALE_DSPI_PUSHR_CTCNT_S                    26
+#define FREESCALE_DSPI_PUSHR_EOQ_M                      0x8000000
+#define FREESCALE_DSPI_PUSHR_EOQ_S                      27
+#define FREESCALE_DSPI_PUSHR_CTAS_M                     0x70000000
+#define FREESCALE_DSPI_PUSHR_CTAS_S                     28
+#define FREESCALE_DSPI_PUSHR_CTAS(__val)                \
+        VALUE_(FREESCALE_DSPI_PUSHR_CTAS_S, __val)
+#define FREESCALE_DSPI_PUSHR_CONT_M                     0x80000000
+#define FREESCALE_DSPI_PUSHR_CONT_S                     31
+// PUSHR_SLAVE Bit Fields
+#define FREESCALE_DSPI_PUSHR_SLAVE_TXDATA_M             0xFFFFFFFF
+#define FREESCALE_DSPI_PUSHR_SLAVE_TXDATA_S             0
+#define FREESCALE_DSPI_PUSHR_SLAVE_TXDATA(__val)        \
+VALUE_(FREESCALE_DSPI_PUSHR_SLAVE_TXDATA_S, __val)
+
+#define FREESCALE_DSPI_PUSHR_PCS_CLEAR(__val)\
+CYG_MACRO_START\
+    __val &= ~FREESCALE_DSPI_PUSHR_PCS_M; \
+CYG_MACRO_END
+
+// POPR Bit Fields
+#define FREESCALE_DSPI_POPR_RXDATA_M                    0xFFFFFFFF
+#define FREESCALE_DSPI_POPR_RXDATA_S                    0
+#define FREESCALE_DSPI_POPR_RXDATA(__val)               \
+        VALUE_(FREESCALE_DSPI_POPR_RXDATA_S, __val)
+// TXFR Bit Fields
+#define FREESCALE_DSPI_TXFR_TXDATA_M                    0xFFFF
+#define FREESCALE_DSPI_TXFR_TXDATA_S                    0
+#define FREESCALE_DSPI_TXFR_TXCMD_TXDATA_M              0xFFFF0000
+#define FREESCALE_DSPI_TXFR_TXCMD_TXDATA_S              16
+#define FREESCALE_DSPI_TXFR_TXCMD_TXDATA(__fr,__val)    \
+        VALUE_(FREESCALE_DSPI_TXFR##__fr##_TXCMD_TXDATA_S, __val)
+// RXFR Bit Fields
+#define FREESCALE_DSPI_RXFR_RXDATA_M                    0xFFFFFFFF
+#define FREESCALE_DSPI_RXFR_RXDATA_S                    0
+#define FREESCALE_DSPI_RXFR_RXDATA(__fr,__val)          \
+        VALUE_(FREESCALE_DSPI_RXFR##_fr##_RXDATA_S, __val)
+
+// Borrow following macros from HAL
+
+// CYGADDR_IO_SPI_FREESCALE_DSPIx_P
+
+// CYGHWR_IO_CLOCK_ENABLE(__clkgate)
+// CYGHWR_IO_FREESCALE_DSPIx_CLK
+
+// CYGHWR_IO_FREESCALE_DSPI_PIN(__pin)
+
+// CYGHWR_IO_FREESCALE_SPIx_PIN_SIN
+// CYGHWR_IO_FREESCALE_SPIx_PIN_SOUT
+// CYGHWR_IO_FREESCALE_SPIx_PIN_SCK
+
+// CYGHWR_IO_FREESCALE_SPIx_PIN_CSn
+
+//=============================================================================
+#endif // CYGONCE_DEVS_SPI_FREESCALE_DSPI_IO_H
diff --git a/packages/devs/spi/freescale/dspi/current/src/spi_freescale_dspi.c b/packages/devs/spi/freescale/dspi/current/src/spi_freescale_dspi.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/spi/freescale/dspi/current/src/spi_freescale_dspi.c
@@ -0,0 +1,1190 @@
+//=============================================================================
+//
+//      spi_freescale_dspi.c
+//
+//      SPI driver implementation for Freescale DSPI
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-11-04
+// Purpose:     Freescale DSPI SPI driver implementation
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <string.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/hal/hal_cache.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/diag.h>
+
+#include <cyg/io/spi.h>
+#include <cyg/hal/hal_endian.h>
+
+#include <pkgconf/devs_spi_freescale_dspi.h>
+#if defined(CYGHWR_DEVS_SPI_FREESCALE_DSPI0) || \
+    defined(CYGHWR_DEVS_SPI_FREESCALE_DSPI1) || \
+    defined(CYGHWR_DEVS_SPI_FREESCALE_DSPI2)
+
+#include <cyg/io/spi_freescale_dspi.h>
+
+
+#define DEBUG_SPI CYGPKG_DEVS_SPI_FREESCALE_DSPI_DEBUG_LEVEL
+
+#if DEBUG_SPI >= 3
+# define DEBUG3_PRINTF(args...) diag_printf(args)
+#else
+# define DEBUG3_PRINTF(args...)
+#endif
+
+#if DEBUG_SPI >= 2
+# define DEBUG2_PRINTF(args...) diag_printf(args)
+#else
+# define DEBUG2_PRINTF(args...)
+#endif
+
+#if DEBUG_SPI >= 1
+# define DEBUG1_PRINTF(args...) diag_printf(args)
+#else
+# define DEBUG1_PRINTF(args...)
+#endif
+
+# define DEBUG0_PRINTF(args...) diag_printf(args)
+
+#define PUSHR_NULL (0xFFFF)
+
+//-----------------------------------------------------------------------------
+// API function call forward references.
+
+static void dspi_transaction_begin    (cyg_spi_device*);
+static void dspi_transaction_transfer (cyg_spi_device*, cyg_bool, cyg_uint32,
+                                       const cyg_uint8*, cyg_uint8*, cyg_bool);
+static void dspi_transaction_tick     (cyg_spi_device*, cyg_bool, cyg_uint32);
+static void dspi_transaction_end      (cyg_spi_device*);
+static int  dspi_get_config           (cyg_spi_device*, cyg_uint32,
+                                       void*, cyg_uint32*);
+static int  dspi_set_config           (cyg_spi_device*, cyg_uint32,
+                                       const void*, cyg_uint32*);
+
+//-----------------------------------------------------------------------------
+// Instantiate the bus state data structures.
+
+#include <cyg/io/spi_freescale_dspi_buses.inl>
+
+// Some hardware manipulation inline functions and macros
+
+static inline void dspi_disable(cyghwr_devs_freescale_dspi_t* dspi_p)
+{
+    dspi_p->mcr |=  FREESCALE_DSPI_MCR_MDIS_M;
+}
+
+static inline void dspi_enable(cyghwr_devs_freescale_dspi_t* dspi_p)
+{
+    dspi_p->mcr &=  ~FREESCALE_DSPI_MCR_MDIS_M;
+}
+
+static inline void dspi_halt(cyghwr_devs_freescale_dspi_t* dspi_p)
+{
+    dspi_p->mcr |=  FREESCALE_DSPI_MCR_HALT_M;
+}
+
+static inline void dspi_tlah(cyghwr_devs_freescale_dspi_t* dspi_p)
+{
+    dspi_p->mcr &=  ~FREESCALE_DSPI_MCR_HALT_M;
+}
+
+static inline void
+dspi_irq_enable(cyghwr_devs_freescale_dspi_t* dspi_p, cyg_uint32 irq_mask)
+{
+    dspi_p->rser |= irq_mask;
+}
+
+static inline void
+dspi_irq_disable(cyghwr_devs_freescale_dspi_t* dspi_p, cyg_uint32 irq_mask)
+{
+    dspi_p->rser &= ~irq_mask;
+}
+
+static inline void
+dspi_status_clear(cyghwr_devs_freescale_dspi_t* dspi_p, cyg_uint32 sr_mask)
+{
+    dspi_p->sr |= sr_mask;
+}
+
+static inline void
+dspi_fifo_clear(cyghwr_devs_freescale_dspi_t* dspi_p)
+{
+    dspi_p->mcr |= FREESCALE_DSPI_MCR_CLR_RXF_M | FREESCALE_DSPI_MCR_CLR_TXF_M;
+}
+
+static inline void
+dspi_fifo_drain(cyghwr_devs_freescale_dspi_t* dspi_p)
+{
+    dspi_p->sr |= FREESCALE_DSPI_SR_RFDF_M;
+}
+
+
+#define DSPI_IRQ_ENABLE(__dspi_p) \
+        dspi_irq_enable(__dspi_p, FREESCALE_DSPI_RSER_EOQF_RE_M)
+#define DSPI_IRQ_DISABLE(__dspi_p) \
+        dspi_irq_disable(__dspi_p, FREESCALE_DSPI_RSER_EOQF_RE_M)
+#define DSPI_EOQ_CLEAR(__dspi_p) \
+        dspi_status_clear(__dspi_p, FREESCALE_DSPI_SR_EOQF_M | \
+                                     FREESCALE_DSPI_SR_TCF_M | \
+                                        FREESCALE_DSPI_SR_RFDF_M)
+#define DSPI_TXRX_ENABLE(__dspi_p) \
+        dspi_status_clear(__dspi_p, FREESCALE_DSPI_SR_TXRXS_M)
+
+// Alternate clocking for spi_transaction_end()
+// Used to initialize CTAR1.
+static const cyg_freescale_dspi_clocking_t aux_clocking =
+{
+    .frame_size = 4,
+    .cl_pol = 0,
+    .cl_pha = 0,
+    .cl_brate = CYGHWR_DEVS_FREESCALEDSPI_DSPI_CTAR1_AUX_SPEED,
+    .cs_up_udly = CYGHWR_DEVS_FREESCALEDSPI_DSPI_CTAR1_AUX_CS_DELAY,
+    .cs_dw_udly = CYGHWR_DEVS_FREESCALEDSPI_DSPI_CTAR1_AUX_CS_DELAY,
+    .tr_bt_udly =CYGHWR_DEVS_FREESCALEDSPI_DSPI_CTAR1_AUX_CS_DELAY,
+    .dl_unit = CYGNUM_DSPI_DELAY_UNIT(
+                   CYGHWR_DEVS_FREESCALE_DSPI_DSPI_CTAR1_AUX_DELAY_UNIT),
+    .cl_dbr = CYGHWR_DEVS_FREESCALEDSPI_DSPI_CTAR1_AUX_USE_DBR
+};
+
+//-----------------------------------------------------------------------------
+// Implement DSPI ISRs.
+
+// ISR for DSPI with DMA
+// Disable DSPI IRQ and Tx DMA channel and schedule DSR.
+static cyg_uint32 dspi_dma_ISR(cyg_vector_t vector, cyg_addrword_t data)
+{
+    cyg_spi_freescale_dspi_bus_t* dspi_bus_p =
+          (cyg_spi_freescale_dspi_bus_t*) data;
+    cyghwr_devs_freescale_dspi_t* dspi_p = dspi_bus_p->setup_p->dspi_p;
+    cyghwr_hal_freescale_dma_set_t *dma_set_p = dspi_bus_p->setup_p->dma_set_p;
+    cyghwr_hal_freescale_edma_t *edma_p;
+    edma_p = dma_set_p->edma_p;
+
+    cyg_drv_isr_lock();
+
+    // Disable the Tx DMA channel and DSPI IRQ.
+    hal_freescale_edma_erq_disable(edma_p, SPI_DMA_CHAN_I(dma_set_p, TX));
+    DSPI_IRQ_DISABLE(dspi_p);
+
+    cyg_drv_interrupt_acknowledge(vector);
+    cyg_drv_isr_unlock();
+    return (CYG_ISR_CALL_DSR | CYG_ISR_HANDLED);
+}
+
+// ISR for DSPI without DMA
+// Disable DSPI IRQ and schedule DSR.
+static cyg_uint32 dspi_nodma_ISR(cyg_vector_t vector, cyg_addrword_t data)
+{
+    cyg_spi_freescale_dspi_bus_t* dspi_bus_p =
+          (cyg_spi_freescale_dspi_bus_t*) data;
+    cyghwr_devs_freescale_dspi_t* dspi_p = dspi_bus_p->setup_p->dspi_p;
+
+    cyg_drv_isr_lock();
+
+    // Disable the DSPI IRQ.
+    DSPI_IRQ_DISABLE(dspi_p);
+
+    cyg_drv_interrupt_acknowledge(vector);
+    cyg_drv_isr_unlock();
+    return (CYG_ISR_CALL_DSR | CYG_ISR_HANDLED);
+}
+
+// DSPI DSR
+static void dspi_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
+{
+    cyg_spi_freescale_dspi_bus_t* dspi_bus = (cyg_spi_freescale_dspi_bus_t*) data;
+
+    cyg_drv_dsr_lock();
+    cyg_drv_cond_signal(&dspi_bus->transfer_done);
+    cyg_drv_dsr_unlock();
+}
+
+//-----------------------------------------------------------------------------
+// Calculate best fit CTAR baud rate setting (using some brute force).
+// Best fit is considered the highest frequency that is not highe than set point.
+
+static const cyg_uint16 ctar_br[16] = { 2/2, 4/2, 6/2, 8/2, 16/2, 32/2, 64/2,
+    128/2, 256/2, 512/2, 1024/2, 2048/2, 4096/2, 8192/2, 16384/2, 32768/2 };
+static const cyg_uint8 ctar_pbr[4] = { 2, 3, 5, 7 };
+
+static const cyg_uint16 ctar_cssck[16] = { 2/2, 4/2, 8/2, 16/2, 32/2, 64/2,
+    128/2, 256/2, 512/2, 1024/2, 2048/2, 4096/2, 8192/2, 16384/2, 32768/2,
+    65536/2 };
+static const cyg_uint8 ctar_pcssck[4] = { 1, 3, 5, 7 };
+
+typedef struct ctar_br_s {
+    cyg_uint8 valid;
+    cyg_uint8 br;
+    cyg_uint8 dbr;
+    cyg_uint8 pbr;
+} ctar_br_t;
+
+static int dspi_ctar_brbf (const cyg_freescale_dspi_clocking_t* spi_cocking,
+                              ctar_br_t* brs_p, const cyg_uint16* br_p,
+                              const cyg_uint8* pbr_p, cyg_uint32* alt_brate,
+                              cyg_uint32 sys_clk)
+{
+    cyg_uint32 pbr_i;
+    cyg_uint32 br_i;
+    cyg_uint32 dbr;
+    cyg_uint32 clk;
+    cyg_uint32 baud_bf = 0; // Best fit
+    cyg_uint32 baud_tmp;
+    cyg_uint32 baud_sp = alt_brate ? *alt_brate :
+                         spi_cocking->cl_brate; // Set point
+
+    // Calculate the maximal viable bus speed.
+    clk = sys_clk;
+     // Desired baud rate very high, use DBR if allowed
+    dbr = (baud_sp > (clk / 4)) && spi_cocking->cl_dbr && (br_p == ctar_br);
+
+    for(pbr_i = 0; pbr_i < 3; pbr_i++) {
+        for(br_i = 0; br_i < 15; br_i++) {
+            if((baud_tmp = (clk * (1+dbr)) / (pbr_p[pbr_i] * (2*br_p[br_i])))
+               <= baud_sp)
+            {
+                if(baud_tmp > baud_bf) {
+                    DEBUG3_PRINTF("DSPI Baud:"
+                                  " SP=%d pbr=0x%x br=0x%x dbr=%d Temp=%d (SysClk=%d)\n",
+                                  baud_sp, pbr_i, br_i, dbr, baud_tmp, clk);
+                    brs_p->br = br_i;
+                    brs_p->pbr = pbr_i;
+                    brs_p->valid = 1;
+                    baud_bf = baud_tmp;
+                    if(baud_tmp == baud_sp)
+                        goto baud_found;
+                }
+            }
+        }
+    }
+    if(!brs_p->valid) {
+        pbr_i = 3;
+        br_i = 15;
+        DEBUG1_PRINTF("DSPI Baud too low:"
+                      " SP=%d pbr=0x%x br=0x%x Actual=%d (SysClk=%d)\n",
+                      baud_sp, pbr_i, br_i,
+                      (clk * (1+dbr)) / (pbr_p[pbr_i] * (2*br_p[br_i])), clk);
+        brs_p->br = br_i;
+        brs_p->pbr = pbr_i;
+
+        return -1;
+    } else {
+baud_found:
+        brs_p->dbr = dbr;
+        DEBUG1_PRINTF("DSPI Baud found:"
+                      " SP=%d pbr=0x%x br=0x%x dbr=%d Actual=%dHz (%dns) (SysClk=%d)\n",
+                      baud_sp, brs_p->pbr, brs_p->br, dbr, baud_bf, 1000000000/baud_bf, clk);
+
+        return 0;
+    }
+}
+
+// Set Clock and Transfer Attributes Register
+#define CYG_ASSERT_LOW_FREQ \
+   CYG_ASSERT (false, "Freescale DSPI: Cannot run bus as slowly as requested.")
+cyg_uint32
+dspi_calc_ctar(const cyg_freescale_dspi_clocking_t* spi_clocking, cyg_uint32 sys_clk)
+{
+    cyg_uint32 regval;
+    ctar_br_t brs;
+    cyg_uint32 delay_brate;
+
+    regval = FREESCALE_DSPI_CTAR_FMSZ(spi_clocking->frame_size - 1);
+    if(spi_clocking->cl_pol)
+        regval |= FREESCALE_DSPI_CTAR_SLAVE_CPOL_M;
+    if(spi_clocking->cl_pha)
+        regval |= FREESCALE_DSPI_CTAR_SLAVE_CPHA_M;
+    if(spi_clocking->lsb_first)
+        regval |= FREESCALE_DSPI_CTAR_LSBFE_M;
+
+    // Get divider bits
+    // Baud rate
+    brs.dbr = 0;
+    if (!dspi_ctar_brbf(spi_clocking, &brs, ctar_br, ctar_pbr, NULL, sys_clk))
+    {
+        regval |= FREESCALE_DSPI_CTAR_BR(brs.br) |
+              FREESCALE_DSPI_CTAR_PBR(brs.pbr) |
+              (brs.dbr ? FREESCALE_DSPI_CTAR_DBR_M : 0);
+    } else
+        CYG_ASSERT_LOW_FREQ;
+
+    delay_brate = 100000000 / (spi_clocking->dl_unit * spi_clocking->cs_up_udly);
+    if (!dspi_ctar_brbf(spi_clocking, &brs, ctar_cssck, ctar_pcssck,
+                           &delay_brate, sys_clk))
+    {
+        regval |= FREESCALE_DSPI_CTAR_CSSCK(brs.br) |
+              FREESCALE_DSPI_CTAR_PCSSCK(brs.pbr);
+    } else
+        CYG_ASSERT_LOW_FREQ;
+
+    // Delay between clock and CS negation
+    delay_brate = 100000000 / (spi_clocking->dl_unit * spi_clocking->cs_dw_udly);
+    if (!dspi_ctar_brbf(spi_clocking, &brs, ctar_cssck, ctar_pcssck,
+                           &delay_brate, sys_clk))
+    {
+        regval |= FREESCALE_DSPI_CTAR_ASC(brs.br) |
+              FREESCALE_DSPI_CTAR_PASC(brs.pbr);
+    } else
+        CYG_ASSERT_LOW_FREQ;
+
+    // Delay between clock and CS negation and assertion
+    delay_brate = 100000000 / (spi_clocking->dl_unit * spi_clocking->tr_bt_udly);
+    if (!dspi_ctar_brbf(spi_clocking, &brs, ctar_cssck, ctar_pcssck,
+                           &delay_brate, sys_clk))
+    {
+        regval |= FREESCALE_DSPI_CTAR_DT(brs.br) |
+              FREESCALE_DSPI_CTAR_PDT(brs.pbr);
+    } else
+        CYG_ASSERT_LOW_FREQ;
+    return regval;
+}
+
+//----------------------------------------------------------------------------
+//Set up SPI bus pins
+
+static void dspi_pin_setup(const cyg_uint32* spi_pins_p,
+                           const cyg_uint32* cs_pins_p, cyg_uint32 cs_pin_n)
+{
+    const cyg_uint32* pin_p;
+
+    for(pin_p = spi_pins_p;
+        pin_p < spi_pins_p + 3;
+        CYGHWR_IO_FREESCALE_DSPI_PIN(*pin_p++));
+
+    for(pin_p = cs_pins_p;
+        pin_p < cs_pins_p + cs_pin_n;
+        CYGHWR_IO_FREESCALE_DSPI_PIN(*pin_p++));
+}
+
+//-----------------------------------------------------------------------------
+// Set up a new SPI bus on initialisation.
+
+static void dspi_bus_setup(cyg_spi_freescale_dspi_bus_t* spi_bus_p)
+{
+    cyghwr_devs_freescale_dspi_t* dspi_p = spi_bus_p->setup_p->dspi_p;
+    cyghwr_hal_freescale_dma_set_t* dma_set_p;
+    cyghwr_hal_freescale_edma_t* edma_p;
+    cyg_uint32 dma_chan_i;
+
+    // Set up the clocking.
+    CYGHWR_IO_CLOCK_ENABLE(spi_bus_p->setup_p->clk_gate);
+    spi_bus_p->clock_freq = CYGHWR_IO_SPI_FREESCALE_DSPI_CLOCK;
+    DEBUG1_PRINTF("DSPI BUS %p: SysClk=%d\n", spi_bus_p, spi_bus_p->clock_freq);
+
+    // Set up the pins.
+    dspi_pin_setup(spi_bus_p->setup_p->spi_pin_list_p,
+                   spi_bus_p->setup_p->cs_pin_list_p,
+                   spi_bus_p->setup_p->cs_pin_num);
+
+    // Set up default SPI configuration.
+    dspi_p->mcr = spi_bus_p->setup_p->mcr_opt | FREESCALE_DSPI_MCR_MSTR_M |
+          FREESCALE_DSPI_MCR_CLR_RXF_M | FREESCALE_DSPI_MCR_CLR_TXF_M |
+          FREESCALE_DSPI_MCR_MDIS_M;
+
+    // Enable DSPI controller.
+    dspi_enable(dspi_p);
+
+    if((dma_set_p=spi_bus_p->setup_p->dma_set_p)) {
+        // Initialize DMA channels
+        hal_freescale_edma_init_chanset(dma_set_p);
+#if DEBUG_SPI >= 1
+        hal_freescale_edma_diag(dma_set_p, 0xffff);
+        cyghwr_devs_freescale_dspi_diag(spi_bus_p);
+#endif
+        // Set up DMA transfer control descriptors
+        edma_p = dma_set_p->edma_p;
+        dma_chan_i = dma_set_p->chan_p[SPI_DMA_CHAN_TX_I].dma_chan_i;
+        hal_freescale_edma_transfer_init(edma_p, dma_chan_i,
+                                         spi_bus_p->tx_dma_tcd_ini_p);
+#if DEBUG_SPI >= 1
+        hal_freescale_edma_transfer_diag(edma_p, dma_chan_i, true);
+#endif
+        dma_chan_i = dma_set_p->chan_p[SPI_DMA_CHAN_RX_I].dma_chan_i;
+        hal_freescale_edma_transfer_init(edma_p, dma_chan_i,
+                                         spi_bus_p->rx_dma_tcd_ini_p);
+#if DEBUG_SPI >= 1
+        hal_freescale_edma_transfer_diag(edma_p, dma_chan_i, true);
+#endif
+    }
+#if DEBUG_SPI >= 1
+    cyghwr_devs_freescale_dspi_diag(spi_bus_p);
+#endif
+    // Initialise the synchronisation primitivies.
+    cyg_drv_mutex_init (&spi_bus_p->transfer_mutex);
+    cyg_drv_cond_init (&spi_bus_p->transfer_done, &spi_bus_p->transfer_mutex);
+
+    // Hook up the ISR and DSR.
+    cyg_drv_interrupt_create (spi_bus_p->setup_p->intr_num,
+                              spi_bus_p->setup_p->intr_prio,
+                              (cyg_addrword_t) spi_bus_p,
+                              dma_set_p ? dspi_dma_ISR : dspi_nodma_ISR,
+                              dspi_DSR, &spi_bus_p->intr_handle,
+                              &spi_bus_p->intr_data);
+    cyg_drv_interrupt_attach (spi_bus_p->intr_handle);
+
+    dspi_p->ctar[1] = dspi_calc_ctar(&aux_clocking, spi_bus_p->clock_freq);
+
+    // Call upper layer bus init.
+    CYG_SPI_BUS_COMMON_INIT(&spi_bus_p->spi_bus);
+}
+
+//-----------------------------------------------------------------------------
+// Set up Rx DMA channel
+static void
+rx_dma_channel_setup(cyghwr_hal_freescale_dma_set_t *dma_set_p,
+                     cyg_uint8* data_buf, cyg_uint32 bus_16bit,
+                     volatile cyghwr_hal_freescale_edma_tcd_t *tcd_p)
+{
+    cyg_uint32 step, sdsize;
+    static cyg_uint8 popr_sink;
+
+    // Set the correct transfer size.
+    if(bus_16bit) {
+        step = 2;
+        sdsize = FREESCALE_EDMA_ATTR_SIZE_16;
+    } else {
+        step = 1;
+        sdsize = FREESCALE_EDMA_ATTR_SIZE_8;
+    }
+    if(data_buf) {
+        tcd_p->doff = step;
+        tcd_p->daddr = data_buf;
+    } else {
+        tcd_p->doff = 0;
+        tcd_p->daddr = &popr_sink;
+    }
+    tcd_p->nbytes.mlno = step;
+    tcd_p->attr =  FREESCALE_EDMA_ATTR_SSIZE(sdsize) |
+          FREESCALE_EDMA_ATTR_DSIZE(sdsize) |
+          FREESCALE_EDMA_ATTR_SMOD(0) |
+          FREESCALE_EDMA_ATTR_DMOD(0);
+#if DEBUG_SPI >= 3
+    hal_freescale_edma_tcd_diag(tcd_p, -1, "[DSPI Rx]");
+#endif
+}
+
+//----------------------------------------------------------------------------
+// Set up Tx FIFO queue
+// Set up Tx FIFO command queue
+//     DSPI requires sending command for every transfer.
+// Used for transfers that fit within DSPI FIFO.
+
+#if DEBUG_SPI >= 2
+static const char debug_format[] = "BUFF %dbit %s: %p 0x%08x remain %d:\n";
+static const char debug_format1[] = "PUSHR 0x%08x %s: %p 0x%08x remain %d:\n";
+#endif
+
+static inline volatile cyg_uint32
+fifo_pushque_fill(cyg_spi_freescale_dspi_bus_t* dspi_bus, cyg_uint8*
+                  data_p, cyg_uint32 count, cyg_bool bus_16bit, cyg_uint32 pushr,
+                  cyg_bool drop_cs)
+{
+    cyghwr_devs_freescale_dspi_t* dspi_p = dspi_bus->setup_p->dspi_p;
+    cyg_uint32 txfifo_n = dspi_bus->txfifo_n;
+
+    if(data_p) {
+        if(!bus_16bit) {
+            for(; count > 1; count--) {
+                if(!(--txfifo_n)) {
+                    dspi_p->pushr = pushr |= *data_p | FREESCALE_DSPI_PUSHR_EOQ_M;
+                    count--;
+                    DEBUG2_PRINTF(debug_format, 8, "FBK", data_p,
+                                  pushr | *data_p, count);
+                    return count;
+                }
+                DEBUG3_PRINTF(debug_format, 8, "FAD", data_p,
+                              pushr | *data_p, count-1);
+                dspi_p->pushr = pushr | *data_p++;
+            }
+            pushr |= *data_p;
+        } else {
+            cyg_uint16* data16_p = (cyg_uint16 *)data_p;
+            cyg_uint16 data_word;
+
+            for(; count > 2; count-=2) {
+                if(!(--txfifo_n)) {
+                    dspi_p->pushr = pushr |= *data16_p | FREESCALE_DSPI_PUSHR_EOQ_M;
+                    count-=2;
+                    DEBUG2_PRINTF(debug_format, 16, "FBK", data_p,
+                                  pushr, count);
+                    return count;
+                }
+                DEBUG3_PRINTF(debug_format, 16, "FAD", data16_p,
+                              pushr | *data16_p, (count-1)*2);
+                data_word = *data16_p++;
+                dspi_p->pushr = pushr | data_word;
+            }
+            data_word = *data16_p;
+            pushr |= data_word;
+        }
+    } else {
+        pushr |= PUSHR_NULL;
+        for(; count > 1; count--) {
+            if(!(--txfifo_n)) {
+                dspi_p->pushr = pushr |= FREESCALE_DSPI_PUSHR_EOQ_M;
+                count--;
+                DEBUG2_PRINTF(debug_format, 0, "FBK", &dspi_p->pushr,
+                              pushr, count);
+                return count;
+            }
+            dspi_p->pushr = pushr;
+            DEBUG3_PRINTF(debug_format, 0, "FAD", &dspi_p->pushr, pushr,
+                          count-1);
+        }
+    }
+    if(drop_cs)
+        pushr &= ~FREESCALE_DSPI_PUSHR_CONT_M;
+    dspi_p->pushr = pushr |= FREESCALE_DSPI_PUSHR_EOQ_M;
+    DEBUG2_PRINTF(data_p ? debug_format : debug_format1, data_p ? (bus_16bit ? 16 :8) : pushr,
+                  (drop_cs ? "FEN" : "FSG"), data_p /*&dspi_p->pushr*/, pushr, 0);
+    return 0;
+}
+
+//----------------------------------------------------------------------------
+// Set up Tx
+// Set up Tx DMA command queue
+//     DSPI requires sending command for every transfer.
+// Used for transfers larger than DSPI FIFO
+
+static inline volatile cyg_uint32
+dma_pushque_fill(cyg_spi_freescale_dspi_bus_t* dspi_bus, cyg_uint8* data_p,
+                 cyg_uint32 count, cyg_bool bus_16bit, cyg_uint32 pushr,
+                 cyg_bool drop_cs)
+{
+    volatile cyg_uint32* pushque_p;
+    volatile cyg_uint32* pushque_end;
+
+    pushque_p = dspi_bus->pushque_p;
+    pushque_end = pushque_p + (dspi_bus->pushque_n - (bus_16bit ? 2 : 1));
+    pushque_p = dspi_bus->pushque_p;
+    if(data_p) {
+        if(!bus_16bit) {
+            do {
+                if(pushque_p == pushque_end) {
+                    *pushque_p = pushr | *data_p | FREESCALE_DSPI_PUSHR_EOQ_M;
+                    count--;
+
+                    DEBUG2_PRINTF(debug_format, 8, "BRK", pushque_p,
+                                  pushque_p[0], count);
+                    return count;
+                }
+                *pushque_p++ = pushr | *data_p++;
+                DEBUG3_PRINTF(debug_format, 8, "ADD", pushque_p-1,
+                              pushque_p[-1], count-1);
+            } while(--count > 1);
+            pushr |= *data_p;
+        } else {
+            cyg_uint16* data16_p = (cyg_uint16 *)data_p;
+            cyg_uint16 data_word;
+            do {
+                if(pushque_p == pushque_end) {
+                    data_word = *data16_p;
+                    *pushque_p = pushr | data_word | FREESCALE_DSPI_PUSHR_EOQ_M;
+                    count-=2;
+
+                    DEBUG2_PRINTF(debug_format, 16, "BRK", pushque_p,
+                                  pushque_p[0], count);
+                    return count;
+                }
+                data_word = *data16_p++;
+                *pushque_p++ = pushr | data_word;
+                DEBUG3_PRINTF(debug_format, 16, "ADD", pushque_p-1,
+                              pushque_p[-1], count-2);
+            } while((count -= 2) > 2);
+            data_word = *data16_p;
+            pushr |= data_word;
+        }
+    } else {
+        pushr |= PUSHR_NULL;
+        do {
+            if(pushque_p == pushque_end) {
+                *pushque_p = pushr | FREESCALE_DSPI_PUSHR_EOQ_M;
+                count--;
+
+                DEBUG2_PRINTF(debug_format, 0, "BRK", pushque_p,
+                              pushque_p[0], count);
+                return count;
+            }
+            *pushque_p++ = pushr;
+            DEBUG3_PRINTF(debug_format, 0, "ADD", pushque_p-1, pushque_p[-1],
+                          count-1);
+        } while(--count > 1);
+    }
+    if(drop_cs) pushr &= ~FREESCALE_DSPI_PUSHR_CONT_M;
+    *pushque_p = pushr |= FREESCALE_DSPI_PUSHR_EOQ_M;
+    DEBUG2_PRINTF(debug_format, data_p ? (bus_16bit ? 16 :8) : 0,
+                  (drop_cs ? "END" : "SGM"), pushque_p, pushque_p[0], 0);
+
+    return 0;
+}
+
+// Set up Tx DMA channel
+// Used for transfers larger than DSPI FIFO
+
+static inline cyg_uint32
+tx_dma_channel_setup(cyg_spi_freescale_dspi_bus_t* dspi_bus,
+                     cyg_uint8* data_buf, cyg_uint32 count,
+                     cyg_bool bus_16bit,
+                     cyg_uint32 pushr, cyg_bool drop_cs)
+{
+    cyghwr_hal_freescale_dma_set_t *dma_set_p = dspi_bus->setup_p->dma_set_p;
+    cyghwr_hal_freescale_edma_t *edma_p =  dma_set_p->edma_p;
+    volatile cyghwr_hal_freescale_edma_tcd_t *tcd_p;
+    cyg_uint32 remain=0;
+    cyg_uint32 dma_chan_i;
+
+    remain = dma_pushque_fill(dspi_bus, data_buf, count, bus_16bit, pushr, drop_cs);
+    dma_chan_i = SPI_DMA_CHAN_I(dma_set_p, TX);
+    tcd_p = &edma_p->tcd[dma_chan_i];
+    tcd_p->saddr = dspi_bus->pushque_p;
+    DEBUG2_PRINTF("DSPI: Tx channel setup\n");
+#if DEBUG_SPI >= 3
+    hal_freescale_edma_transfer_diag(edma_p, dma_chan_i, true);
+#endif
+    return remain;
+}
+
+//-----------------------------------------------------------------------------
+// Set SPI peripheral chip select.
+
+static inline cyg_uint32
+dspi_chip_select_set(cyg_int32 cs_i, cyg_bool pccse, cyg_bool assert)
+{
+    cyg_uint32 spi_pushr;
+
+    if(cs_i < 0) {
+        spi_pushr = 0;
+    } else {
+        if(pccse) {
+            spi_pushr = cs_i;
+        } else {
+            if(cs_i < 5) {
+                if(assert) {
+                    cs_i = 1 << cs_i;
+                    spi_pushr = FREESCALE_DSPI_PUSHR_PCS(cs_i);
+                } else
+                    spi_pushr = 0;
+            } else {
+                CYG_ASSERT(1, "DSPI: Peripheral Chip Select out of range.\n");
+                spi_pushr = 1 << 5;
+            }
+        }
+    }
+    return spi_pushr;
+}
+
+//-----------------------------------------------------------------------------
+// Execute SPI transaction.
+
+static void spi_transaction_do (cyg_spi_device* device, cyg_bool tick_only,
+                                 cyg_bool polled, cyg_uint32 count,
+                                 const cyg_uint8* tx_data, cyg_uint8* rx_data,
+                                 cyg_bool drop_cs)
+{
+    cyg_spi_freescale_dspi_bus_t* dspi_bus =
+          (cyg_spi_freescale_dspi_bus_t*) device->spi_bus;
+    cyg_spi_freescale_dspi_device_t* dspi_device =
+          (cyg_spi_freescale_dspi_device_t*) device;
+    cyg_bool bus_16bit = dspi_device->clocking.bus_16bit;
+    cyghwr_devs_freescale_dspi_t* dspi_p = dspi_bus->setup_p->dspi_p;
+
+    cyghwr_hal_freescale_dma_set_t* dma_set_p;
+    cyghwr_hal_freescale_edma_t* edma_p = NULL;
+
+    cyg_uint32 count_down;
+    cyg_uint32 txfifo_n = dspi_bus->txfifo_n;
+    cyg_uint32 pushr;
+    cyg_uint32 pushque_n;
+    cyg_uint32 dma_chan_rx_i = 0;
+    cyg_uint32 dma_chan_tx_i = 0;
+    cyg_uint8* rx_data0;
+
+#if DEBUG_SPI >= 2
+    cyg_uint32 first_turn = 1;
+#endif
+
+    DEBUG2_PRINTF("DSPI: transaction: count=%d drop_cs=%d tick_only=%d\n",
+                  count, drop_cs, tick_only);
+
+    // Set up peripheral CS field. DSPI automatically asserts and deasserts CS
+    pushr =
+#ifndef CYGOPT_DEVS_SPI_FREESCALE_DSPI_TICK_ONLY_DROPS_CS
+          // Compatibility option
+          // eCos Reference Manual states that CS should drop prior to sending
+          // ticks, but other SPI drivers do not touch the CS.
+          tick_only ? dspi_p->pushr & 0x87FF0000 :
+#endif
+          dspi_chip_select_set(
+#ifdef CYGOPT_DEVS_SPI_FREESCALE_DSPI_TICK_ONLY_DROPS_CS
+                               // Compatibility option. See comment above.
+                                 tick_only ? -1 :
+#endif
+                                 dspi_device->dev_num,
+                                 dspi_p->mcr & FREESCALE_DSPI_MCR_PCSSE_M, true);
+    pushr |= FREESCALE_DSPI_PUSHR_CONT_M;
+
+    dspi_fifo_clear(dspi_p);
+
+    pushque_n = dspi_bus->pushque_n;
+    if(bus_16bit)
+        txfifo_n *= 2;
+
+    dma_set_p = dspi_bus->setup_p->dma_set_p;
+    if((count > txfifo_n) && dma_set_p) {
+        rx_data0 = rx_data;
+        edma_p = dma_set_p->edma_p;
+        // Set up the DMA channels.
+        dma_chan_rx_i = SPI_DMA_CHAN_I(dma_set_p, RX);
+        dma_chan_tx_i = SPI_DMA_CHAN_I(dma_set_p, TX);
+        rx_dma_channel_setup(dma_set_p, (cyg_uint8*) rx_data,
+                             bus_16bit, &edma_p->tcd[dma_chan_rx_i]);
+        hal_freescale_edma_erq_enable(edma_p, dma_chan_rx_i);
+        dspi_irq_enable(dspi_p,
+                        FREESCALE_DSPI_RSER_TFFF_RE_M   |
+                        FREESCALE_DSPI_RSER_RFDF_RE_M   |
+                        FREESCALE_DSPI_RSER_TFFF_DIRS_M |
+                        FREESCALE_DSPI_RSER_RFDF_DIRS_M);
+    } else {
+        rx_data0 = NULL;
+        // If byte count fits in the FIFO don't bother with DMA.
+        if(dma_set_p) {
+            edma_p = dma_set_p->edma_p;
+            hal_freescale_edma_erq_disable(edma_p, SPI_DMA_CHAN_I(dma_set_p, RX));
+        }
+        dma_set_p = NULL;
+        dspi_irq_disable(dspi_p,
+                         FREESCALE_DSPI_RSER_TFFF_RE_M   |
+                         FREESCALE_DSPI_RSER_RFDF_RE_M   |
+                         FREESCALE_DSPI_RSER_TFFF_DIRS_M |
+                         FREESCALE_DSPI_RSER_RFDF_DIRS_M);
+    }
+
+    if(!polled)
+        cyg_drv_interrupt_unmask(dspi_bus->setup_p->intr_num);
+    count_down = count;
+    while(count_down) {
+#if DEBUG_SPI >= 2
+        if(first_turn) {
+            if(dspi_bus->pushque_p)
+                dspi_bus->pushque_p[0] |= FREESCALE_DSPI_PUSHR_CTCNT_M;
+            first_turn = 0;
+        }
+#endif
+        if(dma_set_p && (count_down > txfifo_n)) {
+            // Transfer size is larger than DSPI FIFO
+            // Use DMA Tx
+            count_down = tx_dma_channel_setup(dspi_bus, (cyg_uint8*) tx_data,
+                                              count_down, bus_16bit,
+                                              pushr, drop_cs);
+#if DEBUG_SPI >= 3
+            hal_freescale_edma_transfer_diag(edma_p, dma_chan_rx_i, true);
+#endif
+            // Enable the Tx DMA / SPI controller.
+            hal_freescale_edma_erq_enable(edma_p, dma_chan_tx_i);
+            DSPI_EOQ_CLEAR(dspi_p);
+        } else {
+            // Transfer size fits within DSPI FIFO
+            // No need for DMA Tx
+            DSPI_EOQ_CLEAR(dspi_p);
+            count_down = fifo_pushque_fill(dspi_bus, (cyg_uint8*) tx_data,
+                                           count_down, bus_16bit,
+                                           pushr, drop_cs);
+#if DEBUG_SPI >= 3
+            cyghwr_devs_freescale_dspi_diag(dspi_bus);
+#endif
+        }
+
+        if(polled) {
+            DEBUG2_PRINTF("DSPI Polled:\n");
+            // Busy-wait for DSPI/DMA (polling for completion).
+            while(!(dspi_p->sr & FREESCALE_DSPI_SR_EOQF_M));
+
+            if(dma_set_p) {
+                // Disable the Tx DMA channel on completion.
+                hal_freescale_edma_erq_disable(edma_p, dma_chan_tx_i);
+            }
+        } else {
+            // Wait for DSPI/DMA completion. (interrupt driven).
+            cyg_drv_mutex_lock(&dspi_bus->transfer_mutex);
+            cyg_drv_dsr_lock();
+
+            DSPI_IRQ_ENABLE(dspi_p);
+            DEBUG2_PRINTF("DSPI IRQ: Enabled\n");
+
+            // Sit back and wait for the ISR/DSRs to signal completion.
+            cyg_drv_cond_wait (&dspi_bus->transfer_done);
+
+            cyg_drv_dsr_unlock();
+            cyg_drv_mutex_unlock(&dspi_bus->transfer_mutex);
+        }
+
+        if(dma_set_p) {
+            // Make sure that Rx has been drained by DMA.
+            while((dspi_p->sr & FREESCALE_DSPI_SR_RFDF_M));
+            DEBUG2_PRINTF("Fifo Drained by DMA 0x%08x\n", dspi_p->sr);
+            if(count_down <= txfifo_n && count_down > 0) {
+                hal_freescale_edma_erq_disable(edma_p, dma_chan_rx_i);
+                dma_set_p = NULL;
+            }
+        } else {
+            // No DMA - "manually" drain Rx FIFO
+            DEBUG2_PRINTF("DSPI FIFO: 'Manually' drain Rx fifo rx_data=%p bus_16bit=%d\n",
+                          rx_data, bus_16bit);
+#if DEBUG_SPI >= 3
+            cyghwr_devs_freescale_dspi_diag(dspi_bus);
+#endif
+            if(rx_data) {
+                if(bus_16bit) {
+                    cyg_uint16* rx_data16 = (cyg_uint16*) rx_data;
+                    while(dspi_p->sr & FREESCALE_DSPI_SR_RXCTR_M) {
+                        DEBUG2_PRINTF("  Fifo Pull16 at %p\n", rx_data16);
+                        *rx_data16++ = dspi_p->popr;
+                    }
+                    rx_data = (cyg_uint8*) rx_data16;
+                } else {
+                    while(dspi_p->sr & FREESCALE_DSPI_SR_RXCTR_M) {
+                        DEBUG2_PRINTF("  Fifo Pull at %p\n", rx_data);
+                        *rx_data++ = dspi_p->popr;
+                    }
+                }
+            }
+            dspi_fifo_drain(dspi_p);
+        }
+        dspi_fifo_clear(dspi_p);
+        // Prepare for next iteration
+        if(tx_data) {
+            tx_data += pushque_n;
+            if(bus_16bit)
+                tx_data += pushque_n;
+        }
+    }
+    if(rx_data0) {
+        // Rx buffer may be out of sync with cache.
+        DEBUG2_PRINTF("DSPI DMA: Flush cache %p len=%d\n", rx_data0, count);
+        HAL_DCACHE_INVALIDATE(rx_data0, count);
+        DEBUG2_PRINTF("DSPI DMA: Cache flushed\n");
+    }
+
+    if(!polled)
+        cyg_drv_interrupt_mask(dspi_bus->setup_p->intr_num);
+
+    dspi_device->chip_sel = !drop_cs;
+    DEBUG2_PRINTF("cyg_transaction_do() chip_sel = %d drop_cs = %d\n", dspi_device->chip_sel, drop_cs);
+}
+
+//-----------------------------------------------------------------------------
+// Initialise SPI interfaces on startup.
+
+static void CYGBLD_ATTRIB_C_INIT_PRI(CYG_INIT_BUS_SPI)
+dspi_spi_init(void)
+{
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI0
+  dspi_bus_setup (&cyg_spi_dspi_bus0);
+#endif
+
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI1
+  dspi_bus_setup (&cyg_spi_dspi_bus1);
+#endif
+
+#ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI2
+  dspi_bus_setup (&cyg_spi_dspi_bus2);
+#endif
+}
+
+
+//-----------------------------------------------------------------------------
+// Start a SPI transaction.
+
+static void dspi_transaction_begin(cyg_spi_device* device)
+{
+    cyg_spi_freescale_dspi_bus_t* dspi_bus =
+          (cyg_spi_freescale_dspi_bus_t*) device->spi_bus;
+    cyg_spi_freescale_dspi_device_t* dspi_device =
+          (cyg_spi_freescale_dspi_device_t*) device;
+
+    // On the first transaction, generate the values to be programmed into the
+    // SPI configuration registers for this device and cache them. This avoids
+    // having to recalculate the prescaler for every transaction.
+    if(!(dspi_device->clocking.dspi_ctar))
+        dspi_device->clocking.dspi_ctar = dspi_calc_ctar(&dspi_device->clocking,
+                                                dspi_bus->clock_freq);
+    // Set up the SPI controller.
+    dspi_bus->setup_p->dspi_p->ctar[0] = dspi_device->clocking.dspi_ctar;
+#if DEBUG_SPI >= 2
+    cyghwr_devs_freescale_dspi_diag(dspi_bus);
+#endif
+}
+
+//-----------------------------------------------------------------------------
+// Run a transaction transfer.
+
+static void dspi_transaction_transfer(cyg_spi_device* device, cyg_bool polled,
+                                      cyg_uint32 count,
+                                      const cyg_uint8* tx_data,
+                                      cyg_uint8* rx_data,
+                                      cyg_bool drop_cs)
+{
+    cyg_spi_freescale_dspi_device_t* dspi_device =
+          (cyg_spi_freescale_dspi_device_t*) device;
+
+    DEBUG2_PRINTF("Transaction rx_data = %p tx_data = %p count=%d\n", rx_data, tx_data, count);
+
+    // Check for unsupported transactions.
+    CYG_ASSERT (count > 0, "DSPI: Null transfer requested.");
+
+    // We check that the buffers are half-word aligned and that count is a
+    // multiple of two in order to carry out the 16-bit transfer.
+    if (dspi_device->clocking.bus_16bit) {
+        CYG_ASSERT (!(count & 1) && !((cyg_uint32) tx_data & 1) &&
+                    !((cyg_uint32) rx_data & 1),
+                    "DSPI: Misaligned data in 16-bit transfer.");
+    }
+    spi_transaction_do (device, false, polled, count, tx_data, rx_data, drop_cs);
+}
+
+//-----------------------------------------------------------------------------
+// Carry out a bus tick operation - this drops chip select then pushes the
+// required number of NULL frames onto the bus.
+
+static void dspi_transaction_tick(cyg_spi_device* device, cyg_bool polled,
+                                  cyg_uint32 count)
+{
+    cyg_spi_freescale_dspi_device_t* dspi_device =
+          (cyg_spi_freescale_dspi_device_t*) device;
+
+    // Check for unsupported transactions.
+    CYG_ASSERT (count > 0, "DSPI: Null transfer requested.");
+
+    // We check that count is a multiple of two in order
+    // to carry out the 16-bit transfer.
+    if (dspi_device->clocking.bus_16bit) {
+        CYG_ASSERT (!(count & 1),
+                    "DSPI: Misaligned data in 16-bit transfer.");
+    }
+
+    // Perform null transfer
+    DEBUG2_PRINTF("cyg_transaction_tick()\n");
+    spi_transaction_do (device, true, polled, count, NULL, NULL, false);
+}
+
+//-----------------------------------------------------------------------------
+// Terminate a SPI transaction, disabling the SPI controller.
+
+static void dspi_transaction_end(cyg_spi_device* device)
+{
+    cyg_spi_freescale_dspi_bus_t* dspi_bus =
+          (cyg_spi_freescale_dspi_bus_t*) device->spi_bus;
+    cyg_spi_freescale_dspi_device_t* dspi_device =
+          (cyg_spi_freescale_dspi_device_t*) device;
+
+    const cyghwr_hal_freescale_dma_set_t *dma_set_p = dspi_bus->setup_p->dma_set_p;
+    cyghwr_hal_freescale_edma_t *edma_p;
+    cyghwr_devs_freescale_dspi_t* dspi_p = dspi_bus->setup_p->dspi_p;
+
+    DEBUG2_PRINTF("cyg_transaction_end() chip_sel = %d\n", dspi_device->chip_sel);
+    if(dma_set_p) {
+        edma_p = dma_set_p->edma_p;
+        hal_freescale_edma_erq_disable(edma_p, SPI_DMA_CHAN_I(dma_set_p, TX));
+        hal_freescale_edma_erq_disable(edma_p, SPI_DMA_CHAN_I(dma_set_p, RX));
+    }
+
+    if(dspi_device->chip_sel){
+        // Clear peripheral CS by executing a dummy 4 bit transfer.
+        dspi_p->pushr = PUSHR_NULL | FREESCALE_DSPI_PUSHR_EOQ_M |
+                        FREESCALE_DSPI_PUSHR_CTAS(1);
+        while(!(dspi_p->sr & FREESCALE_DSPI_SR_EOQF_M));
+        DSPI_EOQ_CLEAR(dspi_p);
+        dspi_fifo_drain(dspi_p);
+        dspi_device->chip_sel = 0;
+    }
+}
+
+//-----------------------------------------------------------------------------
+// Get DSPI configuration parameter
+
+static int dspi_get_config (cyg_spi_device* device, cyg_uint32 key,
+                            void* buf, cyg_uint32* len)
+{
+    cyg_spi_freescale_dspi_bus_t* dspi_bus =
+          (cyg_spi_freescale_dspi_bus_t*) device->spi_bus;
+    cyg_spi_freescale_dspi_device_t* dspi_device =
+          (cyg_spi_freescale_dspi_device_t*) device;
+    cyg_uint32* data_p = buf;
+
+    switch (key) {
+    case CYG_IO_GET_CONFIG_SPI_CLOCKRATE :
+        // Sanity check
+        if (NULL == len) {
+            CYG_ASSERT (false, "Freescale DSPI:"
+                        " Null pointer as len argument for dspi_get_config().");
+            return -1;
+        } else if (sizeof(cyg_uint32) != *len) {
+            CYG_ASSERT (false, "Freescale DSPI:"
+                        " Invalid length with dspi_get_config().");
+            return -1;
+        } else if (NULL == buf) {
+            CYG_ASSERT (false, "Freescale DSPI:"
+                        " Null poiter as buf argument for dspi_get_config().");
+            return -1;
+        } else {
+            cyg_uint32 ctar, dbr, br, pbr;
+
+            ctar = dspi_device->clocking.dspi_ctar;
+            dbr = (ctar & FREESCALE_DSPI_CTAR_DBR_M) >>
+                  FREESCALE_DSPI_CTAR_DBR_S;
+            br = (ctar & FREESCALE_DSPI_CTAR_BR_M) >>
+                  FREESCALE_DSPI_CTAR_BR_S;
+            pbr = (ctar & FREESCALE_DSPI_CTAR_PBR_M) >>
+                  FREESCALE_DSPI_CTAR_PBR_S;
+            *data_p = (dspi_bus->clock_freq * (1+dbr)) / (pbr * br);
+
+            DEBUG2_PRINTF("DSPI Get Config: baud = %d\n", *data_p);
+
+            return 0;
+        }
+
+    default :
+        break;
+    }
+    return -1;
+}
+
+//-----------------------------------------------------------------------------
+// Change some SPI device configuration parameters
+
+static int dspi_set_config(cyg_spi_device* device, cyg_uint32 key,
+                           const void* buf, cyg_uint32* len)
+{
+    cyg_spi_freescale_dspi_device_t* dspi_device =
+          (cyg_spi_freescale_dspi_device_t*) device;
+    cyg_spi_freescale_dspi_bus_t* dspi_bus =
+          (cyg_spi_freescale_dspi_bus_t*) device->spi_bus;
+
+    cyg_uint32 regval;
+    ctar_br_t brs;
+
+    switch (key) {
+    case CYG_IO_SET_CONFIG_SPI_CLOCKRATE :
+        // Sanity check
+        if (NULL == len) {
+            CYG_ASSERT (false, "Freescale DSPI:"
+                      " Null pointer as len argument for dspi_set_config().");
+            return -1;
+        } else if (sizeof(cyg_uint32) != *len) {
+            CYG_ASSERT (false, "Freescale DSPI:"
+                        " Invalid length with dspi_set_config().");
+            return -1;
+        } else if (NULL == buf) {
+            CYG_ASSERT (false, "Freescale DSPI:"
+                        " Null pointer as buf argument for dspi_set_config().");
+            return -1;
+        } else {
+            // Get divider bits
+            if (!dspi_ctar_brbf(&dspi_device->clocking, &brs,
+                                   ctar_br, ctar_pbr, (cyg_uint32 *)buf, dspi_bus->clock_freq))
+            {
+                // Update the cache of the configuration register settings.
+                regval = dspi_device->clocking.dspi_ctar;
+                regval &= ~(FREESCALE_DSPI_CTAR_BR_M |
+                            FREESCALE_DSPI_CTAR_PBR_M);
+                regval |= FREESCALE_DSPI_CTAR_BR(brs.br) |
+                      FREESCALE_DSPI_CTAR_PBR(brs.pbr);
+                dspi_device->clocking.dspi_ctar = regval;
+
+                return 0;
+
+            } else {
+                CYG_ASSERT (false, "Freescale DSPI:"
+                            " Cannot run bus as slowly as requested.");
+                return -1;
+            }
+        }
+    default :
+        break;
+    }
+    return -1;
+}
+
+#if DEBUG_SPI
+//----------------------------------------------------------------------------
+// Print out a DSPI array state
+// Helper for cyghwr_devs_freescale_dspi_diag()
+
+void cyghwr_devs_freescale_dspi_diag_array(char* name_p,
+                                           volatile cyg_uint32* array_p,
+                                           cyg_uint32 array_n)
+{
+    diag_printf("%s %p[%u]: ", name_p, array_p, array_n);
+    for(; array_n; array_n--) {
+        diag_printf(" 0x%08x", *array_p++);
+    }
+    diag_printf("\n");
+}
+
+//----------------------------------------------------------------------------
+// Print out DSPI state
+
+void cyghwr_devs_freescale_dspi_diag(cyg_spi_freescale_dspi_bus_t* dspi_bus_p)
+{
+    cyghwr_devs_freescale_dspi_t* dspi_p = dspi_bus_p->setup_p->dspi_p;
+
+    diag_printf("DSPI %p\n", dspi_p);
+    diag_printf("  MCR = 0x%08x TCR = 0x%08x\n", dspi_p->mcr, dspi_p->tcr);
+    cyghwr_devs_freescale_dspi_diag_array("  CTAR",  dspi_p->ctar,
+                                          CYGHWR_DEVS_SPI_FREESCALE_DSPI_CTAR_NUM);
+    diag_printf("  SR = 0x%08x RSER = 0x%08x PUSHR = 0x%08x POPR = 0x%08x\n",
+                dspi_p->sr, dspi_p->rser, dspi_p->pushr, dspi_p->popr);
+    cyghwr_devs_freescale_dspi_diag_array("  TXFR", dspi_p->txfr, dspi_bus_p->txfifo_n);
+    cyghwr_devs_freescale_dspi_diag_array("  RXFR", dspi_p->rxfr, dspi_bus_p->rxfifo_n);
+}
+#endif // DEBUG_SPI
+
+#endif // defined(CYGHWR_DEVS_SPI_FREESCALE_DSPIx)
+
+//=============================================================================
diff --git a/packages/devs/spi/freescale/dspi/current/tests/spi_loopback.c b/packages/devs/spi/freescale/dspi/current/tests/spi_loopback.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/spi/freescale/dspi/current/tests/spi_loopback.c
@@ -0,0 +1,285 @@
+//=============================================================================
+//
+//      spi_loopback.c
+//
+//      Standalone SPI loopback test.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Ilija Kocho
+// Original:    Chris Holgate
+// Date:        2012-12-27
+// Purpose:     Freescale DSPI loopback test
+// Description: Standalone SPI loopback test.
+// Usage:       Compile as a standalone application.
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//=============================================================================
+// This is a quick loopback test for the Freescale DSPI SPI driver.  It only checks
+// the data transfer functionality - chip select handling will require
+// testing with external devices.  In order to run the test, the MOSI and
+// MISO pins for the test port need to be shorted together to provide an
+// external loopback.  Don't do this on a bus which has external devices
+// attached unless you first make sure that none of them are connected to
+// the chip select used by the test harness.
+// The default port and chip select used for this test are SPI bus 1,
+// chip select 0.  These can be changed by editing the loopback_device
+// data structure directly.
+// Note that this is intended to be run as a standalone test and not as part
+// of the standard board tests since it requires a hardware modification.
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/testcase.h>         // Test macros
+
+#include <cyg/infra/cyg_ass.h>          // Assertion macros
+#include <cyg/infra/diag.h>             // Diagnostic output
+
+#include <cyg/hal/hal_arch.h>           // CYGNUM_HAL_STACK_SIZE_TYPICAL
+#include <cyg/kernel/kapi.h>
+
+#include <cyg/io/spi.h>                 // Common SPI API
+#include <cyg/io/spi_freescale_dspi.h>  // Freescale DSPI data structures
+
+#include <string.h>
+
+//---------------------------------------------------------------------------
+// Thread data structures.
+
+cyg_uint8 stack [CYGNUM_HAL_STACK_SIZE_TYPICAL];
+cyg_thread thread_data;
+cyg_handle_t thread_handle;
+
+externC cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus1;
+
+//---------------------------------------------------------------------------
+// SPI loopback device driver data structures.
+
+CYG_DEVS_SPI_FREESCALE_DSPI_DEVICE(
+        loopback_device, // Device name
+        1, //SPI bus
+        0, // Dev num
+        8, // Frame size
+        0, // Clock pol
+        0, // Clock phase
+        6000000, // Clock speed
+        1, // CS assert delay
+        1, // CS negate delay
+        1, // Delay between transfers
+        1000, // Delay unit [ns]
+        0 // Double baud rate
+);
+
+//---------------------------------------------------------------------------
+
+static int errors = 0;
+
+const char tx_data0[] = "0123456789a123456789b123456789c123456789d123456789e";
+const char tx_data1[] = "Performing extended API test first transaction..|";
+const char tx_data2[] = "Testing extended API for a second transaction!";
+
+char rx_data [256];
+char rx_data1 [256];
+char rx_data2 [256];
+
+static void memclr(char *dest_p, cyg_uint32 byte_n)
+{
+    while(byte_n--) {
+        *dest_p++ = 0;
+    }
+}
+
+
+//---------------------------------------------------------------------------
+// Run single loopback transaction using simple transfer API call.
+
+void run_test_tick (cyg_bool polled, cyg_uint32 count)
+{
+    diag_printf ("Test 0 : Tick  (polled = %d).\n", polled ? 1 : 0);
+    cyg_spi_tick(&loopback_device, polled, count);
+    diag_printf ("    Tick end\n");
+}
+
+void run_test_1 (cyg_bool polled, const char* tx_data_p, cyg_uint32 count)
+{
+    diag_printf ("Test 1 : Simple transfer test polled = %d, count=%d\n",
+                 polled ? 1 : 0, count);
+    memclr(rx_data1, sizeof(rx_data1));
+    memclr(rx_data2, sizeof(rx_data1));
+    cyg_spi_transfer (&loopback_device, polled, count,
+        (const cyg_uint8*) tx_data_p, (cyg_uint8*) &rx_data[0]);
+    diag_printf ("    Tx data : %s\n", tx_data_p);
+    diag_printf ("    Rx data : %s 0x%02x\n", rx_data, rx_data[0]);
+
+    if (memcmp (tx_data_p, rx_data, count) != 0) {
+        errors++;
+        diag_printf("Simple transfer loopback failed - mismatched data.\n");
+    }
+}
+
+//---------------------------------------------------------------------------
+// Run two loopback transactions using extended transfer API.
+
+void run_test_2 (cyg_bool polled)
+{
+    diag_printf ("Test 2 : Extended API test (polled = %d).\n", polled ? 1 : 0);
+    memclr(rx_data1, sizeof(rx_data1));
+    memclr(rx_data2, sizeof(rx_data1));
+    cyg_spi_transaction_begin (&loopback_device);
+    cyg_spi_transaction_transfer (&loopback_device, polled, sizeof (tx_data1),
+        (const cyg_uint8*) &tx_data1[0], (cyg_uint8*) &rx_data1[0], false);
+    cyg_spi_transaction_transfer (&loopback_device, polled, sizeof (tx_data2),
+        (const cyg_uint8*) &tx_data2[0], (cyg_uint8*) &rx_data2[0], true);
+    cyg_spi_transaction_end (&loopback_device);
+
+    diag_printf ("    Tx data 1 (%u Bytes): %s\n", sizeof(tx_data1), tx_data1);
+    diag_printf ("    Rx data 1 : %s\n", rx_data1);
+    diag_printf ("    Tx data 2 (%u Bytes): %s\n", sizeof(tx_data2), tx_data2);
+    diag_printf ("    Rx data 2 : %s\n", rx_data2);
+    if (memcmp (tx_data1, rx_data1, sizeof (tx_data1)) != 0) {
+        errors++;
+        diag_printf("Simple transfer loopback failed - mismatched data (transfer 1).\n");
+    }
+    if (memcmp (tx_data2, rx_data2, sizeof (tx_data2)) != 0) {
+        errors++;
+        diag_printf("Simple transfer loopback failed - mismatched data (transfer 2).\n");
+    }
+}
+
+void run_test_3 (cyg_bool polled)
+{
+    diag_printf ("Test 3 : Extended API test (polled = %d).\n", polled ? 1 : 0);
+    memclr(rx_data1, sizeof(rx_data1));
+    memclr(rx_data2, sizeof(rx_data1));
+
+    cyg_spi_transaction_begin (&loopback_device);
+    cyg_spi_transaction_transfer (&loopback_device, polled, sizeof (tx_data1),
+                                  (const cyg_uint8*) &tx_data1[0], (cyg_uint8*) &rx_data1[0], false);
+    cyg_spi_transaction_transfer (&loopback_device, polled, sizeof (tx_data2),
+                                  (const cyg_uint8*) &tx_data2[0], (cyg_uint8*) &rx_data2[0], true);
+    cyg_spi_transaction_end (&loopback_device);
+    diag_printf ("    Tx data 1 (%u Bytes): %s\n", sizeof(tx_data1), tx_data1);
+    diag_printf ("    Rx data 31 : %s\n", rx_data1);
+    diag_printf ("    Tx data 2 (%u Bytes): %s\n", sizeof(tx_data2), tx_data2);
+    diag_printf ("    Rx data 32 : %s\n", rx_data2);
+
+    if (memcmp (tx_data1, rx_data1, sizeof (tx_data1)) != 0) {
+        errors++;
+        diag_printf("Simple transfer loopback failed - mismatched data (transfer 1).\n");
+    }
+    if (memcmp (tx_data2, rx_data2, sizeof (tx_data2)) != 0) {
+        errors++;
+        diag_printf("Simple transfer loopback failed - mismatched data (transfer 2).\n");
+    }
+}
+
+void run_test_4 (cyg_bool polled)
+{
+    diag_printf ("Test 4 : Extended API test NULL transfer (polled = %d).\n", polled ? 1 : 0);
+    memclr(rx_data1, sizeof(rx_data1));
+    memclr(rx_data2, sizeof(rx_data1));
+
+    cyg_spi_transaction_begin (&loopback_device);
+    cyg_spi_transaction_transfer (&loopback_device, polled, sizeof (tx_data1),
+                                  (const cyg_uint8*) NULL, NULL, true);
+    cyg_spi_transaction_end (&loopback_device);
+    diag_printf ("    Tx data 41 (%u Bytes): %s\n", sizeof(tx_data1), tx_data1);
+    diag_printf ("    Rx data 1 : %s\n", rx_data1);
+    diag_printf ("    Tx data 42 (%u Bytes): %s\n", sizeof(tx_data2), tx_data2);
+    diag_printf ("    Rx data 2 : %s\n", rx_data2);
+
+    if (memcmp (rx_data1, rx_data2, sizeof (tx_data1)) != 0) {
+        errors++;
+        diag_printf("Simple transfer loopback failed - mismatched data.\n");
+        errors++;
+    }
+}
+
+
+//---------------------------------------------------------------------------
+// Run all SPI interface loopback tests.
+
+
+void run_tests (void)
+{
+    bool polled = true;
+    diag_printf ("Running Freescale Kinetis/MPC5xxx DSPI driver loopback tests.\n");
+
+    diag_printf ("\nPolled\n");
+    run_test_tick (polled, 1024);
+    run_test_1 (polled, &tx_data0[3], 4);
+    run_test_2 (polled);
+    run_test_3 (polled);
+    run_test_4 (polled);
+
+    polled = false;
+    diag_printf ("\nInterrupt driven.\n");
+    run_test_tick (polled,2048);
+    run_test_1 (polled, &tx_data0[7], 10);
+    run_test_2 (polled);
+    run_test_3 (polled);
+    run_test_4 (polled);
+
+    if(errors)
+        CYG_TEST_FAIL("Errors detected");
+    else
+        CYG_TEST_PASS_FINISH ("Loopback tests ran OK");
+}
+
+//---------------------------------------------------------------------------
+// User startup - tests are run in their own thread.
+
+void cyg_user_start(void)
+{
+    CYG_TEST_INIT();
+    cyg_thread_create(
+        10,                                   // Arbitrary priority
+        (cyg_thread_entry_t*) run_tests,      // Thread entry point
+        0,                                    //
+        "test_thread",                        // Thread name
+        &stack[0],                            // Stack
+        CYGNUM_HAL_STACK_SIZE_TYPICAL,        // Stack size
+        &thread_handle,                       // Thread handle
+        &thread_data                          // Thread data structure
+    );
+    cyg_thread_resume(thread_handle);
+    cyg_scheduler_start();
+}
+
+//=============================================================================
diff --git a/packages/devs/usb/at91/current/ChangeLog b/packages/devs/usb/at91/current/ChangeLog
--- a/packages/devs/usb/at91/current/ChangeLog
+++ b/packages/devs/usb/at91/current/ChangeLog
@@ -1,3 +1,12 @@
+2010-11-12  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* src/usbs_at91.c   : Complete support for halting endpoints
+	* cdl/usbs_at91.cdl : Add option 
+	CYGSEM_DEVS_USB_AT91_ZERO_LENGTH_PACKET_TERMINATION. When data
+	transfer length is known from both side, sending an empty packet
+	at the end of the transfer is not required.
+	Add devtab entry for endpoints 4 to 7.
+    
 2008-11-17  Gabor Toeroek <tgabor84@gmail.com>
 
 	* src/usbs_at91.c (usbs_at91_set_pullup): Fix typo introduced by
@@ -101,7 +110,7 @@ 2006-03-06  Oliver Munz  <oli@snr.ch>
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2010 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/devs/usb/at91/current/cdl/usbs_at91.cdl b/packages/devs/usb/at91/current/cdl/usbs_at91.cdl
--- a/packages/devs/usb/at91/current/cdl/usbs_at91.cdl
+++ b/packages/devs/usb/at91/current/cdl/usbs_at91.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 2006 Free Software Foundation, Inc.                        
+## Copyright (C) 2006, 2010 Free Software Foundation, Inc.                        
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -41,7 +41,7 @@
 #
 # Author(s):      Oliver Munz, Andrew Lunn
 # Original data:  bartv
-# Contributors:
+# Contributors:   ccoutand
 # Date:           2006-02-25
 #
 #####DESCRIPTIONEND####
@@ -143,6 +143,17 @@ cdl_package CYGPKG_DEVS_USB_AT91 {
                    This option indicates that the power detect pin should
                    be inverted. ie VDD is active, VCC is inactive."
         }
+
+        cdl_option CYGSEM_DEVS_USB_AT91_ZERO_LENGTH_PACKET_TERMINATION {
+            display       "Allow USB driver to end data transfer with an empty data packet."
+            flavor        bool
+            default_value 1
+            description "
+                   This option allows the USB driver to automatically signal the
+                   end of a data transmission with an empty packet, if the last packet
+                   fragment is equal to the endpoint buffer size."
+        }
+
     }    
     
     cdl_component CYGPKG_DEVS_USB_AT91_DEVTAB_ENTRIES {
@@ -203,21 +214,73 @@ cdl_package CYGPKG_DEVS_USB_AT91 {
                 application intends to access the endpoint by means
                 of open and read calls then a devtab entry is needed."
         }
-
-            cdl_option CYGDAT_DEVS_USB_AT91_DEVTAB_BASENAME {
-                display       "Base name for devtab entries"
-                flavor        data
-                default_value { "\"/dev/usbs\"" }
-                description "
-                    If the uAT91 USB device driver package provides devtab
-                    entries for any of the endpoints then this option gives
-                    control over the names of these entries. By default the
-                    endpoints will be called \"/dev/usbs0c\", \"/dev/usbs3w\"
-                    and \"/dev/usbs4r\" (assuming all three endpoints are
-                    enabled. The common part \"/dev/usbs\" is determined
-                    by this configuration option. It may be necessary to
-                    change this if there are multiple USB slave-side
-                    devices on the target hardware to prevent a name clash."
-            }
+        
+        cdl_option CYGVAR_DEVS_USB_AT91_EP4_DEVTAB_ENTRY {
+            display       "Provide a devtab entry for endpoint 4"
+            flavor        bool
+            default_value 0
+            requires      CYGPKG_IO 
+            description "
+                If this endpoint will only be accessed via the low-level
+                USB-specific calls then there is no need for an entry
+                in the device table, saving some memory. If the
+                application intends to access the endpoint by means
+                of open and read calls then a devtab entry is needed."
+        }
+                
+        cdl_option CYGVAR_DEVS_USB_AT91_EP5_DEVTAB_ENTRY {
+            display       "Provide a devtab entry for endpoint 5"
+            flavor        bool
+            default_value 0
+            requires      CYGPKG_IO 
+            description "
+                If this endpoint will only be accessed via the low-level
+                USB-specific calls then there is no need for an entry
+                in the device table, saving some memory. If the
+                application intends to access the endpoint by means
+                of open and read calls then a devtab entry is needed."
+        }
+           
+        cdl_option CYGVAR_DEVS_USB_AT91_EP6_DEVTAB_ENTRY {
+            display       "Provide a devtab entry for endpoint 6"
+            flavor        bool
+            default_value 0
+            requires      CYGPKG_IO 
+            description "
+                If this endpoint will only be accessed via the low-level
+                USB-specific calls then there is no need for an entry
+                in the device table, saving some memory. If the
+                application intends to access the endpoint by means
+                of open and read calls then a devtab entry is needed."
+        }
+           
+        cdl_option CYGVAR_DEVS_USB_AT91_EP7_DEVTAB_ENTRY {
+            display       "Provide a devtab entry for endpoint 7"
+            flavor        bool
+            default_value 0
+            requires      CYGPKG_IO 
+            description "
+                If this endpoint will only be accessed via the low-level
+                USB-specific calls then there is no need for an entry
+                in the device table, saving some memory. If the
+                application intends to access the endpoint by means
+                of open and read calls then a devtab entry is needed."
+        }
+                                 
+        cdl_option CYGDAT_DEVS_USB_AT91_DEVTAB_BASENAME {
+            display       "Base name for devtab entries"
+            flavor        data
+            default_value { "\"/dev/usbs\"" }
+            description "
+                If the uAT91 USB device driver package provides devtab
+                entries for any of the endpoints then this option gives
+                control over the names of these entries. By default the
+                endpoints will be called \"/dev/usbs0c\", \"/dev/usbs3w\"
+                and \"/dev/usbs4r\" (assuming all three endpoints are
+                enabled. The common part \"/dev/usbs\" is determined
+                by this configuration option. It may be necessary to
+                change this if there are multiple USB slave-side
+                devices on the target hardware to prevent a name clash."
+        }
     }
 }
diff --git a/packages/devs/usb/at91/current/src/usbs_at91.c b/packages/devs/usb/at91/current/src/usbs_at91.c
--- a/packages/devs/usb/at91/current/src/usbs_at91.c
+++ b/packages/devs/usb/at91/current/src/usbs_at91.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2006 Free Software Foundation, Inc.                        
+// Copyright (C) 2006, 2010 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -40,7 +40,7 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):    Oliver Munz,
-// Contributors: Andrew Lunn, bartv
+// Contributors: Andrew Lunn, bartv, ccoutand
 // Date:         2006-02-22
 //
 // This code implements support for the on-chip USB port on the AT91
@@ -524,7 +524,7 @@ usbs_state_notify (usbs_control_endpoint
     }
     
     if (pcep->state_change_fn) {
-      (*pcep->state_change_fn) (pcep, 0, pcep->state, old_state);
+      (*pcep->state_change_fn) (pcep, pcep->state_change_data, pcep->state, old_state);
     }
     
     old_state = pcep->state;
@@ -579,22 +579,35 @@ usbs_at91_endpoint_set_halted (usbs_rx_e
 {
   int epn = usbs_at91_pep_to_number(pep);
   cyg_addrword_t pCSR = pCSRn(epn);
-  
+  cyg_uint32 reg;  
+
   cyg_drv_dsr_lock ();
   
-  if (pep->halted != new_value) {       
+  if (pep->halted != new_value) {
     /* There is something is to do */
     pep->halted = new_value;
+
+    if ( new_value ) {
     
-    if (new_value && BITS_ARE_SET (pIMR, 1 << epn)) {   
-      /* Ready to transmit */
+      /* Halt endpoint */
+      SET_BITS (pCSR, AT91_UDP_CSR_FORCESTALL);
+
+    } else {
+      /* Restart endpoint */
+      CLEAR_BITS (pCSR, AT91_UDP_CSR_FORCESTALL);
+
+      // Reset Fifo
+      HAL_READ_UINT32 (AT91_UDP + AT91_UDP_RST_EP, reg);
+      reg |= (1 << epn);
+      HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_RST_EP, reg);
+      reg &= ~(1 << epn);
+      HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_RST_EP, reg);
+
+      // Ready to use
       if (pep->complete_fn) {
-        (*pep->complete_fn) (pep->complete_data, -EAGAIN);
+        (*pep->complete_fn) (pep->complete_data, ENOERR);
       }
-      usbs_at91_endpoint_interrupt_enable (epn, false);
-      SET_BITS (pCSR, AT91_UDP_CSR_FORCESTALL);
-    } else {
-      CLEAR_BITS (pCSR, AT91_UDP_CSR_FORCESTALL);
+
     }
   }
   cyg_drv_dsr_unlock ();
@@ -726,11 +739,14 @@ usbs_at91_endpoint_start (usbs_rx_endpoi
     return;
   }
   
+  // Is this endpoint currently stalled? If so then a size of 0 can
+  // be used to block until the stall condition is clear, anything
+  // else should result in an immediate callback.
   if (pep->halted) {            
     /* Halted means nothing to do */
     cyg_drv_dsr_unlock ();
 
-    if (pep->complete_fn) {
+    if (pep->complete_fn && pep->buffer_size != 0) {
       (*pep->complete_fn) (pep->complete_data, -EAGAIN);
     }
     return;
@@ -753,9 +769,12 @@ usbs_at91_endpoint_start (usbs_rx_endpoi
   
   if (BITS_ARE_SET (pCSR, 0x400)) {     /* IN: tx_endpoint */
     space = (cyg_uint32) * ppend - (cyg_uint32) * ppbegin;
+
+#ifdef CYGSEM_DEVS_USB_AT91_ZERO_LENGTH_PACKET_TERMINATION
     if (space == endpoint_size) {
       *ppend = *ppbegin;        /* Send zero-packet */
     }
+#endif
     
     *ppbegin =
       write_fifo_uint8 (pFDR, *ppbegin,
@@ -786,26 +805,32 @@ usbs_at91_endpoint_isr_tx(cyg_uint8 epn)
 
   CLEAR_BITS (pCSR, AT91_UDP_CSR_TXCOMP);
 
-  if (BITS_ARE_CLEARED (pCSR, AT91_UDP_CSR_TXPKTRDY)) {       
+  if (BITS_ARE_CLEARED (pCSR, AT91_UDP_CSR_TXPKTRDY)) {
     /* Ready to transmit ? */
     if (*ppend > *ppbegin) {  
       /* Something to send */
       
       space = (cyg_uint32) * ppend - (cyg_uint32) * ppbegin;
+
+#ifdef CYGSEM_DEVS_USB_AT91_ZERO_LENGTH_PACKET_TERMINATION
       if (space == endpoint_size) {
         *ppend = *ppbegin;            /* Send zero-packet */
       }
+#endif
       
       *ppbegin =
         write_fifo_uint8 (pFDR, *ppbegin,
                           (cyg_uint8 *) ((cyg_uint32) * ppbegin +
                                          MIN (space, endpoint_size)));
       SET_BITS (pCSR, AT91_UDP_CSR_TXPKTRDY);
-      
+
       if (*ppend == *ppbegin) {       /* Last packet ? */
         *ppend = *ppbegin - 1;        /* The packet isn't sent yet */
       }
+
     } else {
+
+#ifdef CYGSEM_DEVS_USB_AT91_ZERO_LENGTH_PACKET_TERMINATION
       if (*ppend + 1 == *ppbegin) {
         *ppend = *ppbegin;    /* Flag for DSR */
         return true;
@@ -813,6 +838,11 @@ usbs_at91_endpoint_isr_tx(cyg_uint8 epn)
         *ppend = *ppbegin - 1;        /* Flag for zero-packet */
         SET_BITS (pCSR, AT91_UDP_CSR_TXPKTRDY);       /* Send no data */
       }
+#else
+      *ppend = *ppbegin;    /* Flag for DSR */
+      return true;
+#endif
+
     }
   }
   
@@ -887,6 +917,11 @@ usbs_at91_endpoint_isr (cyg_uint8 epn)
   
   CYG_ASSERT (AT91_USB_ENDPOINTS > epn && epn, "Invalid end point");
   
+  // Host has acknowledged the endpoint being stall 
+  if (BITS_ARE_SET (pCSR, AT91_UDP_CSR_ISOERROR)) {
+     CLEAR_BITS (pCSR, AT91_UDP_CSR_ISOERROR);
+  }
+    
   if (BITS_ARE_SET (pCSR, 0x400)) {      /* IN: tx_endpoint */
     if (usbs_at91_endpoint_isr_tx(epn))
       return true;  // Call the DSR
@@ -920,12 +955,15 @@ usbs_at91_endpoint_dsr (cyg_uint8 epn)
   if (*ppend == *ppbegin) {     /* Transmitted/Received ? */
     
     pep->buffer_size = (cyg_uint32) * ppbegin - (cyg_uint32) pep->buffer;
-    if (pep->buffer_size && pep->complete_fn) {
-      if (!pep->halted) {
-        (*pep->complete_fn) (pep->complete_data, pep->buffer_size);
-      } else {
-        (*pep->complete_fn) (pep->complete_data, -EAGAIN);
-      }
+    if (pep->complete_fn)
+    {
+       /* Do not check on pep->buffer_size != 0, user should
+        * be allowed to send empty packet */
+       if (!pep->halted) {
+          (*pep->complete_fn) (pep->complete_data, pep->buffer_size);
+       } else {
+          (*pep->complete_fn) (pep->complete_data, -EAGAIN);
+       }
     }
     usbs_at91_endpoint_interrupt_enable (epn, false);
   }
@@ -1018,6 +1056,8 @@ usbs_at91_control_setup_set_feature(void
   ep0_low_level_status_t status;
   usb_devreq *req = (usb_devreq *)usbs_at91_ep0.control_buffer;
   cyg_uint8 recipient = req->type & USB_DEVREQ_RECIPIENT_MASK;
+  usbs_rx_endpoint * pep;
+  cyg_uint8 ep_num = req->index_lo & 0x0F;
   
   usbs_at91_control_setup_send_ack();
   status = EP0_LL_SEND_READY;
@@ -1030,18 +1070,24 @@ usbs_at91_control_setup_set_feature(void
       // Nothing to do
       break;
     case USB_DEVREQ_RECIPIENT_ENDPOINT: 
-      if ((usbs_at91_ep0.state == USBS_STATE_CONFIGURED) && 
-          (req->index_lo > 0) && 
-          (req->index_lo < AT91_USB_ENDPOINTS)) {
+      if ((usbs_at91_ep0.state == USBS_STATE_CONFIGURED) &&
+            (ep_num > 0) &&
+            (ep_num < AT91_USB_ENDPOINTS)) {
         cyg_uint32 CSR;
-        
-        HAL_READ_UINT32(pCSRn(req->index_lo), CSR);
-        if (CSR & AT91_UDP_CSR_EPEDS) {
-          /* TODO */
+
+        HAL_READ_UINT32(pCSRn(ep_num), CSR);
+        pep = (usbs_rx_endpoint *) usbs_at91_endpoints[ep_num];
+        if ( (CSR & AT91_UDP_CSR_EPEDS) ) {
+          usbs_at91_endpoint_set_halted ( pep , true );
         }
-      } else {
+        else
+          status = EP0_LL_STALL;
+
+      }
+      else {
         status = EP0_LL_STALL;
       }
+      break;
     default:
       status = EP0_LL_STALL;
   }
@@ -1055,6 +1101,8 @@ usbs_at91_control_setup_clear_feature(vo
   ep0_low_level_status_t status;
   usb_devreq *req = (usb_devreq *)usbs_at91_ep0.control_buffer;
   cyg_uint8 recipient = req->type & USB_DEVREQ_RECIPIENT_MASK;
+  usbs_rx_endpoint * pep;
+  cyg_uint8 ep_num = req->index_lo & 0x0F;  
   
   usbs_at91_control_setup_send_ack();
   status = EP0_LL_SEND_READY;
@@ -1067,18 +1115,24 @@ usbs_at91_control_setup_clear_feature(vo
       // Nothing to do
       break;
     case USB_DEVREQ_RECIPIENT_ENDPOINT: 
-      if ((usbs_at91_ep0.state == USBS_STATE_CONFIGURED) && 
-          (req->index_lo > 0) && 
-          (req->index_lo < AT91_USB_ENDPOINTS)) {
+      if ((usbs_at91_ep0.state == USBS_STATE_CONFIGURED) &&
+          (ep_num > 0) &&
+          (ep_num < AT91_USB_ENDPOINTS)) {
         cyg_uint32 CSR;
-        
-        HAL_READ_UINT32(pCSRn(req->index_lo), CSR);
-        if (CSR & AT91_UDP_CSR_EPEDS) {
-          /* TODO */
+
+        HAL_READ_UINT32(pCSRn(ep_num), CSR);
+        pep = (usbs_rx_endpoint *) usbs_at91_endpoints[ep_num];
+        if ( (CSR & AT91_UDP_CSR_EPEDS) && pep->halted ) {
+          usbs_at91_endpoint_set_halted ( pep , false );
         }
-      } else {
+        else
+          status = EP0_LL_STALL;
+
+      }
+      else {
         status = EP0_LL_STALL;
       }
+      break;
     default:
       status = EP0_LL_STALL;
   }
diff --git a/packages/devs/usb/cortexm/stm32/current/ChangeLog b/packages/devs/usb/cortexm/stm32/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/usb/cortexm/stm32/current/ChangeLog
@@ -0,0 +1,41 @@
+2012-04-13  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* src/usb_stm32.c (cyg_usbs_cortexm_stm32_init):
+	Peripheral clocks are enable / disable using new 
+	CYGHWR_HAL_STM32_CLOCK_DISABLE / CYGHWR_HAL_STM32_CLOCK_ENABLE
+	macro supplied from the variant HAL
+
+2012-04-03  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* src/usb_stm32.c (cyg_usbs_cortexm_stm32_init):
+	CYGHWR_HAL_STM32_RCC_APB1ENR_CAN was renamed to
+	CYGHWR_HAL_STM32_RCC_APB1ENR_CAN1 in variant HAL.
+
+2010-10-27  Chris Holgate  <chris@zynaptic.com>
+
+	* src/usb_stm32.c, include/usb_stm32.h, cdl/usb_stm32.cdl: New
+	STM32 USB slave driver. [ Bugzilla 1001024 ]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/devs/usb/cortexm/stm32/current/cdl/usb_stm32.cdl b/packages/devs/usb/cortexm/stm32/current/cdl/usb_stm32.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/usb/cortexm/stm32/current/cdl/usb_stm32.cdl
@@ -0,0 +1,325 @@
+##=============================================================================
+##
+##      usb_stm32.cdl
+##
+##      STM32 USB driver configuration options.
+##
+##=============================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##=============================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):   Chris Holgate
+## Date:        2009-05-19
+## Purpose:     Configure STM32 USB driver.
+##
+######DESCRIPTIONEND####
+##
+##=============================================================================
+
+#
+# TODO: Needs to check that the PLL is running off the HSE clock source and
+# is set up to run at 48MHz or 72MHz.
+#
+
+cdl_package CYGPKG_DEVS_USB_CORTEXM_STM32 {
+    display       "ST STM32 USB driver"
+    description   "
+        This package provides USB device side driver support for the ST 
+        STM32 series of microcontrollers.
+    "
+    parent        CYGPKG_IO_USB
+    active_if     CYGPKG_IO_USB
+    hardware
+    include_dir   "cyg/io/usb"
+
+    # Make sure that we are running on the right hardware.
+    requires CYGPKG_HAL_CORTEXM_STM32
+
+    cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_EP0 {
+        display       "Enable the control endpoint 0"
+        default_value CYGINT_IO_USB_SLAVE_CLIENTS
+        requires      CYGPKG_IO_USB_SLAVE
+        requires      !CYGGLO_IO_USB_SLAVE_PROVIDE_DEVTAB_ENTRIES
+        compile       usb_stm32.c
+        description "
+            Enable support for endpoint 0. If this support is disabled
+            then the entire USB port is unusable.  Note that this driver does
+            not support slave side devtab entries."
+        }
+    
+    cdl_option CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM {
+        display       "Max IN endpoints"
+        description   "
+            Specify the maximum number of IN (transmit) endpoints supported by the device.
+            The total number of standard IN and OUT endpoints should not exceed 7.
+        "
+        flavor        data
+        default_value { 2 }
+        legal_values  { 0 to (7 - CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) }
+    }
+
+    cdl_option CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM {
+        display       "Max OUT endpoints"
+        description   "
+            Specify the maximum number of OUT (receive) endpoints supported by the device.
+            The total number of standard IN and OUT endpoints should not exceed 7.
+        "
+        flavor        data
+        default_value { 2 }
+        legal_values  { 0 to (7 - CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) }
+    }
+
+    cdl_option CYGNUM_DEVS_USB_CORTEXM_STM32_EPO_MAX_MSG_SIZE {
+        display       "Control endpoint buffer size"
+        description   "
+            Selects the size of the control endpoint data buffer, which sets the maximum size 
+            of the control endpoint data phase transactions.
+        "
+        flavor        data
+        default_value { 128 }    
+        legal_values  { 8 to 256 }
+    }
+
+    cdl_option CYGHWR_DEVS_USB_CORTEXM_STM32_SELF_POWERED {
+        display       "Self powered"
+        description   "
+            If set, the USB device will report itself to the host as being self-powered.
+            There is no support for dynamically detecting the power state for dual powered
+            devices.
+        "
+        flavor        bool
+        default_value false
+    }
+    
+    cdl_option CYGHWR_DEVS_USB_CORTEXM_STM32_BULK_TERM_ZLP {
+        display       "Variable length bulk transfers"
+        description   "
+            Some USB device classes (eg. CDC ATM) require support for variable length bulk 
+            messages.  This is implemented by terminating bulk transfers using a short or 
+            zero length packet.  Selecting this option enables this form of variable length 
+            bulk message transfer for all bulk endpoints.  Note that this option is incompatible 
+            with the standard eCos USB test framework.  
+        "
+        flavor        bool
+        default_value false
+    }
+    
+    cdl_option CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN {
+        display       "USB disconnect pin"
+        description   "
+            This is the GPIO which is used to control the USB bus D+ pullup resistor, which
+            allows the USB bus connection status to be changed under software control.
+            For the purposes of specifying which GPIO to use, pins are numbered consecutively 
+            from 0 (A0) through 16 (B0) to 111 (G15).
+        "
+        flavor        data
+        default_value { 30 }
+    }
+    
+    cdl_option CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN_ACT_LOW {
+        display       "Active low USB disconnect"
+        description   "
+            The USB disconnect pin is normally treated as active high - so that when set high 
+            the device will be disconnected from the bus.  Select this option for boards where
+            the USB disconnect pin is wired as active low.
+        "
+        flavor        bool
+        default_value false
+    }
+
+    cdl_option CYGNUM_DEVS_USB_CORTEXM_STM32_ISR_PRIORITY {
+        display       "ISR priority"
+        description   "
+            Sets the ISR priority level used by the USB driver.
+        "
+        flavor        data
+        default_value { 4 }
+    }
+    
+    cdl_option CYGBLD_DEVS_USB_CORTEXM_STM32_DEBUG_TRACE {
+        display       "Debug trace enable"
+        description   "
+            Enables debug tracing for the USB driver.
+        "
+        flavor        bool
+        default_value false
+    }
+    
+    cdl_component CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_CONFIG {
+        display       "Physical endpoint configuration."
+        description   "
+            This is the automatically generated physical endpoint configuration for the 
+            STM32 USB device.  Note that the physical endpoint numbering is only used 
+            internally to the driver and has no bearing on the logical endpoint numbers
+            which may be specified in a given device configuration.
+        "
+        flavor none
+    
+        cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_CTRLEP0 {
+            display "Physical endpoint 0 CTRL"
+            flavor bool
+            active_if { (CYGFUN_DEVS_USB_CORTEXM_STM32_EP0) }
+            calculated { (CYGFUN_DEVS_USB_CORTEXM_STM32_EP0) }
+            implements CYGHWR_IO_USB_SLAVE
+        }
+
+        cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_TXEP1 {
+            display "Physical endpoint 1 IN"
+            flavor bool
+            active_if { (1 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) }
+            calculated { (1 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) }
+            implements CYGHWR_IO_USB_SLAVE_IN_ENDPOINTS
+        }
+    
+        cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_TXEP2 {
+            display "Physical endpoint 2 IN"
+            flavor bool
+            active_if { (2 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) }
+            calculated { (2 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) }
+            implements CYGHWR_IO_USB_SLAVE_IN_ENDPOINTS
+        }
+    
+        cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_TXEP3 {
+            display "Physical endpoint 3 IN"
+            flavor bool
+            active_if { (3 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) }
+            calculated { (3 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) }
+            implements CYGHWR_IO_USB_SLAVE_IN_ENDPOINTS
+        }
+    
+        cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_TXEP4 {
+            display "Physical endpoint 4 IN"
+            flavor bool
+            active_if { (4 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) }
+            calculated { (4 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) }
+            implements CYGHWR_IO_USB_SLAVE_IN_ENDPOINTS
+        }
+    
+        cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_TXEP5 {
+            display "Physical endpoint 5 IN"
+            flavor bool
+            active_if { (5 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) }
+            calculated { (5 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) }
+            implements CYGHWR_IO_USB_SLAVE_IN_ENDPOINTS
+        }
+    
+        cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_TXEP6 {
+            display "Physical endpoint 6 IN"
+            flavor bool
+            active_if { (6 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) }
+            calculated { (6 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) }
+            implements CYGHWR_IO_USB_SLAVE_IN_ENDPOINTS
+        }
+    
+        cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_TXEP7 {
+            display "Physical endpoint 7 IN"
+            flavor bool
+            active_if { (7 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) }
+            calculated { (7 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) }
+            implements CYGHWR_IO_USB_SLAVE_IN_ENDPOINTS
+        }
+    
+        cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_RXEP1 {
+            display "Physical endpoint 1 OUT"
+            flavor bool
+            active_if { (1 > CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) && 
+                (1 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) }
+            calculated { (1 > CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) && 
+                (1 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) }
+            implements CYGHWR_IO_USB_SLAVE_OUT_ENDPOINTS
+        }
+    
+        cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_RXEP2 {
+            display "Physical endpoint 2 OUT"
+            flavor bool
+            active_if { (2 > CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) && 
+                (2 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) }
+            calculated { (2 > CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) && 
+                (2 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) }
+            implements CYGHWR_IO_USB_SLAVE_OUT_ENDPOINTS
+        }
+    
+        cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_RXEP3 {
+            display "Physical endpoint 3 OUT"
+            flavor bool
+            active_if { (3 > CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) && 
+                (3 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) }
+            calculated { (3 > CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) && 
+                (3 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) }
+            implements CYGHWR_IO_USB_SLAVE_OUT_ENDPOINTS
+        }
+    
+        cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_RXEP4 {
+            display "Physical endpoint 4 OUT"
+            flavor bool
+            active_if { (4 > CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) && 
+                (4 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) }
+            calculated { (4 > CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) && 
+                (4 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) }
+            implements CYGHWR_IO_USB_SLAVE_OUT_ENDPOINTS
+        }
+    
+        cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_RXEP5 {
+            display "Physical endpoint 5 OUT"
+            flavor bool
+            active_if { (5 > CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) && 
+                (5 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) }
+            calculated { (5 > CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) && 
+                (5 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) }
+            implements CYGHWR_IO_USB_SLAVE_OUT_ENDPOINTS
+        }
+    
+        cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_RXEP6 {
+            display "Physical endpoint 6 OUT"
+            flavor bool
+            active_if { (6 > CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) && 
+                (6 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) }
+            calculated { (6 > CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) && 
+                (6 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) }
+            implements CYGHWR_IO_USB_SLAVE_OUT_ENDPOINTS
+        }
+    
+        cdl_option CYGFUN_DEVS_USB_CORTEXM_STM32_PHY_RXEP7 {
+            display "Physical endpoint 7 OUT"
+            flavor bool
+            active_if { (7 > CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) && 
+                (7 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) }
+            calculated { (7 > CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) && 
+                (7 <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) }
+            implements CYGHWR_IO_USB_SLAVE_OUT_ENDPOINTS
+        }
+    }
+}
+
+# EOF usb_stm32.cdl
diff --git a/packages/devs/usb/cortexm/stm32/current/include/usb_stm32.h b/packages/devs/usb/cortexm/stm32/current/include/usb_stm32.h
new file mode 100644
--- /dev/null
+++ b/packages/devs/usb/cortexm/stm32/current/include/usb_stm32.h
@@ -0,0 +1,56 @@
+#ifndef CYGONCE_DEVS_USB_CORTEXM_STM32_H
+#define CYGONCE_DEVS_USB_CORTEXM_STM32_H
+
+//=============================================================================
+//
+//      usb_stm32.h
+//
+//      USB slave driver for STM32
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Chris Holgate
+// Date:        2009-05-19
+// Purpose:     STM32 USB slave driver 
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+// Provide external access to the common endpoint 0 data structure.
+extern usbs_control_endpoint cyg_usbs_cortexm_stm32_ep0c;
+
+#endif // CYGONCE_DEVS_USB_CORTEXM_STM32_H
diff --git a/packages/devs/usb/cortexm/stm32/current/src/usb_stm32.c b/packages/devs/usb/cortexm/stm32/current/src/usb_stm32.c
new file mode 100644
--- /dev/null
+++ b/packages/devs/usb/cortexm/stm32/current/src/usb_stm32.c
@@ -0,0 +1,2456 @@
+//=============================================================================
+//
+//      usb_stm32.c
+//
+//      USB slave driver implementation for STM32
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Chris Holgate
+// Date:        2009-05-19
+// Purpose:     STM32 USB slave driver implementation
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/diag.h>
+
+#include <cyg/hal/drv_api.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_if.h>
+
+#include <cyg/io/usb/usb.h>
+#include <cyg/io/usb/usbs.h>
+
+#include <string.h>
+
+#include <pkgconf/io_usb_slave.h>
+#include <pkgconf/devs_usb_cortexm_stm32.h>
+
+//-----------------------------------------------------------------------------
+// Maintenance and debug macros.
+
+#define TODO_USB(_msg_) CYG_ASSERT(false, "TODO (USB) : " _msg_)
+#define FAIL_USB(_msg_) CYG_ASSERT(false, "FAIL (USB) : " _msg_)
+#define ASSERT_USB(_test_, _msg_) CYG_ASSERT(_test_, "FAIL (USB) : " _msg_)
+
+#if defined(CYGBLD_DEVS_USB_CORTEXM_STM32_DEBUG_TRACE)
+#define TRACE_USB(_msg_, _args_...) diag_printf ("STM32 USB : " _msg_, ##_args_)
+#else
+#define TRACE_USB(_msg_, _args_...) while(0){}
+#endif
+
+//-----------------------------------------------------------------------------
+// Shorthand for some of the configuration options.
+
+#define USB_BASE     CYGHWR_HAL_STM32_USB
+#define USB_RAM_BASE CYGHWR_HAL_STM32_USB_CAN_SRAM
+#define USB_RAM_SIZE 512
+#define USB_EPNUM    (1 + CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM)
+
+//-----------------------------------------------------------------------------
+// Work out the bus clock frequencies and external timing constraints.
+// NOTE: These require that the clock source is set to HSE, which should be
+// forced by the CDL.
+
+#define PLL_FREQ (CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK * CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL)
+
+#define APB1_FREQ ((CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK * CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL) / \
+  (CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV * CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV)) 
+
+#define USB_TSTARTUP 1
+
+//-----------------------------------------------------------------------------
+// Provide macros for accessing the buffer layout pseudo-registers.
+
+// Pseudo-registers for single buffer configurations.
+#define USB_RAM_SB_TXADDR(__ep)        ((__ep)*16)
+#define USB_RAM_SB_TXCOUNT(__ep)       ((__ep)*16+4)
+#define USB_RAM_SB_RXADDR(__ep)        ((__ep)*16+8)
+#define USB_RAM_SB_RXCOUNT(__ep)       ((__ep)*16+12)
+
+// Pseudo-registers for double buffer configurations.
+#define USB_RAM_DB_TXADDR(__ep,__buf)  ((__ep)*16+(__buf)*8)
+#define USB_RAM_DB_TXCOUNT(__ep,__buf) ((__ep)*16+(__buf)*8+4)
+#define USB_RAM_DB_RXADDR(__ep,__buf)  ((__ep)*16+(__buf)*8)
+#define USB_RAM_DB_RXCOUNT(__ep,__buf) ((__ep)*16+(__buf)*8+4)
+
+#define USB_RAM_XX_RXCOUNT_BLOCKS(__x) VALUE_(10,__x)
+#define USB_RAM_XX_RXCOUNT_COUNT_MASK  VALUE_(0, 0x03FF)
+
+//-----------------------------------------------------------------------------
+// Set up USB I/O pin configurations.
+
+#if (CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN < 0x10)
+#define USB_DISC_PIN CYGHWR_HAL_STM32_GPIO \
+  (A, (CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN & 0x0F), OUT_2MHZ, OUT_PUSHPULL)
+
+#elif (CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN < 0x20)
+#define USB_DISC_PIN CYGHWR_HAL_STM32_GPIO \
+  (B, (CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN & 0x0F), OUT_2MHZ, OUT_PUSHPULL)
+
+#elif (CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN < 0x30)
+#define USB_DISC_PIN CYGHWR_HAL_STM32_GPIO \
+  (C, (CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN & 0x0F), OUT_2MHZ, OUT_PUSHPULL)
+
+#elif (CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN < 0x40)
+#define USB_DISC_PIN CYGHWR_HAL_STM32_GPIO \
+  (D, (CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN & 0x0F), OUT_2MHZ, OUT_PUSHPULL)
+
+#elif (CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN < 0x50)
+#define USB_DISC_PIN CYGHWR_HAL_STM32_GPIO \
+  (E, (CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN & 0x0F), OUT_2MHZ, OUT_PUSHPULL)
+
+#elif (CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN < 0x60)
+#define USB_DISC_PIN CYGHWR_HAL_STM32_GPIO \
+  (F, (CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN & 0x0F), OUT_2MHZ, OUT_PUSHPULL)
+
+#elif (CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN < 0x70)
+#define USB_DISC_PIN CYGHWR_HAL_STM32_GPIO \
+  (G, (CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN & 0x0F), OUT_2MHZ, OUT_PUSHPULL)
+#endif
+
+#define USB_DP_PIN CYGHWR_HAL_STM32_GPIO (A, 12, IN, AIN)
+#define USB_DM_PIN CYGHWR_HAL_STM32_GPIO (A, 11, IN, AIN)
+
+//=============================================================================
+// Define USB transmit endpoint data structures.
+//=============================================================================
+
+typedef enum {
+  TXTR_FLAGS_NONE   = 0x00, // No flags set.
+  TXTR_FLAGS_ZLPKT  = 0x01, // Set to enable zero length packet termination.
+  TXTR_FLAGS_DBUF   = 0x02, // Set to enable doubtle buffered operation.
+} txtr_flags;
+
+typedef enum {
+  TXTR_STATE_RESET,         // TX transaction reset state. 
+  TXTR_STATE_IDLE,          // TX transaction idle (between transactions).
+  TXTR_STATE_SB_NEXT_PKT,   // TX transaction send next packet (single buffer).
+  TXTR_STATE_SB_ZERO_PKT,   // TX transaction send zero length packet (single buffer). 
+  TXTR_STATE_SB_DONE,       // TX transaction complete (single buffer).
+  TXTR_STATE_DB_FIRST_PKT,  // TX transaction queue first packet (double buffer).
+  TXTR_STATE_DB_NEXT_PKT,   // TX transaction queue next packet (double buffer).
+  TXTR_STATE_DB_ZERO_PKT,   // TX transaction queue zero length packet (double buffer).
+  TXTR_STATE_DB_LAST_PKT,   // TX transaction send last queued packet (double buffer).
+  TXTR_STATE_DB_DONE,       // TX transaction complete (double buffer).
+} txtr_state;
+
+typedef struct txtr_impl {
+  txtr_state        state;             // Current transaction state.
+  txtr_flags        flags;             // Transaction flags.
+  cyg_uint16        status;            // Return status. 
+  cyg_uint8         ep_num;            // Endpoint number.
+  const cyg_uint8*  buf_ptr;           // Pointer to next user buffer location.
+  cyg_uint32        buf_size;          // Size of user transmit buffer.
+  cyg_uint32        bytes_sent;        // Track number of bytes sent. 
+} txtr_impl;
+
+typedef struct txep_impl {
+  usbs_tx_endpoint  common;            // High level driver data.
+  txtr_impl         txtr;              // Transaction data.
+} txep_impl;
+
+//=============================================================================
+// Define USB receive endpoint data structures.
+//=============================================================================
+
+typedef enum {
+  RXTR_FLAGS_NONE   = 0x00, // No flags set.
+  RXTR_FLAGS_ZLPKT  = 0x01, // Set to enable zero length packet termination.
+  RXTR_FLAGS_DBUF   = 0x02, // Set to enable doubtle buffered operation.
+} rxtr_flags;
+
+typedef enum {
+  RXTR_STATE_RESET,         // RX transaction reset state.
+  RXTR_STATE_IDLE,          // RX transaction idle (between transactions).
+  RXTR_STATE_SB_NEXT_PKT,   // RX transaction get next packet (single buffer).
+  RXTR_STATE_DB_NEXT_PKT,   // RX transaction get next packet (double buffer).
+} rxtr_state;
+
+typedef struct rxtr_impl {
+  rxtr_state        state;             // Current transaction state.
+  rxtr_flags        flags;             // Transaction flags.
+  cyg_uint16        status;            // Return status. 
+  cyg_uint8         ep_num;            // Endpoint number.
+  cyg_uint8*        buf_ptr;           // Pointer to next user buffer location.
+  cyg_uint32        buf_size;          // Size of receive buffer.
+  cyg_uint32        bytes_rcvd;        // Track number of bytes received.
+} rxtr_impl;
+
+typedef struct rxep_impl {
+  usbs_rx_endpoint  common;            // High level driver data.
+  rxtr_impl         rxtr;              // Transaction data.
+} rxep_impl;
+
+//=============================================================================
+// Instantiate USB control endpoint data structure.
+//=============================================================================
+
+static void stm32_usb_start (usbs_control_endpoint*);
+static void stm32_usb_poll  (usbs_control_endpoint*);
+static usbs_rx_endpoint* stm32_usb_get_rxep (usbs_control_endpoint*, cyg_uint8);
+static usbs_tx_endpoint* stm32_usb_get_txep (usbs_control_endpoint*, cyg_uint8);
+
+// Track the control endpoint state.
+typedef enum {
+  CTRLEP_MSG_STATE_IDLE,
+  CTRLEP_MSG_STATE_IN_DATA,
+  CTRLEP_MSG_STATE_IN_STATUS,
+  CTRLEP_MSG_STATE_OUT_DATA,
+  CTRLEP_MSG_STATE_OUT_STATUS,
+  CTRLEP_MSG_STATE_CTRL_ACK,
+} ctrlep_msg_states;
+
+// Provide the control message buffer.
+static cyg_uint8 ctrlep_msg_buffer [CYGNUM_DEVS_USB_CORTEXM_STM32_EPO_MAX_MSG_SIZE];
+
+// Provide STM32 control endpoint implementation.
+typedef struct ctrlep_impl {
+  usbs_control_endpoint   common;      // High level driver data.
+  txtr_impl               txtr;        // Transmit transaction data.
+  rxtr_impl               rxtr;        // Receive transaction data.
+  ctrlep_msg_states       msg_state;   // Control endpoint messaging state.
+} ctrlep_impl;
+
+// Instantiate control endpoint data structure.
+static ctrlep_impl ctrlep = {
+  { // Set up data for common high level driver.
+    state                  : USBS_STATE_POWERED,
+    enumeration_data       : (usbs_enumeration_data*) 0,
+    start_fn               : &stm32_usb_start,
+    poll_fn                : &stm32_usb_poll,
+    interrupt_vector       : CYGNUM_HAL_INTERRUPT_USB_LP,
+    control_buffer         : { 0, 0, 0, 0, 0, 0, 0, 0 },
+    state_change_fn        : 0,
+    state_change_data      : 0,
+    standard_control_fn    : 0,
+    standard_control_data  : 0,
+    class_control_fn       : 0,
+    class_control_data     : 0,
+    vendor_control_fn      : 0,
+    vendor_control_data    : 0,
+    reserved_control_fn    : 0,
+    reserved_control_data  : 0,
+    buffer                 : 0,
+    buffer_size            : 0,
+    fill_buffer_fn         : 0,
+    fill_data              : 0,
+    fill_index             : 0,
+    complete_fn            : 0,
+    get_rxep_fn            : &stm32_usb_get_rxep,
+    get_txep_fn            : &stm32_usb_get_txep,
+  },
+  { // Initialise transmit transaction data.
+    state                  : TXTR_STATE_RESET,
+    flags                  : TXTR_FLAGS_ZLPKT,
+    status                 : ENOERR,
+    ep_num                 : 0,
+  },
+  { // Initialise receive transaction data.
+    state                  : RXTR_STATE_RESET,
+    flags                  : RXTR_FLAGS_ZLPKT,
+    status                 : ENOERR,
+    ep_num                 : 0,
+  },
+  msg_state                : CTRLEP_MSG_STATE_IDLE,
+};
+
+extern usbs_control_endpoint cyg_usbs_cortexm_stm32_ep0c __attribute__((alias ("ctrlep")));
+
+//=============================================================================
+// ISR/DSR shared data structure.  All data which is shared between ISR and
+// DSR contexts is wrapped up in this data structure to make synchronisation
+// between the two more manageable.
+//=============================================================================
+
+typedef enum {
+  ISR_FLAGS_CLEARED       = 0x00,      // No flags set.
+  ISR_FLAGS_SETUP_READY   = 0x01,      // Setup packet ready in staging buffer.
+  ISR_FLAGS_DEVICE_RESET  = 0x02,      // Device reset detected.
+} isr_flags;
+
+typedef struct isr_shared_data {
+  isr_flags               flags;       // Flags indicating events pending.
+  cyg_uint8               txtr_done;   // Flags for indicating TX complete.
+  cyg_uint8               rxtr_done;   // Flags for indicating RX complete.
+} isr_shared_data;
+
+static isr_shared_data isr_shared = {
+  flags                    : ISR_FLAGS_CLEARED,
+  txtr_done                : 0,
+  rxtr_done                : 0,
+};
+
+//=============================================================================
+// USB driver internal state variables.
+//=============================================================================
+
+// Buffer management.
+static cyg_uint16 stm32_usb_buf_offset;
+static cyg_uint16 stm32_usb_buf_sizes [USB_EPNUM];
+
+// Endpoint descriptors.
+static txep_impl  txep_list [CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM];
+static rxep_impl  rxep_list [CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM];
+static txep_impl* txep_map  [15];
+static rxep_impl* rxep_map  [15];
+
+// Interrupts and synchronisation primitives.
+static cyg_interrupt   interrupt_data;
+static cyg_handle_t    interrupt_handle;
+static cyg_uint32      interrupt_mask_count;
+
+//=============================================================================
+// Provide inlineable functions for implementing counted interrupt masking.
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Mask interrupts if not already masked.
+
+static inline void stm32_usb_request_intr_mask
+  (void)
+{
+  cyg_scheduler_lock();
+  if (interrupt_mask_count++ == 0) {
+    cyg_drv_interrupt_mask (CYGNUM_HAL_INTERRUPT_USB_LP);
+  }
+  cyg_scheduler_unlock();
+}
+
+//-----------------------------------------------------------------------------
+// Release interrupt mask.  Interrupts will be unmasked once all mask requests
+// have been released.
+
+static inline void stm32_usb_release_intr_mask
+  (void)
+{
+  cyg_scheduler_lock();
+  if (interrupt_mask_count == 0) {
+    FAIL_USB ("Interrupt mask counter decremented through 0.");
+  }
+  else if (--interrupt_mask_count == 0) {
+    cyg_drv_interrupt_unmask (CYGNUM_HAL_INTERRUPT_USB_LP);
+  }
+  cyg_scheduler_unlock();
+}
+
+//=============================================================================
+// Provide inlineable functions for setting the 'flip bit' register values.
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Set the transmit status bits to the desired value. 
+
+static inline void stm32_usb_set_txep_status
+  (cyg_uint32 ep, cyg_uint32 txep_status)
+{
+  cyg_uint32 reg_val;
+  HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (ep), reg_val);
+  reg_val &= ~((cyg_uint32) (CYGHWR_HAL_STM32_USB_EPXR_STATRX_MASK |
+    CYGHWR_HAL_STM32_USB_EPXR_DTOGTX | CYGHWR_HAL_STM32_USB_EPXR_DTOGRX)); 
+  reg_val ^= txep_status & CYGHWR_HAL_STM32_USB_EPXR_STATTX_MASK;
+  HAL_WRITE_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (ep), reg_val);
+}
+
+//-----------------------------------------------------------------------------
+// Set the receive status bits to the desired value. 
+
+static inline void stm32_usb_set_rxep_status
+  (cyg_uint32 ep, cyg_uint32 rxep_status)
+{
+  cyg_uint32 reg_val;
+  HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (ep), reg_val);
+  reg_val &= ~((cyg_uint32) (CYGHWR_HAL_STM32_USB_EPXR_STATTX_MASK |
+    CYGHWR_HAL_STM32_USB_EPXR_DTOGTX | CYGHWR_HAL_STM32_USB_EPXR_DTOGRX)); 
+  reg_val ^= rxep_status & CYGHWR_HAL_STM32_USB_EPXR_STATRX_MASK;
+  HAL_WRITE_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (ep), reg_val);
+}
+
+//-----------------------------------------------------------------------------
+// Assign conventional bits in the endpoint status registers without touching
+// the flip-bit values.
+
+static inline void stm32_usb_assign_epxr
+  (cyg_uint32 ep, cyg_uint32 epxr_val)
+{
+  epxr_val &= ~((cyg_uint32) (CYGHWR_HAL_STM32_USB_EPXR_STATTX_MASK |
+    CYGHWR_HAL_STM32_USB_EPXR_STATRX_MASK | CYGHWR_HAL_STM32_USB_EPXR_DTOGTX | 
+    CYGHWR_HAL_STM32_USB_EPXR_DTOGRX));
+  HAL_WRITE_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (ep), epxr_val);
+}
+
+//-----------------------------------------------------------------------------
+// Set specified conventional bits in the endpoint status registers.
+
+static inline void stm32_usb_set_epxr_bits
+  (cyg_uint32 ep, cyg_uint32 epxr_mask)
+{
+  cyg_uint32 reg_val;
+  HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (ep), reg_val);
+  reg_val |= epxr_mask;
+  stm32_usb_assign_epxr (ep, reg_val);
+}
+
+//-----------------------------------------------------------------------------
+// Clear specified conventional bits in the endpoint status registers.
+
+static inline void stm32_usb_clear_epxr_bits
+  (cyg_uint32 ep, cyg_uint32 epxr_mask)
+{
+  cyg_uint32 reg_val;
+  HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (ep), reg_val);
+  reg_val &= ~epxr_mask;
+  stm32_usb_assign_epxr (ep, reg_val);
+}
+
+//-----------------------------------------------------------------------------
+// Set specified toggle bits in the endpoint status registers.
+
+static inline void stm32_usb_set_epxr_toggle
+  (cyg_uint32 ep, cyg_uint32 epxr_mask)
+{
+  cyg_uint32 reg_val;
+  HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (ep), reg_val);
+  reg_val &= epxr_mask | ~((cyg_uint32) (CYGHWR_HAL_STM32_USB_EPXR_STATTX_MASK | 
+    CYGHWR_HAL_STM32_USB_EPXR_STATRX_MASK | CYGHWR_HAL_STM32_USB_EPXR_DTOGTX | 
+    CYGHWR_HAL_STM32_USB_EPXR_DTOGRX)); 
+  reg_val ^= epxr_mask;
+  HAL_WRITE_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (ep), reg_val);
+}
+
+//-----------------------------------------------------------------------------
+// Clear specified toggle bits in the endpoint status registers.
+
+static inline void stm32_usb_clear_epxr_toggle
+  (cyg_uint32 ep, cyg_uint32 epxr_mask)
+{
+  cyg_uint32 reg_val;
+  HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (ep), reg_val);
+  reg_val &= epxr_mask | ~((cyg_uint32) (CYGHWR_HAL_STM32_USB_EPXR_STATTX_MASK | 
+    CYGHWR_HAL_STM32_USB_EPXR_STATRX_MASK | CYGHWR_HAL_STM32_USB_EPXR_DTOGTX | 
+    CYGHWR_HAL_STM32_USB_EPXR_DTOGRX)); 
+  HAL_WRITE_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (ep), reg_val);
+}
+
+//-----------------------------------------------------------------------------
+// Flip specified toggle bits in the endpoint status registers.
+
+static inline void stm32_usb_flip_epxr_toggle
+  (cyg_uint32 ep, cyg_uint32 epxr_mask)
+{
+  cyg_uint32 reg_val;
+  HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (ep), reg_val);
+  reg_val &= ~((cyg_uint32) (CYGHWR_HAL_STM32_USB_EPXR_STATTX_MASK | 
+    CYGHWR_HAL_STM32_USB_EPXR_STATRX_MASK | CYGHWR_HAL_STM32_USB_EPXR_DTOGTX | 
+    CYGHWR_HAL_STM32_USB_EPXR_DTOGRX));
+  reg_val |= epxr_mask; 
+  HAL_WRITE_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (ep), reg_val);
+}
+
+//=============================================================================
+// The following set of functions provide buffer management capabilities for
+// allocating and then accessing USB buffers in the dual-port buffer RAM.
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Get the allocated buffer size for a specified endpoint.
+
+static inline cyg_uint32 stm32_usb_buf_get_size
+  (cyg_uint32 ep)
+{
+  return (stm32_usb_buf_sizes[ep]);
+}
+
+//-----------------------------------------------------------------------------
+// Add a new set of endpoint buffers for the specified endpoint.
+
+static cyg_bool stm32_usb_buf_add_ep
+  (cyg_uint32 ep, cyg_uint32 ep_buf_size, cyg_bool is_tx, cyg_bool is_rx, cyg_bool is_db)
+{
+  cyg_uint32 alloc_size;
+  cyg_uint32 rx_blocks;
+
+  // Check for valid configuration.
+  if ((is_db && is_tx && is_rx) || !(is_tx || is_rx)) {
+    FAIL_USB ("Invalid buffer configuration.");
+    goto failed;
+  }
+
+  // Round up the allocation size so that it matches a valid RX block size.
+  alloc_size = (ep_buf_size & 1) ? ep_buf_size + 1 : ep_buf_size;
+  if ((alloc_size > 62) && (alloc_size & 31)) {
+    alloc_size &= ~31;
+    alloc_size += 32;
+  }
+
+  // Check to see if there is enough RAM available.
+  if (is_db || (is_tx && is_rx)) {
+    if (stm32_usb_buf_offset + 2 * alloc_size > USB_RAM_SIZE) {
+      FAIL_USB ("Insufficient endpoint RAM for configuration.");
+      goto failed;
+    }
+  }
+  else {  
+    if (stm32_usb_buf_offset + alloc_size > USB_RAM_SIZE) {
+      FAIL_USB ("Insufficient endpoint RAM for configuration.");
+      goto failed;
+    }
+  }
+
+  // Calculate the blocks (size + num) field for the receive count register.
+  rx_blocks = (alloc_size <= 62) ? (alloc_size / 2) : (31 + alloc_size / 32);
+  stm32_usb_buf_sizes[ep] = (cyg_uint16) ep_buf_size;
+ 
+  // Program up the pseudo-registers for double buffered transmit.
+  if (is_db && is_tx) {
+    HAL_WRITE_UINT32 (USB_RAM_BASE + USB_RAM_DB_TXADDR (ep, 0), stm32_usb_buf_offset);
+    HAL_WRITE_UINT32 (USB_RAM_BASE + USB_RAM_DB_TXCOUNT (ep, 0), 0);
+    stm32_usb_buf_offset += (cyg_uint16) alloc_size;
+    HAL_WRITE_UINT32 (USB_RAM_BASE + USB_RAM_DB_TXADDR (ep, 1), stm32_usb_buf_offset);
+    HAL_WRITE_UINT32 (USB_RAM_BASE + USB_RAM_DB_TXCOUNT (ep, 1), 0);
+    stm32_usb_buf_offset += (cyg_uint16) alloc_size;
+  }
+
+  // Program up the pseudo-registers for double buffered receive.
+  else if (is_db) {
+    HAL_WRITE_UINT32 (USB_RAM_BASE + USB_RAM_DB_RXADDR (ep, 0), stm32_usb_buf_offset);
+    HAL_WRITE_UINT32 (USB_RAM_BASE + USB_RAM_DB_RXCOUNT (ep, 0), USB_RAM_XX_RXCOUNT_BLOCKS (rx_blocks));
+    stm32_usb_buf_offset += (cyg_uint16) alloc_size;
+    HAL_WRITE_UINT32 (USB_RAM_BASE + USB_RAM_DB_RXADDR (ep, 1), stm32_usb_buf_offset);
+    HAL_WRITE_UINT32 (USB_RAM_BASE + USB_RAM_DB_RXCOUNT (ep, 1), USB_RAM_XX_RXCOUNT_BLOCKS (rx_blocks));
+    stm32_usb_buf_offset += (cyg_uint16) alloc_size;
+  }
+
+  // Program up the pseudo-registers for single buffered transmit/receive.
+  else {
+    if (is_tx) {
+      HAL_WRITE_UINT32 (USB_RAM_BASE + USB_RAM_SB_TXADDR (ep), stm32_usb_buf_offset);
+      HAL_WRITE_UINT32 (USB_RAM_BASE + USB_RAM_SB_TXCOUNT (ep), 0);
+      stm32_usb_buf_offset += (cyg_uint16) alloc_size;
+    }
+    if (is_rx) {
+      HAL_WRITE_UINT32 (USB_RAM_BASE + USB_RAM_SB_RXADDR (ep), stm32_usb_buf_offset);
+      HAL_WRITE_UINT32 (USB_RAM_BASE + USB_RAM_SB_RXCOUNT (ep), USB_RAM_XX_RXCOUNT_BLOCKS (rx_blocks));
+      stm32_usb_buf_offset += (cyg_uint16) alloc_size;
+    }
+  }
+
+  // Exit on success or failure.
+  return true;
+failed :
+  return false;
+}
+
+//-----------------------------------------------------------------------------
+// Clear the buffer RAM layout for non-control endpoints, prior to setting a
+// new configuration.
+
+static inline void stm32_usb_buf_clear_config
+  (void)
+{
+  cyg_uint32 i;
+
+  // Clear buffer size table for non-control endpoints.
+  for (i = 1; i < USB_EPNUM; i++)
+    stm32_usb_buf_sizes[i] = 0;    
+
+  // Update the free pointer to point to the end of the control endpoint buffers.
+  stm32_usb_buf_offset = 8 * USB_EPNUM + 2 * stm32_usb_buf_sizes[0];
+}
+
+//-----------------------------------------------------------------------------
+// Reset the buffer RAM layout, preallocating the requested buffer area for
+// control endpoint 0.
+
+static inline cyg_bool stm32_usb_buf_reset_ep0
+  (cyg_uint32 ep0_buf_size)
+{
+  cyg_uint32 i;
+
+  // The buffer descriptor table is placed at the start of the dual-port RAM.
+  HAL_WRITE_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_BTABLE, 0);
+  stm32_usb_buf_offset = 8 * USB_EPNUM;
+
+  // Clear buffer size table prior to adding endpoint 0.  A zero in this table
+  // essentially prevents any host-side access to a given endpoint buffer.
+  for (i = 0; i < USB_EPNUM; i++)
+    stm32_usb_buf_sizes[i] = 0;    
+  return stm32_usb_buf_add_ep (0, ep0_buf_size, true, true, false);
+}
+
+//-----------------------------------------------------------------------------
+// Copy data from user memory to a specified USB buffer (double buffered).
+// Returns the number of bytes transferred, which is capped at the buffer
+// size.
+
+static cyg_uint32 __attribute__((hot)) stm32_usb_copy_to_dbuf
+  (const cyg_uint8* src, cyg_uint32 size, cyg_uint32 ep, cyg_uint32 buf)
+{
+  cyg_uint32     data, i;
+  cyg_haladdress waddr;
+
+  // Truncate the size parameter to the buffer length.
+  if (size > stm32_usb_buf_sizes[ep])
+    size = stm32_usb_buf_sizes[ep];
+
+  // Get the offset of the start of the buffer from the buffer tables
+  // and convert it into a host-side address.
+  HAL_READ_UINT32 (USB_RAM_BASE + USB_RAM_DB_TXADDR (ep, buf), data);
+  waddr = USB_RAM_BASE + data * 2;
+
+  // Copy over the data, remembering to skip the half-word gaps.  If the size
+  // is not an integer number of half-words, we stick garbage in the last byte.
+  for (i = (size + 1) >> 1; i != 0; i--) {
+    data = *(src++);
+    data |= ((cyg_uint32) *(src++)) << 8;
+    HAL_WRITE_UINT32 (waddr, data);
+    waddr += 4;
+  }
+
+  // Update the buffer count field and return the buffer size.
+  HAL_WRITE_UINT32 (USB_RAM_BASE + USB_RAM_DB_TXCOUNT (ep, buf), size);
+  return size;
+} 
+
+//-----------------------------------------------------------------------------
+// Copy data from user memory to transmit buffer (single buffered endpoint).
+// Returns the number of bytes transferred, which is capped at the buffer
+// size.
+
+static inline cyg_uint32 stm32_usb_copy_to_sbuf
+  (const cyg_uint8* src, cyg_uint32 size, cyg_uint32 ep)
+{
+  return stm32_usb_copy_to_dbuf (src, size, ep, 0);
+}
+
+//-----------------------------------------------------------------------------
+// Copy data from a specified USB buffer to user memory (double buffered).
+// Returns the number of bytes held by the buffer.  Will not write beyond the
+// end of the user buffer, but if the user buffer is not large enough to hold 
+// the received data (returned value > size) this implies an error condition.
+
+static cyg_uint32 __attribute__((hot)) stm32_usb_copy_from_dbuf
+  (cyg_uint8* dest, cyg_uint32 size, cyg_uint32 ep, cyg_uint32 buf)
+{
+  cyg_uint32     data, bufsize, i;
+  cyg_haladdress raddr;
+
+  // Get the receive buffer size.
+  HAL_READ_UINT32 (USB_RAM_BASE + USB_RAM_DB_RXCOUNT (ep, buf), bufsize);
+  bufsize &= USB_RAM_XX_RXCOUNT_COUNT_MASK;
+
+  // Determine the actual amount of data to transfer.
+  if (bufsize > size)
+    FAIL_USB ("Receive buffer overflow detected.");
+  else
+    size = bufsize;
+
+  // Get the offset of the start of the buffer from the buffer tables
+  // and convert it into a host-side address.
+  HAL_READ_UINT32 (USB_RAM_BASE + USB_RAM_DB_RXADDR (ep, buf), data);
+  raddr = USB_RAM_BASE + data * 2;
+
+  // Copy over the half-word aligned data.
+  for (i = size; i > 1; i -= 2) {
+    HAL_READ_UINT32 (raddr, data);
+    *(dest++) = (cyg_uint8) data;
+    *(dest++) = (cyg_uint8) (data >> 8);
+    raddr += 4;
+  }
+
+  // Copy over the trailing byte if present.
+  if (i) {
+    HAL_READ_UINT32 (raddr, data);
+    *(dest) = (cyg_uint8) data;
+  }
+  return bufsize;
+}
+
+//-----------------------------------------------------------------------------
+// Copy data from a receive buffer to user memory (single buffered endpoint).
+// Returns the number of bytes held by the buffer.  Will not write beyond the
+// end of the user buffer, but if the user buffer is not large enough to hold 
+// the received data (returned value > size) this implies an error condition.
+
+static inline cyg_uint32 stm32_usb_copy_from_sbuf
+  (cyg_uint8* dest, cyg_uint32 size, cyg_uint32 ep)
+{
+  return stm32_usb_copy_from_dbuf (dest, size, ep, 1);
+}
+
+//=============================================================================
+// The following set of functions provide support for managing multi-packet
+// USB transactions.
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Implement transmit transaction state machine.  This is called on transaction
+// start and then on all applicable interrupt events in order to progress the 
+// transmit transaction.
+
+static cyg_bool stm32_usb_txtr_run
+  (txtr_impl* txtr)
+{
+  cyg_bool completed = false;
+  cyg_uint32 tx_bytes_req, tx_bytes_sent, buf_sel, reg_val;
+
+  switch (txtr->state) {
+
+    // Send next packet (single buffer transfers).
+    case TXTR_STATE_SB_NEXT_PKT:
+      tx_bytes_req = txtr->buf_size - txtr->bytes_sent;
+      tx_bytes_sent = stm32_usb_copy_to_sbuf (txtr->buf_ptr, tx_bytes_req, txtr->ep_num);
+      txtr->buf_ptr += tx_bytes_sent;
+      txtr->bytes_sent += tx_bytes_sent;
+
+      // All bytes sent - see if we need a zero length termination packet.
+      if (txtr->bytes_sent == txtr->buf_size) {
+        if ((tx_bytes_sent == stm32_usb_buf_get_size (txtr->ep_num)) && (txtr->flags & TXTR_FLAGS_ZLPKT))
+          txtr->state = TXTR_STATE_SB_ZERO_PKT;
+        else
+          txtr->state = TXTR_STATE_SB_DONE;
+      }
+
+      // Set buffer valid via the endpoint control register.
+      stm32_usb_set_txep_status (txtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATTX_VALID);
+      break;
+
+    // Send zero length termination packet (single buffer transfers).
+    case TXTR_STATE_SB_ZERO_PKT :
+      txtr->state = TXTR_STATE_SB_DONE;
+      stm32_usb_copy_to_sbuf (txtr->buf_ptr, 0, txtr->ep_num);
+      stm32_usb_set_txep_status (txtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATTX_VALID);
+      break;
+
+    // Complete transaction (single buffer transfers).
+    case TXTR_STATE_SB_DONE :
+      txtr->state = TXTR_STATE_IDLE;
+      completed = true;
+      break;
+
+    // Sets up the first queued packet.  Start by clearing the data toggle
+    // bits and leaving the endpoint in valid state.
+    case TXTR_STATE_DB_FIRST_PKT :
+      HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (txtr->ep_num), reg_val);
+      buf_sel = (reg_val & CYGHWR_HAL_STM32_USB_EPXR_DTOGTX) ? 1 : 0;  
+      goto queue_packet;
+
+    // Commit the next queued packet for transmission then queue the next 
+    // packet in the CPU-side buffer.
+    case TXTR_STATE_DB_NEXT_PKT :
+      HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (txtr->ep_num), reg_val);
+      buf_sel = (reg_val & CYGHWR_HAL_STM32_USB_EPXR_DTOGTX) ? 0 : 1;  
+      stm32_usb_flip_epxr_toggle (txtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_SWBUFTX);
+      stm32_usb_set_txep_status (txtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATTX_VALID);
+
+    // This section is common to both DB_NEXT_PKT and DB_FIRST_PKT states.  
+    // However, a straight fallthrough won't work and we have to resort to goto.
+    queue_packet:
+      tx_bytes_req = txtr->buf_size - txtr->bytes_sent;
+      tx_bytes_sent = stm32_usb_copy_to_dbuf (txtr->buf_ptr, tx_bytes_req, txtr->ep_num, buf_sel);
+      txtr->buf_ptr += tx_bytes_sent;
+      txtr->bytes_sent += tx_bytes_sent;
+
+      // All bytes queued - see if we need a zero length termination packet.
+      if (txtr->bytes_sent == txtr->buf_size) {
+        if ((tx_bytes_sent == stm32_usb_buf_get_size (txtr->ep_num)) && (txtr->flags & TXTR_FLAGS_ZLPKT))
+          txtr->state = TXTR_STATE_DB_ZERO_PKT;
+        else
+          txtr->state = TXTR_STATE_DB_LAST_PKT;
+      }
+
+      // More data remaining - send next packet.
+      else {
+        txtr->state = TXTR_STATE_DB_NEXT_PKT;
+      }
+      break;
+
+    // Commit the next queued packet for transmission then queue a
+    // zero length packet in the CPU-side buffer.
+    case TXTR_STATE_DB_ZERO_PKT :
+      HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (txtr->ep_num), reg_val);
+      buf_sel = (reg_val & CYGHWR_HAL_STM32_USB_EPXR_DTOGTX) ? 0 : 1;  
+      stm32_usb_flip_epxr_toggle (txtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_SWBUFTX);
+      stm32_usb_set_txep_status (txtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATTX_VALID);
+      stm32_usb_copy_to_dbuf (txtr->buf_ptr, 0, txtr->ep_num, buf_sel);
+      txtr->state = TXTR_STATE_DB_LAST_PKT;
+      break;
+
+    // Commit the final queued packet for transmission.
+    case TXTR_STATE_DB_LAST_PKT :
+      stm32_usb_flip_epxr_toggle (txtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_SWBUFTX);
+      stm32_usb_set_txep_status (txtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATTX_VALID);
+      txtr->state = TXTR_STATE_DB_DONE;
+      break;
+
+    // Complete transaction (double buffer transfers).
+    case TXTR_STATE_DB_DONE :
+      stm32_usb_set_txep_status (txtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATTX_NAK);
+      txtr->state = TXTR_STATE_IDLE;
+      completed = true;
+      break;
+
+    // Unknown state - driver error.
+    default :
+      FAIL_USB ("TX transaction in invalid state.");
+      txtr->state = TXTR_STATE_IDLE;
+      txtr->status = EIO;
+      completed = true;
+      break;
+  }
+  return completed;
+}
+
+//-----------------------------------------------------------------------------
+// Initiate a data transmit transaction.  This sets up a new transaction,
+// priming the buffers and then kicking the state machine for the first time.
+
+static cyg_bool stm32_usb_txtr_start
+  (txtr_impl* txtr, cyg_bool int_safe) 
+{
+  cyg_bool completed;
+
+  // Critical section - avoid races with the ISR.
+  if (!int_safe) stm32_usb_request_intr_mask ();
+
+  // Set up double buffer transactions.  We need to prime the buffers which
+  // requires two ticks of the state machine.
+  if (txtr->flags & TXTR_FLAGS_DBUF) {
+    txtr->status = ENOERR;
+    txtr->bytes_sent = 0;
+    txtr->state = TXTR_STATE_DB_FIRST_PKT;
+    stm32_usb_txtr_run (txtr);
+  }
+
+  // Set up single buffer transactions.
+  else {
+    txtr->status = ENOERR;
+    txtr->bytes_sent = 0;
+    txtr->state = TXTR_STATE_SB_NEXT_PKT;
+  }
+
+  // Run the state machine for the first step.
+  completed = stm32_usb_txtr_run (txtr);  
+
+  // Exit critical section.
+  if (!int_safe) stm32_usb_release_intr_mask ();
+  return completed;
+}
+
+//-----------------------------------------------------------------------------
+// Halt a transmit endpoint.  This places the endpoint in the stall condition 
+// and cancels any outstanding transaction, resetting the transaction state 
+// machine.
+
+static void stm32_usb_txep_halt
+  (txep_impl* txep, cyg_bool int_safe)
+{
+  cyg_bool call_completion;
+
+  // Critical section - avoid races with the ISR.
+  if (!int_safe) stm32_usb_request_intr_mask ();
+  stm32_usb_set_txep_status (txep->txtr.ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATTX_DIS);
+
+  // Reset the transaction state.
+  call_completion = ((txep->txtr.state != TXTR_STATE_IDLE) && 
+    (txep->txtr.state != TXTR_STATE_RESET)) ? true : false;
+  txep->txtr.state = TXTR_STATE_RESET;
+  txep->common.halted = true;
+  stm32_usb_clear_epxr_bits (txep->txtr.ep_num, CYGHWR_HAL_STM32_USB_EPXR_CTRTX);
+
+  // Exit critical section.
+  stm32_usb_set_txep_status (txep->txtr.ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATTX_STALL);
+  if (!int_safe) stm32_usb_release_intr_mask ();
+  
+  // Indicate error via the completion callback.
+  if (call_completion) {
+    if (txep->common.complete_fn)
+      (*txep->common.complete_fn) (txep->common.complete_data, -EIO);
+    TRACE_USB ("TX Transaction cancelled on halt.\n");
+  }
+}
+
+//-----------------------------------------------------------------------------
+// Take a transmit endpoint out of halted state.  This takes the endpoint out
+// of the halted state and resets the endpoint.  Note that according to the
+// spec, the endpoint should also be reset and the toggle bits cleared if 
+// 'clear halted' is called while in normal operation.
+
+static void stm32_usb_txep_unhalt
+  (txep_impl* txep, cyg_bool int_safe)
+{
+  cyg_bool call_completion;
+
+  // Critical section - avoid races with the ISR.
+  if (!int_safe) stm32_usb_request_intr_mask ();
+  stm32_usb_set_txep_status (txep->txtr.ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATTX_DIS);
+
+  // Reset the transaction state.
+  call_completion = ((txep->txtr.state != TXTR_STATE_IDLE) && 
+    (txep->txtr.state != TXTR_STATE_RESET)) ? true : false;
+  txep->txtr.state = TXTR_STATE_IDLE;
+  txep->common.halted = false;
+  stm32_usb_clear_epxr_bits (txep->txtr.ep_num, CYGHWR_HAL_STM32_USB_EPXR_CTRTX);
+  stm32_usb_clear_epxr_toggle (txep->txtr.ep_num, 
+    CYGHWR_HAL_STM32_USB_EPXR_DTOGTX | CYGHWR_HAL_STM32_USB_EPXR_SWBUFTX);
+
+  // Exit critical section.
+  stm32_usb_set_txep_status (txep->txtr.ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATTX_NAK);
+  if (!int_safe) stm32_usb_release_intr_mask ();
+  
+  // Indicate error via the completion callback.
+  if (call_completion) {
+    if (txep->common.complete_fn)
+      (*txep->common.complete_fn) (txep->common.complete_data, -EIO);
+    TRACE_USB ("TX Transaction cancelled on resume.\n");
+  }
+}
+
+//-----------------------------------------------------------------------------
+// Implement receive transaction state machine.  This is called on all
+// applicable interrupt events in order to progress the transaction.
+
+static cyg_bool stm32_usb_rxtr_run
+  (rxtr_impl* rxtr)
+{
+  cyg_bool completed = false;
+  cyg_uint32 rx_bytes_req, rx_bytes_rcvd, buf_sel, reg_val;
+
+  switch (rxtr->state) {
+
+    // Receive new packet (single buffer transfers).
+    case RXTR_STATE_SB_NEXT_PKT:
+      rx_bytes_req = rxtr->buf_size - rxtr->bytes_rcvd;
+      rx_bytes_rcvd = stm32_usb_copy_from_sbuf (rxtr->buf_ptr, rx_bytes_req, rxtr->ep_num);
+
+      // Check for buffer overflow condition before updating buffer pointer.
+      if (rx_bytes_rcvd > rx_bytes_req) {
+        FAIL_USB ("RX message exceeds allocated buffer size.");
+        rxtr->state = RXTR_STATE_IDLE;
+        rxtr->status = EMSGSIZE;
+        completed = true;
+        break;
+      }
+      rxtr->buf_ptr += rx_bytes_rcvd;
+      rxtr->bytes_rcvd += rx_bytes_rcvd;
+
+      // Short packet received - transaction complete.
+      if (rx_bytes_rcvd < stm32_usb_buf_get_size (rxtr->ep_num)) {
+        rxtr->state = RXTR_STATE_IDLE;
+        completed = true;
+        break;
+      }
+
+      // All bytes received - see if we need a zero length termination packet.
+      // Note that zero length packets can be treated as normal short packets
+      // here, so an additional state transition is not required.
+      if (rxtr->bytes_rcvd == rxtr->buf_size) {
+        if (!((rx_bytes_rcvd == stm32_usb_buf_get_size (rxtr->ep_num)) && (rxtr->flags & RXTR_FLAGS_ZLPKT))) {
+          rxtr->state = RXTR_STATE_IDLE;
+          completed = true;
+          break;
+        }
+      }
+
+      // Set buffer clear via the endpoint control register.
+      stm32_usb_set_rxep_status (rxtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATRX_VALID);
+      break;
+
+    // Receive new packet (double buffer transfers).  Start by switching buffers.
+    case RXTR_STATE_DB_NEXT_PKT:
+      HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (rxtr->ep_num), reg_val);
+      buf_sel = (reg_val & CYGHWR_HAL_STM32_USB_EPXR_DTOGRX) ? 0 : 1;  
+
+      // Get the receive buffer size.
+      HAL_READ_UINT32 (USB_RAM_BASE + USB_RAM_DB_RXCOUNT (rxtr->ep_num, buf_sel), rx_bytes_rcvd);
+      rx_bytes_req = rxtr->buf_size - rxtr->bytes_rcvd;
+      rx_bytes_rcvd &= USB_RAM_XX_RXCOUNT_COUNT_MASK;
+ 
+      // Check for buffer overflow condition before updating buffer pointer.
+      if (rx_bytes_rcvd > rx_bytes_req) {
+        FAIL_USB ("RX message exceeds allocated buffer size.");
+        rxtr->state = RXTR_STATE_IDLE;
+        rxtr->status = EMSGSIZE;
+        completed = true;
+        break;
+      }
+
+      // Short packet received - transaction complete.
+      if (rx_bytes_rcvd < stm32_usb_buf_get_size (rxtr->ep_num)) {
+        rxtr->state = RXTR_STATE_IDLE;
+        completed = true;
+      }
+
+      // All bytes received - see if we need a zero length termination packet.
+      // Note that zero length packets can be treated as normal short packets
+      // here, so an additional state transition is not required.
+      if (rxtr->bytes_rcvd + rx_bytes_rcvd == rxtr->buf_size) {
+        if (!((rx_bytes_rcvd == stm32_usb_buf_get_size (rxtr->ep_num)) && (rxtr->flags & RXTR_FLAGS_ZLPKT))) {
+          rxtr->state = RXTR_STATE_IDLE;
+          completed = true;
+        }
+      }
+
+      // Only enable the next receive buffer if this is not the last packet.
+      if (!completed) {
+        stm32_usb_flip_epxr_toggle (rxtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_SWBUFRX);
+        stm32_usb_set_rxep_status (rxtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATRX_VALID);
+      }
+
+      // Set the endpoint to NAK on completion.
+      else {
+        stm32_usb_set_rxep_status (rxtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATRX_NAK);
+      }
+
+      // Copy the received data to our local buffer.
+      rx_bytes_rcvd = stm32_usb_copy_from_dbuf (rxtr->buf_ptr, rx_bytes_req, rxtr->ep_num, buf_sel);
+      rxtr->bytes_rcvd += rx_bytes_rcvd;
+      rxtr->buf_ptr += rx_bytes_rcvd;
+      break;
+
+    // Unknown state - driver error.
+    default :
+      FAIL_USB ("RX transaction in invalid state.");
+      rxtr->state = RXTR_STATE_IDLE;
+      rxtr->status = EIO;
+      completed = true;
+      break;
+
+  }
+  return completed;
+}
+
+//-----------------------------------------------------------------------------
+// Initiate a data receive transaction.  This sets up a new transaction,
+// enabling the receive buffers and then waiting for incoming data.
+
+static cyg_bool stm32_usb_rxtr_start
+  (rxtr_impl* rxtr, cyg_bool int_safe)
+{
+  // Critical section - avoid races with the ISR.
+  if (!int_safe) stm32_usb_request_intr_mask ();
+
+  // Set up double buffer transactions.
+  if (rxtr->flags & RXTR_FLAGS_DBUF) {
+    rxtr->state = RXTR_STATE_DB_NEXT_PKT;
+    rxtr->status = ENOERR;
+    rxtr->bytes_rcvd = 0;
+    stm32_usb_flip_epxr_toggle (rxtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_SWBUFRX);
+    stm32_usb_set_rxep_status (rxtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATRX_VALID);
+  }
+
+  // Set up single buffer transactions.
+  else {
+    rxtr->state = RXTR_STATE_SB_NEXT_PKT;
+    rxtr->status = ENOERR;
+    rxtr->bytes_rcvd = 0;
+    stm32_usb_set_rxep_status (rxtr->ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATRX_VALID);
+  }
+
+  // Exit critical section.
+  if (!int_safe) stm32_usb_release_intr_mask ();
+  return false;
+}
+
+//-----------------------------------------------------------------------------
+// Halt a receive endpoint.  This places the endpoint in the stall condition 
+// and cancels any outstanding transaction, resetting the transaction state 
+// machine.
+
+static void stm32_usb_rxep_halt
+  (rxep_impl* rxep, cyg_bool int_safe)
+{
+  cyg_bool call_completion;
+
+  // Critical section - avoid races with the ISR.
+  if (!int_safe) stm32_usb_request_intr_mask ();
+  stm32_usb_set_rxep_status (rxep->rxtr.ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATRX_DIS);
+
+  // Reset the transaction state.
+  call_completion = ((rxep->rxtr.state != RXTR_STATE_IDLE) && 
+    (rxep->rxtr.state != RXTR_STATE_RESET)) ? true : false;
+  rxep->rxtr.state = RXTR_STATE_RESET;
+  rxep->common.halted = true;
+  stm32_usb_clear_epxr_bits (rxep->rxtr.ep_num, CYGHWR_HAL_STM32_USB_EPXR_CTRRX);
+
+  // Exit critical section.
+  stm32_usb_set_rxep_status (rxep->rxtr.ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATRX_STALL);
+  if (!int_safe) stm32_usb_release_intr_mask ();
+  
+  // Indicate error via the completion callback.
+  if (call_completion) {
+    if (rxep->common.complete_fn)
+      (*rxep->common.complete_fn) (rxep->common.complete_data, -EIO);
+    TRACE_USB ("RX Transaction cancelled on halt.\n");
+  }
+}
+
+//-----------------------------------------------------------------------------
+// Take a receive endpoint out of halted state.  This takes the endpoint out
+// of the halted state and resets the endpoint.  Note that according to the
+// spec, the endpoint should also be reset and the toggle bits cleared if 
+// 'clear halted' is called while in normal operation.
+
+static void stm32_usb_rxep_unhalt
+  (rxep_impl* rxep, cyg_bool int_safe)
+{
+  cyg_bool call_completion;
+
+  // Critical section - avoid races with the ISR.
+  if (!int_safe) stm32_usb_request_intr_mask ();
+  stm32_usb_set_rxep_status (rxep->rxtr.ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATRX_DIS);
+
+  // Reset the transaction state.
+  call_completion = ((rxep->rxtr.state != RXTR_STATE_IDLE) && 
+    (rxep->rxtr.state != RXTR_STATE_RESET)) ? true : false;
+  rxep->rxtr.state = RXTR_STATE_IDLE;
+  rxep->common.halted = false;
+  stm32_usb_clear_epxr_bits (rxep->rxtr.ep_num, CYGHWR_HAL_STM32_USB_EPXR_CTRRX);
+  stm32_usb_clear_epxr_toggle (rxep->rxtr.ep_num, 
+    CYGHWR_HAL_STM32_USB_EPXR_DTOGRX | CYGHWR_HAL_STM32_USB_EPXR_SWBUFRX);
+
+  // Exit critical section.
+  stm32_usb_set_rxep_status (rxep->rxtr.ep_num, CYGHWR_HAL_STM32_USB_EPXR_STATRX_NAK);
+  if (!int_safe) stm32_usb_release_intr_mask ();
+  
+  // Indicate error via the completion callback.
+  if (call_completion) {
+    if (rxep->common.complete_fn)
+      (*rxep->common.complete_fn) (rxep->common.complete_data, -EIO);
+    TRACE_USB ("RX Transaction cancelled on resume.\n");
+  }
+}
+
+//=============================================================================
+// Implement control endpoint protocol handling.
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Forward endpoint 0 state change notifications.
+
+static void stm32_usb_ctrl_update_state
+  (int new_state, usbs_state_change state_change)
+{
+  int old_state = ctrlep.common.state;
+  ctrlep.common.state = new_state;
+  if (ctrlep.common.state_change_fn)
+    (*ctrlep.common.state_change_fn) (&ctrlep.common, 
+      ctrlep.common.state_change_data, state_change, old_state);
+}
+
+// --------------------------------------------------------------------------
+// Called on completion of an endpoint 0 control request transaction.
+
+static void stm32_usb_ctrl_completed 
+  (int status)
+{
+  ctrlep.msg_state = CTRLEP_MSG_STATE_IDLE;
+  if (ctrlep.common.complete_fn)
+    (*ctrlep.common.complete_fn) (&cyg_usbs_cortexm_stm32_ep0c, -status);
+  if (status != 0)
+    TRACE_USB ("Transaction failed (status %d).\n", status);
+}
+
+//-----------------------------------------------------------------------------
+// Clear endpoint configuration.  This disables all non-control endpoints,
+// resetting their state.
+
+static void stm32_usb_ctrl_clear_config
+  (void)
+{
+  cyg_uint32 i;
+  txep_impl* txep = txep_list;
+  rxep_impl* rxep = rxep_list;
+
+  // Disable all non-control endpoints, clearing any outstanding interrupts.
+  // This also ensures that the toggle bits are reset to 0.
+  for (i = 1; i < 8; i++) {
+    stm32_usb_set_txep_status (i, CYGHWR_HAL_STM32_USB_EPXR_STATTX_DIS);
+    stm32_usb_set_rxep_status (i, CYGHWR_HAL_STM32_USB_EPXR_STATRX_DIS);
+    stm32_usb_clear_epxr_toggle (i, 
+      CYGHWR_HAL_STM32_USB_EPXR_DTOGTX | CYGHWR_HAL_STM32_USB_EPXR_DTOGRX);
+    stm32_usb_clear_epxr_bits (i, 0xFFFF);
+  }
+
+  // Reset the transaction state for all transmit endpoints.
+  for (i = 0; i < CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM; i++) {
+    txep->common.halted = true;
+    txep->txtr.state = TXTR_STATE_RESET;
+    txep++;
+  }
+
+  // Reset the transaction state for all receive endpoints.
+  for (i = 0; i < CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM; i++) {
+    rxep->common.halted = true;
+    rxep->rxtr.state = RXTR_STATE_RESET;
+    rxep++;
+  }
+
+  // Clear the logical to physical endpoint mappings.
+  for (i = 0; i < 15; i++) {
+    txep_map [i] = NULL;
+    rxep_map [i] = NULL;
+  }
+
+  // Clear buffer RAM for non-control endpoints (preseverves endpoint 0).
+  stm32_usb_buf_clear_config ();
+}
+
+//-----------------------------------------------------------------------------
+// Reset the control endpoint - placing the device in the 'default' state.
+
+static void stm32_usb_ctrl_reset
+  (void)
+{
+  // Re-enable the device on address 0 only.
+  HAL_WRITE_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_DADDR, CYGHWR_HAL_STM32_USB_DADDR_EF);
+  
+  // Reset the buffer RAM layout, allocating only the endpoint 0 buffers.
+  stm32_usb_buf_reset_ep0 (ctrlep.common.enumeration_data->device.max_packet_size);
+
+  // Clear the previous endpoint configuration.
+  stm32_usb_ctrl_clear_config ();
+
+  // Ensure endpoint 0 is assigned the correct endpoint type.
+  stm32_usb_assign_epxr (0, CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_CTRL);
+
+  // Reset endpoint 0, leaving it configured for valid incoming packets.
+  stm32_usb_set_txep_status (0, CYGHWR_HAL_STM32_USB_EPXR_STATTX_NAK);
+  stm32_usb_set_rxep_status (0, CYGHWR_HAL_STM32_USB_EPXR_STATRX_VALID);
+  stm32_usb_clear_epxr_toggle (0, 
+    CYGHWR_HAL_STM32_USB_EPXR_DTOGTX | CYGHWR_HAL_STM32_USB_EPXR_DTOGRX);
+  stm32_usb_clear_epxr_bits (0, 
+    CYGHWR_HAL_STM32_USB_EPXR_CTRTX | CYGHWR_HAL_STM32_USB_EPXR_CTRRX);
+  
+  // Enter default state.
+  stm32_usb_ctrl_update_state (USBS_STATE_DEFAULT, USBS_STATE_CHANGE_RESET);
+}
+
+//-----------------------------------------------------------------------------
+// Fill the transmit control message buffer.  This function is used to
+// assemble control response messages for transmission to the host.
+
+static cyg_uint32 stm32_usb_ctrl_fill_msg_buffer 
+  (void)
+{
+  cyg_uint32 msg_length = 0;
+
+  // Deal with commands which place their data directly into the staging buffer.
+  if (ctrlep.common.buffer == ctrlep_msg_buffer) {
+    msg_length = ctrlep.common.buffer_size;
+  }
+
+  // Loop until there are no more message segments to append.  For buffer
+  // overflows, debug builds will assert and production builds will send a 
+  // truncated message.
+  else do {
+    if (ctrlep.common.buffer_size != 0) {
+      if (msg_length + ctrlep.common.buffer_size <= CYGNUM_DEVS_USB_CORTEXM_STM32_EPO_MAX_MSG_SIZE) {
+        memcpy (ctrlep_msg_buffer + msg_length, ctrlep.common.buffer, ctrlep.common.buffer_size);
+        msg_length += ctrlep.common.buffer_size;
+      }
+      else {
+        FAIL_USB ("Endpoint 0 transmit buffer overflow.");
+        break;
+      }
+
+      // Get the next message segment, if available.
+      if (ctrlep.common.fill_buffer_fn)
+        (*ctrlep.common.fill_buffer_fn) (&cyg_usbs_cortexm_stm32_ep0c);
+    }
+  } while (ctrlep.common.fill_buffer_fn);
+  
+  return msg_length;
+}
+
+//-----------------------------------------------------------------------------
+// Handle set configuration setup packets.  This is implemented in the low
+// level driver because this is the point at which we need to configure the
+// endpoint RAM and realise the endpoints.  It 'falls through' to the high
+// level handlers so that they can deal with notifying the application.
+// Note: Only a single (default) interface is supported per configuration.
+
+static usbs_control_return stm32_usb_ctrl_set_config
+  (cyg_uint32 config_id)
+{
+  cyg_uint32 i, j;  
+  cyg_uint32 start_interface, start_endpoint, num_endpoints;
+  cyg_uint32 total_interfaces, total_endpoints;
+  cyg_uint32 txep_count = 0;
+  cyg_uint32 rxep_count = 0;
+  cyg_bool   alloc_ok;
+  const usb_configuration_descriptor* configurations;
+  const usb_interface_descriptor*     interfaces;
+  const usb_endpoint_descriptor*      endpoints;
+
+  // Check for valid config.
+  if ((config_id <= 0) || 
+    (config_id > ctrlep.common.enumeration_data->device.number_configurations))
+    return USBS_CONTROL_RETURN_UNKNOWN;
+
+  // Clear the previous endpoint configuration.
+  stm32_usb_ctrl_clear_config ();
+
+  // Get the base pointers for the descriptor tables.
+  configurations = ctrlep.common.enumeration_data->configurations;
+  interfaces     = ctrlep.common.enumeration_data->interfaces;
+  endpoints      = ctrlep.common.enumeration_data->endpoints;
+
+  start_interface = 0;
+  start_endpoint  = 0;
+  num_endpoints = 0;
+  total_interfaces = ctrlep.common.enumeration_data->total_number_interfaces; 
+  total_endpoints  = ctrlep.common.enumeration_data->total_number_endpoints;
+
+  // Skip over the descriptors until we get to the ones we want.
+  for (i = 0; i < (config_id-1); i++) {
+    ASSERT_USB (start_interface + configurations[i].number_interfaces <= total_interfaces,
+      "Invalid number of interfaces in enumeration data.");
+    for (j = 0; j < configurations[i].number_interfaces; j++) {
+      start_endpoint += interfaces[start_interface+j].number_endpoints;
+      ASSERT_USB (start_endpoint < total_endpoints,
+        "Invalid number of endpoints in enumeration data.");
+    }
+    start_interface += configurations[i].number_interfaces;
+  }
+
+  // Determine the number of endpoint descriptors which need to be included for
+  // all interfaces within the specified configuration.
+  ASSERT_USB (start_interface + configurations[i].number_interfaces <= total_interfaces,
+    "Invalid number of interfaces in enumeration data.");
+  for (j = 0; j < configurations[i].number_interfaces; j++) {
+    num_endpoints += interfaces[start_interface+j].number_endpoints;
+    ASSERT_USB (start_endpoint + num_endpoints <= total_endpoints,
+      "Invalid number of endpoints in enumeration data.");
+  }
+  TRACE_USB ("Found %d interfaces and %d endpoints for configuration %d.\n",
+    configurations[i].number_interfaces, num_endpoints, config_id);
+
+  // Realise the endpoints for the specified interfaces.  Set up the buffer
+  // RAM and configure them to NAK the host until the higher layer application
+  // is ready to initiate transfers.  Failures to allocate the endpoint buffers
+  // will put the endpoints in the stalled state.
+  for (i = 0; i < num_endpoints; i++) {  
+    const usb_endpoint_descriptor* ep_desc = endpoints + start_endpoint + i;
+    cyg_uint32 pkt_size = ep_desc->max_packet_lo + (((cyg_uint32) ep_desc->max_packet_hi) << 8);
+
+    // Deal with transmit (input) endpoints.
+    if (ep_desc->endpoint & USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN) {
+      if ((ep_desc->endpoint & 0x7F) < 1 || (ep_desc->endpoint & 0x7F) > 15) {
+        FAIL_USB ("Invalid endpoint ID in configuration.");
+        goto out;
+      }
+      if (txep_count >= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM) {
+        FAIL_USB ("Too many TX endpoints in configuration.");
+        goto out;
+      }
+
+      // Set up transmit (input) buffers.
+      if (ep_desc->attributes == USB_ENDPOINT_DESCRIPTOR_ATTR_BULK) {
+        alloc_ok = stm32_usb_buf_add_ep (txep_count + 1, pkt_size, true, false, true);
+        stm32_usb_set_epxr_bits (txep_count + 1, 
+          CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_BULK | CYGHWR_HAL_STM32_USB_EPXR_EPKIND);
+#ifdef CYGHWR_DEVS_USB_CORTEXM_STM32_BULK_TERM_ZLP
+        (txep_list + txep_count)->txtr.flags = TXTR_FLAGS_ZLPKT | TXTR_FLAGS_DBUF;
+#else
+        (txep_list + txep_count)->txtr.flags = TXTR_FLAGS_DBUF;
+#endif
+        TRACE_USB ("Configured BULK IN endpoint ID %d.\n", ep_desc->endpoint & 0x7F);  
+      }
+      else if (ep_desc->attributes == USB_ENDPOINT_DESCRIPTOR_ATTR_INTERRUPT) {
+        alloc_ok = stm32_usb_buf_add_ep (txep_count + 1, pkt_size, true, false, false);
+        (txep_list + txep_count)->txtr.flags = TXTR_FLAGS_NONE;
+        stm32_usb_set_epxr_bits (txep_count + 1, CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_INTR);
+        TRACE_USB ("Configured INTERRUPT IN endpoint ID %d.\n", ep_desc->endpoint & 0x7F);  
+      }
+      else {
+        FAIL_USB ("Isochronous endpoints are not currently supported.");
+        goto out;
+      }
+
+      // Enable endpoints if buffer allocation was OK - stall them otherwise.
+      if (alloc_ok) {
+        txep_map [(ep_desc->endpoint & 0x7F) - 1] = txep_list + txep_count;
+        (txep_list + txep_count)->common.halted = false;
+        (txep_list + txep_count)->txtr.state = TXTR_STATE_IDLE;
+        stm32_usb_set_txep_status (txep_count + 1, CYGHWR_HAL_STM32_USB_EPXR_STATTX_NAK);
+      }
+      else {
+        stm32_usb_set_txep_status (txep_count + 1, CYGHWR_HAL_STM32_USB_EPXR_STATTX_STALL);
+      }
+      stm32_usb_set_epxr_bits (txep_count + 1, (ep_desc->endpoint & 0xF));
+      txep_count++;
+    }
+
+    // Deal with receive (output) endpoints.
+    else {
+      if ((ep_desc->endpoint & 0x7F) < 1 || (ep_desc->endpoint & 0x7F) > 15) {
+        FAIL_USB ("Invalid endpoint ID in configuration.");
+        goto out;
+      }
+      if (rxep_count >= CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM) {
+        FAIL_USB ("Too many RX endpoints in configuration.");
+        goto out;
+      }
+
+      // Set up receive (output) buffers.
+      if (ep_desc->attributes == USB_ENDPOINT_DESCRIPTOR_ATTR_BULK) {
+        alloc_ok = stm32_usb_buf_add_ep (rxep_count + CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + 1, 
+          pkt_size, false, true, true);
+        stm32_usb_set_epxr_bits (rxep_count + CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + 1, 
+          CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_BULK | CYGHWR_HAL_STM32_USB_EPXR_EPKIND);
+#ifdef CYGHWR_DEVS_USB_CORTEXM_STM32_BULK_TERM_ZLP
+        (rxep_list + rxep_count)->rxtr.flags = RXTR_FLAGS_ZLPKT | RXTR_FLAGS_DBUF;
+#else
+        (rxep_list + rxep_count)->rxtr.flags = RXTR_FLAGS_DBUF;
+#endif
+        TRACE_USB ("Configured BULK OUT endpoint ID %d.\n", ep_desc->endpoint & 0x7F);  
+      }
+      else if (ep_desc->attributes == USB_ENDPOINT_DESCRIPTOR_ATTR_INTERRUPT) {
+        alloc_ok = stm32_usb_buf_add_ep (rxep_count + CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + 1, 
+          pkt_size, false, true, false);
+        (rxep_list + rxep_count)->rxtr.flags = RXTR_FLAGS_NONE;
+        stm32_usb_set_epxr_bits (rxep_count + CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + 1, 
+          CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_INTR);
+        TRACE_USB ("Configured INTERRUPT OUT endpoint ID %d.\n", ep_desc->endpoint & 0x7F);  
+      }
+      else {
+        FAIL_USB ("Isochronous endpoints are not currently supported.");
+        goto out;
+      }
+
+      // Enable endpoints if buffer allocation was OK - stall them otherwise.
+      if (alloc_ok) {
+        rxep_map [(ep_desc->endpoint & 0x7F) - 1] = rxep_list + rxep_count;
+        (rxep_list + rxep_count)->common.halted = false;
+        (rxep_list + rxep_count)->rxtr.state = RXTR_STATE_IDLE;
+        stm32_usb_set_rxep_status (rxep_count + CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + 1, 
+          CYGHWR_HAL_STM32_USB_EPXR_STATRX_NAK);
+      }
+      else {
+        stm32_usb_set_rxep_status (rxep_count + CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + 1, 
+          CYGHWR_HAL_STM32_USB_EPXR_STATRX_STALL);
+      }
+      stm32_usb_set_epxr_bits (rxep_count + CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + 1, 
+        (ep_desc->endpoint & 0xF));
+      rxep_count++;
+    }
+  }
+
+  // Pass up to higher layers.
+out:
+  return USBS_CONTROL_RETURN_UNKNOWN;
+}
+
+//-----------------------------------------------------------------------------
+// Handle get status setup packets.  This function places the status
+// information directly into the staging buffer.  We deal with the device
+// and endpoint status responses here.  The interface status request is
+// dealt with in the common USB slave layer.
+// TODO - should #define the return fields in usb.h.
+
+static inline usbs_control_return stm32_usb_ctrl_get_status
+  (cyg_uint32 recipient, cyg_uint32 ep_sel)
+{
+  cyg_uint8 dev_state = ctrlep.common.state & USBS_STATE_MASK;
+  usbs_control_return result = USBS_CONTROL_RETURN_UNKNOWN;
+
+  // Device status requests are valid in addressed and configured states.
+  // TODO - remote wakeup is not currently supported by this driver.
+  if (recipient == USB_DEVREQ_RECIPIENT_DEVICE) {
+    if (dev_state == USBS_STATE_ADDRESSED || dev_state == USBS_STATE_CONFIGURED) {
+#ifdef CYGHWR_DEVS_USB_CORTEXM_STM32_SELF_POWERED
+      ctrlep_msg_buffer[0] = 0x01;
+#else
+      ctrlep_msg_buffer[0] = 0x00;
+#endif
+      ctrlep_msg_buffer[1] = 0x00;
+      result = USBS_CONTROL_RETURN_HANDLED;
+    }
+  }
+
+  // Endpoint 0 status requests are valid in addressed and configured states.
+  // Endpoint 0 cannot be halted.  Endpoint number is in the lower 4 bits of the ID.
+  else if (recipient == USB_DEVREQ_RECIPIENT_ENDPOINT && (ep_sel & USB_DEVREQ_INDEX_ENDPOINT_MASK) == 0) {
+    if (dev_state == USBS_STATE_ADDRESSED || dev_state == USBS_STATE_CONFIGURED) {
+      ctrlep_msg_buffer[0] = 0x00;
+      ctrlep_msg_buffer[1] = 0x00;
+      result = USBS_CONTROL_RETURN_HANDLED;
+    }
+  }
+
+  // Non-control endpoint status requests are only valid in the configured state.
+  // Returns the halted state of the requested endpoint.
+  else if (recipient == USB_DEVREQ_RECIPIENT_ENDPOINT) {
+    if (dev_state == USBS_STATE_CONFIGURED) {
+
+      // Transmit (IN) endpoint IDs have the top bit set.
+      if ((ep_sel & USB_DEVREQ_INDEX_DIRECTION_MASK) == USB_DEVREQ_INDEX_DIRECTION_IN) {
+        ep_sel = (ep_sel & USB_DEVREQ_INDEX_ENDPOINT_MASK) - 1;
+        if (txep_map[ep_sel] != NULL) {
+          ctrlep_msg_buffer[0] = (txep_map[ep_sel]->common.halted) ? 0x01 : 0x00; 
+          ctrlep_msg_buffer[1] = 0x00;
+          result = USBS_CONTROL_RETURN_HANDLED;
+        }
+      }
+
+      // Receive (OUT) endpoint IDs have the top bit clear.
+      else {
+        ep_sel = (ep_sel & USB_DEVREQ_INDEX_ENDPOINT_MASK) - 1;
+        if (rxep_map[ep_sel] != NULL) {
+          ctrlep_msg_buffer[0] = (rxep_map[ep_sel]->common.halted) ? 0x01 : 0x00; 
+          ctrlep_msg_buffer[1] = 0x00;
+          result = USBS_CONTROL_RETURN_HANDLED;
+        }
+      }
+    }
+  }
+
+  // Point the endpoint 0 response buffer at the staging buffer.
+  if (result != USBS_CONTROL_RETURN_UNKNOWN) {
+    ctrlep.common.buffer_size = 2;
+    ctrlep.common.buffer = ctrlep_msg_buffer;
+  }
+  return result;
+}
+
+//-----------------------------------------------------------------------------
+// Handle set and clear feature commands.  Since remote wakeup support is not 
+// implemented and interface features are dealt with at a higher layer we only 
+// implement endpoint halting here.  This will only ever be called from within
+// the DSR so is interrupt safe.
+
+static usbs_control_return stm32_usb_ctrl_set_feature
+  (cyg_uint32 recipient, cyg_uint32 ep_sel, cyg_uint32 feature, cyg_bool set)
+{
+  cyg_uint8 dev_state = ctrlep.common.state & USBS_STATE_MASK;
+  usbs_control_return result = USBS_CONTROL_RETURN_UNKNOWN;
+
+  // Non-control endpoint feature control is valid in the configured state.
+  if (recipient == USB_DEVREQ_RECIPIENT_ENDPOINT && 
+    dev_state == USBS_STATE_CONFIGURED && feature == USB_DEVREQ_FEATURE_ENDPOINT_HALT) {
+
+    // Transmit (IN) endpoint IDs have the top bit set.
+    if ((ep_sel & USB_DEVREQ_INDEX_DIRECTION_MASK) == USB_DEVREQ_INDEX_DIRECTION_IN) {
+      ep_sel = (ep_sel & USB_DEVREQ_INDEX_ENDPOINT_MASK) - 1;
+      if (txep_map[ep_sel] != NULL) {
+        if (set)
+          stm32_usb_txep_halt (txep_map[ep_sel], true);
+        else
+          stm32_usb_txep_unhalt (txep_map[ep_sel], true);
+        result = USBS_CONTROL_RETURN_HANDLED;
+      }
+    }
+
+    // Receive (OUT) endpoint IDs have the top bit clear.
+    else {
+      ep_sel = (ep_sel & USB_DEVREQ_INDEX_ENDPOINT_MASK) - 1;
+      if (rxep_map[ep_sel] != NULL) {
+        if (set)
+          stm32_usb_rxep_halt (rxep_map[ep_sel], true);
+        else
+          stm32_usb_rxep_unhalt (rxep_map[ep_sel], true);
+        result = USBS_CONTROL_RETURN_HANDLED;
+      }
+    }
+  }
+  return result;
+}
+
+//-----------------------------------------------------------------------------
+// Process standard endpoint 0 setup packets.
+
+static usbs_control_return stm32_usb_ctrl_setup_standard
+  (void)
+{
+  usb_devreq* req = (usb_devreq*) &ctrlep.common.control_buffer[0];
+  usbs_control_return result = USBS_CONTROL_RETURN_UNKNOWN;
+  cyg_uint32 recipient = req->type & USB_DEVREQ_RECIPIENT_MASK;
+
+  switch (req->request) {
+
+    // Assign device address.  We can't actually update the address register 
+    // until after the full bus handshake has completed, otherwise the ACK 
+    // packet gets lost.
+    case USB_DEVREQ_SET_ADDRESS :
+      result = USBS_CONTROL_RETURN_HANDLED;
+      break;
+
+    // Set device configuration.
+    case USB_DEVREQ_SET_CONFIGURATION :
+      TRACE_USB ("Setting USB configuration = %d\n", (cyg_uint32) req->value_lo);
+      result = stm32_usb_ctrl_set_config (req->value_lo);
+      break;
+
+    // TODO: Interfaces with multiple settings are not currently supported.
+    // If a device only supports a default setting for a specified interface
+    // the spec says a stall should be sent.  
+    case USB_DEVREQ_SET_INTERFACE :
+      TRACE_USB ("Using default interface settings.\n");
+      result = USBS_CONTROL_RETURN_STALL;
+      break;
+ 
+    // Get device status.
+    case USB_DEVREQ_GET_STATUS :
+      result = stm32_usb_ctrl_get_status (recipient, req->index_lo);
+      break;
+
+    // Control endpoint halting.  Halt on 'set feature'.
+    case USB_DEVREQ_SET_FEATURE :
+      result = stm32_usb_ctrl_set_feature (recipient, req->index_lo, req->value_lo, true);
+      break;
+
+    // Control endpoint halting.  Resume on 'clear feature'.
+    case USB_DEVREQ_CLEAR_FEATURE :
+      result = stm32_usb_ctrl_set_feature (recipient, req->index_lo, req->value_lo, false);
+      break;
+
+    // Pass up to the user supplied handler, if present.
+    default :
+      if (ctrlep.common.standard_control_fn)
+        result = (*ctrlep.common.standard_control_fn) 
+          (&ctrlep.common, ctrlep.common.standard_control_data);
+      break; 
+  }
+
+  // If not already handled, pass up to the high level driver.
+  if (result == USBS_CONTROL_RETURN_UNKNOWN)
+    result = usbs_handle_standard_control (&ctrlep.common);
+
+  return result;
+}
+
+//-----------------------------------------------------------------------------
+// Perform initial processing of endpoint 0 setup packets.
+
+static void stm32_usb_ctrl_setup_handler
+  (void)
+{
+  cyg_uint32 req_length, req_type, req_dir;
+  usb_devreq* req = (usb_devreq*) &ctrlep.common.control_buffer[0];
+  usbs_control_return result = USBS_CONTROL_RETURN_UNKNOWN;
+
+  // Extract the required fields from the setup packet.
+  req_length = 8 * (cyg_uint32) req->length_hi + req->length_lo;
+  req_type = req->type & USB_DEVREQ_TYPE_MASK;
+  req_dir = req->type & USB_DEVREQ_DIRECTION_MASK;
+
+  // Always fail the transaction if the requested data stage exceeds the
+  // allocated buffer area.
+  if ((req_dir == USB_DEVREQ_DIRECTION_OUT) && 
+    (req_length > CYGNUM_DEVS_USB_CORTEXM_STM32_EPO_MAX_MSG_SIZE)) {
+    FAIL_USB ("Requested control data stage exceeds message buffer size.");
+    result = USBS_CONTROL_RETURN_STALL;
+  }
+
+  // Pass standard requests to the standard handlers.
+  else if (req_type == USB_DEVREQ_TYPE_STANDARD) {
+    result = stm32_usb_ctrl_setup_standard ();
+  }
+
+  // Hand off non-standard requests to their respective handlers.
+  else {
+    usbs_control_return (*callback_fn) (usbs_control_endpoint*, void*);
+    void* callback_arg;
+    
+    if (req_type == USB_DEVREQ_TYPE_CLASS) {
+      callback_fn  = ctrlep.common.class_control_fn;
+      callback_arg = ctrlep.common.class_control_data;
+    }
+    else if (req_type == USB_DEVREQ_TYPE_VENDOR) {
+      callback_fn  = ctrlep.common.vendor_control_fn;
+      callback_arg = ctrlep.common.vendor_control_data;
+    }
+    else {
+      callback_fn  = ctrlep.common.reserved_control_fn;
+      callback_arg = ctrlep.common.reserved_control_data;
+    }
+    
+    result = (callback_fn) ? (*callback_fn) (&ctrlep.common, callback_arg)
+      : USBS_CONTROL_RETURN_STALL;
+  }
+
+  // If correctly handled, initiate the data transfer phase.  This is only 
+  // called from within the DSR, so the transaction start is interrupt safe.
+  if (result == USBS_CONTROL_RETURN_HANDLED) {
+
+    // ACK the transfer by sending a zero length packet.
+    if (req_length == 0) {
+      ctrlep.msg_state = CTRLEP_MSG_STATE_CTRL_ACK;
+      ctrlep.txtr.state = TXTR_STATE_IDLE;
+      ctrlep.txtr.buf_ptr = ctrlep_msg_buffer;
+      ctrlep.txtr.buf_size = 0;
+      stm32_usb_txtr_start (&ctrlep.txtr, true);
+    }
+
+    // Send the inbound data.
+    else if (req_dir == USB_DEVREQ_DIRECTION_IN) {
+      ctrlep.msg_state = CTRLEP_MSG_STATE_IN_DATA;
+      ctrlep.txtr.state = TXTR_STATE_IDLE;
+      ctrlep.txtr.buf_ptr = ctrlep_msg_buffer;
+      ctrlep.txtr.buf_size = stm32_usb_ctrl_fill_msg_buffer ();
+      stm32_usb_txtr_start (&ctrlep.txtr, true);
+    }
+
+    // Receive outbound data from the host.    
+    else {
+      ctrlep.msg_state = CTRLEP_MSG_STATE_OUT_DATA;
+      ctrlep.rxtr.state = RXTR_STATE_IDLE;
+      ctrlep.rxtr.buf_ptr = ctrlep_msg_buffer;
+      ctrlep.rxtr.buf_size = CYGNUM_DEVS_USB_CORTEXM_STM32_EPO_MAX_MSG_SIZE;
+      stm32_usb_rxtr_start (&ctrlep.rxtr, true);
+    }
+  }
+
+  // Stall endpoint on request. 
+  else if (result == USBS_CONTROL_RETURN_STALL) {
+    stm32_usb_set_txep_status (0, CYGHWR_HAL_STM32_USB_EPXR_STATTX_STALL);
+    stm32_usb_set_rxep_status (0, CYGHWR_HAL_STM32_USB_EPXR_STATRX_STALL);
+  }
+
+  // Unsupported setup commands also stall the control endpoint.
+  else {
+    TRACE_USB ("Stall EP0 on UNKNOWN control message : %02X %02X %02X %02X %02X %02X %02X %02X\n",
+      ctrlep.common.control_buffer[0], ctrlep.common.control_buffer[1],
+      ctrlep.common.control_buffer[2], ctrlep.common.control_buffer[3],
+      ctrlep.common.control_buffer[4], ctrlep.common.control_buffer[5],
+      ctrlep.common.control_buffer[6], ctrlep.common.control_buffer[7]);
+    stm32_usb_set_txep_status (0, CYGHWR_HAL_STM32_USB_EPXR_STATTX_STALL);
+    stm32_usb_set_rxep_status (0, CYGHWR_HAL_STM32_USB_EPXR_STATRX_STALL);    
+  }
+}
+
+//-----------------------------------------------------------------------------
+// Completion of control endpoint data transmit phase.
+
+static inline void stm32_usb_ctrl_txtr_done 
+  (void)
+{
+  cyg_uint32 reg_val;
+  usb_devreq* req = (usb_devreq*) &ctrlep.common.control_buffer[0];
+
+  // If this is confirmation that an ACK packet has been sent, complete the
+  // transaction.  We also take the opportunity to update the device address
+  // here if required.
+  if (ctrlep.msg_state == CTRLEP_MSG_STATE_CTRL_ACK) {
+    if (req->request == USB_DEVREQ_SET_ADDRESS) {
+      TRACE_USB ("Setting USB device address = %d\n", (cyg_uint32) req->value_lo);
+      reg_val = CYGHWR_HAL_STM32_USB_DADDR_EF;
+      reg_val |= CYGHWR_HAL_STM32_USB_DADDR_ADD ((cyg_uint32) req->value_lo);
+      HAL_WRITE_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_DADDR, reg_val);
+      stm32_usb_ctrl_update_state (USBS_STATE_ADDRESSED, USBS_STATE_CHANGE_ADDRESSED);
+    }
+    stm32_usb_ctrl_completed (ctrlep.txtr.status);
+  }
+
+  // Complete after transmitting the output status handshake.
+  else if (ctrlep.msg_state == CTRLEP_MSG_STATE_OUT_STATUS) {
+    stm32_usb_ctrl_completed (ctrlep.txtr.status);
+  }
+
+  // If all packets in an inbound transaction have been sent, wait for status 
+  // response from the host.  Called from DSR so is interrupt safe.
+  else if (ctrlep.msg_state == CTRLEP_MSG_STATE_IN_DATA) {
+    if (ctrlep.txtr.status == ENOERR) {
+      ctrlep.msg_state = CTRLEP_MSG_STATE_IN_STATUS;
+      ctrlep.rxtr.state = RXTR_STATE_IDLE;
+      ctrlep.rxtr.buf_ptr = ctrlep_msg_buffer;
+      ctrlep.rxtr.buf_size = 0;
+      stm32_usb_rxtr_start (&ctrlep.rxtr, true);
+    }
+    else {
+      stm32_usb_ctrl_completed (ctrlep.txtr.status);
+    }
+  }
+}
+
+//-----------------------------------------------------------------------------
+// Completion of control endpoint data receive phase.
+
+static inline void stm32_usb_ctrl_rxtr_done 
+  (void)
+{
+  // If waiting for a status response, we should get a zero length packet.
+  if (ctrlep.msg_state == CTRLEP_MSG_STATE_IN_STATUS) {
+    stm32_usb_ctrl_completed (ctrlep.rxtr.status);
+  }
+
+  // Handle conventional data packets.  Incoming packets on endpoint 0 can
+  // be overwritten by setup packets.  Called from DSR so is interrupt safe.
+  else if (ctrlep.msg_state == CTRLEP_MSG_STATE_OUT_DATA) {
+    if (ctrlep.rxtr.status == ENOERR) {
+      ctrlep.msg_state = CTRLEP_MSG_STATE_OUT_STATUS;
+      ctrlep.txtr.state = TXTR_STATE_IDLE;
+      ctrlep.txtr.buf_ptr = ctrlep_msg_buffer;
+      ctrlep.txtr.buf_size = 0;
+      stm32_usb_txtr_start (&ctrlep.txtr, true);
+    }
+    else {
+      stm32_usb_ctrl_completed (ctrlep.rxtr.status);
+    }
+  }
+}
+
+//=============================================================================
+// Implement ISRs for low level data transfer.
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// ISR for handling control endpoint interrupts.
+
+static inline cyg_bool stm32_usb_ctrlep_ISR
+  (void)
+{
+  cyg_bool completed;
+  cyg_bool call_dsr = false; 
+  cyg_uint32 usb_epxr;
+
+  // Process packet transmit events.
+  HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EP0R, usb_epxr);
+  if (usb_epxr & CYGHWR_HAL_STM32_USB_EPXR_CTRTX) {
+    stm32_usb_clear_epxr_bits (0, CYGHWR_HAL_STM32_USB_EPXR_CTRTX);
+
+    completed = stm32_usb_txtr_run (&ctrlep.txtr);
+    if (completed) {
+      isr_shared.txtr_done |= (1 << 0);
+      call_dsr = true;
+    }
+  }
+
+  // Deal with incoming setup packets.  These are copied directly to the
+  // staging buffer in the ISR/DSR shared area for subsequent handling in
+  // DSR context.
+  if (usb_epxr & CYGHWR_HAL_STM32_USB_EPXR_CTRRX) {
+    stm32_usb_clear_epxr_bits (0, CYGHWR_HAL_STM32_USB_EPXR_CTRRX);
+
+    if (usb_epxr & CYGHWR_HAL_STM32_USB_EPXR_SETUP) {
+      stm32_usb_copy_from_sbuf (ctrlep.common.control_buffer, 8, 0);
+      isr_shared.flags |= ISR_FLAGS_SETUP_READY;
+      call_dsr = true;
+    }
+ 
+    // Handle conventional incoming packets.
+    else {
+      completed = stm32_usb_rxtr_run (&ctrlep.rxtr);
+      if (completed) {
+        isr_shared.rxtr_done |= (1 << 0);
+        call_dsr = true;
+      }
+    }
+  }
+  return call_dsr;
+}
+
+//-----------------------------------------------------------------------------
+// ISR for handling transmit endpoint interrupts.  
+
+static inline cyg_bool stm32_usb_txep_ISR
+  (cyg_uint32 txep_id)
+{
+  cyg_bool completed;
+  cyg_bool call_dsr = false; 
+  cyg_uint32 usb_epxr;
+  txep_impl* txep = txep_list + txep_id - 1;
+
+  // Receive events for a transmit endpoint are an error - discard them.
+  HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (txep_id), usb_epxr);
+  if (usb_epxr & CYGHWR_HAL_STM32_USB_EPXR_CTRRX) {
+    FAIL_USB ("Received RX interrupt for TX endpoint.");
+    stm32_usb_clear_epxr_bits (txep_id, CYGHWR_HAL_STM32_USB_EPXR_CTRRX);
+  }
+
+  // Handle transmit interrupt events.
+  if (usb_epxr & CYGHWR_HAL_STM32_USB_EPXR_CTRTX) {
+    stm32_usb_clear_epxr_bits (txep_id, CYGHWR_HAL_STM32_USB_EPXR_CTRTX);
+    completed = stm32_usb_txtr_run (&txep->txtr);
+    if (completed) {
+      isr_shared.txtr_done |= (1 << txep_id);
+      call_dsr = true;
+    }
+  }
+  return call_dsr;
+}
+
+//-----------------------------------------------------------------------------
+// ISR for handling receive endpoint interrupts.  
+
+static inline cyg_bool stm32_usb_rxep_ISR
+  (cyg_uint32 rxep_id)
+{
+  cyg_bool completed;
+  cyg_bool call_dsr = false; 
+  cyg_uint32 usb_epxr;
+  rxep_impl* rxep = rxep_list + rxep_id - CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM - 1;
+
+  // Transmit events for a receive endpoint are an error - discard them.
+  HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_EPXR (rxep_id), usb_epxr);
+  if (usb_epxr & CYGHWR_HAL_STM32_USB_EPXR_CTRTX) {
+    FAIL_USB ("Received TX interrupt for RX endpoint.");
+    stm32_usb_clear_epxr_bits (rxep_id, CYGHWR_HAL_STM32_USB_EPXR_CTRTX);
+  }
+
+  // Handle receive interrupt events.
+  if (usb_epxr & CYGHWR_HAL_STM32_USB_EPXR_CTRRX) {
+    stm32_usb_clear_epxr_bits (rxep_id, CYGHWR_HAL_STM32_USB_EPXR_CTRRX);
+    completed = stm32_usb_rxtr_run (&rxep->rxtr);
+    if (completed) {
+      isr_shared.rxtr_done |= (1 << rxep_id);
+      call_dsr = true;
+    }
+  }
+  return call_dsr;
+}
+
+//-----------------------------------------------------------------------------
+// Main ISR for handling interrupt events.  The interrupt generation for the 
+// USB endpoints is a little strange, with endpoint interrupts effectively being
+// queued through the same interrupt status register.  Clearing the interrupt
+// condition has the effect of popping an endpoint interrupt from the queue so
+// that the next endpoint can be serviced.  This means that serialising the
+// interrupt processing between ISR and DSR would carry an unacceptable latency
+// penalty - which is why we have to do the buffer copies within the ISR.
+
+static cyg_uint32 stm32_usb_ISR
+  (cyg_vector_t vector, cyg_addrword_t data)
+{
+  cyg_bool call_dsr = false; 
+  cyg_uint32 usb_istr, ep_id;
+  cyg_uint32 ret_val = CYG_ISR_HANDLED;
+
+  // Check for device interrupts first.
+  HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_ISTR, usb_istr);
+
+  // Detect reset event and hand it up to the DSR.  Note that these will not
+  // be merged with other events for DSR processing.
+  if (usb_istr & CYGHWR_HAL_STM32_USB_ISTR_RESET) {
+    usb_istr &= ~((cyg_uint32) CYGHWR_HAL_STM32_USB_ISTR_RESET);
+    HAL_WRITE_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_ISTR, usb_istr);
+    isr_shared.flags |= ISR_FLAGS_DEVICE_RESET;
+    call_dsr = true;
+  }
+
+  // TODO: Support for suspend and wake events can be added here if required.
+
+  // Check for endpoint interrupts.  These are indicated by the CTR flag.
+  // The endpoint direction is inferred from the endpoint number, since
+  // transmit endpoints are enumerated before receive endpoints.
+  else while (usb_istr & CYGHWR_HAL_STM32_USB_ISTR_CTR) {
+    ep_id = usb_istr & CYGHWR_HAL_STM32_USB_ISTR_EPID_MASK;
+
+    // Service the control endpoint.
+    if (ep_id == 0)
+      call_dsr |= stm32_usb_ctrlep_ISR ();
+
+    // Service transmit endpoints.
+    else if (ep_id <= CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM)
+      call_dsr |= stm32_usb_txep_ISR (ep_id);
+
+    // Service receive endpoints.
+    else if (ep_id < USB_EPNUM)
+      call_dsr |= stm32_usb_rxep_ISR (ep_id);
+
+    // Invalid endpoint.  Fail in debug, clear down in production builds.
+    else {
+      FAIL_USB ("Interrupt for invalid endpoint detected.");
+      stm32_usb_clear_epxr_bits (ep_id, 
+        CYGHWR_HAL_STM32_USB_EPXR_CTRTX | CYGHWR_HAL_STM32_USB_EPXR_CTRRX);
+    }
+
+    // Check for all endpoints having been serviced.
+    HAL_READ_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_ISTR, usb_istr);
+  }
+
+  // If interrupt has been handled, acknowledge it and return.  Leave the
+  // interrupt unmasked until the DSR is called, since intervening ISR calls
+  // will safely post their events to the event masks.
+  cyg_drv_interrupt_acknowledge (vector);
+  if (call_dsr) {
+    ret_val |= CYG_ISR_CALL_DSR;
+  }
+  return ret_val;
+}
+
+//=============================================================================
+// Implement DSRs for handling high-level interrupt responses.
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Main DSR for high-level interrupt processing.  Information about the
+// interrupt conditions is passed up via the ISR shared data area.
+
+static void stm32_usb_DSR 
+  (cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
+{
+  cyg_uint32 i;
+
+  // Disable interrupts on entry to the DSR to avoid further events getting
+  // added to the event masks.
+  stm32_usb_request_intr_mask ();
+
+  // Process device reset notifications.
+  if (isr_shared.flags & ISR_FLAGS_DEVICE_RESET) {
+    stm32_usb_ctrl_reset ();
+  }
+
+  // Process control endpoint message transmit completions.
+  if (isr_shared.txtr_done & 1) {
+    stm32_usb_ctrl_txtr_done ();
+  }
+
+  // Process control endpoint message receive completions.
+  if (isr_shared.rxtr_done & 1) {
+    stm32_usb_ctrl_rxtr_done ();
+  }
+
+  // Process non-control endpoint message transmit completions.
+  if (isr_shared.txtr_done) {
+    for (i = 1; i < 8; i++) {
+      if (isr_shared.txtr_done & (1 << i)) {
+        txep_impl* txep = txep_list + i - 1;
+        int retval = (txep->txtr.status != ENOERR) ? -txep->txtr.status : txep->txtr.bytes_sent;
+        if (txep->common.complete_fn)
+          (*txep->common.complete_fn) (txep->common.complete_data, retval);
+        if (retval < 0)
+          TRACE_USB ("TX transaction failed (endpoint %d, status %d).\n", txep->txtr.ep_num, retval);
+      }
+    }
+  }
+
+  // Process non-control endpoint message received completions.
+  if (isr_shared.rxtr_done) {
+    for (i = 1; i < 8; i++) {
+      if (isr_shared.rxtr_done & (1 << i)) {
+        rxep_impl* rxep = rxep_list + i - CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM - 1;
+        int retval = (rxep->rxtr.status != ENOERR) ? -rxep->rxtr.status : rxep->rxtr.bytes_rcvd;
+        if (rxep->common.complete_fn)
+          (*rxep->common.complete_fn) (rxep->common.complete_data, retval);
+        if (retval < 0)
+          TRACE_USB ("RX transaction failed (endpoint %d, status %d).\n", rxep->rxtr.ep_num, retval);
+      }
+    }
+  }
+
+  // Process setup packets after ensuring that all outstanding EP0 completions
+  // associated with a previous setup transaction have been dealt with.
+  if (isr_shared.flags & ISR_FLAGS_SETUP_READY) {
+    stm32_usb_ctrl_setup_handler ();
+  }
+
+  // Clear the ISR shared flags before unmasking the interrupt - they should 
+  // all have been dealt with.
+  isr_shared.flags = ISR_FLAGS_CLEARED;
+  isr_shared.txtr_done = 0;
+  isr_shared.rxtr_done = 0;
+
+  // Release the interrupt mask if possible.
+  stm32_usb_release_intr_mask ();
+}
+
+//=============================================================================
+// Provide standard USB driver API entry points.
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// API entry point for endpoint transmit requests.
+
+static void stm32_usb_tx_start
+  (usbs_tx_endpoint* usbs_txep)
+{
+  txep_impl* txep = (txep_impl*) usbs_txep;
+  txtr_impl* txtr = &txep->txtr;
+  cyg_int32 status = -EIO;
+
+  // Check to see whether a transaction is in progress.
+  if (txtr->state != TXTR_STATE_IDLE) {
+    FAIL_USB ("Endpoint TX request when endpoint already busy.");
+    status = -EBUSY;
+    goto out;
+  }
+
+  // Do a sanity check on the descriptor.
+  if (!txep->common.complete_fn) {
+    FAIL_USB ("Endpoint TX requires a completion function.");
+    goto out;
+  }
+  if (!txep->common.buffer) {
+    FAIL_USB ("Endpoint TX requires a valid transmit buffer.");
+    goto out;
+  }
+  if (stm32_usb_buf_get_size (txtr->ep_num) == 0) {
+    FAIL_USB ("TX request when endpoint buffers not allocated.");
+    goto out;
+  }
+
+  // Attempt to start a transmit transaction and extract error status if it 
+  // completes too early.  This is not an interrupt safe call.
+  txtr->buf_ptr = txep->common.buffer;
+  txtr->buf_size = (cyg_uint32) txep->common.buffer_size;
+  if (stm32_usb_txtr_start (txtr, false))
+    status = -txtr->status;
+  else
+    status = -ENOERR;
+
+  // If the transaction failed to start, fire the completion handler.
+out:
+  if ((status < 0) && (txep->common.complete_fn)) {
+    txep->common.complete_fn (txep->common.complete_data, status);
+  }
+}
+
+//-----------------------------------------------------------------------------
+// API entry point for endpoint receive requests.
+
+static void stm32_usb_rx_start
+  (usbs_rx_endpoint* usbs_rxep)
+{
+  rxep_impl* rxep = (rxep_impl*) usbs_rxep;
+  rxtr_impl* rxtr = &rxep->rxtr;
+  cyg_int32 status = -EIO;
+
+  // Check to see whether a transaction is in progress.
+  if (rxtr->state != RXTR_STATE_IDLE) {
+    FAIL_USB ("Endpoint RX request when endpoint already busy.");
+    status = -EBUSY;
+    goto out;
+  }
+
+  // Do a sanity check on the descriptor.
+  if (!rxep->common.complete_fn) {
+    FAIL_USB ("Endpoint RX requires a completion function.");
+    goto out;
+  }
+  if (!rxep->common.buffer) {
+    FAIL_USB ("Endpoint RX requires a valid receive buffer.");
+    goto out;
+  }
+  if (stm32_usb_buf_get_size (rxtr->ep_num) == 0) {
+    FAIL_USB ("RX request when endpoint buffers not allocated.");
+    goto out;
+  }
+  
+  // Attempt to start a receive transaction and extract error status if it 
+  // completes too early.  This is not an interrupt safe call.
+  rxtr->buf_ptr = rxep->common.buffer;
+  rxtr->buf_size = (cyg_uint32) rxep->common.buffer_size;
+  if (stm32_usb_rxtr_start (rxtr, false))
+    status = -rxtr->status;
+  else
+    status = -ENOERR;
+
+  // If the transaction failed to start, fire the completion handler.
+out:
+  if ((status < 0) && (rxep->common.complete_fn)) {
+    rxep->common.complete_fn (rxep->common.complete_data, status);
+  }
+}
+
+//-----------------------------------------------------------------------------
+// API entry point for setting transmit endpoint halted state.  
+
+static void stm32_usb_set_txep_halted
+  (usbs_tx_endpoint* txep, cyg_bool halted)
+{
+  if (halted)
+    stm32_usb_txep_halt ((txep_impl*) txep, false); 
+  else
+    stm32_usb_txep_unhalt ((txep_impl*) txep, false);
+}
+
+//-----------------------------------------------------------------------------
+// API entry point for setting receive endpoint halted state.
+
+static void stm32_usb_set_rxep_halted
+  (usbs_rx_endpoint* rxep, cyg_bool halted)
+{
+  if (halted)
+    stm32_usb_rxep_halt ((rxep_impl*) rxep, false); 
+  else
+    stm32_usb_rxep_unhalt ((rxep_impl*) rxep, false);
+}
+
+//=============================================================================
+// Initialise and reset the USB device.
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// One-time initialisation.  This function is called during device startup
+// in order to bring up the USB peripheral ready for operation.
+
+static void CYGBLD_ATTRIB_C_INIT_PRI(CYG_INIT_DEV_CHAR) cyg_usbs_cortexm_stm32_init 
+  (void)
+{
+  cyg_uint32 reg_data;
+
+  // First ensure that the APB bus is being clocked fast enough.
+  ASSERT_USB (APB1_FREQ > 8000000, "APB1 must be clocked faster than 8MHz.");
+
+  // Check that the endpoint configuration is sane.
+  ASSERT_USB (CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM < 8,
+    "Too many hardware endpoints allocated in configuration.");
+
+  // Make sure that the CAN controller is disabled and held in reset.
+  // TODO: If a CAN driver is to be added to the standard distribution, this
+  // should check for USB/CAN configuration clashes.
+  CYGHWR_HAL_STM32_CLOCK_DISABLE( CYGHWR_HAL_STM32_CAN1_CLOCK );
+
+  // Configure the IO pins for USB operation.
+  CYGHWR_HAL_STM32_GPIO_SET (USB_DISC_PIN);
+  CYGHWR_HAL_STM32_GPIO_SET (USB_DP_PIN);
+  CYGHWR_HAL_STM32_GPIO_SET (USB_DM_PIN);
+#ifdef CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN_ACT_LOW
+  CYGHWR_HAL_STM32_GPIO_OUT (USB_DISC_PIN, 0);
+#else
+  CYGHWR_HAL_STM32_GPIO_OUT (USB_DISC_PIN, 1);
+#endif
+
+  // Ensure that the USB clock is disabled prior to setting prescaler. 
+  CYGHWR_HAL_STM32_CLOCK_DISABLE( CYGHWR_HAL_STM32_USB_CLOCK );
+
+  // Set up the USB 48MHz serial clock.  There are only 2 valid prescaler
+  // settings which correspond to 72MHz and 48MHz PLL clock outputs.
+  HAL_READ_UINT32 (CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_CFGR, reg_data);
+#if (PLL_FREQ == 72000000)
+  reg_data &= ~((cyg_uint32) CYGHWR_HAL_STM32_RCC_CFGR_USBPRE);  
+#elif (PLL_FREQ == 48000000)
+  reg_data |= CYGHWR_HAL_STM32_RCC_CFGR_USBPRE;
+#else
+#error "SMT32 PLL clock must be set to 48MHz or 72MHz for correct USB operation."
+#endif
+  HAL_WRITE_UINT32 (CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_CFGR, reg_data);
+
+  // Activate the USB clock after setting prescaler. 
+  CYGHWR_HAL_STM32_CLOCK_ENABLE( CYGHWR_HAL_STM32_USB_CLOCK );
+
+  // Take USB transceiver out of powerdown state, but leave it in reset until we
+  // are ready to start.  Leave interrupts disabled at source.
+  reg_data = CYGHWR_HAL_STM32_USB_CNTR_FRES;
+  HAL_WRITE_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_CNTR, reg_data);
+  CYGACC_CALL_IF_DELAY_US (USB_TSTARTUP);
+  
+  // Initialise interrupt mask request counter.
+  interrupt_mask_count = 0;
+
+  // Attach USB interrupts.  Everything is done via the standard interrupt - the 
+  // high priority interrupt is not used.
+  cyg_drv_interrupt_mask (CYGNUM_HAL_INTERRUPT_USB_HP);
+  cyg_drv_interrupt_create (CYGNUM_HAL_INTERRUPT_USB_LP, CYGNUM_DEVS_USB_CORTEXM_STM32_ISR_PRIORITY,
+    0, stm32_usb_ISR, stm32_usb_DSR, &interrupt_handle, &interrupt_data);
+  cyg_drv_interrupt_attach (interrupt_handle);
+}
+
+//-----------------------------------------------------------------------------
+// Device endpoint 0 startup.  This function is called once the application 
+// code has set up the desired USB control endpoint configuration.
+
+static void stm32_usb_start
+  (usbs_control_endpoint* endpoint)
+{
+  cyg_uint32 i;
+  txep_impl* txep = txep_list;
+  rxep_impl* rxep = rxep_list;
+
+  // Fill in the generic endpoint data structures.
+  for (i = 0; i < CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM; i++) {
+    txep->common.start_tx_fn   = stm32_usb_tx_start;
+    txep->common.set_halted_fn = stm32_usb_set_txep_halted;
+    txep->common.halted        = true;
+    txep->txtr.state           = TXTR_STATE_RESET;
+    txep->txtr.ep_num          = i + 1;
+    txep++;
+  }
+  for (i = 0; i < CYGNUM_DEVS_USB_CORTEXM_STM32_RXEP_NUM; i++) {
+    rxep->common.start_rx_fn   = stm32_usb_rx_start;
+    rxep->common.set_halted_fn = stm32_usb_set_rxep_halted;
+    rxep->common.halted        = true;
+    rxep->rxtr.state           = RXTR_STATE_RESET;
+    rxep->rxtr.ep_num          = i + CYGNUM_DEVS_USB_CORTEXM_STM32_TXEP_NUM + 1;
+    rxep++;
+  }  
+
+  // Take the USB driver out of reset and cancel any spurious interrupts.
+  HAL_WRITE_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_CNTR, 0);
+  HAL_WRITE_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_ISTR, 0);
+
+  // Enable interrupts at source.
+  HAL_WRITE_UINT32 (USB_BASE + CYGHWR_HAL_STM32_USB_CNTR, 
+    CYGHWR_HAL_STM32_USB_CNTR_CTRM | CYGHWR_HAL_STM32_USB_CNTR_RESETM);
+
+  // Reconnect the device to the USB bus if required.
+#ifdef CYGHWR_DEVS_USB_CORTEXM_STM32_DISC_PIN_ACT_LOW
+  CYGHWR_HAL_STM32_GPIO_OUT (USB_DISC_PIN, 1);
+#else
+  CYGHWR_HAL_STM32_GPIO_OUT (USB_DISC_PIN, 0);
+#endif
+  stm32_usb_ctrl_update_state (USBS_STATE_POWERED, USBS_STATE_CHANGE_POWERED);
+
+  // Allow interrupts to run - the bus reset must be driven by the host.
+  cyg_drv_interrupt_unmask (CYGNUM_HAL_INTERRUPT_USB_LP);
+}
+
+//-----------------------------------------------------------------------------
+// Device endpoint 0 poll.  Polled operation just calls the ISR followed by
+// the DSR.  TODO: Polled operation needs further testing. 
+
+static void stm32_usb_poll  
+  (usbs_control_endpoint* endpoint)
+{
+  cyg_uint32 isr_retval;
+  isr_retval = stm32_usb_ISR (CYGNUM_HAL_INTERRUPT_USB_LP, 0);
+  if (isr_retval & CYG_ISR_CALL_DSR)
+    stm32_usb_DSR (CYGNUM_HAL_INTERRUPT_USB_LP, 1, 0);
+}
+
+//-----------------------------------------------------------------------------
+// Get a handle on the specified transmit (in) endpoint.
+
+static usbs_tx_endpoint* stm32_usb_get_txep 
+  (usbs_control_endpoint* control_endpoint, cyg_uint8 ep_id)
+{
+  txep_impl* txep = NULL;
+
+  // Map from endpoint ID to physical endpoint.
+  if (ep_id > 0 && ep_id < 16)
+    txep = txep_map [ep_id - 1];
+
+  // Return endpoint handle or null pointer for invalid endpoint.
+  if (txep == NULL) {
+    FAIL_USB ("Invalid endpoint ID when accessing transmit (in) endpoint.");
+    return NULL;
+  }
+  return (usbs_tx_endpoint*) txep;
+}
+
+//-----------------------------------------------------------------------------
+// Get a handle on the specified receive (out) endpoint.
+
+static usbs_rx_endpoint* stm32_usb_get_rxep 
+  (usbs_control_endpoint* control_endpoint, cyg_uint8 ep_id)
+{
+  rxep_impl* rxep = NULL;
+
+  // Map from endpoint ID to physical endpoint.
+  if (ep_id > 0 && ep_id < 16)
+    rxep = rxep_map [ep_id - 1];
+
+  // Return endpoint handle or null pointer for invalid endpoint.
+  if (rxep == NULL) {
+    FAIL_USB ("Invalid endpoint ID when accessing receive (out) endpoint.");
+    return NULL;
+  }
+  return (usbs_rx_endpoint*) rxep;
+}
+
+//=============================================================================
+// Instantiate the test endpoint data structures if required.  This creates a
+// single endpoint of each supported type - bulk transmit, bulk receive, 
+// interrupt transmit and interrupt receive.  
+//=============================================================================
+
+#ifdef CYGBLD_IO_USB_SLAVE_USBTEST
+
+usbs_testing_endpoint usbs_testing_endpoints[] = {
+
+  { // Control endpoint.
+    endpoint_type      : USB_ENDPOINT_DESCRIPTOR_ATTR_CONTROL,
+    endpoint_number    : 0,
+    endpoint_direction : USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN,
+    endpoint           : (void*) &ctrlep,
+    devtab_entry       : 0,
+    min_size           : 1,
+    max_size           : CYGNUM_DEVS_USB_CORTEXM_STM32_EPO_MAX_MSG_SIZE,
+    max_in_padding     : 0,
+    alignment          : 0
+  },
+
+  { // Bulk transmit (input) endpoint.
+    endpoint_type      : USB_ENDPOINT_DESCRIPTOR_ATTR_BULK,
+    endpoint_number    : 1,
+    endpoint_direction : USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN,
+    endpoint           : (void*) &txep_list[0],
+    devtab_entry       : 0,
+    min_size           : 0,
+    max_size           : 0x1000,  // 4k max for testing.
+    max_in_padding     : 0,
+    alignment          : 0
+  },
+
+  { // Bulk receive (output) endpoint.
+    endpoint_type      : USB_ENDPOINT_DESCRIPTOR_ATTR_BULK,
+    endpoint_number    : 2,
+    endpoint_direction : USB_ENDPOINT_DESCRIPTOR_ENDPOINT_OUT,
+    endpoint           : (void*) &rxep_list[0],
+    devtab_entry       : 0,
+    min_size           : 0,
+    max_size           : 0x1000,  // 4k max for testing.
+    max_in_padding     : 0,
+    alignment          : 0
+  },
+
+  { // Interrupt transmit (input) endpoint
+    endpoint_type      : USB_ENDPOINT_DESCRIPTOR_ATTR_INTERRUPT,
+    endpoint_number    : 3,
+    endpoint_direction : USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN,
+    endpoint           : (void*) &txep_list[1],
+    devtab_entry       : 0,
+    min_size           : 0,
+    max_size           : 8,  // Maximum for low speed devices.
+    max_in_padding     : 0,
+    alignment          : 0
+  },
+
+  { // Interrupt receive (output) endpoint.
+    endpoint_type      : USB_ENDPOINT_DESCRIPTOR_ATTR_INTERRUPT,
+    endpoint_number    : 4,
+    endpoint_direction : USB_ENDPOINT_DESCRIPTOR_ENDPOINT_OUT,
+    endpoint           : (void*) &rxep_list[1],
+    devtab_entry       : 0,
+    min_size           : 0,
+    max_size           : 8,  // Maximum for low speed devices.
+    max_in_padding     : 0,
+    alignment          : 0
+  },
+
+  USBS_TESTING_ENDPOINTS_TERMINATOR
+};
+
+#endif
+
+//=============================================================================
diff --git a/packages/devs/wallclock/arm/lpc2xxx/current/ChangeLog b/packages/devs/wallclock/arm/lpc2xxx/current/ChangeLog
--- a/packages/devs/wallclock/arm/lpc2xxx/current/ChangeLog
+++ b/packages/devs/wallclock/arm/lpc2xxx/current/ChangeLog
@@ -1,3 +1,8 @@
+2011-01-15  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/lpc2xxx_wallclock.cdl:
+	* src/lpc2xxx_wallclock.cxx: Added support for LPC17XX CPUs.
+
 2008-11-01  Uwe Kindler <uwe_kindler@web.de>
 
 	* cdl/lpc2xxx_wallclock.cdl: Moved CYGNUM_HAL_ARM_LPC2XXX_RTCDEV_PREINT
diff --git a/packages/devs/wallclock/arm/lpc2xxx/current/cdl/lpc2xxx_wallclock.cdl b/packages/devs/wallclock/arm/lpc2xxx/current/cdl/lpc2xxx_wallclock.cdl
--- a/packages/devs/wallclock/arm/lpc2xxx/current/cdl/lpc2xxx_wallclock.cdl
+++ b/packages/devs/wallclock/arm/lpc2xxx/current/cdl/lpc2xxx_wallclock.cdl
@@ -2,7 +2,7 @@
 #
 #      lpc2xxx_wallclock.cdl
 #
-#      eCos configuration data for LPC2xxx internal RTC
+#      eCos configuration data for LPC2xxx, LPC17xx internal RTC
 #
 # ====================================================================
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
@@ -40,7 +40,7 @@
 ######DESCRIPTIONBEGIN####
 #
 # Author(s):      Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
-# Contributors:   jskov
+# Contributors:   jskov, ilijak
 # Date:           2007-06-19
 #
 #####DESCRIPTIONEND####
@@ -48,12 +48,13 @@
 # ====================================================================
 
 cdl_package CYGPKG_DEVICES_WALLCLOCK_ARM_LPC2XXX {
-    display       "LPC2xxx Real-time clock"
-    description   "RTC driver for the LPC2xxx controller"
+    display       "Real-time clock"
+    description   "RTC driver for the LPC2XXX, LPC17XX CPUs"
 
     parent        CYGPKG_IO_WALLCLOCK
     active_if     CYGPKG_IO_WALLCLOCK
-    active_if     CYGPKG_HAL_ARM_LPC2XXX || CYGPKG_HAL_ARM_LPC24XX
+    active_if     { CYGPKG_HAL_ARM_LPC2XXX || CYGPKG_HAL_ARM_LPC24XX ||
+                    CYGPKG_HAL_CORTEXM_LPC17XX }
 
     requires      { CYGHWR_HAL_ARM_LPC2XXX_IDLE_PWRSAVE == 0 }
     compile       lpc2xxx_wallclock.cxx
diff --git a/packages/devs/wallclock/arm/lpc2xxx/current/src/lpc2xxx_wallclock.cxx b/packages/devs/wallclock/arm/lpc2xxx/current/src/lpc2xxx_wallclock.cxx
--- a/packages/devs/wallclock/arm/lpc2xxx/current/src/lpc2xxx_wallclock.cxx
+++ b/packages/devs/wallclock/arm/lpc2xxx/current/src/lpc2xxx_wallclock.cxx
@@ -2,7 +2,7 @@
 //
 //      lpc2xxx_wallclock.cxx
 //
-//      Wallclock implementation for LPC2xxx and LPC24xxx
+//      Wallclock implementation for LPC2xxx and LPC17xx CPUs
 //
 //==========================================================================
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
@@ -40,9 +40,9 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):     Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
-// Contributors:  Uwe Kindler <uwe_kindler@web.de 
+// Contributors:  Uwe Kindler <uwe_kindler@web.de, ilijak
 // Date:          2007-06-19
-// Purpose:       Wallclock driver for LPC2xxx and LPC24xx
+// Purpose:       Wallclock driver for LPC2xxx and LPC17xx CPUs
 //
 //####DESCRIPTIONEND####
 //
@@ -62,7 +62,7 @@
 //
 // The LPC2xxx variant HAL provides the CPU clock and the peripheral divider
 // VPBDIV. The LPC24xx variant HAL provides the RTC clock directly be means
-// of CYGNUM_HAL_ARM_LPC24XX_RTC_CLK. 
+// of CYGNUM_HAL_ARM_LPC24XX_RTC_CLK.
 //
 #ifdef CYGNUM_HAL_ARM_LPC2XXX_VPBDIV
 #define LPC2XXX_RTC_CLK (CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED / \
@@ -110,11 +110,13 @@ struct rtcdev {
   struct time time;
   cyg_uint32 dummy[8];
   struct time alarm;
+#ifndef CYGHWR_HAL_LPC_RTC_32768HZ
   volatile cyg_uint32 preint;
   volatile cyg_uint32 prefrac;
+#endif
 };
 
-static struct rtcdev * const rtc = 
+static struct rtcdev * const rtc =
   (struct rtcdev *) CYGARC_HAL_LPC2XXX_REG_RTC_BASE;
 
 void
@@ -124,13 +126,15 @@ Cyg_WallClock::init_hw_seconds(void)
   rtc->ccr  = 0x2;
   rtc->ciir = 0x0;
   rtc->amr  = 0xf;
-  
+
   // initialize prescaler - if the RTC id driven by an external 32.768 crystal
   // clock then initializing the prescaler is not required but writing the
   // registers here should not cause any trouble
+#ifndef CYGHWR_HAL_LPC_RTC_32768HZ
   rtc->preint  = CYGNUM_HAL_ARM_LPC2XXX_RTCDEV_PREINT;
   rtc->prefrac = CYGNUM_HAL_ARM_LPC2XXX_RTCDEV_PREFRAC;
-  
+#endif
+
 #ifndef CYGSEM_WALLCLOCK_SET_GET_MODE
   /* reset time to the Unix Epoch */
   rtc->time.year  = 1970;
@@ -142,12 +146,12 @@ Cyg_WallClock::init_hw_seconds(void)
   rtc->time.min   = 0;
   rtc->time.sec   = 0;
 #endif
-  
+
   /* reset alarm */
   rtc->alarm.year = rtc->alarm.month = rtc->alarm.dom = rtc->alarm.doy =
-    rtc->alarm.dow = rtc->alarm.hour = rtc->alarm.min = 
+    rtc->alarm.dow = rtc->alarm.hour = rtc->alarm.min =
     rtc->alarm.sec = 0;
-  
+
   /* start clock */
   rtc->ccr = 0x1;
 }
@@ -168,10 +172,10 @@ void
 Cyg_WallClock::set_hw_seconds(cyg_uint32 secs)
 {
   cyg_uint32 year, month, dom, hour, min, sec;
-  
+
   /* halt clock, reset counter */
   rtc->ccr = 0x2;
-  
+
   /* set time */
   _simple_mkdate(secs, &year, &month, &dom, &hour, &min, &sec);
   rtc->time.year  = year;
@@ -180,8 +184,11 @@ Cyg_WallClock::set_hw_seconds(cyg_uint32
   rtc->time.hour  = hour;
   rtc->time.min   = min;
   rtc->time.sec   = sec;
-  
+
   /* restart clock */
   rtc->ccr = 0x1;
 }
-#endif
+#endif // CYGSEM_WALLCLOCK_SET_GET_MODE
+
+//==========================================================================
+// EOF lpc2xxx_wallclock.cxx
diff --git a/packages/devs/wallclock/cortexm/stm32/current/ChangeLog b/packages/devs/wallclock/cortexm/stm32/current/ChangeLog
--- a/packages/devs/wallclock/cortexm/stm32/current/ChangeLog
+++ b/packages/devs/wallclock/cortexm/stm32/current/ChangeLog
@@ -1,3 +1,13 @@
+2012-01-19  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/wallclock_stm32.cdl: Ensure this driver is only active for F1
+	parts.
+
+2009-06-29  Nick Garnett  <nickg@ecoscentric.com>
+
+	* src/stm32_wallclock.cxx (Cyg_WallClock::init_hw_seconds): Add
+	enables for clocks of devices used by this device.
+
 2008-11-12  Simon Kallweit  <simon.kallweit@intefo.ch>
 
 	* src/stm32_wallclock.cxx: Using new CYGHWR_HAL_STM32_BD_PROTECT
diff --git a/packages/devs/wallclock/cortexm/stm32/current/cdl/wallclock_stm32.cdl b/packages/devs/wallclock/cortexm/stm32/current/cdl/wallclock_stm32.cdl
--- a/packages/devs/wallclock/cortexm/stm32/current/cdl/wallclock_stm32.cdl
+++ b/packages/devs/wallclock/cortexm/stm32/current/cdl/wallclock_stm32.cdl
@@ -50,12 +50,12 @@
 cdl_package CYGPKG_DEVS_WALLCLOCK_STM32 {
     display       "STM32 RTC wallclock support"
     description   "
-        Wallclock support for on-chip RTC on STM32 devices.driver for the
-        STM32 controller and compatibles"
+        Wallclock support for on-chip RTC on STM32 devices."
 
     parent        CYGPKG_IO_WALLCLOCK
     active_if     CYGPKG_IO_WALLCLOCK
     active_if     CYGPKG_HAL_CORTEXM_STM32
+    active_if     { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F1" }
 
     compile       stm32_wallclock.cxx
 
@@ -77,3 +77,5 @@ cdl_package CYGPKG_DEVS_WALLCLOCK_STM32 
         legal_values        { "LSE" "LSI" "HSE_128" }
     }
 }
+
+# End of wallclock_stm32.cdl
diff --git a/packages/devs/wallclock/cortexm/stm32/current/src/stm32_wallclock.cxx b/packages/devs/wallclock/cortexm/stm32/current/src/stm32_wallclock.cxx
--- a/packages/devs/wallclock/cortexm/stm32/current/src/stm32_wallclock.cxx
+++ b/packages/devs/wallclock/cortexm/stm32/current/src/stm32_wallclock.cxx
@@ -129,6 +129,10 @@ Cyg_WallClock::init_hw_seconds(void)
     cyg_uint32 bdcr, csr;
     cyg_uint32 prescaler = CYGHWR_DEVS_WALLCLOCK_STM32_CLOCK - 1;
     
+    // Enable backup domain and power control
+    CYGHWR_HAL_STM32_CLOCK_ENABLE( CYGHWR_HAL_STM32_CLOCK_BKP );
+    CYGHWR_HAL_STM32_CLOCK_ENABLE( CYGHWR_HAL_STM32_CLOCK_PWR );
+    
     // Reset the backup domain if clock source does not match as
     // RTCSEL can only be written to backup domain once
     HAL_READ_UINT32( rcc+CYGHWR_HAL_STM32_RCC_BDCR, bdcr );
diff --git a/packages/devs/wallclock/freescale/kinetis/current/ChangeLog b/packages/devs/wallclock/freescale/kinetis/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/devs/wallclock/freescale/kinetis/current/ChangeLog
@@ -0,0 +1,29 @@
+2011-04-24  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/wallclock_kinetis_rtc.cdl:
+	* src/wallclock_kinetis_rtc.cxx:
+	  New wallclock driver
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/packages/devs/wallclock/freescale/kinetis/current/cdl/wallclock_kinetis_rtc.cdl b/packages/devs/wallclock/freescale/kinetis/current/cdl/wallclock_kinetis_rtc.cdl
new file mode 100644
--- /dev/null
+++ b/packages/devs/wallclock/freescale/kinetis/current/cdl/wallclock_kinetis_rtc.cdl
@@ -0,0 +1,70 @@
+# ====================================================================
+#
+#      wallclock_kinetis_rtc.cdl
+#
+#      eCos configuration data for Kinetis RTC
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      ilijak
+# Contributors:
+# Date:           2011-04-23
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVICES_WALLCLOCK_KINETIS_RTC {
+    display       "Real-time clock"
+
+    description   "Driver for the Kinetis RTC"
+
+    parent        CYGPKG_IO_WALLCLOCK
+    active_if     CYGPKG_IO_WALLCLOCK
+
+    compile       wallclock_kinetis_rtc.cxx
+
+    implements    CYGINT_WALLCLOCK_HW_IMPLEMENTATIONS
+    active_if     CYGIMP_WALLCLOCK_HARDWARE
+    implements    CYGINT_WALLCLOCK_SET_GET_MODE_SUPPORTED
+
+    cdl_option CYGIMP_WALLCLOCK_HARDWARE {
+        parent        CYGPKG_IO_WALLCLOCK_IMPLEMENTATION
+        display       "Hardware wallclock"
+        default_value 1
+        implements    CYGINT_WALLCLOCK_IMPLEMENTATIONS
+    }
+}
diff --git a/packages/devs/wallclock/freescale/kinetis/current/src/wallclock_kinetis_rtc.cxx b/packages/devs/wallclock/freescale/kinetis/current/src/wallclock_kinetis_rtc.cxx
new file mode 100644
--- /dev/null
+++ b/packages/devs/wallclock/freescale/kinetis/current/src/wallclock_kinetis_rtc.cxx
@@ -0,0 +1,105 @@
+//==========================================================================
+//
+//      wallclock_kinetis_rtc.cxx
+//
+//      Wallclock implementation for Kinetis RTC module
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Contributors:
+// Date:          2011-04-23
+// Purpose:       Wallclock driver for Kinetis RTC module
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/wallclock.h>
+#include <pkgconf/devices_wallclock_kinetis_rtc.h>
+
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/io/wallclock.hxx>
+
+void
+Cyg_WallClock::init_hw_seconds(void)
+{
+    volatile cyghwr_hal_kinetis_rtc_t *rtc_p = CYGHWR_HAL_KINETIS_RTC_P;
+#ifdef CYGSEM_WALLCLOCK_SET_GET_MODE
+    // if RTC is disabled (e.g. due to power loss) initialize it.
+    if(!(rtc_p->sr &CYGHWR_HAL_KINETIS_RTC_SR_TCE))
+#endif
+    {
+        // halt clock, reset
+        rtc_p->sr &= ~CYGHWR_HAL_KINETIS_RTC_SR_TCE;
+        // set time
+        rtc_p->tpr = 0;
+        rtc_p->tsr = 0;
+        // restart clock
+        rtc_p->sr |= CYGHWR_HAL_KINETIS_RTC_SR_TCE;
+    }
+}
+
+cyg_uint32
+Cyg_WallClock::get_hw_seconds(void)
+{
+    volatile cyghwr_hal_kinetis_rtc_t *rtc_p = CYGHWR_HAL_KINETIS_RTC_P;
+
+    return rtc_p->tsr;
+}
+
+#ifdef CYGSEM_WALLCLOCK_SET_GET_MODE
+void
+Cyg_WallClock::set_hw_seconds(cyg_uint32 secs)
+{
+    volatile cyghwr_hal_kinetis_rtc_t *rtc_p = CYGHWR_HAL_KINETIS_RTC_P;
+
+    // halt clock, reset
+    rtc_p->sr &= ~CYGHWR_HAL_KINETIS_RTC_SR_TCE;
+    // set time
+    rtc_p->tpr = 0;
+    rtc_p->tsr = secs;
+    // restart clock
+    rtc_p->sr |= CYGHWR_HAL_KINETIS_RTC_SR_TCE;
+}
+#endif // CYGSEM_WALLCLOCK_SET_GET_MODE
+
+//==========================================================================
+// EOF wallclock_kinetis_rtc.cxx
diff --git a/packages/ecos.db b/packages/ecos.db
--- a/packages/ecos.db
+++ b/packages/ecos.db
@@ -1,6976 +1,7629 @@
-#=============================================================================
-#
-#    ecos.db
-#
-#    This file is a temporary database for eCos package information.
-#    It replaces the old packages and targets files, and will in turn
-#    be subsumed by another file containing more inormation.
-#
-#=============================================================================
-## ####ECOSGPLCOPYRIGHTBEGIN####                                            
-## -------------------------------------------                              
-## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2008, 2009 Free Software Foundation, Inc.
-##
-## eCos is free software; you can redistribute it and/or modify it under    
-## the terms of the GNU General Public License as published by the Free     
-## Software Foundation; either version 2 or (at your option) any later      
-## version.                                                                 
-##
-## eCos is distributed in the hope that it will be useful, but WITHOUT      
-## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
-## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
-## for more details.                                                        
-##
-## You should have received a copy of the GNU General Public License        
-## along with eCos; if not, write to the Free Software Foundation, Inc.,    
-## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
-##
-## As a special exception, if other files instantiate templates or use      
-## macros or inline functions from this file, or you compile this file      
-## and link it with other works to produce a work based on this file,       
-## this file does not by itself cause the resulting work to be covered by   
-## the GNU General Public License. However the source code for this file    
-## must still be made available in accordance with section (3) of the GNU   
-## General Public License v2.                                               
-##
-## This exception does not invalidate any other reasons why a work based    
-## on this file might be covered by the GNU General Public License.         
-## -------------------------------------------                              
-## ####ECOSGPLCOPYRIGHTEND####                                              
-#=============================================================================
-######DESCRIPTIONBEGIN####
-#
-# Author(s):	bartv
-# Date:		1999-06-13
-#
-# This file contains three lots of information. It details the packages
-# in the component repository, the target boards supported by those
-# packages, and a set of templates that can be used to instantiate
-# configuration.
-# 
-#####DESCRIPTIONEND####
-#===============================================================================
-
-package CYGPKG_HAL {
-        alias		{ "eCos common HAL" hal hal_common }
-	directory	hal/common
-	script		hal.cdl
-	description "
-The eCos HAL package provide a porting layer for higher-level parts of
-the system such as the kernel and the C library. Each installation
-should have HAL packages for one or more architectures, and for each
-architecture there may be one or more supported platforms. It is
-necessary to select one target architecture and one platform for that
-architecture. There are also a number of configuration options that
-are common to all HAL packages."
-}
-
-package CYGPKG_INFRA {
-	alias 		{ Infrastructure infra }
-	directory	infra
-	script		infra.cdl
-        description "
-Common types and useful macros.
-Tracing and assertion facilities.
-Package startup options." 
-}
-
-package CYGPKG_IO {
-	alias 		{ "I/O sub-system" io }
-	directory	io/common
-	script		io.cdl
-        description "
-           The eCos system is supplied with a number of different
-           device drivers.  This package contains the basic I/O system
-           support which is the basis for all drivers."
-}
-
-package CYGPKG_IO_SERIAL {
-	alias 		{ "Serial device drivers" serial io_serial }
-	directory	io/serial
-	script		io_serial.cdl
-        description "
-           This package contains drivers for basic I/O services on
-           serial devices."
-}
-
-package CYGPKG_IO_CAN {
-	alias 		{ "CAN device drivers" can io_can }
-	directory	io/can
-	script		io_can.cdl
-        description "
-           This package contains drivers for basic I/O services on
-           CAN devices."
-}
-
-package CYGPKG_DEVS_CAN_MCF52xx_FLEXCAN {
-    alias             { "MCF52xx FlexCAN device drivers"
-                        devs_can_mcf52xx_flexcan mcf52xx_flexcan_serial_driver }
-    hardware
-    directory	      devs/can/m68k/mcf52xx
-    script	          can_mcf52xx.cdl	
-    description       "Generic CAN device driver for the on-chip
-                       FlexCAN modules in MCF52xx ColdFire processors."
-}
-
-package CYGPKG_DEVS_CAN_AT91SAM7 {
-    alias             { "AT91SAM7 CAN device drivers"
-                        devs_can_at91sam7 at91sam7_can_driver }
-    hardware
-    directory	      devs/can/arm/at91/at91sam7
-    script	          can_at91sam7.cdl	
-    description       "Atmel AT91SAM7 on-chip CAN device driver."
-}
-
-package CYGPKG_DEVS_CAN_LPC2XXX {
-    alias             { "LPC2xxx CAN device drivers"
-                        devs_can_lpc2xxx lpc2xxx_can_driver }
-    hardware
-    directory	      devs/can/arm/lpc2xxx
-    script	          can_lpc2xxx.cdl	
-    description       "LPC2xxx on-chip CAN device driver."
-}
-
-package CYGPKG_DEVS_CAN_LOOP {
-    alias             { "Loop CAN device drivers"
-                        devs_can_loop loop_can_driver }
-    directory	      devs/can/loop
-    script	      can_loop.cdl	
-    description       "Loopback CAN device driver."
-}
-
-
-package CYGPKG_IO_PCMCIA {
-	alias 		{ "PCMCIA & Compact Flash support" pcmcia io_pcmcia cf }
-	directory	io/pcmcia
-	script		io_pcmcia.cdl
-        description "
-           This package contains basic card services support for PCMCIA
-           and Compact Flash devices."
-}
-
-package CYGPKG_DEVS_PCMCIA_ASSABET {
-	alias 		{ "SA11x0/Assabet PCMCIA & Compact Flash support" pcmcia_assabet assabet_pcmcia assabet_cf io_assabet_pcmcia}
-	directory	devs/pcmcia/arm/assabet
-	script		pcmcia_assabet.cdl
-	hardware
-        description "
-           This package contains hardware support for PCMCIA
-           and Compact Flash devices on the SA11x0/Assabet board."
-}
-
-package CYGPKG_DEVS_PCMCIA_CERF {
-	alias 		{ "SA11x0/Cerf PCMCIA & Compact Flash support" pcmcia_cerf cerf_pcmcia cerf_cf io_cerf_pcmcia}
-	directory	devs/pcmcia/arm/cerf
-	script		pcmcia_cerf.cdl
-	hardware
-        description "
-           This package contains hardware support for PCMCIA
-           and Compact Flash devices on the SA11x0/Cerf board."
-}
-
-package CYGPKG_DEVS_PCMCIA_CERFPDA {
-	alias 		{ "SA11x0/Cerfpda PCMCIA & Compact Flash support" pcmcia_cerfpda cerfpda_pcmcia cerfpda_cf io_cerfpda_pcmcia}
-	directory	devs/pcmcia/arm/cerfpda
-	script		pcmcia_cerfpda.cdl
-	hardware
-        description "
-           This package contains hardware support for PCMCIA
-           and Compact Flash devices on the SA11x0/Cerfpda."
-}
-
-package CYGPKG_DEVS_PCMCIA_IPAQ {
-        alias           { "SA11x0/iPAQ PCMCIA & Compact Flash support" pcmcia_ipaq ipaq_pcmcia ipaq_cf io_ipaq_pcmcia}
-        directory       devs/pcmcia/arm/ipaq
-        script          pcmcia_ipaq.cdl
-        hardware
-        description "
-           This package contains hardware support for PCMCIA
-           and Compact Flash devices on the Compaq iPAQ pocket PC."
-}
-
-package CYGPKG_IO_FLASH {
-	alias 		{ "Generic FLASH memory support" flash }
-	directory	io/flash
-	script		io_flash.cdl
-        description "
-           This package contains generic support for FLASH memory."
-}
-
-package CYGPKG_DEVS_FLASH_ARM_AAED2000 {
-	alias 		{ "Support for flash memory on Agilent AAED2000 board" flash_aaed2000 }
-	directory	devs/flash/arm/aaed2000
-	script		flash_arm_aaed2000.cdl
-	hardware
-        description "
-           This package contains hardware support for flash memory
-	   on the Agilent AAED2000 platform."
-}
-
-package CYGPKG_DEVS_FLASH_AMD_AM29XXXXX {
-	alias 		{ "Support for AMD AM29xxxxx flash memory (deprecated)" flash_amd_am29xxxxx }
-	directory	devs/flash/amd/am29xxxxx
-	script		flash_amd_am29xxxxx.cdl
-	hardware
-        description "
-           This package contains hardware support for AMD AM29xxxxx
-           flash memory devices."
-}
-
-package CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2 {
-	alias 		{ "Support for AMD AM29xxxxx flash memory" flash_amd_am29xxxxx_v2 }
-	directory	devs/flash/amd/am29xxxxxv2
-	script		flash_am29xxxxx_v2.cdl
-	hardware
-        description "
-           This package contains hardware support for AMD AM29xxxxx
-           flash memory devices."
-}
-
-package CYGPKG_DEVS_FLASH_ATMEL_AT29CXXXX {
-	alias 		{ "Support for Atmel AT29Cxxxx flash memory" flash_atmel_at29cxxxx }
-	directory	devs/flash/atmel/at29cxxxx
-	script		flash_atmel_at29cxxxx.cdl
-	hardware
-        description "
-           This package contains hardware support for Atmel AT29Cxxxx
-           flash memory devices."
-}
-
-package CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX {
-	alias 		{ "Support for Atmel AT49xxxx flash memory" flash_atmel_at49xxxx }
-	directory	devs/flash/atmel/at49xxxx
-	script		flash_atmel_at49xxxx.cdl
-	hardware
-        description "
-           This package contains hardware support for Atmel AT49xxxx
-           flash memory devices."
-}
-
-package CYGPKG_DEVS_FLASH_ATMEL_DATAFLASH {
-    alias       { "Atmel DataFlash support" flash_dataflash dataflash }
-    directory   devs/flash/atmel/dataflash
-    script      devs_flash_atmel_dataflash.cdl
-    hardware
-    description "This package contains hardware support for Atmel DataFlash."
-}
-
-package CYGPKG_DEVS_FLASH_SPI_M25PXX {
-        alias           { "M25Pxx SPI Flash" flash_spi_m25pxx }
-        directory       devs/flash/spi/m25pxx
-        script          flash_m25pxx.cdl
-        hardware
-        description "
-        Support for M25Pxx SPI flash devices."
-}
-
-package CYGPKG_DEVS_FLASH_ARM_PID {
-	alias 		{ "Support for flash memory on ARM/PID board" flash_arm_pid }
-	directory	devs/flash/arm/pid
-	script		flash_arm_pid.cdl
-	hardware
-        description "
-           This package contains hardware support for flash memory
-	   on the ARM PID platform."
-}
-
-package CYGPKG_DEVS_FLASH_ARM_E7T {
-    alias       { "FLASH memory support for the ARM Evaluator-7T" flash_e7t }
-    directory   devs/flash/arm/e7t
-    script      flash_e7t.cdl
-    hardware
-        description "
-           This package contains hardware support for FLASH memory
-       on the ARM Evaluator-7T platform."
-}
-
-package CYGPKG_DEVS_FLASH_EA2468 {
-    alias       { "FLASH memory support for EA LPC2468 OEM board" flash_ea2468 }
-    directory   devs/flash/arm/ea2468
-    script      flash_ea2468.cdl
-    hardware
-        description "
-           This package contains hardware support for FLASH memory
-           on the Embedded Artists LCP2468 OEM board."
-}
-
-package CYGPKG_DEVS_FLASH_SH_EDK7708 {
-	alias 		{ "Support for flash memory on Hitachi/EDK7708 board" flash_sh_edk7708 }
-	directory	devs/flash/sh/edk7708
-	script		flash_sh_edk7708.cdl
-	hardware
-        description "
-           This package contains hardware support for flash memory
-	   on the Hitachi EDK7708 platform."
-}
-
-package CYGPKG_DEVS_FLASH_CQ7750 {
-	alias 		{ "Support for flash memory on CqREEK SH7750 board" flash_cq7750 }
-	directory	devs/flash/sh/cq7750
-	script		flash_cq7750.cdl
-	hardware
-        description "
-           This package contains hardware support for flash memory
-	   on the CqREEK SH7750 platform."
-}
-
-package CYGPKG_DEVS_FLASH_MIPS_OCELOT {
-	alias 		{ "Support for flash memory on PMC-Sierra/Ocelot board" flash_qed_ocelot }
-	directory	devs/flash/mips/ocelot
-	script		flash_mips_ocelot.cdl
-	hardware
-        description "
-           This package contains hardware support for flash memory
-	   on the PMC-Sierra Ocelot platform."
-}
-
-package CYGPKG_DEVS_FLASH_MIPS_VRC437X {
-	alias 		{ "Support for flash memory on VRC437X boards" flash_vrc437x }
-	directory	devs/flash/mips/vrc437x
-	script		flash_mips_vrc437x.cdl
-	hardware
-        description "
-           This package contains hardware support for flash memory
-	   on the VRC437X platform."
-}
-
-package CYGPKG_DEVS_FLASH_MIPS_REFIDT334 {
-	alias 		{ "MIPS IDT 79RC32334 reference platform flash support" flash_refidt334 }
-	directory	devs/flash/mips/idt79s334a
-	script		flash_mips_refidt334.cdl
-	hardware
-        description "
-           This package contains hardware support for flash memory
-	   on the IDT MIPS 334a reference platform."
-}
-
-package CYGPKG_DEVS_FLASH_SH_HS7729PCI {
-        alias           { "Hitachi SH/HS7729PCI FLASH memory support" flash_hs7729pci }
-        directory       devs/flash/sh/hs7729pci
-        script          flash_sh_hs7729pci.cdl
-        hardware
-        description "
-           This package contains hardware support for FLASH memory
-           on the Hitachi/HS7729PCI platform."
-}
-
-package CYGPKG_DEVS_FLASH_SH_SE77X9 {
-        alias           { "Hitachi SH/SE77X9 FLASH memory support" flash_se77x9 }
-        directory       devs/flash/sh/se77x9
-        script          flash_sh_se77x9.cdl
-        hardware
-        description "
-           This package contains hardware support for FLASH memory
-           on the Hitachi/SE77X9 platform."
-}
-
-package CYGPKG_DEVS_FLASH_SH_SE7751 {
-        alias           { "Hitachi SH/SE7751 FLASH memory support" flash_se7751 }
-        directory       devs/flash/sh/se7751
-        script          flash_sh_se7751.cdl
-        hardware
-        description "
-           This package contains hardware support for FLASH memory
-           on the Hitachi/SE7751 platform."
-}
-
-package CYGPKG_DEVS_FLASH_SH_MICRODEV {
-        alias           { "SuperH SH4-202 MicroDev CPU board FLASH memory support" flash_microdev }
-        directory       devs/flash/sh/microdev
-        script          flash_microdev.cdl
-        hardware
-        description "
-           This package contains hardware support for FLASH memory
-           on the SuperH SH4-202 MicroDev CPU board platform."
-}
-
-package CYGPKG_DEVS_FLASH_EBSA285 {
-	alias 		{ "FLASH memory support for StrongARM EBSA-285" flash_ebsa285 }
-	directory	devs/flash/arm/ebsa285
-	script		flash_ebsa285.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the StrongARM EBSA-285 platform."
-}
-
-package CYGPKG_DEVS_FLASH_SA1100MM {
-	alias 		{ "FLASH memory support for StrongARM SA1100 Multimedia" flash_sa1100mm }
-	directory	devs/flash/arm/sa1100mm
-	script		flash_sa1100mm.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the StrongARM SA1100 Multimedia platform."
-}
-
-package CYGPKG_DEVS_FLASH_EDB7XXX {
-	alias 		{ "FLASH support for Cirrus Logic EP7xxx based boards" flash_edb7xxx }
-	directory	devs/flash/arm/edb7xxx
-	script		flash_edb7xxx.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Cirrus Logic EP7xxx based platform(s)."
-}
-
-package CYGPKG_DEVS_FLASH_AT91 {
-	alias 		{ "FLASH memory support for Atmel AT91 EFC" flash_at91 }
-	directory	devs/flash/arm/at91
-	script		flash_at91.cdl
-	hardware
-        description "
-           This package contains hardware support for Embedded FLASH 
-           controller as found in the AT91SAM7S platform"
-}
-
-package CYGPKG_DEVS_FLASH_EB40 {
-	alias 		{ "FLASH memory support for Atmel AT91/EB40" flash_eb40 }
-	directory	devs/flash/arm/eb40
-	script		flash_eb40.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Atmel AT91/EB40 platform(s)."
-}
-
-package CYGPKG_DEVS_FLASH_EB40A {
-	alias 		{ "FLASH memory support for Atmel AT91/EB40A" flash_eb40a }
-	directory	devs/flash/arm/eb40a
-	script		flash_eb40a.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Atmel AT91/EB40A platform(s)."
-}
-
-package CYGPKG_DEVS_FLASH_EB42 {
-	alias 		{ "FLASH memory support for Atmel AT91/EB42" flash_eb42 }
-	directory	devs/flash/arm/eb42
-	script		flash_eb42.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Atmel AT91/EB42 platform(s)."
-}
-
-package CYGPKG_DEVS_FLASH_EB55 {
-	alias 		{ "FLASH memory support for Atmel AT91/EB55" flash_eb55 }
-	directory	devs/flash/arm/eb55
-	script		flash_eb55.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Atmel AT91/EB55 platform(s)."
-}
-
-package CYGPKG_DEVS_FLASH_JTST {
-	alias 		{ "FLASH memory support for Atmel JTST" flash_jtst }
-	directory	devs/flash/arm/jtst
-	script		flash_jtst.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Atmel JTST platform(s)."
-}
-
-package CYGPKG_DEVS_FLASH_PHYCORE {
-	alias 		{ "FLASH memory support for PHYTEC phyCORE AT91M55800A" flash_phycore }
-	directory	devs/flash/arm/phycore
-	script		flash_phycore.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the PHYTEC phyCORE AT91M55800A platform(s)."
-}
-
-package CYGPKG_DEVS_FLASH_PHYCORE229X {
-        alias           { "FLASH memory support for Phytec phyCORE-LPC229x" flash_phycore229x }
-        directory       devs/flash/arm/phycore229x
-        script          flash_phycore229x.cdl
-        hardware
-        description "
-           This package contains hardware support for FLASH memory
-           on the Phytec phyCORE-LPC229x platform(s)."
-}
-
-package CYGPKG_DEVS_FLASH_ASSABET {
-	alias 		{ "FLASH memory support for Intel SA1110 (Assabet)" flash_assabet }
-	directory	devs/flash/arm/assabet
-	script		flash_assabet.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Intel StrongARM SA-1110 Assabet platform."
-}
-
-package CYGPKG_DEVS_FLASH_CERF {
-	alias 		{ "FLASH memory support for Intrinsyc SA1110 (Cerf)" flash_cerf }
-	directory	devs/flash/arm/cerf
-	script		flash_cerf.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Intrinsyc SA1110 Cerf board."
-}
-
-package CYGPKG_DEVS_FLASH_CERFPDA {
-	alias 		{ "FLASH memory support for Intrinsyc SA1110 (Cerfpda)" flash_cerfpda }
-	directory	devs/flash/arm/cerfpda
-	script		flash_cerfpda.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Intrinsyc SA1110 Cerfpda."
-}
-
-package CYGPKG_DEVS_FLASH_IPAQ {
-	alias 		{ "FLASH memory support for Intel SA1110 (Ipaq)" flash_ipaq }
-	directory	devs/flash/arm/ipaq
-	script		flash_ipaq.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Intel StrongARM SA-1110 iPAQ platform."
-}
-
-package CYGPKG_DEVS_FLASH_FLEXANET {
-      alias           { "FLASH memory support for Flexanet" flash_flexanet }
-      directory       devs/flash/arm/flexanet
-      script          flash_flexanet.cdl
-      hardware
-        description "
-           This package contains hardware support for FLASH memory
-           on the SA-1100 Flexanet platform."
-}
-
-package CYGPKG_DEVS_FLASH_MPC50 {
-	alias 		{ "FLASH memory support for MPC 5.0" flash_mpc50 }
-	directory	devs/flash/arm/mpc50
-	script		flash_mpc50.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the MPC 5.0."
-}
-
-package CYGPKG_DEVS_FLASH_MALTA {
-	alias 		{ "FLASH memory support for MIPS Malta board" flash_malta }
-	directory	devs/flash/mips/malta
-	script		flash_malta.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the MIPS Malta platform."
-}
-
-package CYGPKG_DEVS_FLASH_ARM_EXCALIBUR {
-	alias 		{ "FLASH memory support for Altera ARM9/Excalibur board" flash_excalibur }
-	directory	devs/flash/arm/excalibur
-	script		flash_excalibur.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Altera Excalibur platform."
-}
-
-package CYGPKG_DEVS_FLASH_ARM_SMDK2410 {
-        alias           { "FLASH memory support for Samsung ARM9/SMDK2410 board" flash_smdk2410 }
-        directory       devs/flash/arm/smdk2410
-        script          flash_smdk2410.cdl
-        hardware
-        description "
-           This package contains hardware support for FLASH memory
-           on the Samsung smdk2410 platform."
-}
-
-package CYGPKG_DEVS_FLASH_ARM_INNOVATOR {
-	alias 		{ "FLASH memory support for the Innovator" flash_innovator }
-	directory	devs/flash/arm/innovator
-	script		flash_innovator.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Innovator platform."
-}
-
-package CYGPKG_DEVS_FLASH_ARM_AIM711 {
-        alias           { "Support for flash memory on AIM 711 board" flash_arm_snds }
-        directory       devs/flash/arm/aim711
-        script          flash_arm_aim711.cdl
-        hardware
-        description "
-           This package contains hardware support for flash memory
-           on the ARM Industrial Module AIM 711 platform."
-}
-
-package CYGPKG_DEVS_FLASH_NANO {
-	alias 		{ "FLASH memory support for Intel SA1110 nanoEngine" flash_nano }
-	directory	devs/flash/arm/nano
-	script		flash_nano.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the StrongARM SA-1110 nanoEngine platform."
-}
-
-package CYGPKG_DEVS_FLASH_STRATA {
-	alias 		{ "Generic FLASH memory support for Intel StrataFLASH (deprecated)" strata }
-	directory	devs/flash/intel/strata
-	script		flash_strata.cdl
-	hardware
-        description "
-           This package contains generic hardware support for Intel
-	   StrataFLASH memory devices."
-}
-
-package CYGPKG_DEVS_FLASH_STRATA_V2 {
-	alias 		{ "Generic FLASH memory support for Intel StrataFLASH" strata_v2 }
-	directory	devs/flash/intel/stratav2
-	script		flash_strata_v2.cdl
-	hardware
-        description "
-           This package contains generic hardware support for Intel
-	   StrataFLASH memory devices using the V2 device API."
-}
-
-package CYGPKG_DEVS_FLASH_SST_39VFXXX {
-    alias       { "Support for SST 39VFXXX flash memory" flash_sst_39vfXXX }
-    directory   devs/flash/sst/39vfxxx
-    script      flash_sst_39vfxxx.cdl
-    hardware
-        description "
-           This package contains hardware support for SST 39VFxxx
-           flash memory devices. Until now it supports SST 39VF080,
-           39VF016 and 39VF400 devices."
-}
-
-package CYGPKG_DEVS_FLASH_INTEL_28FXXX {
-	alias 		{ "Generic FLASH memory support for Intel 28Fxxx Flash parts" flashfile }
-	directory	devs/flash/intel/28fxxx
-	script		flash_intel_28fxxx.cdl
-	hardware
-        description "
-           This package contains generic hardware support for Intel
-	   Flash memory devices."
-}
-
-package CYGPKG_DEVS_FLASH_ARM_XSCALE_IQ80310 {
-	alias 		{ "FLASH memory support for Cyclone IQ80310" flash_iq80310 }
-	directory	devs/flash/arm/iq80310
-	script		flash_iq80310.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Cyclone IQ80310 platform."
-}
-
-package CYGPKG_DEVS_FLASH_IQ80321 {
-	alias 		{ "FLASH memory support for IQ80321" flash_iq80321 }
-	directory	devs/flash/arm/iq80321
-	script		flash_iq80321.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the IQ80321 platform."
-}
-
-package CYGPKG_DEVS_FLASH_IXDP425 {
-	alias 		{ "FLASH memory support for IXDP425" flash_ixdp425 }
-	directory	devs/flash/arm/ixdp425
-	script		flash_ixdp425.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the IXDP425 platform."
-}
-
-package CYGPKG_DEVS_FLASH_XSENGINE {
-       alias           { "FLASH memory support for XSEngine" flash_xsengine }
-       directory       devs/flash/arm/xsengine
-       script          flash_xsengine.cdl
-       hardware
-       description "
-          This package contains hardware support for FLASH memory
-          on the XSEngine platform."
-}
-
-package CYGPKG_DEVS_FLASH_GRG {
-	alias 		{ "FLASH memory support for GRG" flash_grg }
-	directory	devs/flash/arm/grg
-	script		flash_grg.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Intel Generic Residential Gateway platform."
-}
-
-package CYGPKG_DEVS_FLASH_PRPMC1100 {
-	alias 		{ "FLASH memory support for PrPMC1100" flash_prpmc1100 }
-	directory	devs/flash/arm/prpmc1100
-	script		flash_prpmc1100.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Motorola PrPMC1100 platform."
-}
-
-package CYGPKG_DEVS_FLASH_ARM_INTEGRATOR {
-        alias           { "FLASH memory support for ARM INTEGRATOR" flash_integrator }
-        directory       devs/flash/arm/integrator
-        script          flash_integrator.cdl
-        hardware
-        description "
-           This package contains hardware support for FLASH memory
-           on the ARM INTEGRATOR platform."
-}
-
-package CYGPKG_DEVS_FLASH_MBX {
-	alias 		{ "FLASH memory support for Motorola PowerPC/860 MBX" flash_mbx }
-	directory	devs/flash/powerpc/mbx
-	script		flash_mbx.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Motorola PowerPC/860 MBX platform."
-}
-
-package CYGPKG_DEVS_FLASH_TS6 {
-	alias 		{ "FLASH memory support for Delphi Communication Systems, Inc. TigerSHARC6 Board" flash_ts6 }
-	directory	devs/flash/powerpc/ts6
-	script		flash_ts6.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Delphi Communication Systems TigerSHARC6 platform."
-}
-
-package CYGPKG_DEVS_FLASH_VADS {
-	alias 		{ "FLASH memory support for Motorola MPC8260 Voyager ADS board" flash_vads }
-	directory	devs/flash/powerpc/vads
-	script		flash_vads.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Motorola MPC8260 Voyager ADS platform."
-}
-
-package CYGPKG_DEVS_FLASH_CME555 {
-	alias 		{ "FLASH memory support for Axiom's CME555" flash_cme555 }
-	directory	devs/flash/powerpc/cme555
-	script		flash_cme555.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on Axiom's CME555 board."
-}
-
-package CYGPKG_DEVS_FLASH_EC555 {
-	alias 		{ "FLASH memory support for ec555 board" flash_ec555 }
-	directory	devs/flash/powerpc/ec555
-	script		flash_ec555.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the ec555 board."
-}
-
-package CYGPKG_DEVS_FLASH_PATI {
-       alias           { "FLASH memory support for PowerPC PATI board" flash_pati }
-       directory       devs/flash/powerpc/pati
-       script          flash_pati.cdl
-       hardware
-        description "
-           This package contains hardware support for FLASH memory
-           on the PowerPC PATI platform."
-}
-
-package CYGPKG_DEVS_FLASH_VIPER {
-	alias 		{ "FLASH memory support for A&M Viper PowerPC/8xx" flash_viper }
-	directory	devs/flash/powerpc/viper
-	script		flash_viper.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the A&M PowerPC/8xx VIPER platform."
-}
-
-package CYGPKG_DEVS_FLASH_MN10300_STB {
-	alias 		{ "FLASH memory support for Matsushita MN10300 STB" flash_stb }
-	directory	devs/flash/mn10300/stb
-	script		flash_stb.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Matsushita MN10300 STB platform (SRAM2 socket)."
-}
-
-package CYGPKG_DEVS_FLASH_MN10300_ASB2303 {
-	alias 		{ "FLASH memory support for Matsushita ASB2303" flash_asb2303 }
-	directory	devs/flash/mn10300/asb2303
-	script		flash_asb2303.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Matsushita MN10300 ASB2303 platform (system flash socket)."
-}
-
-package CYGPKG_DEVS_FLASH_MN10300_ASB2305 {
-	alias 		{ "FLASH memory support for Matsushita ASB2305" flash_asb2305 }
-	directory	devs/flash/mn10300/asb2305
-	script		flash_asb2305.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Matsushita MN10300 ASB2305 platform (system flash socket)."
-}
-
-package CYGPKG_DEVS_FLASH_ATLAS {
-	alias 		{ "FLASH memory support for MIPS Atlas" flash_atlas }
-	directory	devs/flash/mips/atlas
-	script		flash_atlas.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the MIPS Atlas platform."
-}
-package CYGPKG_DEVS_FLASH_SYNTH {
-    alias               { "Synthetic FLASH memory support (legacy)" synth_flash flash_synth }
-    directory           devs/flash/synth
-    script              flash_synth.cdl
-    hardware
-    description   "
-        FLASH memory device support for Synthetic target"
-}
-
-package CYGPKG_DEVS_FLASH_SYNTH_V2 {
-    alias               { "Synthetic FLASH memory support" synth_flashv2 flash_synthv2 }
-    directory           devs/flash/synthv2
-    script              flash_synth.cdl
-    hardware
-    description   "
-        FLASH memory device support for Synthetic target using the new API"
-}
-
-package CYGPKG_DEVS_FLASH_TOSHIBA_TC58XXX {
-	alias 		{ "Support for Toshiba TC58xxx flash memory" flash_toshiba_tc58xxx }
-	directory	devs/flash/toshiba/tc58xxx
-	script		flash_toshiba_tc58xxx.cdl
-	hardware
-        description "
-           This package contains hardware support for Toshiba TC58xxx
-           NAND flash memory devices."
-}
-
-package CYGPKG_DEVS_FLASH_FRV_FRV400 {
-        alias           { "Fujitsu FRV400 FLASH memory support" flash_frv400 }
-        directory       devs/flash/frv/frv400
-        script          flash_frv_frv400.cdl
-        hardware
-        description "
-           This package contains hardware support for FLASH memory
-           on the Fujitsu FRV400 platform."
-}
-
-package CYGPKG_DEVS_FLASH_FRV_PDK403 {
-        alias           { "Fujitsu MB93093 FLASH memory support" flash_mb93093 }
-        directory       devs/flash/frv/pdk403
-        script          flash_frv_pdk403.cdl
-        hardware
-        description "
-           This package contains hardware support for FLASH memory
-           on the Fujitsu MB93093-PD00 Portable Development Kit."
-}
-
-package CYGPKG_DEVS_FLASH_ARM_LPC2XXX {
-        alias           { "Support for the internal flash memory of LPC2xxx devices" flash_arm_lpc2xxx }
-        directory       devs/flash/arm/lpc2xxx
-        script          flash_arm_lpc2xxx.cdl
-        hardware
-        description     "
-           This package contains hardware support for the internal
-           flash memory of the LPC2xxx devices."
-}
-
-package CYGPKG_DEVS_FLASH_ARM_OLPCX2294 {
-        alias           { "Support for Flash memory on Olimex LPC-E2294, LPC-H2294, LPC-L2294-1M boards" flash_olpcx2294 }
-        directory       devs/flash/arm/olpcx2294
-        script          flash_olpcx2294.cdl
-        hardware
-        description "
-        This package contains hardware support for flash memory parts
-        on the Olimex LPC-E2294, LPC-H2294 LPC-L2294-1M platforms."
-
-}
-
-package CYGPKG_DEVS_FLASH_ARM_OLPCX2294_V2 {
-        alias           { "External Flash memory support for OLPCE2294, OLPCH2294, OLPCL2294" flash_olpcx2294_v2 }
-        directory       devs/flash/arm/olpcx2294v2
-        script          flash_olpcx2294.cdl
-        hardware
-        description "
-            The flash_olpcx2294_v2 provides hardware support for external
-            flash memory parts on the Olimex LPC-E2294, LPC-H2294,
-            and LPC-L2294-1M boards. It uses eCos Flash v2 API."
-}
-
-package CYGPKG_DEVS_TOUCH_IPAQ {
-	alias 		{ "Touch screen support for iPAQ" touch_ipaq }
-	directory	devs/touch/arm/ipaq
-	script		touch_ipaq.cdl
-	hardware
-        description "
-           This package contains hardware support for the touch screen
-	   on the Compaq iPAQ Pocket PC."
-}
-
-package CYGPKG_DEVS_KBD_IPAQ {
-	alias 		{ "Keypad/button support for iPAQ" kbd_ipaq }
-	directory	devs/kbd/arm/ipaq
-	script		kbd_ipaq.cdl
-	hardware
-        description "
-           This package contains hardware support for the keyboard buttons
-	   on the Compaq iPAQ Pocket PC."
-}
-
-package CYGPKG_DEVS_TOUCH_AAED2000 {
-	alias 		{ "Touch screen support for Agilent AAED2000" touch_aaed2000 }
-	directory	devs/touch/arm/aaed2000
-	script		touch_aaed2000.cdl
-	hardware
-        description "
-           This package contains hardware support for the touch screen
-	   on the Agilent AAED2000 prototype."
-}
-
-package CYGPKG_DEVS_KBD_AAED2000 {
-	alias 		{ "Keyboard support for Agilent AAED2000" kbd_aaed2000 }
-	directory	devs/kbd/arm/aaed2000
-	script		kbd_aaed2000.cdl
-	hardware
-        description "
-           This package contains hardware support for the keyboard
-	   on the Agilent AAED2000 prototype."
-}
-
-package CYGPKG_IO_SERIAL_ARM_EBSA285 {
-    alias 	      { "Intel EBSA285 serial driver"
-                        devs_serial_arm_ebsa285 ebsa285_serial_driver }
-    hardware
-    directory	      devs/serial/arm/ebsa285
-    script	      ser_arm_ebsa285.cdl	
-    description       "Intel StrongARM/EBSA285 serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_ARM_XSCALE_PXA2X0 {
-    alias         { "Intel XScale PXA2X0 serial driver"
-                        devs_serial_arm_xscale_pxa pxa_serial_driver }
-    hardware
-    directory        devs/serial/arm/pxa2x0
-    script        ser_arm_xscale_pxa2x0.cdl
-    description       "Intel XScale/PXA2X0 serial device drivers"
-}
-
-
-package CYGPKG_IO_SERIAL_ARM_XSCALE_IOP310 {
-    alias 	      { "Intel XScale IOP310 serial driver"
-                        devs_serial_arm_iop310 iop310_serial_driver }
-    hardware
-    directory	      devs/serial/arm/iop310
-    script	      ser_arm_iop310.cdl	
-    description       "Intel XScale IOP310 serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_ARM_IQ80321 {
-    alias 	      { "Intel XScale IQ80321 serial driver"
-                        devs_serial_arm_iq80321 iq80321_serial_driver }
-    hardware
-    directory	      devs/serial/arm/iq80321
-    script	      ser_arm_iq80321.cdl	
-    description       "Intel XScale/IQ80321 serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_ARM_SA11X0 {
-    alias 	      { "Intel StrongARM SA11x0 serial driver"
-                        devs_serial_arm_sa11x0 sa11x0_serial_driver }
-    hardware
-    directory	      devs/serial/arm/sa11x0
-    script	      ser_arm_sa11x0.cdl	
-    description       "Intel StrongARM/SA11x0 serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_ARM_PID {
-    alias             { "ARM PID serial device drivers"
-                        devs_serial_arm_pid pid_serial_driver }
-    hardware
-    directory	      devs/serial/arm/pid
-    script	      ser_arm_pid.cdl	
-    description       "ARM PID serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_ARM_CERFPDA {
-    alias             { "Cerfpda 16x5x serial device drivers"
-                        devs_serial_arm_cerfpda cerfpda_serial_driver }
-    hardware
-    directory	      devs/serial/arm/cerfpda
-    script	      ser_arm_cerfpda.cdl	
-    description       "Cerfpda serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_ARM_AEB {
-    alias             { "ARM AEB-1 serial device drivers"
-                        devs_serial_arm_aeb aeb_serial_driver }
-    hardware
-    directory	      devs/serial/arm/aeb
-    script	      ser_arm_aeb.cdl	
-    description       "ARM AEB-1 serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_ARM_AAED2000 {
-    alias             { "Agilent AAED2000 serial device drivers"
-                        devs_serial_arm_aaed2000 aaed2000_serial_driver }
-    hardware
-    directory	      devs/serial/arm/aaed2000
-    script	      ser_arm_aaed2000.cdl
-    description       "Agilent AAED2000 serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_ARM_SMDK2410 {
-    alias             { "Samsung ARM9/SMDK2410 board serial device drivers"
-                        devs_serial_arm_smdk2410 smdk2410_serial_driver }
-    hardware
-    directory         devs/serial/arm/smdk2410
-    script            ser_arm_smdk2410.cdl        
-    description       "Samsung ARM9/SMDK2410 board serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_ARM_EDB7XXX {
-    alias             { "Cirrus Logic ARM based board serial device drivers"
-                        devs_serial_arm_edb7xxx edb7xxx_serial_driver }
-    hardware
-    directory	      devs/serial/arm/edb7xxx
-    script	      ser_arm_edb7xxx.cdl	
-    description       "Cirrus Logic ARM based development board serial
-                       device drivers"
-}
-
-package CYGPKG_IO_SERIAL_ARM_CMA230 {
-    alias             { "Cogent ARM/CMA230 serial device drivers"
-                        devs_serial_arm_cma230 cma230_serial_driver }
-    hardware
-    directory	      devs/serial/arm/cma230
-    script	      ser_arm_cma230.cdl	
-    description       "Cogent ARM/CMA230 serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_ARM_E7T {
-    alias             { "ARM AEB-2 (E7T) serial device drivers"
-                        devs_serial_arm_e7t e7t_serial_driver }
-    hardware
-    directory         devs/serial/arm/e7t
-    script            ser_arm_e7t.cdl   
-    description       "ARM AEB-2 (E7T) serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_ARM_S3C4510 {
-    alias             { "Generig ARM S3C4510 serial device driver"
-                        devs_serial_arm_s3c4510 s3c4510_serial_driver }
-    hardware
-    directory         devs/serial/arm/s3c4510
-    script            ser_arm_s3c4510.cdl
-    description       "Generic serial device driver for the internal
-                       serial interface of the S3C4510"
-}
-
-package CYGPKG_IO_SERIAL_ARM_AIM711 {
-    alias             { "AIM 711 serial device drivers"
-                        devs_serial_arm_aim711 aim711_serial_driver }
-    hardware
-    directory         devs/serial/arm/aim711
-    script            ser_arm_aim711.cdl
-    description       "ARM Industral Module AIM 711 serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_ARM_INTEGRATOR {
-    alias             { "ARM INTEGRATOR serial device drivers"
-                        devs_serial_arm_integrator integrator_serial_driver }
-    hardware
-    directory         devs/serial/arm/integrator
-    script            ser_arm_integrator.cdl    
-    description       "ARM INTEGRATOR serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_ARM_AT91 {
-    alias 	      { "Atmel AT91 serial device driver"
-                        devs_serial_arm_at91 at91_serial_driver }
-    hardware
-    directory	      devs/serial/arm/at91
-    script	      ser_arm_at91.cdl	
-    description       "Atmel AT91 on-chip serial device driver."
-}
-
-package CYGPKG_IO_SERIAL_ARM_LPC2XXX {
-    alias             { "ARM LPC2XXX serial device drivers"
-                        devs_serial_arm_lpc2xxx lpc2xxx_serial_driver }
-    hardware
-    directory         devs/serial/arm/lpc2xxx
-    script            ser_arm_lpc2xxx.cdl
-    description       "ARM LPC2XXX serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_ARM_LPC24XX {
-    alias             { "ARM LPC24XX serial device drivers"
-                        devs_serial_arm_lpc24xx lpc24xx_serial_driver }
-    hardware
-    directory         devs/serial/arm/lpc24xx
-    script            ser_arm_lpc24xx.cdl
-    description       "ARM LPC24XX serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_POWERPC_COGENT {
-    alias             { "Cogent PowerPC serial device drivers"
-                        devs_serial_powerpc_cogent cogent_serial_driver }
-    hardware
-    directory	      devs/serial/powerpc/cogent
-    script	      ser_powerpc_cogent.cdl	
-    description       "Cogent PowerPC serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_POWERPC_MPC555 {
-    alias             { "mpc555 PowerPC serial device drivers"
-                        devs_serial_powerpc_mpc555 mpc555_serial_driver }
-    hardware
-    directory	      devs/serial/powerpc/mpc555
-    script	      ser_powerpc_mpc555.cdl	
-    description       "mpc555 PowerPC serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_FREESCALE_ESCI_H {
-    alias             { "ESCI serial device header"
-                        devs_serial_freescale_esci_h esci_serial_header }
-    hardware
-    directory	      devs/serial/freescale/esci/hdr
-    script	      ser_freescale_esci_h.cdl	
-    description       "Freescale eSCI - Enhanced Serial Communications Interface header.
-                       Needed by hal_diag and ser_esci drivers."
-}
-
-package CYGPKG_IO_SERIAL_FREESCALE_ESCI {
-    alias             { "ESCI serial device driver"
-                        devs_serial_freescale_esci esci_serial_driver }
-    hardware
-    directory	      devs/serial/freescale/esci/drv
-    script	      ser_freescale_esci.cdl	
-    description       "Freescale eSCI - Enhanced Serial Communications Interface serial device driver"
-}
-
-package CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC {
-    alias             { "PowerPC QUICC/SMC serial device drivers"
-                        devs_serial_quicc_smc quicc_smc_serial_driver
-                        devs_serial_powerpc_quicc_smc
-                        devs_serial_powerpc_quicc quicc_serial_driver }
-    hardware
-    directory	      devs/serial/powerpc/quicc
-    script	      ser_quicc_smc.cdl	
-    description       "PowerPC QUICC/SMC serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_POWERPC_MPC8XXX {
-    alias             { "PowerPC MPC8XXX (QUICC-II) serial device drivers"
-                        devs_serial_powerpc_mpc8xxx mpc8xxx_serial_driver }
-    hardware
-    directory	      devs/serial/powerpc/mpc8xxx
-    script	      ser_mpc8xxx.cdl	
-    description       "PowerPC MPC8XXX (QUICC-II) serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC {
-    alias             { "PowerPC VADS QUICC2/SCC serial device drivers"
-                        devs_serial_quicc2_scc quicc2_scc_serial_driver
-                        devs_serial_powerpc_quicc2_scc
-                        devs_serial_powerpc_quicc2 quicc2_serial_driver }
-    hardware
-    directory	      devs/serial/powerpc/quicc2
-    script	      ser_quicc2_scc.cdl	
-    description       "PowerPC VADS QUICC2/SCC serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_POWERPC_PPC405 {
-    alias             { "PowerPC PPC405GP serial device drivers" devs_serial_ppc405 }
-    hardware
-    directory	      devs/serial/powerpc/ppc405
-    script	      ser_powerpc_ppc405.cdl	
-    description       "PowerPC PPC405GP serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_SPARCLITE_SLEB {
-    alias             { "SPARClite SLEB serial device drivers"
-                        devs_serial_sparclite_sleb sleb_serial_driver }
-    hardware
-    directory	      devs/serial/sparclite/sleb
-    script	      ser_sparclite_sleb.cdl	
-    description       "SPARClite SLEB serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_TX39_JMR3904 {
-    alias             { "TX39 JMR3904 serial device drivers"
-                        devs_serial_tx39_jmr3904 jmr3904_serial_driver
-                        devs_serial_mips_jmr3904 tx3904_serial_driver }
-    hardware
-    directory	      devs/serial/mips/jmr3904
-    script	      ser_mips_jmr3904.cdl	
-    description       "TX39 JMR3904 serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_MIPS_ATLAS {
-    alias             { "Atlas serial device drivers"
-                        devs_serial_atlas atlas_serial_driver
-                        devs_serial_mips_atlas mips_atlas_serial_driver }
-    hardware
-    directory	      devs/serial/mips/atlas
-    script	      ser_mips_atlas.cdl	
-    description       "Atlas serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_MIPS_REF4955 {
-    alias             { "TX49 REF4955 serial device drivers"
-                        devs_serial_mips_ref4955 ref4955_serial_driver }
-    hardware
-    directory	      devs/serial/mips/ref4955
-    script	      ser_mips_ref4955.cdl	
-    description       "TX49 REF4955 serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_MIPS_VRC437X {
-    alias             { "VRC437X serial device drivers"
-                        devs_serial_mips_vrc437x vrc437x_serial_driver }
-    hardware
-    directory	      devs/serial/mips/vrc437x
-    script	      ser_mips_vrc437x.cdl	
-    description       "VRC437X serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_MN10300 {
-    alias             { "MN10300 serial device drivers"
-                        devs_serial_mn10300_mn10300
-                        devs_serial_mn10300 mn10300_serial_driver }
-    hardware
-    directory	      devs/serial/mn10300/mn10300
-    script	      ser_mn10300.cdl	
-    description       "MN10300 serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_I386_PC {
-    alias             { "PC serial device drivers"
-                        devs_serial_i386_pc pc_serial_driver }
-    hardware
-    directory	      devs/serial/i386/pc
-    script	      ser_i386_pc.cdl	
-    description       "PC serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_GENERIC_16X5X {
-    alias             { "16x5x compatible serial device drivers"
-                        devs_serial_generic_16x5x 16x5x_serial_driver }
-    hardware
-    directory	      devs/serial/generic/16x5x
-    script	      ser_generic_16x5x.cdl
-    description       "16x5x compatible serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_SH_SCI {
-    alias             { "SH SCI serial device drivers"
-                        devs_serial_sh_sci sh_sci_serial_driver }
-    hardware
-    directory	      devs/serial/sh/sci
-    script	      ser_sh_sci.cdl	
-    description       "SH SCI serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_SH_SCIF {
-    alias             { "SH SCIF serial device drivers"
-                        devs_serial_sh_scif scif_serial_driver }
-    hardware
-    directory	      devs/serial/sh/scif
-    script	      ser_sh_scif.cdl	
-    description       "SH SCIF serial device drivers"
-}
-
-package CYGPKG_DEVS_ETH_PHY {
-	alias 		{ "Generic PHY support" eth_phy_support }
-	hardware
-	directory	devs/eth/phy
-	script		phy_eth_drivers.cdl
-        description     "PHY (ethernet physical transciever) API."
-}
-
-package CYGPKG_DEVS_ETH_ARM_CERF {
-	alias 		{ "Crystal LAN ethernet driver for Cerf boards" cerf_eth_driver }
-	hardware
-	directory	devs/eth/arm/cerf
-	script		cerf_eth_drivers.cdl
-        description     "Ethernet driver for Crystal LAN on Cerf based
-                         development boards."
-}
-
-package CYGPKG_DEVS_ETH_ARM_CERFPDA {
-	alias 		{ "Crystal LAN ethernet driver for the Cerfpda" cerfpda_eth_driver }
-	hardware
-	directory	devs/eth/arm/cerfpda
-	script		cerfpda_eth_drivers.cdl
-        description     "Ethernet driver for Crystal LAN on the Cerfpda."
-}
-
-package CYGPKG_DEVS_ETH_ARM_NETARM {
-	alias 		{ "Ethernet driver for the NETARM" NETARM_eth_driver }
-	hardware
-	directory	devs/eth/arm/netarm
-	script		netarm_eth_driver.cdl
-        description     "Ethernet driver for NETARM."
-}
-
-package CYGPKG_DEVS_ETH_ARM_PHYCORE229X {
-      alias           { "Ethernet driver for phyCORE-LPC229x board" devs_eth_arm_phycore229x }
-      hardware
-      directory       devs/eth/arm/phycore229x
-      script          phycore229x_eth_drivers.cdl
-      description     "Ethernet device driver for phyCORE-LPC229x board"
-}
-
-package CYGPKG_DEVS_ETH_ARM_OLPCE2294 {
-        alias           { "Ethernet driver for Olimex LPC-E2294 board" olpce2294_eth_driver }
-        hardware
-        directory       devs/eth/arm/olpce2294
-        script          olpce2294_eth_drivers.cdl
-        description     "
-            Ethernet device driver for Olimex LPC-E2294 board."
-}
-
-package CYGPKG_DEVS_ETH_ARM_OLPCL2294 {
-        alias           { "Ethernet driver for Olimex LPC-L2294-1MB board" olpcl2294_eth_driver }
-        hardware
-        directory       devs/eth/arm/olpcl2294
-        script          olpcl2294_eth_drivers.cdl
-        description     "
-            Ethernet device driver for Olimex LPC-L2294-1MB board."
-}
-
-package CYGPKG_IO_SERIAL_SH_EDK7708 {
-    alias             { "SH3 EDK7708 serial device drivers"
-                        devs_serial_sh3_edk7708
-                        devs_serial_sh_edk7708 edk7708_serial_driver }
-    hardware
-    directory	      devs/serial/sh/edk7708
-    script	      ser_sh_edk7708.cdl	
-    description       "SH3 EDK7708 serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_SH_CQ7708 {
-    alias             { "SH3 cq7708 serial device drivers"
-                        devs_serial_sh3_cq7708
-                        devs_serial_sh_cq7708 cq7708_serial_driver }
-    hardware
-    directory	      devs/serial/sh/cq7708
-    script	      ser_sh_cq7708.cdl	
-    description       "SH3 cq7708 serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_SH_SE77X9 {
-    alias             { "SH3 SE77X9 serial device driver"
-                        devs_serial_sh3_se77x9 se77x9_serial_driver }
-    hardware
-    directory	      devs/serial/sh/se77x9
-    script	      ser_sh_se77x9.cdl	
-    description       "SH3 SE77x9 serial device driver"
-}
-
-package CYGPKG_IO_SERIAL_SH_SH4_202_MD {
-    alias             { "SH4-202 MicroDev serial device driver"
-                        devs_serial_sh4_202_md sh4_202_md_serial_driver }
-    hardware
-    directory	      devs/serial/sh/sh4_202_md
-    script	      ser_sh4_202_md.cdl	
-    description       "This option enables the serial device drivers for the
-        SuperH SH4-202 MicroDev board, based on the generic SH SCIF driver."
-}
-
-package CYGPKG_IO_SERIAL_V85X_V850 {
-    alias             { "NEC V850 serial device drivers"
-                        devs_serial_v85x_v850 v850_serial_driver }
-    hardware
-    directory	      devs/serial/v85x/v850
-    script	      ser_v85x_v850.cdl	
-    description       "Serial device drivers for systems based on NEC V850
-                       SA1 (70F3017) or SB1 (70F3033) processors."
-}
-
-package CYGPKG_IO_SERIAL_MIPS_UPD985XX {
-    alias 	      { "NEC MIPS uPD985xx serial driver"
-                        devs_serial_mips_upd985xx upd985xx_serial_driver }
-    hardware
-    directory	      devs/serial/mips/upd985xx
-    script	      ser_mips_upd985xx.cdl	
-    description       "NEC MIPS uPD985xx serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_MIPS_IDT79S334A {
-    alias             { "MIPS IDT 79RC32334 reference platform serial device drivers"
-                        devs_serial_idt79s334a idt79s334a_serial_driver
-                        devs_serial_mips_idt79s334 mips_idt79s334a_serial_driver }
-    hardware
-    directory	      devs/serial/mips/idt79s334a
-    script	      ser_mipsidt_334a.cdl	
-    description       "IDT 334a reference platform serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_H8300_SCI {
-    alias             { "H8/300 SCI serial device drivers"
-                        devs_serial_h8300h_sci h8300h_sci_serial_driver }
-    hardware
-    directory       devs/serial/h8300/h8300h
-    script          serial_h8300.cdl  
-    description       "H8/300 SCI serial device drivers"
-}
-
-package CYGPKG_IO_SERIAL_MCF5272_UART {
-    alias             { "MCF5272 Serial UART Drivers"
-                         devs_MCF5272_uart_driver }
-    hardware
-    directory	      devs/serial/mcf52xx/mcf5272
-    script	      ser_mcf5272_uart.cdl	
-    description       "Serial MCF5272 UART Drivers."
-}
-
-package CYGPKG_IO_SERIAL_LOOP {
-    alias             { "Loop serial device drivers"
-                        devs_serial_loop loop_serial_driver }
-    directory	      devs/serial/loop
-    script	      ser_loop.cdl	
-    description       "Loopback serial device driver."
-}
-
-package CYGPKG_IO_FILEIO {
-	alias 		{ "File IO" fileio io_file }
-	directory	io/fileio
-	script		fileio.cdl
-        description "
-	   This package contains the infrastructure for doing POSIX compliant
-	   file IO."
-}
-
-package CYGPKG_FS_RAM {
-	alias 		{ "RAM Filesystem" ramfs ram_fs fs_ram }
-	directory	fs/ram
-	script		ramfs.cdl
-        description "
-	   This package contains a RAM resident filesystem."
-}
-
-package CYGPKG_FS_ROM {
-	alias 		{ "ROM Filesystem" romfs rom_fs fs_rom }
-	directory	fs/rom
-	script		romfs.cdl
-        description "
-	   This package contains a ROM resident filesystem."
-}
-
-package CYGPKG_FS_JFFS2 {
-	alias 		{ "JFFS2 Filesystem" jffs2 }
-	directory	fs/jffs2
-	script		jffs2.cdl
-        description "
-	   This package contains the JFFS2 filesystem."
-}
-
-package CYGPKG_LINUX_COMPAT {
-        alias           { "Linux compatibility" linux_compat linuxcompat }
-        directory       compat/linux
-        script          linux.cdl
-        description "
-eCos supports a basic Linux compatibility Layer providing various
-functions, equivalents or stubs expected by Linux kernel code, for
-assistance in porting drivers and file system code from Linux.
-Note this does not provide Linux compatibility to applications."
-}
-
-package CYGPKG_IO_ETH_DRIVERS {
-	alias 		{ "Common ethernet support" net_drivers eth_drivers CYGPKG_NET_ETH_DRIVERS }
-	directory	io/eth
-	script		eth_drivers.cdl
-        description     "Platform independent ethernet support."
-}
-
-package CYGPKG_IO_USB { 
-        alias           { "Generic USB support" usb }
-        hardware
-        directory       io/usb/common
-        script          usb.cdl
-        description     "Generic USB support"
-}
-
-package CYGPKG_IO_USB_SLAVE {
-	alias           { "Generic USB slave-side support" usbs }
-        hardware
-        directory       io/usb/slave
-        script          usbs.cdl
-	description     "Generic USB slave-side support"
-}
-
-package CYGPKG_IO_USB_SLAVE_ETH {
-        alias		{ "USB slave-side ethernet class drivers" usbs_eth }
-        directory       io/usb/eth/slave
-        script          usbs_eth.cdl
-        description     "Support for USB peripherals that provide an ethernet-class function"
-}
-
-package CYGPKG_IO_USB_SLAVE_SERIAL {
-        alias		{ "USB slave-side serial drivers" usbs_serial }
-        directory       io/usb/serial/slave
-        script          usbs_serial.cdl
-        description     "Support for USB peripherals that present themselves 
-                         as serial devices to the host."
-}
-
-package CYGPKG_DEVS_USB_SA11X0 {
-        alias           { "Device-driver for the SA11X0 on-chip USB support" usb_sa11x0 }
-        hardware
-        directory       devs/usb/sa11x0
-        script          usbs_sa11x0.cdl
-        description     "A device driver for the SA11X0 on-chip USB slave port"
-}
-
-package CYGPKG_DEVS_USB_UPD985XX {
-        alias           { usb_upd985xx }
-        hardware
-        directory       devs/usb/nec_upd985xx
-        script          usbs_upd985xx.cdl
-        description     "A device driver for the NEC uPD985xx on-chip USB device"
-}
-
-package CYGPKG_DEVS_USB_AT91 {
-        alias           { usb_at91 }
-        hardware
-        directory       devs/usb/at91
-        script          usbs_at91.cdl
-        description     "A device driver for the ATMEL AT91 on-chip USB device"
-}
-
-package CYGPKG_DEVS_USB_D12 {
-	alias           { usb_d12 }
-	hardware
-	directory       devs/usb/d12
-	script          usbs_d12.cdl
-	description     "A device driver for the Philips PDIUSBD12 full speed USB peripheral chip."
-}
-
-package CYGPKG_DEVS_USB_I386_SOROD12 {
-	alias           { usb_sorod12 }
-	hardware
-	directory       devs/usb/i386/SoRoD12
-	script          usbs_i386_sorod12.cdl
-	description     "A device driver for the SoRo PC/104 D12 USB Slave Board."
-}
-
-package CYGPKG_NET {
-	alias 		{ "Networking" net }
-	directory	net/common
-	script		net.cdl
-        description     "Generic networking support, including TCP/IP."
-}
-
-package CYGPKG_NET_AUTOTEST {
-	alias 		{ "Network Autotesting" autotest net_autotest }
-	directory	net/autotest
-	script		net_autotest.cdl
-        description     "Automated network testing support."
-}
-
-package CYGPKG_NET_OPENBSD_STACK {
-	alias 		{ "OpenBSD Stack" openbsd_net }
-	directory	net/tcpip
-	script		openbsd_net.cdl
-        description     "TCP/IP stack from OpenBSD."
-}
-
-package CYGPKG_NET_FREEBSD_STACK {
-	alias 		{ "FreeBSD Stack" freebsd_net }
-	directory	net/bsd_tcpip
-	script		freebsd_net.cdl
-        description     "TCP/IP stack from FreeBSD, including KAME IPv6."
-}
-
-package CYGPKG_NET_FTPCLIENT {
-        alias           { "FTP Client" ftpclient }
-        directory       net/ftpclient
-        script          ftpclient.cdl
-        description     "FTP client support for get and put of files."
-}
-
-package CYGPKG_SNMPLIB {
-	alias 		{ "SNMP library" snmplib }
-	directory	net/snmp/lib
-	script		snmplib.cdl
-        description     "UCD SNMP library."
-}
-
-package CYGPKG_SNMPAGENT {
-	alias 		{ "SNMP agent" snmpagent }
-	directory	net/snmp/agent
-	script		snmpagent.cdl
-        description     "UCD SNMP agent."
-}
-
-package CYGPKG_HTTPD {
-	alias 		{ "HTTP server" httpd }
-	directory	net/httpd
-	script		httpd.cdl
-        description     "HTTP server."
-}
-
-package CYGPKG_NS_DNS {
-	alias 		{ "DNS" dns }
-	directory	net/ns/dns
-	script		dns.cdl
-        description     "DNS client support."
-}
-
-package CYGPKG_NET_SNTP {
-        alias           { "SNTP support" sntp }
-        directory       net/sntp
-        script          sntp.cdl
-        description "
-This package provides a SNTP client which can recieve broadcast time 
-information and set the system clock."
-}  
-
-package CYGPKG_PPP {
-	alias 		{ "PPP support" ppp }
-	directory	net/ppp
-	script		ppp.cdl
-        description     "PPP support."
-}
-
-package CYGPKG_NET_IPSEC_LIBIPSEC {
-        alias           { "libipsec support" libipsec }
-        directory       net/ipsec/libipsec
-        script          libipsec.cdl
-        description "
-This package provides the libipsec library used by racoon etc for 
-configuring IPSEC"
-}
-
-package CYGPKG_DEVS_ETH_ARM_EDB7XXX {
-	alias 		{ "Cirrus Logic ethernet driver for EP7xxx boards" edb7xxx_eth_driver }
-	hardware
-	directory	devs/eth/arm/edb7xxx
-	script		edb7xxx_eth_drivers.cdl
-        description     "Ethernet driver for Cirrus Logic EP7xxx based
-                         development boards."
-}
-
-package CYGPKG_DEVS_ETH_ARM_KS32C5000 {
-	alias 		{ "Samsung KS32C5000 ethernet driver" eth_ks32c5000 }
-	hardware
-	directory	devs/eth/arm/ks32c5000
-	script		ks32c5000_eth.cdl
-        description     "Ethernet driver for Samsung ks32c5000/S3c4510."
-}
-
-
-package CYGPKG_DEVS_ETH_ARM_AAED2000 {
-	alias 		{ "Ethernet driver for Agilent AAED2000 board" aaed2000_eth_driver }
-	hardware
-	directory	devs/eth/arm/aaed2000
-	script		aaed2000_eth_drivers.cdl
-        description     "Ethernet driver for Agilent AAED2000
-                         development boards."
-}
-package CYGPKG_DEVS_ETH_AMD_PCNET {
-	alias 		{ "AMD PCNET ethernet driver" pcnet_eth_driver }
-	hardware
-	directory	devs/eth/amd/pcnet
-	script		amd_pcnet_eth_drivers.cdl
-        description     "Ethernet driver for AMD PCNET controller."
-}
-
-package CYGPKG_DEVS_ETH_AMD_LANCEPCI {
-	alias 		{ "AMD Lance PCI ethernet driver" lancepci_eth_driver }
-	hardware
-	directory	devs/eth/amd/lancepci
-	script		amd_lancepci_eth_drivers.cdl
-        description     "Ethernet driver for AMD Lance PCI controller (vmWare)."
-}
-
-package CYGPKG_DEVS_ETH_DAVICOM_DM9000 {
-	alias 		{ "Davicom DM9000 ethernet driver" dm9000_eth_driver }
-	hardware
-	directory	devs/eth/davicom/dm9000
-	script		davicom_dm9000_eth_drivers.cdl
-        description     "Ethernet driver for Davicom DM9000 controller."
-}
-
-package CYGPKG_DEVS_ETH_MIPS_MIPS32_MALTA {
-	alias 		{ "MIPS Malta board ethernet driver" malta_eth_driver }
-	hardware
-	directory	devs/eth/mips/malta
-	script		mips_mips32_malta_eth_drivers.cdl
-        description     "Ethernet driver for MIPS Malta board."
-}
-
-package CYGPKG_DEVS_ETH_MN10300_ASB2305 {
-	alias 		{ "MN10300 ASB2305 board ethernet driver" asb2305_eth_driver }
-	hardware
-	directory	devs/eth/mn10300/asb2305
-	script		mn10300_asb2305_eth.cdl
-        description     "Ethernet driver for MN10300 ASB2305 board."
-}
-
-package CYGPKG_DEVS_ETH_VIA_RHINE {
-	alias 		{ "VIA Rhine ethernet driver" rhine_eth_driver }
-	hardware
-	directory	devs/eth/via/rhine
-	script		via_rhine_eth_drivers.cdl
-        description     "Ethernet driver for VIA Rhine controller."
-}
-
-package CYGPKG_DEVS_ETH_SH_HS7729PCI {
-	alias 		{ "HS7729PCI ethernet driver" hs7729pci_eth_driver }
-	hardware
-	directory	devs/eth/sh/hs7729pci
-	script		sh_hs7729pci_eth_drivers.cdl
-        description     "Ethernet driver for HS7729PCI development boards."
-}
-
-package CYGPKG_DEVS_ETH_SH_SE77X9 {
-	alias 		{ "SE77X9 ethernet driver" se77x9_eth_driver }
-	hardware
-	directory	devs/eth/sh/se77x9
-	script		sh_se77x9_eth_drivers.cdl
-        description     "Ethernet driver for SE77x9 development boards."
-}
-
-package CYGPKG_DEVS_ETH_SH_SE7751 {
-	alias 		{ "SE7751 ethernet driver" se7751_eth_driver }
-	hardware
-	directory	devs/eth/sh/se7751
-	script		sh_se7751_eth_drivers.cdl
-        description     "Ethernet driver for SE7751 board."
-}
-
-package CYGPKG_DEVS_ETH_SH_ETHERC {
-	alias 		{ "SH2 etherc driver" etherc_eth_driver }
-	hardware
-	directory	devs/eth/sh/etherc
-	script		sh_etherc_eth_drivers.cdl
-        description     "Ethernet driver for SH2 etherc controller."
-}
-
-package CYGPKG_DEVS_ETH_SH_MICRODEV {
-      alias           { "SH4-202 MicroDev onboard ethernet support" devs_eth_sh_md }
-      hardware
-      directory       devs/eth/sh/sh4_202_md
-      script          sh4_202_md_eth_drivers.cdl
-      description "This package contains hardware support for onboard SMC91C111
-                   ethernet device on the MicroDev board."
-}
-
-package CYGPKG_DEVS_ETH_ARM_EBSA285 {
-	alias 		{ "Intel EBSA285 with PRO/100+ ethernet driver"
-			   devs_eth_arm_ebsa285 ebsa285_eth_driver }
-	hardware
-	directory	devs/eth/arm/ebsa285
-	script		ebsa285_eth_drivers.cdl
-        description     "Ethernet driver for Intel EBSA285 with PRO/100+ boards."
-}
-
-package CYGPKG_DEVS_ETH_ARM_FLEXANET {
-      alias           { "SA11x0/Flexanet onboard ethernet support" devs_eth_arm_flexanet }
-      hardware
-      directory       devs/eth/arm/flexanet
-      script          flexanet_eth_drivers.cdl
-      description "This package contains hardware support for onboard SMC91C96
-                   ethernet device on the Flexanet board."
-}
-
-package CYGPKG_DEVS_ETH_ARM_INNOVATOR {
-      alias           { "OMAP Innovator onboard ethernet support" devs_eth_arm_innovator }
-      hardware
-      directory       devs/eth/arm/innovator
-      script          innovator_eth_drivers.cdl
-      description "This package contains hardware support for onboard SMC91C96
-                   ethernet device on the Innovator board."
-}
-
-package CYGPKG_DEVS_ETH_ARM_INTEGRATOR {
-        alias           { "ARM INTEGRATOR with Intel PRO/100+ ethernet driver"
-                           devs_eth_arm_integrator integrator_eth_driver }
-        hardware
-        directory       devs/eth/arm/integrator
-        script          integrator_eth_drivers.cdl
-        description     "Ethernet driver for Intel PRO/100+ boards on ARM INTEGRATOR."
-}
-
-package CYGPKG_DEVS_ETH_POWERPC_QUICC {
-	alias 		{ "QUICC ethernet driver" quicc_eth_driver }
-	hardware
-	directory	devs/eth/powerpc/quicc
-	script		quicc_eth_drivers.cdl
-        description     "Ethernet driver for PowerPC QUICC (MPC8xx) based boards."
-}
-
-package CYGPKG_DEVS_ETH_POWERPC_MBX {
-	alias 		{ "MBX ethernet driver specifics" mbx_eth_driver }
-	hardware
-	directory	devs/eth/powerpc/mbx
-	script		mbx_eth_drivers.cdl
-        description     "Ethernet driver specifics for Motorola MBX PowerPC (MPC8xx) based boards."
-}
-
-package CYGPKG_DEVS_ETH_POWERPC_QUICC2 {
-	alias 		{ "QUICC2 ethernet driver" quicc2_eth_driver }
-	hardware
-	directory	devs/eth/powerpc/quicc2
-	script		quicc2_eth_drivers.cdl
-        description     "Fast ethernet driver for PowerPC QUICC2 (MPC8260) based boards."
-}
-
-package CYGPKG_DEVS_ETH_POWERPC_FEC {
-	alias 		{ "FEC ethernet driver" fec_eth_driver }
-	hardware
-	directory	devs/eth/powerpc/fec
-	script		fec_eth_drivers.cdl
-        description     "Ethernet driver for PowerPC FEC (MPC8xxT) based boards."
-}
-
-package CYGPKG_DEVS_ETH_POWERPC_FCC {
-	alias 		{ "FCC ethernet driver" fcc_eth_driver }
-	hardware
-	directory	devs/eth/powerpc/fcc
-	script		fcc_eth_drivers.cdl
-        description     "Fast ethernet driver for PowerPC MPCxxx based boards."
-}
-
-package CYGPKG_DEVS_ETH_POWERPC_PPC405 {
-	alias 		{ "PPC405 ethernet driver" ppc405_eth_driver }
-	hardware
-	directory	devs/eth/powerpc/ppc405
-	script		ppc405_eth_drivers.cdl
-        description     "Ethernet driver for PowerPC 405GP based boards."
-}
-
-package CYGPKG_DEVS_ETH_POWERPC_VIPER {
-	alias 		{ "A&M Viper ethernet driver" viper_eth_driver }
-	hardware
-	directory	devs/eth/powerpc/viper
-	script		viper_eth_drivers.cdl
-        description     "Ethernet driver specifics for A&M Viper (MPC8xxT) based boards."
-}
-
-package CYGPKG_DEVS_ETH_POWERPC_EC555 {
-	alias 		{ "Crystal LAN ethernet driver for ec555 boards" ec555_eth_driver }
-	hardware
-	directory	devs/eth/powerpc/ec555
-	script		ec555_eth_drivers.cdl
-    description     "Ethernet driver for Crystal LAN on ec555 board."
-}
-
-package CYGPKG_DEVS_ETH_INTEL_I82559 {
-	alias 		{ "Intel 82559 ethernet driver"
-			   devs_eth_intel_i82559 i82559_eth_driver }
-	hardware
-	directory	devs/eth/intel/i82559
-	script		intel_i82559_eth_drivers.cdl
-        description     "Ethernet driver for Intel 82559 NIC."
-}
-
-package CYGPKG_DEVS_ETH_INTEL_I82544 {
-	alias 		{ "Intel 82544 ethernet driver"
-			   devs_eth_intel_i82544 i82544_eth_driver }
-	hardware
-	directory	devs/eth/intel/i82544
-	script		intel_i82544_eth_drivers.cdl
-        description     "Ethernet driver for Intel 82544 NIC."
-}
-
-package CYGPKG_DEVS_ETH_INTEL_I21143 {
-	alias 		{ "Intel 21143 ethernet driver"
-			   devs_eth_intel_i21143 i21143_eth_driver }
-	hardware
-	directory	devs/eth/intel/i21143
-	script		intel_i21143_eth_drivers.cdl
-        description     "Ethernet driver for Intel \[DEC\] 21143 NIC."
-}
-
-package CYGPKG_DEVS_ETH_MIPS_VRC4375 {
-	alias 		{ "NEC MIPS VRC4375 ethernet driver"
-			   devs_eth_mips_vrc4375 vrc4375_eth_driver }
-	hardware
-	directory	devs/eth/mips/vrc4375
-	script		vrc4375_eth_drivers.cdl
-        description     "Ethernet driver for NEC MIPS VRC4375 'Blue Nile'
-			board with Intel \[ex Digital Equipment\]
-                        i21143 ethernet interface."
-}
-
-package CYGPKG_DEVS_ETH_MIPS_RM7000_OCELOT {
-	alias 		{ "Ocelot ethernet drivers"
-			   devs_eth_mips_rm7000_ocelot ocelot_eth_driver }
-	hardware
-	directory	devs/eth/mips/ocelot
-	script		mips_rm7000_ocelot_eth_drivers.cdl
-        description     "Ethernet driver for PMC-Sierra Ocelot board."
-}
-
-package CYGPKG_DEVS_ETH_ARM_IQ80321 {
-	alias 		{ "Intel IQ80321 with onboard 82544 ethernet driver"
-			   devs_eth_arm_iq80321 iq80321_eth_driver }
-	hardware
-	directory	devs/eth/arm/iq80321
-	script		iq80321_eth_drivers.cdl
-        description     "Ethernet driver for Intel IQ80321 with onboard 82544 NIC."
-}
-
-package CYGPKG_DEVS_ETH_ARM_XSCALE_IQ80310 {
-	alias 		{ "Intel IQ80310 with onboard 82559 ethernet driver"
-			   devs_eth_arm_iq80310 iq80310_eth_driver }
-	hardware
-	directory	devs/eth/arm/iq80310
-	script		iq80310_eth_drivers.cdl
-        description     "Ethernet driver for Intel IQ80310 with onboard 82559 NIC."
-}
-
-package CYGPKG_DEVS_ETH_ARM_IXDP425_I82559 {
-	alias 		{ "IXDP425 (PCI) / Intel 82559 ethernet driver"
-			   devs_eth_arm_ixdp425_i82559 }
-	hardware
-	directory	devs/eth/arm/ixdp425/i82559
-	script		ixdp425_i82559_eth_driver.cdl
-        description     "Ethernet driver for IXDP425 with Intel 82559 PCI NIC."
-}
-
-package CYGPKG_DEVS_ETH_ARM_XSCALE_XSENGINE {
-       alias           { "XSEngine SMC91C111 ethernet driver" devs_eth_arm_xsengine }
-       hardware
-       directory       devs/eth/arm/xsengine
-       script          xsengine_eth_drivers.cdl
-       description     "Ethernet driver for XSEngine board."
-}
-
-package CYGPKG_DEVS_ETH_ARM_GRG_I82559 {
-	alias 		{ "GRG / Intel 82559 ethernet driver"
-			   devs_eth_arm_grg_i82559 }
-	hardware
-	directory	devs/eth/arm/grg/i82559
-	script		grg_i82559_eth_driver.cdl
-        description     "Ethernet driver for GRG with Intel 82559 PCI NIC."
-}
-
-package CYGPKG_DEVS_ETH_I386_PC_I82559 {
-	alias 		{ "Standard PC with EtherPro 10/100 ethernet device"
-			   devs_eth_i386_pc_i82559 pc_etherpro }
-	hardware
-	directory	devs/eth/i386/pc/i82559
-	script		i386_pc_i82559_eth_drivers.cdl
-        description     "Ethernet driver for standard PC with Intel 82559 NIC. This is
-			 essentially support for a EtherPro 10/100 PCI card."
-}
-
-package CYGPKG_DEVS_ETH_I386_PC_I82544 {
-	alias 		{ "Standard PC with Intel Gigabit ethernet device"
-			   devs_eth_i386_pc_i82544 pc_ether_giga }
-	hardware
-	directory	devs/eth/i386/pc/i82544
-	script		i386_pc_i82544_eth_drivers.cdl
-        description     "Ethernet driver for standard PC with Intel 82544 Gigabit NIC."
-}
-
-package CYGPKG_DEVS_ETH_I386_PC_LANCEPCI {
-	alias 		{ "Standard PC with AMD Lance PCI device"
-			   devs_eth_i386_pc_lancepci pc_ether_lancepci }
-	hardware
-	directory	devs/eth/i386/pc/lancepci
-	script		i386_pc_lancepci_eth_drivers.cdl
-        description     "Ethernet driver for standard PC with AMD Lance NIC (vmWare)."
-}
-
-package CYGPKG_DEVS_ETH_MIPS_ATLAS {
-	alias 		{ "MIPS Atlas with onboard SAA9730 ethernet driver"
-			   devs_eth_mips_atlas atlas_eth_driver }
-	hardware
-	directory	devs/eth/mips/atlas
-	script		atlas_eth_drivers.cdl
-        description     "Ethernet driver for MIPS Atlas with onboard SAA9730 NIC."
-}
-
-package CYGPKG_DEVS_ETH_NS_DP83902A {
-	alias 		{ "NS DP83902A ethernet driver" dp83902a_eth_driver }
-	hardware
-	directory	devs/eth/ns/dp83902a
-	script		ns_dp83902a_eth_drivers.cdl
-        description     "Ethernet driver for NS DP83902A controller."
-}
-
-package CYGPKG_DEVS_ETH_NS_DP83816 {
-	alias 		{ "NS DP83816 ethernet driver" dp83816_eth_driver }
-	hardware
-	directory	devs/eth/ns/dp83816
-	script		ns_dp83816_eth_drivers.cdl
-        description     "Ethernet driver for NS DP83816 controller."
-}
-
-package CYGPKG_DEVS_ETH_CL_CS8900A {
-	alias 		{ "Cirrus Logic CS8900A ethernet driver" cs8900a_eth_driver }
-	hardware
-	directory	devs/eth/cl/cs8900a
-	script		cl_cs8900a_eth_drivers.cdl
-        description     "Ethernet driver for Cirrus Logic CS8900A controller."
-}
-
-package CYGPKG_DEVS_ETH_MIPS_UPD985XX {
-	alias		{ "NEC uPD985xx ethernet driver" uPD985xx_eth_driver }
-	hardware
-	directory	devs/eth/mips/upd985xx
-	script		upd985xx_eth_drivers.cdl
-	description     "NEC uPD985xx ethernet driver"
-}
-
-package CYGPKG_DEVS_ETH_MIPS_REFIDT334 {
-        alias           { "MIPS IDT 79RC32334 reference platform ethernet driver"
-                           devs_eth_refidt334 refidt334_eth_driver }
-        hardware
-        directory       devs/eth/mips/idt79s334a
-        script          refidt334_eth_drivers.cdl
-        description     "Ethernet driver for MIPS IDT 79RC32334 reference platform."
-}
-
-# Not sure whether this should be "hardware"; if so, it should be mentioned
-# in all targets that can use it.
-package CYGPKG_DEVS_ETH_CF {
-	alias 		{ "PCMCIA (Compact Flash) ethernet drivers" cf_eth_drivers }
-	directory	devs/eth/cf
-	script		cf_eth_drivers.cdl
-        hardware
-        description     "Ethernet drivers for PCMCIA (Compact Flash) cardss."
-}
-
-package CYGPKG_DEVS_ETH_H8300_AKI3068NET {
-	alias 		{ "Akizuki H8/3068 Board ethernet driver" aki3068net_eth_drivers }
-	directory	devs/eth/h8300/aki3068net
-	script		h8300_aki3068net_eth_drivers.cdl
-        hardware
-        description     "Ethernet drivers for Akizuki H8/3068 Network
-   	                 micom board."
-}
-
-package CYGPKG_DEVS_ETH_H8300_H8MAX {
-	alias 		{ "H8MAX Board ethernet driver" h8max_eth_drivers }
-	directory	devs/eth/h8300/h8max
-	script		h8300_h8max_eth_drivers.cdl
-        hardware
-        description     "Ethernet drivers for H8MAX board."
-}
-
-package CYGPKG_DEVS_ETH_H8300_EDOSK2674 {
-	alias 		{ "EDOSK-2674 Board ethernet driver" edosk2674_eth_drivers }
-	directory	devs/eth/h8300/edosk2674
-	script		h8300_edosk2674_eth_drivers.cdl
-        hardware
-        description     "Ethernet drivers for EDOSK-2674 board."
-}
-
-package CYGPKG_DEVS_ETH_MCF5272 {
-        alias           { "MCF5272 Fast Ethernet Controller driver" mcf5272_eth_driver}
-        hardware
-        directory       devs/eth/mcf52xx/mcf5272
-        script          mcf5272_eth_driver.cdl
-        description     "Ethernet driver for the MCF5272."
-}
-
-
-package CYGPKG_DEVS_ETH_ECOSYNTH {
-        alias           { "Synthetic target ethernet driver" ecosyntheth ecosynth_eth_driver }
-        directory       devs/eth/synth/ecosynth
-        script          syntheth.cdl
-        hardware
-        description     "Ethernet driver for the synthetic target"
-}
-
-package CYGPKG_IO_PCI	{
-	alias		{ "PCI configuration library" io_pci }
-	directory	io/pci
-	script		io_pci.cdl
-	hardware
-        description "
-           This package contains the PCI configuration library."
-}
-
-package CYGPKG_IO_WALLCLOCK {
-        alias           { "Wallclock device framework" wallclock io_wallclock devices_wallclock device_wallclock }
-	directory	io/wallclock
-	script          wallclock.cdl
-        description "
-           This package provides a wallclock device framework. It is
-           also necessary to select an actual driver implementation."
-}
-
-package CYGPKG_DEVICES_WALLCLOCK_SH3 {
-	alias		{ "Wallclock driver for SH3 RTC module" devices_wallclock_sh3 device_wallclock_sh3 }
-	directory	devs/wallclock/sh/sh3
-	script          wallclock_sh3.cdl
-	hardware
-        description "
-           This package provides a wallclock driver implementation for the
-           Hitachi SH3 CPU's RTC module."
-}
-
-package CYGPKG_DEVICES_WALLCLOCK_MPC5xx {
-	alias		{ "Wallclock driver for mpc5xx RTC module" devices_wallclock_mpc5xx device_wallclock_mpc5xx }
-	directory	devs/wallclock/powerpc/mpc5xx
-	script          wallclock_mpc5xx.cdl
-	hardware
-        description "
-           This package provides a wallclock driver implementation for the
-           Motorola mpc5xx CPU's RTC module."
-}
-
-package CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1307 {
-	alias		{ "Wallclock driver for Dallas 1307" devices_wallclock_ds1307 device_wallclock_ds1307 }
-	directory	devs/wallclock/dallas/ds1307
-	script          wallclock_ds1307.cdl
-	hardware
-        description "
-           This package provides a driver implementation for 
-           the Dallas 1307 wallclock."
-}
-
-package CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1742 {
-	alias		{ "Wallclock driver for Dallas 1742" devices_wallclock_ds1742 device_wallclock_ds1742 }
-	directory	devs/wallclock/dallas/ds1742
-	script          wallclock_ds1742.cdl
-	hardware
-        description "
-           This package provides a driver implementation for 
-           the Dallas 1742 wallclock."
-}
-
-package CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS12887 {
-	alias		{ "Wallclock driver for Dallas 12887" devices_wallclock_ds12887 device_wallclock_ds12887 }
-	directory	devs/wallclock/dallas/ds12887
-	script          wallclock_ds12887.cdl
-	hardware
-        description "
-           This package provides a driver implementation for 
-           the Dallas 12887 wallclock."
-}
-
-package CYGPKG_DEVICES_WALLCLOCK_MIPS_REF4955 {
-	alias		{ "Wallclock driver for REF4955 board" devices_wallclock_ref4955 device_wallclock_ref4955 }
-	directory	devs/wallclock/mips/ref4955
-	script          wallclock_ref4955.cdl
-	hardware
-        description "
-           This package provides a wallclock driver implementation for the
-           Toshiba REF4955 board."
-}
-
-package CYGPKG_DEVICES_WALLCLOCK_I386_PC {
-         alias          { "Standard PC RTC device" devs_wallclock_i386_pc_ds12887 pc_rtc }
-         hardware
-         directory      devs/wallclock/i386/pc
-         script         i386_pc_wallclock_drivers.cdl
-         description    "
-            RTC driver for standard PC. This is essentially support for a
-            Dallas DS12887 RTC."
-}
-
-package CYGPKG_DEVICES_WALLCLOCK_SH_HS7729PCI {
-	alias		{ "Wallclock driver for HS7729PCI board" devices_wallclock_hs7729pci device_wallclock_hs7729pci }
-	directory	devs/wallclock/sh/hs7729pci
-	script          wallclock_hs7729pci.cdl
-	hardware
-        description "
-           This package provides a wallclock driver implementation for the
-           Hitachi HS7729PCI board."
-}
-
-package CYGPKG_DEVS_WALLCLOCK_SYNTH {
-        alias           { "Wallclock driver for synthetic target" devs_wallclock_synth wallclock_synth }
-        directory       devs/wallclock/synth
-        script          wallclock_synth.cdl
-        hardware
-        description "
-           This package provides a wallclock driver implementation for the
-           synthetic target."
-}
-
-package CYGPKG_DEVICES_WALLCLOCK_ARM_AIM711 {
-       alias           { "Wallclock driver for AIM 711" devs_wallclock_arm_aim711 aim711_rt
-c }
-       directory       devs/wallclock/arm/aim711
-       script          aim711_wallclock_drivers.cdl
-       hardware
-        description "
-           This package provides a wallclock driver implementation for the
-           ARM Industrial Module AIM 711."
-}
-
-package CYGPKG_DEVICES_WALLCLOCK_ARM_LPC2XXX {
-        alias           { "Wallclock driver for LPC2xxx RTC module" }
-        directory       devs/wallclock/arm/lpc2xxx
-        script          lpc2xxx_wallclock.cdl
-        hardware
-        description "
-           This package provides a wallclock driver implementation for the
-           LPC2xxx RTC module."
-}
-
-package CYGPKG_DEVICES_WATCHDOG_ARM_AEB {
-	alias		{ "Watchdog driver for ARM/AEB board" devices_watchdog_aeb device_watchdog_aeb }
-	directory	devs/watchdog/arm/aeb
-	script          watchdog_aeb.cdl
-	hardware
-        description "
-           This package provides a watchdog driver implementation for the
-           ARM/AEB board."
-}
-
-package CYGPKG_DEVICES_WATCHDOG_ARM_AT91 {
-	alias		{ "Watchdog driver for ARM AT91 CPU" devices_watchdog_at91 device_watchdog_at91 }
-	directory	devs/watchdog/arm/at91
-	script          watchdog_at91.cdl
-	hardware
-        description "
-           This package provides a watchdog driver implementation for the
-           ARM AT91 CPU."
-}
-
-package CYGPKG_DEVICES_WATCHDOG_ARM_AT91WDTC {
-	alias		{ "Watchdog driver for ARM AT91 WDTC" devices_watchdog_at91wdtc device_watchdog_at91wdtc }
-	directory	devs/watchdog/arm/at91wdtc
-	script          watchdog_at91wdtc.cdl
-	hardware
-        description "
-           This package provides a watchdog driver implementation for the
-           ARM AT91 CPUs which have the Watchdog Timer Controller."
-}
-
-package CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX {
-        alias           { "Watchdog driver for ARM LPC2XXX CPU" devices_watchdog_lpc2xxx device_watchdog_lpc2xxx }
-       directory       devs/watchdog/arm/lpc2xxx
-       script          watchdog_lpc2xxx.cdl
-       hardware
-       description "
-           This package provides a watchdog driver implementation for the
-           ARM LPC2XXX CPU."
-}
-
-package CYGPKG_DEVICES_WATCHDOG_ARM_EBSA285 {
-	alias		{ "Watchdog driver for ARM/EBSA285 board" devices_watchdog_ebsa285 device_watchdog_ebsa285 }
-	directory	devs/watchdog/arm/ebsa285
-	script          watchdog_ebsa285.cdl
-	hardware
-        description "
-           This package provides a watchdog driver implementation for the
-           ARM/EBSA285 board."
-}
-
-package CYGPKG_DEVICES_WATCHDOG_ARM_SA11X0 {
-	alias		{ "Watchdog driver for StrongARM SA11x0 devices" devices_watchdog_sa11x0 device_watchdog_sa11x0 }
-	directory	devs/watchdog/arm/sa11x0
-	script          watchdog_sa11x0.cdl
-	hardware
-        description "
-           This package provides a watchdog driver implementation for
-           Intel StrongARM SA11x0 integrated devices."
-}
-
-package CYGPKG_DEVICES_WATCHDOG_MN10300_MN10300 {
-	alias		{ "Watchdog driver for MN10300 chip" devices_watchdog_mn10300 device_watchdog_mn10300 }
-	directory	devs/watchdog/mn10300/mn10300
-	script          watchdog_mn10300.cdl
-	hardware
-        description "
-           This package provides a watchdog driver implementation for the
-           MN10300 chip."
-}
-
-package CYGPKG_DEVICES_WATCHDOG_MPC5xx {
-	alias		{ "Watchdog driver for mpc5xx processor" devices_watchdog_mpc5xx device_watchdog_mpc5xx }
-	directory	devs/watchdog/powerpc/mpc5xx
-	script          watchdog_mpc5xx.cdl
-	hardware
-        description "
-           This package provides a watchdog driver implementation for the
-           mpc5xx processor family."
-}
-
-package CYGPKG_DEVICES_WATCHDOG_SH_SH3 {
-	alias		{ "Watchdog driver for the Hitachi SH3 chip" devices_watchdog_sh3 device_watchdog_sh3 }
-	directory	devs/watchdog/sh/sh3
-	script          watchdog_sh3.cdl
-	hardware
-        description "
-           This package provides a watchdog driver implementation for the
-           Hitachi SH3 chip."
-}
-
-package CYGPKG_DEVICES_WATCHDOG_H8300_H8300H {
-	alias		{ "Watchdog driver for the Hitachi H8/300H chip" devices_watchdog_h8300h device_watchdog_h8300h }
-	directory	devs/watchdog/h8300/h8300h
-	script          watchdog_h8300h.cdl
-	hardware
-        description "
-           This package provides a watchdog driver implementation for the
-           Hitachi H8/300H chip."
-}
-
-package CYGPKG_DEVS_WATCHDOG_SYNTH {
-	alias		{ "Watchdog driver for the synthetic target" devices_watchdog_synth device_watchdog_synth }
-	directory	devs/watchdog/synth
-	script          synth_watchdog.cdl
-	hardware
-        description "
-           This package provides a watchdog driver for the eCos
-           synthetic target."
-}
-
-package CYGPKG_IO_WATCHDOG {
-	alias		{ "Watchdog IO device" watchdog io_watchdog }
-	directory	io/watchdog
-        script          watchdog.cdl
-        description "
-           This package provides a watchdog device."
-}
-
-package CYGPKG_DEVS_SPI_ARM_AT91 {
-    alias         { "Atmel AT91 SPI device driver" devs_spi_arm_at91 spi_at91_driver }
-    hardware
-    directory     devs/spi/arm/at91
-    script        spi_at91.cdl
-    description   "Atmel AT91 on-chip spi device driver."
-}
-
-package CYGPKG_DEVS_SPI_ARM_EB55 {
-    alias         { "Atmel AT91EB55 SPI devices" devs_spi_arm_eb55 spi_eb55_devices }
-    hardware
-    directory     devs/spi/arm/eb55
-    script        spi_eb55.cdl
-    description   "Atmel AT91EB55 spi devices."
-}
-
-package CYGPKG_DEVS_SPI_ARM_LPC2XXX {
-    alias         { "LPC2xxx SPI driver" }
-    hardware
-    directory     devs/spi/arm/lpc2xxx
-    script        spi_lpc2xxx.cdl
-    description "This package provides a driver for the SPI unit of the LPC2xxx
-                 controller family."
-}
-
-package CYGPKG_IO_SPI {
-        alias      { "Generic SPI support" spi io_spi spi_io }
-        directory  io/spi
-        script     spi.cdl
-        hardware
-        description "
-          The generic SPI package provides an API for accessing devices
-          attached to an SPI bus. It also provides support for writing
-          bus drivers and for defining SPI device structures."
-}
-
-package CYGPKG_IO_I2C {
-        alias           { "Generic I2C support" i2c io_i2c i2c_io }
-        directory       io/i2c
-        script          i2c.cdl
-        hardware
-        description "
-            The generic I2C package provides an API for accessing devices
-            attached to an I2C bus. It specifies how I2C bus drivers should
-            be written and how I2C devices should be defined. There is also
-            support for bit-banged I2C buses."
-}
-
-package CYGPKG_DEVS_I2C_MCF52xx {
-	alias		{ "MCF52xx I2C driver" devs_i2c_mcf52xx mcf52xx_i2c_driver }
-	hardware
-	directory	devs/i2c/m68k/mcf52xx
-	script		i2c_mcf52xx.cdl
-	description "
-            This packages provides an I2C driver for the on-chip
-	        device provided by the MCF52xx coldfire processor family."
-}
-
-package CYGPKG_DEVS_I2C_ARM_LPC2XXX {
-    alias           { "LPC2xxx I2C driver" }
-    hardware
-    directory       devs/i2c/arm/lpc2xxx
-    script          i2c_lpc2xxx.cdl
-    description "This package provides a driver for the I2C unit of the LPC2xxx
-                 controller family."
-}
-
-package CYGPKG_DEVS_ADC_ARM_LPC24XX {
-    alias           { "LPC24xx ADC driver" }
-    hardware
-    directory       devs/adc/arm/lpc24xx
-    script          adc_lpc24xx.cdl
-    description "
-            This packages provides an ADC driver for the on-chip
-            ADC provided by the LPC24xx processor family."
-}
-
-package CYGPKG_DEVS_ADC_SYNTH {
-    alias         { "Synthethic ADC driver" adc_synth }
-    hardware
-    directory     devs/adc/synth
-    script        adc_synth.cdl
-    description "
-            This package provides an ADC driver for the Synthethic target."
-}
-
-package CYGPKG_IO_ADC {
-	alias 		{ "Generic ADC support" adc io_adc }
-	directory	io/adc
-	script		io_adc.cdl
-        description "
-           This package contains drivers for basic I/O services on
-           adc devices."
-}
-
-package CYGPKG_KERNEL {
-	alias		{ "eCos kernel" kernel }
-	directory	kernel
-	script		kernel.cdl
-     	description "
-This package contains the core functionality of the eCos kernel. It
-relies on functionality provided by various HAL packages and by the
-eCos infrastructure. In turn the eCos kernel provides support for
-other packages such as the device drivers and the uITRON compatibility
-layer."
-}
-
-package CYGPKG_MEMALLOC {
-        alias           { "Dynamic memory allocation" memalloc malloc }
-        directory       services/memalloc/common
-        script          memalloc.cdl
-        description "
-This package provides memory allocator infrastructure required for
-dynamic memory allocators, including the ISO standard malloc
-interface. It also contains some sample implementations."
-}
-
-package CYGPKG_LOADER {
-        alias           { "Dynamic loader" loader dload }
-        directory       services/loader
-        script          loader.cdl
-        description "
-This package provides support for the dynamic executable and
-library loader."
-}
-
-package CYGPKG_OBJLOADER {
-        alias           { "Object file loader" objloader }
-        directory       services/objloader
-        script          objloader.cdl
-        description "
-This package provides support for the object file loader and relocator."
-}
-
-package CYGPKG_COMPRESS_ZLIB {
-        alias           { "Zlib compress/decompress" zlib_compress compress_zlib zlib }
-        directory       services/compress/zlib
-        script          compress_zlib.cdl
-        description "
-This package provides zlib compression and decompression support."
-}
-
-package CYGPKG_POWER {
-	alias 		{ "Power Management support" power }
-	directory	services/power/common
-	script		power.cdl
-	description "
-This package provides some generic support for power management."
-}
-
-package CYGPKG_CRC {
-        alias           { "CRC support" crc }
-        directory       services/crc
-        script          crc.cdl
-        description "
-This package provides support for CRC functions, including the 
-POSIX 1003 defined CRC algorithm."
-}  
-
-package CYGPKG_CPULOAD {
-        alias           { "cpuload support" cpuload }
-        directory       services/cpuload
-        script          cpuload.cdl
-        description "
-This package measures the CPU load over the last 100ms, 1second 
-and 10 second. All loads are returned as a percentage, ie 0-100.
-This is only a rough measure."
-}     
-
-package CYGPKG_PROFILE_GPROF {
-        alias           { "Application profile support" profile_gprof gprof_profile }
-        directory       services/profile/gprof
-        script          profile_gprof.cdl
-        description "
-This package instruments applications to collect profiling data,
-using a methodology compatible with the gprof utility."
-}     
-                  
-package CYGPKG_EZXML {
-        alias           { "ezXML" XML ezxml }
-        directory       services/ezxml
-        script          ezxml.cdl
-        description     "ezXML, Simple XML Parser"
-}
-                 
-package CYGPKG_PDCURSES {
-	alias 		{ "PDCurses" pdcurses }
-	directory	services/curses/pdcurses
-	script		pdcurses.cdl
-        description     "Public Domain Curses."
-}
-
-package CYGPKG_UITRON {
-	alias		{ "uITRON compatibility" uitron }
-	directory	compat/uitron
-	script		uitron.cdl
-	description "
-eCos supports a uITRON Compatibility Layer, providing full Level S
-(Standard) compliance with Version 3.02 of the uITRON Standard, plus
-many Level E (Extended) features. uITRON is the premier Japanese
-embedded RTOS standard."
-}
-
-package CYGPKG_ISOINFRA {
-        alias           { "ISO C and POSIX infrastructure" isoinfra }
-        directory       isoinfra
-        script          isoinfra.cdl
-        description "
-eCos supports implementations of ISO C libraries and POSIX implementations.
-This package provides infrastructure used by all such implementations."
-}
-
-package CYGPKG_POSIX {
-	alias		{ "POSIX compatibility" posix }
-	directory	compat/posix
-	script		posix.cdl
-	description "
-This package enables compatibility with the ISO/IEEE 1003.1 POSIX
-standard.  This allows the user application to use a well known
-standard API, and starts a thread to invoke the user function
-main()"
-}
-
-package CYGPKG_LIBC {
-	alias		{ "C library" libc clib clibrary }
-	directory	language/c/libc/common
-	script		libc.cdl
-        description  "
-The packages under this package enable compatibility with the ISO C
-standard - ISO/IEC 9899:1990. This allows the user application to use
-well known standard C library functions, and in eCos starts a thread
-to invoke the user function main(). This package is a top-level placeholder
-to contain the implementations."
-}
-
-package CYGPKG_LIBC_I18N {
-	alias		{ "ISO C library internationalization" libc_i18n }
-	directory	language/c/libc/i18n
-	script		i18n.cdl
-        description  "
-This package provides internationalization functions specified by the
-ISO C standard - ISO/IEC 9899:1990."
-}
-
-package CYGPKG_LIBC_SETJMP {
-	alias		{ "ISO C library non-local jumps" libc_setjmp }
-	directory	language/c/libc/setjmp
-	script		setjmp.cdl
-        description  "
-This package provides non-local jump functionality specified by the
-ISO C standard - ISO/IEC 9899:1990."
-}
-
-package CYGPKG_LIBC_SIGNALS {
-	alias		{ "ISO C library signals" libc_signals }
-	directory	language/c/libc/signals
-	script		signals.cdl
-        description   "
-This component controls signal functionality, as implemented in
-ISO/IEC 9899:1990 chapter 7.7 with the signal() and raise() functions.
-As well as allowing a program to send itself signals, it is also
-possible to cause hardware exceptions to be signalled to the program
-in a similar way."
-}
-
-package CYGPKG_LIBC_STARTUP {
-	alias		{ "ISO environment startup/termination" libc_startup }
-	directory	language/c/libc/startup
-	script		startup.cdl
-        description   "
-            This package manages the control of the
-            environment (in the general sense) that an
-            application would require for full ISO C / POSIX
-            compatibility, including a main() entry point
-            supplied with arguments and an environment
-            (as retrievable by the getenv() function).
-            It also includes at the other end of things,
-            what happens when main() returns or exit() is
-            called."
-}
-
-package CYGPKG_LIBC_STDIO {
-	alias		{ "ISO C library standard input/output functions" libc_stdio }
-	directory	language/c/libc/stdio
-	script		stdio.cdl
-        description  "
-This package provides standard input/output functions associated
-with the header file <stdio.h> as specified by the
-ISO C standard - ISO/IEC 9899:1990."
-}
-
-package CYGPKG_LIBC_STDLIB {
-	alias		{ "ISO C library general utility functions" libc_stdlib }
-	directory	language/c/libc/stdlib
-	script		stdlib.cdl
-        description  "
-This package provides general utility functions associated
-with the header file <stdlib.h> as specified by the
-ISO C standard - ISO/IEC 9899:1990."
-}
-
-package CYGPKG_LIBC_STRING {
-	alias		{ "ISO C library string functions" libc_string }
-	directory	language/c/libc/string
-	script		string.cdl
-        description  "
-This package provides string functions specified by the ISO C standard
-- ISO/IEC 9899:1990."
-}
-
-package CYGPKG_LIBC_TIME {
-	alias		{ "ISO C library date/time functions" libc_time }
-	directory	language/c/libc/time
-	script		time.cdl
-        description  "
-This package provides date and time manipulation functionality specified
-by the ISO C standard - ISO/IEC 9899:1990."
-}
-
-package CYGPKG_LIBM {
-	alias		{ "Math library" libm mathlib mathlibrary }
-	directory	language/c/libm
-	script		libm.cdl
-        description  "
-ISO standard floating point mathematical library containing many
-useful functions for mathematical calculations."
-}
-
-package CYGPKG_USTL {
-	alias		{ "uSTL library" ustl }
-	directory	language/cxx/ustl
-	script		ustl.cdl
-	description  "
+#=============================================================================
+#
+#    ecos.db
+#
+#    This file is a temporary database for eCos package information.
+#    It replaces the old packages and targets files, and will in turn
+#    be subsumed by another file containing more inormation.
+#
+#=============================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+#=============================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):	bartv
+# Date:		1999-06-13
+#
+# This file contains three lots of information. It details the packages
+# in the component repository, the target boards supported by those
+# packages, and a set of templates that can be used to instantiate
+# configuration.
+# 
+#####DESCRIPTIONEND####
+#===============================================================================
+
+package CYGPKG_HAL {
+        alias		{ "eCos common HAL" hal hal_common }
+	directory	hal/common
+	script		hal.cdl
+	description "
+The eCos HAL package provide a porting layer for higher-level parts of
+the system such as the kernel and the C library. Each installation
+should have HAL packages for one or more architectures, and for each
+architecture there may be one or more supported platforms. It is
+necessary to select one target architecture and one platform for that
+architecture. There are also a number of configuration options that
+are common to all HAL packages."
+}
+
+package CYGPKG_INFRA {
+	alias 		{ Infrastructure infra }
+	directory	infra
+	script		infra.cdl
+        description "
+Common types and useful macros.
+Tracing and assertion facilities.
+Package startup options." 
+}
+
+package CYGPKG_IO {
+	alias 		{ "I/O sub-system" io }
+	directory	io/common
+	script		io.cdl
+        description "
+           The eCos system is supplied with a number of different
+           device drivers.  This package contains the basic I/O system
+           support which is the basis for all drivers."
+}
+
+package CYGPKG_IO_SERIAL {
+	alias 		{ "Serial device drivers" serial io_serial }
+	directory	io/serial
+	script		io_serial.cdl
+        description "
+           This package contains drivers for basic I/O services on
+           serial devices."
+}
+
+package CYGPKG_IO_CAN {
+	alias 		{ "CAN device drivers" can io_can }
+	directory	io/can
+	script		io_can.cdl
+        description "
+           This package contains drivers for basic I/O services on
+           CAN devices."
+}
+
+package CYGPKG_DEVS_CAN_MCF52xx_FLEXCAN {
+    alias             { "MCF52xx FlexCAN device drivers"
+                        devs_can_mcf52xx_flexcan mcf52xx_flexcan_serial_driver }
+    hardware
+    directory	      devs/can/m68k/mcf52xx
+    script	          can_mcf52xx.cdl	
+    description       "Generic CAN device driver for the on-chip
+                       FlexCAN modules in MCF52xx ColdFire processors."
+}
+
+package CYGPKG_DEVS_CAN_AT91SAM7 {
+    alias             { "AT91SAM7 CAN device drivers"
+                        devs_can_at91sam7 at91sam7_can_driver }
+    hardware
+    directory	      devs/can/arm/at91/at91sam7
+    script	          can_at91sam7.cdl	
+    description       "Atmel AT91SAM7 on-chip CAN device driver."
+}
+
+package CYGPKG_DEVS_CAN_LPC2XXX {
+    alias             { "LPC2xxx CAN device drivers"
+                        devs_can_lpc2xxx lpc2xxx_can_driver }
+    hardware
+    directory	      devs/can/arm/lpc2xxx
+    script	          can_lpc2xxx.cdl	
+    description       "LPC2xxx on-chip CAN device driver."
+}
+
+package CYGPKG_DEVS_CAN_LOOP {
+    alias             { "Loop CAN device drivers"
+                        devs_can_loop loop_can_driver }
+    directory	      devs/can/loop
+    script	      can_loop.cdl	
+    description       "Loopback CAN device driver."
+}
+
+
+package CYGPKG_IO_PCMCIA {
+	alias 		{ "PCMCIA & Compact Flash support" pcmcia io_pcmcia cf }
+	directory	io/pcmcia
+	script		io_pcmcia.cdl
+        description "
+           This package contains basic card services support for PCMCIA
+           and Compact Flash devices."
+}
+
+package CYGPKG_DEVS_PCMCIA_ASSABET {
+	alias 		{ "SA11x0/Assabet PCMCIA & Compact Flash support" pcmcia_assabet assabet_pcmcia assabet_cf io_assabet_pcmcia}
+	directory	devs/pcmcia/arm/assabet
+	script		pcmcia_assabet.cdl
+	hardware
+        description "
+           This package contains hardware support for PCMCIA
+           and Compact Flash devices on the SA11x0/Assabet board."
+}
+
+package CYGPKG_DEVS_PCMCIA_CERF {
+	alias 		{ "SA11x0/Cerf PCMCIA & Compact Flash support" pcmcia_cerf cerf_pcmcia cerf_cf io_cerf_pcmcia}
+	directory	devs/pcmcia/arm/cerf
+	script		pcmcia_cerf.cdl
+	hardware
+        description "
+           This package contains hardware support for PCMCIA
+           and Compact Flash devices on the SA11x0/Cerf board."
+}
+
+package CYGPKG_DEVS_PCMCIA_CERFPDA {
+	alias 		{ "SA11x0/Cerfpda PCMCIA & Compact Flash support" pcmcia_cerfpda cerfpda_pcmcia cerfpda_cf io_cerfpda_pcmcia}
+	directory	devs/pcmcia/arm/cerfpda
+	script		pcmcia_cerfpda.cdl
+	hardware
+        description "
+           This package contains hardware support for PCMCIA
+           and Compact Flash devices on the SA11x0/Cerfpda."
+}
+
+package CYGPKG_DEVS_PCMCIA_IPAQ {
+        alias           { "SA11x0/iPAQ PCMCIA & Compact Flash support" pcmcia_ipaq ipaq_pcmcia ipaq_cf io_ipaq_pcmcia}
+        directory       devs/pcmcia/arm/ipaq
+        script          pcmcia_ipaq.cdl
+        hardware
+        description "
+           This package contains hardware support for PCMCIA
+           and Compact Flash devices on the Compaq iPAQ pocket PC."
+}
+
+package CYGPKG_IO_FLASH {
+	alias 		{ "Generic FLASH memory support" flash }
+	directory	io/flash
+	script		io_flash.cdl
+        description "
+           This package contains generic support for FLASH memory."
+}
+
+package CYGPKG_DEVS_FLASH_ARM_AAED2000 {
+	alias 		{ "Support for flash memory on Agilent AAED2000 board" flash_aaed2000 }
+	directory	devs/flash/arm/aaed2000
+	script		flash_arm_aaed2000.cdl
+	hardware
+        description "
+           This package contains hardware support for flash memory
+	   on the Agilent AAED2000 platform."
+}
+
+package CYGPKG_DEVS_FLASH_AMD_AM29XXXXX {
+	alias 		{ "Support for AMD AM29xxxxx flash memory (deprecated)" flash_amd_am29xxxxx }
+	directory	devs/flash/amd/am29xxxxx
+	script		flash_amd_am29xxxxx.cdl
+	hardware
+        description "
+           This package contains hardware support for AMD AM29xxxxx
+           flash memory devices."
+}
+
+package CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2 {
+	alias 		{ "Support for AMD AM29xxxxx flash memory" flash_amd_am29xxxxx_v2 }
+	directory	devs/flash/amd/am29xxxxxv2
+	script		flash_am29xxxxx_v2.cdl
+	hardware
+        description "
+           This package contains hardware support for AMD AM29xxxxx
+           flash memory devices."
+}
+
+package CYGPKG_DEVS_FLASH_ATMEL_AT29CXXXX {
+	alias 		{ "Support for Atmel AT29Cxxxx flash memory" flash_atmel_at29cxxxx }
+	directory	devs/flash/atmel/at29cxxxx
+	script		flash_atmel_at29cxxxx.cdl
+	hardware
+        description "
+           This package contains hardware support for Atmel AT29Cxxxx
+           flash memory devices."
+}
+
+package CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX {
+	alias 		{ "Support for Atmel AT49xxxx flash memory" flash_atmel_at49xxxx }
+	directory	devs/flash/atmel/at49xxxx
+	script		flash_atmel_at49xxxx.cdl
+	hardware
+        description "
+           This package contains hardware support for Atmel AT49xxxx
+           flash memory devices."
+}
+
+package CYGPKG_DEVS_FLASH_ATMEL_DATAFLASH {
+    alias       { "Atmel DataFlash support" flash_dataflash dataflash }
+    directory   devs/flash/atmel/dataflash
+    script      devs_flash_atmel_dataflash.cdl
+    hardware
+    description "This package contains hardware support for Atmel DataFlash."
+}
+
+package CYGPKG_DEVS_FLASH_SPI_AT25DFXXX {
+        alias           { "AT25DFxxx SPI Flash" flash_spi_at25dfxxx }
+        directory       devs/flash/spi/at25dfxxx
+        script          flash_at25dfxxx.cdl
+        hardware
+        description "
+        Support for AT25DFxxx SPI flash devices from Atmel."
+}
+
+package CYGPKG_DEVS_FLASH_SPI_M25PXX {
+        alias           { "M25Pxx SPI Flash" flash_spi_m25pxx }
+        directory       devs/flash/spi/m25pxx
+        script          flash_m25pxx.cdl
+        hardware
+        description "
+        Support for M25Pxx SPI flash devices."
+}
+
+package CYGPKG_DEVS_FLASH_SPI_SST25XX {
+        alias           { "SST25xx SPI Flash" flash_spi_sst25xx }
+        directory       devs/flash/spi/sst25xx
+        script          flash_sst25xx.cdl
+        hardware
+        description "
+        Support for SST25xx SPI flash devices from Silicon Storage
+        Technology."
+}
+
+package CYGPKG_DEVS_FLASH_SST25XX_FREESCALE_DSPI {
+    alias         { "SST25XX FLASH over Freescale DSPI" }
+
+    directory     devs/flash/freescale/dspi/sst25xx
+    script        flash_sst25xx_freescale_dspi.cdl
+    description   "
+        This package provides a driver for SST25XX serial FLASH
+        attached to a Freescale DSPI interfaces."
+}
+
+package CYGPKG_DEVS_FLASH_ARM_PID {
+	alias 		{ "Support for flash memory on ARM/PID board" flash_arm_pid }
+	directory	devs/flash/arm/pid
+	script		flash_arm_pid.cdl
+	hardware
+        description "
+           This package contains hardware support for flash memory
+	   on the ARM PID platform."
+}
+
+package CYGPKG_DEVS_FLASH_ARM_E7T {
+    alias       { "FLASH memory support for the ARM Evaluator-7T" flash_e7t }
+    directory   devs/flash/arm/e7t
+    script      flash_e7t.cdl
+    hardware
+        description "
+           This package contains hardware support for FLASH memory
+       on the ARM Evaluator-7T platform."
+}
+
+package CYGPKG_DEVS_FLASH_EA2468 {
+    alias       { "FLASH memory support for EA LPC2468 OEM board" flash_ea2468 }
+    directory   devs/flash/arm/ea2468
+    script      flash_ea2468.cdl
+    hardware
+        description "
+           This package contains hardware support for FLASH memory
+           on the Embedded Artists LCP2468 OEM board."
+}
+
+package CYGPKG_DEVS_FLASH_SH_EDK7708 {
+	alias 		{ "Support for flash memory on Hitachi/EDK7708 board" flash_sh_edk7708 }
+	directory	devs/flash/sh/edk7708
+	script		flash_sh_edk7708.cdl
+	hardware
+        description "
+           This package contains hardware support for flash memory
+	   on the Hitachi EDK7708 platform."
+}
+
+package CYGPKG_DEVS_FLASH_CQ7750 {
+	alias 		{ "Support for flash memory on CqREEK SH7750 board" flash_cq7750 }
+	directory	devs/flash/sh/cq7750
+	script		flash_cq7750.cdl
+	hardware
+        description "
+           This package contains hardware support for flash memory
+	   on the CqREEK SH7750 platform."
+}
+
+package CYGPKG_DEVS_FLASH_MIPS_OCELOT {
+	alias 		{ "Support for flash memory on PMC-Sierra/Ocelot board" flash_qed_ocelot }
+	directory	devs/flash/mips/ocelot
+	script		flash_mips_ocelot.cdl
+	hardware
+        description "
+           This package contains hardware support for flash memory
+	   on the PMC-Sierra Ocelot platform."
+}
+
+package CYGPKG_DEVS_FLASH_MIPS_VRC437X {
+	alias 		{ "Support for flash memory on VRC437X boards" flash_vrc437x }
+	directory	devs/flash/mips/vrc437x
+	script		flash_mips_vrc437x.cdl
+	hardware
+        description "
+           This package contains hardware support for flash memory
+	   on the VRC437X platform."
+}
+
+package CYGPKG_DEVS_FLASH_MIPS_REFIDT334 {
+	alias 		{ "MIPS IDT 79RC32334 reference platform flash support" flash_refidt334 }
+	directory	devs/flash/mips/idt79s334a
+	script		flash_mips_refidt334.cdl
+	hardware
+        description "
+           This package contains hardware support for flash memory
+	   on the IDT MIPS 334a reference platform."
+}
+
+package CYGPKG_DEVS_FLASH_SH_HS7729PCI {
+        alias           { "Hitachi SH/HS7729PCI FLASH memory support" flash_hs7729pci }
+        directory       devs/flash/sh/hs7729pci
+        script          flash_sh_hs7729pci.cdl
+        hardware
+        description "
+           This package contains hardware support for FLASH memory
+           on the Hitachi/HS7729PCI platform."
+}
+
+package CYGPKG_DEVS_FLASH_SH_SE77X9 {
+        alias           { "Hitachi SH/SE77X9 FLASH memory support" flash_se77x9 }
+        directory       devs/flash/sh/se77x9
+        script          flash_sh_se77x9.cdl
+        hardware
+        description "
+           This package contains hardware support for FLASH memory
+           on the Hitachi/SE77X9 platform."
+}
+
+package CYGPKG_DEVS_FLASH_SH_SE7751 {
+        alias           { "Hitachi SH/SE7751 FLASH memory support" flash_se7751 }
+        directory       devs/flash/sh/se7751
+        script          flash_sh_se7751.cdl
+        hardware
+        description "
+           This package contains hardware support for FLASH memory
+           on the Hitachi/SE7751 platform."
+}
+
+package CYGPKG_DEVS_FLASH_SH_MICRODEV {
+        alias           { "SuperH SH4-202 MicroDev CPU board FLASH memory support" flash_microdev }
+        directory       devs/flash/sh/microdev
+        script          flash_microdev.cdl
+        hardware
+        description "
+           This package contains hardware support for FLASH memory
+           on the SuperH SH4-202 MicroDev CPU board platform."
+}
+
+package CYGPKG_DEVS_FLASH_EBSA285 {
+	alias 		{ "FLASH memory support for StrongARM EBSA-285" flash_ebsa285 }
+	directory	devs/flash/arm/ebsa285
+	script		flash_ebsa285.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the StrongARM EBSA-285 platform."
+}
+
+package CYGPKG_DEVS_FLASH_SA1100MM {
+	alias 		{ "FLASH memory support for StrongARM SA1100 Multimedia" flash_sa1100mm }
+	directory	devs/flash/arm/sa1100mm
+	script		flash_sa1100mm.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the StrongARM SA1100 Multimedia platform."
+}
+
+package CYGPKG_DEVS_FLASH_EDB7XXX {
+	alias 		{ "FLASH support for Cirrus Logic EP7xxx based boards" flash_edb7xxx }
+	directory	devs/flash/arm/edb7xxx
+	script		flash_edb7xxx.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Cirrus Logic EP7xxx based platform(s)."
+}
+
+package CYGPKG_DEVS_FLASH_AT91 {
+	alias 		{ "FLASH memory support for Atmel AT91 EFC" flash_at91 }
+	directory	devs/flash/arm/at91
+	script		flash_at91.cdl
+	hardware
+        description "
+           This package contains hardware support for Embedded FLASH 
+           controller as found in the AT91SAM7S platform"
+}
+
+package CYGPKG_DEVS_FLASH_EB40 {
+	alias 		{ "FLASH memory support for Atmel AT91/EB40" flash_eb40 }
+	directory	devs/flash/arm/eb40
+	script		flash_eb40.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Atmel AT91/EB40 platform(s)."
+}
+
+package CYGPKG_DEVS_FLASH_EB40A {
+	alias 		{ "FLASH memory support for Atmel AT91/EB40A" flash_eb40a }
+	directory	devs/flash/arm/eb40a
+	script		flash_eb40a.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Atmel AT91/EB40A platform(s)."
+}
+
+package CYGPKG_DEVS_FLASH_EB42 {
+	alias 		{ "FLASH memory support for Atmel AT91/EB42" flash_eb42 }
+	directory	devs/flash/arm/eb42
+	script		flash_eb42.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Atmel AT91/EB42 platform(s)."
+}
+
+package CYGPKG_DEVS_FLASH_EB55 {
+	alias 		{ "FLASH memory support for Atmel AT91/EB55" flash_eb55 }
+	directory	devs/flash/arm/eb55
+	script		flash_eb55.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Atmel AT91/EB55 platform(s)."
+}
+
+package CYGPKG_DEVS_FLASH_JTST {
+	alias 		{ "FLASH memory support for Atmel JTST" flash_jtst }
+	directory	devs/flash/arm/jtst
+	script		flash_jtst.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Atmel JTST platform(s)."
+}
+
+package CYGPKG_DEVS_FLASH_PHYCORE {
+	alias 		{ "FLASH memory support for PHYTEC phyCORE AT91M55800A" flash_phycore }
+	directory	devs/flash/arm/phycore
+	script		flash_phycore.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the PHYTEC phyCORE AT91M55800A platform(s)."
+}
+
+package CYGPKG_DEVS_FLASH_PHYCORE229X {
+        alias           { "FLASH memory support for Phytec phyCORE-LPC229x" flash_phycore229x }
+        directory       devs/flash/arm/phycore229x
+        script          flash_phycore229x.cdl
+        hardware
+        description "
+           This package contains hardware support for FLASH memory
+           on the Phytec phyCORE-LPC229x platform(s)."
+}
+
+package CYGPKG_DEVS_FLASH_ASSABET {
+	alias 		{ "FLASH memory support for Intel SA1110 (Assabet)" flash_assabet }
+	directory	devs/flash/arm/assabet
+	script		flash_assabet.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Intel StrongARM SA-1110 Assabet platform."
+}
+
+package CYGPKG_DEVS_FLASH_CERF {
+	alias 		{ "FLASH memory support for Intrinsyc SA1110 (Cerf)" flash_cerf }
+	directory	devs/flash/arm/cerf
+	script		flash_cerf.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Intrinsyc SA1110 Cerf board."
+}
+
+package CYGPKG_DEVS_FLASH_CERFPDA {
+	alias 		{ "FLASH memory support for Intrinsyc SA1110 (Cerfpda)" flash_cerfpda }
+	directory	devs/flash/arm/cerfpda
+	script		flash_cerfpda.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Intrinsyc SA1110 Cerfpda."
+}
+
+package CYGPKG_DEVS_FLASH_IPAQ {
+	alias 		{ "FLASH memory support for Intel SA1110 (Ipaq)" flash_ipaq }
+	directory	devs/flash/arm/ipaq
+	script		flash_ipaq.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Intel StrongARM SA-1110 iPAQ platform."
+}
+
+package CYGPKG_DEVS_FLASH_FLEXANET {
+      alias           { "FLASH memory support for Flexanet" flash_flexanet }
+      directory       devs/flash/arm/flexanet
+      script          flash_flexanet.cdl
+      hardware
+        description "
+           This package contains hardware support for FLASH memory
+           on the SA-1100 Flexanet platform."
+}
+
+package CYGPKG_DEVS_FLASH_MPC50 {
+	alias 		{ "FLASH memory support for MPC 5.0" flash_mpc50 }
+	directory	devs/flash/arm/mpc50
+	script		flash_mpc50.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the MPC 5.0."
+}
+
+package CYGPKG_DEVS_FLASH_MALTA {
+	alias 		{ "FLASH memory support for MIPS Malta board" flash_malta }
+	directory	devs/flash/mips/malta
+	script		flash_malta.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the MIPS Malta platform."
+}
+
+package CYGPKG_DEVS_FLASH_ARM_EXCALIBUR {
+	alias 		{ "FLASH memory support for Altera ARM9/Excalibur board" flash_excalibur }
+	directory	devs/flash/arm/excalibur
+	script		flash_excalibur.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Altera Excalibur platform."
+}
+
+package CYGPKG_DEVS_FLASH_ARM_SMDK2410 {
+        alias           { "FLASH memory support for Samsung ARM9/SMDK2410 board" flash_smdk2410 }
+        directory       devs/flash/arm/smdk2410
+        script          flash_smdk2410.cdl
+        hardware
+        description "
+           This package contains hardware support for FLASH memory
+           on the Samsung smdk2410 platform."
+}
+
+package CYGPKG_DEVS_FLASH_ARM_INNOVATOR {
+	alias 		{ "FLASH memory support for the Innovator" flash_innovator }
+	directory	devs/flash/arm/innovator
+	script		flash_innovator.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Innovator platform."
+}
+
+package CYGPKG_DEVS_FLASH_ARM_AIM711 {
+        alias           { "Support for flash memory on AIM 711 board" flash_arm_snds }
+        directory       devs/flash/arm/aim711
+        script          flash_arm_aim711.cdl
+        hardware
+        description "
+           This package contains hardware support for flash memory
+           on the ARM Industrial Module AIM 711 platform."
+}
+
+package CYGPKG_DEVS_FLASH_NANO {
+	alias 		{ "FLASH memory support for Intel SA1110 nanoEngine" flash_nano }
+	directory	devs/flash/arm/nano
+	script		flash_nano.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the StrongARM SA-1110 nanoEngine platform."
+}
+
+package CYGPKG_DEVS_FLASH_STRATA {
+	alias 		{ "Generic FLASH memory support for Intel StrataFLASH (deprecated)" strata }
+	directory	devs/flash/intel/strata
+	script		flash_strata.cdl
+	hardware
+        description "
+           This package contains generic hardware support for Intel
+	   StrataFLASH memory devices."
+}
+
+package CYGPKG_DEVS_FLASH_STRATA_V2 {
+	alias 		{ "Generic FLASH memory support for Intel StrataFLASH" strata_v2 }
+	directory	devs/flash/intel/stratav2
+	script		flash_strata_v2.cdl
+	hardware
+        description "
+           This package contains generic hardware support for Intel
+	   StrataFLASH memory devices using the V2 device API."
+}
+
+package CYGPKG_DEVS_FLASH_SST_39VFXXX {
+    alias       { "Support for SST 39VFXXX flash memory" flash_sst_39vfXXX }
+    directory   devs/flash/sst/39vfxxx
+    script      flash_sst_39vfxxx.cdl
+    hardware
+        description "
+           This package contains hardware support for SST 39VFxxx
+           flash memory devices. Until now it supports SST 39VF080,
+           39VF016 and 39VF400 devices."
+}
+
+package CYGPKG_DEVS_FLASH_INTEL_28FXXX {
+	alias 		{ "Generic FLASH memory support for Intel 28Fxxx Flash parts" flashfile }
+	directory	devs/flash/intel/28fxxx
+	script		flash_intel_28fxxx.cdl
+	hardware
+        description "
+           This package contains generic hardware support for Intel
+	   Flash memory devices."
+}
+
+package CYGPKG_DEVS_FLASH_ARM_XSCALE_IQ80310 {
+	alias 		{ "FLASH memory support for Cyclone IQ80310" flash_iq80310 }
+	directory	devs/flash/arm/iq80310
+	script		flash_iq80310.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Cyclone IQ80310 platform."
+}
+
+package CYGPKG_DEVS_FLASH_IQ80321 {
+	alias 		{ "FLASH memory support for IQ80321" flash_iq80321 }
+	directory	devs/flash/arm/iq80321
+	script		flash_iq80321.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the IQ80321 platform."
+}
+
+package CYGPKG_DEVS_FLASH_IXDP425 {
+	alias 		{ "FLASH memory support for IXDP425" flash_ixdp425 }
+	directory	devs/flash/arm/ixdp425
+	script		flash_ixdp425.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the IXDP425 platform."
+}
+
+package CYGPKG_DEVS_FLASH_XSENGINE {
+       alias           { "FLASH memory support for XSEngine" flash_xsengine }
+       directory       devs/flash/arm/xsengine
+       script          flash_xsengine.cdl
+       hardware
+       description "
+          This package contains hardware support for FLASH memory
+          on the XSEngine platform."
+}
+
+package CYGPKG_DEVS_FLASH_GRG {
+	alias 		{ "FLASH memory support for GRG" flash_grg }
+	directory	devs/flash/arm/grg
+	script		flash_grg.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Intel Generic Residential Gateway platform."
+}
+
+package CYGPKG_DEVS_FLASH_PRPMC1100 {
+	alias 		{ "FLASH memory support for PrPMC1100" flash_prpmc1100 }
+	directory	devs/flash/arm/prpmc1100
+	script		flash_prpmc1100.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Motorola PrPMC1100 platform."
+}
+
+package CYGPKG_DEVS_FLASH_ARM_INTEGRATOR {
+        alias           { "FLASH memory support for ARM INTEGRATOR" flash_integrator }
+        directory       devs/flash/arm/integrator
+        script          flash_integrator.cdl
+        hardware
+        description "
+           This package contains hardware support for FLASH memory
+           on the ARM INTEGRATOR platform."
+}
+
+package CYGPKG_DEVS_FLASH_MBX {
+	alias 		{ "FLASH memory support for Motorola PowerPC/860 MBX" flash_mbx }
+	directory	devs/flash/powerpc/mbx
+	script		flash_mbx.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Motorola PowerPC/860 MBX platform."
+}
+
+package CYGPKG_DEVS_FLASH_TS6 {
+	alias 		{ "FLASH memory support for Delphi Communication Systems, Inc. TigerSHARC6 Board" flash_ts6 }
+	directory	devs/flash/powerpc/ts6
+	script		flash_ts6.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Delphi Communication Systems TigerSHARC6 platform."
+}
+
+package CYGPKG_DEVS_FLASH_VADS {
+	alias 		{ "FLASH memory support for Motorola MPC8260 Voyager ADS board" flash_vads }
+	directory	devs/flash/powerpc/vads
+	script		flash_vads.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Motorola MPC8260 Voyager ADS platform."
+}
+
+package CYGPKG_DEVS_FLASH_CME555 {
+	alias 		{ "FLASH memory support for Axiom's CME555" flash_cme555 }
+	directory	devs/flash/powerpc/cme555
+	script		flash_cme555.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on Axiom's CME555 board."
+}
+
+package CYGPKG_DEVS_FLASH_EC555 {
+	alias 		{ "FLASH memory support for ec555 board" flash_ec555 }
+	directory	devs/flash/powerpc/ec555
+	script		flash_ec555.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the ec555 board."
+}
+
+package CYGPKG_DEVS_FLASH_PATI {
+       alias           { "FLASH memory support for PowerPC PATI board" flash_pati }
+       directory       devs/flash/powerpc/pati
+       script          flash_pati.cdl
+       hardware
+        description "
+           This package contains hardware support for FLASH memory
+           on the PowerPC PATI platform."
+}
+
+package CYGPKG_DEVS_FLASH_VIPER {
+	alias 		{ "FLASH memory support for A&M Viper PowerPC/8xx" flash_viper }
+	directory	devs/flash/powerpc/viper
+	script		flash_viper.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the A&M PowerPC/8xx VIPER platform."
+}
+
+package CYGPKG_DEVS_FLASH_MN10300_STB {
+	alias 		{ "FLASH memory support for Matsushita MN10300 STB" flash_stb }
+	directory	devs/flash/mn10300/stb
+	script		flash_stb.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Matsushita MN10300 STB platform (SRAM2 socket)."
+}
+
+package CYGPKG_DEVS_FLASH_MN10300_ASB2303 {
+	alias 		{ "FLASH memory support for Matsushita ASB2303" flash_asb2303 }
+	directory	devs/flash/mn10300/asb2303
+	script		flash_asb2303.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Matsushita MN10300 ASB2303 platform (system flash socket)."
+}
+
+package CYGPKG_DEVS_FLASH_MN10300_ASB2305 {
+	alias 		{ "FLASH memory support for Matsushita ASB2305" flash_asb2305 }
+	directory	devs/flash/mn10300/asb2305
+	script		flash_asb2305.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Matsushita MN10300 ASB2305 platform (system flash socket)."
+}
+
+package CYGPKG_DEVS_FLASH_ATLAS {
+	alias 		{ "FLASH memory support for MIPS Atlas" flash_atlas }
+	directory	devs/flash/mips/atlas
+	script		flash_atlas.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the MIPS Atlas platform."
+}
+package CYGPKG_DEVS_FLASH_SYNTH {
+    alias               { "Synthetic FLASH memory support (legacy)" synth_flash flash_synth }
+    directory           devs/flash/synth
+    script              flash_synth.cdl
+    hardware
+    description   "
+        FLASH memory device support for Synthetic target"
+}
+
+package CYGPKG_DEVS_FLASH_SYNTH_V2 {
+    alias               { "Synthetic FLASH memory support" synth_flashv2 flash_synthv2 }
+    directory           devs/flash/synthv2
+    script              flash_synth.cdl
+    hardware
+    description   "
+        FLASH memory device support for Synthetic target using the new API"
+}
+
+package CYGPKG_DEVS_FLASH_TOSHIBA_TC58XXX {
+	alias 		{ "Support for Toshiba TC58xxx flash memory" flash_toshiba_tc58xxx }
+	directory	devs/flash/toshiba/tc58xxx
+	script		flash_toshiba_tc58xxx.cdl
+	hardware
+        description "
+           This package contains hardware support for Toshiba TC58xxx
+           NAND flash memory devices."
+}
+
+package CYGPKG_DEVS_FLASH_FRV_FRV400 {
+        alias           { "Fujitsu FRV400 FLASH memory support" flash_frv400 }
+        directory       devs/flash/frv/frv400
+        script          flash_frv_frv400.cdl
+        hardware
+        description "
+           This package contains hardware support for FLASH memory
+           on the Fujitsu FRV400 platform."
+}
+
+package CYGPKG_DEVS_FLASH_FRV_PDK403 {
+        alias           { "Fujitsu MB93093 FLASH memory support" flash_mb93093 }
+        directory       devs/flash/frv/pdk403
+        script          flash_frv_pdk403.cdl
+        hardware
+        description "
+           This package contains hardware support for FLASH memory
+           on the Fujitsu MB93093-PD00 Portable Development Kit."
+}
+
+package CYGPKG_DEVS_FLASH_ARM_LPC2XXX {
+        alias           { "Support for the internal flash memory of LPC2xxx devices" flash_arm_lpc2xxx }
+        directory       devs/flash/arm/lpc2xxx
+        script          flash_arm_lpc2xxx.cdl
+        hardware
+        description     "
+           This package contains hardware support for the internal
+           flash memory of the LPC2xxx devices."
+}
+
+package CYGPKG_DEVS_FLASH_ARM_OLPCX2294 {
+        alias           { "Support for Flash memory on Olimex LPC-E2294, LPC-H2294, LPC-L2294-1M boards" flash_olpcx2294 }
+        directory       devs/flash/arm/olpcx2294
+        script          flash_olpcx2294.cdl
+        hardware
+        description "
+        This package contains hardware support for flash memory parts
+        on the Olimex LPC-E2294, LPC-H2294 LPC-L2294-1M platforms."
+
+}
+
+package CYGPKG_DEVS_FLASH_ARM_OLPCX2294_V2 {
+        alias           { "External Flash memory support for OLPCE2294, OLPCH2294, OLPCL2294" flash_olpcx2294_v2 }
+        directory       devs/flash/arm/olpcx2294v2
+        script          flash_olpcx2294.cdl
+        hardware
+        description "
+            The flash_olpcx2294_v2 provides hardware support for external
+            flash memory parts on the Olimex LPC-E2294, LPC-H2294,
+            and LPC-L2294-1M boards. It uses eCos Flash v2 API."
+}
+
+package CYGPKG_DEVS_FLASH_KINETIS {
+	alias           { "Internal FLASH memory support for freescale kinetis" }
+    directory       devs/flash/freescale/kinetis
+    script          kinetis_flash.cdl
+    hardware
+    description "
+    This package contains hardware support for the internal FLASH memory
+    on kinetis devices."
+}
+
+package CYGPKG_DEVS_RAM_MICRON_CELLULARRAM {
+	alias		{ "Micron CellularRam 1.5 support" }
+	directory	hal/misc/ram/micron/cellularram
+	script		ram_micron_cellularram.cdl
+	hardware
+        description "
+           This package contains hardware support for Micron
+           CellularRam memory devices."
+}
+
+package CYGPKG_DEVS_TOUCH_IPAQ {
+	alias 		{ "Touch screen support for iPAQ" touch_ipaq }
+	directory	devs/touch/arm/ipaq
+	script		touch_ipaq.cdl
+	hardware
+        description "
+           This package contains hardware support for the touch screen
+	   on the Compaq iPAQ Pocket PC."
+}
+
+package CYGPKG_DEVS_KBD_IPAQ {
+	alias 		{ "Keypad/button support for iPAQ" kbd_ipaq }
+	directory	devs/kbd/arm/ipaq
+	script		kbd_ipaq.cdl
+	hardware
+        description "
+           This package contains hardware support for the keyboard buttons
+	   on the Compaq iPAQ Pocket PC."
+}
+
+package CYGPKG_DEVS_TOUCH_AAED2000 {
+	alias 		{ "Touch screen support for Agilent AAED2000" touch_aaed2000 }
+	directory	devs/touch/arm/aaed2000
+	script		touch_aaed2000.cdl
+	hardware
+        description "
+           This package contains hardware support for the touch screen
+	   on the Agilent AAED2000 prototype."
+}
+
+package CYGPKG_DEVS_KBD_AAED2000 {
+	alias 		{ "Keyboard support for Agilent AAED2000" kbd_aaed2000 }
+	directory	devs/kbd/arm/aaed2000
+	script		kbd_aaed2000.cdl
+	hardware
+        description "
+           This package contains hardware support for the keyboard
+	   on the Agilent AAED2000 prototype."
+}
+
+package CYGPKG_IO_SERIAL_ARM_EBSA285 {
+    alias 	      { "Intel EBSA285 serial driver"
+                        devs_serial_arm_ebsa285 ebsa285_serial_driver }
+    hardware
+    directory	      devs/serial/arm/ebsa285
+    script	      ser_arm_ebsa285.cdl	
+    description       "Intel StrongARM/EBSA285 serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_ARM_XSCALE_PXA2X0 {
+    alias         { "Intel XScale PXA2X0 serial driver"
+                        devs_serial_arm_xscale_pxa pxa_serial_driver }
+    hardware
+    directory        devs/serial/arm/pxa2x0
+    script        ser_arm_xscale_pxa2x0.cdl
+    description       "Intel XScale/PXA2X0 serial device drivers"
+}
+
+
+package CYGPKG_IO_SERIAL_ARM_XSCALE_IOP310 {
+    alias 	      { "Intel XScale IOP310 serial driver"
+                        devs_serial_arm_iop310 iop310_serial_driver }
+    hardware
+    directory	      devs/serial/arm/iop310
+    script	      ser_arm_iop310.cdl	
+    description       "Intel XScale IOP310 serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_ARM_IQ80321 {
+    alias 	      { "Intel XScale IQ80321 serial driver"
+                        devs_serial_arm_iq80321 iq80321_serial_driver }
+    hardware
+    directory	      devs/serial/arm/iq80321
+    script	      ser_arm_iq80321.cdl	
+    description       "Intel XScale/IQ80321 serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_ARM_SA11X0 {
+    alias 	      { "Intel StrongARM SA11x0 serial driver"
+                        devs_serial_arm_sa11x0 sa11x0_serial_driver }
+    hardware
+    directory	      devs/serial/arm/sa11x0
+    script	      ser_arm_sa11x0.cdl	
+    description       "Intel StrongARM/SA11x0 serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_ARM_PID {
+    alias             { "ARM PID serial device drivers"
+                        devs_serial_arm_pid pid_serial_driver }
+    hardware
+    directory	      devs/serial/arm/pid
+    script	      ser_arm_pid.cdl	
+    description       "ARM PID serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_ARM_CERFPDA {
+    alias             { "Cerfpda 16x5x serial device drivers"
+                        devs_serial_arm_cerfpda cerfpda_serial_driver }
+    hardware
+    directory	      devs/serial/arm/cerfpda
+    script	      ser_arm_cerfpda.cdl	
+    description       "Cerfpda serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_ARM_AEB {
+    alias             { "ARM AEB-1 serial device drivers"
+                        devs_serial_arm_aeb aeb_serial_driver }
+    hardware
+    directory	      devs/serial/arm/aeb
+    script	      ser_arm_aeb.cdl	
+    description       "ARM AEB-1 serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_ARM_AAED2000 {
+    alias             { "Agilent AAED2000 serial device drivers"
+                        devs_serial_arm_aaed2000 aaed2000_serial_driver }
+    hardware
+    directory	      devs/serial/arm/aaed2000
+    script	      ser_arm_aaed2000.cdl
+    description       "Agilent AAED2000 serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_ARM_SMDK2410 {
+    alias             { "Samsung ARM9/SMDK2410 board serial device drivers"
+                        devs_serial_arm_smdk2410 smdk2410_serial_driver }
+    hardware
+    directory         devs/serial/arm/smdk2410
+    script            ser_arm_smdk2410.cdl        
+    description       "Samsung ARM9/SMDK2410 board serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_ARM_EDB7XXX {
+    alias             { "Cirrus Logic ARM based board serial device drivers"
+                        devs_serial_arm_edb7xxx edb7xxx_serial_driver }
+    hardware
+    directory	      devs/serial/arm/edb7xxx
+    script	      ser_arm_edb7xxx.cdl	
+    description       "Cirrus Logic ARM based development board serial
+                       device drivers"
+}
+
+package CYGPKG_IO_SERIAL_ARM_CMA230 {
+    alias             { "Cogent ARM/CMA230 serial device drivers"
+                        devs_serial_arm_cma230 cma230_serial_driver }
+    hardware
+    directory	      devs/serial/arm/cma230
+    script	      ser_arm_cma230.cdl	
+    description       "Cogent ARM/CMA230 serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_ARM_E7T {
+    alias             { "ARM AEB-2 (E7T) serial device drivers"
+                        devs_serial_arm_e7t e7t_serial_driver }
+    hardware
+    directory         devs/serial/arm/e7t
+    script            ser_arm_e7t.cdl   
+    description       "ARM AEB-2 (E7T) serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_ARM_S3C4510 {
+    alias             { "Generig ARM S3C4510 serial device driver"
+                        devs_serial_arm_s3c4510 s3c4510_serial_driver }
+    hardware
+    directory         devs/serial/arm/s3c4510
+    script            ser_arm_s3c4510.cdl
+    description       "Generic serial device driver for the internal
+                       serial interface of the S3C4510"
+}
+
+package CYGPKG_IO_SERIAL_ARM_AIM711 {
+    alias             { "AIM 711 serial device drivers"
+                        devs_serial_arm_aim711 aim711_serial_driver }
+    hardware
+    directory         devs/serial/arm/aim711
+    script            ser_arm_aim711.cdl
+    description       "ARM Industral Module AIM 711 serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_ARM_INTEGRATOR {
+    alias             { "ARM INTEGRATOR serial device drivers"
+                        devs_serial_arm_integrator integrator_serial_driver }
+    hardware
+    directory         devs/serial/arm/integrator
+    script            ser_arm_integrator.cdl    
+    description       "ARM INTEGRATOR serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_ARM_AT91 {
+    alias 	      { "Atmel AT91 serial device driver"
+                        devs_serial_arm_at91 at91_serial_driver }
+    hardware
+    directory	      devs/serial/arm/at91
+    script	      ser_arm_at91.cdl	
+    description       "Atmel AT91 on-chip serial device driver."
+}
+
+package CYGPKG_IO_SERIAL_ARM_LPC2XXX {
+    alias             { "ARM LPC2XXX serial device drivers"
+                        devs_serial_arm_lpc2xxx lpc2xxx_serial_driver }
+    hardware
+    directory         devs/serial/arm/lpc2xxx
+    script            ser_arm_lpc2xxx.cdl
+    description       "ARM LPC2XXX serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_ARM_LPC24XX {
+    alias             { "ARM LPC24XX/LPC17XX serial device drivers" }
+    hardware
+    directory         devs/serial/arm/lpc24xx
+    script            ser_arm_lpc24xx.cdl
+    description       "ARM LPC24XX/LPC17XX serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_CORTEXM_A2FXXX {
+    alias             { "Cortex-M3/Actel Smartfusion (A2Fxxx) serial device drivers"
+                        devs_serial_cortexm_a2fxxx a2fxxx_serial_driver }
+    hardware
+    directory         devs/serial/cortexm/a2fxxx
+    script            ser_cortexm_a2fxxx.cdl
+    description       "Cortex-M3/Actel Smartfusion serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_POWERPC_COGENT {
+    alias             { "Cogent PowerPC serial device drivers"
+                        devs_serial_powerpc_cogent cogent_serial_driver }
+    hardware
+    directory	      devs/serial/powerpc/cogent
+    script	      ser_powerpc_cogent.cdl	
+    description       "Cogent PowerPC serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_POWERPC_MPC555 {
+    alias             { "mpc555 PowerPC serial device drivers"
+                        devs_serial_powerpc_mpc555 mpc555_serial_driver }
+    hardware
+    directory	      devs/serial/powerpc/mpc555
+    script	      ser_powerpc_mpc555.cdl	
+    description       "mpc555 PowerPC serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_FREESCALE_ESCI_H {
+    alias             { "ESCI serial device header"
+                        devs_serial_freescale_esci_h esci_serial_header }
+    hardware
+    directory	      devs/serial/freescale/esci/hdr
+    script	      ser_freescale_esci_h.cdl	
+    description       "Freescale eSCI - Enhanced Serial Communications Interface header.
+                       Needed by hal_diag and ser_esci drivers."
+}
+
+package CYGPKG_IO_SERIAL_FREESCALE_ESCI {
+    alias             { "ESCI serial device driver"
+                        devs_serial_freescale_esci esci_serial_driver }
+    hardware
+    directory	      devs/serial/freescale/esci/drv
+    script	      ser_freescale_esci.cdl	
+    description       "Freescale eSCI - Enhanced Serial Communications Interface serial device driver"
+}
+
+package CYGPKG_IO_SERIAL_FREESCALE_UART_HDR {
+    alias             { "Freescale UART serial device header"
+                        devs_serial_freescale_uart_hdr freescale_uart_serial_header }
+    hardware
+    directory	      devs/serial/freescale/uart/hdr
+    script	      ser_freescale_uart_hdr.cdl
+    description       "Freescale UART header.
+                       Needed by hal_diag and ser_freescale_uart drivers."
+}
+
+package CYGPKG_IO_SERIAL_FREESCALE_UART {
+    alias             { "Freescale UART serial device driver"
+                        devs_serial_freescale_uart freescale_uart_serial_driver }
+    hardware
+    directory	      devs/serial/freescale/uart/drv
+    script	      ser_freescale_uart.cdl
+    description       "Freescale UART driver."
+}
+
+package CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC {
+    alias             { "PowerPC QUICC/SMC serial device drivers"
+                        devs_serial_quicc_smc quicc_smc_serial_driver
+                        devs_serial_powerpc_quicc_smc
+                        devs_serial_powerpc_quicc quicc_serial_driver }
+    hardware
+    directory	      devs/serial/powerpc/quicc
+    script	      ser_quicc_smc.cdl	
+    description       "PowerPC QUICC/SMC serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_POWERPC_MPC8XXX {
+    alias             { "PowerPC MPC8XXX (QUICC-II) serial device drivers"
+                        devs_serial_powerpc_mpc8xxx mpc8xxx_serial_driver }
+    hardware
+    directory	      devs/serial/powerpc/mpc8xxx
+    script	      ser_mpc8xxx.cdl	
+    description       "PowerPC MPC8XXX (QUICC-II) serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC {
+    alias             { "PowerPC VADS QUICC2/SCC serial device drivers"
+                        devs_serial_quicc2_scc quicc2_scc_serial_driver
+                        devs_serial_powerpc_quicc2_scc
+                        devs_serial_powerpc_quicc2 quicc2_serial_driver }
+    hardware
+    directory	      devs/serial/powerpc/quicc2
+    script	      ser_quicc2_scc.cdl	
+    description       "PowerPC VADS QUICC2/SCC serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_POWERPC_PPC405 {
+    alias             { "PowerPC PPC405GP serial device drivers" devs_serial_ppc405 }
+    hardware
+    directory	      devs/serial/powerpc/ppc405
+    script	      ser_powerpc_ppc405.cdl	
+    description       "PowerPC PPC405GP serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_SPARCLITE_SLEB {
+    alias             { "SPARClite SLEB serial device drivers"
+                        devs_serial_sparclite_sleb sleb_serial_driver }
+    hardware
+    directory	      devs/serial/sparclite/sleb
+    script	      ser_sparclite_sleb.cdl	
+    description       "SPARClite SLEB serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_TX39_JMR3904 {
+    alias             { "TX39 JMR3904 serial device drivers"
+                        devs_serial_tx39_jmr3904 jmr3904_serial_driver
+                        devs_serial_mips_jmr3904 tx3904_serial_driver }
+    hardware
+    directory	      devs/serial/mips/jmr3904
+    script	      ser_mips_jmr3904.cdl	
+    description       "TX39 JMR3904 serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_MIPS_ATLAS {
+    alias             { "Atlas serial device drivers"
+                        devs_serial_atlas atlas_serial_driver
+                        devs_serial_mips_atlas mips_atlas_serial_driver }
+    hardware
+    directory	      devs/serial/mips/atlas
+    script	      ser_mips_atlas.cdl	
+    description       "Atlas serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_MIPS_REF4955 {
+    alias             { "TX49 REF4955 serial device drivers"
+                        devs_serial_mips_ref4955 ref4955_serial_driver }
+    hardware
+    directory	      devs/serial/mips/ref4955
+    script	      ser_mips_ref4955.cdl	
+    description       "TX49 REF4955 serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_MIPS_VRC437X {
+    alias             { "VRC437X serial device drivers"
+                        devs_serial_mips_vrc437x vrc437x_serial_driver }
+    hardware
+    directory	      devs/serial/mips/vrc437x
+    script	      ser_mips_vrc437x.cdl	
+    description       "VRC437X serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_MN10300 {
+    alias             { "MN10300 serial device drivers"
+                        devs_serial_mn10300_mn10300
+                        devs_serial_mn10300 mn10300_serial_driver }
+    hardware
+    directory	      devs/serial/mn10300/mn10300
+    script	      ser_mn10300.cdl	
+    description       "MN10300 serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_I386_PC {
+    alias             { "PC serial device drivers"
+                        devs_serial_i386_pc pc_serial_driver }
+    hardware
+    directory	      devs/serial/i386/pc
+    script	      ser_i386_pc.cdl	
+    description       "PC serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_GENERIC_16X5X {
+    alias             { "16x5x compatible serial device drivers"
+                        devs_serial_generic_16x5x 16x5x_serial_driver }
+    hardware
+    directory	      devs/serial/generic/16x5x
+    script	      ser_generic_16x5x.cdl
+    description       "16x5x compatible serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_SH_SCI {
+    alias             { "SH SCI serial device drivers"
+                        devs_serial_sh_sci sh_sci_serial_driver }
+    hardware
+    directory	      devs/serial/sh/sci
+    script	      ser_sh_sci.cdl	
+    description       "SH SCI serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_SH_SCIF {
+    alias             { "SH SCIF serial device drivers"
+                        devs_serial_sh_scif scif_serial_driver }
+    hardware
+    directory	      devs/serial/sh/scif
+    script	      ser_sh_scif.cdl	
+    description       "SH SCIF serial device drivers"
+}
+
+package CYGPKG_DEVS_ETH_PHY {
+	alias 		{ "Generic PHY support" eth_phy_support }
+	hardware
+	directory	devs/eth/phy
+	script		phy_eth_drivers.cdl
+        description     "PHY (ethernet physical transciever) API."
+}
+
+package CYGPKG_DEVS_ETH_ARM_CERF {
+	alias 		{ "Crystal LAN ethernet driver for Cerf boards" cerf_eth_driver }
+	hardware
+	directory	devs/eth/arm/cerf
+	script		cerf_eth_drivers.cdl
+        description     "Ethernet driver for Crystal LAN on Cerf based
+                         development boards."
+}
+
+package CYGPKG_DEVS_ETH_ARM_CERFPDA {
+	alias 		{ "Crystal LAN ethernet driver for the Cerfpda" cerfpda_eth_driver }
+	hardware
+	directory	devs/eth/arm/cerfpda
+	script		cerfpda_eth_drivers.cdl
+        description     "Ethernet driver for Crystal LAN on the Cerfpda."
+}
+
+package CYGPKG_DEVS_ETH_ARM_NETARM {
+	alias 		{ "Ethernet driver for the NETARM" NETARM_eth_driver }
+	hardware
+	directory	devs/eth/arm/netarm
+	script		netarm_eth_driver.cdl
+        description     "Ethernet driver for NETARM."
+}
+
+package CYGPKG_DEVS_ETH_ARM_PHYCORE229X {
+      alias           { "Ethernet driver for phyCORE-LPC229x board" devs_eth_arm_phycore229x }
+      hardware
+      directory       devs/eth/arm/phycore229x
+      script          phycore229x_eth_drivers.cdl
+      description     "Ethernet device driver for phyCORE-LPC229x board"
+}
+
+package CYGPKG_DEVS_ETH_ARM_OLPCE2294 {
+        alias           { "Ethernet driver for Olimex LPC-E2294 board" olpce2294_eth_driver }
+        hardware
+        directory       devs/eth/arm/olpce2294
+        script          olpce2294_eth_drivers.cdl
+        description     "
+            Ethernet device driver for Olimex LPC-E2294 board."
+}
+
+package CYGPKG_DEVS_ETH_ARM_OLPCL2294 {
+        alias           { "Ethernet driver for Olimex LPC-L2294-1MB board" olpcl2294_eth_driver }
+        hardware
+        directory       devs/eth/arm/olpcl2294
+        script          olpcl2294_eth_drivers.cdl
+        description     "
+            Ethernet device driver for Olimex LPC-L2294-1MB board."
+}
+
+package CYGPKG_DEVS_ETH_FREESCALE_ENET {
+        alias           { "Freescale ENET Ethernet driver" }
+        directory       devs/eth/freescale/enet
+        script          eth_freescale_enet.cdl
+        hardware
+        description     "Ethernet driver for the Freescale ENET ethernet controller."
+}
+
+package CYGPKG_DEVS_ETH_CORTEXM_A2FXXX {
+    alias        { "Cortex-M3/Actel Smartfusion (A2Fxxx) ethernet driver" a2fxxx_eth_driver }
+    directory    devs/eth/cortexm/a2fxxx
+    script       a2fxxx_eth.cdl
+    hardware
+    description  "Actel A2Fxxx Ethernet driver for Cortex-M3 A2Fxxx based boards."
+}
+
+package CYGPKG_IO_SERIAL_SH_EDK7708 {
+    alias             { "SH3 EDK7708 serial device drivers"
+                        devs_serial_sh3_edk7708
+                        devs_serial_sh_edk7708 edk7708_serial_driver }
+    hardware
+    directory	      devs/serial/sh/edk7708
+    script	      ser_sh_edk7708.cdl	
+    description       "SH3 EDK7708 serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_SH_CQ7708 {
+    alias             { "SH3 cq7708 serial device drivers"
+                        devs_serial_sh3_cq7708
+                        devs_serial_sh_cq7708 cq7708_serial_driver }
+    hardware
+    directory	      devs/serial/sh/cq7708
+    script	      ser_sh_cq7708.cdl	
+    description       "SH3 cq7708 serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_SH_SE77X9 {
+    alias             { "SH3 SE77X9 serial device driver"
+                        devs_serial_sh3_se77x9 se77x9_serial_driver }
+    hardware
+    directory	      devs/serial/sh/se77x9
+    script	      ser_sh_se77x9.cdl	
+    description       "SH3 SE77x9 serial device driver"
+}
+
+package CYGPKG_IO_SERIAL_SH_SH4_202_MD {
+    alias             { "SH4-202 MicroDev serial device driver"
+                        devs_serial_sh4_202_md sh4_202_md_serial_driver }
+    hardware
+    directory	      devs/serial/sh/sh4_202_md
+    script	      ser_sh4_202_md.cdl	
+    description       "This option enables the serial device drivers for the
+        SuperH SH4-202 MicroDev board, based on the generic SH SCIF driver."
+}
+
+package CYGPKG_IO_SERIAL_V85X_V850 {
+    alias             { "NEC V850 serial device drivers"
+                        devs_serial_v85x_v850 v850_serial_driver }
+    hardware
+    directory	      devs/serial/v85x/v850
+    script	      ser_v85x_v850.cdl	
+    description       "Serial device drivers for systems based on NEC V850
+                       SA1 (70F3017) or SB1 (70F3033) processors."
+}
+
+package CYGPKG_IO_SERIAL_MIPS_UPD985XX {
+    alias 	      { "NEC MIPS uPD985xx serial driver"
+                        devs_serial_mips_upd985xx upd985xx_serial_driver }
+    hardware
+    directory	      devs/serial/mips/upd985xx
+    script	      ser_mips_upd985xx.cdl	
+    description       "NEC MIPS uPD985xx serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_MIPS_IDT79S334A {
+    alias             { "MIPS IDT 79RC32334 reference platform serial device drivers"
+                        devs_serial_idt79s334a idt79s334a_serial_driver
+                        devs_serial_mips_idt79s334 mips_idt79s334a_serial_driver }
+    hardware
+    directory	      devs/serial/mips/idt79s334a
+    script	      ser_mipsidt_334a.cdl	
+    description       "IDT 334a reference platform serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_H8300_SCI {
+    alias             { "H8/300 SCI serial device drivers"
+                        devs_serial_h8300h_sci h8300h_sci_serial_driver }
+    hardware
+    directory       devs/serial/h8300/h8300h
+    script          serial_h8300.cdl  
+    description       "H8/300 SCI serial device drivers"
+}
+
+package CYGPKG_IO_SERIAL_MCF5272_UART {
+    alias             { "MCF5272 Serial UART Drivers"
+                         devs_MCF5272_uart_driver }
+    hardware
+    directory	      devs/serial/mcf52xx/mcf5272
+    script	      ser_mcf5272_uart.cdl	
+    description       "Serial MCF5272 UART Drivers."
+}
+
+package CYGPKG_IO_SERIAL_LOOP {
+    alias             { "Loop serial device drivers"
+                        devs_serial_loop loop_serial_driver }
+    directory	      devs/serial/loop
+    script	      ser_loop.cdl	
+    description       "Loopback serial device driver."
+}
+
+package CYGPKG_IO_FILEIO {
+	alias 		{ "File IO" fileio io_file }
+	directory	io/fileio
+	script		fileio.cdl
+        description "
+	   This package contains the infrastructure for doing POSIX compliant
+	   file IO."
+}
+
+package CYGPKG_FS_RAM {
+	alias 		{ "RAM Filesystem" ramfs ram_fs fs_ram }
+	directory	fs/ram
+	script		ramfs.cdl
+        description "
+	   This package contains a RAM resident filesystem."
+}
+
+package CYGPKG_FS_ROM {
+	alias 		{ "ROM Filesystem" romfs rom_fs fs_rom }
+	directory	fs/rom
+	script		romfs.cdl
+        description "
+	   This package contains a ROM resident filesystem."
+}
+
+package CYGPKG_FS_JFFS2 {
+	alias 		{ "JFFS2 Filesystem" jffs2 }
+	directory	fs/jffs2
+	script		jffs2.cdl
+        description "
+	   This package contains the JFFS2 filesystem."
+}
+
+package CYGPKG_LINUX_COMPAT {
+        alias           { "Linux compatibility" linux_compat linuxcompat }
+        directory       compat/linux
+        script          linux.cdl
+        description "
+eCos supports a basic Linux compatibility Layer providing various
+functions, equivalents or stubs expected by Linux kernel code, for
+assistance in porting drivers and file system code from Linux.
+Note this does not provide Linux compatibility to applications."
+}
+
+package CYGPKG_IO_ETH_DRIVERS {
+	alias 		{ "Common ethernet support" net_drivers eth_drivers CYGPKG_NET_ETH_DRIVERS }
+	directory	io/eth
+	script		eth_drivers.cdl
+        description     "Platform independent ethernet support."
+}
+
+package CYGPKG_IO_USB { 
+        alias           { "Generic USB support" usb }
+        hardware
+        directory       io/usb/common
+        script          usb.cdl
+        description     "Generic USB support"
+}
+
+package CYGPKG_IO_USB_SLAVE {
+	alias           { "Generic USB slave-side support" usbs }
+        hardware
+        directory       io/usb/slave
+        script          usbs.cdl
+	description     "Generic USB slave-side support"
+}
+
+package CYGPKG_IO_USB_SLAVE_ETH {
+        alias		{ "USB slave-side ethernet class drivers" usbs_eth }
+        directory       io/usb/eth/slave
+        script          usbs_eth.cdl
+        description     "Support for USB peripherals that provide an ethernet-class function"
+}
+
+package CYGPKG_IO_USB_SLAVE_SERIAL {
+        alias		{ "USB slave-side serial drivers" usbs_serial }
+        directory       io/usb/serial/slave
+        script          usbs_serial.cdl
+        description     "Support for USB peripherals that present themselves 
+                         as serial devices to the host."
+}
+
+package CYGPKG_IO_USB_SLAVE_MSD {
+       alias           { "USB slave-side mass-storage drivers" usbs_msd }
+       directory       io/usb/msd/slave
+       script          usbs_msd.cdl
+       description     "Support for USB peripherals that present themselves 
+                        as mass storage devices to the host."
+}
+
+package CYGPKG_DEVS_USB_SA11X0 {
+        alias           { "Device-driver for the SA11X0 on-chip USB support" usb_sa11x0 }
+        hardware
+        directory       devs/usb/sa11x0
+        script          usbs_sa11x0.cdl
+        description     "A device driver for the SA11X0 on-chip USB slave port"
+}
+
+package CYGPKG_DEVS_USB_UPD985XX {
+        alias           { usb_upd985xx }
+        hardware
+        directory       devs/usb/nec_upd985xx
+        script          usbs_upd985xx.cdl
+        description     "A device driver for the NEC uPD985xx on-chip USB device"
+}
+
+package CYGPKG_DEVS_USB_AT91 {
+        alias           { usb_at91 }
+        hardware
+        directory       devs/usb/at91
+        script          usbs_at91.cdl
+        description     "A device driver for the ATMEL AT91 on-chip USB device"
+}
+
+package CYGPKG_DEVS_USB_D12 {
+	alias           { usb_d12 }
+	hardware
+	directory       devs/usb/d12
+	script          usbs_d12.cdl
+	description     "A device driver for the Philips PDIUSBD12 full speed USB peripheral chip."
+}
+
+package CYGPKG_DEVS_USB_I386_SOROD12 {
+	alias           { usb_sorod12 }
+	hardware
+	directory       devs/usb/i386/SoRoD12
+	script          usbs_i386_sorod12.cdl
+	description     "A device driver for the SoRo PC/104 D12 USB Slave Board."
+}
+
+package CYGPKG_NET {
+	alias 		{ "Networking" net }
+	directory	net/common
+	script		net.cdl
+        description     "Generic networking support, including TCP/IP."
+}
+
+package CYGPKG_NET_AUTOTEST {
+	alias 		{ "Network Autotesting" autotest net_autotest }
+	directory	net/autotest
+	script		net_autotest.cdl
+        description     "Automated network testing support."
+}
+
+package CYGPKG_NET_OPENBSD_STACK {
+	alias 		{ "OpenBSD Stack" openbsd_net }
+	directory	net/tcpip
+	script		openbsd_net.cdl
+        description     "TCP/IP stack from OpenBSD."
+}
+
+package CYGPKG_NET_FREEBSD_STACK {
+	alias 		{ "FreeBSD Stack" freebsd_net }
+	directory	net/bsd_tcpip
+	script		freebsd_net.cdl
+        description     "TCP/IP stack from FreeBSD, including KAME IPv6."
+}
+
+package CYGPKG_NET_FTPCLIENT {
+        alias           { "FTP Client" ftpclient }
+        directory       net/ftpclient
+        script          ftpclient.cdl
+        description     "FTP client support for get and put of files."
+}
+
+package CYGPKG_SNMPLIB {
+	alias 		{ "SNMP library" snmplib }
+	directory	net/snmp/lib
+	script		snmplib.cdl
+        description     "UCD SNMP library."
+}
+
+package CYGPKG_SNMPAGENT {
+	alias 		{ "SNMP agent" snmpagent }
+	directory	net/snmp/agent
+	script		snmpagent.cdl
+        description     "UCD SNMP agent."
+}
+
+package CYGPKG_HTTPD {
+	alias 		{ "HTTP server" httpd }
+	directory	net/httpd
+	script		httpd.cdl
+        description     "HTTP server."
+}
+
+package CYGPKG_NS_DNS {
+	alias 		{ "DNS" dns }
+	directory	net/ns/dns
+	script		dns.cdl
+        description     "DNS client support."
+}
+
+package CYGPKG_NET_SNTP {
+        alias           { "SNTP support" sntp }
+        directory       net/sntp
+        script          sntp.cdl
+        description "
+This package provides a SNTP client which can recieve broadcast time 
+information and set the system clock."
+}  
+
+package CYGPKG_PPP {
+	alias 		{ "PPP support" ppp }
+	directory	net/ppp
+	script		ppp.cdl
+        description     "PPP support."
+}
+
+package CYGPKG_NET_IPSEC_LIBIPSEC {
+        alias           { "libipsec support" libipsec }
+        directory       net/ipsec/libipsec
+        script          libipsec.cdl
+        description "
+This package provides the libipsec library used by racoon etc for 
+configuring IPSEC"
+}
+
+package CYGPKG_DEVS_ETH_ARM_EDB7XXX {
+	alias 		{ "Cirrus Logic ethernet driver for EP7xxx boards" edb7xxx_eth_driver }
+	hardware
+	directory	devs/eth/arm/edb7xxx
+	script		edb7xxx_eth_drivers.cdl
+        description     "Ethernet driver for Cirrus Logic EP7xxx based
+                         development boards."
+}
+
+package CYGPKG_DEVS_ETH_ARM_KS32C5000 {
+	alias 		{ "Samsung KS32C5000 ethernet driver" eth_ks32c5000 }
+	hardware
+	directory	devs/eth/arm/ks32c5000
+	script		ks32c5000_eth.cdl
+        description     "Ethernet driver for Samsung ks32c5000/S3c4510."
+}
+
+
+package CYGPKG_DEVS_ETH_ARM_AAED2000 {
+	alias 		{ "Ethernet driver for Agilent AAED2000 board" aaed2000_eth_driver }
+	hardware
+	directory	devs/eth/arm/aaed2000
+	script		aaed2000_eth_drivers.cdl
+        description     "Ethernet driver for Agilent AAED2000
+                         development boards."
+}
+package CYGPKG_DEVS_ETH_AMD_PCNET {
+	alias 		{ "AMD PCNET ethernet driver" pcnet_eth_driver }
+	hardware
+	directory	devs/eth/amd/pcnet
+	script		amd_pcnet_eth_drivers.cdl
+        description     "Ethernet driver for AMD PCNET controller."
+}
+
+package CYGPKG_DEVS_ETH_AMD_LANCEPCI {
+	alias 		{ "AMD Lance PCI ethernet driver" lancepci_eth_driver }
+	hardware
+	directory	devs/eth/amd/lancepci
+	script		amd_lancepci_eth_drivers.cdl
+        description     "Ethernet driver for AMD Lance PCI controller (vmWare)."
+}
+
+package CYGPKG_DEVS_ETH_DAVICOM_DM9000 {
+	alias 		{ "Davicom DM9000 ethernet driver" dm9000_eth_driver }
+	hardware
+	directory	devs/eth/davicom/dm9000
+	script		davicom_dm9000_eth_drivers.cdl
+        description     "Ethernet driver for Davicom DM9000 controller."
+}
+
+package CYGPKG_DEVS_ETH_MIPS_MIPS32_MALTA {
+	alias 		{ "MIPS Malta board ethernet driver" malta_eth_driver }
+	hardware
+	directory	devs/eth/mips/malta
+	script		mips_mips32_malta_eth_drivers.cdl
+        description     "Ethernet driver for MIPS Malta board."
+}
+
+package CYGPKG_DEVS_ETH_MN10300_ASB2305 {
+	alias 		{ "MN10300 ASB2305 board ethernet driver" asb2305_eth_driver }
+	hardware
+	directory	devs/eth/mn10300/asb2305
+	script		mn10300_asb2305_eth.cdl
+        description     "Ethernet driver for MN10300 ASB2305 board."
+}
+
+package CYGPKG_DEVS_ETH_VIA_RHINE {
+	alias 		{ "VIA Rhine ethernet driver" rhine_eth_driver }
+	hardware
+	directory	devs/eth/via/rhine
+	script		via_rhine_eth_drivers.cdl
+        description     "Ethernet driver for VIA Rhine controller."
+}
+
+package CYGPKG_DEVS_ETH_SH_HS7729PCI {
+	alias 		{ "HS7729PCI ethernet driver" hs7729pci_eth_driver }
+	hardware
+	directory	devs/eth/sh/hs7729pci
+	script		sh_hs7729pci_eth_drivers.cdl
+        description     "Ethernet driver for HS7729PCI development boards."
+}
+
+package CYGPKG_DEVS_ETH_SH_SE77X9 {
+	alias 		{ "SE77X9 ethernet driver" se77x9_eth_driver }
+	hardware
+	directory	devs/eth/sh/se77x9
+	script		sh_se77x9_eth_drivers.cdl
+        description     "Ethernet driver for SE77x9 development boards."
+}
+
+package CYGPKG_DEVS_ETH_SH_SE7751 {
+	alias 		{ "SE7751 ethernet driver" se7751_eth_driver }
+	hardware
+	directory	devs/eth/sh/se7751
+	script		sh_se7751_eth_drivers.cdl
+        description     "Ethernet driver for SE7751 board."
+}
+
+package CYGPKG_DEVS_ETH_SH_ETHERC {
+	alias 		{ "SH2 etherc driver" etherc_eth_driver }
+	hardware
+	directory	devs/eth/sh/etherc
+	script		sh_etherc_eth_drivers.cdl
+        description     "Ethernet driver for SH2 etherc controller."
+}
+
+package CYGPKG_DEVS_ETH_SH_MICRODEV {
+      alias           { "SH4-202 MicroDev onboard ethernet support" devs_eth_sh_md }
+      hardware
+      directory       devs/eth/sh/sh4_202_md
+      script          sh4_202_md_eth_drivers.cdl
+      description "This package contains hardware support for onboard SMC91C111
+                   ethernet device on the MicroDev board."
+}
+
+package CYGPKG_DEVS_ETH_ARM_EBSA285 {
+	alias 		{ "Intel EBSA285 with PRO/100+ ethernet driver"
+			   devs_eth_arm_ebsa285 ebsa285_eth_driver }
+	hardware
+	directory	devs/eth/arm/ebsa285
+	script		ebsa285_eth_drivers.cdl
+        description     "Ethernet driver for Intel EBSA285 with PRO/100+ boards."
+}
+
+package CYGPKG_DEVS_ETH_ARM_FLEXANET {
+      alias           { "SA11x0/Flexanet onboard ethernet support" devs_eth_arm_flexanet }
+      hardware
+      directory       devs/eth/arm/flexanet
+      script          flexanet_eth_drivers.cdl
+      description "This package contains hardware support for onboard SMC91C96
+                   ethernet device on the Flexanet board."
+}
+
+package CYGPKG_DEVS_ETH_ARM_INNOVATOR {
+      alias           { "OMAP Innovator onboard ethernet support" devs_eth_arm_innovator }
+      hardware
+      directory       devs/eth/arm/innovator
+      script          innovator_eth_drivers.cdl
+      description "This package contains hardware support for onboard SMC91C96
+                   ethernet device on the Innovator board."
+}
+
+package CYGPKG_DEVS_ETH_ARM_INTEGRATOR {
+        alias           { "ARM INTEGRATOR with Intel PRO/100+ ethernet driver"
+                           devs_eth_arm_integrator integrator_eth_driver }
+        hardware
+        directory       devs/eth/arm/integrator
+        script          integrator_eth_drivers.cdl
+        description     "Ethernet driver for Intel PRO/100+ boards on ARM INTEGRATOR."
+}
+
+package CYGPKG_DEVS_ETH_POWERPC_QUICC {
+	alias 		{ "QUICC ethernet driver" quicc_eth_driver }
+	hardware
+	directory	devs/eth/powerpc/quicc
+	script		quicc_eth_drivers.cdl
+        description     "Ethernet driver for PowerPC QUICC (MPC8xx) based boards."
+}
+
+package CYGPKG_DEVS_ETH_POWERPC_MBX {
+	alias 		{ "MBX ethernet driver specifics" mbx_eth_driver }
+	hardware
+	directory	devs/eth/powerpc/mbx
+	script		mbx_eth_drivers.cdl
+        description     "Ethernet driver specifics for Motorola MBX PowerPC (MPC8xx) based boards."
+}
+
+package CYGPKG_DEVS_ETH_POWERPC_QUICC2 {
+	alias 		{ "QUICC2 ethernet driver" quicc2_eth_driver }
+	hardware
+	directory	devs/eth/powerpc/quicc2
+	script		quicc2_eth_drivers.cdl
+        description     "Fast ethernet driver for PowerPC QUICC2 (MPC8260) based boards."
+}
+
+package CYGPKG_DEVS_ETH_POWERPC_FEC {
+	alias 		{ "FEC ethernet driver" fec_eth_driver }
+	hardware
+	directory	devs/eth/powerpc/fec
+	script		fec_eth_drivers.cdl
+        description     "Ethernet driver for PowerPC FEC (MPC8xxT) based boards."
+}
+
+package CYGPKG_DEVS_ETH_POWERPC_FCC {
+	alias 		{ "FCC ethernet driver" fcc_eth_driver }
+	hardware
+	directory	devs/eth/powerpc/fcc
+	script		fcc_eth_drivers.cdl
+        description     "Fast ethernet driver for PowerPC MPCxxx based boards."
+}
+
+package CYGPKG_DEVS_ETH_POWERPC_PPC405 {
+	alias 		{ "PPC405 ethernet driver" ppc405_eth_driver }
+	hardware
+	directory	devs/eth/powerpc/ppc405
+	script		ppc405_eth_drivers.cdl
+        description     "Ethernet driver for PowerPC 405GP based boards."
+}
+
+package CYGPKG_DEVS_ETH_POWERPC_VIPER {
+	alias 		{ "A&M Viper ethernet driver" viper_eth_driver }
+	hardware
+	directory	devs/eth/powerpc/viper
+	script		viper_eth_drivers.cdl
+        description     "Ethernet driver specifics for A&M Viper (MPC8xxT) based boards."
+}
+
+package CYGPKG_DEVS_ETH_POWERPC_EC555 {
+	alias 		{ "Crystal LAN ethernet driver for ec555 boards" ec555_eth_driver }
+	hardware
+	directory	devs/eth/powerpc/ec555
+	script		ec555_eth_drivers.cdl
+    description     "Ethernet driver for Crystal LAN on ec555 board."
+}
+
+package CYGPKG_DEVS_ETH_INTEL_I82559 {
+	alias 		{ "Intel 82559 ethernet driver"
+			   devs_eth_intel_i82559 i82559_eth_driver }
+	hardware
+	directory	devs/eth/intel/i82559
+	script		intel_i82559_eth_drivers.cdl
+        description     "Ethernet driver for Intel 82559 NIC."
+}
+
+package CYGPKG_DEVS_ETH_INTEL_I82544 {
+	alias 		{ "Intel 82544 ethernet driver"
+			   devs_eth_intel_i82544 i82544_eth_driver }
+	hardware
+	directory	devs/eth/intel/i82544
+	script		intel_i82544_eth_drivers.cdl
+        description     "Ethernet driver for Intel 82544 NIC."
+}
+
+package CYGPKG_DEVS_ETH_INTEL_I21143 {
+	alias 		{ "Intel 21143 ethernet driver"
+			   devs_eth_intel_i21143 i21143_eth_driver }
+	hardware
+	directory	devs/eth/intel/i21143
+	script		intel_i21143_eth_drivers.cdl
+        description     "Ethernet driver for Intel \[DEC\] 21143 NIC."
+}
+
+package CYGPKG_DEVS_ETH_MIPS_VRC4375 {
+	alias 		{ "NEC MIPS VRC4375 ethernet driver"
+			   devs_eth_mips_vrc4375 vrc4375_eth_driver }
+	hardware
+	directory	devs/eth/mips/vrc4375
+	script		vrc4375_eth_drivers.cdl
+        description     "Ethernet driver for NEC MIPS VRC4375 'Blue Nile'
+			board with Intel \[ex Digital Equipment\]
+                        i21143 ethernet interface."
+}
+
+package CYGPKG_DEVS_ETH_MIPS_RM7000_OCELOT {
+	alias 		{ "Ocelot ethernet drivers"
+			   devs_eth_mips_rm7000_ocelot ocelot_eth_driver }
+	hardware
+	directory	devs/eth/mips/ocelot
+	script		mips_rm7000_ocelot_eth_drivers.cdl
+        description     "Ethernet driver for PMC-Sierra Ocelot board."
+}
+
+package CYGPKG_DEVS_ETH_ARM_IQ80321 {
+	alias 		{ "Intel IQ80321 with onboard 82544 ethernet driver"
+			   devs_eth_arm_iq80321 iq80321_eth_driver }
+	hardware
+	directory	devs/eth/arm/iq80321
+	script		iq80321_eth_drivers.cdl
+        description     "Ethernet driver for Intel IQ80321 with onboard 82544 NIC."
+}
+
+package CYGPKG_DEVS_ETH_ARM_XSCALE_IQ80310 {
+	alias 		{ "Intel IQ80310 with onboard 82559 ethernet driver"
+			   devs_eth_arm_iq80310 iq80310_eth_driver }
+	hardware
+	directory	devs/eth/arm/iq80310
+	script		iq80310_eth_drivers.cdl
+        description     "Ethernet driver for Intel IQ80310 with onboard 82559 NIC."
+}
+
+package CYGPKG_DEVS_ETH_ARM_IXDP425_I82559 {
+	alias 		{ "IXDP425 (PCI) / Intel 82559 ethernet driver"
+			   devs_eth_arm_ixdp425_i82559 }
+	hardware
+	directory	devs/eth/arm/ixdp425/i82559
+	script		ixdp425_i82559_eth_driver.cdl
+        description     "Ethernet driver for IXDP425 with Intel 82559 PCI NIC."
+}
+
+package CYGPKG_DEVS_ETH_ARM_XSCALE_XSENGINE {
+       alias           { "XSEngine SMC91C111 ethernet driver" devs_eth_arm_xsengine }
+       hardware
+       directory       devs/eth/arm/xsengine
+       script          xsengine_eth_drivers.cdl
+       description     "Ethernet driver for XSEngine board."
+}
+
+package CYGPKG_DEVS_ETH_ARM_GRG_I82559 {
+	alias 		{ "GRG / Intel 82559 ethernet driver"
+			   devs_eth_arm_grg_i82559 }
+	hardware
+	directory	devs/eth/arm/grg/i82559
+	script		grg_i82559_eth_driver.cdl
+        description     "Ethernet driver for GRG with Intel 82559 PCI NIC."
+}
+
+package CYGPKG_DEVS_ETH_I386_PC_I82559 {
+	alias 		{ "Standard PC with EtherPro 10/100 ethernet device"
+			   devs_eth_i386_pc_i82559 pc_etherpro }
+	hardware
+	directory	devs/eth/i386/pc/i82559
+	script		i386_pc_i82559_eth_drivers.cdl
+        description     "Ethernet driver for standard PC with Intel 82559 NIC. This is
+			 essentially support for a EtherPro 10/100 PCI card."
+}
+
+package CYGPKG_DEVS_ETH_I386_PC_I82544 {
+	alias 		{ "Standard PC with Intel Gigabit ethernet device"
+			   devs_eth_i386_pc_i82544 pc_ether_giga }
+	hardware
+	directory	devs/eth/i386/pc/i82544
+	script		i386_pc_i82544_eth_drivers.cdl
+        description     "Ethernet driver for standard PC with Intel 82544 Gigabit NIC."
+}
+
+package CYGPKG_DEVS_ETH_I386_PC_LANCEPCI {
+	alias 		{ "Standard PC with AMD Lance PCI device"
+			   devs_eth_i386_pc_lancepci pc_ether_lancepci }
+	hardware
+	directory	devs/eth/i386/pc/lancepci
+	script		i386_pc_lancepci_eth_drivers.cdl
+        description     "Ethernet driver for standard PC with AMD Lance NIC (vmWare)."
+}
+
+package CYGPKG_DEVS_ETH_MIPS_ATLAS {
+	alias 		{ "MIPS Atlas with onboard SAA9730 ethernet driver"
+			   devs_eth_mips_atlas atlas_eth_driver }
+	hardware
+	directory	devs/eth/mips/atlas
+	script		atlas_eth_drivers.cdl
+        description     "Ethernet driver for MIPS Atlas with onboard SAA9730 NIC."
+}
+
+package CYGPKG_DEVS_ETH_NS_DP83902A {
+	alias 		{ "NS DP83902A ethernet driver" dp83902a_eth_driver }
+	hardware
+	directory	devs/eth/ns/dp83902a
+	script		ns_dp83902a_eth_drivers.cdl
+        description     "Ethernet driver for NS DP83902A controller."
+}
+
+package CYGPKG_DEVS_ETH_NS_DP83816 {
+	alias 		{ "NS DP83816 ethernet driver" dp83816_eth_driver }
+	hardware
+	directory	devs/eth/ns/dp83816
+	script		ns_dp83816_eth_drivers.cdl
+        description     "Ethernet driver for NS DP83816 controller."
+}
+
+package CYGPKG_DEVS_ETH_CL_CS8900A {
+	alias 		{ "Cirrus Logic CS8900A ethernet driver" cs8900a_eth_driver }
+	hardware
+	directory	devs/eth/cl/cs8900a
+	script		cl_cs8900a_eth_drivers.cdl
+        description     "Ethernet driver for Cirrus Logic CS8900A controller."
+}
+
+package CYGPKG_DEVS_ETH_MIPS_UPD985XX {
+	alias		{ "NEC uPD985xx ethernet driver" uPD985xx_eth_driver }
+	hardware
+	directory	devs/eth/mips/upd985xx
+	script		upd985xx_eth_drivers.cdl
+	description     "NEC uPD985xx ethernet driver"
+}
+
+package CYGPKG_DEVS_ETH_MIPS_REFIDT334 {
+        alias           { "MIPS IDT 79RC32334 reference platform ethernet driver"
+                           devs_eth_refidt334 refidt334_eth_driver }
+        hardware
+        directory       devs/eth/mips/idt79s334a
+        script          refidt334_eth_drivers.cdl
+        description     "Ethernet driver for MIPS IDT 79RC32334 reference platform."
+}
+
+# Not sure whether this should be "hardware"; if so, it should be mentioned
+# in all targets that can use it.
+package CYGPKG_DEVS_ETH_CF {
+	alias 		{ "PCMCIA (Compact Flash) ethernet drivers" cf_eth_drivers }
+	directory	devs/eth/cf
+	script		cf_eth_drivers.cdl
+        hardware
+        description     "Ethernet drivers for PCMCIA (Compact Flash) cardss."
+}
+
+package CYGPKG_DEVS_ETH_H8300_AKI3068NET {
+	alias 		{ "Akizuki H8/3068 Board ethernet driver" aki3068net_eth_drivers }
+	directory	devs/eth/h8300/aki3068net
+	script		h8300_aki3068net_eth_drivers.cdl
+        hardware
+        description     "Ethernet drivers for Akizuki H8/3068 Network
+   	                 micom board."
+}
+
+package CYGPKG_DEVS_ETH_H8300_H8MAX {
+	alias 		{ "H8MAX Board ethernet driver" h8max_eth_drivers }
+	directory	devs/eth/h8300/h8max
+	script		h8300_h8max_eth_drivers.cdl
+        hardware
+        description     "Ethernet drivers for H8MAX board."
+}
+
+package CYGPKG_DEVS_ETH_H8300_EDOSK2674 {
+	alias 		{ "EDOSK-2674 Board ethernet driver" edosk2674_eth_drivers }
+	directory	devs/eth/h8300/edosk2674
+	script		h8300_edosk2674_eth_drivers.cdl
+        hardware
+        description     "Ethernet drivers for EDOSK-2674 board."
+}
+
+package CYGPKG_DEVS_ETH_MCF5272 {
+        alias           { "MCF5272 Fast Ethernet Controller driver" mcf5272_eth_driver}
+        hardware
+        directory       devs/eth/mcf52xx/mcf5272
+        script          mcf5272_eth_driver.cdl
+        description     "Ethernet driver for the MCF5272."
+}
+
+
+package CYGPKG_DEVS_ETH_ECOSYNTH {
+        alias           { "Synthetic target ethernet driver" ecosyntheth ecosynth_eth_driver }
+        directory       devs/eth/synth/ecosynth
+        script          syntheth.cdl
+        hardware
+        description     "Ethernet driver for the synthetic target"
+}
+
+package CYGPKG_DEVS_ETH_ENC424J600 {
+	alias 		{ "Microchip ENC424J600 / ENC624J600 ethernet controller driver" enc424j600_eth_driver }
+	directory	devs/eth/microchip/enc424j600
+	script		enc424j600_eth_drivers.cdl
+        description     "Driver for Microchip ENC424J600 and ENC624J600 Ethernet controllers."
+}
+
+package CYGPKG_IO_PCI	{
+	alias		{ "PCI configuration library" io_pci }
+	directory	io/pci
+	script		io_pci.cdl
+	hardware
+        description "
+           This package contains the PCI configuration library."
+}
+
+package CYGPKG_IO_WALLCLOCK {
+        alias           { "Wallclock device framework" wallclock io_wallclock devices_wallclock device_wallclock }
+	directory	io/wallclock
+	script          wallclock.cdl
+        description "
+           This package provides a wallclock device framework. It is
+           also necessary to select an actual driver implementation."
+}
+
+package CYGPKG_DEVICES_WALLCLOCK_SH3 {
+	alias		{ "Wallclock driver for SH3 RTC module" devices_wallclock_sh3 device_wallclock_sh3 }
+	directory	devs/wallclock/sh/sh3
+	script          wallclock_sh3.cdl
+	hardware
+        description "
+           This package provides a wallclock driver implementation for the
+           Hitachi SH3 CPU's RTC module."
+}
+
+package CYGPKG_DEVICES_WALLCLOCK_MPC5xx {
+	alias		{ "Wallclock driver for mpc5xx RTC module" devices_wallclock_mpc5xx device_wallclock_mpc5xx }
+	directory	devs/wallclock/powerpc/mpc5xx
+	script          wallclock_mpc5xx.cdl
+	hardware
+        description "
+           This package provides a wallclock driver implementation for the
+           Motorola mpc5xx CPU's RTC module."
+}
+
+package CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1307 {
+	alias		{ "Wallclock driver for Dallas 1307" devices_wallclock_ds1307 device_wallclock_ds1307 }
+	directory	devs/wallclock/dallas/ds1307
+	script          wallclock_ds1307.cdl
+	hardware
+        description "
+           This package provides a driver implementation for 
+           the Dallas 1307 wallclock."
+}
+
+package CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1742 {
+	alias		{ "Wallclock driver for Dallas 1742" devices_wallclock_ds1742 device_wallclock_ds1742 }
+	directory	devs/wallclock/dallas/ds1742
+	script          wallclock_ds1742.cdl
+	hardware
+        description "
+           This package provides a driver implementation for 
+           the Dallas 1742 wallclock."
+}
+
+package CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS12887 {
+	alias		{ "Wallclock driver for Dallas 12887" devices_wallclock_ds12887 device_wallclock_ds12887 }
+	directory	devs/wallclock/dallas/ds12887
+	script          wallclock_ds12887.cdl
+	hardware
+        description "
+           This package provides a driver implementation for 
+           the Dallas 12887 wallclock."
+}
+
+package CYGPKG_DEVICES_WALLCLOCK_MIPS_REF4955 {
+	alias		{ "Wallclock driver for REF4955 board" devices_wallclock_ref4955 device_wallclock_ref4955 }
+	directory	devs/wallclock/mips/ref4955
+	script          wallclock_ref4955.cdl
+	hardware
+        description "
+           This package provides a wallclock driver implementation for the
+           Toshiba REF4955 board."
+}
+
+package CYGPKG_DEVICES_WALLCLOCK_I386_PC {
+         alias          { "Standard PC RTC device" devs_wallclock_i386_pc_ds12887 pc_rtc }
+         hardware
+         directory      devs/wallclock/i386/pc
+         script         i386_pc_wallclock_drivers.cdl
+         description    "
+            RTC driver for standard PC. This is essentially support for a
+            Dallas DS12887 RTC."
+}
+
+package CYGPKG_DEVICES_WALLCLOCK_SH_HS7729PCI {
+	alias		{ "Wallclock driver for HS7729PCI board" devices_wallclock_hs7729pci device_wallclock_hs7729pci }
+	directory	devs/wallclock/sh/hs7729pci
+	script          wallclock_hs7729pci.cdl
+	hardware
+        description "
+           This package provides a wallclock driver implementation for the
+           Hitachi HS7729PCI board."
+}
+
+package CYGPKG_DEVS_WALLCLOCK_SYNTH {
+        alias           { "Wallclock driver for synthetic target" devs_wallclock_synth wallclock_synth }
+        directory       devs/wallclock/synth
+        script          wallclock_synth.cdl
+        hardware
+        description "
+           This package provides a wallclock driver implementation for the
+           synthetic target."
+}
+
+package CYGPKG_DEVICES_WALLCLOCK_ARM_AIM711 {
+       alias           { "Wallclock driver for AIM 711" devs_wallclock_arm_aim711 aim711_rt
+c }
+       directory       devs/wallclock/arm/aim711
+       script          aim711_wallclock_drivers.cdl
+       hardware
+        description "
+           This package provides a wallclock driver implementation for the
+           ARM Industrial Module AIM 711."
+}
+
+package CYGPKG_DEVICES_WALLCLOCK_ARM_LPC2XXX {
+        alias           { "Wallclock driver for LPC2xxx/LPC17xx RTC module" }
+        directory       devs/wallclock/arm/lpc2xxx
+        script          lpc2xxx_wallclock.cdl
+        hardware
+        description "
+           This package provides a wallclock driver implementation for the
+           LPC2xxx/LPC17xx RTC module."
+}
+
+package CYGPKG_DEVICES_WALLCLOCK_KINETIS_RTC {
+        alias           { "Wallclock driver for Kinetis RTC module" }
+        directory       devs/wallclock/freescale/kinetis
+        script          wallclock_kinetis_rtc.cdl
+        hardware
+        description "
+           This package provides a wallclock driver implementation for the
+           Kinetis RTC module."
+}
+
+package CYGPKG_DEVICES_WATCHDOG_ARM_AEB {
+	alias		{ "Watchdog driver for ARM/AEB board" devices_watchdog_aeb device_watchdog_aeb }
+	directory	devs/watchdog/arm/aeb
+	script          watchdog_aeb.cdl
+	hardware
+        description "
+           This package provides a watchdog driver implementation for the
+           ARM/AEB board."
+}
+
+package CYGPKG_DEVICES_WATCHDOG_ARM_AT91 {
+	alias		{ "Watchdog driver for ARM AT91 CPU" devices_watchdog_at91 device_watchdog_at91 }
+	directory	devs/watchdog/arm/at91
+	script          watchdog_at91.cdl
+	hardware
+        description "
+           This package provides a watchdog driver implementation for the
+           ARM AT91 CPU."
+}
+
+package CYGPKG_DEVICES_WATCHDOG_ARM_AT91WDTC {
+	alias		{ "Watchdog driver for ARM AT91 WDTC" devices_watchdog_at91wdtc device_watchdog_at91wdtc }
+	directory	devs/watchdog/arm/at91wdtc
+	script          watchdog_at91wdtc.cdl
+	hardware
+        description "
+           This package provides a watchdog driver implementation for the
+           ARM AT91 CPUs which have the Watchdog Timer Controller."
+}
+
+package CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX {
+        alias           { "Watchdog driver for ARM LPC2XXX CPU" devices_watchdog_lpc2xxx device_watchdog_lpc2xxx }
+       directory       devs/watchdog/arm/lpc2xxx
+       script          watchdog_lpc2xxx.cdl
+       hardware
+       description "
+           This package provides a watchdog driver implementation for the
+           ARM LPC2XXX CPU."
+}
+
+package CYGPKG_DEVICES_WATCHDOG_ARM_EBSA285 {
+	alias		{ "Watchdog driver for ARM/EBSA285 board" devices_watchdog_ebsa285 device_watchdog_ebsa285 }
+	directory	devs/watchdog/arm/ebsa285
+	script          watchdog_ebsa285.cdl
+	hardware
+        description "
+           This package provides a watchdog driver implementation for the
+           ARM/EBSA285 board."
+}
+
+package CYGPKG_DEVICES_WATCHDOG_ARM_SA11X0 {
+	alias		{ "Watchdog driver for StrongARM SA11x0 devices" devices_watchdog_sa11x0 device_watchdog_sa11x0 }
+	directory	devs/watchdog/arm/sa11x0
+	script          watchdog_sa11x0.cdl
+	hardware
+        description "
+           This package provides a watchdog driver implementation for
+           Intel StrongARM SA11x0 integrated devices."
+}
+
+package CYGPKG_DEVICES_WATCHDOG_MN10300_MN10300 {
+	alias		{ "Watchdog driver for MN10300 chip" devices_watchdog_mn10300 device_watchdog_mn10300 }
+	directory	devs/watchdog/mn10300/mn10300
+	script          watchdog_mn10300.cdl
+	hardware
+        description "
+           This package provides a watchdog driver implementation for the
+           MN10300 chip."
+}
+
+package CYGPKG_DEVICES_WATCHDOG_MPC5xx {
+	alias		{ "Watchdog driver for mpc5xx processor" devices_watchdog_mpc5xx device_watchdog_mpc5xx }
+	directory	devs/watchdog/powerpc/mpc5xx
+	script          watchdog_mpc5xx.cdl
+	hardware
+        description "
+           This package provides a watchdog driver implementation for the
+           mpc5xx processor family."
+}
+
+package CYGPKG_DEVICES_WATCHDOG_SH_SH3 {
+	alias		{ "Watchdog driver for the Hitachi SH3 chip" devices_watchdog_sh3 device_watchdog_sh3 }
+	directory	devs/watchdog/sh/sh3
+	script          watchdog_sh3.cdl
+	hardware
+        description "
+           This package provides a watchdog driver implementation for the
+           Hitachi SH3 chip."
+}
+
+package CYGPKG_DEVICES_WATCHDOG_H8300_H8300H {
+	alias		{ "Watchdog driver for the Hitachi H8/300H chip" devices_watchdog_h8300h device_watchdog_h8300h }
+	directory	devs/watchdog/h8300/h8300h
+	script          watchdog_h8300h.cdl
+	hardware
+        description "
+           This package provides a watchdog driver implementation for the
+           Hitachi H8/300H chip."
+}
+
+package CYGPKG_DEVS_WATCHDOG_SYNTH {
+	alias		{ "Watchdog driver for the synthetic target" devices_watchdog_synth device_watchdog_synth }
+	directory	devs/watchdog/synth
+	script          synth_watchdog.cdl
+	hardware
+        description "
+           This package provides a watchdog driver for the eCos
+           synthetic target."
+}
+
+package CYGPKG_IO_WATCHDOG {
+	alias		{ "Watchdog IO device" watchdog io_watchdog }
+	directory	io/watchdog
+        script          watchdog.cdl
+        description "
+           This package provides a watchdog device."
+}
+
+package CYGPKG_DEVS_SPI_ARM_AT91 {
+    alias         { "Atmel AT91 SPI device driver" devs_spi_arm_at91 spi_at91_driver }
+    hardware
+    directory     devs/spi/arm/at91
+    script        spi_at91.cdl
+    description   "Atmel AT91 on-chip spi device driver."
+}
+
+package CYGPKG_DEVS_SPI_ARM_EB55 {
+    alias         { "Atmel AT91EB55 SPI devices" devs_spi_arm_eb55 spi_eb55_devices }
+    hardware
+    directory     devs/spi/arm/eb55
+    script        spi_eb55.cdl
+    description   "Atmel AT91EB55 spi devices."
+}
+
+package CYGPKG_DEVS_SPI_ARM_LPC2XXX {
+    alias         { "LPC2xxx SPI driver" }
+    hardware
+    directory     devs/spi/arm/lpc2xxx
+    script        spi_lpc2xxx.cdl
+    description "This package provides a driver for the SPI unit of the LPC2xxx
+                 controller family."
+}
+
+package CYGPKG_DEVS_SPI_FREESCALE_DSPI {
+    alias         { "Freescale DSPI driver" }
+    hardware
+    directory     devs/spi/freescale/dspi
+    script        spi_freescale_dspi.cdl
+    description   "
+        This package provides a driver for the Freescale DSPI interfaces."
+}
+
+package CYGPKG_DEVS_SPI_CORTEXM_A2FXXX {
+    alias         { "Cortex-M3/Actel Smartfusion (A2Fxxx) SPI driver" }
+    hardware
+    directory     devs/spi/cortexm/a2fxxx
+    script        spi_a2fxxx.cdl
+    description "This package provides a driver for the SPI peripheral of Actel Smartfusion (A2Fxxx)
+                 controller family."
+}
+
+package CYGPKG_IO_SPI {
+        alias      { "Generic SPI support" spi io_spi spi_io }
+        directory  io/spi
+        script     spi.cdl
+        hardware
+        description "
+          The generic SPI package provides an API for accessing devices
+          attached to an SPI bus. It also provides support for writing
+          bus drivers and for defining SPI device structures."
+}
+
+package CYGPKG_IO_I2C {
+        alias           { "Generic I2C support" i2c io_i2c i2c_io }
+        directory       io/i2c
+        script          i2c.cdl
+        hardware
+        description "
+            The generic I2C package provides an API for accessing devices
+            attached to an I2C bus. It specifies how I2C bus drivers should
+            be written and how I2C devices should be defined. There is also
+            support for bit-banged I2C buses."
+}
+
+package CYGPKG_DEVS_I2C_MCF52xx {
+	alias		{ "MCF52xx I2C driver" devs_i2c_mcf52xx mcf52xx_i2c_driver }
+	hardware
+	directory	devs/i2c/m68k/mcf52xx
+	script		i2c_mcf52xx.cdl
+	description "
+            This packages provides an I2C driver for the on-chip
+	        device provided by the MCF52xx coldfire processor family."
+}
+
+package CYGPKG_DEVS_I2C_ARM_LPC2XXX {
+    alias           { "LPC2xxx I2C driver" }
+    hardware
+    directory       devs/i2c/arm/lpc2xxx
+    script          i2c_lpc2xxx.cdl
+    description "This package provides a driver for the I2C unit of the LPC2xxx
+                 controller family."
+}
+
+package CYGPKG_DEVS_I2C_CORTEXM_LM3S {
+    alias        { "Stellaris Cortex-M3 I2C driver" lm3s_i2c lm3s_i2c_driver i2c_lm3s}
+    hardware
+    directory    devs/i2c/cortexm/lm3s
+    script       i2c_lm3s.cdl
+    description  "
+        This package provides a driver for the I2C unit of the Stellaris
+        Cortex-M3 controller family."
+}
+
+package CYGPKG_DEVS_I2C_CORTEXM_A2FXXX {
+    alias           { "Cortex-M3/Actel Smartfusion (A2Fxxx) I2C driver" a2fxxx_i2c a2fxxx_i2c_driver i2c_a2fxxx}
+    hardware
+    directory       devs/i2c/cortexm/a2fxxx
+    script          i2c_a2fxxx.cdl
+    description "This package provides a driver for the I2C peripheral of the Actel Smartfusion (A2Fxxx)
+                 controller family."
+}
+
+package CYGPKG_DEVS_I2C_FREESCALE_I2C {
+    alias        { "Freescale I2C driver" freescale_i2c i2c_freescale kinetis_i2c i2c_kinetis}
+    hardware
+    directory    devs/i2c/freescale/i2c
+    script       i2c_freescale.cdl
+    description  "
+        This package provides a driver for the I2C unit of the Freescale chips, such as the Kinetis MCU family."
+}
+
+
+package CYGPKG_DEVS_ADC_ARM_LPC24XX {
+    alias           { "LPC24xx ADC driver" }
+    hardware
+    directory       devs/adc/arm/lpc24xx
+    script          adc_lpc24xx.cdl
+    description "
+            This packages provides an ADC driver for the on-chip
+            ADC provided by the LPC24xx processor family."
+}
+
+package CYGPKG_DEVS_ADC_ARM_AT91 {
+    alias           { "AT91 ADC driver" }
+    hardware
+    directory       devs/adc/arm/at91
+    script          adc_at91.cdl
+    description "
+            This packages provides an ADC driver for the on-chip
+            ADC provided by the Atmel AT91 processor family."
+}
+
+package CYGPKG_DEVS_ADC_CORTEXM_LM3S {
+    alias         { "Stellaris Cortex M3 ADC driver" lm3s_adc }
+    hardware
+    directory     devs/adc/cortexm/lm3s
+    script        adc_lm3s.cdl
+    description   "
+        This packages provides an ADC driver for the on-chip ADC provided
+        by the Stellaris Cortex M3 controller family."
+}
+
+package CYGPKG_DEVS_ADC_SYNTH {
+    alias         { "Synthethic ADC driver" adc_synth }
+    hardware
+    directory     devs/adc/synth
+    script        adc_synth.cdl
+    description "
+            This package provides an ADC driver for the Synthethic target."
+}
+
+package CYGPKG_IO_ADC {
+	alias 		{ "Generic ADC support" adc io_adc }
+	directory	io/adc
+	script		io_adc.cdl
+        description "
+           This package contains drivers for basic I/O services on
+           adc devices."
+}
+
+package CYGPKG_KERNEL {
+	alias		{ "eCos kernel" kernel }
+	directory	kernel
+	script		kernel.cdl
+     	description "
+This package contains the core functionality of the eCos kernel. It
+relies on functionality provided by various HAL packages and by the
+eCos infrastructure. In turn the eCos kernel provides support for
+other packages such as the device drivers and the uITRON compatibility
+layer."
+}
+
+package CYGPKG_MEMALLOC {
+        alias           { "Dynamic memory allocation" memalloc malloc }
+        directory       services/memalloc/common
+        script          memalloc.cdl
+        description "
+This package provides memory allocator infrastructure required for
+dynamic memory allocators, including the ISO standard malloc
+interface. It also contains some sample implementations."
+}
+
+package CYGPKG_LOADER {
+        alias           { "Dynamic loader" loader dload }
+        directory       services/loader
+        script          loader.cdl
+        description "
+This package provides support for the dynamic executable and
+library loader."
+}
+
+package CYGPKG_OBJLOADER {
+        alias           { "Object file loader" objloader }
+        directory       services/objloader
+        script          objloader.cdl
+        description "
+This package provides support for the object file loader and relocator."
+}
+
+package CYGPKG_COMPRESS_ZLIB {
+        alias           { "Zlib compress/decompress" zlib_compress compress_zlib zlib }
+        directory       services/compress/zlib
+        script          compress_zlib.cdl
+        description "
+This package provides zlib compression and decompression support."
+}
+
+package CYGPKG_POWER {
+	alias 		{ "Power Management support" power }
+	directory	services/power/common
+	script		power.cdl
+	description "
+This package provides some generic support for power management."
+}
+
+package CYGPKG_CRC {
+        alias           { "CRC support" crc }
+        directory       services/crc
+        script          crc.cdl
+        description "
+This package provides support for CRC functions, including the 
+POSIX 1003 defined CRC algorithm."
+}  
+
+package CYGPKG_CPULOAD {
+        alias           { "cpuload support" cpuload }
+        directory       services/cpuload
+        script          cpuload.cdl
+        description "
+This package measures the CPU load over the last 100ms, 1second 
+and 10 second. All loads are returned as a percentage, ie 0-100.
+This is only a rough measure."
+}     
+
+package CYGPKG_PROFILE_GPROF {
+        alias           { "Application profile support" profile_gprof gprof_profile }
+        directory       services/profile/gprof
+        script          profile_gprof.cdl
+        description "
+This package instruments applications to collect profiling data,
+using a methodology compatible with the gprof utility."
+}     
+                  
+package CYGPKG_EZXML {
+        alias           { "ezXML" XML ezxml }
+        directory       services/ezxml
+        script          ezxml.cdl
+        description     "ezXML, Simple XML Parser"
+}
+                 
+package CYGPKG_PDCURSES {
+	alias 		{ "PDCurses" pdcurses }
+	directory	services/curses/pdcurses
+	script		pdcurses.cdl
+        description     "Public Domain Curses."
+}
+
+package CYGPKG_UITRON {
+	alias		{ "uITRON compatibility" uitron }
+	directory	compat/uitron
+	script		uitron.cdl
+	description "
+eCos supports a uITRON Compatibility Layer, providing full Level S
+(Standard) compliance with Version 3.02 of the uITRON Standard, plus
+many Level E (Extended) features. uITRON is the premier Japanese
+embedded RTOS standard."
+}
+
+package CYGPKG_ISOINFRA {
+        alias           { "ISO C and POSIX infrastructure" isoinfra }
+        directory       isoinfra
+        script          isoinfra.cdl
+        description "
+eCos supports implementations of ISO C libraries and POSIX implementations.
+This package provides infrastructure used by all such implementations."
+}
+
+package CYGPKG_POSIX {
+	alias		{ "POSIX compatibility" posix }
+	directory	compat/posix
+	script		posix.cdl
+	description "
+This package enables compatibility with the ISO/IEEE 1003.1 POSIX
+standard.  This allows the user application to use a well known
+standard API, and starts a thread to invoke the user function
+main()"
+}
+
+package CYGPKG_LIBC {
+	alias		{ "C library" libc clib clibrary }
+	directory	language/c/libc/common
+	script		libc.cdl
+        description  "
+The packages under this package enable compatibility with the ISO C
+standard - ISO/IEC 9899:1990. This allows the user application to use
+well known standard C library functions, and in eCos starts a thread
+to invoke the user function main(). This package is a top-level placeholder
+to contain the implementations."
+}
+
+package CYGPKG_LIBC_I18N {
+	alias		{ "ISO C library internationalization" libc_i18n }
+	directory	language/c/libc/i18n
+	script		i18n.cdl
+        description  "
+This package provides internationalization functions specified by the
+ISO C standard - ISO/IEC 9899:1990."
+}
+
+package CYGPKG_LIBC_SETJMP {
+	alias		{ "ISO C library non-local jumps" libc_setjmp }
+	directory	language/c/libc/setjmp
+	script		setjmp.cdl
+        description  "
+This package provides non-local jump functionality specified by the
+ISO C standard - ISO/IEC 9899:1990."
+}
+
+package CYGPKG_LIBC_SIGNALS {
+	alias		{ "ISO C library signals" libc_signals }
+	directory	language/c/libc/signals
+	script		signals.cdl
+        description   "
+This component controls signal functionality, as implemented in
+ISO/IEC 9899:1990 chapter 7.7 with the signal() and raise() functions.
+As well as allowing a program to send itself signals, it is also
+possible to cause hardware exceptions to be signalled to the program
+in a similar way."
+}
+
+package CYGPKG_LIBC_STARTUP {
+	alias		{ "ISO environment startup/termination" libc_startup }
+	directory	language/c/libc/startup
+	script		startup.cdl
+        description   "
+            This package manages the control of the
+            environment (in the general sense) that an
+            application would require for full ISO C / POSIX
+            compatibility, including a main() entry point
+            supplied with arguments and an environment
+            (as retrievable by the getenv() function).
+            It also includes at the other end of things,
+            what happens when main() returns or exit() is
+            called."
+}
+
+package CYGPKG_LIBC_STDIO {
+	alias		{ "ISO C library standard input/output functions" libc_stdio }
+	directory	language/c/libc/stdio
+	script		stdio.cdl
+        description  "
+This package provides standard input/output functions associated
+with the header file <stdio.h> as specified by the
+ISO C standard - ISO/IEC 9899:1990."
+}
+
+package CYGPKG_LIBC_STDLIB {
+	alias		{ "ISO C library general utility functions" libc_stdlib }
+	directory	language/c/libc/stdlib
+	script		stdlib.cdl
+        description  "
+This package provides general utility functions associated
+with the header file <stdlib.h> as specified by the
+ISO C standard - ISO/IEC 9899:1990."
+}
+
+package CYGPKG_LIBC_STRING {
+	alias		{ "ISO C library string functions" libc_string }
+	directory	language/c/libc/string
+	script		string.cdl
+        description  "
+This package provides string functions specified by the ISO C standard
+- ISO/IEC 9899:1990."
+}
+
+package CYGPKG_LIBC_TIME {
+	alias		{ "ISO C library date/time functions" libc_time }
+	directory	language/c/libc/time
+	script		time.cdl
+        description  "
+This package provides date and time manipulation functionality specified
+by the ISO C standard - ISO/IEC 9899:1990."
+}
+
+package CYGPKG_LIBM {
+	alias		{ "Math library" libm mathlib mathlibrary }
+	directory	language/c/libm
+	script		libm.cdl
+        description  "
+ISO standard floating point mathematical library containing many
+useful functions for mathematical calculations."
+}
+
+package CYGPKG_USTL {
+	alias		{ "uSTL library" ustl }
+	directory	language/cxx/ustl
+	script		ustl.cdl
+	description  "
 This package provides the uSTL library. uSTL is a 
 partial implementation of the STL specification intended to 
 reduce code size of the derivative programs. This allows the 
 user application to use well known standard C++ STL library 
-containers, streams, iterators, algorithms and functors."
-}
-
-package CYGPKG_ERROR {
-	alias 		{ "Common error code support" error errors }
-	directory	error
-	script		error.cdl
-        description  "
-This package contains the common list of error and status codes. It is
-held centrally to allow packages to interchange error codes and status
-codes in a common way, rather than each package having its own
-conventions for error/status reporting. The error codes are modelled
-on the POSIX style naming e.g. EINVAL etc. This package also provides
-the standard strerror() function to convert error codes to textual
-representation, as well as an implementation of the errno idiom."
-}
-package CYGPKG_CYGMON {
-    alias           { "CygMon support via eCos" cygmon }
-    directory       cygmon
-    script          cygmon.cdl
-    description     "
-        This package supports the CygMon \[stand-alone debug monitor\]
-        using eCos as the underlying board support mechanism."
-}
-
-package CYGPKG_REDBOOT {
-    alias           { "RedBoot ROM monitor" redboot }
-    directory       redboot
-    script          redboot.cdl
-    description     "
-        This package creates the RedBoot \[stand-alone bootstrap & debug monitor\]
-        using eCos as the underlying board support mechanism."
-}
-
-package CYGPKG_MICROWINDOWS {
-	alias 		{ "Microwindows" mw }
-	directory	services/gfx/mw
-	script		microwindows.cdl
-        description     "Microwindows."
-}
-
-package CYGPKG_HAL_SH_SH7750_DREAMCAST {
-	alias		{ "SEGA Dreamcast" hal_sh_dreamcast sh_dreamcast_hal }
-	directory	hal/sh/dreamcast
-	script		hal_sh_sh7750_dreamcast.cdl
-	hardware
-        description "
-           This SH HAL package provides the support needed to run
-           eCos on SEGA Dreamcast."
-}
-
-# --------------------------------------------------------------------------
-# ARM packages
-package CYGPKG_HAL_ARM {
-	alias		{ "ARM common HAL" hal_arm arm_hal arm_arch_hal }
-	directory	hal/arm/arch
-	script		hal_arm.cdl
-	hardware
-	description "
-The ARM architecture HAL package provides generic support for this
-processor architecture. It is also necessary to select a specific
-target platform HAL package."
-}
-
-package CYGPKG_HAL_ARM_PID {
-	alias		{ "ARM development board (PID)" hal_arm_pid arm_pid_hal }
-	directory	hal/arm/pid
-	script		hal_arm_pid.cdl
-	hardware
-        description "
-The pid HAL package provides the support needed to run eCos on a ARM
-PID eval board."
-}
-
-package CYGPKG_HAL_ARM_AEB {
-	alias		{ "ARM evaluation board (AEB-1)" hal_arm_aeb arm_aeb_hal }
-	directory	hal/arm/aeb
-	script		hal_arm_aeb.cdl
-	hardware
-        description "
-The aeb HAL package provides the support needed to run eCos on a ARM
-AEB-1 eval board."
-}
-
-package CYGPKG_HAL_ARM_E7T {
-	alias		{ "ARM Evaluator7T board (AEB-2)" hal_arm_e7t arm_e7t_hal }
-	directory	hal/arm/e7t
-	script		hal_arm_e7t.cdl
-	hardware
-        description "
-The e7t HAL package provides the support needed to run eCos on a ARM
-Evaluator7T board (aka the AEB-2)."
-}
-
-package CYGPKG_HAL_ARM_INTEGRATOR {
-        alias           { "ARM development board (INTEGRATOR)" hal_arm_integrator arm_integrator_hal }
-        directory       hal/arm/integrator
-        script          hal_arm_integrator.cdl
-        hardware
-        description "
-        The INTEGRATOR HAL package provides the support needed to 
-        run eCos on a ARM INTEGRATOR eval board."
-}
-
-package CYGPKG_HAL_ARM_AT91 {
-	alias		{ "Atmel AT91 variant HAL" hal_arm_at91 arm_at91_hal }
-	directory	hal/arm/at91/var
-	script		hal_arm_at91.cdl
-	hardware
-        description "
-        The at91 HAL package provides the support needed to run eCos on Atmel
-        AT91 based targets."
-}
-
-package CYGPKG_HAL_ARM_AT91_JTST {
-	alias		{ "Atmel AT572D740 (diopsis) evaluation board (jtst)" hal_arm_at91_jtst arm_at91_jtst_hal }
-	directory	hal/arm/at91/jtst
-	script		hal_arm_at91_jtst.cdl
-	hardware
-        description "
-	The JTST HAL package provides the support needed to run eCos on 
-        the Atmel evaluation board AT572D74-DK1."
-}
-
-package CYGPKG_HAL_ARM_AT91SAM7 {
-	alias		{ "Atmel AT91SAM7" hal_arm_at91sam7 arm_at91_sam7 }
-	directory	hal/arm/at91/at91sam7s
-	script		hal_arm_at91sam7s.cdl
-	hardware
-        description "
-	The at91sam7 HAL package provides the support needed to run eCos on 
-        an Atmel AT91SAM7 family of CPUs."
-}
-
-package CYGPKG_HAL_ARM_AT91SAM7SEK {
-	alias		{ "Atmel AT91SAM7S" hal_arm_at91sam7sek arm_at91_sam7sek }
-	directory	hal/arm/at91/at91sam7sek
-	script		hal_arm_at91sam7sek.cdl
-	hardware
-        description "
-	The at91sam7sek HAL package provides the support needed to run eCos on 
-        an Atmel AT91SAM7S-EK development board."
-}
-
-package CYGPKG_HAL_ARM_AT91SAM7XEK {
-	alias		{ "Atmel AT91SAM7X" hal_arm_at91sam7xek arm_at91_sam7xek }
-	directory	hal/arm/at91/at91sam7xek
-	script		hal_arm_at91sam7xek.cdl
-	hardware
-        description "
-	The at91sam7xek HAL package provides the support needed to run eCos on 
-        an Atmel AT91SAM7X-EK development board."
-}
-
-package CYGPKG_HAL_ARM_SAM7EX256 {
-	alias		{ "Olimex SAM7EX256" hal_arm_sam7ex256 arm_sam7_ex256 }
-	directory	hal/arm/at91/sam7ex256
-	script		hal_arm_sam7ex256.cdl
-	hardware
-        description "
-	The SAM7EX256 HAL package provides the support needed to run eCos on 
-        an Olimex SAM7-EX256 development board."
-}
-
-package CYGPKG_HAL_ARM_AT91_EB40 {
-	alias		{ "Atmel evaluation board (EB40)" hal_arm_at91_eb40 arm_at91_eb40_hal }
-	directory	hal/arm/at91/eb40
-	script		hal_arm_at91_eb40.cdl
-	hardware
-        description "
-	The eb40 HAL package provides the support needed to run eCos on an Atmel
-	evaluation board (EB40)."
-}
-
-package CYGPKG_HAL_ARM_AT91_EB40A {
-	alias		{ "Atmel evaluation board (EB40A)" hal_arm_at91_eb40a arm_at91_eb40a_hal }
-	directory	hal/arm/at91/eb40a
-	script		hal_arm_at91_eb40a.cdl
-	hardware
-        description "
-	The eb40a HAL package provides the support needed to run eCos on an Atmel
-	evaluation board (EB40A)."
-}
-
-package CYGPKG_HAL_ARM_AT91_EB42 {
-	alias		{ "Atmel evaluation board (EB42)" hal_arm_at91_eb42 arm_at91_eb42_hal }
-	directory	hal/arm/at91/eb42
-	script		hal_arm_at91_eb42.cdl
-	hardware
-        description "
-	The eb42 HAL package provides the support needed to run eCos on an Atmel
-	evaluation board (EB42)."
-}
-
-package CYGPKG_HAL_ARM_AT91_EB55 {
-	alias		{ "Atmel evaluation board (EB55)" hal_arm_at91_eb55 arm_at91_eb55_hal }
-	directory	hal/arm/at91/eb55
-	script		hal_arm_at91_eb55.cdl
-	hardware
-        description "
-	The eb55 HAL package provides the support needed to run eCos on an 
-        Atmel evaluation board (EB55)."
-}
-
-package CYGPKG_HAL_ARM_AT91_PHYCORE {
-	alias		{ "PHYTEC evaluation board (phyCORE AT91M55800A)" hal_arm_at91_phycore arm_at91_phycore_hal }
-	directory	hal/arm/at91/phycore
-	script		hal_arm_at91_phycore.cdl
-	hardware
-        description "
-	The phyCORE HAL package provides the support needed to run eCos on 
-        an PHYTEC evaluation board (phyCORE AT91M55800A based on HD200)."
-} 
-
-package CYGPKG_HAL_ARM_LPC2XXX {
-        alias           { "Philips LPC2XXX variant HAL" hal_arm_lpc2xxx arm_lpc2xxx_hal }
-        directory       hal/arm/lpc2xxx/var
-        script          hal_arm_lpc2xxx.cdl
-        hardware
-        description "
-        The LPC2XXX HAL package provides the support needed to run eCos on
-        Philips LPC2XXX based targets."
-}
-
-package CYGPKG_HAL_ARM_LPC24XX {
-        alias           { "NXP LPC24XX variant HAL" hal_arm_lpc24xx arm_lpc24xx_hal }
-        directory       hal/arm/lpc24xx/var
-        script          hal_arm_lpc24xx.cdl
-        hardware
-        description "
-        The LPC24XX HAL package provides the support needed to run eCos on
-        NXP LPC24XX based targets."
-}
-
-package CYGPKG_HAL_ARM_LPC2XXX_MCB2100 {
-        alias           { "Keil evaluation board MCB2100 " hal_mcb2100_arm }
-        directory       hal/arm/lpc2xxx/mcb2100
-        script          hal_arm_lpc2xxx_mcb2100.cdl
-        hardware
-        description "
-        The mcb2100 HAL package provides the support needed to run eCos on an 
-        the MCB2100 evaluation board from Keil."
-}
-
-package CYGPKG_HAL_ARM_LPC2XXX_P2106 {
-        alias           { "Olimex evaluation board LPC-P2106 " hal_p2106_arm }
-        directory       hal/arm/lpc2xxx/p2106
-        script          hal_arm_lpc2xxx_p2106.cdl
-        hardware
-        description "
-        The p2106 HAL package provides the support needed to run eCos on an the
-        LPC-2106 evaluation board from Olimex."
-}
-
-package CYGPKG_HAL_ARM_LPC2XXX_PHYCORE229X {
-        alias           { "phyCORE-LPC229x development board" arm_lpc2xxx_phycore229x }
-        directory       hal/arm/lpc2xxx/phycore229x
-        script          hal_arm_lpc2xxx_phycore229x.cdl
-        hardware
-        description "
-            The Phycore HAL package provides the support needed to run eCos 
-            on a Phytec phyCORE-LPC229x development board."
-}
-
-package CYGPKG_HAL_ARM_LPC24XX_EA2468 {
-        alias           { "Embedded Artists LPC2468 OEM board" arm_lpc2xxx_ea2468 }
-        directory       hal/arm/lpc24xx/ea2468
-        script          hal_arm_lpc24xx_ea2468.cdl
-        hardware
-        description "
-            The Embedded Artists LPC2468 HAL package provides the support needed 
-            to run eCos on a Embbeded Artists LPC2468 OEM board."
-}
-
-package CYGPKG_HAL_ARM_LPC2XXX_LPCMT {
-	alias		{ "Olimex evaluation board LPC-MT " hal_lpcmt_arm }
-	directory	hal/arm/lpc2xxx/lpcmt
-	script		hal_arm_lpc2xxx_lpcmt.cdl
-	hardware
-	description "
-	The lpcmt HAL package provides the support needed to run eCos on an the 
-	LPC-MT evaluation board from Olimex."
-}
-
-package CYGPKG_HAL_ARM_LPC2XXX_OLPCH2294 {
-        alias           { "Olimex LPC-H2294 header board" hal_olpch2294_arm }
-        directory       hal/arm/lpc2xxx/olpch2294
-        script          hal_arm_lpc2xxx_olpch2294.cdl
-        hardware
-        description "
-            The olpch2294 HAL package provides the support needed to
-            run eCos on the Olimex LPC-H2294 header board."
-}
-
-package CYGPKG_HAL_ARM_LPC2XXX_OLPCE2294 {
-        alias           { "Olimex LPC-E2294 development board" hal_olpce2294_arm }
-        directory       hal/arm/lpc2xxx/olpce2294
-        script          hal_arm_lpc2xxx_olpce2294.cdl
-        hardware
-        description "
-            The olpce2294 HAL package provides the support needed to
-            run eCos on Olimex LPC-E2294 development board."
-}
-
-package CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294 {
-        alias           { "Olimex LPC-L2294-1MB development board" hal_olpcl2294_arm }
-        directory       hal/arm/lpc2xxx/olpcl2294
-        script          hal_arm_lpc2xxx_olpcl2294.cdl
-        hardware
-        description "
-            The olpcl2294 HAL package provides the support needed to run
-            eCos on Olimex LPC-L2294-1MB development board."
-}
-
-package CYGPKG_HAL_ARM_MAC7100 {
-	alias		{ "Freescale MAC7100 variant HAL" hal_arm_mac7100 arm_mac7100_hal }
-	directory	hal/arm/mac7100/var
-	script		hal_arm_mac7100.cdl
-	hardware
-        description "
-        The mac7100 HAL package provides the support needed to run eCos on Freescale
-        MAC7100 based targets."
-}
-
-package CYGPKG_HAL_ARM_MAC7100_MACE1 {
-	alias		{ "MAC7100 evaluation board (MACE1)" hal_arm_mac7100_mace1 arm_mac7100_mace1_hal }
-	directory	hal/arm/mac7100/mace1
-	script		hal_arm_mac7100_mace1.cdl
-	hardware
-        description "
-	The MACE1 HAL package provides the support needed to run eCos on an 
-        MAC7100 evaluation board (MACE1)."
-}
-
-package CYGPKG_HAL_ARM_MAC7100_MAC7100EVB {
-	alias		{ "MAC7100EVB evaluation board (Freescale)" hal_arm_mac7100_mac7100evb arm_mac7100_mac7100evb_hal }
-	directory	hal/arm/mac7100/mac7100evb
-	script		hal_arm_mac7100_mac7100evb.cdl
-	hardware
-        description "
-	The MAC7100EVB HAL package provides the support needed to run eCos on an 
-        MAC7100 evaluation board (MAC7100EVB)."
-}
-
-package CYGPKG_HAL_ARM_EBSA285 {
-	alias		{ "Intel EBSA285 StrongARM board" hal_arm_ebsa285 arm_ebsa285_hal }
-	directory	hal/arm/ebsa285
-	script		hal_arm_ebsa285.cdl
-	hardware
-        description "
-        The EBSA285 HAL package provides the support needed to run
-        eCos on a Intel EBSA285 StrongARM eval board."
-}
-
-package CYGPKG_HAL_ARM_ARM9 {
-	alias		{ "ARM9 variant" hal_arm_arm9 }
-	directory	hal/arm/arm9/var
-	script		hal_arm_arm9.cdl
-	hardware
-        description "
-        The ARM9 HAL package provides the support needed to run
-        eCos on a ARM9 based systems."
-}
-
-
-package CYGPKG_HAL_ARM_ARM9_AAED2000 {
-	alias		{ "Agilent AAED2000 unit" hal_arm_arm9_aaed }
-	directory	hal/arm/arm9/aaed2000
-	script		hal_arm_arm9_aaed2000.cdl
-	hardware
-        description "
-        The AAED2000 HAL package provides the support needed to run
-        eCos on an Agilent AAED2000 board."
-}
-
-package CYGPKG_HAL_ARM_ARM9_EXCALIBUR {
-	alias		{ "Altera Excalibur ARM9 board" hal_arm_arm9_excalibur }
-	directory	hal/arm/arm9/excalibur
-	script		hal_arm_arm9_excalibur.cdl
-	hardware
-        description "
-        The Excalibur HAL package provides the support needed to run
-        eCos on an Altera Excalibur ARM9 board."
-}
-
-package CYGPKG_HAL_ARM_ARM9_SMDK2410 {
-        alias           { "Samsung ARM9/SMDK2410 development board" hal_arm_arm9_smdk2410 }
-        directory       hal/arm/arm9/smdk2410
-        script          hal_arm_arm9_smdk2410.cdl
-        hardware
-        description "
-        The SMDK2410 HAL package provides the support needed to run
-        eCos on Samsung SMDK2410 and S3c2410x (ARM9) based development boards."
-}
-
-package CYGPKG_HAL_ARM_ARM9_INNOVATOR {
-	alias		{ "Innovator (ARM)" hal_arm_arm9_innovator }
-	directory	hal/arm/arm9/innovator
-	script		hal_arm_arm9_innovator.cdl
-	hardware
-        description "
-        The Innovator HAL package provides the support needed to run
-        RedBoot on the ARM processor of the Innovator.
-	
-	NOTE: Full support for eCos is not provided yet.  This HAL
-	contains only the minimum amount necessary to run RedBoot
-	on the Innovator.  In particular, interrupts are not yet
-	supported.  Watch this space for more details in the near
-	future."
-}
-
-package CYGPKG_HAL_ARM_SA11X0 {
-	alias		{ "Intel SA11X0 Chipset" hal_arm_sa11x0 }
-	directory	hal/arm/sa11x0/var
-	script		hal_arm_sa11x0.cdl
-	hardware
-        description "
-        The SA11X0 HAL package provides the support needed to run
-        eCos on a Intel StrongARM SA11X0 based systems."
-}
-
-package CYGPKG_HAL_ARM_SA11X0_ASSABET {
-	alias		{ "Intel SA1110 Assabet eval board" hal_arm_sa11x0_assabet }
-	directory	hal/arm/sa11x0/assabet
-	script		hal_arm_sa11x0_assabet.cdl
-	hardware
-        description "
-        The ASSABET HAL package provides the support needed to run
-        eCos on a Intel StrongARM SA1110 evaluation board (assabet)."
-}
-
-package CYGPKG_HAL_ARM_SA11X0_CERF {
-	alias		{ "Intrinsyc Cerf board" hal_arm_sa11x0_cerf }
-	directory	hal/arm/sa11x0/cerf
-	script		hal_arm_sa11x0_cerf.cdl
-	hardware
-        description "
-        The CERF HAL package provides the support needed to run
-        eCos on a Intrinsyc StrongARM SA1110 Cerf board."
-}
-
-package CYGPKG_HAL_ARM_SA11X0_CERFPDA {
-	alias		{ "Intrinsyc Cerfpda" hal_arm_sa11x0_cerfpda }
-	directory	hal/arm/sa11x0/cerfpda
-	script		hal_arm_sa11x0_cerfpda.cdl
-	hardware
-        description "
-        The CERFPDA HAL package provides the support needed to run
-        eCos on a Intrinsyc StrongARM SA1110 Cerfpda."
-}
-
-package CYGPKG_HAL_ARM_SA11X0_IPAQ {
-	alias		{ "Compaq iPAQ Pocket PC" hal_arm_sa11x0_ipaq }
-	directory	hal/arm/sa11x0/ipaq
-	script		hal_arm_sa11x0_ipaq.cdl
-	hardware
-        description "
-        The IPAQ HAL package provides the support needed to run
-        eCos on a Intel StrongARM SA1110 pocket PC (Compaq iPAQ)."
-}
-
-package CYGPKG_HAL_ARM_SA11X0_FLEXANET {
-      alias           { "SA1110 Flexanet board" hal_arm_sa11x0_flexanet }
-      directory       hal/arm/sa11x0/flexanet
-      script          hal_arm_sa11x0_flexanet.cdl
-      hardware
-      description "
-        The FLEXANET HAL package provides the support needed to run
-        eCos on an SA1110 Flexanet board."
-}
-
-package CYGPKG_HAL_ARM_SNDS {
-      alias       { "Samsung SNDS" hal_arm_snds arm_snds_hal}
-      directory   hal/arm/snds
-      script      hal_arm_snds.cdl
-      hardware
-      description "
-          The SNDS HAL package provides the support needed to run eCos on a
-          Samsung SNDS eval board"
-}
-
-package CYGPKG_DEVS_ETH_SMSC_LAN91CXX {
-	alias 		{ "SMSC LAN91CXX ethernet driver" lan91cxx_eth_driver lan9000_eth_driver }
-	hardware
-	directory	devs/eth/smsc/lan91cxx
-	script		smsc_lan91cxx_eth_drivers.cdl
-        description     "Ethernet driver for SMSC LAN91CXX (LAN9000) controller."
-}
-
-
-package CYGPKG_HAL_ARM_SA11X0_NANO {
-	alias		{ "Intel SA1110 nanoEngine eval board" hal_arm_sa11x0_nano }
-	directory	hal/arm/sa11x0/nano
-	script		hal_arm_sa11x0_nano.cdl
-	hardware
-        description "
-        The nanoEngine HAL package provides the support needed to run
-        eCos on the Bright Star Engineering nanoEngine StrongARM SA1110 board."
-}
-
-package CYGPKG_DEVS_ETH_ARM_NANO {
-	alias 		{ "BSE nanoEngine with 82559 ethernet driver"
-			   devs_eth_arm_nano nano_eth_driver }
-	hardware
-	directory	devs/eth/arm/nano
-	script		nano_eth_drivers.cdl
-        description     "Ethernet driver for SA11x0 nanoEngine with Intel
-                         i82559 ethernet interfaces."
-}
-
-package CYGPKG_HAL_ARM_SA11X0_BRUTUS {
-	alias		{ "Intel SA1100 Brutus eval board" hal_arm_sa11x0_brutus }
-	directory	hal/arm/sa11x0/brutus
-	script		hal_arm_sa11x0_brutus.cdl
-	hardware
-        description "
-        The BRUTUS HAL package provides the support needed to run
-        eCos on a Intel StrongARM SA1110 evaluation board (brutus)."
-}
-
-package CYGPKG_HAL_ARM_SA11X0_SA1100MM {
-	alias		{ "Intel SA1100 Multimedia eval board" hal_arm_sa11x0_sa1100mm }
-	directory	hal/arm/sa11x0/sa1100mm
-	script		hal_arm_sa11x0_sa1100mm.cdl
-	hardware
-        description "
-        The MULTIMEDIA HAL package provides the support needed to run
-        eCos on a Intel StrongARM SA1110 Multimedia evaluation board."
-}
-
-package CYGPKG_HAL_ARM_EDB7XXX {
-	alias		{ "Cirrus Logic ARM7 based development boards" hal_arm_edb7xxx arm_edb7xxx_hal }
-	directory	hal/arm/edb7xxx
-	script		hal_arm_edb7xxx.cdl
-	hardware
-        description "
-The EDB7XXX HAL package provides the support needed to run eCos on Cirrus Logic CL-PS7111 and EP7xxx based development boards."
-}
-
-package CYGPKG_HAL_ARM_CMA230 {
-	alias		{ "Cogent CMA230/222 board" hal_arm_cma230 arm_cma230_hal }
-	directory	hal/arm/cma230
-	script		hal_arm_cma230.cdl
-	hardware
-        description "
-The cma230 HAL package provides the support needed to run eCos on a Cogent 
-CMA230 (ARM7TDMI) or CMA222 (ARM710T) eval board."
-}
-
-package CYGPKG_HAL_ARM_AIM711 {
-      alias       { "ARM Industial Module AIM 711" hal_arm_aim711 arm_aim711_hal}
-      directory   hal/arm/aim711
-      script      hal_arm_aim711.cdl
-      hardware
-      description "
-          The ARM Industial Module AIM 711 HAL package provides the support
-          needed to run eCos on a ARM Industial Module AIM 711 from
-          Vision Systems GmbH."
-}
-
-package CYGPKG_HAL_ARM_XSCALE_CORE {
-	alias		{ "Intel XScale Core" hal_arm_xscale_core }
-	directory	hal/arm/xscale/cores
-	script		hal_arm_xscale_core.cdl
-	hardware
-        description "
-        The XScale core HAL package provides the support needed to run eCos
-        on all Intel XScale based systems."
-}
-
-package CYGPKG_HAL_ARM_XSCALE_IOP310 {
-	alias		{ "Intel IOP8310 (IQ80200/IQ80310) XScale chipset" hal_arm_iop310 arm_iop310_hal }
-	directory	hal/arm/xscale/iop310
-	script		hal_arm_xscale_iop310.cdl
-	hardware
-	description "
-	The IOP310 HAL package provides the support needed to run
-	eCos on a system using the Intel XScale IOP310 (IQ80200/80310) chipset."
-}
-
-package CYGPKG_HAL_ARM_XSCALE_IQ80310 {
-	alias		{ "Intel IQ80310 (Cyclone) eval board" hal_arm_xscale_iq80310 hal_arm_xscale_cyclone }
-	directory	hal/arm/xscale/iq80310
-	script		hal_arm_xscale_iq80310.cdl
-	hardware
-	description "
-	The IQ80310 HAL package provides the support needed to run
-	eCos on an Intel Cyclone evaluation board, utilizing an Intel XScale 
-        IQ80200/80310 chipset."
-}
-
-package CYGPKG_HAL_ARM_XSCALE_NPWR {
-	alias		{ "NPWR Linux Engine" hal_arm_xscale_npwr }
-	directory	hal/arm/xscale/npwr
-	script		hal_arm_xscale_npwr.cdl
-	hardware
-	description "
-	The NPWR HAL package provides the support needed to run
-	eCos on a NPWR Linux Engine, utilizing an Intel XScale 
-        IQ80200/80310 chipset."
-}
-
-package CYGPKG_DEVS_ETH_ARM_XSCALE_NPWR {
-	alias 		{ "NPWR Linux Engine ethernet drivers" devs_eth_arm_xscale_npwr }
-	hardware
-	directory	devs/eth/arm/npwr
-	script		npwr_eth_drivers.cdl
-        description     "Ethernet drivers for NPWR Linux Engine via 82544 NIC."
-}
-
-package CYGPKG_HAL_ARM_XSCALE_VERDE {
-	alias		{ "Intel XScale 80320 I/O Processor" hal_arm_xscale_verde }
-	directory	hal/arm/xscale/verde
-	script		hal_arm_xscale_verde.cdl
-	hardware
-        description "
-        The XSCALE HAL package provides the support needed to run
-        eCos on Intel 80320 based systems."
-}
-
-package CYGPKG_HAL_ARM_XSCALE_IQ80321 {
-	alias		{ "Intel XScale IQ80321 eval board" hal_arm_xscale_iq80321 }
-	directory	hal/arm/xscale/iq80321
-	script		hal_arm_xscale_iq80321.cdl
-	hardware
-        description "
-        The IQ80321 HAL package provides the support needed to run
-        eCos on an Intel XScale IQ80321 evaluation board."
-}
-
-package CYGPKG_HAL_ARM_XSCALE_IXP425 {
-	alias		{ "Intel XScale IXP425 Network Processor" hal_arm_xscale_ixp425 }
-	directory	hal/arm/xscale/ixp425
-	script		hal_arm_xscale_ixp425.cdl
-	hardware
-        description "
-        The XScale IXP425 HAL package provides the support needed to run
-        eCos on Intel XScale IXP425 network processor based systems."
-}
-
-package CYGPKG_HAL_ARM_XSCALE_XSENGINE {
-       alias           { "Exys XSEngine" hal_arm_xscale_xsengine }
-       directory       hal/arm/xscale/xsengine
-       script          hal_arm_xscale_xsengine.cdl
-       hardware
-       description "
-         The XSEngine HAL package provides the support needed to run
-         eCos on an Exys XSEngine board."
-}
-
-package CYGPKG_HAL_ARM_XSCALE_IXDP425 {
-	alias		{ "Intel XScale IXDP425 Network Processor eval board" hal_arm_xscale_ixdp425 }
-	directory	hal/arm/xscale/ixdp425
-	script		hal_arm_xscale_ixdp425.cdl
-	hardware
-        description "
-        The IXDP425 HAL package provides the support needed to run
-        eCos on an Intel XScale IXDP425 network processor evaluation board."
-}
-
-package CYGPKG_HAL_ARM_XSCALE_GRG {
-	alias		{ "Intel XScale Generic Residential Gateway" hal_arm_xscale_grg }
-	directory	hal/arm/xscale/grg
-	script		hal_arm_xscale_grg.cdl
-	hardware
-        description "
-        The GRG HAL package provides the support needed to run eCos on an
-        Intel Generic Residential Gateway evaluation board."
-}
-
-package CYGPKG_HAL_ARM_XSCALE_PRPMC1100 {
-	alias		{ "Motorola PrPMC1100 PMC for Intel XScale IXC1100" hal_arm_xscale_prpmc1100 }
-	directory	hal/arm/xscale/prpmc1100
-	script		hal_arm_xscale_prpmc1100.cdl
-	hardware
-        description "
-        The PrPMC1100 HAL package provides the support needed to run eCos on an
-        Motorola PrPMC1100 evaluation board."
-}
-
-package CYGPKG_HAL_ARM_XSCALE_PXA2X0 {
-	alias		{ "Intel PXA2X0" hal_arm_xscale_pxa2x0 }
-	directory	hal/arm/xscale/pxa2x0
-	script		hal_arm_xscale_pxa2x0.cdl
-	hardware
-		description "
-		The PXA2X0 HAL package provides the support needed to run
-		eCos on Intel PXA2X0 based systems."
-}
-
-package CYGPKG_HAL_ARM_XSCALE_MPC50 {
-	alias		{ "MICROPLEX Printer Controller 5.0" hal_arm_xscale_mpc50 }
-	directory	hal/arm/xscale/mpc50
-	script		hal_arm_xscale_mpc50.cdl
-	hardware
-        description "
-        The MPC50 HAL package provides the support needed to run
-        eCos on a MPC 5.0."
-}
-
-# --------------------------------------------------------------------------
-# SH packages
-package CYGPKG_HAL_SH {
-	alias		{ "SH common HAL" hal_sh sh_hal sh_arch_hal }
-	directory	hal/sh/arch
-	script		hal_sh.cdl
-	hardware
-	description "
-           The SH (SuperH) architecture HAL package provides generic
-           support for this processor architecture. It is also
-           necessary to select variant and target platform HAL
-           packages."
-}
-
-package CYGPKG_HAL_SH_SH2 {
-    alias         { "SH2 architecture" hal_sh_sh2 }
-    directory     hal/sh/sh2
-    script        hal_sh_sh2.cdl
-    hardware
-    description   "
-        The SH2 (SuperH 2) variant HAL package provides generic
-        support for SH2 variant CPUs."
-}
-
-package CYGPKG_HAL_SH_SH3 {
-    alias         { "SH3 architecture" hal_sh_sh3 }
-    directory     hal/sh/sh3
-    script        hal_sh_sh3.cdl
-    hardware
-    description   "
-        The SH3 (SuperH 3) variant HAL package provides generic
-        support for SH3 variant CPUs."
-}
-
-package CYGPKG_HAL_SH_SH4 {
-    alias         { "SH4 architecture" hal_sh_sh4 }
-    directory     hal/sh/sh4
-    script        hal_sh_sh4.cdl
-    hardware
-    description   "
-        The SH4 (SuperH 4) variant HAL package provides generic
-        support for SH4 variant CPUs."
-}
-
-package CYGPKG_HAL_SH_EDK7708 {
-	alias		{ "Hitachi SH7708 board" hal_sh_edk sh_edk_hal }
-	directory	hal/sh/edk7708
-	script		hal_sh_edk7708.cdl
-	hardware
-        description "
-           This SH HAL package provides the support needed to run
-           eCos on a Hitachi SH3 EDK7708 board."
-}
-
-package CYGPKG_HAL_SH_SH7708_CQ7708 {
-        alias           { "CqREEK SH7708 board" hal_sh_cq sh_cq_hal }
-        directory       hal/sh/cq7708
-        script          hal_sh_sh7708_cq7708.cdl
-        hardware
-        description "
-           This SH HAL package provides the support needed to run
-           eCos on a CqREEK SH7708 board."
-}
-
-package CYGPKG_HAL_SH_SH7750_CQ7750 {
-	alias		{ "CqREEK SH7750 board" hal_sh_cqsh4 sh_cqsh4_hal }
-	directory	hal/sh/cq7750
-	script		hal_sh_sh7750_cq7750.cdl
-	hardware
-        description "
-           This SH HAL package provides the support needed to run
-           eCos on a CqREEK SH7750 board."
-}
-
-
-package CYGPKG_HAL_SH_SH7729_HS7729PCI {
-	alias		{ "Hitachi HS7729PCI board" hal_sh_sh7729_hs7729pci sh_sh7729_hs7729pci_hal }
-	directory	hal/sh/hs7729pci
-	script		hal_sh_sh7729_hs7729pci.cdl
-	hardware
-        description "
-           This SH HAL package provides the support needed to run
-           eCos on a Hitachi HS7729PCI board."
-}
-
-package CYGPKG_HAL_SH_SH77X9_SE77X9 {
-	alias		{ "Hitachi SE77x9 board" hal_sh_sh77x9_se77x9 sh_sh77x9_se77x9_hal }
-	directory	hal/sh/se77x9
-	script		hal_sh_sh77x9_se77x9.cdl
-	hardware
-        description "
-           This SH HAL package provides the support needed to run
-           eCos on a Hitachi Solution Engine 77x9 board."
-}
-
-package CYGPKG_HAL_SH_SH7751_SE7751 {
-	alias		{ "Hitachi SE7751 board" hal_sh_sh7751_se7751 sh_sh7751_se7751_hal }
-	directory	hal/sh/se7751
-	script		hal_sh_sh7751_se7751.cdl
-	hardware
-        description "
-           This SH HAL package provides the support needed to run
-           eCos on a Hitachi Solution Engine 7751 board."
-}
-
-package CYGPKG_HAL_SH_SH4_202_MD {
-    alias         { "SuperH SH4-202 MicroDev CPU Board" hal_sh_sh4_202_md }
-    directory     hal/sh/sh4_202_md
-    script        hal_sh_sh4_202_md.cdl
-    hardware
-    description   "
-        The SH4-202 HAL package provides generic
-        support for the SuperH SH4-202 MicroDev CPU board."
-}
-
-# --------------------------------------------------------------------------
-# H8/300 packages
-package CYGPKG_HAL_H8300 {
-	alias		{ "Hitachi H8300 common HAL" hal_h8300 h8300_hal}
-	directory	hal/h8300/arch
-	script		hal_h8300.cdl
-	hardware
-	description "
-The Hitachi H8/300 architecture HAL package provides generic support for this
-processor architecture. It is also necessary to select a specific
-target platform HAL package."
-}
-
-package CYGPKG_HAL_H8300_H8300H {
-	alias		{ "Hitachi H8300H variant HAL" hal_h8300h h8300h_hal}
-	directory	hal/h8300/h8300h
-	script		hal_h8300_h8300h.cdl
-	hardware
-        description "
-The H8/300H HAL package provides the support needed to run eCos on a Hitachi
-H8/300H processor."
-}
-
-package CYGPKG_HAL_H8300_H8S {
-	alias		{ "Hitachi H8S variant HAL" hal_h8s h8s_hal}
-	directory	hal/h8300/h8s
-	script		hal_h8300_h8s.cdl
-	hardware
-        description "
-The H8S HAL package provides the support needed to run eCos on a Hitachi
-H8S processor."
-}
-
-package CYGPKG_HAL_H8300_H8300H_SIM {
-	alias		{ "H8/300H simulator" hal_h8300h_sim h8300h_sim_hal }
-	directory	hal/h8300/sim
-	script		hal_h8300_h8300h_sim.cdl
-	hardware
-        description "
-           The minimal simulator HAL package is provided for use when
-           only a simple simulation of the processor architecture is
-           desired, as opposed to detailed simulation of any specific
-           board. In particular it is not possible to simulate any of
-           the I/O devices, so device drivers cannot be used."
-}
-
-package CYGPKG_HAL_H8300_H8300H_AKI3068NET {
-	alias		{ "Akizuki H8/3068 board" hal_h8300h_aki3068net h8300h_aki3068net_hal }
-	directory	hal/h8300/aki3068net
-	script		hal_h8300_h8300h_aki3068net.cdl
-	hardware
-        description "
-           The aki3068net HAL package provides the support needed to run
-           eCos on a Akizuki H8/3068 Network micom board." 
-}
-
-package CYGPKG_HAL_H8300_H8300H_H8MAX {
-	alias		{ "H8MAX board" hal_h8300h_h8max h8300h_h8max_hal }
-	directory	hal/h8300/h8max
-	script		hal_h8300_h8300h_h8max.cdl
-	hardware
-        description "
-           The h8max HAL package provides the support needed to run
-           eCos on a H8MAX board." 
-}
-
-package CYGPKG_HAL_H8300_H8S_SIM {
-	alias		{ "H8S simulator" hal_h8s_sim h8s_sim_hal }
-	directory	hal/h8300/sim_s
-	script		hal_h8300_h8s_sim.cdl
-	hardware
-        description "
-           The minimal simulator HAL package is provided for use when
-           only a simple simulation of the processor architecture is
-           desired, as opposed to detailed simulation of any specific
-           board. In particular it is not possible to simulate any of
-           the I/O devices, so device drivers cannot be used."
-}
-
-package CYGPKG_HAL_H8300_H8S_EDOSK2674 {
-	alias		{ "EDOSK-2674 board" hal_h8s_edosk2674 h8s_edosk2674_hal }
-	directory	hal/h8300/edosk2674
-	script		hal_h8300_h8s_edosk2674.cdl
-	hardware
-        description "
-           The edosk2674 HAL package provides the support needed to run
-           eCos on a Hitachi Micro System Europe EDOSK-2674 Evalution board." 
-}
-
-# ==========================================================================
-# --------------------------------------------------------------------------
-# i386 packages
-package CYGPKG_HAL_I386 {
-	alias		{ "i386 common HAL" hal_i386 i386_hal i386_arch_hal }
-	directory	hal/i386/arch
-	script		hal_i386.cdl
-	hardware
-	description "
-    	    The i386 architecture HAL package provides generic
-    	    support for this processor architecture. It is also
-    	    necessary to select a specific target platform HAL
-    	    package."
-}
-
-package CYGPKG_HAL_I386_GENERIC {
-	alias		{ "i386 generic target" hal_i386_generic }
-	directory	hal/i386/generic
-	script		hal_i386_generic.cdl
-	hardware
-        description "
-    	    The i386 generic Target HAL package provides support
-            for generic IA32 processors, from the 80386 to the latest
-            Pentium/Athlon."
-	    
-}
-package CYGPKG_HAL_I386_PCMB {
-	alias		{ "i386 PC Motherboard" hal_i386_pcmb }
-	directory	hal/i386/pcmb
-	script		hal_i386_pcmb.cdl
-	hardware
-        description "
-    	    The i386 PC Motherboard HAL package provides the 
-    	    support needed to run eCos binaries on a standard i386
-    	    PC motherboard. This is a support package for various
-            actual platform specific targets."
-}
-package CYGPKG_HAL_I386_PC {
-	alias		{ "i386 PC target" hal_i386_pc }
-	directory	hal/i386/pc
-	script		hal_i386_pc.cdl
-	hardware
-        description "
-    	    The i386 PC Target HAL package provides the 
-    	    support needed to run eCos binaries on a standard i386
-    	    PC."
-}
-
-# --------------------------------------------------------------------------
-# Synthetic target.
-package CYGPKG_HAL_SYNTH {
-	alias		{ "Linux synthetic target" linux }
-	directory	hal/synth/arch
-	script		hal_synth.cdl
-	hardware
-        description "
-    	    The Linux Synthetic Target HAL package provides the 
-    	    support needed to run eCos binaries on top of the i386
-    	    Linux kernel."
-}
-
-package CYGPKG_HAL_SYNTH_I386 {
-	alias		{ "Linux/i386 synthetic target" i386_linux }
-	directory	hal/synth/i386linux
-	script		hal_synth_i386.cdl
-	hardware
-        description "
-            i386 processor-specific support for the Linux synthetic target"
-}
-
-# --------------------------------------------------------------------------
-# SPARClite packages
-package CYGPKG_HAL_SPARCLITE {
-	alias		{ "SPARClite common HAL" hal_sparclite sparclite_hal sparclite_arch_hal }
-	directory	hal/sparclite/arch
-	script		hal_sparclite.cdl
-	hardware
-	description "
-    	    The SPARClite architecture HAL package provides generic support
-    	    for this processor architecture. It is also necessary to select
-    	    a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_SPARCLITE_SLEB {
-	alias		{ "Fujitsu MB86800-MA01 board" hal_sparclite_sleb sparclite_sleb_hal }
-	directory	hal/sparclite/sleb
-	script		hal_sparclite_sleb.cdl
-	hardware
-        description "
-    	    The SPARClite evaluation board HAL package is provided for use
-    	    with the Fujitsu MB8683x boards."
-}
-
-package CYGPKG_HAL_SPARCLITE_SIM {
-	alias		{ "SPARClite simulator" hal_sparclite_sim sparclite_sim_hal }
-	directory	hal/sparclite/sim
-	script		hal_sparclite_sim.cdl
-	hardware
-        description "
-    	    The SPARClite simulator HAL package is provided for use
-    	    with the SPARClite simulator."
-}
-
-# --------------------------------------------------------------------------
-# SPARC V7/V8 packages
-package CYGPKG_HAL_SPARC {
-	alias		{ "SPARC V7/V8 common HAL" hal_sparc sparc_hal sparc_arch_hal }
-	directory	hal/sparc/arch
-	script		hal_sparc.cdl
-	hardware
-	description "
-    	    The SPARC V7/V8 architecture HAL package provides generic support
-    	    for this processor architecture. It is also necessary to select
-    	    a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_SPARC_ERC32 {
-	alias		{ "ERC32 processor" hal_sparc_erc32 sparc_erc32_hal }
-	directory	hal/sparc/erc32
-	script		hal_sparc_erc32.cdl
-	hardware
-        description "
-    	    The ERC32 processor HAL package is provided for use
-    	    with both real hardware and the TSIM/ERC32 simulator."
-}
-
-package CYGPKG_HAL_SPARC_LEON {
-	alias		{ "LEON processor" hal_sparc_leon sparc_leon_hal }
-	directory	hal/sparc/leon
-	script		hal_sparc_leon.cdl
-	hardware
-        description "
-    	    The LEON processor HAL package is provided for use
-    	    with both real hardware and the TSIM/LEON simulator."
-}
-
-# --------------------------------------------------------------------------
-# PowerPC packages
-package CYGPKG_HAL_POWERPC {
-	alias		{ "PowerPC common HAL" hal_powerpc powerpc_hal powerpc_arch_hal }
-	directory	hal/powerpc/arch
-	script		hal_powerpc.cdl
-	hardware
-	description "
- 	    The PowerPC architecture HAL package provides generic
- 	    support for this processor architecture. It is also necessary to
-    	    select a CPU variant and a specific target platform HAL
-    	    package."
-}
-
-package CYGPKG_HAL_POWERPC_MPC8260 {
-	alias		{ "PowerPC MPC8260 variant HAL" hal_mpc8260 }
-	directory	hal/powerpc/mpc8260/
-	script		hal_powerpc_mpc8260.cdl
-	hardware
-        description "
-           The PowerPC MPC8260 PowerQUICCII variant HAL package provides 
-           support for this processor variant. It is also necessary to
-           select a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_POWERPC_MPC8XXX {
-	alias		{ "PowerPC MPC8XXX variant HAL" hal_mpc8xxx }
-	directory	hal/powerpc/mpc8xxx/
-	script		hal_powerpc_mpc8xxx.cdl
-	hardware
-        description "
-           The PowerPC MPC8XXX PowerQUICCII variant HAL package provides 
-           support for this processor variant. It is also necessary to
-           select a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_POWERPC_MPC8xx {
-	alias		{ "PowerPC 8xx variant HAL" hal_mpc8xx mpc8xx_hal mpc8xx_arch_hal }
-	directory	hal/powerpc/mpc8xx/
-	script		hal_powerpc_mpc8xx.cdl
-	hardware
-        description "
-           The PowerPC 8xx variant HAL package provides generic support
-           for this processor variant. It is also necessary to
-           select a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_POWERPC_PPC60x {
-	alias		{ "PowerPC 60x variant HAL" hal_ppc60x ppc60x_hal ppc60x_arch_hal }
-	directory	hal/powerpc/ppc60x/
-	script		hal_powerpc_ppc60x.cdl
-	hardware
-        description "
-           The PowerPC 60x variant HAL package provides generic support
-           for this processor variant. It is also necessary to
-           select a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_POWERPC_MPC5xx {
-        alias           { "PowerPC 5xx variant HAL" hal_mpc5xx mpc5xx_hal mpc5xx_arch_hal }
-        directory       hal/powerpc/mpc5xx/
-        script          hal_powerpc_mpc5xx.cdl
-        hardware
-        description "
-           The PowerPC 5xx variant HAL package provides generic support
-           for this processor variant. It is also necessary to
-           select a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_POWERPC_PPC40x {
-	alias		{ "PowerPC 40x variant HAL" hal_ppc40x ppc40x_hal ppc40x_arch_hal }
-	directory	hal/powerpc/ppc40x/
-	script		hal_powerpc_ppc40x.cdl
-	hardware
-        description "
-           The PowerPC 40x variant HAL package provides generic support
-           for this processor variant. It is also necessary to
-           select a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_POWERPC_COGENT {
-	alias		{ "Cogent CMA286/287 board" hal_powerpc_cogent powerpc_cogent_hal }
-	directory	hal/powerpc/cogent
-	script		hal_powerpc_cogent.cdl
-	hardware
-        description "
-            The cogent HAL package provides the support needed to run
-            eCos on a Cogent board equipped with a PowerPC processor."
-}
-
-package CYGPKG_HAL_POWERPC_CME555 {
-        alias           { "Axiom's CME555 evaluation board" hal_powerpc_cme555 powerpc_cme555_hal }
-        directory       hal/powerpc/cme555
-        script          hal_powerpc_cme555.cdl
-        hardware
-        description "
-            The CME555 HAL package provides the support needed to run
-            eCos on a CME555 evaluation board from Axiom Manufacturing."
-}
-
-package CYGPKG_HAL_POWERPC_EC555 {
-        alias           { "Wuerz development board" hal_powerpc_ec555 powerpc_ec555_hal }
-        directory       hal/powerpc/ec555
-        script          hal_powerpc_ec555.cdl
-        hardware
-        description "
-            The EC555 HAL package provides the support needed to run
-            eCos on an EC555 development board from Wuerz elektronik."
-}
-
-package CYGPKG_HAL_POWERPC_PATI {
-        alias           { "MPL PATI PC/104+ board" hal_powerpc_pati powerpc_pati_hal }
-        directory       hal/powerpc/pati
-        script          hal_powerpc_pati.cdl
-        hardware
-        description "
-            The PATI HAL package provides the support needed to run
-            eCos on an PATI PC/104+ board from MPL elektronik."
-}
-
-package CYGPKG_HAL_POWERPC_FADS {
-	alias		{ "Motorola MPC8xxFADS board" hal_powerpc_fads powerpc_fads_hal }
-	directory	hal/powerpc/fads
-	script		hal_powerpc_fads.cdl
-	hardware
-        description "
-            The FADS HAL package provides the support needed to run
-            eCos on a Motorola FADS board equipped with a PowerPC processor."
-}
-package CYGPKG_HAL_POWERPC_MBX {
-	alias		{ "Motorola MBX860/821 board" hal_powerpc_mbx powerpc_mbx_hal }
-	directory	hal/powerpc/mbx
-	script		hal_powerpc_mbx.cdl
-	hardware
-        description "
-            The MBX HAL package provides the support needed to run
-            eCos on a Motorola MBX board equipped with a PowerPC processor."
-}
-
-package CYGPKG_HAL_POWERPC_VIPER {
-	alias		{ "A&M Viper PPC860 board" hal_powerpc_viper powerpc_viper_hal }
-	directory	hal/powerpc/viper
-	script		hal_powerpc_viper.cdl
-	hardware
-        description "
-            The VIPER HAL package provides the support needed to run
-            eCos on a A&M VIPER board equipped with a PowerPC processor."
-}
-
-package CYGPKG_HAL_POWERPC_TS6 {
-	alias		{ "Delphi TigerSHARC-6 board" hal_powerpc_ts6 powerpc_ts6_hal }
-	directory	hal/powerpc/ts6
-	script		hal_powerpc_ts6.cdl
-	hardware
-        description "
-            The TS6 HAL package provides the support needed to run
-            eCos on a Delphi TigerSHARC-6 board equipped with a
-            PowerPC processor."
-}
-
-package CYGPKG_HAL_POWERPC_VADS {
-	alias		{ "Motorola MPC8260 VADS board" hal_powerpc_vads powerpc_vads_hal }
-	directory	hal/powerpc/vads
-	script		hal_powerpc_vads.cdl
-	hardware
-        description "
-            The VADS HAL package provides the support needed to run
-            eCos on a Motorola MPC8260 VADS board equipped with a
-            PowerPC processor."
-}
-
-package CYGPKG_HAL_QUICC {
-	alias		{ "Motorola MPC8xx QUICC support" hal_quicc quicc_hal quicc }
-	directory	hal/powerpc/quicc
-	script		hal_powerpc_quicc.cdl
-	hardware
-        description "
-            The QUICC package provides some of the support needed
-            to run eCos on a Motorola MPC8xx processors, using the QUICC
-            communications subsystem."
-}
-
-package CYGPKG_HAL_POWERPC_SIM {
-	alias		{ "PowerPC simulator" hal_powerpc_sim powerpc_sim_hal }
-	directory	hal/powerpc/sim
-	script		hal_powerpc_sim.cdl
-	hardware
-        description "
-            The minimal simulator HAL package is provided for use when
-            only a simple simulation of the processor architecture is
-            desired, as opposed to detailed simulation of any specific
-            board. In particular it is not possible to simulate any of
-            the I/O devices, so device drivers cannot be used."
-}
-
-# --------------------------------------------------------------------------
-# MIPS packages
-
-package CYGPKG_HAL_MIPS {
-	alias		{ "MIPS common HAL" hal_mips mips_hal mips_arch_hal }
-	directory	hal/mips/arch/
-	script		hal_mips.cdl
-	hardware
-	description "
-    	    The MIPS architecture HAL package provides generic support
-    	    for this processor architecture. It is also necessary to
-    	    select a CPU variant and a specific target platform HAL
-    	    package."
-}
-
-package CYGPKG_HAL_MIPS_SIM {
-	alias		{ "MIPS simulator" hal_mips_sim mips_sim_hal }
-	directory	hal/mips/sim
-	script		hal_mips_sim.cdl
-	hardware
-	description "
-           The minimal simulator HAL package is provided for when only
-           a simple simulation of the processor architecture is
-           desired, as opposed to detailed simulation of any specific
-           board. To use this minimal simulator the command
-           `target sim --board=jmr3904pal' should be used from inside
-           gdb. It is not possible to use any of the eCos device
-           drivers when the simulator is running in this mode"
-}
-
-package CYGPKG_HAL_MIPS_TX39 {
-	alias		{ "TX39 chip HAL" hal_tx39 tx39_hal tx39_arch_hal }
-	directory	hal/mips/tx39/
-	script		hal_mips_tx39.cdl
-	hardware
-        description "
-           The TX39 architecture HAL package provides generic support
-           for this processor architecture. It is also necessary to
-           select a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_MIPS_TX39_JMR3904 {
-	alias		{ "Toshiba JMR-TX3904 board" hal_tx39_jmr3904 tx39_jmr3904_hal }
-	directory	hal/mips/jmr3904
-	script		hal_mips_tx39_jmr3904.cdl
-	hardware
-	description "
-           The JMR3904 HAL package should be used when targetting the
-           actual hardware. The same package can also be used when
-           running on the full simulator, since this provides an
-           accurate simulation of the hardware including I/O devices.
-           To use the simulator in this mode the command
-           `target sim --board=jmr3904' should be used from inside gdb."
-}
-
-package CYGPKG_HAL_MIPS_MIPS32 {
-	alias		{ "MIPS32 HAL" hal_mips32 mips32_hal mips32_arch_hal }
-	directory	hal/mips/mips32/
-	script		hal_mips_mips32.cdl
-	hardware
-        description "
-           The MIPS 32 architecture HAL package provides generic support
-           for this processor architecture. It is also necessary to
-           select a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_MIPS_MIPS64 {
-	alias		{ "MIPS64 HAL" hal_mips64 mips64_hal mips64_arch_hal }
-	directory	hal/mips/mips64/
-	script		hal_mips_mips64.cdl
-	hardware
-        description "
-           The MIPS 64 architecture HAL package provides generic support
-           for this processor architecture. It is also necessary to
-           select a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_MIPS_ATLAS {
-	alias		{ "MIPS Atlas board" hal_atlas atlas_hal }
-	directory	hal/mips/atlas
-	script		hal_mips_atlas.cdl
-	hardware
-	description "
-           The Atlas HAL package should be used when targetting the
-           actual hardware. "
-}
-package CYGPKG_HAL_MIPS_MALTA {
-	alias		{ "MIPS Malta board" hal_malta malta_hal }
-	directory	hal/mips/malta
-	script		hal_mips_malta.cdl
-	hardware
-	description "
-           The Malta HAL package should be used when targetting the
-           actual hardware. "
-}
-
-package CYGPKG_HAL_MIPS_TX49 {
-	alias		{ "TX49 chip HAL" hal_tx49 tx49_hal tx49_arch_hal }
-	directory	hal/mips/tx49/
-	script		hal_mips_tx49.cdl
-	hardware
-        description "
-           The TX49 architecture HAL package provides generic support
-           for this processor architecture. It is also necessary to
-           select a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_MIPS_TX49_REF4955 {
-	alias		{ "Toshiba TX4955 reference platform" hal_tx49_ref4955 tx49_ref4955_hal }
-	directory	hal/mips/ref4955
-	script		hal_mips_tx49_ref4955.cdl
-	hardware
-	description "
-           The REF4955 HAL package should be used when targetting the
-           actual hardware."
-}
-
-package CYGPKG_HAL_MIPS_RM7000 {
-	alias		{ "RM7000 chip HAL" hal_rm7000 rm7000_hal rm7000_arch_hal }
-	directory	hal/mips/rm7000/var
-	script		hal_mips_rm7000.cdl
-	hardware
-        description "
-           The RM7000 architecture HAL package provides generic support
-           for this processor architecture. It is also necessary to
-           select a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_MIPS_RM7000_OCELOT {
-	alias		{ "PMC-Sierra Ocelot platform" hal_rm7000_ocelot rm7000_ocelot_hal }
-	directory	hal/mips/rm7000/ocelot
-	script		hal_mips_rm7000_ocelot.cdl
-	hardware
-	description "
-           The Ocelot HAL package should be used when targetting the
-           actual hardware."
-}
-
-package CYGPKG_HAL_MIPS_VR4300 {
-	alias		{ "VR4300 chip HAL" hal_vr4300 vr4300_hal vr4300_arch_hal }
-	directory	hal/mips/vr4300/
-	script		hal_mips_vr4300.cdl
-	hardware
-        description "
-           The VR4300 variant HAL package provides generic support
-           for this processor architecture. It is also necessary to
-           select a specific target platform HAL package."
-}
-package CYGPKG_HAL_MIPS_VR4300_VRC4373 {
-	alias		{ "NEC VRC4373 board" hal_vrc4373 vrc4373_hal }
-	directory	hal/mips/vrc4373
-	script		hal_mips_vr4300_vrc4373.cdl
-	hardware
-	description "
-           The VRC4373 HAL package should be used when targetting the
-           actual hardware."
-}
-
-package CYGPKG_HAL_MIPS_VR4300_VRC4375 {
-	alias		{ "NEC VRC4375 board" hal_vrc4375 vrc4375_hal }
-	directory	hal/mips/vrc4375
-	script		hal_mips_vr4300_vrc4375.cdl
-	hardware
-	description "
-           The VRC4375 HAL package should be used when targetting the
-           actual hardware."
-}
-
-package CYGPKG_HAL_MIPS_VR4300_VRC437X {
-	alias		{ "NEC VRC437X support" hal_vrc437x vrc437x_hal }
-	directory	hal/mips/vrc437x
-	script		hal_mips_vr4300_vrc437x.cdl
-	hardware
-	description "
-           The VRC437X HAL package should be used when targetting harware
-           that contains either a VRC437X companion chip."
-}
-
-package CYGPKG_HAL_MIPS_UPD985XX {
-	alias		{ "upd985xx chip HAL" hal_upd985xx upd985xx_hal upd985xx_arch_hal }
-	directory	hal/mips/upd985xx/
-	script		hal_mips_upd985xx.cdl
-	hardware
-        description "
-           The UPD985XX variant HAL package provides generic support
-           for this NEC system-on-chip processor architecture, uPD985xx.
-	   It is also necessary to
-           select a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_MIPS_IDT32334 {
-	alias		{ "MIPS IDT32334 variant HAL" hal_idt32334 idt32334_hal idt32334_arch_hal }
-	directory	hal/mips/idt32334
-	script		hal_mips_idt32334.cdl
-	hardware
-        description "
-           The IDT32334 variant HAL package provides generic support
-           for platforms based on this variant. It is also necessary to
-           select a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_MIPS_IDT32334_REFIDT334 {
-	alias		{ "MIPS IDT79S334A reference platform" hal_idt32334_refIDT334 idt32334_refIDT334_hal }
-	directory	hal/mips/idt79s334a
-	script		hal_mips_idt32334_refidt334.cdl
-	hardware
-	description "
-           The REFIDT334 HAL package should be used when targetting the
-           actual hardware."
-}
-
-# --------------------------------------------------------------------------
-# MN10300 packages
-
-package CYGPKG_HAL_MN10300 {
-	alias		{ "MN10300 common HAL" hal_mn10300 mn10300_hal mn10300_arch_hal }
-	directory	hal/mn10300/arch
-	script		hal_mn10300.cdl
-	hardware
-	description "
-           The MN10300 architecture HAL package provides generic
-           support for this processor architecture. It is also
-           necessary to select a specific target platform HAL
-           package."
-}
-
-package CYGPKG_HAL_MN10300_AM31 {
-	alias		{ "MN10300 AM31 variant HAL" hal_mn10300_am31 mn10300_am31_hal }
-	directory	hal/mn10300/am31
-	script		hal_mn10300_am31.cdl
-	hardware
-        description "
-           The MN10300 AM31 variant HAL package provides generic
-           support for this processor architecture. It is also
-           necessary to select a specific target platform HAL
-           package."
-}
-
-package CYGPKG_HAL_MN10300_AM31_SIM {
-	alias		{ "MN10300 simulator" hal_mn10300_sim mn10300_sim_hal }
-	directory	hal/mn10300/sim
-	script		hal_mn10300_am31_sim.cdl
-	hardware
-        description "
-           The minimal simulator HAL package is provided for use when
-           only a simple simulation of the processor architecture is
-           desired, as opposed to detailed simulation of any specific
-           board. In particular it is not possible to simulate any of
-           the I/O devices, so device drivers cannot be used."
-}
-
-package CYGPKG_HAL_MN10300_AM31_STDEVAL1 {
-	alias		{ "Matsushita stdeval1 board" hal_mn10300_stdeval1 mn10300_stdeval1_hal }
-	directory	hal/mn10300/stdeval1
-	script		hal_mn10300_am31_stdeval1.cdl
-	hardware
-        description "
-           The stdeval1 HAL package should be used when targetting the
-           actual hardware. The same package can also be used when
-           running on the full MN10300 simulator, since this provides
-           an accurate simulation of the full hardware including I/O
-           devices."
-}
-package CYGPKG_HAL_MN10300_AM33 {
-	alias		{ "MN10300 AM33 variant HAL" hal_mn10300_am33 mn10300_am33_hal }
-	directory	hal/mn10300/am33
-	script		hal_mn10300_am33.cdl
-	hardware
-        description "
-           The MN10300 AM33 variant HAL package provides generic
-           support for this processor architecture. It is also
-           necessary to select a specific target platform HAL
-           package."
-}
-
-package CYGPKG_HAL_MN10300_AM33_STB {
-	alias		{ "Matsushita STB board" hal_mn10300_am33_stb mn10300_am33_stb_hal }
-	directory	hal/mn10300/stb
-	script		hal_mn10300_am33_stb.cdl
-	hardware
-        description "
-           The STB HAL package should be used when targetting the
-           actual hardware for the AM33 STB evaluation board."
-}
-
-package CYGPKG_HAL_MN10300_AM33_ASB {
-	alias		{ "Matsushita ASB2303 board" hal_mn10300_am33_asb mn10300_am33_asb_hal }
-	directory	hal/mn10300/asb
-	script		hal_mn10300_am33_asb.cdl
-	hardware
-        description "
-           The ASB2303 HAL package should be used when targetting the
-           actual hardware for the AM33 ASB2303 evaluation board."
-}
-
-package CYGPKG_HAL_MN10300_AM33_ASB2305 {
-	alias		{ "Matsushita ASB2305 board" hal_mn10300_am33_asb2305
-			  mn10300_am33_asb2305_hal }
-	directory	hal/mn10300/asb2305
-	script		hal_mn10300_am33_asb2305.cdl
-	hardware
-        description "
-           The ASB2305 HAL package should be used when targetting the
-           actual hardware for the AM33 ASB2305 evaluation board."
-}
-
-# --------------------------------------------------------------------------
-# NEC packages
-package CYGPKG_HAL_V85X {
-	alias		{ "NEC V85x common HAL" hal_v85x nec_arch_hal }
-	directory	hal/v85x/arch
-	script		hal_v85x.cdl
-	hardware
-	description "
-The NEC V85x architecture HAL package provides generic support for this
-processor architecture. It is also necessary to select a specific
-target platform HAL package."
-}
-
-package CYGPKG_HAL_V85X_V850 {
-	alias		{ "NEC V850 variant HAL" hal_v85x_v850 nec_v850_hal }
-	directory	hal/v85x/v850
-	script		hal_v85x_v850.cdl
-	hardware
-        description "
-The V850 HAL package provides the support needed to run eCos on a NEC V850
-processor."
-}
-
-package CYGPKG_HAL_V85X_V850_CEB {
-	alias		{ "Cosmo CEB-V850/SA1 board" hal_v85x_v850_ceb nec_v850_ceb_hal }
-	directory	hal/v85x/ceb_v850
-	script		hal_v85x_ceb_v850.cdl
-	hardware
-        description "
-The CEB-V850/SA1 HAL package provides the support needed to run eCos on a Cosmo CEB-V850/SA1
-evaluation board."
-}
-
-# --------------------------------------------------------------------------
-# m68k packages
-
-package CYGPKG_HAL_M68K {
-    alias       { "M68K common HAL" hal_m68k m68k_hal m68k_arch_hal }
-    directory   hal/m68k/arch
-    script      hal_m68k.cdl
-    hardware
-
-    description   "The M68K architecture HAL package provides generic
-                   support for this architecture."
-}
-
-package CYGPKG_HAL_M68K_MCFxxxx {
-    alias       { "M68K/ColdFire variant HAL" hal_m68k_mcfxxxx m68k_mcfxxxx_hal }
-    directory   hal/m68k/mcf52xx/var
-    script      hal_m68k_mcf52xx.cdl
-    hardware
-
-    description   "The M68k/ColdFire variant  HAL  package provides generic
-                  support for Freescale ColdFire  cores."
-}
-
-package CYGPKG_HAL_M68K_MCF5272 {
-    alias       { "mcf5272 68k/ColdFire processor variant HAL" hal_m68k_mcf5272 m68k_mcf5272_hal }
-    directory   hal/m68k/mcf52xx/mcf5272/proc
-    script      hal_m68k_mcf5272.cdl
-    hardware
-
-    description   "The mcf5272 processor variant HAL package provides generic
-                   support for this processor."
-}
-
-package CYGPKG_HAL_M68K_M5272C3 {
-    alias       { "Freescale m5272c3 evaluation board platform HAL"
-        hal_m68k_m5272c3 m68k_m5272c3_hal }
-    directory   hal/m68k/mcf52xx/mcf5272/m5272c3
-    script      hal_m68k_m5272c3.cdl
-    hardware
-
-    description   "The Freescale  m5272c3 evaluation  board platform  HAL
-                  package should be used when targeting the actual  hardware
-                  for the Freescale m5272c3 evaluation board platform."
-}
-
-package CYGPKG_DEVS_ETH_MCFxxxx {
-    alias       { "MCFxxxx ethernet driver" devs_eth_mcfxxxx mcfxxxx_eth_driver }
-    hardware
-    directory   devs/eth/m68k/mcf5272
-    script      mcf5272_eth.cdl
-    description "
-            This packages provides an ethernet driver for the on-chip
-        device provided by MCFxxxx ColdFire processors."
-}
-
-package CYGPKG_DEVS_SERIAL_MCFxxxx {
-    alias       { "MCFxxxx serial device driver" devs_serial_mcfxxxx mcfxxxx_serial_driver }
-    hardware
-    directory   devs/serial/m68k/mcf52xx
-    script      ser_mcf52xx.cdl
-    description "
-            This package provides serial drivers for the on-chip UART's
-            provided by MCFxxxx ColdFire processors."
-}
-
-# --------------------------------------------------------------------------
-# CalmRISC16 packages
-
-package CYGPKG_HAL_CALM16 {
-	alias		{ "CalmRISC16 common HAL" hal_calm16 calm16_hal calm16_arch_hal }
-	directory	hal/calmrisc16/arch/
-	script		hal_calm16.cdl
-	hardware
-	description "
-    	    The CalmRISC16 architecture HAL package provides generic support
-    	    for this processor architecture. It is also necessary to
-    	    select a CPU variant and a specific target platform HAL
-    	    package."
-}
-
-package CYGPKG_HAL_CALM16_CORE {
-	alias		{ "CalmRISC16 Core HAL" hal_calm16core calm16core_hal calm16core_arch_hal }
-	directory	hal/calmrisc16/core/
-	script		hal_calm16_core.cdl
-	hardware
-        description "
-           The CalmRISC16 Core architecture HAL package provides generic support
-           for this processor architecture. It is also necessary to
-           select a specific target platform HAL package."
-}
-
-package CYGPKG_HAL_CALM16_CEB {
-	alias		{ "CalmRISC16 Core eval board" hal_calm16_ceb calm16_ceb_hal }
-	directory	hal/calmrisc16/ceb
-	script		hal_calm16_ceb.cdl
-	hardware
-	description "
-           The CalmRISC16 HAL package should be used when targetting the
-           actual hardware. "
-}
-# --------------------------------------------------------------------------
-# CalmRISC32 packages
-
-package CYGPKG_HAL_CALM32 {
-	alias		{ "CalmRISC32 common HAL" hal_calm32 calm32_hal calm32_arch_hal }
-	directory	hal/calmrisc32/arch/
-	script		hal_calm32.cdl
-	hardware
-	description "
-    	    The CalmRISC32 architecture HAL package provides generic support
-    	    for this processor architecture. It is also necessary to
-    	    select a CPU variant and a specific target platform HAL
-    	    package."
-}
-
-package CYGPKG_HAL_CALM32_CORE {
-	alias		{ "CalmRISC32 Core HAL" hal_calm32core calm32core_hal calm32core_arch_hal }
-	directory	hal/calmrisc32/core/
-	script		hal_calm32_core.cdl
-	hardware
-}
-
-package CYGPKG_HAL_CALM32_CEB {
-	alias		{ "CalmRISC32 Core eval board" hal_calm32_ceb calm32_ceb_hal hal_commo }
-	directory	hal/calmrisc32/ceb
-	script		hal_calm32_ceb.cdl
-	hardware
-	description "
-           The CalmRISC32 HAL package should be used when targetting the
-           actual hardware. "
-}
-
-
-# --------------------------------------------------------------------------
-# FUJITSU packages
-package CYGPKG_HAL_FRV {
-	alias		{ "FR-V (Fujitsu) common HAL" hal_frv frv_hal frv_arch_hal }
-	directory	hal/frv/arch
-	script		hal_frv.cdl
-	hardware
-	description "
-The FRV architecture HAL package provides generic support for this
-processor architecture. It is also necessary to select a specific
-target platform HAL package."
-}
-
-package CYGPKG_HAL_FRV_FRV400 {
-	alias		{ "FUJITSU development board (FR-V 400)" hal_frv_frv400 frv_frv400_hal }
-	directory	hal/frv/frv400
-	script		hal_frv_frv400.cdl
-	hardware
-        description "
-The FRV400 HAL package provides the support needed to run eCos on a FUJITSU
-MB93091 (FR-V 400) eval board."
-}
-
-package CYGPKG_HAL_FRV_MB93091 {
-	alias		{ "FUJITSU development board (FR-V)" mb93091 }
-	directory	hal/frv/mb93091
-	script		hal_frv_mb93091.cdl
-	hardware
-        description "
-The FRV Generic HAL package provides the support needed to run eCos on 
-various FUJITSU FR-V eval boards."
-}
-
-package CYGPKG_HAL_FRV_MB93093 {
-	alias		{ "FUJITSU MB93093-PD00 Portable Development Kit (FR-V)" mb93093 }
-	directory	hal/frv/mb93093
-	script		hal_frv_mb93093.cdl
-	hardware
-        description "
-The MB93093 HAL package provides the support needed to run eCos on 
-the Fujitsu MB93093-PD00 Portable Development Kit board."
-}
-
-package CYGPKG_DEVS_ETH_FRV_FRV400 {
-	alias 		{ "Fujitsu FR-V 400 with 82559 ethernet driver"
-			   devs_eth_frv_frv400 frv400_eth_driver }
-	hardware
-	directory	devs/eth/frv/frv400
-	script		frv400_eth_drivers.cdl
-        description     "Ethernet driver for Fujitsu FR-V 400 with Intel
-                         i82559 ethernet interfaces."
-}
-
-package CYGPKG_DEVS_ETH_FRV_PDK403 {
-	alias 		{ "Fujitsu MB93093-PD00 with AXL88796 ethernet driver"
-			   devs_eth_frv_pdk403 pdk403_eth_driver }
-	hardware
-	directory	devs/eth/frv/pdk403
-	script		pdk403_eth_drivers.cdl
-        description     "Ethernet driver for Fujitsu MB93093-PD00 Portable
-			 Demonstration Kit with AXL88796 Ethernet device"
-}
-
-package CYGPKG_DEVS_ETH_FRV_CB70 {
-	alias 		{ "Fujitsu FR-V 405 with DM9000 ethernet driver"
-			   devs_eth_frv_cb70 cb70_eth_driver }
-	hardware
-	directory	devs/eth/frv/cb70
-	script		cb70_eth_driver.cdl
-        description     "Ethernet driver for Fujitsu FR-V 405 CB70 CPU card with
-                         Davicom DM9000 ethernet interface."
-}
-
-# FR30 packages
-
-package CYGPKG_HAL_FR30 {
-    alias       { "Fujitsu FR30 architecture (FR30/FR50/FR60)" hal_fr30
-                    fr30_hal }
-    directory   hal/fr30/arch
-    script      hal_fr30.cdl
-    hardware
-        description "
-The Fujitsu FR30 HAL package provides the generic support needed to run eCos on 
-a FR30 based microcontroller. FR50 and FR60 architectures should also select
-this one."
-}
-
-package CYGPKG_HAL_FR30_MB91301 {
-    alias       { "Fujitsu MB31301 variant (FR60)" hal_fr30_mb91301
-                    fr30_mb91301_hal }
-    directory   hal/fr30/mb91301
-    script      hal_fr30_mb91301.cdl
-    hardware
-        description "
-The Fujitsu MB91301 HAL package provides the support needed to run eCos on
-the Fujitsu Starterkit MB91302 Evaluation board. It contains a MB91302A
-Microcontroller from Fujitsu with a FR60 Core. So FR30 support is also needed."
-}
-
-package CYGPKG_HAL_FR30_MB91301_SKMB91302 {
-    alias       { "Fujitsu Starterkit MB91302 board" hal_fr30_skmb91302
-                    fr30_skmb91302_hal }
-    directory   hal/fr30/skmb91302
-    script      hal_fr30_skmb91302.cdl
-    hardware
-        description "
-The SKMB91302 HAL package provides the support needed to run eCos on
-the Fujitsu Starterkit MB91302 board. It contains a MB91302
-Microcontroller from Fujitsu with a FR60 Core. So FR30 support is needed."
-}
-
-package CYGPKG_DEVS_FLASH_FR30_SKMB91302 {
-    alias       { "Fujitsu Starterkit MB91302 FLASH memory support" flash_skmb91302 }
-    directory   devs/flash/fr30/skmb91302
-    script      flash_skmb91302.cdl
-    hardware
-        description "
-           This package contains hardware support for FLASH memory
-       on the Fujitsu Starterkit MB91302 platform.
-        (AMD 29DL640E-90 Device)"
-}
-
-package CYGPKG_DEVS_ETH_ARM_AT91 {
-        alias           { "AT91 Ethernet driver" at91_eth_driver }
-        directory       devs/eth/arm/at91
-        script          at91_eth.cdl
-        hardware
-        description     "Ethernet driver for the AT91 family of chips"
-}
-
-package CYGPKG_DEVS_ETH_ARM_LPC2XXX {
-        alias           { "LPC2xxx Ethernet driver" lpc2xxx_eth_driver }
-        directory       devs/eth/arm/lpc2xxx
-        script          lpc2xxx_eth.cdl
-        hardware
-        description     "Ethernet driver for the LPC2xxx family of chips"
-}
-
-
-# --------------------------------------------------------------------------
-
-# ==========================================================================
-
-# --------------------------------------------------------------------------
-# FRV targets
-target frv400 {
-	alias { "Fujitsu development board (FR-V 400)" FRV400 }
-	packages { CYGPKG_HAL_FRV
-                   CYGPKG_HAL_FRV_FRV400
-                   CYGPKG_IO_PCI
-                   CYGPKG_DEVS_ETH_FRV_FRV400
-                   CYGPKG_DEVS_ETH_NS_DP83902A
-                   CYGPKG_DEVS_FLASH_FRV_FRV400
-                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-        }
-        description "
-The frv400 target provides the packages needed to run eCos on a Fujistu
-development board (FR-V 400)."
-}
-
-target mb93091 {
-	alias { "Fujitsu MB93091 development board (FR-V 4xx,5xx)" MB93091 }
-	packages { CYGPKG_HAL_FRV
-                   CYGPKG_HAL_FRV_MB93091
-                   CYGPKG_IO_PCI
-                   CYGPKG_DEVS_ETH_FRV_FRV400
-                   CYGPKG_DEVS_ETH_NS_DP83902A
-                   CYGPKG_DEVS_ETH_FRV_CB70
-                   CYGPKG_DEVS_ETH_DAVICOM_DM9000
-                   CYGPKG_DEVS_FLASH_FRV_FRV400
-                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-        }
-        description "
-The MB93091 target provides the packages needed to run eCos on a Fujitsu
-MB93091 development board (FR-V 400 etc.)."
-}
-
-target mb93093 {
-	alias { "Fujitsu development board (FR-V 400)" MB93093 }
-	packages { CYGPKG_HAL_FRV
-                   CYGPKG_HAL_FRV_MB93093
-                   CYGPKG_DEVS_ETH_FRV_PDK403
-                   CYGPKG_DEVS_ETH_NS_DP83902A
-                   CYGPKG_DEVS_FLASH_FRV_PDK403
-                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-        }
-        description "
-The MB93093 target provides the packages needed to run eCos on a Fujitsu
-MB93090-PD00 Portable Development Kit."
-}
-
-# FR30 Targets
-
-target skmb91302 {
-    alias { "Fujitsu Starterkit MB91302 board" }
-    packages { CYGPKG_HAL_FR30
-                   CYGPKG_HAL_FR30_MB91301
-                   CYGPKG_HAL_FR30_MB91301_SKMB91302
-                   CYGPKG_DEVS_FLASH_FR30_SKMB91302
-                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-}
-        description "
-The Starterkit MB91302 HAL package provides the support needed to run
-eCos on the Fujitsu Starterkit MB91302 board. It contains a MB91302
-Microcontroller from Fujitsu with a FR60 Core. So FR30 support is
-included."
-}
-
-# --------------------------------------------------------------------------
-# ARM Targets
-
-target pid {
-	alias { "ARM development board (PID)" PID }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_PID
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-	           CYGPKG_IO_SERIAL_ARM_PID
-                   CYGPKG_DEVS_FLASH_ARM_PID
-                   CYGPKG_DEVS_FLASH_ATMEL_AT29CXXXX
-        }
-        description "
-The pid target provides the packages needed to run eCos on an ARM
-development board (formerly known as PID)."
-}
-
-target aeb {
-	alias { "ARM evaluation board (AEB-1)" aeb1 }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_AEB
-	           CYGPKG_IO_SERIAL_ARM_AEB
-                   CYGPKG_DEVICES_WATCHDOG_ARM_AEB
-        }
-        description "
-The aeb target provides the packages needed to run eCos on an ARM
-evaluation board (AEB-1)."
-}
-
-target e7t {
-	alias { "ARM Evaluator7T board (AEB-2)" aeb2 }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_E7T
-                   CYGPKG_DEVS_FLASH_ARM_E7T
-                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                   CYGPKG_DEVS_FLASH_SST_39VFXXX
-	           CYGPKG_IO_SERIAL_ARM_E7T
-                   CYGPKG_DEVS_ETH_ARM_KS32C5000
-        }
-        description "
- The e7t target provides the packages needed to run eCos on an ARM
- Evaluator7T board (aka AEB-2)."
-}
-
-target integrator_arm7 {
-        alias { "ARM INTEGRATOR development board w/ ARM7TDMI" integrator }
-        packages { CYGPKG_HAL_ARM 
-                   CYGPKG_HAL_ARM_INTEGRATOR 
-                   CYGPKG_IO_PCI
-                   CYGPKG_IO_SERIAL_ARM_INTEGRATOR
-		   CYGPKG_DEVS_FLASH_INTEL_28FXXX
-                   CYGPKG_DEVS_FLASH_ARM_INTEGRATOR
-		   CYGPKG_DEVS_ETH_INTEL_I82559
-                   CYGPKG_DEVS_ETH_ARM_INTEGRATOR
-        }
-        description "
-        The INTEGRATOR_ARM7 target provides the packages needed to 
-        run eCos on an ARM development board with an ARM7TDMI core
-        module installed."
-}
-
-target integrator_arm9 {
-        alias { "ARM INTEGRATOR development board w/ ARM966" }
-        packages { CYGPKG_HAL_ARM
-		   CYGPKG_HAL_ARM_ARM9
-                   CYGPKG_HAL_ARM_INTEGRATOR 
-                   CYGPKG_IO_PCI
-                   CYGPKG_IO_SERIAL_ARM_INTEGRATOR
-		   CYGPKG_DEVS_FLASH_INTEL_28FXXX
-                   CYGPKG_DEVS_FLASH_ARM_INTEGRATOR
-		   CYGPKG_DEVS_ETH_INTEL_I82559
-                   CYGPKG_DEVS_ETH_ARM_INTEGRATOR
-        }
-        description "
-        The INTEGRATOR_ARM9 target provides the packages needed to 
-        run eCos on an ARM development board with an ARM966 core
-        module installed."
-}
-
-target eb40 {
-	alias { "Atmel evaluation board (EB40)" at91 at91_eb40 }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_AT91
-                   CYGPKG_HAL_ARM_AT91_EB40
-                   CYGPKG_DEVS_FLASH_EB40
-                   CYGPKG_DEVS_FLASH_ATMEL_AT29CXXXX
-                   CYGPKG_IO_SERIAL_ARM_AT91
-                   CYGPKG_DEVICES_WATCHDOG_ARM_AT91
-        }
-        description "
-        The eb40 target provides the packages needed to run eCos on an Atmel
-        evaluation board (EB40)."
-}
-
-target jtst {
-	alias { "Atmel Diopsis evaluation board (jtst)" at91_jtst }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_AT91
-                   CYGPKG_HAL_ARM_AT91_JTST
-                   CYGPKG_IO_SERIAL_ARM_AT91
-                   CYGPKG_DEVS_FLASH_JTST
-                   CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX
-		   CYGPKG_DEVICES_WATCHDOG_ARM_AT91
-        }
-        description "
-        The jtst target provides the packages needed to run eCos on an Atmel
-        Diospsis evaluation board (jtst)."
-}
-
-target at91sam7sek {
-	alias { "Atmel AT91SAM7SEK evaluation board" at91_at91sam7sek }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_AT91
-                   CYGPKG_HAL_ARM_AT91SAM7
-                   CYGPKG_HAL_ARM_AT91SAM7SEK
-                   CYGPKG_IO_SERIAL_ARM_AT91
-                   CYGPKG_DEVS_FLASH_AT91
-                   CYGPKG_IO_SPI
-                   CYGPKG_DEVS_SPI_ARM_AT91
-                   CYGPKG_DEVICES_WATCHDOG_ARM_AT91WDTC
-                   CYGPKG_IO_USB
-                   CYGPKG_IO_USB_SLAVE
-                   CYGPKG_DEVS_USB_AT91
-        }
-        description "
-        The at91sam7sek target provides the packages needed to run eCos on an 
-        Atmel AT91SAM7S-EK evaluation board."
-}
-
-target at91sam7xek {
-	alias { "Atmel AT91SAM7XEK evaluation board" at91_at91sam7xek }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_AT91
-                   CYGPKG_HAL_ARM_AT91SAM7
-                   CYGPKG_HAL_ARM_AT91SAM7XEK
-                   CYGPKG_IO_SERIAL_ARM_AT91
-                   CYGPKG_DEVS_FLASH_AT91
-                   CYGPKG_IO_SPI
-                   CYGPKG_DEVS_SPI_ARM_AT91
-                   CYGPKG_DEVICES_WATCHDOG_ARM_AT91WDTC
-                   CYGPKG_IO_USB
-                   CYGPKG_IO_USB_SLAVE
-                   CYGPKG_DEVS_USB_AT91
-                   CYGPKG_DEVS_ETH_PHY
-                   CYGPKG_DEVS_ETH_ARM_AT91
-        }
-        description "
-        The at91sam7xek target provides the packages needed to run eCos on an 
-        Atmel AT91SAM7X-EK evaluation board."
-}
-
-target sam7ex256 {
-	alias { "Olimex SAM7-EX256 evaluation board" at91_sam7ex256 }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_AT91
-                   CYGPKG_HAL_ARM_AT91SAM7
-                   CYGPKG_HAL_ARM_SAM7EX256
-                   CYGPKG_IO_SERIAL_ARM_AT91
-                   CYGPKG_DEVS_FLASH_AT91
-                   CYGPKG_IO_SPI
-                   CYGPKG_DEVS_SPI_ARM_AT91
-                   CYGPKG_DEVICES_WATCHDOG_ARM_AT91WDTC
-                   CYGPKG_IO_USB
-                   CYGPKG_IO_USB_SLAVE
-                   CYGPKG_DEVS_USB_AT91
-                   CYGPKG_DEVS_ETH_PHY
-                   CYGPKG_DEVS_ETH_ARM_AT91
-                   CYGPKG_DEVS_CAN_AT91SAM7
-        }
-        description "
-        The SAM7EX256 target provides the packages needed to run eCos on an 
-        Olimex SAM7-EX256 evaluation board."
-}
-
-target eb40a {
-	alias { "Atmel evaluation board (EB40A)" at91_eb40a }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_AT91
-                   CYGPKG_HAL_ARM_AT91_EB40A
-                   CYGPKG_DEVS_FLASH_EB40A
-                   CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX
-                   CYGPKG_IO_SERIAL_ARM_AT91
-                   CYGPKG_DEVICES_WATCHDOG_ARM_AT91
-        }
-        description "
-	The eb40a target provides the packages needed to run eCos on an Atmel
-	evaluation board (EB40A)."
-}
-
-target eb42 {
-	alias { "Atmel evaluation board (EB42)" at91_eb42 }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_AT91
-                   CYGPKG_HAL_ARM_AT91_EB42
-                   CYGPKG_DEVS_FLASH_EB42
-                   CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX
-                   CYGPKG_IO_SERIAL_ARM_AT91
-        }
-        description "
-	The eb42 target provides the packages needed to run eCos on an Atmel
-	evaluation board (EB42)."
-}
-
-target eb55 {
-	alias { "Atmel evaluation board (EB55)" at91_eb55 }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_AT91
-                   CYGPKG_HAL_ARM_AT91_EB55
-                   CYGPKG_DEVS_FLASH_EB55
-                   CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX
-                   CYGPKG_DEVS_FLASH_ATMEL_DATAFLASH
-                   CYGPKG_IO_SERIAL_ARM_AT91
-                   CYGPKG_IO_SPI
-                   CYGPKG_DEVS_SPI_ARM_EB55
-                   CYGPKG_DEVS_SPI_ARM_AT91
-                   CYGPKG_DEVICES_WATCHDOG_ARM_AT91
-        }
-        description "
-	The eb55 target provides the packages needed to run eCos on an Atmel
-	evaluation board (EB55)."
-}
-
-target phycore {
-	alias { "PHYTEC evaluation board (phyCORE AT91M55800A)" at91_phycore }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_AT91
-                   CYGPKG_HAL_ARM_AT91_PHYCORE
-                   CYGPKG_DEVS_FLASH_PHYCORE
-                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                   CYGPKG_IO_SERIAL_ARM_AT91
-                   CYGPKG_DEVICES_WATCHDOG_ARM_AT91
-        }
-        description "
-	The phyCORE AT91M55800A target provides the packages needed to 
-        run eCos on an PHYTEC evaluation board (phycore AT91M55800A based 
-        on HD200)."
-}
-
-target mcb2100 {
-        alias { "Keil evaluation board MCB2100" }
-        packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_LPC2XXX
-                   CYGPKG_HAL_ARM_LPC2XXX_MCB2100
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-                   CYGPKG_IO_SERIAL_ARM_LPC2XXX
-                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
-        }
-        description "
-        The mcb2100 target provides the packages needed to run eCos on the
-        MCB2100 evaluation board from Keil."
-}
-
-target p2106 {
-        alias { "Olimex evaluation board LPC-P2106" }
-        packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_LPC2XXX
-                   CYGPKG_HAL_ARM_LPC2XXX_P2106
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-                   CYGPKG_IO_SERIAL_ARM_LPC2XXX
-                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
-        }
-        description "
-        The p2106 target provides the packages needed to run eCos on the
-        LPC-P2106 evaluation board from Olimex."
-}
-
-target lpcmt {
-	alias { "Olimex evaluation board LPC-LPCMT" }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_LPC2XXX
-                   CYGPKG_HAL_ARM_LPC2XXX_LPCMT
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-                   CYGPKG_IO_SERIAL_ARM_LPC2XXX
-                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
-        }
-        description "
-        The lpcmt target provides the packages needed to run eCos on the
-        LPC-LPCMT evaluation board from Olimex."
-}
-
-target phycore229x {
-        alias { "phyCORE-LPC2294/92 development board HAL" }
-        packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_LPC2XXX
-                   CYGPKG_HAL_ARM_LPC2XXX_PHYCORE229X 
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-                   CYGPKG_IO_SERIAL_ARM_LPC2XXX
-                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
-                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                   CYGPKG_DEVS_FLASH_PHYCORE229X
-                   CYGPKG_DEVS_ETH_ARM_PHYCORE229X
-                   CYGPKG_DEVS_ETH_SMSC_LAN91CXX
-                   CYGPKG_DEVS_CAN_LPC2XXX
-        }
-        description "
-            The phyCORE-LPC229x HAL package provides the support
-            needed to run eCos on a Phytec phyCORE-LPC2294/2
-            development board."
-}
-
-target ea2468 {
-        alias { "Embedded Artists LPC2468 OEM board HAL" }
-        packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_LPC24XX
-                   CYGPKG_HAL_ARM_LPC24XX_EA2468 
-                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX                        
-                   CYGPKG_DEVICES_WALLCLOCK_ARM_LPC2XXX
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-                   CYGPKG_IO_SERIAL_ARM_LPC24XX
-                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
-                   CYGPKG_DEVS_CAN_LPC2XXX
-                   CYGPKG_DEVS_FLASH_EA2468
-                   CYGPKG_DEVS_FLASH_SST_39VFXXX
-                   CYGPKG_DEVS_ETH_PHY
-                   CYGPKG_DEVS_ETH_ARM_LPC2XXX
-                   CYGPKG_IO_I2C
-                   CYGPKG_DEVS_I2C_ARM_LPC2XXX     
-                   CYGPKG_DEVS_ADC_ARM_LPC24XX
-                   CYGPKG_DEVS_NAND_SAMSUNG_K9
-        }
-        description "
-            The Embedded Artists LPC2468 HAL package provides the support
-            needed to run eCos on an Embedded Artists LPC2468 OEM board."
-}
-
-target olpch2294 {
-        alias { "Olimex LPC-H2294 header board" }
-        packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_LPC2XXX
-                   CYGPKG_HAL_ARM_LPC2XXX_OLPCH2294
-                   CYGPKG_DEVS_FLASH_STRATA_V2
-                   CYGPKG_DEVS_FLASH_ARM_OLPCX2294_V2
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-                   CYGPKG_IO_SERIAL_ARM_LPC2XXX
-                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
-        }
-        description "
-            The olpch2294 target provides the packages needed to run
-            eCos on Olimex LPC-H2294 header board."
-}
-
-
-target olpce2294 {
-        alias { "Olimex LPC-E2294 development board" }
-        packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_LPC2XXX
-                   CYGPKG_HAL_ARM_LPC2XXX_OLPCE2294
-                   CYGPKG_DEVS_FLASH_STRATA_V2
-                   CYGPKG_DEVS_FLASH_ARM_OLPCX2294_V2
-                   CYGPKG_DEVS_ETH_CL_CS8900A
-                   CYGPKG_DEVS_ETH_ARM_OLPCE2294
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-                   CYGPKG_IO_SERIAL_ARM_LPC2XXX
-                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
-        }
-        description "
-            The olpce2294 target provides the packages needed to run
-            eCos on Olimex LPC-E2294 development board."
-}
-
-target olpcl2294 {
-        alias { "Olimex LPC-L2294-1MB development board" }
-        packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_LPC2XXX
-                   CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294
-                   CYGPKG_DEVS_FLASH_STRATA_V2
-                   CYGPKG_DEVS_FLASH_ARM_OLPCX2294_V2
-                   CYGPKG_DEVS_ETH_CL_CS8900A
-                   CYGPKG_DEVS_ETH_ARM_OLPCL2294
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-                   CYGPKG_IO_SERIAL_ARM_LPC2XXX
-                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
-        }
-        description "
-            The olpcl2294 target provides the packages needed to run
-            eCos on Olimex LPC-L2294-1MB development board."
-}
-
-target mace1 {
-	alias { "MACE1 - a MAC7100 evaluation board" mac7100_mace1 }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_MAC7100
-                   CYGPKG_HAL_ARM_MAC7100_MACE1
-                   CYGPKG_IO_SERIAL_FREESCALE_ESCI_H
-                   CYGPKG_IO_SERIAL_FREESCALE_ESCI
-        }
-        description "
-            The mace1 target provides the packages needed to run eCos
-            on MAC7100 evaluation board (MACE1).  "
-}
-
-target mac7100evb {
-	alias { "MAC7100EVB - Freescale MAC7100 evaluation board" mac7100_mac7100evb }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_MAC7100
-                   CYGPKG_HAL_ARM_MAC7100_MAC7100EVB
-                   CYGPKG_IO_SERIAL_FREESCALE_ESCI_H
-                   CYGPKG_IO_SERIAL_FREESCALE_ESCI
-        }
-        description "
-            The MAC7100EVB target provides the packages needed to run eCos
-            on Freescale MAC7100EVB evaluation board.  "
-}
-
-target ebsa285 {
-	alias { "Intel EBSA285 StrongARM board" ebsa }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_EBSA285
-                   CYGPKG_IO_PCI
-		   CYGPKG_DEVS_ETH_ARM_EBSA285
-                   CYGPKG_DEVS_ETH_INTEL_I82559
-		   CYGPKG_IO_SERIAL_ARM_EBSA285
-                   CYGPKG_DEVICES_WATCHDOG_ARM_EBSA285
-		   CYGPKG_DEVS_FLASH_EBSA285
-        }
-        description "
-        The ebsa285 target provides the packages needed to run
-        eCos on an Intel EBSA285 StrongARM board."
-}
-
-
-target aaed2000 {
-	alias { "Agilent AAED2000 unit" aaed }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_ARM9
-                   CYGPKG_HAL_ARM_ARM9_AAED2000
-                   CYGPKG_DEVS_FLASH_ARM_AAED2000
-                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                   CYGPKG_DEVS_ETH_CL_CS8900A
-                   CYGPKG_DEVS_ETH_ARM_AAED2000
-                   CYGPKG_DEVS_KBD_AAED2000
-                   CYGPKG_DEVS_TOUCH_AAED2000
-        }
-        description "
-        The AAED2000 target provides the packages needed to run
-        eCos on an Agilent AAED2000 board."
-}
-
-target excalibur_arm9 {
-	alias { "Altera ARM9/Excalibur board" epxa10 }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_ARM9
-                   CYGPKG_HAL_ARM_ARM9_EXCALIBUR
-                   CYGPKG_DEVS_FLASH_INTEL_28FXXX
-                   CYGPKG_DEVS_FLASH_ARM_EXCALIBUR
-        }
-        description "
-        The Excalibur target provides the packages needed to run
-        eCos on an Altera Excalibur board."
-}
-
-target smdk2410 {
-        alias { "Samsung ARM9/SMDK2410 development board" s3c2410x }
-        packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_ARM9
-                   CYGPKG_HAL_ARM_ARM9_SMDK2410
-                   CYGPKG_IO_SERIAL_ARM_SMDK2410
-                   CYGPKG_DEVS_FLASH_ARM_SMDK2410
-                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-        }
-        description "
-        The SMDK2410 target provides the packages needed to run eCos on 
-        Samsung S3c2410x (ARM920T) based development boards (SMDK2410)."
-}
-
-target innovator {
-	alias { "Innovator (ARM) board" }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_ARM9
-                   CYGPKG_HAL_ARM_ARM9_INNOVATOR
-                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                   CYGPKG_DEVS_FLASH_ARM_INNOVATOR
-		   CYGPKG_DEVS_ETH_SMSC_LAN91CXX
-		   CYGPKG_DEVS_ETH_ARM_INNOVATOR
-        }
-        description "
-        The Innovator HAL package provides the support needed to run
-        RedBoot on the ARM processor of the Innovator.
-	
-	NOTE: Full support for eCos is not provided yet.  This HAL
-	contains only the minimum amount necessary to run RedBoot
-	on the Innovator.  In particular, interrupts are not yet
-	supported.  Watch this space for more details in the near
-	future."
-}
-
-target assabet {
-	alias { "Intel StrongARM SA1110 board" }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_SA11X0
-                   CYGPKG_HAL_ARM_SA11X0_ASSABET
-		   CYGPKG_IO_SERIAL_ARM_SA11X0
-		   CYGPKG_DEVS_PCMCIA_ASSABET
-                   CYGPKG_DEVS_FLASH_STRATA
-		   CYGPKG_DEVS_FLASH_ASSABET
-                   CYGPKG_IO_USB
-                   CYGPKG_IO_USB_SLAVE
-                   CYGPKG_DEVS_USB_SA11X0
-		   CYGPKG_DEVICES_WATCHDOG_ARM_SA11X0
-                   CYGPKG_DEVS_ETH_CF
-                   CYGPKG_DEVS_ETH_NS_DP83902A
-        }
-        description "
-        The assabet target provides the packages needed to run
-        eCos on an Intel StrongARM SA1110 evaluation board."
-}
-
-target cerf {
-	alias { "Intrinsyc SA1110 Cerf board" cerf_cube }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_SA11X0
-                   CYGPKG_HAL_ARM_SA11X0_CERF
-		   CYGPKG_IO_SERIAL_ARM_SA11X0
-		   CYGPKG_DEVS_PCMCIA_CERF
-                   CYGPKG_DEVS_FLASH_STRATA
-		   CYGPKG_DEVS_FLASH_CERF
-                   CYGPKG_IO_USB
-                   CYGPKG_IO_USB_SLAVE
-                   CYGPKG_DEVS_USB_SA11X0
-		   CYGPKG_DEVICES_WATCHDOG_ARM_SA11X0
-                   CYGPKG_DEVS_ETH_CF
-		   CYGPKG_DEVS_ETH_ARM_CERF
-                   CYGPKG_DEVS_ETH_CL_CS8900A
-        }
-        description "
-        The cerf target provides the packages needed to run
-        eCos on an Intrinsyc SA1110 Cerf board."
-}
-
-target cerfpda {
-	alias { "Intrinsyc SA1110 Cerfpda" cerf_pda }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_SA11X0
-                   CYGPKG_HAL_ARM_SA11X0_CERFPDA
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-	           CYGPKG_IO_SERIAL_ARM_CERFPDA
-		   CYGPKG_IO_SERIAL_ARM_SA11X0
-		   CYGPKG_DEVS_PCMCIA_CERFPDA
-                   CYGPKG_DEVS_FLASH_STRATA
-		   CYGPKG_DEVS_FLASH_CERFPDA
-                   CYGPKG_IO_USB
-                   CYGPKG_IO_USB_SLAVE
-                   CYGPKG_DEVS_USB_SA11X0
-		   CYGPKG_DEVICES_WATCHDOG_ARM_SA11X0
-                   CYGPKG_DEVS_ETH_CF
-		   CYGPKG_DEVS_ETH_ARM_CERFPDA
-                   CYGPKG_DEVS_ETH_CL_CS8900A
-        }
-        description "
-        The cerfpda target provides the packages needed to run
-        eCos on an Intrinsyc SA1110 cerfpda."
-}
-
-target ipaq {
-	alias { "Compaq iPAQ Pocket PC" }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_SA11X0
-                   CYGPKG_HAL_ARM_SA11X0_IPAQ
-		   CYGPKG_IO_SERIAL_ARM_SA11X0
-		   CYGPKG_DEVS_PCMCIA_IPAQ
-                   CYGPKG_DEVS_FLASH_IPAQ
-                   CYGPKG_DEVS_FLASH_STRATA
-		   CYGPKG_DEVICES_WATCHDOG_ARM_SA11X0
-                   CYGPKG_DEVS_TOUCH_IPAQ
-                   CYGPKG_DEVS_KBD_IPAQ
-                   CYGPKG_DEVS_ETH_CF
-                   CYGPKG_DEVS_ETH_NS_DP83902A
-        }
-        description "
-        The IPAQ target provides the packages needed to run
-        eCos on an Intel StrongARM SA1110 Pocket PC (Compaq iPAQ)."
-}
-
-
-target nano {
-	alias { "nanoEngine StrongARM SA1110 board" nanoEngine }
-        packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_SA11X0
-                   CYGPKG_HAL_ARM_SA11X0_NANO
-                   CYGPKG_IO_SERIAL_ARM_SA11X0
-                   CYGPKG_DEVS_FLASH_NANO
-                   CYGPKG_DEVS_FLASH_STRATA
-		   CYGPKG_DEVICES_WATCHDOG_ARM_SA11X0
-                   CYGPKG_IO_PCI
-                   CYGPKG_DEVS_ETH_ARM_NANO
-                   CYGPKG_DEVS_ETH_INTEL_I82559
-        }
-        description "
-        The nanoEngine target provides the packages needed to run
-        eCos on a Bright Star Engineering nanoEngine StrongARM SA1110 board."
-}
-
-target flexanet {
-      alias { "Flexanet StrongARM SA1110 platform" }
-      packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_SA11X0
-                   CYGPKG_HAL_ARM_SA11X0_FLEXANET
-                   CYGPKG_IO_SERIAL_ARM_SA11X0
-                   CYGPKG_DEVS_FLASH_STRATA
-                   CYGPKG_DEVS_FLASH_FLEXANET
-                   CYGPKG_DEVS_ETH_SMSC_LAN91CXX
-                   CYGPKG_DEVS_ETH_ARM_FLEXANET
-                   CYGPKG_IO_USB
-                   CYGPKG_IO_USB_SLAVE
-                   CYGPKG_DEVS_USB_SA11X0
-                   CYGPKG_DEVICES_WATCHDOG_ARM_SA11X0
-        }
-        description "
-          The Flexanet target provides the packages needed to run
-          eCos on an SA1110 Flexanet board."
-}
-
-target brutus {
-	alias { "Intel StrongARM SA1100 board" }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_SA11X0
-                   CYGPKG_HAL_ARM_SA11X0_BRUTUS
-		   CYGPKG_IO_SERIAL_ARM_SA11X0
-        }
-        description "
-        The brutus target provides the packages needed to run
-        eCos on an Intel StrongARM SA1100 evaluation board."
-}
-
-target sa1100mm {
-	alias { "Intel StrongARM SA1100 Multimedia board" }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_SA11X0
-                   CYGPKG_HAL_ARM_SA11X0_SA1100MM
-		   CYGPKG_IO_SERIAL_ARM_SA11X0
-		   CYGPKG_DEVS_FLASH_SA1100MM
-        }
-        description "
-        The sa1100mm target provides the packages needed to run
-        eCos on an Intel StrongARM SA1100 Multimedia evaluation board."
-}
-
-target iq80310 {
- 	alias { "Intel IQ80310 XScale board" cyclone }
-        packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_XSCALE_CORE
-                   CYGPKG_HAL_ARM_XSCALE_IOP310
-                   CYGPKG_HAL_ARM_XSCALE_IQ80310
-                   CYGPKG_IO_PCI
-                   CYGPKG_DEVS_ETH_INTEL_I82559
-                   CYGPKG_DEVS_ETH_ARM_XSCALE_IQ80310
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-                   CYGPKG_IO_SERIAL_ARM_XSCALE_IOP310
-                   CYGPKG_DEVS_FLASH_ARM_XSCALE_IQ80310
-        }
-        description "
-        The iq80310 target provides the packages needed to run
-        eCos on a Cyclone IQ80310 board."
-}
-
-target npwr {
-	alias { "NPWR Linux Engine (Intel XScale)" }
-        packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_XSCALE_CORE
-                   CYGPKG_HAL_ARM_XSCALE_IOP310
-                   CYGPKG_HAL_ARM_XSCALE_NPWR
-                   CYGPKG_DEVS_FLASH_ARM_XSCALE_IQ80310
-                   CYGPKG_DEVS_ETH_INTEL_I82544
-                   CYGPKG_DEVS_ETH_ARM_XSCALE_NPWR
-                   CYGPKG_IO_PCI
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-                   CYGPKG_IO_SERIAL_ARM_XSCALE_IOP310
-        }
-        description "
-        The npwr target provides the packages needed to run
-        eCos on a NPWR Linux Engine."
-}
-
-target iq80321 {
-	alias { "Intel XScale IQ80321 Board" }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_XSCALE_CORE
-                   CYGPKG_HAL_ARM_XSCALE_VERDE
-                   CYGPKG_HAL_ARM_XSCALE_IQ80321
-                   CYGPKG_IO_PCI
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-		   CYGPKG_IO_SERIAL_ARM_IQ80321
-                   CYGPKG_DEVS_ETH_INTEL_I82544
-                   CYGPKG_DEVS_FLASH_STRATA
-                   CYGPKG_DEVS_FLASH_IQ80321
-                   CYGPKG_DEVS_ETH_ARM_IQ80321
-        }
-        description "
-        The IQ80321 target provides the packages needed to run
-        eCos on an Intel XScale IQ80321 board."
-}
-
-target ixdp425 {
-	alias { "IXDP425 board" }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_XSCALE_CORE
-	           CYGPKG_HAL_ARM_XSCALE_IXP425
-                   CYGPKG_HAL_ARM_XSCALE_IXDP425
-		   CYGPKG_IO_PCI
-                   CYGPKG_DEVS_ETH_INTEL_I82559
-		   CYGPKG_DEVS_ETH_ARM_IXDP425_I82559
-                   CYGPKG_DEVS_FLASH_STRATA_V2
-        }
-        description "
-        The ixdp425 target provides the packages needed to run
-        eCos on an Intel network processor evaluation board."
-}
-
-target XSEngine {
-        alias { "Exys XSEngine Board" xsengine }
-        packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_XSCALE_CORE
-                   CYGPKG_HAL_ARM_XSCALE_PXA2X0
-                   CYGPKG_HAL_ARM_XSCALE_XSENGINE
-                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                   CYGPKG_DEVS_FLASH_XSENGINE
-                   CYGPKG_DEVS_ETH_SMSC_LAN91CXX
-                   CYGPKG_DEVS_ETH_ARM_XSCALE_XSENGINE
-        }
-        description "
-            The XSEngine target provides the packages needed to run
-            eCos on an Exys XSEngine board."
-}
-
-target grg {
-	alias { "Generic Residential Gateway" }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_XSCALE_CORE
-	           CYGPKG_HAL_ARM_XSCALE_IXP425
-                   CYGPKG_HAL_ARM_XSCALE_GRG
-		   CYGPKG_IO_PCI
-                   CYGPKG_DEVS_ETH_INTEL_I82559
-                   CYGPKG_DEVS_ETH_ARM_GRG_I82559
-                   CYGPKG_DEVS_FLASH_STRATA
-		   CYGPKG_DEVS_FLASH_GRG
-        }
-        description "
-        The grg target provides the packages needed to run
-        eCos on an Intel Generic Residential Gateway board."
-}
-
-target prpmc1100 {
-	alias { "Motorola PrPMC1100" }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_XSCALE_CORE
-	           CYGPKG_HAL_ARM_XSCALE_IXP425
-                   CYGPKG_HAL_ARM_XSCALE_PRPMC1100
-		   CYGPKG_IO_PCI
-                   CYGPKG_DEVS_FLASH_STRATA
-		   CYGPKG_DEVS_FLASH_PRPMC1100
-        }
-        description "
-        The prpmc1100 target provides the packages needed to run
-        eCos on a Motorola PrPMC1100."
-}
-
-target edb7xxx {
-        alias		{ "Cirrus Logic EDB7xxx development board" edb7211 eb7xxx eb7211 }
-	packages	{ CYGPKG_HAL_ARM
-                          CYGPKG_HAL_ARM_EDB7XXX
-			  CYGPKG_DEVS_ETH_ARM_EDB7XXX
-                          CYGPKG_DEVS_ETH_CL_CS8900A
-	                  CYGPKG_IO_SERIAL_ARM_EDB7XXX
-			  CYGPKG_DEVS_FLASH_EDB7XXX
-        }
-        description "
-The edb7xxx target provides the packages needed to run eCos on the Cirrus Logic EDB7xxx development boards."
-    }
-
-target pati {
-        alias           { "MPL PATI" }
-        packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_MPC5xx
-                          CYGPKG_HAL_POWERPC_PATI
-                          CYGPKG_IO_SERIAL_POWERPC_MPC555
-                          CYGPKG_DEVICES_WALLCLOCK_MPC5xx
-                          CYGPKG_DEVS_FLASH_PATI
-                          CYGPKG_DEVS_FLASH_INTEL_28FXXX
-        }
-        description "
-            The pati target provides the packages needed to run
-            eCos on a PATI MPC555 PC/104+ board from MLP
-            elektronik."
-}
-
-target cma230 {
-        alias		{ "Cogent CMA230/222 board" cma222 }
-	packages	{ CYGPKG_HAL_ARM
-                          CYGPKG_HAL_ARM_CMA230
-	                  CYGPKG_IO_SERIAL_ARM_CMA230
-        }
-        description "
-The cma230 target provides the packages needed to run eCos on a Cogent 
-CMA230 (ARM7TDMI) or CMA222 (ARM710T) board."
-    }
-
-
-target snds {
-      alias { "Samsung SNDS" SNDS snds100 }
-      packages { CYGPKG_HAL_ARM 
-                 CYGPKG_HAL_ARM_SNDS 
-                 CYGPKG_DEVS_ETH_ARM_KS32C5000
-               }
-      enable { CYGHWR_HAL_ARM_BIGENDIAN }
-      description "
-        The snds target provides the packages needed to run eCos on a
-        Samsung SNDS eval board."
-}
-
-target aim711 {
-      alias { "ARM Industrial Module AIM 711" AIM711 }
-      packages {
-                   CYGPKG_HAL_ARM 
-                   CYGPKG_HAL_ARM_AIM711 
-                   CYGPKG_DEVS_FLASH_SST_39VFXXX
-                   CYGPKG_DEVS_FLASH_ARM_AIM711
-                   CYGPKG_DEVS_ETH_ARM_KS32C5000
-                   CYGPKG_IO_SERIAL_ARM_AIM711
-                   CYGPKG_IO_SERIAL_ARM_S3C4510
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-                   CYGPKG_DEVICES_WALLCLOCK_ARM_AIM711
-                   CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1307 
-               }
-      description "
-        The aim711 target provides the packages needed to run eCos on a
-        ARM Industrial Module AIM 711."
- }
-
-
-target mpc50 {
-	alias { "MICROPLEX Printer Controller 5.0" }
-	packages {
-				CYGPKG_HAL_ARM
-				CYGPKG_HAL_ARM_XSCALE_CORE
-				CYGPKG_HAL_ARM_XSCALE_PXA2X0
-				CYGPKG_HAL_ARM_XSCALE_MPC50
-				CYGPKG_DEVS_FLASH_STRATA
-				CYGPKG_DEVS_FLASH_MPC50
-        }
-        description "
-        MICROPLEX Printer Controller 5.0"
-}
-
-# --------------------------------------------------------------------------
-# SH targets
-
-target sh7708 {
-	alias       { "Hitachi EDK/SH7708 board" edk7708 }
-	packages    { CYGPKG_HAL_SH
-                      CYGPKG_HAL_SH_SH3
-                      CYGPKG_HAL_SH_EDK7708
-                      CYGPKG_DEVICES_WALLCLOCK_SH3 
-	              CYGPKG_IO_SERIAL_SH_SCI
-	              CYGPKG_IO_SERIAL_SH_EDK7708
-                      CYGPKG_DEVICES_WATCHDOG_SH_SH3
-                      CYGPKG_DEVS_FLASH_SH_EDK7708
-                      CYGPKG_DEVS_FLASH_ATMEL_AT29CXXXX
-        }
-        description "
-           The sh7708 target provides the packages needed to run
-           eCos on a Hitachi EDK/SH7708 board."
-}
-target cq7708 {
-        alias { "CqREEK SH7708 board" }
-        packages { CYGPKG_HAL_SH
-                   CYGPKG_HAL_SH_SH3
-                   CYGPKG_HAL_SH_SH7708_CQ7708
-	           CYGPKG_IO_SERIAL_SH_SCI
-	           CYGPKG_IO_SERIAL_SH_CQ7708
-        }
-        description "
-           The cq7708 target provides the packages needed to run
-           eCos on a CqREEK SH7708 board."
-}
-
-target cq7750 {
-        alias { "CqREEK SH7750 board" cqsh4 }
-        packages { CYGPKG_HAL_SH
-                   CYGPKG_HAL_SH_SH4
-                   CYGPKG_HAL_SH_SH7750_CQ7750
-		   CYGPKG_DEVS_FLASH_CQ7750
-		   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                   CYGPKG_IO_SERIAL_SH_SCIF }
-        description "
-           The sh7750 target provides the packages needed to run
-           eCos on a CqREEK SH7750 board."
-}
-
-target hs7729pci {
-        alias       { "Hitachi HS7729PCI board" hs7729 }
-        packages    { CYGPKG_HAL_SH
-                      CYGPKG_HAL_SH_SH3
-                      CYGPKG_HAL_SH_SH7729_HS7729PCI
-                      CYGPKG_DEVS_FLASH_SH_HS7729PCI
-                      CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                      CYGPKG_IO_PCI
-                      CYGPKG_DEVS_ETH_SH_HS7729PCI
-                      CYGPKG_DEVS_ETH_VIA_RHINE
-                      CYGPKG_DEVICES_WATCHDOG_SH_SH3
-                      CYGPKG_DEVICES_WALLCLOCK_SH_HS7729PCI
-                      CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS12887
-        }
-        description "
-           The hs7729pci target provides the packages needed to run
-           eCos on a Hitachi HS7729PCI board."
-}
-
-target se77x9 {
-        alias       { "Hitachi SE77x9 board" }
-        packages    { CYGPKG_HAL_SH
-                      CYGPKG_HAL_SH_SH3
-                      CYGPKG_HAL_SH_SH77X9_SE77X9
-                      CYGPKG_DEVS_FLASH_SH_SE77X9
-                      CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                      CYGPKG_DEVS_ETH_NS_DP83902A
-                      CYGPKG_DEVS_ETH_SH_SE77X9
-                      CYGPKG_IO_SERIAL_SH_SE77X9
-                      CYGPKG_IO_SERIAL_SH_SCIF
-                      CYGPKG_IO_SERIAL_GENERIC_16X5X
-                      CYGPKG_DEVICES_WATCHDOG_SH_SH3
-        }
-        description "
-           The se77x9 target provides the packages needed to run
-           eCos on a Hitachi Solution Engine 77x9 board."
-}
-
-target se7751 {
-        alias       { "Hitachi SE7751 board" }
-        packages    { CYGPKG_HAL_SH
-                      CYGPKG_HAL_SH_SH4
-                      CYGPKG_HAL_SH_SH7751_SE7751
-                      CYGPKG_IO_PCI
-                      CYGPKG_DEVS_FLASH_SH_SE7751
-                      CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                      CYGPKG_IO_SERIAL_SH_SCIF
-                      CYGPKG_DEVICES_WATCHDOG_SH_SH3
-                      CYGPKG_DEVS_ETH_SH_SE7751
-                      CYGPKG_DEVS_ETH_AMD_PCNET
-        }
-        description "
-           The se7751 target provides the packages needed to run
-           eCos on a Hitachi Solution Engine 7751 board."
-}
-
-target dreamcast {
-        alias { "SEGA Dreamcast" }
-        packages { CYGPKG_HAL_SH
-                   CYGPKG_HAL_SH_SH4
-                   CYGPKG_HAL_SH_SH7750_DREAMCAST
-                   CYGPKG_IO_PCI
-		   CYGPKG_DEVS_ETH_RLTK_8139
-	           CYGPKG_DEVS_ETH_SH_DREAMCAST_RLTK8139
-                   CYGPKG_IO_SERIAL_SH_SCIF }
-        description "
-           The sh7750 target provides the packages needed to run
-           eCos on SEGA Dreamcast."
-}
-
-target sh4_202_md {
-        alias       { "SuperH SH4-202 MicroDev CPU board" }
-        packages    { CYGPKG_HAL_SH
-                      CYGPKG_HAL_SH_SH4
-                      CYGPKG_HAL_SH_SH4_202_MD
-                      CYGPKG_DEVS_FLASH_STRATA
-                      CYGPKG_DEVS_FLASH_SH_MICRODEV
-                      CYGPKG_IO_SERIAL_SH_SCIF
-                      CYGPKG_IO_SERIAL_SH_SH4_202_MD
-                      CYGPKG_DEVS_ETH_SH_MICRODEV
-                      CYGPKG_DEVS_ETH_SMSC_LAN91CXX
-        }
-        description "
-           The sh4_202_md target provides the packages needed to run
-           eCos on a SuperH SH4-202 MicroDev CPU board."
-}
-
-# --------------------------------------------------------------------------
-# i386 targets
-target pc_i82559 {
-        alias		{ "i386 PC target with i82559 ethernet" pc }
-	packages        { CYGPKG_HAL_I386
-                          CYGPKG_HAL_I386_GENERIC
-                          CYGPKG_HAL_I386_PC
-                          CYGPKG_HAL_I386_PCMB
-			  CYGPKG_IO_PCI
-                          CYGPKG_IO_SERIAL_GENERIC_16X5X
-	                  CYGPKG_IO_SERIAL_I386_PC
-			  CYGPKG_DEVS_ETH_INTEL_I82559
-			  CYGPKG_DEVS_ETH_I386_PC_I82559
-                          CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS12887
-                          CYGPKG_DEVICES_WALLCLOCK_I386_PC
-        }
-        description "
-    	    The pc_i82559 target provides the 
-    	    packages needed to run eCos binaries on a standard i386
-    	    PC motherboard with an Intel 82559 based ethernet interface."
-}
-
-target pc_i82544 {
-        alias		{ "i386 PC target with i82544 gigabit ethernet" pc_giga }
-	packages        { CYGPKG_HAL_I386
-                          CYGPKG_HAL_I386_GENERIC
-                          CYGPKG_HAL_I386_PC
-                          CYGPKG_HAL_I386_PCMB
-			  CYGPKG_IO_PCI
-                          CYGPKG_IO_SERIAL_GENERIC_16X5X
-	                  CYGPKG_IO_SERIAL_I386_PC
-			  CYGPKG_DEVS_ETH_INTEL_I82544
-			  CYGPKG_DEVS_ETH_I386_PC_I82544
-                          CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS12887
-                          CYGPKG_DEVICES_WALLCLOCK_I386_PC
-        }
-        description "
-    	    The pc_i82544 target provides the packages needed to run eCos binaries
-            on a standard i386 PC motherboard with an Intel 82543/82544 based
-            gigabit ethernet interface."
-}
-
-target pc_vmWare {
-        alias		{ "i386 PC target (vmWare)" }
-	packages        { CYGPKG_HAL_I386
-                          CYGPKG_HAL_I386_GENERIC
-                          CYGPKG_HAL_I386_PC
-                          CYGPKG_HAL_I386_PCMB
-			  CYGPKG_IO_PCI
-                          CYGPKG_IO_SERIAL_GENERIC_16X5X
-	                  CYGPKG_IO_SERIAL_I386_PC
-			  CYGPKG_DEVS_ETH_AMD_LANCEPCI
-			  CYGPKG_DEVS_ETH_I386_PC_LANCEPCI
-                          CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS12887
-                          CYGPKG_DEVICES_WALLCLOCK_I386_PC
-        }
-        description "
-    	    The pc_vmWare target provides the packages needed to run eCos binaries
-            on a standard i386 PC under wmWare."
-}
-
-
-target pc_usb_d12 {
-        alias		{ "i386 PC target with SoRo PC/104 D12 USB Slave" }
-	packages        { CYGPKG_HAL_I386
-                          CYGPKG_HAL_I386_GENERIC
-                          CYGPKG_HAL_I386_PC
-                          CYGPKG_HAL_I386_PCMB
-                          CYGPKG_IO_PCI
-                          CYGPKG_IO_SERIAL_GENERIC_16X5X
-                          CYGPKG_IO_SERIAL_I386_PC
-                          CYGPKG_IO_USB
-                          CYGPKG_IO_USB_SLAVE
-                          CYGPKG_DEVS_USB_D12
-                          CYGPKG_DEVS_USB_I386_SOROD12
-                          CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS12887
-                          CYGPKG_DEVICES_WALLCLOCK_I386_PC
-        }
-        description "
-    	    Provides the packages needed to run eCos binaries
-	    on a standard i386 PC motherboard with USB Slave support for the
-	    Philips D12 chip."
-}
-
-# --------------------------------------------------------------------------
-# Synthetic targets.
-target linux {
-        alias		{ "Linux synthetic target" i386linux }
-	packages        { CYGPKG_HAL_SYNTH
-                      CYGPKG_HAL_SYNTH_I386
-                      CYGPKG_DEVS_FLASH_SYNTH_V2
-                      CYGPKG_DEVS_ETH_ECOSYNTH
-                      CYGPKG_DEVS_WATCHDOG_SYNTH
-                      CYGPKG_DEVS_WALLCLOCK_SYNTH      
-                      CYGPKG_DEVS_FRAMEBUF_SYNTH
-                      CYGPKG_DEVS_ADC_SYNTH
-                      CYGPKG_DEVS_NAND_SYNTH
-        }
-        description "
-    	    The linux target provides the 
-    	    packages needed to run eCos binaries on top of the i386
-    	    Linux kernel."
-}
-
-# --------------------------------------------------------------------------
-# SPARClite targets
-
-target sleb {
-	alias		{ "Fujitsu MB86800-MA01 board" }
-	packages        { CYGPKG_HAL_SPARCLITE
-                          CYGPKG_HAL_SPARCLITE_SLEB
-	                  CYGPKG_IO_SERIAL_SPARCLITE_SLEB
-        }
-        description "
-    	    The sleb target provides the packages need to run eCos
-            on a Fujitsu MB86800-MA01 board."
-}
-
-target sparclite_sim {
-	alias		{ "SPARClite simulator" sl_sim sparcl_sim }
-	packages        { CYGPKG_HAL_SPARCLITE 
-                          CYGPKG_HAL_SPARCLITE_SIM
-        }
-        description "
-    	    The sparclite_sim target provides the packages need to run eCos
-            on the SPARClite simulator."
-}
-
-# --------------------------------------------------------------------------
-# SPARC V7/V8 targets
-
-target sparc_erc32 {
-	alias		{ "ERC32 processor" erc32 }
-	packages        { CYGPKG_HAL_SPARC 
-                          CYGPKG_HAL_SPARC_ERC32
-        }
-        description "
-    	    The sparc_erc32 target provides the packages need to run eCos
-            on the ERC32 processor or TSIM/ERC32 simulator."
-}
-
-target sparc_leon {
-	alias		{ "LEON processor" leon }
-	packages        { CYGPKG_HAL_SPARC 
-                          CYGPKG_HAL_SPARC_LEON
-        }
-        description "
-    	    The sparc_leon target provides the packages need to run eCos
-            on the LEON processor or TSIM/LEON simulator."
-}
-
-# --------------------------------------------------------------------------
-# PowerPC targets
-target cme555 {
-        alias           { "Axiom's CME555 board" }
-        packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_MPC5xx
-                          CYGPKG_HAL_POWERPC_CME555
-                          CYGPKG_DEVS_FLASH_CME555
-                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                          CYGPKG_IO_SERIAL_POWERPC_MPC555
-                          CYGPKG_DEVICES_WALLCLOCK_MPC5xx
-        }
-        description "
-            The cme555 target provides the packages needed to run
-            eCos on a CME555 MPC555 evaluation board from Axiom
-            Manufacturing."
-}
-
-target ec555 {
-        alias           { "Wuerz ec555" }
-        packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_MPC5xx
-                          CYGPKG_HAL_POWERPC_EC555
-                          CYGPKG_DEVS_FLASH_EC555
-                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                          CYGPKG_IO_SERIAL_POWERPC_MPC555
-                          CYGPKG_DEVICES_WALLCLOCK_MPC5xx
-        }
-        description "
-            The ec555 target provides the packages needed to run
-            eCos on a EC555 MPC555 development board from Wuerz
-            elektronik."
-}
-
-target cma28x {
-        alias		{ "Cogent CMA286/287 board" cma286 cma287 }
-	packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_MPC8xx 
-                          CYGPKG_HAL_POWERPC_COGENT
-                          CYGPKG_IO_SERIAL_POWERPC_COGENT
-        }
-        description "
-            The cma28x target provides the packages needed to run
-            eCos on a Cogent CMA286 or CMA287 board."
-}
-
-target fads {
-        alias		{ "Motorola MPC8xxFADS board" }
-	packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_MPC8xx 
-                          CYGPKG_HAL_POWERPC_FADS
-        }
-        description "
-            The fads target provides the packages needed to run
-            eCos on a Motorola MPC8xxFADS board."
-}
-
-target mbx {
-        alias		{ "Motorola MBX860/821 board" mbx860 mbx821 }
-	packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_MPC8xx
-                          CYGPKG_HAL_POWERPC_MBX
-                          CYGPKG_HAL_QUICC 
-                          CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
-                          CYGPKG_DEVS_ETH_POWERPC_QUICC
-                          CYGPKG_DEVS_ETH_POWERPC_MBX
-                          CYGPKG_DEVS_FLASH_MBX
-                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-        }
-        description "
-            The mbx target provides the packages needed to run
-            eCos on a Motorola MBX860 or MBX821 board."
-}
-
-target ts6 {
-        alias		{ "Delphi TigerSHARC-6 board" Pleiades sixpack }
-	packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_MPC8260
-                          CYGPKG_HAL_POWERPC_TS6
-                          CYGPKG_DEVS_ETH_POWERPC_QUICC2
-                          CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC
-                          CYGPKG_DEVS_FLASH_TS6
-                          CYGPKG_DEVS_FLASH_INTEL_28FXXX
-        }
-        description "
-            The ts6 target provides the packages needed to run
-            eCos on a Delphi TigerSHARC-6 board."
-}
-
-target vads {
-        alias		{ "Motorola MPC8260 VADS board" }
-	packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_MPC8260
-                          CYGPKG_HAL_POWERPC_VADS
-                          CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC
-                          CYGPKG_DEVS_ETH_POWERPC_QUICC2
-                          CYGPKG_DEVS_FLASH_VADS
-                          CYGPKG_DEVS_FLASH_INTEL_28FXXX
-        }
-        description "
-            The vads target provides the packages needed to run
-            eCos on a Motorola MPC8260 VADS board."
-}
-
-target viper {
-        alias		{ "A&M Viper PPC860 board" viper860 }
-	packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_MPC8xx
-                          CYGPKG_HAL_POWERPC_VIPER
-                          CYGPKG_HAL_QUICC 
-                          CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
-                          CYGPKG_DEVS_ETH_POWERPC_FEC
-                          CYGPKG_DEVS_ETH_POWERPC_VIPER
-                          CYGPKG_DEVS_FLASH_VIPER
-                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-        }
-        description "
-            The viper target provides the packages needed to run
-            eCos on a A&M Viper PPC860 board."
-}
-
-target psim {
-	alias		{ "PowerPC simulator" ppc_sim powerpc_sim }
-	packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_PPC60x
-                          CYGPKG_HAL_POWERPC_SIM
-        }
-        description "
-            The psim target provides the packages needed to run
-            eCos in the PSIM simulator."
-}
-
-##-------------------------------------------------------------------------------------------
-## Cogent CSB281 (PowerPC 8245) packages
-##
-package CYGPKG_HAL_POWERPC_CSB281 {
-	alias		{ "Cogent PowerPC 8245 board" hal_powerpc_csb281 }
-	directory	hal/powerpc/csb281
-	script		hal_powerpc_csb281.cdl
-	hardware
-        description "
-            The CSB281 HAL package provides the support needed to run
-            eCos on a Cogent PowerPC 8245 board."
-}
-
-package CYGPKG_DEVS_FLASH_CSB281 {
-	alias 		{ "FLASH memory support for Cogent PowerPC 8245 board" flash_csb281 }
-	directory	devs/flash/powerpc/csb281
-	script		flash_csb281.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Cogent CSB281 (PowerPC 8245) board."
-}
-
-package CYGPKG_DEVS_ETH_CSB281 {
-	alias 		{ "Cogent CSB281 (PowerPC 8245) 82559 ethernet driver"
-			   devs_eth_csb281 }
-	hardware
-	directory	devs/eth/powerpc/csb281
-	script		csb281_eth_drivers.cdl
-        description     "Ethernet driver for Cogent CSB281 (PowerPC 8245)
-                         with Intel i82559 ethernet interfaces."
-}
-
-target csb281 {
-	alias		{ "Cogent PowerPC 8245" cogent8245 }
-	packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_PPC60x
-                          CYGPKG_HAL_POWERPC_CSB281
-                          CYGPKG_DEVS_FLASH_STRATA
-                          CYGPKG_DEVS_FLASH_CSB281
-                          CYGPKG_IO_PCI
-                          CYGPKG_DEVS_ETH_CSB281
-                          CYGPKG_DEVS_ETH_INTEL_I82559
-        }
-        description "
-            The csb281 target provides the packages needed to run
-            eCos on the Cogent CSB281 (8245) board."
-}
-##-------------------------------------------------------------------------------------------
-
-# --------------------------------------------------------------------------
-# MIPS targets
-
-target jmr3904 {
-        alias		{ "Toshiba JMR-TX3904 board" jmr tx39 }
-	packages        { CYGPKG_HAL_MIPS
-                          CYGPKG_HAL_MIPS_TX39
-                          CYGPKG_HAL_MIPS_TX39_JMR3904
-	                  CYGPKG_IO_SERIAL_TX39_JMR3904
-        }
-        description "
-           The jmr3904 target provides the packages needed to run
-           eCos on a Toshiba JMR-TX3904 board. This target can also
-           be used when running in the full simulator, since the simulator provides an
-           accurate simulation of the hardware including I/O devices.
-           To use the simulator in this mode the command
-           `target sim --board=jmr3904' should be used from inside gdb."
-}
-
-target atlas_mips32_4kc {
-        alias		{ "MIPS Atlas board with Mips32 4Kc processor" }
-	packages        { CYGPKG_HAL_MIPS
-                          CYGPKG_HAL_MIPS_MIPS32
-                          CYGPKG_HAL_MIPS_ATLAS
-                          CYGPKG_IO_SERIAL_MIPS_ATLAS
-                          CYGPKG_DEVS_FLASH_ATLAS
-                          CYGPKG_DEVS_ETH_MIPS_ATLAS
-                          CYGPKG_IO_PCI
-        }
-    set_value CYGHWR_HAL_MIPS_MIPS32_CORE "4Kc"
-        description "
-           The atlas_mips32_4Kc target provides the packages needed to run
-           eCos on a MIPS Atlas board with a Mips32 4Kc processor."
-}
-
-target atlas_mips64_5kc {
-        alias		{ "MIPS Atlas board with Mips64 5Kc processor" ruby }
-	packages        { CYGPKG_HAL_MIPS
-                          CYGPKG_HAL_MIPS_MIPS64
-                          CYGPKG_HAL_MIPS_ATLAS
-                          CYGPKG_IO_SERIAL_MIPS_ATLAS
-                          CYGPKG_DEVS_FLASH_ATLAS
-                          CYGPKG_DEVS_ETH_MIPS_ATLAS
-        }
-    set_value CYGHWR_HAL_MIPS_MIPS64_CORE "5K"
-        description "
-           The atlas_mips32_5Kc target provides the packages needed to run
-           eCos on a MIPS Atlas board with a Mips64 5Kc processor."
-}
-target malta_mips32_4kc {
-        alias		{ "MIPS Malta board with Mips32 4Kc processor" }
-	packages        { CYGPKG_HAL_MIPS
-                          CYGPKG_HAL_MIPS_MIPS32
-                          CYGPKG_HAL_MIPS_MALTA
-                          CYGPKG_DEVS_FLASH_INTEL_28FXXX
-                          CYGPKG_DEVS_FLASH_MALTA
-                          CYGPKG_IO_PCI
-                          CYGPKG_DEVS_ETH_AMD_PCNET
-                          CYGPKG_DEVS_ETH_MIPS_MIPS32_MALTA
-        }
-        set_value CYGHWR_HAL_MIPS_MIPS32_CORE "4Kc"
-        description "
-           The malta_mips32_4Kc target provides the packages needed to run
-           eCos on a MIPS Malta board with a Mips32 4Kc processor."
-}
-
-target malta_mips64_5kc {
-        alias		{ "MIPS Malta board with Mips64 5Kc processor" }
-	packages        { CYGPKG_HAL_MIPS
-                          CYGPKG_HAL_MIPS_MIPS64
-                          CYGPKG_HAL_MIPS_MALTA
-                          CYGPKG_DEVS_FLASH_INTEL_28FXXX
-                          CYGPKG_DEVS_FLASH_MALTA
-                          CYGPKG_IO_PCI
-                          CYGPKG_DEVS_ETH_AMD_PCNET
-                          CYGPKG_DEVS_ETH_MIPS_MIPS32_MALTA
-        }
-        set_value CYGHWR_HAL_MIPS_MIPS64_CORE "5K"
-        description "
-           The malta_mips64_5Kc target provides the packages needed to run
-           eCos on a MIPS Malta board with a Mips64 5Kc processor."
-}
-target tx39_sim {
-        alias		{ "TX39 minimal simulator" }
-	packages        { CYGPKG_HAL_MIPS
-                          CYGPKG_HAL_MIPS_TX39
-                          CYGPKG_HAL_MIPS_SIM
-        }
-        description "
-           The tx39_sim target provides the packages needed to run
-           eCos in the TX39 minimal simulator. To use this minimal
-           simulator the command `target sim --board=jmr3904pal'
-           should be used from inside gdb. It is not possible to
-           use any of the eCos device drivers when the simulator
-           is running in this mode."
-}
-target ref4955 {
-        alias		{ "Toshiba TX4955 reference platform" tx49 }
-	packages        { CYGPKG_HAL_MIPS
-                          CYGPKG_HAL_MIPS_TX49
-                          CYGPKG_HAL_MIPS_TX49_REF4955
-                          CYGPKG_IO_SERIAL_GENERIC_16X5X
-                          CYGPKG_IO_SERIAL_MIPS_REF4955
-                          CYGPKG_DEVICES_WALLCLOCK_MIPS_REF4955
-                          CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1742
-        }
-        description "
-           The ref4955 target provides the packages needed to run
-           eCos on a Toshiba TX4955 reference platform."
-}
-
-target ocelot {
-        alias		{ "PMC-Sierra Ocelot platform" }
-	packages        { CYGPKG_HAL_MIPS
-                          CYGPKG_HAL_MIPS_RM7000
-                          CYGPKG_HAL_MIPS_RM7000_OCELOT
-                          CYGPKG_IO_PCI
-                          CYGPKG_DEVS_FLASH_MIPS_OCELOT
-                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                          CYGPKG_IO_SERIAL_GENERIC_16X5X
-                          CYGPKG_DEVS_ETH_INTEL_I82559
-                          CYGPKG_DEVS_ETH_MIPS_RM7000_OCELOT
-        }
-        description "
-           The ocelot target provides the packages needed to run
-           eCos on a PMC-Sierra Ocelot Hot-Swap Computer."
-}
-
-target vrc4373 {
-        alias		{ "NEC VRC4373 board" }
-	packages        { CYGPKG_HAL_MIPS
-                          CYGPKG_HAL_MIPS_VR4300
-                          CYGPKG_HAL_MIPS_VR4300_VRC4373
-                          CYGPKG_HAL_MIPS_VR4300_VRC437X
-	                  CYGPKG_IO_SERIAL_MIPS_VRC437X
-                          CYGPKG_DEVS_FLASH_MIPS_VRC437X
-			  CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-			  CYGPKG_IO_PCI
-        }
-        description "
-           The vrc4373 target provides the packages needed to run
-           eCos on an NEC VRC4373 board."
-}
-target vrc4375 {
-        alias		{ "NEC VRC4375 board" }
-	packages        { CYGPKG_HAL_MIPS
-                          CYGPKG_HAL_MIPS_VR4300
-                          CYGPKG_HAL_MIPS_VR4300_VRC4375
-                          CYGPKG_HAL_MIPS_VR4300_VRC437X
-	                  CYGPKG_IO_SERIAL_MIPS_VRC437X
-                          CYGPKG_DEVS_FLASH_MIPS_VRC437X
-			  CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                          CYGPKG_IO_PCI
-			  CYGPKG_DEVS_ETH_INTEL_I21143
-			  CYGPKG_DEVS_ETH_MIPS_VRC4375
-        }
-        description "
-           The vrc4375 target provides the packages needed to run
-           eCos on an NEC VRC4375 board."
-}
-
-target refidt334 {
-        alias		{ "MIPS IDT79S334A reference platform" idt32334 }
-	packages        { CYGPKG_HAL_MIPS
-                          CYGPKG_HAL_MIPS_IDT32334
-                          CYGPKG_HAL_MIPS_IDT32334_REFIDT334
-                          CYGPKG_IO_PCI
-			  CYGPKG_DEVS_ETH_INTEL_I82559
-			  CYGPKG_DEVS_ETH_MIPS_REFIDT334
-			  CYGPKG_DEVS_FLASH_MIPS_REFIDT334
-			  CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-			  CYGPKG_IO_SERIAL_MIPS_IDT79S334A
-        }
-        description "
-           The refidt334 target provides the packages needed to run
-           eCos on a MIPS IDT IDT79S334A reference board."
-}
-
-# --------------------------------------------------------------------------
-# MN10300 targets
-
-target am31_sim {
-        alias		{ "MN10300 AM31 minimal simulator" }
-	packages        { CYGPKG_HAL_MN10300
-                          CYGPKG_HAL_MN10300_AM31
-                          CYGPKG_HAL_MN10300_AM31_SIM
-        }
-        description "
-           The am31_sim target provides the packages need to run
-           eCos in the MN10300 minimal simulator. It is not possible to
-           use any of the eCos device drivers when the simulator
-           is running in this mode."
-}
-
-target stdeval1 {
-        alias		{ "Matsushita stdeval1 board" }
-	packages        { CYGPKG_HAL_MN10300 
-                          CYGPKG_HAL_MN10300_AM31_STDEVAL1 
-                          CYGPKG_HAL_MN10300_AM31 
-                          CYGPKG_IO_SERIAL_MN10300
-                          CYGPKG_DEVICES_WATCHDOG_MN10300_MN10300
-        }
-        description "
-           The stdeval1 target provides the packages needed to run
-           eCos on a Matsushita stdeval1 board. This target can also
-           be used when running in the full simulator, since the simulator provides an
-           accurate simulation of the hardware including I/O devices."
-}
-target stb {
-        alias		{ "Matsushita STB board" }
-	packages        { CYGPKG_HAL_MN10300
-                          CYGPKG_HAL_MN10300_AM33_STB
-                          CYGPKG_HAL_MN10300_AM33
-                          CYGPKG_IO_SERIAL_MN10300
-                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                          CYGPKG_DEVS_FLASH_MN10300_STB
-                          CYGPKG_DEVICES_WATCHDOG_MN10300_MN10300
-        }
-        description "
-           The stb target provides the packages needed to run
-           eCos on a Matsushita STB board."
-}
-
-target asb {
-        alias		{ "Matsushita ASB2303 board" }
-	packages        { CYGPKG_HAL_MN10300
-                          CYGPKG_HAL_MN10300_AM33_ASB
-                          CYGPKG_HAL_MN10300_AM33
-                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                          CYGPKG_DEVS_FLASH_MN10300_ASB2303
-        }
-        description "
-           The asb target provides the packages needed to run
-           eCos on a Matsushita ASB2303 board."
-}
-
-target asb2305 {
-        alias		{ "Matsushita ASB2305 board" }
-	packages        { CYGPKG_HAL_MN10300
-                          CYGPKG_HAL_MN10300_AM33_ASB2305
-                          CYGPKG_HAL_MN10300_AM33
-                          CYGPKG_IO_SERIAL_GENERIC_16X5X
-                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                          CYGPKG_DEVS_FLASH_MN10300_ASB2305
-        }
-        description "
-           The asb2305 target provides the packages needed to run
-           eCos on a Matsushita ASB2305 board."
-}
-
-# --------------------------------------------------------------------------
-# NEC targets
-
-target ceb_v850 {
-	alias { "Cosmo CEB-V850 board" CEB ceb_v850_sa1 }
-	packages { CYGPKG_HAL_V85X
-                   CYGPKG_HAL_V85X_V850
-                   CYGPKG_HAL_V85X_V850_CEB
-                   CYGPKG_IO_SERIAL_V85X_V850
-        }
-        description "
-The ceb_v850 target provides the packages needed to run eCos on a
-Cosmo CEB-V850 evaluation board fitted with a NEC V850/SA1 or NEC V850/SB1."
-}
-
-# --------------------------------------------------------------------------
-# m68k targets
-
-target m5272c3 {
-    alias { "Freescale m5272c3 evaluation board" }
-    packages {
-        CYGPKG_HAL_M68K
-        CYGPKG_HAL_M68K_MCFxxxx
-        CYGPKG_HAL_M68K_MCF5272
-        CYGPKG_HAL_M68K_M5272C3
-        CYGPKG_DEVS_ETH_MCFxxxx
-        CYGPKG_DEVS_SERIAL_MCFxxxx
-        CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2
-    }
-
-    description   "The m5272c3 target provides  the packages  needed to  run
-                eCos on the Freescale m5272c3 evaluation board."
-}
-
-# --------------------------------------------------------------------------
-# H8 targets
-
-target h8300h_sim {
-        alias		{ "H8/300H minimal simulator" }
-	packages        { CYGPKG_HAL_H8300
-                          CYGPKG_HAL_H8300_H8300H
-                          CYGPKG_HAL_H8300_H8300H_SIM
-                          CYGPKG_IO_SERIAL_H8300_SCI
-        }
-        description "
-           The h8300h_sim target provides the packages need to run
-           eCos in the H8/300H minimal simulator. It is not possible to
-           use any of the eCos device drivers when the simulator
-           is running in this mode."
-}
-
-target h8s_sim {
-        alias		{ "H8S minimal simulator" }
-	packages        { CYGPKG_HAL_H8300
-                          CYGPKG_HAL_H8300_H8S
-                          CYGPKG_HAL_H8300_H8S_SIM
-                          CYGPKG_IO_SERIAL_H8300_SCI
-        }
-        description "
-           The h8300h_sim target provides the packages need to run
-           eCos in the H8/300H minimal simulator. It is not possible to
-           use any of the eCos device drivers when the simulator
-           is running in this mode."
-}
-
-target aki3068net {
-        alias		{ "Akizuki H8/3068 Network board" }
-	packages        { CYGPKG_HAL_H8300
-                          CYGPKG_HAL_H8300_H8300H
-                          CYGPKG_HAL_H8300_H8300H_AKI3068NET
-                          CYGPKG_IO_SERIAL_H8300_SCI
-			  CYGPKG_DEVS_ETH_H8300_AKI3068NET
-                          CYGPKG_DEVICES_WATCHDOG_H8300_H8300H
-        }
-        description "
-           The aki3068net target provides the packages need to run
-           eCos in the Akizuki H8/3068 Network board."
-}
-
-target h8max {
-        alias		{ "H8MAX" }
-	packages        { CYGPKG_HAL_H8300
-                          CYGPKG_HAL_H8300_H8300H
-                          CYGPKG_HAL_H8300_H8300H_H8MAX
-                          CYGPKG_IO_SERIAL_H8300_SCI
-			  CYGPKG_DEVS_ETH_H8300_H8MAX
-                          CYGPKG_DEVICES_WATCHDOG_H8300_H8300H
-        }
-        description "
-           The h8max target provides the packages need to run
-           eCos in the strawberry-linux.com H8MAX board."
-}
-
-target edosk2674 {
-        alias		{ "EDOSK-2674" }
-	packages        { CYGPKG_HAL_H8300
-                          CYGPKG_HAL_H8300_H8S
-                          CYGPKG_HAL_H8300_H8S_EDOSK2674
-                          CYGPKG_IO_SERIAL_H8300_SCI
-			  CYGPKG_DEVS_ETH_H8300_EDOSK2674
-        }
-        description "
-           The h8max target provides the packages need to run
-           eCos in the Hitachi Micro System Europe EDOSK-2674 Evalution board."
-}
-
-# --------------------------------------------------------------------------
-# CalmRISC16 targets
-
-target calm16_ceb {
-        alias		{ "CalmRISC16 Core Eval Board" }
-	packages        { CYGPKG_HAL_CALM16
-                          CYGPKG_HAL_CALM16_CORE
-                          CYGPKG_HAL_CALM16_CEB
-        }
-        description "
-           The calm16_ceb target provides the packages needed to run
-           eCos on the CalmRISC16 Core Evaluation Board."
-}
-# --------------------------------------------------------------------------
-# CalmRISC32 targets
-
-target calm32_ceb {
-        alias		{ "CalmRISC32 Core Eval Board" }
-	packages        { CYGPKG_HAL_CALM32
-                          CYGPKG_HAL_CALM32_CORE
-                          CYGPKG_HAL_CALM32_CEB
-        }
-        description "
-           The calm32_ceb target provides the packages needed to run
-           eCos on the CalmRISC32 Core Evaluation Board."
-}
-
-# --------------------------------------------------------------------------
-
-package CYGPKG_HAL_POWERPC_TS1000 {
-	alias		{ "Allied Telesyn TS1000 board" hal_powerpc_ts1000 }
-	directory	hal/powerpc/ts1000
-	script		hal_powerpc_ts1000.cdl
-	hardware
-        description "
-            The TS1000 HAL package provides the support needed to run
-            eCos on a Allied Telesyn TS1000 board equipped with a PowerPC processor."
-}
-
-package CYGPKG_DEVS_FLASH_POWERPC_TS1000 {
-	alias 		{ "FLASH memory support for Allied Telesyn TS1000 (PPC855) board" flash_ts1000 }
-	directory	devs/flash/powerpc/ts1000
-	script		flash_ts1000.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the Allied Telesyn TS1000 (PPC855) platform."
-}
-
-package CYGPKG_DEVS_ETH_POWERPC_TS1000 {
-	alias 		{ "Allied Telesyn TS1000 ethernet driver" ts1000_eth_driver }
-	hardware
-	directory	devs/eth/powerpc/ts1000
-	script		ts1000_eth_drivers.cdl
-        description     "Ethernet driver specifics for Allied Telesyn TS1000 (MPC855T) based boards."
-}
-
-target ts1000 {
-        alias		{ "Allied Telesyn TS1000 board" ts1000_855 }
-	packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_MPC8xx
-                          CYGPKG_HAL_POWERPC_TS1000
-                          CYGPKG_HAL_QUICC 
-                          CYGPKG_DEVS_FLASH_POWERPC_TS1000
-                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                          CYGPKG_DEVS_ETH_POWERPC_FEC
-                          CYGPKG_DEVS_ETH_POWERPC_TS1000
-                          CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
-        }
-        description "
-            The ts1000 target provides the packages needed to run
-            eCos on a Allied Telesyn TS1000 (PPC855T) board."
-}
-
-# --------------------------------------------------------------------------
-
-package CYGPKG_DEVS_FLASH_UE250 {
-	alias 		{ "FLASH memory support for uE250" flash_uE250 }
-	directory	devs/flash/arm/uE250
-	script		flash_uE250.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the uE250 platform."
-}
-
-package CYGPKG_DEVS_ETH_ARM_XSCALE_UE250 {
-	alias 		{ "NMI uE250 PCI ethernet driver" devs_eth_arm_ue250 }
-	hardware
-	directory	devs/eth/arm/uE250
-	script		uE250_eth_drivers.cdl
-        description     "Ethernet driver for NMI uE250 via PCI card."
-}
-
-package CYGPKG_HAL_ARM_XSCALE_UE250 {
-	alias		{ "NMI uEngine uE250" hal_arm_xscale_uE250 }
-	directory	hal/arm/xscale/uE250
-	script		hal_arm_xscale_uE250.cdl
-	hardware
-        description "
-        The UE250 HAL package provides the support needed to run
-        eCos on an NMI uEngine u250 board."
-}
-
-target uE250 {
-	alias { "NMI uEngine uE250 Board" ue250 }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_XSCALE_CORE
-                   CYGPKG_HAL_ARM_XSCALE_PXA2X0
-                   CYGPKG_HAL_ARM_XSCALE_UE250
-                   CYGPKG_IO_PCI
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-                   CYGPKG_DEVS_FLASH_STRATA
-                   CYGPKG_DEVS_FLASH_UE250
-                   CYGPKG_DEVS_ETH_NS_DP83902A
-                   CYGPKG_DEVS_ETH_ARM_XSCALE_UE250
-        }
-        description "
-        The uE250 target provides the packages needed to run
-        eCos on an NMI uEngine uE250 board."
-}
-
-# --------------------------------------------------------------------------
-
-package CYGPKG_DEVS_FLASH_PICASSO {
-	alias 		{ "FLASH memory support for picasso" flash_picasso }
-	directory	devs/flash/arm/picasso
-	script		flash_picasso.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the picasso platform."
-}
-
-package CYGPKG_DEVS_ETH_ARM_XSCALE_PICASSO {
-	alias 		{ "NMI picasso PCI ethernet driver" devs_eth_arm_picasso }
-	hardware
-	directory	devs/eth/arm/picasso
-	script		picasso_eth_drivers.cdl
-        description     "Ethernet driver for NMI picasso via PCI card."
-}
-
-package CYGPKG_HAL_ARM_XSCALE_PICASSO {
-	alias		{ "NMI uEngine picasso" hal_arm_xscale_picasso }
-	directory	hal/arm/xscale/picasso
-	script		hal_arm_xscale_picasso.cdl
-	hardware
-        description "
-        The PICASSO HAL package provides the support needed to run
-        eCos on an NMI uEngine u250 board."
-}
-
-target picasso {
-	alias { "NMI uEngine picasso Board" }
-	packages { CYGPKG_HAL_ARM
-                   CYGPKG_HAL_ARM_XSCALE_CORE
-                   CYGPKG_HAL_ARM_XSCALE_PXA2X0
-                   CYGPKG_HAL_ARM_XSCALE_PICASSO
-                   CYGPKG_IO_PCI
-                   CYGPKG_IO_SERIAL_GENERIC_16X5X
-                   CYGPKG_DEVS_FLASH_STRATA
-                   CYGPKG_DEVS_FLASH_PICASSO
-                   CYGPKG_DEVS_ETH_NS_DP83902A
-                   CYGPKG_DEVS_ETH_ARM_XSCALE_PICASSO
-        }
-        description "
-        The picasso target provides the packages needed to run
-        eCos on an NMI uEngine picasso board."
-}
-
-# --------------------------------------------------------------------------
-
-package CYGPKG_HAL_POWERPC_ADDER {
-	alias		{ "A&M Adder PPC85x board" hal_powerpc_adder powerpc_adder_hal }
-	directory	hal/powerpc/adder
-	script		hal_powerpc_adder.cdl
-	hardware
-        description "
-            The ADDER HAL package provides the support needed to run
-            eCos on a A&M ADDER board equipped with a PowerPC processor."
-}
-
-package CYGPKG_DEVS_FLASH_POWERPC_ADDER {
-	alias 		{ "FLASH memory support for A&M Adder PowerPC/85x" flash_adder }
-	directory	devs/flash/powerpc/adder
-	script		flash_adder.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the A&M PowerPC/8xx ADDER platforms."
-}
-
-package CYGPKG_DEVS_ETH_POWERPC_ADDER {
-	alias 		{ "A&M Adder ethernet driver" adder_eth_driver }
-	hardware
-	directory	devs/eth/powerpc/adder
-	script		adder_eth_drivers.cdl
-        description     "Ethernet driver specifics for A&M Adder (MPC85x) based boards."
-}
-
-package CYGPKG_DEVS_ETH_POWERPC_ADDERII {
-        alias           { "A&M AdderII ethernet driver" adderII_eth_driver }
-        hardware
-        directory       devs/eth/powerpc/adderII
-        script          adderII_eth_drivers.cdl
-        description     "Ethernet driver specifics for A&M AdderII (MPC852T) based boards."
-}
-
-target adder {
-        alias		{ "A&M Adder PPC850 board" adder850 }
-	packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_MPC8xx
-                          CYGPKG_HAL_POWERPC_ADDER
-                          CYGPKG_HAL_QUICC 
-                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2
-                          CYGPKG_DEVS_ETH_POWERPC_QUICC
-                          CYGPKG_DEVS_ETH_POWERPC_ADDER
-                          CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
-        }
-        enable { CYGHWR_HAL_POWERPC_ADDER_I }
-        description "
-            The adder target provides the packages needed to run
-            eCos on a A&M Adder PPC850 board."
-}
-
-target adderII {
-        alias		{ "A&M Adder PPC852T board" adder852T }
-	packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_MPC8xx
-                          CYGPKG_HAL_POWERPC_ADDER
-                          CYGPKG_HAL_QUICC 
-                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2
-                          CYGPKG_DEVS_ETH_POWERPC_FEC
-                          CYGPKG_DEVS_ETH_POWERPC_ADDERII
-                          CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
-        }
-        enable { CYGHWR_HAL_POWERPC_ADDER_II }
-        description "
-            The adderII target provides the packages needed to run
-            eCos on a A&M Adder PPC852T board."
-}
-
-# --------------------------------------------------------------------------
-
-package CYGPKG_HAL_POWERPC_RATTLER {
-	alias		{ "A&M Rattler MPC8250 board" hal_powerpc_rattler powerpc_rattler_hal }
-	directory	hal/powerpc/rattler
-	script		hal_powerpc_rattler.cdl
-	hardware
-        description "
-            The RATTLER HAL package provides the support needed to run
-            eCos on a A&M RATTLER board equipped with a PowerPC processor."
-}
-
-package CYGPKG_DEVS_ETH_POWERPC_RATTLER {
-        alias           { "A&M Rattler ethernet driver" rattler_eth_driver }
-        hardware
-        directory       devs/eth/powerpc/rattler
-        script          rattler_eth_drivers.cdl
-        description     "Ethernet driver specifics for A&M Rattler (MPC8250) based boards."
-}
-
-package CYGPKG_DEVS_FLASH_POWERPC_RATTLER {
-	alias 		{ "FLASH memory support for A&M Rattler (MPC8250)" flash_rattler }
-	directory	devs/flash/powerpc/rattler
-	script		flash_rattler.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the A&M Rattler (MPC8250) platforms."
-}
-
-target rattler {
-        alias		{ "A&M Rattler (8250) board" }
-	packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_MPC8XXX
-                          CYGPKG_HAL_POWERPC_RATTLER
-                          CYGPKG_DEVS_FLASH_POWERPC_RATTLER
-                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
-                          CYGPKG_DEVS_ETH_POWERPC_FCC
-                          CYGPKG_DEVS_ETH_POWERPC_RATTLER
-                          CYGPKG_DEVS_ETH_PHY
-                          CYGPKG_IO_SERIAL_POWERPC_MPC8XXX
-        }
-        description "
-            The rattler target provides the packages needed to run
-            eCos on an Analogue & Micro Rattler (MPC8250) board."
-}
-
-##-------------------------------------------------------------------------------------------
-## TAMS MOAB (PowerPC 405GPr) packages
-##
-package CYGPKG_HAL_POWERPC_MOAB {
-	alias		{ "TAMS PowerPC 405GP board" hal_powerpc_moab }
-	directory	hal/powerpc/moab
-	script		hal_powerpc_moab.cdl
-	hardware
-        description "
-            The MOAB HAL package provides the support needed to run
-            eCos on a TAMS PowerPC 405GP board."
-}
-
-package CYGPKG_DEVS_FLASH_POWERPC_MOAB {
-	alias 		{ "FLASH memory support for MOAB" flash_moab }
-	directory	devs/flash/powerpc/moab
-	script		flash_moab.cdl
-	hardware
-        description "
-           This package contains hardware support for both the boot FLASH 
-           and NAND (main) memory on the MOAB platform."
-}
-
-package CYGPKG_DEVS_ETH_POWERPC_MOAB {
-        alias           { "TAMS PowerPC 405GP ethernet support" moab_eth_driver }
-        hardware
-        directory       devs/eth/powerpc/moab
-        script          moab_eth_drivers.cdl
-        description     "Ethernet driver specifics for TAMS MOAB (PPC405GP) based boards."
-}
-
-package CYGPKG_DEVICES_WALLCLOCK_POWERPC_MOAB {
-         alias          { "MOAB RTC device" devs_wallclock_moab_ds1307 moab_rtc }
-         hardware
-         directory      devs/wallclock/powerpc/moab
-         script         moab_wallclock_drivers.cdl
-         description    "
-            RTC driver for MOAB (PowerPC PPC405GPr) using a
-            Dallas DS1307 RTC."
-}
-
-target moab {
-	alias		{ "TAMS PowerPC 405GPr" moab405GPr }
-	packages        { CYGPKG_HAL_POWERPC
-                          CYGPKG_HAL_POWERPC_PPC40x
-                          CYGPKG_HAL_POWERPC_MOAB
-                          CYGPKG_DEVS_FLASH_POWERPC_MOAB
-                          CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX
-                          CYGPKG_DEVS_FLASH_TOSHIBA_TC58XXX
-                          CYGPKG_DEVS_ETH_POWERPC_MOAB
-                          CYGPKG_DEVS_ETH_POWERPC_PPC405
-                          CYGPKG_DEVS_ETH_NS_DP83816
-                          CYGPKG_DEVS_ETH_PHY
-                          CYGPKG_IO_PCI
-                          CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1307
-                          CYGPKG_DEVICES_WALLCLOCK_POWERPC_MOAB
-                          CYGPKG_IO_SERIAL_GENERIC_16X5X
-                          CYGPKG_IO_SERIAL_POWERPC_PPC405
-        }
-        description "
-            The moab target provides the packages needed to run
-            eCos on the TAMS MOAB (405GPr) board."
-}
-##-------------------------------------------------------------------------------------------
-
-# --------------------------------------------------------------------------
-
-# Realtek 8139 (PCI) Ethernet driver
-package CYGPKG_DEVS_ETH_RLTK_8139 {
-	alias 		{ "Realtek 8139 ethernet driver" rltk8139_eth_driver }
-	hardware
-	directory	devs/eth/rltk/8139
-	script		rltk_8139_eth_drivers.cdl
-        description     "Ethernet driver for Realtek 8139 (PCI) card."
-}
-
-package CYGPKG_DEVS_ETH_I386_PC_RLTK8139 {
-	alias 		{ "Intel PC with Realtek 8139 ethernet driver" pc_rltk8139_eth_driver }
-	hardware
-	directory	devs/eth/i386/pc/rltk8139
-	script		i386_pc_rltk8139_eth_drivers.cdl
-        description     "Intel PC using Realtek 8139 (PCI) card."
-}
-
-package CYGPKG_DEVS_ETH_SH_DREAMCAST_RLTK8139 {
-	alias 		{ "SEGA Dreamcast with BroadBandAdapter driver" dreamcast_rltk8139_eth_driver }
-	hardware
-	directory	devs/eth/sh/dreamcast
-	script		sh_dreamcast_rltk8139_eth_drivers.cdl
-        description     "SEGA Dreamcast with BroadBandAdapter."
-}
-
-target pc_rltk8139 {
-        alias		{ "i386 PC target with RTL8139 ethernet" }
-	packages        { CYGPKG_HAL_I386
-                          CYGPKG_HAL_I386_GENERIC
-                          CYGPKG_HAL_I386_PC
-                          CYGPKG_HAL_I386_PCMB
-			  CYGPKG_IO_PCI
-                          CYGPKG_IO_SERIAL_GENERIC_16X5X
-	                  CYGPKG_IO_SERIAL_I386_PC
-			  CYGPKG_DEVS_ETH_RLTK_8139
-			  CYGPKG_DEVS_ETH_I386_PC_RLTK8139
-                          CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS12887
-                          CYGPKG_DEVICES_WALLCLOCK_I386_PC
-        }
-        description "
-    	    The pc_rltk8139 target provides the packages needed to run eCos binaries 
-            on a standard i386 PC motherboard, using a Realtek 8139 network card."
-}
-
-# --------------------------------------------------------------------------
-
-package CYGPKG_HAL_ARM_GPS4020 {
-	alias		{ "GPS4020" hal_gps4020 }
-	directory	hal/arm/gps4020
-	script		hal_arm_gps4020.cdl
-	hardware
-        description "
-            The GPS4020 HAL package provides the support needed to run
-            eCos on a GPS 4020 board using the Firefly MF1 (ARM) processor."
-}
-
-package CYGPKG_DEVS_FLASH_GPS4020 {
-	alias 		{ "FLASH memory support for GPS4020" flash_gps4020 }
-	directory	devs/flash/arm/gps4020
-	script		flash_gps4020.cdl
-	hardware
-        description "
-           This package contains hardware support for FLASH memory
-	   on the GPS4020 platform."
-}
-
-package CYGPKG_IO_SERIAL_ARM_GPS4020 {
-    alias             { "GPS4020 serial device drivers"
-                        devs_serial_arm_gps4020 gps4020_serial_driver }
-    hardware
-    directory	      devs/serial/arm/gps4020
-    script	      ser_arm_gps4020.cdl	
-    description       "GPS4020 serial device drivers"
-}
-
-target gps4020 {
-        alias		{ "GPS 4020" gps_4020 gps}
-	packages        { CYGPKG_HAL_ARM
-                          CYGPKG_HAL_ARM_GPS4020
-                          CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX
-                          CYGPKG_DEVS_FLASH_GPS4020
-                          CYGPKG_IO_SERIAL_ARM_GPS4020
-        }
-        description "
-            The gps4020 target provides the packages needed to run
-            eCos on a GPS-4020 board."
-}
-
-# --------------------------------------------------------------------------
-
-package CYGPKG_VNC_SERVER {
-    alias       { "VNC server" vnc_server }
-    directory   net/vnc_server
-    script      vnc-server.cdl
-    description "VNC server."
-}
-
-# --------------------------------------------------------------------------
-
-package CYGPKG_DEVS_DISK_V85X_EDB_V850 {
-    alias           { "Elatec v850 development board disk driver" edb_v850_disk }
-    directory       devs/disk/v85x/edb_v850
-    script          v85x_edb_v850_disk.cdl
-    hardware
-    description     "Disk driver for the Elatec v850 development board." 
-}
-
-package CYGPKG_DEVS_DISK_ECOSYNTH {
-    alias           { "Synthetic target disk driver" ecosynthdisk ecosynth_disk_driver }
-    directory       devs/disk/synth
-    script          synthdisk.cdl
-    hardware
-    description     "Disk driver for the synthetic target."
-}
-
-package CYGPKG_DEVS_DISK_IDE {
-    alias           { "Generic IDE disk driver" ide_disk }
-    directory       devs/disk/ide
-    script          ide_disk.cdl
-    description     "Disk driver for generic IDE interface." 
-}
-
-package CYGPKG_DEVS_DISK_MMC {
-    alias      { "Disk driver for MMC cards" mmcdisk mmc_disk_driver }
-    directory  devs/disk/generic/mmc
-    script     devs_disk_mmc.cdl
-    hardware
-    description "Disk driver for MMC cards"
-}
-
-package CYGPKG_IO_DISK {
-    alias           { "Disk device drivers" disk io_disk }
-    directory       io/disk
-    script          io_disk.cdl
-    description "
-        This package contains drivers for basic I/O services on
-        disk devices."
-}
-
-package CYGPKG_BLOCK_LIB {
-    alias       { "Block cache and access library" blib block_lib }
-    directory   services/blib
-    script      blib.cdl
-    description "
-        This package contains the block cache and access library."
-}
-
-package CYGPKG_FS_FAT {
-    alias       { "FAT Filesystem" fatfs fat_fs fs_fat }
-    directory   fs/fat
-    script      fatfs.cdl
-    description "
-        This package contains a FAT filesystem implementation."
-}
-
-
-# --------------------------------------------------------------------------
-
-package CYGPKG_IO_FRAMEBUF {
-        alias	   { "Frame buffer support" framebuf framebuffer io_framebuf framebuf_io }
-        directory  io/framebuf
-        script     framebuf.cdl
-        description "
-          The generic frame buffer package provides an API for accessing
-          frame buffer devices. It also provides support for writing
-          the corresponding the device drivers."
-}
-
-package CYGPKG_DEVS_FRAMEBUF_SYNTH {
-    alias		{ "Synthetic target framebuffer device driver" devs_framebuf_synth synth_framebuf_driver }
-    hardware
-    directory		devs/framebuf/synth
-    script		framebuf_synth.cdl
-    
-    description "
-        This package provides a framebuffer device driver for the
-        synthetic target."
-}
-
-# --------------------------------------------------------------------------
-
-package CYGPKG_NET_LWIP {
-	alias		{"lwIP" lwip}
-	directory	net/lwip_tcpip
-	script		cdl/lwip_net.cdl
-	description	"Lightweight TCP/IP stack: lwIP"
-}
-
-package CYGPKG_ATHTTPD {
-	alias 		{ "ATHTTP server" athttpd }
-	directory	net/athttpd
-	script		httpd.cdl
-    description "Another Tiny HTTP server."
-}
-
-
-# ==========================================================================
-# Cortex-M architecture support
-
-package CYGPKG_HAL_CORTEXM {
-	alias		{ "Cortex-M common HAL" hal_cortexm cortexm_hal cortexm_arch_hal }
-	directory	hal/cortexm/arch
-	script		hal_cortexm.cdl
-	hardware
-	description "
-        The CortexM architecture HAL package provides generic support for the ARM
-        Cortex-M processor architecture. It is also necessary to select
-        variant and platform HAL packages."
-}
-
-package CYGPKG_HAL_CORTEXM_STM32 {
-	alias		{ "ST STM32 variant HAL" hal_cortexm_stm32 }
-	directory	hal/cortexm/stm32/var
-	script		hal_cortexm_stm32.cdl
-	hardware
-        description "
-        The STM32 HAL package provides the support needed to run
-        eCos and RedBoot on targets based on the ST STM32
-        family of microcontrollers."
-}
-
-package CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL {
-	alias		{ "ST STM3210E EVAL HAL" hal_cortexm_stm3210e_eval }
-	directory	hal/cortexm/stm32/stm3210e_eval
-	script		hal_cortexm_stm32_stm3210e_eval.cdl
-	hardware
-        description "
-        The stm3210e_eval HAL package provides the support needed to run
-        eCos on the ST STM3210E EVAL board."
-}
-
-package CYGPKG_IO_SERIAL_CORTEXM_STM32 {
-        alias           { "ST STM32 serial device drivers"
-                          devs_serial_cortexm_stm32 stm32_serial_driver }
-        hardware
-        directory	devs/serial/cortexm/stm32
-        script	        ser_cortexm_stm32.cdl	
-        description     "ST STM32 serial device driver"
-}
-
-package CYGPKG_DEVS_FLASH_STM32 {
-        alias           { "Internal FLASH memory support for ST STM32" flash_stm32 }
-        directory       devs/flash/cortexm/stm32
-        script          flash_stm32.cdl
-        hardware
-        description "
-        This package contains hardware support for the internal FLASH memory
-        on the ST STM32 devices."
-}
-
-package CYGPKG_DEVS_SPI_CORTEXM_STM32 {
-    alias         { "STM32 SPI driver" }
-    hardware
-    directory     devs/spi/cortexm/stm32
-    script        spi_stm32.cdl
-    description   "This package provides a driver for the SPI interfaces found on 
-                  the ST STM32 microcontroller family."
-}
-
-package CYGPKG_DEVS_WALLCLOCK_STM32 {
-        alias           { "ST STM32 RTC wallclock support" wallclock_stm32 }
-        directory       devs/wallclock/cortexm/stm32
-        script          wallclock_stm32.cdl
-        hardware
-        description "
-        Wallclock support for on-chip RTC on STM32 devices.driver for the
-        STM32 controller and compatibles"
-}
-
-package CYGPKG_DEVS_ADC_CORTEXM_STM32 {
-    alias         { "STM32 ADC driver" adc_stm32 }
-    hardware
-    directory     devs/adc/cortexm/stm32
-    script        adc_stm32.cdl
-    description "
-    This package provides a driver for the ADC interfaces found on the
-    ST STM32 microcontroller family."
-}
-
-target stm3210e_eval {
-        alias { "ST STM3210E EVAL board" stm3210e }
-        packages { CYGPKG_HAL_CORTEXM
-                   CYGPKG_HAL_CORTEXM_STM32
-                   CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL
-                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2
-                   CYGPKG_DEVS_FLASH_STM32
-                   CYGPKG_DEVS_FLASH_SPI_M25PXX
-                   CYGPKG_IO_SERIAL_CORTEXM_STM32
-                   CYGPKG_DEVS_WALLCLOCK_STM32
-                   CYGPKG_IO_SPI
-                   CYGPKG_DEVS_SPI_CORTEXM_STM32
-                   CYGPKG_DEVS_ADC_CORTEXM_STM32
-                   CYGPKG_DEVS_NAND_ST_NANDXXXX3A
-                 }
-        description "The stm3210e_eval target provides the packages needed
-        to run eCos on the STM3210E EVAL board."
-}
-
-# ==========================================================================
-# NAND packages
-
-package CYGPKG_IO_NAND {
-    alias       { "NAND flash memory support" nand io_nand }
-    directory   io/nand
-    script      nand.cdl
-    description     "
-        This package provides the NAND flash access library.
-		Further platform-specific package(s) are required to implement
-		support for the specific devices present."
-}
-
-package CYGPKG_DEVS_NAND_SAMSUNG_K9 {
-    alias       { "Samsung K9 NAND chip family support" nand_samsung_k9 }
-    directory   devs/nand/samsung_k9
-    script      k9fxx08x0a.cdl
-    description     "
-		This package provides support for the Samsung K9Fxx08x0A family of NAND 
-        flash devices."
-}
-
-package CYGPKG_DEVS_NAND_SYNTH {
-	alias 		{ "Synthetic NAND device" nand_synth }
-	directory	devs/nand/synth
-	script		nand_synth.cdl
-	description "
-		This package provides a synthetic NAND device, for testing purposes."
-}
-
-package CYGPKG_DEVS_NAND_ST_NANDXXXX3A {
-    alias       { "ST Microelectronics NANDxxxx3A chip family support" nand_st_nandxxxx3a }
-    directory   devs/nand/st/nandxxxx3a
-    script      nandxxxx3a.cdl
-    description     "
-        This package provides support for the ST Microelectronics family of
-        NANDxxxx3A flash devices."
-}
-
-package CYGPKG_DEVS_NAND_MICRON_MT29F {
-    alias       { "Micron MT29F NAND chip family support" nand_micron_mt29f }
-    directory   devs/nand/micron_mt29
-    script      mt29f.cdl
-    hardware
-    description     "
-		This package provides support for the Micron MT29F family of NAND 
-        flash devices."
-}
-
-package CYGPKG_DEVS_NAND_ARM_AT91SAM9 {
-    alias       { "Common NAND support for the AT91SAM926X family" nand_at91sam926x }
-    directory   devs/nand/arm/at91sam9
-    script      devs_nand_arm_at91sam9.cdl
-    hardware
-    description "Common support definitions and code for the NAND support
-        hardware found on the Atmel AT91SAM926X chip family."
-}
-
-# ==========================================================================
-# End of ecos.db
+containers, streams, iterators, algorithms and functors."
+}
+
+package CYGPKG_ERROR {
+	alias 		{ "Common error code support" error errors }
+	directory	error
+	script		error.cdl
+        description  "
+This package contains the common list of error and status codes. It is
+held centrally to allow packages to interchange error codes and status
+codes in a common way, rather than each package having its own
+conventions for error/status reporting. The error codes are modelled
+on the POSIX style naming e.g. EINVAL etc. This package also provides
+the standard strerror() function to convert error codes to textual
+representation, as well as an implementation of the errno idiom."
+}
+package CYGPKG_CYGMON {
+    alias           { "CygMon support via eCos" cygmon }
+    directory       cygmon
+    script          cygmon.cdl
+    description     "
+        This package supports the CygMon \[stand-alone debug monitor\]
+        using eCos as the underlying board support mechanism."
+}
+
+package CYGPKG_REDBOOT {
+    alias           { "RedBoot ROM monitor" redboot }
+    directory       redboot
+    script          redboot.cdl
+    description     "
+        This package creates the RedBoot \[stand-alone bootstrap & debug monitor\]
+        using eCos as the underlying board support mechanism."
+}
+
+package CYGPKG_MICROWINDOWS {
+	alias 		{ "Microwindows" mw }
+	directory	services/gfx/mw
+	script		microwindows.cdl
+        description     "Microwindows."
+}
+
+package CYGPKG_HAL_SH_SH7750_DREAMCAST {
+	alias		{ "SEGA Dreamcast" hal_sh_dreamcast sh_dreamcast_hal }
+	directory	hal/sh/dreamcast
+	script		hal_sh_sh7750_dreamcast.cdl
+	hardware
+        description "
+           This SH HAL package provides the support needed to run
+           eCos on SEGA Dreamcast."
+}
+
+# --------------------------------------------------------------------------
+# ARM packages
+package CYGPKG_HAL_ARM {
+	alias		{ "ARM common HAL" hal_arm arm_hal arm_arch_hal }
+	directory	hal/arm/arch
+	script		hal_arm.cdl
+	hardware
+	description "
+The ARM architecture HAL package provides generic support for this
+processor architecture. It is also necessary to select a specific
+target platform HAL package."
+}
+
+package CYGPKG_HAL_ARM_PID {
+	alias		{ "ARM development board (PID)" hal_arm_pid arm_pid_hal }
+	directory	hal/arm/pid
+	script		hal_arm_pid.cdl
+	hardware
+        description "
+The pid HAL package provides the support needed to run eCos on a ARM
+PID eval board."
+}
+
+package CYGPKG_HAL_ARM_AEB {
+	alias		{ "ARM evaluation board (AEB-1)" hal_arm_aeb arm_aeb_hal }
+	directory	hal/arm/aeb
+	script		hal_arm_aeb.cdl
+	hardware
+        description "
+The aeb HAL package provides the support needed to run eCos on a ARM
+AEB-1 eval board."
+}
+
+package CYGPKG_HAL_ARM_E7T {
+	alias		{ "ARM Evaluator7T board (AEB-2)" hal_arm_e7t arm_e7t_hal }
+	directory	hal/arm/e7t
+	script		hal_arm_e7t.cdl
+	hardware
+        description "
+The e7t HAL package provides the support needed to run eCos on a ARM
+Evaluator7T board (aka the AEB-2)."
+}
+
+package CYGPKG_HAL_ARM_INTEGRATOR {
+        alias           { "ARM development board (INTEGRATOR)" hal_arm_integrator arm_integrator_hal }
+        directory       hal/arm/integrator
+        script          hal_arm_integrator.cdl
+        hardware
+        description "
+        The INTEGRATOR HAL package provides the support needed to 
+        run eCos on a ARM INTEGRATOR eval board."
+}
+
+package CYGPKG_HAL_ARM_AT91 {
+	alias		{ "Atmel AT91 variant HAL" hal_arm_at91 arm_at91_hal }
+	directory	hal/arm/at91/var
+	script		hal_arm_at91.cdl
+	hardware
+        description "
+        The at91 HAL package provides the support needed to run eCos on Atmel
+        AT91 based targets."
+}
+
+package CYGPKG_HAL_ARM_AT91_JTST {
+	alias		{ "Atmel AT572D740 (diopsis) evaluation board (jtst)" hal_arm_at91_jtst arm_at91_jtst_hal }
+	directory	hal/arm/at91/jtst
+	script		hal_arm_at91_jtst.cdl
+	hardware
+        description "
+	The JTST HAL package provides the support needed to run eCos on 
+        the Atmel evaluation board AT572D74-DK1."
+}
+
+package CYGPKG_HAL_ARM_AT91SAM7 {
+	alias		{ "Atmel AT91SAM7" hal_arm_at91sam7 arm_at91_sam7 }
+	directory	hal/arm/at91/at91sam7s
+	script		hal_arm_at91sam7s.cdl
+	hardware
+        description "
+	The at91sam7 HAL package provides the support needed to run eCos on 
+        an Atmel AT91SAM7 family of CPUs."
+}
+
+package CYGPKG_HAL_ARM_AT91SAM7SEK {
+	alias		{ "Atmel AT91SAM7S" hal_arm_at91sam7sek arm_at91_sam7sek }
+	directory	hal/arm/at91/at91sam7sek
+	script		hal_arm_at91sam7sek.cdl
+	hardware
+        description "
+	The at91sam7sek HAL package provides the support needed to run eCos on 
+        an Atmel AT91SAM7S-EK development board."
+}
+
+package CYGPKG_HAL_ARM_AT91SAM7XEK {
+	alias		{ "Atmel AT91SAM7X" hal_arm_at91sam7xek arm_at91_sam7xek }
+	directory	hal/arm/at91/at91sam7xek
+	script		hal_arm_at91sam7xek.cdl
+	hardware
+        description "
+	The at91sam7xek HAL package provides the support needed to run eCos on 
+        an Atmel AT91SAM7X-EK development board."
+}
+
+package CYGPKG_HAL_ARM_SAM7EX256 {
+	alias		{ "Olimex SAM7EX256" hal_arm_sam7ex256 arm_sam7_ex256 }
+	directory	hal/arm/at91/sam7ex256
+	script		hal_arm_sam7ex256.cdl
+	hardware
+        description "
+	The SAM7EX256 HAL package provides the support needed to run eCos on 
+        an Olimex SAM7-EX256 development board."
+}
+
+package CYGPKG_HAL_ARM_AT91_EB40 {
+	alias		{ "Atmel evaluation board (EB40)" hal_arm_at91_eb40 arm_at91_eb40_hal }
+	directory	hal/arm/at91/eb40
+	script		hal_arm_at91_eb40.cdl
+	hardware
+        description "
+	The eb40 HAL package provides the support needed to run eCos on an Atmel
+	evaluation board (EB40)."
+}
+
+package CYGPKG_HAL_ARM_AT91_EB40A {
+	alias		{ "Atmel evaluation board (EB40A)" hal_arm_at91_eb40a arm_at91_eb40a_hal }
+	directory	hal/arm/at91/eb40a
+	script		hal_arm_at91_eb40a.cdl
+	hardware
+        description "
+	The eb40a HAL package provides the support needed to run eCos on an Atmel
+	evaluation board (EB40A)."
+}
+
+package CYGPKG_HAL_ARM_AT91_EB42 {
+	alias		{ "Atmel evaluation board (EB42)" hal_arm_at91_eb42 arm_at91_eb42_hal }
+	directory	hal/arm/at91/eb42
+	script		hal_arm_at91_eb42.cdl
+	hardware
+        description "
+	The eb42 HAL package provides the support needed to run eCos on an Atmel
+	evaluation board (EB42)."
+}
+
+package CYGPKG_HAL_ARM_AT91_EB55 {
+	alias		{ "Atmel evaluation board (EB55)" hal_arm_at91_eb55 arm_at91_eb55_hal }
+	directory	hal/arm/at91/eb55
+	script		hal_arm_at91_eb55.cdl
+	hardware
+        description "
+	The eb55 HAL package provides the support needed to run eCos on an 
+        Atmel evaluation board (EB55)."
+}
+
+package CYGPKG_HAL_ARM_AT91_PHYCORE {
+	alias		{ "PHYTEC evaluation board (phyCORE AT91M55800A)" hal_arm_at91_phycore arm_at91_phycore_hal }
+	directory	hal/arm/at91/phycore
+	script		hal_arm_at91_phycore.cdl
+	hardware
+        description "
+	The phyCORE HAL package provides the support needed to run eCos on 
+        an PHYTEC evaluation board (phyCORE AT91M55800A based on HD200)."
+} 
+
+package CYGPKG_HAL_ARM_LPC2XXX {
+        alias           { "Philips LPC2XXX variant HAL" hal_arm_lpc2xxx arm_lpc2xxx_hal }
+        directory       hal/arm/lpc2xxx/var
+        script          hal_arm_lpc2xxx.cdl
+        hardware
+        description "
+        The LPC2XXX HAL package provides the support needed to run eCos on
+        Philips LPC2XXX based targets."
+}
+
+package CYGPKG_HAL_ARM_LPC24XX {
+        alias           { "NXP LPC24XX variant HAL" hal_arm_lpc24xx arm_lpc24xx_hal }
+        directory       hal/arm/lpc24xx/var
+        script          hal_arm_lpc24xx.cdl
+        hardware
+        description "
+        The LPC24XX HAL package provides the support needed to run eCos on
+        NXP LPC24XX based targets."
+}
+
+package CYGPKG_HAL_ARM_LPC2XXX_MCB2100 {
+        alias           { "Keil evaluation board MCB2100 " hal_mcb2100_arm }
+        directory       hal/arm/lpc2xxx/mcb2100
+        script          hal_arm_lpc2xxx_mcb2100.cdl
+        hardware
+        description "
+        The mcb2100 HAL package provides the support needed to run eCos on an 
+        the MCB2100 evaluation board from Keil."
+}
+
+package CYGPKG_HAL_ARM_LPC2XXX_P2106 {
+        alias           { "Olimex evaluation board LPC-P2106 " hal_p2106_arm }
+        directory       hal/arm/lpc2xxx/p2106
+        script          hal_arm_lpc2xxx_p2106.cdl
+        hardware
+        description "
+        The p2106 HAL package provides the support needed to run eCos on an the
+        LPC-2106 evaluation board from Olimex."
+}
+
+package CYGPKG_HAL_ARM_LPC2XXX_PHYCORE229X {
+        alias           { "phyCORE-LPC229x development board" arm_lpc2xxx_phycore229x }
+        directory       hal/arm/lpc2xxx/phycore229x
+        script          hal_arm_lpc2xxx_phycore229x.cdl
+        hardware
+        description "
+            The Phycore HAL package provides the support needed to run eCos 
+            on a Phytec phyCORE-LPC229x development board."
+}
+
+package CYGPKG_HAL_ARM_LPC24XX_EA2468 {
+        alias           { "Embedded Artists LPC2468 OEM board" arm_lpc2xxx_ea2468 }
+        directory       hal/arm/lpc24xx/ea2468
+        script          hal_arm_lpc24xx_ea2468.cdl
+        hardware
+        description "
+            The Embedded Artists LPC2468 HAL package provides the support needed 
+            to run eCos on a Embbeded Artists LPC2468 OEM board."
+}
+
+package CYGPKG_HAL_ARM_LPC2XXX_LPCMT {
+	alias		{ "Olimex evaluation board LPC-MT " hal_lpcmt_arm }
+	directory	hal/arm/lpc2xxx/lpcmt
+	script		hal_arm_lpc2xxx_lpcmt.cdl
+	hardware
+	description "
+	The lpcmt HAL package provides the support needed to run eCos on an the 
+	LPC-MT evaluation board from Olimex."
+}
+
+package CYGPKG_HAL_ARM_LPC2XXX_OLPCH2294 {
+        alias           { "Olimex LPC-H2294 header board" hal_olpch2294_arm }
+        directory       hal/arm/lpc2xxx/olpch2294
+        script          hal_arm_lpc2xxx_olpch2294.cdl
+        hardware
+        description "
+            The olpch2294 HAL package provides the support needed to
+            run eCos on the Olimex LPC-H2294 header board."
+}
+
+package CYGPKG_HAL_ARM_LPC2XXX_OLPCE2294 {
+        alias           { "Olimex LPC-E2294 development board" hal_olpce2294_arm }
+        directory       hal/arm/lpc2xxx/olpce2294
+        script          hal_arm_lpc2xxx_olpce2294.cdl
+        hardware
+        description "
+            The olpce2294 HAL package provides the support needed to
+            run eCos on Olimex LPC-E2294 development board."
+}
+
+package CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294 {
+        alias           { "Olimex LPC-L2294-1MB development board" hal_olpcl2294_arm }
+        directory       hal/arm/lpc2xxx/olpcl2294
+        script          hal_arm_lpc2xxx_olpcl2294.cdl
+        hardware
+        description "
+            The olpcl2294 HAL package provides the support needed to run
+            eCos on Olimex LPC-L2294-1MB development board."
+}
+
+package CYGPKG_HAL_ARM_MAC7100 {
+	alias		{ "Freescale MAC7100 variant HAL" hal_arm_mac7100 arm_mac7100_hal }
+	directory	hal/arm/mac7100/var
+	script		hal_arm_mac7100.cdl
+	hardware
+        description "
+        The mac7100 HAL package provides the support needed to run eCos on Freescale
+        MAC7100 based targets."
+}
+
+package CYGPKG_HAL_ARM_MAC7100_MACE1 {
+	alias		{ "MAC7100 evaluation board (MACE1)" hal_arm_mac7100_mace1 arm_mac7100_mace1_hal }
+	directory	hal/arm/mac7100/mace1
+	script		hal_arm_mac7100_mace1.cdl
+	hardware
+        description "
+	The MACE1 HAL package provides the support needed to run eCos on an 
+        MAC7100 evaluation board (MACE1)."
+}
+
+package CYGPKG_HAL_ARM_MAC7100_MAC7100EVB {
+	alias		{ "MAC7100EVB evaluation board (Freescale)" hal_arm_mac7100_mac7100evb arm_mac7100_mac7100evb_hal }
+	directory	hal/arm/mac7100/mac7100evb
+	script		hal_arm_mac7100_mac7100evb.cdl
+	hardware
+        description "
+	The MAC7100EVB HAL package provides the support needed to run eCos on an 
+        MAC7100 evaluation board (MAC7100EVB)."
+}
+
+package CYGPKG_HAL_ARM_EBSA285 {
+	alias		{ "Intel EBSA285 StrongARM board" hal_arm_ebsa285 arm_ebsa285_hal }
+	directory	hal/arm/ebsa285
+	script		hal_arm_ebsa285.cdl
+	hardware
+        description "
+        The EBSA285 HAL package provides the support needed to run
+        eCos on a Intel EBSA285 StrongARM eval board."
+}
+
+package CYGPKG_HAL_ARM_ARM9 {
+	alias		{ "ARM9 variant" hal_arm_arm9 }
+	directory	hal/arm/arm9/var
+	script		hal_arm_arm9.cdl
+	hardware
+        description "
+        The ARM9 HAL package provides the support needed to run
+        eCos on a ARM9 based systems."
+}
+
+
+package CYGPKG_HAL_ARM_ARM9_AAED2000 {
+	alias		{ "Agilent AAED2000 unit" hal_arm_arm9_aaed }
+	directory	hal/arm/arm9/aaed2000
+	script		hal_arm_arm9_aaed2000.cdl
+	hardware
+        description "
+        The AAED2000 HAL package provides the support needed to run
+        eCos on an Agilent AAED2000 board."
+}
+
+package CYGPKG_HAL_ARM_ARM9_EXCALIBUR {
+	alias		{ "Altera Excalibur ARM9 board" hal_arm_arm9_excalibur }
+	directory	hal/arm/arm9/excalibur
+	script		hal_arm_arm9_excalibur.cdl
+	hardware
+        description "
+        The Excalibur HAL package provides the support needed to run
+        eCos on an Altera Excalibur ARM9 board."
+}
+
+package CYGPKG_HAL_ARM_ARM9_SMDK2410 {
+        alias           { "Samsung ARM9/SMDK2410 development board" hal_arm_arm9_smdk2410 }
+        directory       hal/arm/arm9/smdk2410
+        script          hal_arm_arm9_smdk2410.cdl
+        hardware
+        description "
+        The SMDK2410 HAL package provides the support needed to run
+        eCos on Samsung SMDK2410 and S3c2410x (ARM9) based development boards."
+}
+
+package CYGPKG_HAL_ARM_ARM9_INNOVATOR {
+	alias		{ "Innovator (ARM)" hal_arm_arm9_innovator }
+	directory	hal/arm/arm9/innovator
+	script		hal_arm_arm9_innovator.cdl
+	hardware
+        description "
+        The Innovator HAL package provides the support needed to run
+        RedBoot on the ARM processor of the Innovator.
+	
+	NOTE: Full support for eCos is not provided yet.  This HAL
+	contains only the minimum amount necessary to run RedBoot
+	on the Innovator.  In particular, interrupts are not yet
+	supported.  Watch this space for more details in the near
+	future."
+}
+
+package CYGPKG_HAL_ARM_SA11X0 {
+	alias		{ "Intel SA11X0 Chipset" hal_arm_sa11x0 }
+	directory	hal/arm/sa11x0/var
+	script		hal_arm_sa11x0.cdl
+	hardware
+        description "
+        The SA11X0 HAL package provides the support needed to run
+        eCos on a Intel StrongARM SA11X0 based systems."
+}
+
+package CYGPKG_HAL_ARM_SA11X0_ASSABET {
+	alias		{ "Intel SA1110 Assabet eval board" hal_arm_sa11x0_assabet }
+	directory	hal/arm/sa11x0/assabet
+	script		hal_arm_sa11x0_assabet.cdl
+	hardware
+        description "
+        The ASSABET HAL package provides the support needed to run
+        eCos on a Intel StrongARM SA1110 evaluation board (assabet)."
+}
+
+package CYGPKG_HAL_ARM_SA11X0_CERF {
+	alias		{ "Intrinsyc Cerf board" hal_arm_sa11x0_cerf }
+	directory	hal/arm/sa11x0/cerf
+	script		hal_arm_sa11x0_cerf.cdl
+	hardware
+        description "
+        The CERF HAL package provides the support needed to run
+        eCos on a Intrinsyc StrongARM SA1110 Cerf board."
+}
+
+package CYGPKG_HAL_ARM_SA11X0_CERFPDA {
+	alias		{ "Intrinsyc Cerfpda" hal_arm_sa11x0_cerfpda }
+	directory	hal/arm/sa11x0/cerfpda
+	script		hal_arm_sa11x0_cerfpda.cdl
+	hardware
+        description "
+        The CERFPDA HAL package provides the support needed to run
+        eCos on a Intrinsyc StrongARM SA1110 Cerfpda."
+}
+
+package CYGPKG_HAL_ARM_SA11X0_IPAQ {
+	alias		{ "Compaq iPAQ Pocket PC" hal_arm_sa11x0_ipaq }
+	directory	hal/arm/sa11x0/ipaq
+	script		hal_arm_sa11x0_ipaq.cdl
+	hardware
+        description "
+        The IPAQ HAL package provides the support needed to run
+        eCos on a Intel StrongARM SA1110 pocket PC (Compaq iPAQ)."
+}
+
+package CYGPKG_HAL_ARM_SA11X0_FLEXANET {
+      alias           { "SA1110 Flexanet board" hal_arm_sa11x0_flexanet }
+      directory       hal/arm/sa11x0/flexanet
+      script          hal_arm_sa11x0_flexanet.cdl
+      hardware
+      description "
+        The FLEXANET HAL package provides the support needed to run
+        eCos on an SA1110 Flexanet board."
+}
+
+package CYGPKG_HAL_ARM_SNDS {
+      alias       { "Samsung SNDS" hal_arm_snds arm_snds_hal}
+      directory   hal/arm/snds
+      script      hal_arm_snds.cdl
+      hardware
+      description "
+          The SNDS HAL package provides the support needed to run eCos on a
+          Samsung SNDS eval board"
+}
+
+package CYGPKG_DEVS_ETH_SMSC_LAN91CXX {
+	alias 		{ "SMSC LAN91CXX ethernet driver" lan91cxx_eth_driver lan9000_eth_driver }
+	hardware
+	directory	devs/eth/smsc/lan91cxx
+	script		smsc_lan91cxx_eth_drivers.cdl
+        description     "Ethernet driver for SMSC LAN91CXX (LAN9000) controller."
+}
+
+
+package CYGPKG_HAL_ARM_SA11X0_NANO {
+	alias		{ "Intel SA1110 nanoEngine eval board" hal_arm_sa11x0_nano }
+	directory	hal/arm/sa11x0/nano
+	script		hal_arm_sa11x0_nano.cdl
+	hardware
+        description "
+        The nanoEngine HAL package provides the support needed to run
+        eCos on the Bright Star Engineering nanoEngine StrongARM SA1110 board."
+}
+
+package CYGPKG_DEVS_ETH_ARM_NANO {
+	alias 		{ "BSE nanoEngine with 82559 ethernet driver"
+			   devs_eth_arm_nano nano_eth_driver }
+	hardware
+	directory	devs/eth/arm/nano
+	script		nano_eth_drivers.cdl
+        description     "Ethernet driver for SA11x0 nanoEngine with Intel
+                         i82559 ethernet interfaces."
+}
+
+package CYGPKG_HAL_ARM_SA11X0_BRUTUS {
+	alias		{ "Intel SA1100 Brutus eval board" hal_arm_sa11x0_brutus }
+	directory	hal/arm/sa11x0/brutus
+	script		hal_arm_sa11x0_brutus.cdl
+	hardware
+        description "
+        The BRUTUS HAL package provides the support needed to run
+        eCos on a Intel StrongARM SA1110 evaluation board (brutus)."
+}
+
+package CYGPKG_HAL_ARM_SA11X0_SA1100MM {
+	alias		{ "Intel SA1100 Multimedia eval board" hal_arm_sa11x0_sa1100mm }
+	directory	hal/arm/sa11x0/sa1100mm
+	script		hal_arm_sa11x0_sa1100mm.cdl
+	hardware
+        description "
+        The MULTIMEDIA HAL package provides the support needed to run
+        eCos on a Intel StrongARM SA1110 Multimedia evaluation board."
+}
+
+package CYGPKG_HAL_ARM_EDB7XXX {
+	alias		{ "Cirrus Logic ARM7 based development boards" hal_arm_edb7xxx arm_edb7xxx_hal }
+	directory	hal/arm/edb7xxx
+	script		hal_arm_edb7xxx.cdl
+	hardware
+        description "
+The EDB7XXX HAL package provides the support needed to run eCos on Cirrus Logic CL-PS7111 and EP7xxx based development boards."
+}
+
+package CYGPKG_HAL_ARM_CMA230 {
+	alias		{ "Cogent CMA230/222 board" hal_arm_cma230 arm_cma230_hal }
+	directory	hal/arm/cma230
+	script		hal_arm_cma230.cdl
+	hardware
+        description "
+The cma230 HAL package provides the support needed to run eCos on a Cogent 
+CMA230 (ARM7TDMI) or CMA222 (ARM710T) eval board."
+}
+
+package CYGPKG_HAL_ARM_AIM711 {
+      alias       { "ARM Industial Module AIM 711" hal_arm_aim711 arm_aim711_hal}
+      directory   hal/arm/aim711
+      script      hal_arm_aim711.cdl
+      hardware
+      description "
+          The ARM Industial Module AIM 711 HAL package provides the support
+          needed to run eCos on a ARM Industial Module AIM 711 from
+          Vision Systems GmbH."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_CORE {
+	alias		{ "Intel XScale Core" hal_arm_xscale_core }
+	directory	hal/arm/xscale/cores
+	script		hal_arm_xscale_core.cdl
+	hardware
+        description "
+        The XScale core HAL package provides the support needed to run eCos
+        on all Intel XScale based systems."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_IOP310 {
+	alias		{ "Intel IOP8310 (IQ80200/IQ80310) XScale chipset" hal_arm_iop310 arm_iop310_hal }
+	directory	hal/arm/xscale/iop310
+	script		hal_arm_xscale_iop310.cdl
+	hardware
+	description "
+	The IOP310 HAL package provides the support needed to run
+	eCos on a system using the Intel XScale IOP310 (IQ80200/80310) chipset."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_IQ80310 {
+	alias		{ "Intel IQ80310 (Cyclone) eval board" hal_arm_xscale_iq80310 hal_arm_xscale_cyclone }
+	directory	hal/arm/xscale/iq80310
+	script		hal_arm_xscale_iq80310.cdl
+	hardware
+	description "
+	The IQ80310 HAL package provides the support needed to run
+	eCos on an Intel Cyclone evaluation board, utilizing an Intel XScale 
+        IQ80200/80310 chipset."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_NPWR {
+	alias		{ "NPWR Linux Engine" hal_arm_xscale_npwr }
+	directory	hal/arm/xscale/npwr
+	script		hal_arm_xscale_npwr.cdl
+	hardware
+	description "
+	The NPWR HAL package provides the support needed to run
+	eCos on a NPWR Linux Engine, utilizing an Intel XScale 
+        IQ80200/80310 chipset."
+}
+
+package CYGPKG_DEVS_ETH_ARM_XSCALE_NPWR {
+	alias 		{ "NPWR Linux Engine ethernet drivers" devs_eth_arm_xscale_npwr }
+	hardware
+	directory	devs/eth/arm/npwr
+	script		npwr_eth_drivers.cdl
+        description     "Ethernet drivers for NPWR Linux Engine via 82544 NIC."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_VERDE {
+	alias		{ "Intel XScale 80320 I/O Processor" hal_arm_xscale_verde }
+	directory	hal/arm/xscale/verde
+	script		hal_arm_xscale_verde.cdl
+	hardware
+        description "
+        The XSCALE HAL package provides the support needed to run
+        eCos on Intel 80320 based systems."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_IQ80321 {
+	alias		{ "Intel XScale IQ80321 eval board" hal_arm_xscale_iq80321 }
+	directory	hal/arm/xscale/iq80321
+	script		hal_arm_xscale_iq80321.cdl
+	hardware
+        description "
+        The IQ80321 HAL package provides the support needed to run
+        eCos on an Intel XScale IQ80321 evaluation board."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_IXP425 {
+	alias		{ "Intel XScale IXP425 Network Processor" hal_arm_xscale_ixp425 }
+	directory	hal/arm/xscale/ixp425
+	script		hal_arm_xscale_ixp425.cdl
+	hardware
+        description "
+        The XScale IXP425 HAL package provides the support needed to run
+        eCos on Intel XScale IXP425 network processor based systems."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_XSENGINE {
+       alias           { "Exys XSEngine" hal_arm_xscale_xsengine }
+       directory       hal/arm/xscale/xsengine
+       script          hal_arm_xscale_xsengine.cdl
+       hardware
+       description "
+         The XSEngine HAL package provides the support needed to run
+         eCos on an Exys XSEngine board."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_IXDP425 {
+	alias		{ "Intel XScale IXDP425 Network Processor eval board" hal_arm_xscale_ixdp425 }
+	directory	hal/arm/xscale/ixdp425
+	script		hal_arm_xscale_ixdp425.cdl
+	hardware
+        description "
+        The IXDP425 HAL package provides the support needed to run
+        eCos on an Intel XScale IXDP425 network processor evaluation board."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_GRG {
+	alias		{ "Intel XScale Generic Residential Gateway" hal_arm_xscale_grg }
+	directory	hal/arm/xscale/grg
+	script		hal_arm_xscale_grg.cdl
+	hardware
+        description "
+        The GRG HAL package provides the support needed to run eCos on an
+        Intel Generic Residential Gateway evaluation board."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_PRPMC1100 {
+	alias		{ "Motorola PrPMC1100 PMC for Intel XScale IXC1100" hal_arm_xscale_prpmc1100 }
+	directory	hal/arm/xscale/prpmc1100
+	script		hal_arm_xscale_prpmc1100.cdl
+	hardware
+        description "
+        The PrPMC1100 HAL package provides the support needed to run eCos on an
+        Motorola PrPMC1100 evaluation board."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_PXA2X0 {
+	alias		{ "Intel PXA2X0" hal_arm_xscale_pxa2x0 }
+	directory	hal/arm/xscale/pxa2x0
+	script		hal_arm_xscale_pxa2x0.cdl
+	hardware
+		description "
+		The PXA2X0 HAL package provides the support needed to run
+		eCos on Intel PXA2X0 based systems."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_MPC50 {
+	alias		{ "MICROPLEX Printer Controller 5.0" hal_arm_xscale_mpc50 }
+	directory	hal/arm/xscale/mpc50
+	script		hal_arm_xscale_mpc50.cdl
+	hardware
+        description "
+        The MPC50 HAL package provides the support needed to run
+        eCos on a MPC 5.0."
+}
+
+# --------------------------------------------------------------------------
+# SH packages
+package CYGPKG_HAL_SH {
+	alias		{ "SH common HAL" hal_sh sh_hal sh_arch_hal }
+	directory	hal/sh/arch
+	script		hal_sh.cdl
+	hardware
+	description "
+           The SH (SuperH) architecture HAL package provides generic
+           support for this processor architecture. It is also
+           necessary to select variant and target platform HAL
+           packages."
+}
+
+package CYGPKG_HAL_SH_SH2 {
+    alias         { "SH2 architecture" hal_sh_sh2 }
+    directory     hal/sh/sh2
+    script        hal_sh_sh2.cdl
+    hardware
+    description   "
+        The SH2 (SuperH 2) variant HAL package provides generic
+        support for SH2 variant CPUs."
+}
+
+package CYGPKG_HAL_SH_SH3 {
+    alias         { "SH3 architecture" hal_sh_sh3 }
+    directory     hal/sh/sh3
+    script        hal_sh_sh3.cdl
+    hardware
+    description   "
+        The SH3 (SuperH 3) variant HAL package provides generic
+        support for SH3 variant CPUs."
+}
+
+package CYGPKG_HAL_SH_SH4 {
+    alias         { "SH4 architecture" hal_sh_sh4 }
+    directory     hal/sh/sh4
+    script        hal_sh_sh4.cdl
+    hardware
+    description   "
+        The SH4 (SuperH 4) variant HAL package provides generic
+        support for SH4 variant CPUs."
+}
+
+package CYGPKG_HAL_SH_EDK7708 {
+	alias		{ "Hitachi SH7708 board" hal_sh_edk sh_edk_hal }
+	directory	hal/sh/edk7708
+	script		hal_sh_edk7708.cdl
+	hardware
+        description "
+           This SH HAL package provides the support needed to run
+           eCos on a Hitachi SH3 EDK7708 board."
+}
+
+package CYGPKG_HAL_SH_SH7708_CQ7708 {
+        alias           { "CqREEK SH7708 board" hal_sh_cq sh_cq_hal }
+        directory       hal/sh/cq7708
+        script          hal_sh_sh7708_cq7708.cdl
+        hardware
+        description "
+           This SH HAL package provides the support needed to run
+           eCos on a CqREEK SH7708 board."
+}
+
+package CYGPKG_HAL_SH_SH7750_CQ7750 {
+	alias		{ "CqREEK SH7750 board" hal_sh_cqsh4 sh_cqsh4_hal }
+	directory	hal/sh/cq7750
+	script		hal_sh_sh7750_cq7750.cdl
+	hardware
+        description "
+           This SH HAL package provides the support needed to run
+           eCos on a CqREEK SH7750 board."
+}
+
+
+package CYGPKG_HAL_SH_SH7729_HS7729PCI {
+	alias		{ "Hitachi HS7729PCI board" hal_sh_sh7729_hs7729pci sh_sh7729_hs7729pci_hal }
+	directory	hal/sh/hs7729pci
+	script		hal_sh_sh7729_hs7729pci.cdl
+	hardware
+        description "
+           This SH HAL package provides the support needed to run
+           eCos on a Hitachi HS7729PCI board."
+}
+
+package CYGPKG_HAL_SH_SH77X9_SE77X9 {
+	alias		{ "Hitachi SE77x9 board" hal_sh_sh77x9_se77x9 sh_sh77x9_se77x9_hal }
+	directory	hal/sh/se77x9
+	script		hal_sh_sh77x9_se77x9.cdl
+	hardware
+        description "
+           This SH HAL package provides the support needed to run
+           eCos on a Hitachi Solution Engine 77x9 board."
+}
+
+package CYGPKG_HAL_SH_SH7751_SE7751 {
+	alias		{ "Hitachi SE7751 board" hal_sh_sh7751_se7751 sh_sh7751_se7751_hal }
+	directory	hal/sh/se7751
+	script		hal_sh_sh7751_se7751.cdl
+	hardware
+        description "
+           This SH HAL package provides the support needed to run
+           eCos on a Hitachi Solution Engine 7751 board."
+}
+
+package CYGPKG_HAL_SH_SH4_202_MD {
+    alias         { "SuperH SH4-202 MicroDev CPU Board" hal_sh_sh4_202_md }
+    directory     hal/sh/sh4_202_md
+    script        hal_sh_sh4_202_md.cdl
+    hardware
+    description   "
+        The SH4-202 HAL package provides generic
+        support for the SuperH SH4-202 MicroDev CPU board."
+}
+
+# --------------------------------------------------------------------------
+# H8/300 packages
+package CYGPKG_HAL_H8300 {
+	alias		{ "Hitachi H8300 common HAL" hal_h8300 h8300_hal}
+	directory	hal/h8300/arch
+	script		hal_h8300.cdl
+	hardware
+	description "
+The Hitachi H8/300 architecture HAL package provides generic support for this
+processor architecture. It is also necessary to select a specific
+target platform HAL package."
+}
+
+package CYGPKG_HAL_H8300_H8300H {
+	alias		{ "Hitachi H8300H variant HAL" hal_h8300h h8300h_hal}
+	directory	hal/h8300/h8300h
+	script		hal_h8300_h8300h.cdl
+	hardware
+        description "
+The H8/300H HAL package provides the support needed to run eCos on a Hitachi
+H8/300H processor."
+}
+
+package CYGPKG_HAL_H8300_H8S {
+	alias		{ "Hitachi H8S variant HAL" hal_h8s h8s_hal}
+	directory	hal/h8300/h8s
+	script		hal_h8300_h8s.cdl
+	hardware
+        description "
+The H8S HAL package provides the support needed to run eCos on a Hitachi
+H8S processor."
+}
+
+package CYGPKG_HAL_H8300_H8300H_SIM {
+	alias		{ "H8/300H simulator" hal_h8300h_sim h8300h_sim_hal }
+	directory	hal/h8300/sim
+	script		hal_h8300_h8300h_sim.cdl
+	hardware
+        description "
+           The minimal simulator HAL package is provided for use when
+           only a simple simulation of the processor architecture is
+           desired, as opposed to detailed simulation of any specific
+           board. In particular it is not possible to simulate any of
+           the I/O devices, so device drivers cannot be used."
+}
+
+package CYGPKG_HAL_H8300_H8300H_AKI3068NET {
+	alias		{ "Akizuki H8/3068 board" hal_h8300h_aki3068net h8300h_aki3068net_hal }
+	directory	hal/h8300/aki3068net
+	script		hal_h8300_h8300h_aki3068net.cdl
+	hardware
+        description "
+           The aki3068net HAL package provides the support needed to run
+           eCos on a Akizuki H8/3068 Network micom board." 
+}
+
+package CYGPKG_HAL_H8300_H8300H_H8MAX {
+	alias		{ "H8MAX board" hal_h8300h_h8max h8300h_h8max_hal }
+	directory	hal/h8300/h8max
+	script		hal_h8300_h8300h_h8max.cdl
+	hardware
+        description "
+           The h8max HAL package provides the support needed to run
+           eCos on a H8MAX board." 
+}
+
+package CYGPKG_HAL_H8300_H8S_SIM {
+	alias		{ "H8S simulator" hal_h8s_sim h8s_sim_hal }
+	directory	hal/h8300/sim_s
+	script		hal_h8300_h8s_sim.cdl
+	hardware
+        description "
+           The minimal simulator HAL package is provided for use when
+           only a simple simulation of the processor architecture is
+           desired, as opposed to detailed simulation of any specific
+           board. In particular it is not possible to simulate any of
+           the I/O devices, so device drivers cannot be used."
+}
+
+package CYGPKG_HAL_H8300_H8S_EDOSK2674 {
+	alias		{ "EDOSK-2674 board" hal_h8s_edosk2674 h8s_edosk2674_hal }
+	directory	hal/h8300/edosk2674
+	script		hal_h8300_h8s_edosk2674.cdl
+	hardware
+        description "
+           The edosk2674 HAL package provides the support needed to run
+           eCos on a Hitachi Micro System Europe EDOSK-2674 Evalution board." 
+}
+
+# ==========================================================================
+# --------------------------------------------------------------------------
+# i386 packages
+package CYGPKG_HAL_I386 {
+	alias		{ "i386 common HAL" hal_i386 i386_hal i386_arch_hal }
+	directory	hal/i386/arch
+	script		hal_i386.cdl
+	hardware
+	description "
+    	    The i386 architecture HAL package provides generic
+    	    support for this processor architecture. It is also
+    	    necessary to select a specific target platform HAL
+    	    package."
+}
+
+package CYGPKG_HAL_I386_GENERIC {
+	alias		{ "i386 generic target" hal_i386_generic }
+	directory	hal/i386/generic
+	script		hal_i386_generic.cdl
+	hardware
+        description "
+    	    The i386 generic Target HAL package provides support
+            for generic IA32 processors, from the 80386 to the latest
+            Pentium/Athlon."
+	    
+}
+package CYGPKG_HAL_I386_PCMB {
+	alias		{ "i386 PC Motherboard" hal_i386_pcmb }
+	directory	hal/i386/pcmb
+	script		hal_i386_pcmb.cdl
+	hardware
+        description "
+    	    The i386 PC Motherboard HAL package provides the 
+    	    support needed to run eCos binaries on a standard i386
+    	    PC motherboard. This is a support package for various
+            actual platform specific targets."
+}
+package CYGPKG_HAL_I386_PC {
+	alias		{ "i386 PC target" hal_i386_pc }
+	directory	hal/i386/pc
+	script		hal_i386_pc.cdl
+	hardware
+        description "
+    	    The i386 PC Target HAL package provides the 
+    	    support needed to run eCos binaries on a standard i386
+    	    PC."
+}
+
+# --------------------------------------------------------------------------
+# Synthetic target.
+package CYGPKG_HAL_SYNTH {
+	alias		{ "Linux synthetic target" linux }
+	directory	hal/synth/arch
+	script		hal_synth.cdl
+	hardware
+        description "
+    	    The Linux Synthetic Target HAL package provides the 
+    	    support needed to run eCos binaries on top of the i386
+    	    Linux kernel."
+}
+
+package CYGPKG_HAL_SYNTH_I386 {
+	alias		{ "Linux/i386 synthetic target" i386_linux }
+	directory	hal/synth/i386linux
+	script		hal_synth_i386.cdl
+	hardware
+        description "
+            i386 processor-specific support for the Linux synthetic target"
+}
+
+# --------------------------------------------------------------------------
+# SPARClite packages
+package CYGPKG_HAL_SPARCLITE {
+	alias		{ "SPARClite common HAL" hal_sparclite sparclite_hal sparclite_arch_hal }
+	directory	hal/sparclite/arch
+	script		hal_sparclite.cdl
+	hardware
+	description "
+    	    The SPARClite architecture HAL package provides generic support
+    	    for this processor architecture. It is also necessary to select
+    	    a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_SPARCLITE_SLEB {
+	alias		{ "Fujitsu MB86800-MA01 board" hal_sparclite_sleb sparclite_sleb_hal }
+	directory	hal/sparclite/sleb
+	script		hal_sparclite_sleb.cdl
+	hardware
+        description "
+    	    The SPARClite evaluation board HAL package is provided for use
+    	    with the Fujitsu MB8683x boards."
+}
+
+package CYGPKG_HAL_SPARCLITE_SIM {
+	alias		{ "SPARClite simulator" hal_sparclite_sim sparclite_sim_hal }
+	directory	hal/sparclite/sim
+	script		hal_sparclite_sim.cdl
+	hardware
+        description "
+    	    The SPARClite simulator HAL package is provided for use
+    	    with the SPARClite simulator."
+}
+
+# --------------------------------------------------------------------------
+# SPARC V7/V8 packages
+package CYGPKG_HAL_SPARC {
+	alias		{ "SPARC V7/V8 common HAL" hal_sparc sparc_hal sparc_arch_hal }
+	directory	hal/sparc/arch
+	script		hal_sparc.cdl
+	hardware
+	description "
+    	    The SPARC V7/V8 architecture HAL package provides generic support
+    	    for this processor architecture. It is also necessary to select
+    	    a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_SPARC_ERC32 {
+	alias		{ "ERC32 processor" hal_sparc_erc32 sparc_erc32_hal }
+	directory	hal/sparc/erc32
+	script		hal_sparc_erc32.cdl
+	hardware
+        description "
+    	    The ERC32 processor HAL package is provided for use
+    	    with both real hardware and the TSIM/ERC32 simulator."
+}
+
+package CYGPKG_HAL_SPARC_LEON {
+	alias		{ "LEON processor" hal_sparc_leon sparc_leon_hal }
+	directory	hal/sparc/leon
+	script		hal_sparc_leon.cdl
+	hardware
+        description "
+    	    The LEON processor HAL package is provided for use
+    	    with both real hardware and the TSIM/LEON simulator."
+}
+
+# --------------------------------------------------------------------------
+# PowerPC packages
+package CYGPKG_HAL_POWERPC {
+	alias		{ "PowerPC common HAL" hal_powerpc powerpc_hal powerpc_arch_hal }
+	directory	hal/powerpc/arch
+	script		hal_powerpc.cdl
+	hardware
+	description "
+ 	    The PowerPC architecture HAL package provides generic
+ 	    support for this processor architecture. It is also necessary to
+    	    select a CPU variant and a specific target platform HAL
+    	    package."
+}
+
+package CYGPKG_HAL_POWERPC_MPC8260 {
+	alias		{ "PowerPC MPC8260 variant HAL" hal_mpc8260 }
+	directory	hal/powerpc/mpc8260/
+	script		hal_powerpc_mpc8260.cdl
+	hardware
+        description "
+           The PowerPC MPC8260 PowerQUICCII variant HAL package provides 
+           support for this processor variant. It is also necessary to
+           select a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_POWERPC_MPC8XXX {
+	alias		{ "PowerPC MPC8XXX variant HAL" hal_mpc8xxx }
+	directory	hal/powerpc/mpc8xxx/
+	script		hal_powerpc_mpc8xxx.cdl
+	hardware
+        description "
+           The PowerPC MPC8XXX PowerQUICCII variant HAL package provides 
+           support for this processor variant. It is also necessary to
+           select a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_POWERPC_MPC8xx {
+	alias		{ "PowerPC 8xx variant HAL" hal_mpc8xx mpc8xx_hal mpc8xx_arch_hal }
+	directory	hal/powerpc/mpc8xx/
+	script		hal_powerpc_mpc8xx.cdl
+	hardware
+        description "
+           The PowerPC 8xx variant HAL package provides generic support
+           for this processor variant. It is also necessary to
+           select a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_POWERPC_PPC60x {
+	alias		{ "PowerPC 60x variant HAL" hal_ppc60x ppc60x_hal ppc60x_arch_hal }
+	directory	hal/powerpc/ppc60x/
+	script		hal_powerpc_ppc60x.cdl
+	hardware
+        description "
+           The PowerPC 60x variant HAL package provides generic support
+           for this processor variant. It is also necessary to
+           select a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_POWERPC_MPC5xx {
+        alias           { "PowerPC 5xx variant HAL" hal_mpc5xx mpc5xx_hal mpc5xx_arch_hal }
+        directory       hal/powerpc/mpc5xx/
+        script          hal_powerpc_mpc5xx.cdl
+        hardware
+        description "
+           The PowerPC 5xx variant HAL package provides generic support
+           for this processor variant. It is also necessary to
+           select a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_POWERPC_PPC40x {
+	alias		{ "PowerPC 40x variant HAL" hal_ppc40x ppc40x_hal ppc40x_arch_hal }
+	directory	hal/powerpc/ppc40x/
+	script		hal_powerpc_ppc40x.cdl
+	hardware
+        description "
+           The PowerPC 40x variant HAL package provides generic support
+           for this processor variant. It is also necessary to
+           select a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_POWERPC_COGENT {
+	alias		{ "Cogent CMA286/287 board" hal_powerpc_cogent powerpc_cogent_hal }
+	directory	hal/powerpc/cogent
+	script		hal_powerpc_cogent.cdl
+	hardware
+        description "
+            The cogent HAL package provides the support needed to run
+            eCos on a Cogent board equipped with a PowerPC processor."
+}
+
+package CYGPKG_HAL_POWERPC_CME555 {
+        alias           { "Axiom's CME555 evaluation board" hal_powerpc_cme555 powerpc_cme555_hal }
+        directory       hal/powerpc/cme555
+        script          hal_powerpc_cme555.cdl
+        hardware
+        description "
+            The CME555 HAL package provides the support needed to run
+            eCos on a CME555 evaluation board from Axiom Manufacturing."
+}
+
+package CYGPKG_HAL_POWERPC_EC555 {
+        alias           { "Wuerz development board" hal_powerpc_ec555 powerpc_ec555_hal }
+        directory       hal/powerpc/ec555
+        script          hal_powerpc_ec555.cdl
+        hardware
+        description "
+            The EC555 HAL package provides the support needed to run
+            eCos on an EC555 development board from Wuerz elektronik."
+}
+
+package CYGPKG_HAL_POWERPC_PATI {
+        alias           { "MPL PATI PC/104+ board" hal_powerpc_pati powerpc_pati_hal }
+        directory       hal/powerpc/pati
+        script          hal_powerpc_pati.cdl
+        hardware
+        description "
+            The PATI HAL package provides the support needed to run
+            eCos on an PATI PC/104+ board from MPL elektronik."
+}
+
+package CYGPKG_HAL_POWERPC_FADS {
+	alias		{ "Motorola MPC8xxFADS board" hal_powerpc_fads powerpc_fads_hal }
+	directory	hal/powerpc/fads
+	script		hal_powerpc_fads.cdl
+	hardware
+        description "
+            The FADS HAL package provides the support needed to run
+            eCos on a Motorola FADS board equipped with a PowerPC processor."
+}
+package CYGPKG_HAL_POWERPC_MBX {
+	alias		{ "Motorola MBX860/821 board" hal_powerpc_mbx powerpc_mbx_hal }
+	directory	hal/powerpc/mbx
+	script		hal_powerpc_mbx.cdl
+	hardware
+        description "
+            The MBX HAL package provides the support needed to run
+            eCos on a Motorola MBX board equipped with a PowerPC processor."
+}
+
+package CYGPKG_HAL_POWERPC_VIPER {
+	alias		{ "A&M Viper PPC860 board" hal_powerpc_viper powerpc_viper_hal }
+	directory	hal/powerpc/viper
+	script		hal_powerpc_viper.cdl
+	hardware
+        description "
+            The VIPER HAL package provides the support needed to run
+            eCos on a A&M VIPER board equipped with a PowerPC processor."
+}
+
+package CYGPKG_HAL_POWERPC_TS6 {
+	alias		{ "Delphi TigerSHARC-6 board" hal_powerpc_ts6 powerpc_ts6_hal }
+	directory	hal/powerpc/ts6
+	script		hal_powerpc_ts6.cdl
+	hardware
+        description "
+            The TS6 HAL package provides the support needed to run
+            eCos on a Delphi TigerSHARC-6 board equipped with a
+            PowerPC processor."
+}
+
+package CYGPKG_HAL_POWERPC_VADS {
+	alias		{ "Motorola MPC8260 VADS board" hal_powerpc_vads powerpc_vads_hal }
+	directory	hal/powerpc/vads
+	script		hal_powerpc_vads.cdl
+	hardware
+        description "
+            The VADS HAL package provides the support needed to run
+            eCos on a Motorola MPC8260 VADS board equipped with a
+            PowerPC processor."
+}
+
+package CYGPKG_HAL_QUICC {
+	alias		{ "Motorola MPC8xx QUICC support" hal_quicc quicc_hal quicc }
+	directory	hal/powerpc/quicc
+	script		hal_powerpc_quicc.cdl
+	hardware
+        description "
+            The QUICC package provides some of the support needed
+            to run eCos on a Motorola MPC8xx processors, using the QUICC
+            communications subsystem."
+}
+
+package CYGPKG_HAL_POWERPC_SIM {
+	alias		{ "PowerPC simulator" hal_powerpc_sim powerpc_sim_hal }
+	directory	hal/powerpc/sim
+	script		hal_powerpc_sim.cdl
+	hardware
+        description "
+            The minimal simulator HAL package is provided for use when
+            only a simple simulation of the processor architecture is
+            desired, as opposed to detailed simulation of any specific
+            board. In particular it is not possible to simulate any of
+            the I/O devices, so device drivers cannot be used."
+}
+
+# --------------------------------------------------------------------------
+# MIPS packages
+
+package CYGPKG_HAL_MIPS {
+	alias		{ "MIPS common HAL" hal_mips mips_hal mips_arch_hal }
+	directory	hal/mips/arch/
+	script		hal_mips.cdl
+	hardware
+	description "
+    	    The MIPS architecture HAL package provides generic support
+    	    for this processor architecture. It is also necessary to
+    	    select a CPU variant and a specific target platform HAL
+    	    package."
+}
+
+package CYGPKG_HAL_MIPS_SIM {
+	alias		{ "MIPS simulator" hal_mips_sim mips_sim_hal }
+	directory	hal/mips/sim
+	script		hal_mips_sim.cdl
+	hardware
+	description "
+           The minimal simulator HAL package is provided for when only
+           a simple simulation of the processor architecture is
+           desired, as opposed to detailed simulation of any specific
+           board. To use this minimal simulator the command
+           `target sim --board=jmr3904pal' should be used from inside
+           gdb. It is not possible to use any of the eCos device
+           drivers when the simulator is running in this mode"
+}
+
+package CYGPKG_HAL_MIPS_TX39 {
+	alias		{ "TX39 chip HAL" hal_tx39 tx39_hal tx39_arch_hal }
+	directory	hal/mips/tx39/
+	script		hal_mips_tx39.cdl
+	hardware
+        description "
+           The TX39 architecture HAL package provides generic support
+           for this processor architecture. It is also necessary to
+           select a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_MIPS_TX39_JMR3904 {
+	alias		{ "Toshiba JMR-TX3904 board" hal_tx39_jmr3904 tx39_jmr3904_hal }
+	directory	hal/mips/jmr3904
+	script		hal_mips_tx39_jmr3904.cdl
+	hardware
+	description "
+           The JMR3904 HAL package should be used when targetting the
+           actual hardware. The same package can also be used when
+           running on the full simulator, since this provides an
+           accurate simulation of the hardware including I/O devices.
+           To use the simulator in this mode the command
+           `target sim --board=jmr3904' should be used from inside gdb."
+}
+
+package CYGPKG_HAL_MIPS_MIPS32 {
+	alias		{ "MIPS32 HAL" hal_mips32 mips32_hal mips32_arch_hal }
+	directory	hal/mips/mips32/
+	script		hal_mips_mips32.cdl
+	hardware
+        description "
+           The MIPS 32 architecture HAL package provides generic support
+           for this processor architecture. It is also necessary to
+           select a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_MIPS_MIPS64 {
+	alias		{ "MIPS64 HAL" hal_mips64 mips64_hal mips64_arch_hal }
+	directory	hal/mips/mips64/
+	script		hal_mips_mips64.cdl
+	hardware
+        description "
+           The MIPS 64 architecture HAL package provides generic support
+           for this processor architecture. It is also necessary to
+           select a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_MIPS_ATLAS {
+	alias		{ "MIPS Atlas board" hal_atlas atlas_hal }
+	directory	hal/mips/atlas
+	script		hal_mips_atlas.cdl
+	hardware
+	description "
+           The Atlas HAL package should be used when targetting the
+           actual hardware. "
+}
+package CYGPKG_HAL_MIPS_MALTA {
+	alias		{ "MIPS Malta board" hal_malta malta_hal }
+	directory	hal/mips/malta
+	script		hal_mips_malta.cdl
+	hardware
+	description "
+           The Malta HAL package should be used when targetting the
+           actual hardware. "
+}
+
+package CYGPKG_HAL_MIPS_TX49 {
+	alias		{ "TX49 chip HAL" hal_tx49 tx49_hal tx49_arch_hal }
+	directory	hal/mips/tx49/
+	script		hal_mips_tx49.cdl
+	hardware
+        description "
+           The TX49 architecture HAL package provides generic support
+           for this processor architecture. It is also necessary to
+           select a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_MIPS_TX49_REF4955 {
+	alias		{ "Toshiba TX4955 reference platform" hal_tx49_ref4955 tx49_ref4955_hal }
+	directory	hal/mips/ref4955
+	script		hal_mips_tx49_ref4955.cdl
+	hardware
+	description "
+           The REF4955 HAL package should be used when targetting the
+           actual hardware."
+}
+
+package CYGPKG_HAL_MIPS_RM7000 {
+	alias		{ "RM7000 chip HAL" hal_rm7000 rm7000_hal rm7000_arch_hal }
+	directory	hal/mips/rm7000/var
+	script		hal_mips_rm7000.cdl
+	hardware
+        description "
+           The RM7000 architecture HAL package provides generic support
+           for this processor architecture. It is also necessary to
+           select a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_MIPS_RM7000_OCELOT {
+	alias		{ "PMC-Sierra Ocelot platform" hal_rm7000_ocelot rm7000_ocelot_hal }
+	directory	hal/mips/rm7000/ocelot
+	script		hal_mips_rm7000_ocelot.cdl
+	hardware
+	description "
+           The Ocelot HAL package should be used when targetting the
+           actual hardware."
+}
+
+package CYGPKG_HAL_MIPS_VR4300 {
+	alias		{ "VR4300 chip HAL" hal_vr4300 vr4300_hal vr4300_arch_hal }
+	directory	hal/mips/vr4300/
+	script		hal_mips_vr4300.cdl
+	hardware
+        description "
+           The VR4300 variant HAL package provides generic support
+           for this processor architecture. It is also necessary to
+           select a specific target platform HAL package."
+}
+package CYGPKG_HAL_MIPS_VR4300_VRC4373 {
+	alias		{ "NEC VRC4373 board" hal_vrc4373 vrc4373_hal }
+	directory	hal/mips/vrc4373
+	script		hal_mips_vr4300_vrc4373.cdl
+	hardware
+	description "
+           The VRC4373 HAL package should be used when targetting the
+           actual hardware."
+}
+
+package CYGPKG_HAL_MIPS_VR4300_VRC4375 {
+	alias		{ "NEC VRC4375 board" hal_vrc4375 vrc4375_hal }
+	directory	hal/mips/vrc4375
+	script		hal_mips_vr4300_vrc4375.cdl
+	hardware
+	description "
+           The VRC4375 HAL package should be used when targetting the
+           actual hardware."
+}
+
+package CYGPKG_HAL_MIPS_VR4300_VRC437X {
+	alias		{ "NEC VRC437X support" hal_vrc437x vrc437x_hal }
+	directory	hal/mips/vrc437x
+	script		hal_mips_vr4300_vrc437x.cdl
+	hardware
+	description "
+           The VRC437X HAL package should be used when targetting harware
+           that contains either a VRC437X companion chip."
+}
+
+package CYGPKG_HAL_MIPS_UPD985XX {
+	alias		{ "upd985xx chip HAL" hal_upd985xx upd985xx_hal upd985xx_arch_hal }
+	directory	hal/mips/upd985xx/
+	script		hal_mips_upd985xx.cdl
+	hardware
+        description "
+           The UPD985XX variant HAL package provides generic support
+           for this NEC system-on-chip processor architecture, uPD985xx.
+	   It is also necessary to
+           select a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_MIPS_IDT32334 {
+	alias		{ "MIPS IDT32334 variant HAL" hal_idt32334 idt32334_hal idt32334_arch_hal }
+	directory	hal/mips/idt32334
+	script		hal_mips_idt32334.cdl
+	hardware
+        description "
+           The IDT32334 variant HAL package provides generic support
+           for platforms based on this variant. It is also necessary to
+           select a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_MIPS_IDT32334_REFIDT334 {
+	alias		{ "MIPS IDT79S334A reference platform" hal_idt32334_refIDT334 idt32334_refIDT334_hal }
+	directory	hal/mips/idt79s334a
+	script		hal_mips_idt32334_refidt334.cdl
+	hardware
+	description "
+           The REFIDT334 HAL package should be used when targetting the
+           actual hardware."
+}
+
+# --------------------------------------------------------------------------
+# MN10300 packages
+
+package CYGPKG_HAL_MN10300 {
+	alias		{ "MN10300 common HAL" hal_mn10300 mn10300_hal mn10300_arch_hal }
+	directory	hal/mn10300/arch
+	script		hal_mn10300.cdl
+	hardware
+	description "
+           The MN10300 architecture HAL package provides generic
+           support for this processor architecture. It is also
+           necessary to select a specific target platform HAL
+           package."
+}
+
+package CYGPKG_HAL_MN10300_AM31 {
+	alias		{ "MN10300 AM31 variant HAL" hal_mn10300_am31 mn10300_am31_hal }
+	directory	hal/mn10300/am31
+	script		hal_mn10300_am31.cdl
+	hardware
+        description "
+           The MN10300 AM31 variant HAL package provides generic
+           support for this processor architecture. It is also
+           necessary to select a specific target platform HAL
+           package."
+}
+
+package CYGPKG_HAL_MN10300_AM31_SIM {
+	alias		{ "MN10300 simulator" hal_mn10300_sim mn10300_sim_hal }
+	directory	hal/mn10300/sim
+	script		hal_mn10300_am31_sim.cdl
+	hardware
+        description "
+           The minimal simulator HAL package is provided for use when
+           only a simple simulation of the processor architecture is
+           desired, as opposed to detailed simulation of any specific
+           board. In particular it is not possible to simulate any of
+           the I/O devices, so device drivers cannot be used."
+}
+
+package CYGPKG_HAL_MN10300_AM31_STDEVAL1 {
+	alias		{ "Matsushita stdeval1 board" hal_mn10300_stdeval1 mn10300_stdeval1_hal }
+	directory	hal/mn10300/stdeval1
+	script		hal_mn10300_am31_stdeval1.cdl
+	hardware
+        description "
+           The stdeval1 HAL package should be used when targetting the
+           actual hardware. The same package can also be used when
+           running on the full MN10300 simulator, since this provides
+           an accurate simulation of the full hardware including I/O
+           devices."
+}
+package CYGPKG_HAL_MN10300_AM33 {
+	alias		{ "MN10300 AM33 variant HAL" hal_mn10300_am33 mn10300_am33_hal }
+	directory	hal/mn10300/am33
+	script		hal_mn10300_am33.cdl
+	hardware
+        description "
+           The MN10300 AM33 variant HAL package provides generic
+           support for this processor architecture. It is also
+           necessary to select a specific target platform HAL
+           package."
+}
+
+package CYGPKG_HAL_MN10300_AM33_STB {
+	alias		{ "Matsushita STB board" hal_mn10300_am33_stb mn10300_am33_stb_hal }
+	directory	hal/mn10300/stb
+	script		hal_mn10300_am33_stb.cdl
+	hardware
+        description "
+           The STB HAL package should be used when targetting the
+           actual hardware for the AM33 STB evaluation board."
+}
+
+package CYGPKG_HAL_MN10300_AM33_ASB {
+	alias		{ "Matsushita ASB2303 board" hal_mn10300_am33_asb mn10300_am33_asb_hal }
+	directory	hal/mn10300/asb
+	script		hal_mn10300_am33_asb.cdl
+	hardware
+        description "
+           The ASB2303 HAL package should be used when targetting the
+           actual hardware for the AM33 ASB2303 evaluation board."
+}
+
+package CYGPKG_HAL_MN10300_AM33_ASB2305 {
+	alias		{ "Matsushita ASB2305 board" hal_mn10300_am33_asb2305
+			  mn10300_am33_asb2305_hal }
+	directory	hal/mn10300/asb2305
+	script		hal_mn10300_am33_asb2305.cdl
+	hardware
+        description "
+           The ASB2305 HAL package should be used when targetting the
+           actual hardware for the AM33 ASB2305 evaluation board."
+}
+
+# --------------------------------------------------------------------------
+# NEC packages
+package CYGPKG_HAL_V85X {
+	alias		{ "NEC V85x common HAL" hal_v85x nec_arch_hal }
+	directory	hal/v85x/arch
+	script		hal_v85x.cdl
+	hardware
+	description "
+The NEC V85x architecture HAL package provides generic support for this
+processor architecture. It is also necessary to select a specific
+target platform HAL package."
+}
+
+package CYGPKG_HAL_V85X_V850 {
+	alias		{ "NEC V850 variant HAL" hal_v85x_v850 nec_v850_hal }
+	directory	hal/v85x/v850
+	script		hal_v85x_v850.cdl
+	hardware
+        description "
+The V850 HAL package provides the support needed to run eCos on a NEC V850
+processor."
+}
+
+package CYGPKG_HAL_V85X_V850_CEB {
+	alias		{ "Cosmo CEB-V850/SA1 board" hal_v85x_v850_ceb nec_v850_ceb_hal }
+	directory	hal/v85x/ceb_v850
+	script		hal_v85x_ceb_v850.cdl
+	hardware
+        description "
+The CEB-V850/SA1 HAL package provides the support needed to run eCos on a Cosmo CEB-V850/SA1
+evaluation board."
+}
+
+# --------------------------------------------------------------------------
+# m68k packages
+
+package CYGPKG_HAL_M68K {
+    alias       { "M68K common HAL" hal_m68k m68k_hal m68k_arch_hal }
+    directory   hal/m68k/arch
+    script      hal_m68k.cdl
+    hardware
+
+    description   "The M68K architecture HAL package provides generic
+                   support for this architecture."
+}
+
+package CYGPKG_HAL_M68K_MCFxxxx {
+    alias       { "M68K/ColdFire variant HAL" hal_m68k_mcfxxxx m68k_mcfxxxx_hal }
+    directory   hal/m68k/mcf52xx/var
+    script      hal_m68k_mcf52xx.cdl
+    hardware
+
+    description   "The M68k/ColdFire variant  HAL  package provides generic
+                  support for Freescale ColdFire  cores."
+}
+
+package CYGPKG_HAL_M68K_MCF5272 {
+    alias       { "mcf5272 68k/ColdFire processor variant HAL" hal_m68k_mcf5272 m68k_mcf5272_hal }
+    directory   hal/m68k/mcf52xx/mcf5272/proc
+    script      hal_m68k_mcf5272.cdl
+    hardware
+
+    description   "The mcf5272 processor variant HAL package provides generic
+                   support for this processor."
+}
+
+package CYGPKG_HAL_M68K_M5272C3 {
+    alias       { "Freescale m5272c3 evaluation board platform HAL"
+        hal_m68k_m5272c3 m68k_m5272c3_hal }
+    directory   hal/m68k/mcf52xx/mcf5272/m5272c3
+    script      hal_m68k_m5272c3.cdl
+    hardware
+
+    description   "The Freescale  m5272c3 evaluation  board platform  HAL
+                  package should be used when targeting the actual  hardware
+                  for the Freescale m5272c3 evaluation board platform."
+}
+
+package CYGPKG_DEVS_ETH_MCFxxxx {
+    alias       { "MCFxxxx ethernet driver" devs_eth_mcfxxxx mcfxxxx_eth_driver }
+    hardware
+    directory   devs/eth/m68k/mcf5272
+    script      mcf5272_eth.cdl
+    description "
+            This packages provides an ethernet driver for the on-chip
+        device provided by MCFxxxx ColdFire processors."
+}
+
+package CYGPKG_DEVS_SERIAL_MCFxxxx {
+    alias       { "MCFxxxx serial device driver" devs_serial_mcfxxxx mcfxxxx_serial_driver }
+    hardware
+    directory   devs/serial/m68k/mcf52xx
+    script      ser_mcf52xx.cdl
+    description "
+            This package provides serial drivers for the on-chip UART's
+            provided by MCFxxxx ColdFire processors."
+}
+
+# --------------------------------------------------------------------------
+# CalmRISC16 packages
+
+package CYGPKG_HAL_CALM16 {
+	alias		{ "CalmRISC16 common HAL" hal_calm16 calm16_hal calm16_arch_hal }
+	directory	hal/calmrisc16/arch/
+	script		hal_calm16.cdl
+	hardware
+	description "
+    	    The CalmRISC16 architecture HAL package provides generic support
+    	    for this processor architecture. It is also necessary to
+    	    select a CPU variant and a specific target platform HAL
+    	    package."
+}
+
+package CYGPKG_HAL_CALM16_CORE {
+	alias		{ "CalmRISC16 Core HAL" hal_calm16core calm16core_hal calm16core_arch_hal }
+	directory	hal/calmrisc16/core/
+	script		hal_calm16_core.cdl
+	hardware
+        description "
+           The CalmRISC16 Core architecture HAL package provides generic support
+           for this processor architecture. It is also necessary to
+           select a specific target platform HAL package."
+}
+
+package CYGPKG_HAL_CALM16_CEB {
+	alias		{ "CalmRISC16 Core eval board" hal_calm16_ceb calm16_ceb_hal }
+	directory	hal/calmrisc16/ceb
+	script		hal_calm16_ceb.cdl
+	hardware
+	description "
+           The CalmRISC16 HAL package should be used when targetting the
+           actual hardware. "
+}
+# --------------------------------------------------------------------------
+# CalmRISC32 packages
+
+package CYGPKG_HAL_CALM32 {
+	alias		{ "CalmRISC32 common HAL" hal_calm32 calm32_hal calm32_arch_hal }
+	directory	hal/calmrisc32/arch/
+	script		hal_calm32.cdl
+	hardware
+	description "
+    	    The CalmRISC32 architecture HAL package provides generic support
+    	    for this processor architecture. It is also necessary to
+    	    select a CPU variant and a specific target platform HAL
+    	    package."
+}
+
+package CYGPKG_HAL_CALM32_CORE {
+	alias		{ "CalmRISC32 Core HAL" hal_calm32core calm32core_hal calm32core_arch_hal }
+	directory	hal/calmrisc32/core/
+	script		hal_calm32_core.cdl
+	hardware
+}
+
+package CYGPKG_HAL_CALM32_CEB {
+	alias		{ "CalmRISC32 Core eval board" hal_calm32_ceb calm32_ceb_hal hal_commo }
+	directory	hal/calmrisc32/ceb
+	script		hal_calm32_ceb.cdl
+	hardware
+	description "
+           The CalmRISC32 HAL package should be used when targetting the
+           actual hardware. "
+}
+
+
+# --------------------------------------------------------------------------
+# FUJITSU packages
+package CYGPKG_HAL_FRV {
+	alias		{ "FR-V (Fujitsu) common HAL" hal_frv frv_hal frv_arch_hal }
+	directory	hal/frv/arch
+	script		hal_frv.cdl
+	hardware
+	description "
+The FRV architecture HAL package provides generic support for this
+processor architecture. It is also necessary to select a specific
+target platform HAL package."
+}
+
+package CYGPKG_HAL_FRV_FRV400 {
+	alias		{ "FUJITSU development board (FR-V 400)" hal_frv_frv400 frv_frv400_hal }
+	directory	hal/frv/frv400
+	script		hal_frv_frv400.cdl
+	hardware
+        description "
+The FRV400 HAL package provides the support needed to run eCos on a FUJITSU
+MB93091 (FR-V 400) eval board."
+}
+
+package CYGPKG_HAL_FRV_MB93091 {
+	alias		{ "FUJITSU development board (FR-V)" mb93091 }
+	directory	hal/frv/mb93091
+	script		hal_frv_mb93091.cdl
+	hardware
+        description "
+The FRV Generic HAL package provides the support needed to run eCos on 
+various FUJITSU FR-V eval boards."
+}
+
+package CYGPKG_HAL_FRV_MB93093 {
+	alias		{ "FUJITSU MB93093-PD00 Portable Development Kit (FR-V)" mb93093 }
+	directory	hal/frv/mb93093
+	script		hal_frv_mb93093.cdl
+	hardware
+        description "
+The MB93093 HAL package provides the support needed to run eCos on 
+the Fujitsu MB93093-PD00 Portable Development Kit board."
+}
+
+package CYGPKG_DEVS_ETH_FRV_FRV400 {
+	alias 		{ "Fujitsu FR-V 400 with 82559 ethernet driver"
+			   devs_eth_frv_frv400 frv400_eth_driver }
+	hardware
+	directory	devs/eth/frv/frv400
+	script		frv400_eth_drivers.cdl
+        description     "Ethernet driver for Fujitsu FR-V 400 with Intel
+                         i82559 ethernet interfaces."
+}
+
+package CYGPKG_DEVS_ETH_FRV_PDK403 {
+	alias 		{ "Fujitsu MB93093-PD00 with AXL88796 ethernet driver"
+			   devs_eth_frv_pdk403 pdk403_eth_driver }
+	hardware
+	directory	devs/eth/frv/pdk403
+	script		pdk403_eth_drivers.cdl
+        description     "Ethernet driver for Fujitsu MB93093-PD00 Portable
+			 Demonstration Kit with AXL88796 Ethernet device"
+}
+
+package CYGPKG_DEVS_ETH_FRV_CB70 {
+	alias 		{ "Fujitsu FR-V 405 with DM9000 ethernet driver"
+			   devs_eth_frv_cb70 cb70_eth_driver }
+	hardware
+	directory	devs/eth/frv/cb70
+	script		cb70_eth_driver.cdl
+        description     "Ethernet driver for Fujitsu FR-V 405 CB70 CPU card with
+                         Davicom DM9000 ethernet interface."
+}
+
+# FR30 packages
+
+package CYGPKG_HAL_FR30 {
+    alias       { "Fujitsu FR30 architecture (FR30/FR50/FR60)" hal_fr30
+                    fr30_hal }
+    directory   hal/fr30/arch
+    script      hal_fr30.cdl
+    hardware
+        description "
+The Fujitsu FR30 HAL package provides the generic support needed to run eCos on 
+a FR30 based microcontroller. FR50 and FR60 architectures should also select
+this one."
+}
+
+package CYGPKG_HAL_FR30_MB91301 {
+    alias       { "Fujitsu MB31301 variant (FR60)" hal_fr30_mb91301
+                    fr30_mb91301_hal }
+    directory   hal/fr30/mb91301
+    script      hal_fr30_mb91301.cdl
+    hardware
+        description "
+The Fujitsu MB91301 HAL package provides the support needed to run eCos on
+the Fujitsu Starterkit MB91302 Evaluation board. It contains a MB91302A
+Microcontroller from Fujitsu with a FR60 Core. So FR30 support is also needed."
+}
+
+package CYGPKG_HAL_FR30_MB91301_SKMB91302 {
+    alias       { "Fujitsu Starterkit MB91302 board" hal_fr30_skmb91302
+                    fr30_skmb91302_hal }
+    directory   hal/fr30/skmb91302
+    script      hal_fr30_skmb91302.cdl
+    hardware
+        description "
+The SKMB91302 HAL package provides the support needed to run eCos on
+the Fujitsu Starterkit MB91302 board. It contains a MB91302
+Microcontroller from Fujitsu with a FR60 Core. So FR30 support is needed."
+}
+
+package CYGPKG_DEVS_FLASH_FR30_SKMB91302 {
+    alias       { "Fujitsu Starterkit MB91302 FLASH memory support" flash_skmb91302 }
+    directory   devs/flash/fr30/skmb91302
+    script      flash_skmb91302.cdl
+    hardware
+        description "
+           This package contains hardware support for FLASH memory
+       on the Fujitsu Starterkit MB91302 platform.
+        (AMD 29DL640E-90 Device)"
+}
+
+package CYGPKG_DEVS_ETH_ARM_AT91 {
+        alias           { "AT91 Ethernet driver" at91_eth_driver }
+        directory       devs/eth/arm/at91
+        script          at91_eth.cdl
+        hardware
+        description     "Ethernet driver for the AT91 family of chips"
+}
+
+package CYGPKG_DEVS_ETH_ARM_LPC2XXX {
+        alias           { "LPC2xxx/LPC17xx Ethernet driver" }
+        directory       devs/eth/arm/lpc2xxx
+        script          lpc2xxx_eth.cdl
+        hardware
+        description     "Ethernet driver for the LPC2xxx/LPC17xx family of chips"
+}
+
+
+# --------------------------------------------------------------------------
+
+# ==========================================================================
+
+# --------------------------------------------------------------------------
+# FRV targets
+target frv400 {
+	alias { "Fujitsu development board (FR-V 400)" FRV400 }
+	packages { CYGPKG_HAL_FRV
+                   CYGPKG_HAL_FRV_FRV400
+                   CYGPKG_IO_PCI
+                   CYGPKG_DEVS_ETH_FRV_FRV400
+                   CYGPKG_DEVS_ETH_NS_DP83902A
+                   CYGPKG_DEVS_FLASH_FRV_FRV400
+                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+        }
+        description "
+The frv400 target provides the packages needed to run eCos on a Fujistu
+development board (FR-V 400)."
+}
+
+target mb93091 {
+	alias { "Fujitsu MB93091 development board (FR-V 4xx,5xx)" MB93091 }
+	packages { CYGPKG_HAL_FRV
+                   CYGPKG_HAL_FRV_MB93091
+                   CYGPKG_IO_PCI
+                   CYGPKG_DEVS_ETH_FRV_FRV400
+                   CYGPKG_DEVS_ETH_NS_DP83902A
+                   CYGPKG_DEVS_ETH_FRV_CB70
+                   CYGPKG_DEVS_ETH_DAVICOM_DM9000
+                   CYGPKG_DEVS_FLASH_FRV_FRV400
+                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+        }
+        description "
+The MB93091 target provides the packages needed to run eCos on a Fujitsu
+MB93091 development board (FR-V 400 etc.)."
+}
+
+target mb93093 {
+	alias { "Fujitsu development board (FR-V 400)" MB93093 }
+	packages { CYGPKG_HAL_FRV
+                   CYGPKG_HAL_FRV_MB93093
+                   CYGPKG_DEVS_ETH_FRV_PDK403
+                   CYGPKG_DEVS_ETH_NS_DP83902A
+                   CYGPKG_DEVS_FLASH_FRV_PDK403
+                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+        }
+        description "
+The MB93093 target provides the packages needed to run eCos on a Fujitsu
+MB93090-PD00 Portable Development Kit."
+}
+
+# FR30 Targets
+
+target skmb91302 {
+    alias { "Fujitsu Starterkit MB91302 board" }
+    packages { CYGPKG_HAL_FR30
+                   CYGPKG_HAL_FR30_MB91301
+                   CYGPKG_HAL_FR30_MB91301_SKMB91302
+                   CYGPKG_DEVS_FLASH_FR30_SKMB91302
+                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+}
+        description "
+The Starterkit MB91302 HAL package provides the support needed to run
+eCos on the Fujitsu Starterkit MB91302 board. It contains a MB91302
+Microcontroller from Fujitsu with a FR60 Core. So FR30 support is
+included."
+}
+
+# --------------------------------------------------------------------------
+# ARM Targets
+
+target pid {
+	alias { "ARM development board (PID)" PID }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_PID
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+	           CYGPKG_IO_SERIAL_ARM_PID
+                   CYGPKG_DEVS_FLASH_ARM_PID
+                   CYGPKG_DEVS_FLASH_ATMEL_AT29CXXXX
+        }
+        description "
+The pid target provides the packages needed to run eCos on an ARM
+development board (formerly known as PID)."
+}
+
+target aeb {
+	alias { "ARM evaluation board (AEB-1)" aeb1 }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_AEB
+	           CYGPKG_IO_SERIAL_ARM_AEB
+                   CYGPKG_DEVICES_WATCHDOG_ARM_AEB
+        }
+        description "
+The aeb target provides the packages needed to run eCos on an ARM
+evaluation board (AEB-1)."
+}
+
+target e7t {
+	alias { "ARM Evaluator7T board (AEB-2)" aeb2 }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_E7T
+                   CYGPKG_DEVS_FLASH_ARM_E7T
+                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                   CYGPKG_DEVS_FLASH_SST_39VFXXX
+	           CYGPKG_IO_SERIAL_ARM_E7T
+                   CYGPKG_DEVS_ETH_ARM_KS32C5000
+        }
+        description "
+ The e7t target provides the packages needed to run eCos on an ARM
+ Evaluator7T board (aka AEB-2)."
+}
+
+target integrator_arm7 {
+        alias { "ARM INTEGRATOR development board w/ ARM7TDMI" integrator }
+        packages { CYGPKG_HAL_ARM 
+                   CYGPKG_HAL_ARM_INTEGRATOR 
+                   CYGPKG_IO_PCI
+                   CYGPKG_IO_SERIAL_ARM_INTEGRATOR
+		   CYGPKG_DEVS_FLASH_INTEL_28FXXX
+                   CYGPKG_DEVS_FLASH_ARM_INTEGRATOR
+		   CYGPKG_DEVS_ETH_INTEL_I82559
+                   CYGPKG_DEVS_ETH_ARM_INTEGRATOR
+        }
+        description "
+        The INTEGRATOR_ARM7 target provides the packages needed to 
+        run eCos on an ARM development board with an ARM7TDMI core
+        module installed."
+}
+
+target integrator_arm9 {
+        alias { "ARM INTEGRATOR development board w/ ARM966" }
+        packages { CYGPKG_HAL_ARM
+		   CYGPKG_HAL_ARM_ARM9
+                   CYGPKG_HAL_ARM_INTEGRATOR 
+                   CYGPKG_IO_PCI
+                   CYGPKG_IO_SERIAL_ARM_INTEGRATOR
+		   CYGPKG_DEVS_FLASH_INTEL_28FXXX
+                   CYGPKG_DEVS_FLASH_ARM_INTEGRATOR
+		   CYGPKG_DEVS_ETH_INTEL_I82559
+                   CYGPKG_DEVS_ETH_ARM_INTEGRATOR
+        }
+        description "
+        The INTEGRATOR_ARM9 target provides the packages needed to 
+        run eCos on an ARM development board with an ARM966 core
+        module installed."
+}
+
+target eb40 {
+	alias { "Atmel evaluation board (EB40)" at91 at91_eb40 }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_AT91
+                   CYGPKG_HAL_ARM_AT91_EB40
+                   CYGPKG_DEVS_FLASH_EB40
+                   CYGPKG_DEVS_FLASH_ATMEL_AT29CXXXX
+                   CYGPKG_IO_SERIAL_ARM_AT91
+                   CYGPKG_DEVICES_WATCHDOG_ARM_AT91
+        }
+        description "
+        The eb40 target provides the packages needed to run eCos on an Atmel
+        evaluation board (EB40)."
+}
+
+target jtst {
+	alias { "Atmel Diopsis evaluation board (jtst)" at91_jtst }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_AT91
+                   CYGPKG_HAL_ARM_AT91_JTST
+                   CYGPKG_IO_SERIAL_ARM_AT91
+                   CYGPKG_DEVS_FLASH_JTST
+                   CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX
+		   CYGPKG_DEVICES_WATCHDOG_ARM_AT91
+        }
+        description "
+        The jtst target provides the packages needed to run eCos on an Atmel
+        Diospsis evaluation board (jtst)."
+}
+
+target at91sam7sek {
+	alias { "Atmel AT91SAM7SEK evaluation board" at91_at91sam7sek }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_AT91
+                   CYGPKG_HAL_ARM_AT91SAM7
+                   CYGPKG_HAL_ARM_AT91SAM7SEK
+                   CYGPKG_IO_SERIAL_ARM_AT91
+                   CYGPKG_DEVS_FLASH_AT91
+                   CYGPKG_IO_SPI
+                   CYGPKG_DEVS_SPI_ARM_AT91
+                   CYGPKG_DEVICES_WATCHDOG_ARM_AT91WDTC
+                   CYGPKG_IO_USB
+                   CYGPKG_IO_USB_SLAVE
+                   CYGPKG_DEVS_USB_AT91
+                   CYGPKG_DEVS_ADC_ARM_AT91
+        }
+        description "
+        The at91sam7sek target provides the packages needed to run eCos on an 
+        Atmel AT91SAM7S-EK evaluation board."
+}
+
+target at91sam7xek {
+	alias { "Atmel AT91SAM7XEK evaluation board" at91_at91sam7xek }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_AT91
+                   CYGPKG_HAL_ARM_AT91SAM7
+                   CYGPKG_HAL_ARM_AT91SAM7XEK
+                   CYGPKG_IO_SERIAL_ARM_AT91
+                   CYGPKG_DEVS_FLASH_AT91
+                   CYGPKG_IO_SPI
+                   CYGPKG_DEVS_SPI_ARM_AT91
+                   CYGPKG_DEVICES_WATCHDOG_ARM_AT91WDTC
+                   CYGPKG_IO_USB
+                   CYGPKG_IO_USB_SLAVE
+                   CYGPKG_DEVS_USB_AT91
+                   CYGPKG_DEVS_ETH_PHY
+                   CYGPKG_DEVS_ETH_ARM_AT91
+                   CYGPKG_DEVS_CAN_AT91SAM7
+                   CYGPKG_DEVS_ADC_ARM_AT91
+        }
+        description "
+        The at91sam7xek target provides the packages needed to run eCos on an 
+        Atmel AT91SAM7X-EK evaluation board."
+}
+
+target sam7ex256 {
+	alias { "Olimex SAM7-EX256 evaluation board" at91_sam7ex256 }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_AT91
+                   CYGPKG_HAL_ARM_AT91SAM7
+                   CYGPKG_HAL_ARM_SAM7EX256
+                   CYGPKG_IO_SERIAL_ARM_AT91
+                   CYGPKG_DEVS_FLASH_AT91
+                   CYGPKG_IO_SPI
+                   CYGPKG_DEVS_SPI_ARM_AT91
+                   CYGPKG_DEVICES_WATCHDOG_ARM_AT91WDTC
+                   CYGPKG_IO_USB
+                   CYGPKG_IO_USB_SLAVE
+                   CYGPKG_DEVS_USB_AT91
+                   CYGPKG_DEVS_ETH_PHY
+                   CYGPKG_DEVS_ETH_ARM_AT91
+                   CYGPKG_DEVS_CAN_AT91SAM7
+                   CYGPKG_DEVS_ADC_ARM_AT91
+        }
+        description "
+        The SAM7EX256 target provides the packages needed to run eCos on an 
+        Olimex SAM7-EX256 evaluation board."
+}
+
+target eb40a {
+	alias { "Atmel evaluation board (EB40A)" at91_eb40a }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_AT91
+                   CYGPKG_HAL_ARM_AT91_EB40A
+                   CYGPKG_DEVS_FLASH_EB40A
+                   CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX
+                   CYGPKG_IO_SERIAL_ARM_AT91
+                   CYGPKG_DEVICES_WATCHDOG_ARM_AT91
+        }
+        description "
+	The eb40a target provides the packages needed to run eCos on an Atmel
+	evaluation board (EB40A)."
+}
+
+target eb42 {
+	alias { "Atmel evaluation board (EB42)" at91_eb42 }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_AT91
+                   CYGPKG_HAL_ARM_AT91_EB42
+                   CYGPKG_DEVS_FLASH_EB42
+                   CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX
+                   CYGPKG_IO_SERIAL_ARM_AT91
+        }
+        description "
+	The eb42 target provides the packages needed to run eCos on an Atmel
+	evaluation board (EB42)."
+}
+
+target eb55 {
+	alias { "Atmel evaluation board (EB55)" at91_eb55 }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_AT91
+                   CYGPKG_HAL_ARM_AT91_EB55
+                   CYGPKG_DEVS_FLASH_EB55
+                   CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX
+                   CYGPKG_DEVS_FLASH_ATMEL_DATAFLASH
+                   CYGPKG_IO_SERIAL_ARM_AT91
+                   CYGPKG_IO_SPI
+                   CYGPKG_DEVS_SPI_ARM_EB55
+                   CYGPKG_DEVS_SPI_ARM_AT91
+                   CYGPKG_DEVICES_WATCHDOG_ARM_AT91
+                   CYGPKG_DEVS_ADC_ARM_AT91
+        }
+        description "
+	The eb55 target provides the packages needed to run eCos on an Atmel
+	evaluation board (EB55)."
+}
+
+target phycore {
+	alias { "PHYTEC evaluation board (phyCORE AT91M55800A)" at91_phycore }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_AT91
+                   CYGPKG_HAL_ARM_AT91_PHYCORE
+                   CYGPKG_DEVS_FLASH_PHYCORE
+                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                   CYGPKG_IO_SERIAL_ARM_AT91
+                   CYGPKG_DEVICES_WATCHDOG_ARM_AT91
+                   CYGPKG_DEVS_ADC_ARM_AT91
+        }
+        description "
+	The phyCORE AT91M55800A target provides the packages needed to 
+        run eCos on an PHYTEC evaluation board (phycore AT91M55800A based 
+        on HD200)."
+}
+
+target mcb2100 {
+        alias { "Keil evaluation board MCB2100" }
+        packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_LPC2XXX
+                   CYGPKG_HAL_ARM_LPC2XXX_MCB2100
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+                   CYGPKG_IO_SERIAL_ARM_LPC2XXX
+                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
+        }
+        description "
+        The mcb2100 target provides the packages needed to run eCos on the
+        MCB2100 evaluation board from Keil."
+}
+
+target p2106 {
+        alias { "Olimex evaluation board LPC-P2106" }
+        packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_LPC2XXX
+                   CYGPKG_HAL_ARM_LPC2XXX_P2106
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+                   CYGPKG_IO_SERIAL_ARM_LPC2XXX
+                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
+        }
+        description "
+        The p2106 target provides the packages needed to run eCos on the
+        LPC-P2106 evaluation board from Olimex."
+}
+
+target lpcmt {
+	alias { "Olimex evaluation board LPC-LPCMT" }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_LPC2XXX
+                   CYGPKG_HAL_ARM_LPC2XXX_LPCMT
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+                   CYGPKG_IO_SERIAL_ARM_LPC2XXX
+                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
+        }
+        description "
+        The lpcmt target provides the packages needed to run eCos on the
+        LPC-LPCMT evaluation board from Olimex."
+}
+
+target phycore229x {
+        alias { "phyCORE-LPC2294/92 development board HAL" }
+        packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_LPC2XXX
+                   CYGPKG_HAL_ARM_LPC2XXX_PHYCORE229X 
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+                   CYGPKG_IO_SERIAL_ARM_LPC2XXX
+                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
+                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                   CYGPKG_DEVS_FLASH_PHYCORE229X
+                   CYGPKG_DEVS_ETH_ARM_PHYCORE229X
+                   CYGPKG_DEVS_ETH_SMSC_LAN91CXX
+                   CYGPKG_DEVS_CAN_LPC2XXX
+        }
+        description "
+            The phyCORE-LPC229x HAL package provides the support
+            needed to run eCos on a Phytec phyCORE-LPC2294/2
+            development board."
+}
+
+target ea2468 {
+        alias { "Embedded Artists LPC2468 OEM board HAL" }
+        packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_LPC24XX
+                   CYGPKG_HAL_ARM_LPC24XX_EA2468 
+                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX                        
+                   CYGPKG_DEVICES_WALLCLOCK_ARM_LPC2XXX
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+                   CYGPKG_IO_SERIAL_ARM_LPC24XX
+                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
+                   CYGPKG_DEVS_CAN_LPC2XXX
+                   CYGPKG_DEVS_FLASH_EA2468
+                   CYGPKG_DEVS_FLASH_SST_39VFXXX
+                   CYGPKG_DEVS_ETH_PHY
+                   CYGPKG_DEVS_ETH_ARM_LPC2XXX
+                   CYGPKG_IO_I2C
+                   CYGPKG_DEVS_I2C_ARM_LPC2XXX     
+                   CYGPKG_DEVS_ADC_ARM_LPC24XX
+                   CYGPKG_DEVS_NAND_SAMSUNG_K9
+        }
+        description "
+            The Embedded Artists LPC2468 HAL package provides the support
+            needed to run eCos on an Embedded Artists LPC2468 OEM board."
+}
+
+target olpch2294 {
+        alias { "Olimex LPC-H2294 header board" }
+        packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_LPC2XXX
+                   CYGPKG_HAL_ARM_LPC2XXX_OLPCH2294
+                   CYGPKG_DEVS_FLASH_STRATA_V2
+                   CYGPKG_DEVS_FLASH_ARM_OLPCX2294_V2
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+                   CYGPKG_IO_SERIAL_ARM_LPC2XXX
+                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
+        }
+        description "
+            The olpch2294 target provides the packages needed to run
+            eCos on Olimex LPC-H2294 header board."
+}
+
+
+target olpce2294 {
+        alias { "Olimex LPC-E2294 development board" }
+        packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_LPC2XXX
+                   CYGPKG_HAL_ARM_LPC2XXX_OLPCE2294
+                   CYGPKG_DEVS_FLASH_STRATA_V2
+                   CYGPKG_DEVS_FLASH_ARM_OLPCX2294_V2
+                   CYGPKG_DEVS_ETH_CL_CS8900A
+                   CYGPKG_DEVS_ETH_ARM_OLPCE2294
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+                   CYGPKG_IO_SERIAL_ARM_LPC2XXX
+                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
+                   CYGPKG_DEVS_CAN_LPC2XXX
+        }
+        description "
+            The olpce2294 target provides the packages needed to run
+            eCos on Olimex LPC-E2294 development board."
+}
+
+target olpcl2294 {
+        alias { "Olimex LPC-L2294-1MB development board" }
+        packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_LPC2XXX
+                   CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294
+                   CYGPKG_DEVS_FLASH_STRATA_V2
+                   CYGPKG_DEVS_FLASH_ARM_OLPCX2294_V2
+                   CYGPKG_DEVS_ETH_CL_CS8900A
+                   CYGPKG_DEVS_ETH_ARM_OLPCL2294
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+                   CYGPKG_IO_SERIAL_ARM_LPC2XXX
+                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
+                   CYGPKG_DEVS_CAN_LPC2XXX
+        }
+        description "
+            The olpcl2294 target provides the packages needed to run
+            eCos on Olimex LPC-L2294-1MB development board."
+}
+
+target mace1 {
+	alias { "MACE1 - a MAC7100 evaluation board" mac7100_mace1 }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_MAC7100
+                   CYGPKG_HAL_ARM_MAC7100_MACE1
+                   CYGPKG_IO_SERIAL_FREESCALE_ESCI_H
+                   CYGPKG_IO_SERIAL_FREESCALE_ESCI
+        }
+        description "
+            The mace1 target provides the packages needed to run eCos
+            on MAC7100 evaluation board (MACE1).  "
+}
+
+target mac7100evb {
+	alias { "MAC7100EVB - Freescale MAC7100 evaluation board" mac7100_mac7100evb }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_MAC7100
+                   CYGPKG_HAL_ARM_MAC7100_MAC7100EVB
+                   CYGPKG_IO_SERIAL_FREESCALE_ESCI_H
+                   CYGPKG_IO_SERIAL_FREESCALE_ESCI
+        }
+        description "
+            The MAC7100EVB target provides the packages needed to run eCos
+            on Freescale MAC7100EVB evaluation board.  "
+}
+
+target ebsa285 {
+	alias { "Intel EBSA285 StrongARM board" ebsa }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_EBSA285
+                   CYGPKG_IO_PCI
+		   CYGPKG_DEVS_ETH_ARM_EBSA285
+                   CYGPKG_DEVS_ETH_INTEL_I82559
+		   CYGPKG_IO_SERIAL_ARM_EBSA285
+                   CYGPKG_DEVICES_WATCHDOG_ARM_EBSA285
+		   CYGPKG_DEVS_FLASH_EBSA285
+        }
+        description "
+        The ebsa285 target provides the packages needed to run
+        eCos on an Intel EBSA285 StrongARM board."
+}
+
+
+target aaed2000 {
+	alias { "Agilent AAED2000 unit" aaed }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_ARM9
+                   CYGPKG_HAL_ARM_ARM9_AAED2000
+                   CYGPKG_DEVS_FLASH_ARM_AAED2000
+                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                   CYGPKG_DEVS_ETH_CL_CS8900A
+                   CYGPKG_DEVS_ETH_ARM_AAED2000
+                   CYGPKG_DEVS_KBD_AAED2000
+                   CYGPKG_DEVS_TOUCH_AAED2000
+        }
+        description "
+        The AAED2000 target provides the packages needed to run
+        eCos on an Agilent AAED2000 board."
+}
+
+target excalibur_arm9 {
+	alias { "Altera ARM9/Excalibur board" epxa10 }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_ARM9
+                   CYGPKG_HAL_ARM_ARM9_EXCALIBUR
+                   CYGPKG_DEVS_FLASH_INTEL_28FXXX
+                   CYGPKG_DEVS_FLASH_ARM_EXCALIBUR
+        }
+        description "
+        The Excalibur target provides the packages needed to run
+        eCos on an Altera Excalibur board."
+}
+
+target smdk2410 {
+        alias { "Samsung ARM9/SMDK2410 development board" s3c2410x }
+        packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_ARM9
+                   CYGPKG_HAL_ARM_ARM9_SMDK2410
+                   CYGPKG_IO_SERIAL_ARM_SMDK2410
+                   CYGPKG_DEVS_FLASH_ARM_SMDK2410
+                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+        }
+        description "
+        The SMDK2410 target provides the packages needed to run eCos on 
+        Samsung S3c2410x (ARM920T) based development boards (SMDK2410)."
+}
+
+target innovator {
+	alias { "Innovator (ARM) board" }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_ARM9
+                   CYGPKG_HAL_ARM_ARM9_INNOVATOR
+                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                   CYGPKG_DEVS_FLASH_ARM_INNOVATOR
+		   CYGPKG_DEVS_ETH_SMSC_LAN91CXX
+		   CYGPKG_DEVS_ETH_ARM_INNOVATOR
+        }
+        description "
+        The Innovator HAL package provides the support needed to run
+        RedBoot on the ARM processor of the Innovator.
+	
+	NOTE: Full support for eCos is not provided yet.  This HAL
+	contains only the minimum amount necessary to run RedBoot
+	on the Innovator.  In particular, interrupts are not yet
+	supported.  Watch this space for more details in the near
+	future."
+}
+
+target assabet {
+	alias { "Intel StrongARM SA1110 board" }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_SA11X0
+                   CYGPKG_HAL_ARM_SA11X0_ASSABET
+		   CYGPKG_IO_SERIAL_ARM_SA11X0
+		   CYGPKG_DEVS_PCMCIA_ASSABET
+                   CYGPKG_DEVS_FLASH_STRATA
+		   CYGPKG_DEVS_FLASH_ASSABET
+                   CYGPKG_IO_USB
+                   CYGPKG_IO_USB_SLAVE
+                   CYGPKG_DEVS_USB_SA11X0
+		   CYGPKG_DEVICES_WATCHDOG_ARM_SA11X0
+                   CYGPKG_DEVS_ETH_CF
+                   CYGPKG_DEVS_ETH_NS_DP83902A
+        }
+        description "
+        The assabet target provides the packages needed to run
+        eCos on an Intel StrongARM SA1110 evaluation board."
+}
+
+target cerf {
+	alias { "Intrinsyc SA1110 Cerf board" cerf_cube }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_SA11X0
+                   CYGPKG_HAL_ARM_SA11X0_CERF
+		   CYGPKG_IO_SERIAL_ARM_SA11X0
+		   CYGPKG_DEVS_PCMCIA_CERF
+                   CYGPKG_DEVS_FLASH_STRATA
+		   CYGPKG_DEVS_FLASH_CERF
+                   CYGPKG_IO_USB
+                   CYGPKG_IO_USB_SLAVE
+                   CYGPKG_DEVS_USB_SA11X0
+		   CYGPKG_DEVICES_WATCHDOG_ARM_SA11X0
+                   CYGPKG_DEVS_ETH_CF
+		   CYGPKG_DEVS_ETH_ARM_CERF
+                   CYGPKG_DEVS_ETH_CL_CS8900A
+        }
+        description "
+        The cerf target provides the packages needed to run
+        eCos on an Intrinsyc SA1110 Cerf board."
+}
+
+target cerfpda {
+	alias { "Intrinsyc SA1110 Cerfpda" cerf_pda }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_SA11X0
+                   CYGPKG_HAL_ARM_SA11X0_CERFPDA
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+	           CYGPKG_IO_SERIAL_ARM_CERFPDA
+		   CYGPKG_IO_SERIAL_ARM_SA11X0
+		   CYGPKG_DEVS_PCMCIA_CERFPDA
+                   CYGPKG_DEVS_FLASH_STRATA
+		   CYGPKG_DEVS_FLASH_CERFPDA
+                   CYGPKG_IO_USB
+                   CYGPKG_IO_USB_SLAVE
+                   CYGPKG_DEVS_USB_SA11X0
+		   CYGPKG_DEVICES_WATCHDOG_ARM_SA11X0
+                   CYGPKG_DEVS_ETH_CF
+		   CYGPKG_DEVS_ETH_ARM_CERFPDA
+                   CYGPKG_DEVS_ETH_CL_CS8900A
+        }
+        description "
+        The cerfpda target provides the packages needed to run
+        eCos on an Intrinsyc SA1110 cerfpda."
+}
+
+target ipaq {
+	alias { "Compaq iPAQ Pocket PC" }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_SA11X0
+                   CYGPKG_HAL_ARM_SA11X0_IPAQ
+		   CYGPKG_IO_SERIAL_ARM_SA11X0
+		   CYGPKG_DEVS_PCMCIA_IPAQ
+                   CYGPKG_DEVS_FLASH_IPAQ
+                   CYGPKG_DEVS_FLASH_STRATA
+		   CYGPKG_DEVICES_WATCHDOG_ARM_SA11X0
+                   CYGPKG_DEVS_TOUCH_IPAQ
+                   CYGPKG_DEVS_KBD_IPAQ
+                   CYGPKG_DEVS_ETH_CF
+                   CYGPKG_DEVS_ETH_NS_DP83902A
+        }
+        description "
+        The IPAQ target provides the packages needed to run
+        eCos on an Intel StrongARM SA1110 Pocket PC (Compaq iPAQ)."
+}
+
+
+target nano {
+	alias { "nanoEngine StrongARM SA1110 board" nanoEngine }
+        packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_SA11X0
+                   CYGPKG_HAL_ARM_SA11X0_NANO
+                   CYGPKG_IO_SERIAL_ARM_SA11X0
+                   CYGPKG_DEVS_FLASH_NANO
+                   CYGPKG_DEVS_FLASH_STRATA
+		   CYGPKG_DEVICES_WATCHDOG_ARM_SA11X0
+                   CYGPKG_IO_PCI
+                   CYGPKG_DEVS_ETH_ARM_NANO
+                   CYGPKG_DEVS_ETH_INTEL_I82559
+        }
+        description "
+        The nanoEngine target provides the packages needed to run
+        eCos on a Bright Star Engineering nanoEngine StrongARM SA1110 board."
+}
+
+target flexanet {
+      alias { "Flexanet StrongARM SA1110 platform" }
+      packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_SA11X0
+                   CYGPKG_HAL_ARM_SA11X0_FLEXANET
+                   CYGPKG_IO_SERIAL_ARM_SA11X0
+                   CYGPKG_DEVS_FLASH_STRATA
+                   CYGPKG_DEVS_FLASH_FLEXANET
+                   CYGPKG_DEVS_ETH_SMSC_LAN91CXX
+                   CYGPKG_DEVS_ETH_ARM_FLEXANET
+                   CYGPKG_IO_USB
+                   CYGPKG_IO_USB_SLAVE
+                   CYGPKG_DEVS_USB_SA11X0
+                   CYGPKG_DEVICES_WATCHDOG_ARM_SA11X0
+        }
+        description "
+          The Flexanet target provides the packages needed to run
+          eCos on an SA1110 Flexanet board."
+}
+
+target brutus {
+	alias { "Intel StrongARM SA1100 board" }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_SA11X0
+                   CYGPKG_HAL_ARM_SA11X0_BRUTUS
+		   CYGPKG_IO_SERIAL_ARM_SA11X0
+        }
+        description "
+        The brutus target provides the packages needed to run
+        eCos on an Intel StrongARM SA1100 evaluation board."
+}
+
+target sa1100mm {
+	alias { "Intel StrongARM SA1100 Multimedia board" }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_SA11X0
+                   CYGPKG_HAL_ARM_SA11X0_SA1100MM
+		   CYGPKG_IO_SERIAL_ARM_SA11X0
+		   CYGPKG_DEVS_FLASH_SA1100MM
+        }
+        description "
+        The sa1100mm target provides the packages needed to run
+        eCos on an Intel StrongARM SA1100 Multimedia evaluation board."
+}
+
+target iq80310 {
+ 	alias { "Intel IQ80310 XScale board" cyclone }
+        packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_XSCALE_CORE
+                   CYGPKG_HAL_ARM_XSCALE_IOP310
+                   CYGPKG_HAL_ARM_XSCALE_IQ80310
+                   CYGPKG_IO_PCI
+                   CYGPKG_DEVS_ETH_INTEL_I82559
+                   CYGPKG_DEVS_ETH_ARM_XSCALE_IQ80310
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+                   CYGPKG_IO_SERIAL_ARM_XSCALE_IOP310
+                   CYGPKG_DEVS_FLASH_ARM_XSCALE_IQ80310
+        }
+        description "
+        The iq80310 target provides the packages needed to run
+        eCos on a Cyclone IQ80310 board."
+}
+
+target npwr {
+	alias { "NPWR Linux Engine (Intel XScale)" }
+        packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_XSCALE_CORE
+                   CYGPKG_HAL_ARM_XSCALE_IOP310
+                   CYGPKG_HAL_ARM_XSCALE_NPWR
+                   CYGPKG_DEVS_FLASH_ARM_XSCALE_IQ80310
+                   CYGPKG_DEVS_ETH_INTEL_I82544
+                   CYGPKG_DEVS_ETH_ARM_XSCALE_NPWR
+                   CYGPKG_IO_PCI
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+                   CYGPKG_IO_SERIAL_ARM_XSCALE_IOP310
+        }
+        description "
+        The npwr target provides the packages needed to run
+        eCos on a NPWR Linux Engine."
+}
+
+target iq80321 {
+	alias { "Intel XScale IQ80321 Board" }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_XSCALE_CORE
+                   CYGPKG_HAL_ARM_XSCALE_VERDE
+                   CYGPKG_HAL_ARM_XSCALE_IQ80321
+                   CYGPKG_IO_PCI
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+		   CYGPKG_IO_SERIAL_ARM_IQ80321
+                   CYGPKG_DEVS_ETH_INTEL_I82544
+                   CYGPKG_DEVS_FLASH_STRATA
+                   CYGPKG_DEVS_FLASH_IQ80321
+                   CYGPKG_DEVS_ETH_ARM_IQ80321
+        }
+        description "
+        The IQ80321 target provides the packages needed to run
+        eCos on an Intel XScale IQ80321 board."
+}
+
+target ixdp425 {
+	alias { "IXDP425 board" }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_XSCALE_CORE
+	           CYGPKG_HAL_ARM_XSCALE_IXP425
+                   CYGPKG_HAL_ARM_XSCALE_IXDP425
+		   CYGPKG_IO_PCI
+                   CYGPKG_DEVS_ETH_INTEL_I82559
+		   CYGPKG_DEVS_ETH_ARM_IXDP425_I82559
+                   CYGPKG_DEVS_FLASH_STRATA_V2
+        }
+        description "
+        The ixdp425 target provides the packages needed to run
+        eCos on an Intel network processor evaluation board."
+}
+
+target XSEngine {
+        alias { "Exys XSEngine Board" xsengine }
+        packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_XSCALE_CORE
+                   CYGPKG_HAL_ARM_XSCALE_PXA2X0
+                   CYGPKG_HAL_ARM_XSCALE_XSENGINE
+                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                   CYGPKG_DEVS_FLASH_XSENGINE
+                   CYGPKG_DEVS_ETH_SMSC_LAN91CXX
+                   CYGPKG_DEVS_ETH_ARM_XSCALE_XSENGINE
+        }
+        description "
+            The XSEngine target provides the packages needed to run
+            eCos on an Exys XSEngine board."
+}
+
+target grg {
+	alias { "Generic Residential Gateway" }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_XSCALE_CORE
+	           CYGPKG_HAL_ARM_XSCALE_IXP425
+                   CYGPKG_HAL_ARM_XSCALE_GRG
+		   CYGPKG_IO_PCI
+                   CYGPKG_DEVS_ETH_INTEL_I82559
+                   CYGPKG_DEVS_ETH_ARM_GRG_I82559
+                   CYGPKG_DEVS_FLASH_STRATA
+		   CYGPKG_DEVS_FLASH_GRG
+        }
+        description "
+        The grg target provides the packages needed to run
+        eCos on an Intel Generic Residential Gateway board."
+}
+
+target prpmc1100 {
+	alias { "Motorola PrPMC1100" }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_XSCALE_CORE
+	           CYGPKG_HAL_ARM_XSCALE_IXP425
+                   CYGPKG_HAL_ARM_XSCALE_PRPMC1100
+		   CYGPKG_IO_PCI
+                   CYGPKG_DEVS_FLASH_STRATA
+		   CYGPKG_DEVS_FLASH_PRPMC1100
+        }
+        description "
+        The prpmc1100 target provides the packages needed to run
+        eCos on a Motorola PrPMC1100."
+}
+
+target edb7xxx {
+        alias		{ "Cirrus Logic EDB7xxx development board" edb7211 eb7xxx eb7211 }
+	packages	{ CYGPKG_HAL_ARM
+                          CYGPKG_HAL_ARM_EDB7XXX
+			  CYGPKG_DEVS_ETH_ARM_EDB7XXX
+                          CYGPKG_DEVS_ETH_CL_CS8900A
+	                  CYGPKG_IO_SERIAL_ARM_EDB7XXX
+			  CYGPKG_DEVS_FLASH_EDB7XXX
+        }
+        description "
+The edb7xxx target provides the packages needed to run eCos on the Cirrus Logic EDB7xxx development boards."
+    }
+
+target pati {
+        alias           { "MPL PATI" }
+        packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_MPC5xx
+                          CYGPKG_HAL_POWERPC_PATI
+                          CYGPKG_IO_SERIAL_POWERPC_MPC555
+                          CYGPKG_DEVICES_WALLCLOCK_MPC5xx
+                          CYGPKG_DEVS_FLASH_PATI
+                          CYGPKG_DEVS_FLASH_INTEL_28FXXX
+        }
+        description "
+            The pati target provides the packages needed to run
+            eCos on a PATI MPC555 PC/104+ board from MLP
+            elektronik."
+}
+
+target cma230 {
+        alias		{ "Cogent CMA230/222 board" cma222 }
+	packages	{ CYGPKG_HAL_ARM
+                          CYGPKG_HAL_ARM_CMA230
+	                  CYGPKG_IO_SERIAL_ARM_CMA230
+        }
+        description "
+The cma230 target provides the packages needed to run eCos on a Cogent 
+CMA230 (ARM7TDMI) or CMA222 (ARM710T) board."
+    }
+
+
+target snds {
+      alias { "Samsung SNDS" SNDS snds100 }
+      packages { CYGPKG_HAL_ARM 
+                 CYGPKG_HAL_ARM_SNDS 
+                 CYGPKG_DEVS_ETH_ARM_KS32C5000
+               }
+      enable { CYGHWR_HAL_ARM_BIGENDIAN }
+      description "
+        The snds target provides the packages needed to run eCos on a
+        Samsung SNDS eval board."
+}
+
+target aim711 {
+      alias { "ARM Industrial Module AIM 711" AIM711 }
+      packages {
+                   CYGPKG_HAL_ARM 
+                   CYGPKG_HAL_ARM_AIM711 
+                   CYGPKG_DEVS_FLASH_SST_39VFXXX
+                   CYGPKG_DEVS_FLASH_ARM_AIM711
+                   CYGPKG_DEVS_ETH_ARM_KS32C5000
+                   CYGPKG_IO_SERIAL_ARM_AIM711
+                   CYGPKG_IO_SERIAL_ARM_S3C4510
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+                   CYGPKG_DEVICES_WALLCLOCK_ARM_AIM711
+                   CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1307 
+               }
+      description "
+        The aim711 target provides the packages needed to run eCos on a
+        ARM Industrial Module AIM 711."
+ }
+
+
+target mpc50 {
+	alias { "MICROPLEX Printer Controller 5.0" }
+	packages {
+				CYGPKG_HAL_ARM
+				CYGPKG_HAL_ARM_XSCALE_CORE
+				CYGPKG_HAL_ARM_XSCALE_PXA2X0
+				CYGPKG_HAL_ARM_XSCALE_MPC50
+				CYGPKG_DEVS_FLASH_STRATA
+				CYGPKG_DEVS_FLASH_MPC50
+        }
+        description "
+        MICROPLEX Printer Controller 5.0"
+}
+
+# --------------------------------------------------------------------------
+# SH targets
+
+target sh7708 {
+	alias       { "Hitachi EDK/SH7708 board" edk7708 }
+	packages    { CYGPKG_HAL_SH
+                      CYGPKG_HAL_SH_SH3
+                      CYGPKG_HAL_SH_EDK7708
+                      CYGPKG_DEVICES_WALLCLOCK_SH3 
+	              CYGPKG_IO_SERIAL_SH_SCI
+	              CYGPKG_IO_SERIAL_SH_EDK7708
+                      CYGPKG_DEVICES_WATCHDOG_SH_SH3
+                      CYGPKG_DEVS_FLASH_SH_EDK7708
+                      CYGPKG_DEVS_FLASH_ATMEL_AT29CXXXX
+        }
+        description "
+           The sh7708 target provides the packages needed to run
+           eCos on a Hitachi EDK/SH7708 board."
+}
+target cq7708 {
+        alias { "CqREEK SH7708 board" }
+        packages { CYGPKG_HAL_SH
+                   CYGPKG_HAL_SH_SH3
+                   CYGPKG_HAL_SH_SH7708_CQ7708
+	           CYGPKG_IO_SERIAL_SH_SCI
+	           CYGPKG_IO_SERIAL_SH_CQ7708
+        }
+        description "
+           The cq7708 target provides the packages needed to run
+           eCos on a CqREEK SH7708 board."
+}
+
+target cq7750 {
+        alias { "CqREEK SH7750 board" cqsh4 }
+        packages { CYGPKG_HAL_SH
+                   CYGPKG_HAL_SH_SH4
+                   CYGPKG_HAL_SH_SH7750_CQ7750
+		   CYGPKG_DEVS_FLASH_CQ7750
+		   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                   CYGPKG_IO_SERIAL_SH_SCIF }
+        description "
+           The sh7750 target provides the packages needed to run
+           eCos on a CqREEK SH7750 board."
+}
+
+target hs7729pci {
+        alias       { "Hitachi HS7729PCI board" hs7729 }
+        packages    { CYGPKG_HAL_SH
+                      CYGPKG_HAL_SH_SH3
+                      CYGPKG_HAL_SH_SH7729_HS7729PCI
+                      CYGPKG_DEVS_FLASH_SH_HS7729PCI
+                      CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                      CYGPKG_IO_PCI
+                      CYGPKG_DEVS_ETH_SH_HS7729PCI
+                      CYGPKG_DEVS_ETH_VIA_RHINE
+                      CYGPKG_DEVICES_WATCHDOG_SH_SH3
+                      CYGPKG_DEVICES_WALLCLOCK_SH_HS7729PCI
+                      CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS12887
+        }
+        description "
+           The hs7729pci target provides the packages needed to run
+           eCos on a Hitachi HS7729PCI board."
+}
+
+target se77x9 {
+        alias       { "Hitachi SE77x9 board" }
+        packages    { CYGPKG_HAL_SH
+                      CYGPKG_HAL_SH_SH3
+                      CYGPKG_HAL_SH_SH77X9_SE77X9
+                      CYGPKG_DEVS_FLASH_SH_SE77X9
+                      CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                      CYGPKG_DEVS_ETH_NS_DP83902A
+                      CYGPKG_DEVS_ETH_SH_SE77X9
+                      CYGPKG_IO_SERIAL_SH_SE77X9
+                      CYGPKG_IO_SERIAL_SH_SCIF
+                      CYGPKG_IO_SERIAL_GENERIC_16X5X
+                      CYGPKG_DEVICES_WATCHDOG_SH_SH3
+        }
+        description "
+           The se77x9 target provides the packages needed to run
+           eCos on a Hitachi Solution Engine 77x9 board."
+}
+
+target se7751 {
+        alias       { "Hitachi SE7751 board" }
+        packages    { CYGPKG_HAL_SH
+                      CYGPKG_HAL_SH_SH4
+                      CYGPKG_HAL_SH_SH7751_SE7751
+                      CYGPKG_IO_PCI
+                      CYGPKG_DEVS_FLASH_SH_SE7751
+                      CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                      CYGPKG_IO_SERIAL_SH_SCIF
+                      CYGPKG_DEVICES_WATCHDOG_SH_SH3
+                      CYGPKG_DEVS_ETH_SH_SE7751
+                      CYGPKG_DEVS_ETH_AMD_PCNET
+        }
+        description "
+           The se7751 target provides the packages needed to run
+           eCos on a Hitachi Solution Engine 7751 board."
+}
+
+target dreamcast {
+        alias { "SEGA Dreamcast" }
+        packages { CYGPKG_HAL_SH
+                   CYGPKG_HAL_SH_SH4
+                   CYGPKG_HAL_SH_SH7750_DREAMCAST
+                   CYGPKG_IO_PCI
+		   CYGPKG_DEVS_ETH_RLTK_8139
+	           CYGPKG_DEVS_ETH_SH_DREAMCAST_RLTK8139
+                   CYGPKG_IO_SERIAL_SH_SCIF }
+        description "
+           The sh7750 target provides the packages needed to run
+           eCos on SEGA Dreamcast."
+}
+
+target sh4_202_md {
+        alias       { "SuperH SH4-202 MicroDev CPU board" }
+        packages    { CYGPKG_HAL_SH
+                      CYGPKG_HAL_SH_SH4
+                      CYGPKG_HAL_SH_SH4_202_MD
+                      CYGPKG_DEVS_FLASH_STRATA
+                      CYGPKG_DEVS_FLASH_SH_MICRODEV
+                      CYGPKG_IO_SERIAL_SH_SCIF
+                      CYGPKG_IO_SERIAL_SH_SH4_202_MD
+                      CYGPKG_DEVS_ETH_SH_MICRODEV
+                      CYGPKG_DEVS_ETH_SMSC_LAN91CXX
+        }
+        description "
+           The sh4_202_md target provides the packages needed to run
+           eCos on a SuperH SH4-202 MicroDev CPU board."
+}
+
+# --------------------------------------------------------------------------
+# i386 targets
+target pc_i82559 {
+        alias		{ "i386 PC target with i82559 ethernet" pc }
+	packages        { CYGPKG_HAL_I386
+                          CYGPKG_HAL_I386_GENERIC
+                          CYGPKG_HAL_I386_PC
+                          CYGPKG_HAL_I386_PCMB
+			  CYGPKG_IO_PCI
+                          CYGPKG_IO_SERIAL_GENERIC_16X5X
+	                  CYGPKG_IO_SERIAL_I386_PC
+			  CYGPKG_DEVS_ETH_INTEL_I82559
+			  CYGPKG_DEVS_ETH_I386_PC_I82559
+                          CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS12887
+                          CYGPKG_DEVICES_WALLCLOCK_I386_PC
+        }
+        description "
+    	    The pc_i82559 target provides the 
+    	    packages needed to run eCos binaries on a standard i386
+    	    PC motherboard with an Intel 82559 based ethernet interface."
+}
+
+target pc_i82544 {
+        alias		{ "i386 PC target with i82544 gigabit ethernet" pc_giga }
+	packages        { CYGPKG_HAL_I386
+                          CYGPKG_HAL_I386_GENERIC
+                          CYGPKG_HAL_I386_PC
+                          CYGPKG_HAL_I386_PCMB
+			  CYGPKG_IO_PCI
+                          CYGPKG_IO_SERIAL_GENERIC_16X5X
+	                  CYGPKG_IO_SERIAL_I386_PC
+			  CYGPKG_DEVS_ETH_INTEL_I82544
+			  CYGPKG_DEVS_ETH_I386_PC_I82544
+                          CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS12887
+                          CYGPKG_DEVICES_WALLCLOCK_I386_PC
+        }
+        description "
+    	    The pc_i82544 target provides the packages needed to run eCos binaries
+            on a standard i386 PC motherboard with an Intel 82543/82544 based
+            gigabit ethernet interface."
+}
+
+target pc_vmWare {
+        alias		{ "i386 PC target (vmWare)" }
+	packages        { CYGPKG_HAL_I386
+                          CYGPKG_HAL_I386_GENERIC
+                          CYGPKG_HAL_I386_PC
+                          CYGPKG_HAL_I386_PCMB
+			  CYGPKG_IO_PCI
+                          CYGPKG_IO_SERIAL_GENERIC_16X5X
+	                  CYGPKG_IO_SERIAL_I386_PC
+			  CYGPKG_DEVS_ETH_AMD_LANCEPCI
+			  CYGPKG_DEVS_ETH_I386_PC_LANCEPCI
+                          CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS12887
+                          CYGPKG_DEVICES_WALLCLOCK_I386_PC
+        }
+        description "
+    	    The pc_vmWare target provides the packages needed to run eCos binaries
+            on a standard i386 PC under wmWare."
+}
+
+
+target pc_usb_d12 {
+        alias		{ "i386 PC target with SoRo PC/104 D12 USB Slave" }
+	packages        { CYGPKG_HAL_I386
+                          CYGPKG_HAL_I386_GENERIC
+                          CYGPKG_HAL_I386_PC
+                          CYGPKG_HAL_I386_PCMB
+                          CYGPKG_IO_PCI
+                          CYGPKG_IO_SERIAL_GENERIC_16X5X
+                          CYGPKG_IO_SERIAL_I386_PC
+                          CYGPKG_IO_USB
+                          CYGPKG_IO_USB_SLAVE
+                          CYGPKG_DEVS_USB_D12
+                          CYGPKG_DEVS_USB_I386_SOROD12
+                          CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS12887
+                          CYGPKG_DEVICES_WALLCLOCK_I386_PC
+        }
+        description "
+    	    Provides the packages needed to run eCos binaries
+	    on a standard i386 PC motherboard with USB Slave support for the
+	    Philips D12 chip."
+}
+
+# --------------------------------------------------------------------------
+# Synthetic targets.
+target linux {
+        alias		{ "Linux synthetic target" i386linux }
+	packages        { CYGPKG_HAL_SYNTH
+                      CYGPKG_HAL_SYNTH_I386
+                      CYGPKG_DEVS_FLASH_SYNTH_V2
+                      CYGPKG_DEVS_ETH_ECOSYNTH
+                      CYGPKG_DEVS_WATCHDOG_SYNTH
+                      CYGPKG_DEVS_WALLCLOCK_SYNTH      
+                      CYGPKG_DEVS_FRAMEBUF_SYNTH
+                      CYGPKG_DEVS_ADC_SYNTH
+                      CYGPKG_DEVS_DISK_ECOSYNTH
+                      CYGPKG_DEVS_NAND_SYNTH
+        }
+        description "
+    	    The linux target provides the 
+    	    packages needed to run eCos binaries on top of the i386
+    	    Linux kernel."
+}
+
+# --------------------------------------------------------------------------
+# SPARClite targets
+
+target sleb {
+	alias		{ "Fujitsu MB86800-MA01 board" }
+	packages        { CYGPKG_HAL_SPARCLITE
+                          CYGPKG_HAL_SPARCLITE_SLEB
+	                  CYGPKG_IO_SERIAL_SPARCLITE_SLEB
+        }
+        description "
+    	    The sleb target provides the packages need to run eCos
+            on a Fujitsu MB86800-MA01 board."
+}
+
+target sparclite_sim {
+	alias		{ "SPARClite simulator" sl_sim sparcl_sim }
+	packages        { CYGPKG_HAL_SPARCLITE 
+                          CYGPKG_HAL_SPARCLITE_SIM
+        }
+        description "
+    	    The sparclite_sim target provides the packages need to run eCos
+            on the SPARClite simulator."
+}
+
+# --------------------------------------------------------------------------
+# SPARC V7/V8 targets
+
+target sparc_erc32 {
+	alias		{ "ERC32 processor" erc32 }
+	packages        { CYGPKG_HAL_SPARC 
+                          CYGPKG_HAL_SPARC_ERC32
+        }
+        description "
+    	    The sparc_erc32 target provides the packages need to run eCos
+            on the ERC32 processor or TSIM/ERC32 simulator."
+}
+
+target sparc_leon {
+	alias		{ "LEON processor" leon }
+	packages        { CYGPKG_HAL_SPARC 
+                          CYGPKG_HAL_SPARC_LEON
+        }
+        description "
+    	    The sparc_leon target provides the packages need to run eCos
+            on the LEON processor or TSIM/LEON simulator."
+}
+
+# --------------------------------------------------------------------------
+# PowerPC targets
+target cme555 {
+        alias           { "Axiom's CME555 board" }
+        packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_MPC5xx
+                          CYGPKG_HAL_POWERPC_CME555
+                          CYGPKG_DEVS_FLASH_CME555
+                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                          CYGPKG_IO_SERIAL_POWERPC_MPC555
+                          CYGPKG_DEVICES_WALLCLOCK_MPC5xx
+        }
+        description "
+            The cme555 target provides the packages needed to run
+            eCos on a CME555 MPC555 evaluation board from Axiom
+            Manufacturing."
+}
+
+target ec555 {
+        alias           { "Wuerz ec555" }
+        packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_MPC5xx
+                          CYGPKG_HAL_POWERPC_EC555
+                          CYGPKG_DEVS_FLASH_EC555
+                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                          CYGPKG_IO_SERIAL_POWERPC_MPC555
+                          CYGPKG_DEVICES_WALLCLOCK_MPC5xx
+        }
+        description "
+            The ec555 target provides the packages needed to run
+            eCos on a EC555 MPC555 development board from Wuerz
+            elektronik."
+}
+
+target cma28x {
+        alias		{ "Cogent CMA286/287 board" cma286 cma287 }
+	packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_MPC8xx 
+                          CYGPKG_HAL_POWERPC_COGENT
+                          CYGPKG_IO_SERIAL_POWERPC_COGENT
+        }
+        description "
+            The cma28x target provides the packages needed to run
+            eCos on a Cogent CMA286 or CMA287 board."
+}
+
+target fads {
+        alias		{ "Motorola MPC8xxFADS board" }
+	packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_MPC8xx 
+                          CYGPKG_HAL_POWERPC_FADS
+        }
+        description "
+            The fads target provides the packages needed to run
+            eCos on a Motorola MPC8xxFADS board."
+}
+
+target mbx {
+        alias		{ "Motorola MBX860/821 board" mbx860 mbx821 }
+	packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_MPC8xx
+                          CYGPKG_HAL_POWERPC_MBX
+                          CYGPKG_HAL_QUICC 
+                          CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
+                          CYGPKG_DEVS_ETH_POWERPC_QUICC
+                          CYGPKG_DEVS_ETH_POWERPC_MBX
+                          CYGPKG_DEVS_FLASH_MBX
+                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+        }
+        description "
+            The mbx target provides the packages needed to run
+            eCos on a Motorola MBX860 or MBX821 board."
+}
+
+target ts6 {
+        alias		{ "Delphi TigerSHARC-6 board" Pleiades sixpack }
+	packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_MPC8260
+                          CYGPKG_HAL_POWERPC_TS6
+                          CYGPKG_DEVS_ETH_POWERPC_QUICC2
+                          CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC
+                          CYGPKG_DEVS_FLASH_TS6
+                          CYGPKG_DEVS_FLASH_INTEL_28FXXX
+        }
+        description "
+            The ts6 target provides the packages needed to run
+            eCos on a Delphi TigerSHARC-6 board."
+}
+
+target vads {
+        alias		{ "Motorola MPC8260 VADS board" }
+	packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_MPC8260
+                          CYGPKG_HAL_POWERPC_VADS
+                          CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC
+                          CYGPKG_DEVS_ETH_POWERPC_QUICC2
+                          CYGPKG_DEVS_FLASH_VADS
+                          CYGPKG_DEVS_FLASH_INTEL_28FXXX
+        }
+        description "
+            The vads target provides the packages needed to run
+            eCos on a Motorola MPC8260 VADS board."
+}
+
+target viper {
+        alias		{ "A&M Viper PPC860 board" viper860 }
+	packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_MPC8xx
+                          CYGPKG_HAL_POWERPC_VIPER
+                          CYGPKG_HAL_QUICC 
+                          CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
+                          CYGPKG_DEVS_ETH_POWERPC_FEC
+                          CYGPKG_DEVS_ETH_POWERPC_VIPER
+                          CYGPKG_DEVS_FLASH_VIPER
+                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+        }
+        description "
+            The viper target provides the packages needed to run
+            eCos on a A&M Viper PPC860 board."
+}
+
+target psim {
+	alias		{ "PowerPC simulator" ppc_sim powerpc_sim }
+	packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_PPC60x
+                          CYGPKG_HAL_POWERPC_SIM
+        }
+        description "
+            The psim target provides the packages needed to run
+            eCos in the PSIM simulator."
+}
+
+##-------------------------------------------------------------------------------------------
+## Cogent CSB281 (PowerPC 8245) packages
+##
+package CYGPKG_HAL_POWERPC_CSB281 {
+	alias		{ "Cogent PowerPC 8245 board" hal_powerpc_csb281 }
+	directory	hal/powerpc/csb281
+	script		hal_powerpc_csb281.cdl
+	hardware
+        description "
+            The CSB281 HAL package provides the support needed to run
+            eCos on a Cogent PowerPC 8245 board."
+}
+
+package CYGPKG_DEVS_FLASH_CSB281 {
+	alias 		{ "FLASH memory support for Cogent PowerPC 8245 board" flash_csb281 }
+	directory	devs/flash/powerpc/csb281
+	script		flash_csb281.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Cogent CSB281 (PowerPC 8245) board."
+}
+
+package CYGPKG_DEVS_ETH_CSB281 {
+	alias 		{ "Cogent CSB281 (PowerPC 8245) 82559 ethernet driver"
+			   devs_eth_csb281 }
+	hardware
+	directory	devs/eth/powerpc/csb281
+	script		csb281_eth_drivers.cdl
+        description     "Ethernet driver for Cogent CSB281 (PowerPC 8245)
+                         with Intel i82559 ethernet interfaces."
+}
+
+target csb281 {
+	alias		{ "Cogent PowerPC 8245" cogent8245 }
+	packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_PPC60x
+                          CYGPKG_HAL_POWERPC_CSB281
+                          CYGPKG_DEVS_FLASH_STRATA
+                          CYGPKG_DEVS_FLASH_CSB281
+                          CYGPKG_IO_PCI
+                          CYGPKG_DEVS_ETH_CSB281
+                          CYGPKG_DEVS_ETH_INTEL_I82559
+        }
+        description "
+            The csb281 target provides the packages needed to run
+            eCos on the Cogent CSB281 (8245) board."
+}
+##-------------------------------------------------------------------------------------------
+
+# --------------------------------------------------------------------------
+# MIPS targets
+
+target jmr3904 {
+        alias		{ "Toshiba JMR-TX3904 board" jmr tx39 }
+	packages        { CYGPKG_HAL_MIPS
+                          CYGPKG_HAL_MIPS_TX39
+                          CYGPKG_HAL_MIPS_TX39_JMR3904
+	                  CYGPKG_IO_SERIAL_TX39_JMR3904
+        }
+        description "
+           The jmr3904 target provides the packages needed to run
+           eCos on a Toshiba JMR-TX3904 board. This target can also
+           be used when running in the full simulator, since the simulator provides an
+           accurate simulation of the hardware including I/O devices.
+           To use the simulator in this mode the command
+           `target sim --board=jmr3904' should be used from inside gdb."
+}
+
+target atlas_mips32_4kc {
+        alias		{ "MIPS Atlas board with Mips32 4Kc processor" }
+	packages        { CYGPKG_HAL_MIPS
+                          CYGPKG_HAL_MIPS_MIPS32
+                          CYGPKG_HAL_MIPS_ATLAS
+                          CYGPKG_IO_SERIAL_MIPS_ATLAS
+                          CYGPKG_DEVS_FLASH_ATLAS
+                          CYGPKG_DEVS_ETH_MIPS_ATLAS
+                          CYGPKG_IO_PCI
+        }
+    set_value CYGHWR_HAL_MIPS_MIPS32_CORE "4Kc"
+        description "
+           The atlas_mips32_4Kc target provides the packages needed to run
+           eCos on a MIPS Atlas board with a Mips32 4Kc processor."
+}
+
+target atlas_mips64_5kc {
+        alias		{ "MIPS Atlas board with Mips64 5Kc processor" ruby }
+	packages        { CYGPKG_HAL_MIPS
+                          CYGPKG_HAL_MIPS_MIPS64
+                          CYGPKG_HAL_MIPS_ATLAS
+                          CYGPKG_IO_SERIAL_MIPS_ATLAS
+                          CYGPKG_DEVS_FLASH_ATLAS
+                          CYGPKG_DEVS_ETH_MIPS_ATLAS
+        }
+    set_value CYGHWR_HAL_MIPS_MIPS64_CORE "5K"
+        description "
+           The atlas_mips32_5Kc target provides the packages needed to run
+           eCos on a MIPS Atlas board with a Mips64 5Kc processor."
+}
+target malta_mips32_4kc {
+        alias		{ "MIPS Malta board with Mips32 4Kc processor" }
+	packages        { CYGPKG_HAL_MIPS
+                          CYGPKG_HAL_MIPS_MIPS32
+                          CYGPKG_HAL_MIPS_MALTA
+                          CYGPKG_DEVS_FLASH_INTEL_28FXXX
+                          CYGPKG_DEVS_FLASH_MALTA
+                          CYGPKG_IO_PCI
+                          CYGPKG_DEVS_ETH_AMD_PCNET
+                          CYGPKG_DEVS_ETH_MIPS_MIPS32_MALTA
+        }
+        set_value CYGHWR_HAL_MIPS_MIPS32_CORE "4Kc"
+        description "
+           The malta_mips32_4Kc target provides the packages needed to run
+           eCos on a MIPS Malta board with a Mips32 4Kc processor."
+}
+
+target malta_mips64_5kc {
+        alias		{ "MIPS Malta board with Mips64 5Kc processor" }
+	packages        { CYGPKG_HAL_MIPS
+                          CYGPKG_HAL_MIPS_MIPS64
+                          CYGPKG_HAL_MIPS_MALTA
+                          CYGPKG_DEVS_FLASH_INTEL_28FXXX
+                          CYGPKG_DEVS_FLASH_MALTA
+                          CYGPKG_IO_PCI
+                          CYGPKG_DEVS_ETH_AMD_PCNET
+                          CYGPKG_DEVS_ETH_MIPS_MIPS32_MALTA
+        }
+        set_value CYGHWR_HAL_MIPS_MIPS64_CORE "5K"
+        description "
+           The malta_mips64_5Kc target provides the packages needed to run
+           eCos on a MIPS Malta board with a Mips64 5Kc processor."
+}
+target tx39_sim {
+        alias		{ "TX39 minimal simulator" }
+	packages        { CYGPKG_HAL_MIPS
+                          CYGPKG_HAL_MIPS_TX39
+                          CYGPKG_HAL_MIPS_SIM
+        }
+        description "
+           The tx39_sim target provides the packages needed to run
+           eCos in the TX39 minimal simulator. To use this minimal
+           simulator the command `target sim --board=jmr3904pal'
+           should be used from inside gdb. It is not possible to
+           use any of the eCos device drivers when the simulator
+           is running in this mode."
+}
+target ref4955 {
+        alias		{ "Toshiba TX4955 reference platform" tx49 }
+	packages        { CYGPKG_HAL_MIPS
+                          CYGPKG_HAL_MIPS_TX49
+                          CYGPKG_HAL_MIPS_TX49_REF4955
+                          CYGPKG_IO_SERIAL_GENERIC_16X5X
+                          CYGPKG_IO_SERIAL_MIPS_REF4955
+                          CYGPKG_DEVICES_WALLCLOCK_MIPS_REF4955
+                          CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1742
+        }
+        description "
+           The ref4955 target provides the packages needed to run
+           eCos on a Toshiba TX4955 reference platform."
+}
+
+target ocelot {
+        alias		{ "PMC-Sierra Ocelot platform" }
+	packages        { CYGPKG_HAL_MIPS
+                          CYGPKG_HAL_MIPS_RM7000
+                          CYGPKG_HAL_MIPS_RM7000_OCELOT
+                          CYGPKG_IO_PCI
+                          CYGPKG_DEVS_FLASH_MIPS_OCELOT
+                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                          CYGPKG_IO_SERIAL_GENERIC_16X5X
+                          CYGPKG_DEVS_ETH_INTEL_I82559
+                          CYGPKG_DEVS_ETH_MIPS_RM7000_OCELOT
+        }
+        description "
+           The ocelot target provides the packages needed to run
+           eCos on a PMC-Sierra Ocelot Hot-Swap Computer."
+}
+
+target vrc4373 {
+        alias		{ "NEC VRC4373 board" }
+	packages        { CYGPKG_HAL_MIPS
+                          CYGPKG_HAL_MIPS_VR4300
+                          CYGPKG_HAL_MIPS_VR4300_VRC4373
+                          CYGPKG_HAL_MIPS_VR4300_VRC437X
+	                  CYGPKG_IO_SERIAL_MIPS_VRC437X
+                          CYGPKG_DEVS_FLASH_MIPS_VRC437X
+			  CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+			  CYGPKG_IO_PCI
+        }
+        description "
+           The vrc4373 target provides the packages needed to run
+           eCos on an NEC VRC4373 board."
+}
+target vrc4375 {
+        alias		{ "NEC VRC4375 board" }
+	packages        { CYGPKG_HAL_MIPS
+                          CYGPKG_HAL_MIPS_VR4300
+                          CYGPKG_HAL_MIPS_VR4300_VRC4375
+                          CYGPKG_HAL_MIPS_VR4300_VRC437X
+	                  CYGPKG_IO_SERIAL_MIPS_VRC437X
+                          CYGPKG_DEVS_FLASH_MIPS_VRC437X
+			  CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                          CYGPKG_IO_PCI
+			  CYGPKG_DEVS_ETH_INTEL_I21143
+			  CYGPKG_DEVS_ETH_MIPS_VRC4375
+        }
+        description "
+           The vrc4375 target provides the packages needed to run
+           eCos on an NEC VRC4375 board."
+}
+
+target refidt334 {
+        alias		{ "MIPS IDT79S334A reference platform" idt32334 }
+	packages        { CYGPKG_HAL_MIPS
+                          CYGPKG_HAL_MIPS_IDT32334
+                          CYGPKG_HAL_MIPS_IDT32334_REFIDT334
+                          CYGPKG_IO_PCI
+			  CYGPKG_DEVS_ETH_INTEL_I82559
+			  CYGPKG_DEVS_ETH_MIPS_REFIDT334
+			  CYGPKG_DEVS_FLASH_MIPS_REFIDT334
+			  CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+			  CYGPKG_IO_SERIAL_MIPS_IDT79S334A
+        }
+        description "
+           The refidt334 target provides the packages needed to run
+           eCos on a MIPS IDT IDT79S334A reference board."
+}
+
+# --------------------------------------------------------------------------
+# MN10300 targets
+
+target am31_sim {
+        alias		{ "MN10300 AM31 minimal simulator" }
+	packages        { CYGPKG_HAL_MN10300
+                          CYGPKG_HAL_MN10300_AM31
+                          CYGPKG_HAL_MN10300_AM31_SIM
+        }
+        description "
+           The am31_sim target provides the packages need to run
+           eCos in the MN10300 minimal simulator. It is not possible to
+           use any of the eCos device drivers when the simulator
+           is running in this mode."
+}
+
+target stdeval1 {
+        alias		{ "Matsushita stdeval1 board" }
+	packages        { CYGPKG_HAL_MN10300 
+                          CYGPKG_HAL_MN10300_AM31_STDEVAL1 
+                          CYGPKG_HAL_MN10300_AM31 
+                          CYGPKG_IO_SERIAL_MN10300
+                          CYGPKG_DEVICES_WATCHDOG_MN10300_MN10300
+        }
+        description "
+           The stdeval1 target provides the packages needed to run
+           eCos on a Matsushita stdeval1 board. This target can also
+           be used when running in the full simulator, since the simulator provides an
+           accurate simulation of the hardware including I/O devices."
+}
+target stb {
+        alias		{ "Matsushita STB board" }
+	packages        { CYGPKG_HAL_MN10300
+                          CYGPKG_HAL_MN10300_AM33_STB
+                          CYGPKG_HAL_MN10300_AM33
+                          CYGPKG_IO_SERIAL_MN10300
+                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                          CYGPKG_DEVS_FLASH_MN10300_STB
+                          CYGPKG_DEVICES_WATCHDOG_MN10300_MN10300
+        }
+        description "
+           The stb target provides the packages needed to run
+           eCos on a Matsushita STB board."
+}
+
+target asb {
+        alias		{ "Matsushita ASB2303 board" }
+	packages        { CYGPKG_HAL_MN10300
+                          CYGPKG_HAL_MN10300_AM33_ASB
+                          CYGPKG_HAL_MN10300_AM33
+                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                          CYGPKG_DEVS_FLASH_MN10300_ASB2303
+        }
+        description "
+           The asb target provides the packages needed to run
+           eCos on a Matsushita ASB2303 board."
+}
+
+target asb2305 {
+        alias		{ "Matsushita ASB2305 board" }
+	packages        { CYGPKG_HAL_MN10300
+                          CYGPKG_HAL_MN10300_AM33_ASB2305
+                          CYGPKG_HAL_MN10300_AM33
+                          CYGPKG_IO_SERIAL_GENERIC_16X5X
+                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                          CYGPKG_DEVS_FLASH_MN10300_ASB2305
+        }
+        description "
+           The asb2305 target provides the packages needed to run
+           eCos on a Matsushita ASB2305 board."
+}
+
+# --------------------------------------------------------------------------
+# NEC targets
+
+target ceb_v850 {
+	alias { "Cosmo CEB-V850 board" CEB ceb_v850_sa1 }
+	packages { CYGPKG_HAL_V85X
+                   CYGPKG_HAL_V85X_V850
+                   CYGPKG_HAL_V85X_V850_CEB
+                   CYGPKG_IO_SERIAL_V85X_V850
+        }
+        description "
+The ceb_v850 target provides the packages needed to run eCos on a
+Cosmo CEB-V850 evaluation board fitted with a NEC V850/SA1 or NEC V850/SB1."
+}
+
+# --------------------------------------------------------------------------
+# m68k targets
+
+target m5272c3 {
+    alias { "Freescale m5272c3 evaluation board" }
+    packages {
+        CYGPKG_HAL_M68K
+        CYGPKG_HAL_M68K_MCFxxxx
+        CYGPKG_HAL_M68K_MCF5272
+        CYGPKG_HAL_M68K_M5272C3
+        CYGPKG_DEVS_ETH_MCFxxxx
+        CYGPKG_DEVS_SERIAL_MCFxxxx
+        CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2
+    }
+
+    description   "The m5272c3 target provides  the packages  needed to  run
+                eCos on the Freescale m5272c3 evaluation board."
+}
+
+# --------------------------------------------------------------------------
+# H8 targets
+
+target h8300h_sim {
+        alias		{ "H8/300H minimal simulator" }
+	packages        { CYGPKG_HAL_H8300
+                          CYGPKG_HAL_H8300_H8300H
+                          CYGPKG_HAL_H8300_H8300H_SIM
+                          CYGPKG_IO_SERIAL_H8300_SCI
+        }
+        description "
+           The h8300h_sim target provides the packages need to run
+           eCos in the H8/300H minimal simulator. It is not possible to
+           use any of the eCos device drivers when the simulator
+           is running in this mode."
+}
+
+target h8s_sim {
+        alias		{ "H8S minimal simulator" }
+	packages        { CYGPKG_HAL_H8300
+                          CYGPKG_HAL_H8300_H8S
+                          CYGPKG_HAL_H8300_H8S_SIM
+                          CYGPKG_IO_SERIAL_H8300_SCI
+        }
+        description "
+           The h8300h_sim target provides the packages need to run
+           eCos in the H8/300H minimal simulator. It is not possible to
+           use any of the eCos device drivers when the simulator
+           is running in this mode."
+}
+
+target aki3068net {
+        alias		{ "Akizuki H8/3068 Network board" }
+	packages        { CYGPKG_HAL_H8300
+                          CYGPKG_HAL_H8300_H8300H
+                          CYGPKG_HAL_H8300_H8300H_AKI3068NET
+                          CYGPKG_IO_SERIAL_H8300_SCI
+			  CYGPKG_DEVS_ETH_H8300_AKI3068NET
+                          CYGPKG_DEVICES_WATCHDOG_H8300_H8300H
+        }
+        description "
+           The aki3068net target provides the packages need to run
+           eCos in the Akizuki H8/3068 Network board."
+}
+
+target h8max {
+        alias		{ "H8MAX" }
+	packages        { CYGPKG_HAL_H8300
+                          CYGPKG_HAL_H8300_H8300H
+                          CYGPKG_HAL_H8300_H8300H_H8MAX
+                          CYGPKG_IO_SERIAL_H8300_SCI
+			  CYGPKG_DEVS_ETH_H8300_H8MAX
+                          CYGPKG_DEVICES_WATCHDOG_H8300_H8300H
+        }
+        description "
+           The h8max target provides the packages need to run
+           eCos in the strawberry-linux.com H8MAX board."
+}
+
+target edosk2674 {
+        alias		{ "EDOSK-2674" }
+	packages        { CYGPKG_HAL_H8300
+                          CYGPKG_HAL_H8300_H8S
+                          CYGPKG_HAL_H8300_H8S_EDOSK2674
+                          CYGPKG_IO_SERIAL_H8300_SCI
+			  CYGPKG_DEVS_ETH_H8300_EDOSK2674
+        }
+        description "
+           The h8max target provides the packages need to run
+           eCos in the Hitachi Micro System Europe EDOSK-2674 Evalution board."
+}
+
+# --------------------------------------------------------------------------
+# CalmRISC16 targets
+
+target calm16_ceb {
+        alias		{ "CalmRISC16 Core Eval Board" }
+	packages        { CYGPKG_HAL_CALM16
+                          CYGPKG_HAL_CALM16_CORE
+                          CYGPKG_HAL_CALM16_CEB
+        }
+        description "
+           The calm16_ceb target provides the packages needed to run
+           eCos on the CalmRISC16 Core Evaluation Board."
+}
+# --------------------------------------------------------------------------
+# CalmRISC32 targets
+
+target calm32_ceb {
+        alias		{ "CalmRISC32 Core Eval Board" }
+	packages        { CYGPKG_HAL_CALM32
+                          CYGPKG_HAL_CALM32_CORE
+                          CYGPKG_HAL_CALM32_CEB
+        }
+        description "
+           The calm32_ceb target provides the packages needed to run
+           eCos on the CalmRISC32 Core Evaluation Board."
+}
+
+# --------------------------------------------------------------------------
+
+package CYGPKG_HAL_POWERPC_TS1000 {
+	alias		{ "Allied Telesyn TS1000 board" hal_powerpc_ts1000 }
+	directory	hal/powerpc/ts1000
+	script		hal_powerpc_ts1000.cdl
+	hardware
+        description "
+            The TS1000 HAL package provides the support needed to run
+            eCos on a Allied Telesyn TS1000 board equipped with a PowerPC processor."
+}
+
+package CYGPKG_DEVS_FLASH_POWERPC_TS1000 {
+	alias 		{ "FLASH memory support for Allied Telesyn TS1000 (PPC855) board" flash_ts1000 }
+	directory	devs/flash/powerpc/ts1000
+	script		flash_ts1000.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Allied Telesyn TS1000 (PPC855) platform."
+}
+
+package CYGPKG_DEVS_ETH_POWERPC_TS1000 {
+	alias 		{ "Allied Telesyn TS1000 ethernet driver" ts1000_eth_driver }
+	hardware
+	directory	devs/eth/powerpc/ts1000
+	script		ts1000_eth_drivers.cdl
+        description     "Ethernet driver specifics for Allied Telesyn TS1000 (MPC855T) based boards."
+}
+
+target ts1000 {
+        alias		{ "Allied Telesyn TS1000 board" ts1000_855 }
+	packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_MPC8xx
+                          CYGPKG_HAL_POWERPC_TS1000
+                          CYGPKG_HAL_QUICC 
+                          CYGPKG_DEVS_FLASH_POWERPC_TS1000
+                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                          CYGPKG_DEVS_ETH_POWERPC_FEC
+                          CYGPKG_DEVS_ETH_POWERPC_TS1000
+                          CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
+        }
+        description "
+            The ts1000 target provides the packages needed to run
+            eCos on a Allied Telesyn TS1000 (PPC855T) board."
+}
+
+# --------------------------------------------------------------------------
+
+package CYGPKG_DEVS_FLASH_UE250 {
+	alias 		{ "FLASH memory support for uE250" flash_uE250 }
+	directory	devs/flash/arm/uE250
+	script		flash_uE250.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the uE250 platform."
+}
+
+package CYGPKG_DEVS_ETH_ARM_XSCALE_UE250 {
+	alias 		{ "NMI uE250 PCI ethernet driver" devs_eth_arm_ue250 }
+	hardware
+	directory	devs/eth/arm/uE250
+	script		uE250_eth_drivers.cdl
+        description     "Ethernet driver for NMI uE250 via PCI card."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_UE250 {
+	alias		{ "NMI uEngine uE250" hal_arm_xscale_uE250 }
+	directory	hal/arm/xscale/uE250
+	script		hal_arm_xscale_uE250.cdl
+	hardware
+        description "
+        The UE250 HAL package provides the support needed to run
+        eCos on an NMI uEngine u250 board."
+}
+
+target uE250 {
+	alias { "NMI uEngine uE250 Board" ue250 }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_XSCALE_CORE
+                   CYGPKG_HAL_ARM_XSCALE_PXA2X0
+                   CYGPKG_HAL_ARM_XSCALE_UE250
+                   CYGPKG_IO_PCI
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+                   CYGPKG_DEVS_FLASH_STRATA
+                   CYGPKG_DEVS_FLASH_UE250
+                   CYGPKG_DEVS_ETH_NS_DP83902A
+                   CYGPKG_DEVS_ETH_ARM_XSCALE_UE250
+        }
+        description "
+        The uE250 target provides the packages needed to run
+        eCos on an NMI uEngine uE250 board."
+}
+
+# --------------------------------------------------------------------------
+
+package CYGPKG_DEVS_FLASH_PICASSO {
+	alias 		{ "FLASH memory support for picasso" flash_picasso }
+	directory	devs/flash/arm/picasso
+	script		flash_picasso.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the picasso platform."
+}
+
+package CYGPKG_DEVS_ETH_ARM_XSCALE_PICASSO {
+	alias 		{ "NMI picasso PCI ethernet driver" devs_eth_arm_picasso }
+	hardware
+	directory	devs/eth/arm/picasso
+	script		picasso_eth_drivers.cdl
+        description     "Ethernet driver for NMI picasso via PCI card."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_PICASSO {
+	alias		{ "NMI uEngine picasso" hal_arm_xscale_picasso }
+	directory	hal/arm/xscale/picasso
+	script		hal_arm_xscale_picasso.cdl
+	hardware
+        description "
+        The PICASSO HAL package provides the support needed to run
+        eCos on an NMI uEngine u250 board."
+}
+
+target picasso {
+	alias { "NMI uEngine picasso Board" }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_XSCALE_CORE
+                   CYGPKG_HAL_ARM_XSCALE_PXA2X0
+                   CYGPKG_HAL_ARM_XSCALE_PICASSO
+                   CYGPKG_IO_PCI
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+                   CYGPKG_DEVS_FLASH_STRATA
+                   CYGPKG_DEVS_FLASH_PICASSO
+                   CYGPKG_DEVS_ETH_NS_DP83902A
+                   CYGPKG_DEVS_ETH_ARM_XSCALE_PICASSO
+        }
+        description "
+        The picasso target provides the packages needed to run
+        eCos on an NMI uEngine picasso board."
+}
+
+# --------------------------------------------------------------------------
+
+package CYGPKG_HAL_POWERPC_ADDER {
+	alias		{ "A&M Adder PPC85x board" hal_powerpc_adder powerpc_adder_hal }
+	directory	hal/powerpc/adder
+	script		hal_powerpc_adder.cdl
+	hardware
+        description "
+            The ADDER HAL package provides the support needed to run
+            eCos on a A&M ADDER board equipped with a PowerPC processor."
+}
+
+package CYGPKG_DEVS_FLASH_POWERPC_ADDER {
+	alias 		{ "FLASH memory support for A&M Adder PowerPC/85x" flash_adder }
+	directory	devs/flash/powerpc/adder
+	script		flash_adder.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the A&M PowerPC/8xx ADDER platforms."
+}
+
+package CYGPKG_DEVS_ETH_POWERPC_ADDER {
+	alias 		{ "A&M Adder ethernet driver" adder_eth_driver }
+	hardware
+	directory	devs/eth/powerpc/adder
+	script		adder_eth_drivers.cdl
+        description     "Ethernet driver specifics for A&M Adder (MPC85x) based boards."
+}
+
+package CYGPKG_DEVS_ETH_POWERPC_ADDERII {
+        alias           { "A&M AdderII ethernet driver" adderII_eth_driver }
+        hardware
+        directory       devs/eth/powerpc/adderII
+        script          adderII_eth_drivers.cdl
+        description     "Ethernet driver specifics for A&M AdderII (MPC852T) based boards."
+}
+
+target adder {
+        alias		{ "A&M Adder PPC850 board" adder850 }
+	packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_MPC8xx
+                          CYGPKG_HAL_POWERPC_ADDER
+                          CYGPKG_HAL_QUICC 
+                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2
+                          CYGPKG_DEVS_ETH_POWERPC_QUICC
+                          CYGPKG_DEVS_ETH_POWERPC_ADDER
+                          CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
+        }
+        enable { CYGHWR_HAL_POWERPC_ADDER_I }
+        description "
+            The adder target provides the packages needed to run
+            eCos on a A&M Adder PPC850 board."
+}
+
+target adderII {
+        alias		{ "A&M Adder PPC852T board" adder852T }
+	packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_MPC8xx
+                          CYGPKG_HAL_POWERPC_ADDER
+                          CYGPKG_HAL_QUICC 
+                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2
+                          CYGPKG_DEVS_ETH_POWERPC_FEC
+                          CYGPKG_DEVS_ETH_POWERPC_ADDERII
+                          CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
+        }
+        enable { CYGHWR_HAL_POWERPC_ADDER_II }
+        description "
+            The adderII target provides the packages needed to run
+            eCos on a A&M Adder PPC852T board."
+}
+
+# --------------------------------------------------------------------------
+
+package CYGPKG_HAL_POWERPC_RATTLER {
+	alias		{ "A&M Rattler MPC8250 board" hal_powerpc_rattler powerpc_rattler_hal }
+	directory	hal/powerpc/rattler
+	script		hal_powerpc_rattler.cdl
+	hardware
+        description "
+            The RATTLER HAL package provides the support needed to run
+            eCos on a A&M RATTLER board equipped with a PowerPC processor."
+}
+
+package CYGPKG_DEVS_ETH_POWERPC_RATTLER {
+        alias           { "A&M Rattler ethernet driver" rattler_eth_driver }
+        hardware
+        directory       devs/eth/powerpc/rattler
+        script          rattler_eth_drivers.cdl
+        description     "Ethernet driver specifics for A&M Rattler (MPC8250) based boards."
+}
+
+package CYGPKG_DEVS_FLASH_POWERPC_RATTLER {
+	alias 		{ "FLASH memory support for A&M Rattler (MPC8250)" flash_rattler }
+	directory	devs/flash/powerpc/rattler
+	script		flash_rattler.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the A&M Rattler (MPC8250) platforms."
+}
+
+target rattler {
+        alias		{ "A&M Rattler (8250) board" }
+	packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_MPC8XXX
+                          CYGPKG_HAL_POWERPC_RATTLER
+                          CYGPKG_DEVS_FLASH_POWERPC_RATTLER
+                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                          CYGPKG_DEVS_ETH_POWERPC_FCC
+                          CYGPKG_DEVS_ETH_POWERPC_RATTLER
+                          CYGPKG_DEVS_ETH_PHY
+                          CYGPKG_IO_SERIAL_POWERPC_MPC8XXX
+        }
+        description "
+            The rattler target provides the packages needed to run
+            eCos on an Analogue & Micro Rattler (MPC8250) board."
+}
+
+##-------------------------------------------------------------------------------------------
+## TAMS MOAB (PowerPC 405GPr) packages
+##
+package CYGPKG_HAL_POWERPC_MOAB {
+	alias		{ "TAMS PowerPC 405GP board" hal_powerpc_moab }
+	directory	hal/powerpc/moab
+	script		hal_powerpc_moab.cdl
+	hardware
+        description "
+            The MOAB HAL package provides the support needed to run
+            eCos on a TAMS PowerPC 405GP board."
+}
+
+package CYGPKG_DEVS_FLASH_POWERPC_MOAB {
+	alias 		{ "FLASH memory support for MOAB" flash_moab }
+	directory	devs/flash/powerpc/moab
+	script		flash_moab.cdl
+	hardware
+        description "
+           This package contains hardware support for both the boot FLASH 
+           and NAND (main) memory on the MOAB platform."
+}
+
+package CYGPKG_DEVS_ETH_POWERPC_MOAB {
+        alias           { "TAMS PowerPC 405GP ethernet support" moab_eth_driver }
+        hardware
+        directory       devs/eth/powerpc/moab
+        script          moab_eth_drivers.cdl
+        description     "Ethernet driver specifics for TAMS MOAB (PPC405GP) based boards."
+}
+
+package CYGPKG_DEVICES_WALLCLOCK_POWERPC_MOAB {
+         alias          { "MOAB RTC device" devs_wallclock_moab_ds1307 moab_rtc }
+         hardware
+         directory      devs/wallclock/powerpc/moab
+         script         moab_wallclock_drivers.cdl
+         description    "
+            RTC driver for MOAB (PowerPC PPC405GPr) using a
+            Dallas DS1307 RTC."
+}
+
+target moab {
+	alias		{ "TAMS PowerPC 405GPr" moab405GPr }
+	packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_PPC40x
+                          CYGPKG_HAL_POWERPC_MOAB
+                          CYGPKG_DEVS_FLASH_POWERPC_MOAB
+                          CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX
+                          CYGPKG_DEVS_FLASH_TOSHIBA_TC58XXX
+                          CYGPKG_DEVS_ETH_POWERPC_MOAB
+                          CYGPKG_DEVS_ETH_POWERPC_PPC405
+                          CYGPKG_DEVS_ETH_NS_DP83816
+                          CYGPKG_DEVS_ETH_PHY
+                          CYGPKG_IO_PCI
+                          CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1307
+                          CYGPKG_DEVICES_WALLCLOCK_POWERPC_MOAB
+                          CYGPKG_IO_SERIAL_GENERIC_16X5X
+                          CYGPKG_IO_SERIAL_POWERPC_PPC405
+        }
+        description "
+            The moab target provides the packages needed to run
+            eCos on the TAMS MOAB (405GPr) board."
+}
+##-------------------------------------------------------------------------------------------
+
+# --------------------------------------------------------------------------
+
+# Realtek 8139 (PCI) Ethernet driver
+package CYGPKG_DEVS_ETH_RLTK_8139 {
+	alias 		{ "Realtek 8139 ethernet driver" rltk8139_eth_driver }
+	hardware
+	directory	devs/eth/rltk/8139
+	script		rltk_8139_eth_drivers.cdl
+        description     "Ethernet driver for Realtek 8139 (PCI) card."
+}
+
+package CYGPKG_DEVS_ETH_I386_PC_RLTK8139 {
+	alias 		{ "Intel PC with Realtek 8139 ethernet driver" pc_rltk8139_eth_driver }
+	hardware
+	directory	devs/eth/i386/pc/rltk8139
+	script		i386_pc_rltk8139_eth_drivers.cdl
+        description     "Intel PC using Realtek 8139 (PCI) card."
+}
+
+package CYGPKG_DEVS_ETH_SH_DREAMCAST_RLTK8139 {
+	alias 		{ "SEGA Dreamcast with BroadBandAdapter driver" dreamcast_rltk8139_eth_driver }
+	hardware
+	directory	devs/eth/sh/dreamcast
+	script		sh_dreamcast_rltk8139_eth_drivers.cdl
+        description     "SEGA Dreamcast with BroadBandAdapter."
+}
+
+target pc_rltk8139 {
+        alias		{ "i386 PC target with RTL8139 ethernet" }
+	packages        { CYGPKG_HAL_I386
+                          CYGPKG_HAL_I386_GENERIC
+                          CYGPKG_HAL_I386_PC
+                          CYGPKG_HAL_I386_PCMB
+			  CYGPKG_IO_PCI
+                          CYGPKG_IO_SERIAL_GENERIC_16X5X
+	                  CYGPKG_IO_SERIAL_I386_PC
+			  CYGPKG_DEVS_ETH_RLTK_8139
+			  CYGPKG_DEVS_ETH_I386_PC_RLTK8139
+                          CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS12887
+                          CYGPKG_DEVICES_WALLCLOCK_I386_PC
+        }
+        description "
+    	    The pc_rltk8139 target provides the packages needed to run eCos binaries 
+            on a standard i386 PC motherboard, using a Realtek 8139 network card."
+}
+
+# --------------------------------------------------------------------------
+
+package CYGPKG_HAL_ARM_GPS4020 {
+	alias		{ "GPS4020" hal_gps4020 }
+	directory	hal/arm/gps4020
+	script		hal_arm_gps4020.cdl
+	hardware
+        description "
+            The GPS4020 HAL package provides the support needed to run
+            eCos on a GPS 4020 board using the Firefly MF1 (ARM) processor."
+}
+
+package CYGPKG_DEVS_FLASH_GPS4020 {
+	alias 		{ "FLASH memory support for GPS4020" flash_gps4020 }
+	directory	devs/flash/arm/gps4020
+	script		flash_gps4020.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the GPS4020 platform."
+}
+
+package CYGPKG_IO_SERIAL_ARM_GPS4020 {
+    alias             { "GPS4020 serial device drivers"
+                        devs_serial_arm_gps4020 gps4020_serial_driver }
+    hardware
+    directory	      devs/serial/arm/gps4020
+    script	      ser_arm_gps4020.cdl	
+    description       "GPS4020 serial device drivers"
+}
+
+target gps4020 {
+        alias		{ "GPS 4020" gps_4020 gps}
+	packages        { CYGPKG_HAL_ARM
+                          CYGPKG_HAL_ARM_GPS4020
+                          CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX
+                          CYGPKG_DEVS_FLASH_GPS4020
+                          CYGPKG_IO_SERIAL_ARM_GPS4020
+        }
+        description "
+            The gps4020 target provides the packages needed to run
+            eCos on a GPS-4020 board."
+}
+
+# --------------------------------------------------------------------------
+
+package CYGPKG_VNC_SERVER {
+    alias       { "VNC server" vnc_server }
+    directory   net/vnc_server
+    script      vnc-server.cdl
+    description "VNC server."
+}
+
+# --------------------------------------------------------------------------
+
+package CYGPKG_DEVS_DISK_V85X_EDB_V850 {
+    alias           { "Elatec v850 development board disk driver" edb_v850_disk }
+    directory       devs/disk/v85x/edb_v850
+    script          v85x_edb_v850_disk.cdl
+    hardware
+    description     "Disk driver for the Elatec v850 development board." 
+}
+
+package CYGPKG_DEVS_DISK_ECOSYNTH {
+    alias           { "Synthetic target disk driver" ecosynthdisk ecosynth_disk_driver }
+    directory       devs/disk/synth
+    script          synthdisk.cdl
+    hardware
+    description     "Disk driver for the synthetic target."
+}
+
+package CYGPKG_DEVS_DISK_IDE {
+    alias           { "Generic IDE disk driver" ide_disk }
+    directory       devs/disk/ide
+    script          ide_disk.cdl
+    description     "Disk driver for generic IDE interface." 
+}
+
+package CYGPKG_DEVS_DISK_MMC {
+    alias      { "Disk driver for MMC cards" mmcdisk mmc_disk_driver }
+    directory  devs/disk/generic/mmc
+    script     devs_disk_mmc.cdl
+    hardware
+    description "Disk driver for MMC cards"
+}
+
+package CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI {
+    alias         { "MMC/SD disk over Freescale DSPI" }
+    hardware
+    directory     devs/disk/spi/freescale/dspi/mmc
+    script        disk_mmc_freescale_dspi.cdl
+    description   "
+        This package provides a driver for MMC/SD disk attached to a
+        Freescale DSPI interface."
+}
+
+package CYGPKG_IO_DISK {
+    alias           { "Disk device drivers" disk io_disk }
+    directory       io/disk
+    script          io_disk.cdl
+    description "
+        This package contains drivers for basic I/O services on
+        disk devices."
+}
+
+package CYGPKG_BLOCK_LIB {
+    alias       { "Block cache and access library" blib block_lib }
+    directory   services/blib
+    script      blib.cdl
+    description "
+        This package contains the block cache and access library."
+}
+
+package CYGPKG_FS_FAT {
+    alias       { "FAT Filesystem" fatfs fat_fs fs_fat }
+    directory   fs/fat
+    script      fatfs.cdl
+    description "
+        This package contains a FAT filesystem implementation."
+}
+
+
+# --------------------------------------------------------------------------
+
+package CYGPKG_IO_FRAMEBUF {
+        alias	   { "Frame buffer support" framebuf framebuffer io_framebuf framebuf_io }
+        directory  io/framebuf
+        script     framebuf.cdl
+        description "
+          The generic frame buffer package provides an API for accessing
+          frame buffer devices. It also provides support for writing
+          the corresponding the device drivers."
+}
+
+package CYGPKG_DEVS_FRAMEBUF_SYNTH {
+    alias		{ "Synthetic target framebuffer device driver" devs_framebuf_synth synth_framebuf_driver }
+    hardware
+    directory		devs/framebuf/synth
+    script		framebuf_synth.cdl
+    
+    description "
+        This package provides a framebuffer device driver for the
+        synthetic target."
+}
+
+# --------------------------------------------------------------------------
+
+package CYGPKG_NET_LWIP {
+	alias		{"lwIP networking stack" lwip}
+	directory	net/lwip_tcpip
+	script		cdl/lwip_net.cdl
+	description	"Lightweight TCP/IP stack: lwIP"
+}
+
+package CYGPKG_ATHTTPD {
+	alias 		{ "ATHTTP server" athttpd }
+	directory	net/athttpd
+	script		httpd.cdl
+    description "Another Tiny HTTP server."
+}
+
+
+# ==========================================================================
+# Cortex-M architecture support
+
+package CYGPKG_HAL_CORTEXM {
+	alias		{ "Cortex-M common HAL" hal_cortexm cortexm_hal cortexm_arch_hal }
+	directory	hal/cortexm/arch
+	script		hal_cortexm.cdl
+	hardware
+	description "
+        The CortexM architecture HAL package provides generic support for the ARM
+        Cortex-M processor architecture. It is also necessary to select
+        variant and platform HAL packages."
+}
+
+package CYGPKG_HAL_CORTEXM_LM3S {
+    alias       { "Stellaris Cortex M3 variant HAL" hal_cortexm_lm3s }
+    directory   hal/cortexm/lm3s/var
+    script      hal_cortexm_lm3s.cdl
+    hardware
+    description "
+        The Stellaris Cortex M3 HAL package provides the support needed
+        to run eCos on targets based on the Stellaris Cortex M3 family
+        of microcontrollers."
+}
+
+package CYGPKG_HAL_CORTEXM_LM3S8XX {
+    alias       { "Stellaris 800 Series variant HAL" hal_cortexm_lm3s8xx }
+    directory   hal/cortexm/lm3s/lm3s8xx/
+    script      hal_cortexm_lm3s8xx.cdl
+    hardware
+    description "
+        The Stellaris Cortex M3 800 Series HAL package provides the
+        support needed to run eCos on targets based on the Stellaris
+        Luminary Micro 800 Series family of microcontrollers."
+}
+
+package CYGPKG_HAL_CORTEXM_EK_LM3S811 {
+    alias       { "Stellaris EK-LM3S811 HAL" hal_cortexm_ek_lm3s811 }
+    directory   hal/cortexm/lm3s/ek_lm3s811
+    script      hal_cortexm_ek_lm3s811.cdl
+    hardware
+    description "
+        The ek-lm3s811 HAL package provides the support needed to run
+        eCos on the Stellaris EK-LM3S811 board from Luminary Micro."
+}
+
+package CYGPKG_HAL_CORTEXM_LPC17XX {
+        alias           { "NXP LPC17XX variant HAL" hal_cortexm_lpc17xx }
+        directory       hal/cortexm/lpc17xx/var
+        script          hal_cortexm_lpc17xx.cdl
+        hardware
+        description "
+            The LPC 17XX HAL package provides the support needed to
+            run eCos on targets based on the NXP LPC17XX family of
+            microcontrollers."
+}
+
+package CYGPKG_HAL_CORTEXM_LPC17XX_LPC1766STK {
+        alias           { "Olimex LPC-1766-STK HAL" hal_cortexm_lpc1766stk }
+        directory       hal/cortexm/lpc17xx/lpc1766stk
+        script          hal_cortexm_lpc17xx_lpc1766stk.cdl
+        hardware
+        description "
+            The lpc1766stk HAL package provides the support needed to run
+            eCos on the Olimex LPC-1766-STK board."
+}
+
+package CYGPKG_HAL_CORTEXM_STM32 {
+	alias		{ "ST STM32 variant HAL" hal_cortexm_stm32 }
+	directory	hal/cortexm/stm32/var
+	script		hal_cortexm_stm32.cdl
+	hardware
+        description "
+        The STM32 HAL package provides the support needed to run
+        eCos and RedBoot on targets based on the ST STM32
+        family of microcontrollers."
+}
+
+package CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL {
+	alias		{ "ST STM3210E EVAL HAL" hal_cortexm_stm3210e_eval }
+	directory	hal/cortexm/stm32/stm3210e_eval
+	script		hal_cortexm_stm32_stm3210e_eval.cdl
+	hardware
+        description "
+        The stm3210e_eval HAL package provides the support needed to run
+        eCos on the ST STM3210E EVAL board."
+}
+
+package CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL {
+	alias		{ "ST STM32x0G-EVAL HAL" hal_cortexm_stm32x0g_eval }
+	directory	hal/cortexm/stm32/stm32x0g_eval
+	script		hal_cortexm_stm32_stm32x0g_eval.cdl
+	hardware
+        description "
+        The stm32x0g_eval HAL package provides the support needed to run
+        eCos on the ST STM3220G-EVAL and STM3240G-EVAL boards."
+}
+
+package CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY {
+        alias		{ "STMicroelectronics STM32F4-Discovery HAL" hal_cortexm_stm32f4discovery }
+        directory	hal/cortexm/stm32/stm32f4discovery
+        script		hal_cortexm_stm32_stm32f4discovery.cdl
+        hardware
+        description "
+            The STM32F4-Discovery HAL package provides the platform support needed to run
+            eCos on the STMicroelectronics STM32F4-Discovery board."
+}
+
+package CYGPKG_IO_SERIAL_CORTEXM_STM32 {
+        alias           { "ST STM32 serial device drivers"
+                          devs_serial_cortexm_stm32 stm32_serial_driver }
+        hardware
+        directory	devs/serial/cortexm/stm32
+        script	        ser_cortexm_stm32.cdl	
+        description     "ST STM32 serial device driver"
+}
+
+package CYGPKG_DEVS_FLASH_STM32 {
+        alias           { "Internal FLASH memory support for ST STM32" flash_stm32 }
+        directory       devs/flash/cortexm/stm32
+        script          flash_stm32.cdl
+        hardware
+        description "
+        This package contains hardware support for the internal FLASH memory
+        on the ST STM32 devices."
+}
+
+package CYGPKG_DEVS_SPI_CORTEXM_STM32 {
+    alias         { "STM32 SPI driver" }
+    hardware
+    directory     devs/spi/cortexm/stm32
+    script        spi_stm32.cdl
+    description   "This package provides a driver for the SPI interfaces found on 
+                  the ST STM32 microcontroller family."
+}
+
+package CYGPKG_DEVS_WALLCLOCK_STM32 {
+        alias           { "ST STM32 RTC wallclock support" wallclock_stm32 }
+        directory       devs/wallclock/cortexm/stm32
+        script          wallclock_stm32.cdl
+        hardware
+        description "
+        Wallclock support for on-chip RTC on STM32 devices.driver for the
+        STM32 controller and compatibles"
+}
+
+package CYGPKG_DEVS_ADC_CORTEXM_STM32 {
+    alias         { "STM32 ADC driver" adc_stm32 }
+    hardware
+    directory     devs/adc/cortexm/stm32
+    script        adc_stm32.cdl
+    description "
+    This package provides a driver for the ADC interfaces found on the
+    ST STM32 microcontroller family."
+}
+
+package CYGPKG_DEVS_USB_CORTEXM_STM32 {
+        alias           { "ST STM32 USB slave support" usb_stm32 }
+        directory       devs/usb/cortexm/stm32
+        script          usb_stm32.cdl
+        hardware
+        description     "USB slave support for STM32 devices."
+}
+
+package CYGPKG_DEVS_ETH_CORTEXM_STM32 {
+	alias 		{ "STM32 ethernet driver" stm32_eth_driver }
+	hardware
+	directory	devs/eth/cortexm/stm32
+	script		stm32_eth.cdl
+        description     "
+    This package provides a driver for the Ethernet interfaces found on the
+    ST STM32 microcontroller family."
+}
+
+target stm3210e_eval {
+        alias { "ST STM3210E EVAL board" stm3210e }
+        packages { CYGPKG_HAL_CORTEXM
+                   CYGPKG_HAL_CORTEXM_STM32
+                   CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL
+                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2
+                   CYGPKG_DEVS_FLASH_STM32
+                   CYGPKG_DEVS_FLASH_SPI_M25PXX
+                   CYGPKG_IO_SERIAL_CORTEXM_STM32
+                   CYGPKG_DEVS_WALLCLOCK_STM32
+                   CYGPKG_IO_SPI
+                   CYGPKG_DEVS_SPI_CORTEXM_STM32
+                   CYGPKG_DEVS_ADC_CORTEXM_STM32
+                   CYGPKG_DEVS_NAND_ST_NANDXXXX3A
+                   CYGPKG_IO_USB
+                   CYGPKG_IO_USB_SLAVE
+                   CYGPKG_DEVS_USB_CORTEXM_STM32
+                 }
+        description "The stm3210e_eval target provides the packages needed
+        to run eCos on the STM3210E EVAL board."
+}
+
+# ==========================================================================
+# NAND packages
+
+package CYGPKG_IO_NAND {
+    alias       { "NAND flash memory support" nand io_nand }
+    directory   io/nand
+    script      nand.cdl
+    description     "
+        This package provides the NAND flash access library.
+		Further platform-specific package(s) are required to implement
+		support for the specific devices present."
+}
+
+package CYGPKG_DEVS_NAND_SAMSUNG_K9 {
+    alias       { "Samsung K9 NAND chip family support" nand_samsung_k9 }
+    directory   devs/nand/samsung_k9
+    script      k9fxx08x0a.cdl
+    description     "
+		This package provides support for the Samsung K9Fxx08x0A family of NAND 
+        flash devices."
+}
+
+package CYGPKG_DEVS_NAND_SYNTH {
+	alias 		{ "Synthetic NAND device" nand_synth }
+	directory	devs/nand/synth
+	script		nand_synth.cdl
+	description "
+		This package provides a synthetic NAND device, for testing purposes."
+}
+
+package CYGPKG_DEVS_NAND_ST_NANDXXXX3A {
+    alias       { "ST Microelectronics NANDxxxx3A chip family support" nand_st_nandxxxx3a }
+    directory   devs/nand/st/nandxxxx3a
+    script      nandxxxx3a.cdl
+    description     "
+        This package provides support for the ST Microelectronics family of
+        NANDxxxx3A flash devices."
+}
+
+package CYGPKG_DEVS_NAND_MICRON_MT29F {
+    alias       { "Micron MT29F NAND chip family support" nand_micron_mt29f }
+    directory   devs/nand/micron_mt29
+    script      mt29f.cdl
+    hardware
+    description     "
+		This package provides support for the Micron MT29F family of NAND 
+        flash devices."
+}
+
+package CYGPKG_DEVS_NAND_ARM_AT91SAM9 {
+    alias       { "Common NAND support for the AT91SAM926X family" nand_at91sam926x }
+    directory   devs/nand/arm/at91sam9
+    script      devs_nand_arm_at91sam9.cdl
+    hardware
+    description "Common support definitions and code for the NAND support
+        hardware found on the Atmel AT91SAM926X chip family."
+}
+
+target stm3220g_eval {
+        alias { "ST STM3220G EVAL board" stm3220g }
+        packages { CYGPKG_HAL_CORTEXM
+                   CYGPKG_HAL_CORTEXM_STM32
+                   CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL
+                   CYGPKG_DEVS_FLASH_STM32
+                   CYGPKG_IO_SERIAL_CORTEXM_STM32
+                   CYGPKG_IO_SPI
+                   CYGPKG_DEVS_SPI_CORTEXM_STM32
+                   CYGPKG_DEVS_ETH_PHY
+                   CYGPKG_DEVS_ETH_CORTEXM_STM32
+                 }
+        set_value CYGHWR_HAL_CORTEXM_STM32_FAMILY "F2"
+        set_value CYGHWR_HAL_CORTEXM_STM32_F2 "F207IG"
+        description "The stm3220g_eval target provides the packages needed
+        to run eCos on the STM3220G EVAL board."
+}
+
+target stm3240g_eval {
+        alias { "ST STM3240G EVAL board" stm3240g }
+        packages { CYGPKG_HAL_CORTEXM
+                   CYGPKG_HAL_CORTEXM_STM32
+                   CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL
+                   CYGPKG_DEVS_FLASH_STM32
+                   CYGPKG_IO_SERIAL_CORTEXM_STM32
+                   CYGPKG_IO_SPI
+                   CYGPKG_DEVS_SPI_CORTEXM_STM32
+                   CYGPKG_DEVS_ETH_PHY
+                   CYGPKG_DEVS_ETH_CORTEXM_STM32
+                 }
+        set_value CYGHWR_HAL_CORTEXM_STM32_FAMILY "F4"
+        set_value CYGHWR_HAL_CORTEXM_STM32_F4 "F407IG"
+        description "The stm3240g_eval target provides the packages needed
+        to run eCos on the STM3240G-EVAL board."
+}
+
+target stm32f4discovery {
+        alias { "STMicroelectronics STM32F4-Discovery board" }
+        packages {
+                CYGPKG_HAL_CORTEXM
+                CYGPKG_HAL_CORTEXM_STM32
+                CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY
+                CYGPKG_DEVS_FLASH_STM32
+                CYGPKG_IO_SERIAL_CORTEXM_STM32
+        }
+        description "The stm32f4discovery target provides the packages needed
+        to run eCos on the STMicroelectronics STM32F4-Discovery board."
+}
+
+target ek-lm3s811 {
+        alias      { "Stellaris EK-LM3S811 board" }
+        packages   { CYGPKG_HAL_CORTEXM
+                     CYGPKG_HAL_CORTEXM_LM3S
+                     CYGPKG_HAL_CORTEXM_LM3S8XX
+                     CYGPKG_HAL_CORTEXM_EK_LM3S811
+                     CYGPKG_DEVS_I2C_CORTEXM_LM3S
+                     CYGPKG_DEVS_ADC_CORTEXM_LM3S
+                     CYGPKG_IO_I2C
+                    }
+        description "
+            The ek-lm3s811 target provides the packages needed to run eCos
+            on the Stellaris EK-LM3S811 board from Luminary Micro."
+}
+
+target lpc1766stk {
+        alias      { "Olimex LPC-1766-STK" }
+        packages   { CYGPKG_HAL_CORTEXM
+                     CYGPKG_HAL_CORTEXM_LPC17XX
+                     CYGPKG_HAL_CORTEXM_LPC17XX_LPC1766STK
+                     CYGPKG_DEVICES_WALLCLOCK_ARM_LPC2XXX
+                     CYGPKG_IO_SERIAL_GENERIC_16X5X
+                     CYGPKG_IO_SERIAL_ARM_LPC24XX
+                     CYGPKG_DEVS_ETH_PHY
+                     CYGPKG_DEVS_ETH_ARM_LPC2XXX
+                    }
+        description "
+            The lpc1766stk target provides the packages needed
+            to run eCos on the Olimex LPC-1766-STK board."
+}
+
+package CYGPKG_HAL_FREESCALE_EDMA {
+    alias         { "Freescale eDMA driver" }
+    hardware
+    directory     hal/misc/freescale/edma
+    script        hal_freescale_edma.cdl
+    description   "
+        This package provides a library for the Freescale eDMA (Enhanced DMA)
+        controller."
+}
+
+package CYGPKG_HAL_CORTEXM_KINETIS {
+	alias		{ "Freescale Kinetis variant HAL" hal_cortexm_kinetis }
+	directory	hal/cortexm/kinetis/var
+	script		hal_cortexm_kinetis.cdl
+	hardware
+        description "
+        The Kinetis HAL package provides the support needed to run
+        eCos on targets based on the Freescale Kinetis
+        family of microcontrollers."
+}
+
+package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60N512 {
+	alias		{ "Freescale TWR-K60N512 HAL" hal_cortexm_twr_k60n512 }
+	directory	hal/cortexm/kinetis/twr_k60n512
+	script		hal_cortexm_kinetis_twr_k60n512.cdl
+	hardware
+        description "
+        The TWR-K60N512 HAL package provides the support needed to run
+        eCos on the Freescale Tower development system."
+}
+
+package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K40X256 {
+	alias		{ "Freescale TWR-K40X256 HAL" hal_cortexm_twr_k40x256 }
+	directory	hal/cortexm/kinetis/twr_k40x256
+	script		hal_cortexm_kinetis_twr_k40x256.cdl
+	hardware
+        description "
+        The TWR-K40X256 HAL package provides the support needed to run
+        eCos on the Freescale Tower development system."
+}
+
+package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60N512_FXM {
+	alias		{ "Freescale TWR-K60N512-FXM HAL" hal_cortexm_twr_k60n512_fxm }
+	directory	hal/cortexm/kinetis/twr_k60n512_fxm
+	script		hal_cortexm_kinetis_twr_k60n512_fxm.cdl
+	hardware
+        description "
+        The TWR-K60N512-FXM HAL package provides the support needed to run
+        eCos on the Freescale Tower development system equpped with TWR-FXM module."
+}
+
+package CYGPKG_HAL_CORTEXM_KINETIS_KWIKSTIK {
+	alias		{ "Freescale KwikStik HAL" hal_cortexm_kwikstik }
+	directory	hal/cortexm/kinetis/kwikstik
+	script		hal_cortexm_kinetis_kwikstik.cdl
+	hardware
+        description "
+        The KwikStik HAL package provides the support needed to run
+        eCos on the Freescale KwikStik development board."
+}
+
+package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K70F120M {
+	alias		{ "Freescale TWR-K70F120M HAL" hal_cortexm_twr_k70f120m }
+	directory	hal/cortexm/kinetis/twr_k70f120m
+	script		hal_cortexm_kinetis_twr_k70f120m.cdl
+	hardware
+        description "
+        The TWR-K70F120M HAL package provides the support needed to run
+        eCos on the Freescale Tower development system."
+}
+
+package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60F120M {
+	alias		{ "Freescale TWR-K60F120M HAL" hal_cortexm_twr_k60f120m }
+	directory	hal/cortexm/kinetis/twr_k60f120m
+	script		hal_cortexm_kinetis_twr_k60f120m.cdl
+	hardware
+        description "
+        The TWR-K60F120M HAL package provides the support needed to run
+        eCos on the Freescale Tower development system."
+}
+
+target freescale_twr_k60n512 {
+        alias { "Freescale Kinetis TWR-K60N512" twr_k60n512 }
+        packages { CYGPKG_HAL_CORTEXM
+                   CYGPKG_HAL_CORTEXM_KINETIS
+                   CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60N512
+                   CYGPKG_HAL_FREESCALE_EDMA
+                   CYGPKG_IO_SERIAL_FREESCALE_UART_HDR
+                   CYGPKG_IO_SERIAL_FREESCALE_UART
+                   CYGPKG_DEVICES_WALLCLOCK_KINETIS_RTC
+                   CYGPKG_DEVS_ETH_PHY
+                   CYGPKG_DEVS_ETH_FREESCALE_ENET
+                   CYGPKG_IO_SPI
+                   CYGPKG_DEVS_SPI_FREESCALE_DSPI
+                   CYGPKG_IO_I2C
+                   CYGPKG_DEVS_I2C_FREESCALE_I2C
+                   CYGPKG_DEVS_DISK_MMC
+                   CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+                   CYGPKG_DEVS_FLASH_KINETIS
+                 }
+        description "The freescale_twr_k60n512 target provides the packages needed
+        to run eCos on the Freescale TWR-K60N512 development system."
+}
+
+target freescale_twr_k40x256 {
+        alias { "Freescale Kinetis TWR-K40X256" twr_k40x256 }
+        packages { CYGPKG_HAL_CORTEXM
+                   CYGPKG_HAL_CORTEXM_KINETIS
+                   CYGPKG_HAL_CORTEXM_KINETIS_TWR_K40X256
+                   CYGPKG_HAL_FREESCALE_EDMA
+                   CYGPKG_IO_SERIAL_FREESCALE_UART_HDR
+                   CYGPKG_IO_SERIAL_FREESCALE_UART
+                   CYGPKG_DEVICES_WALLCLOCK_KINETIS_RTC
+                   CYGPKG_IO_SPI
+                   CYGPKG_DEVS_SPI_FREESCALE_DSPI
+                   CYGPKG_IO_I2C
+                   CYGPKG_DEVS_I2C_FREESCALE_I2C
+                   CYGPKG_DEVS_DISK_MMC
+                   CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+                   CYGPKG_DEVS_FLASH_KINETIS
+                 }
+        description "The freescale_twr_k40x256 target provides the packages needed
+        to run eCos on the Freescale TWR-K40X256 development system."
+}
+
+target freescale_kwikstik {
+        alias { "Freescale Kinetis KwikStik" kwikstik }
+        packages { CYGPKG_HAL_CORTEXM
+                   CYGPKG_HAL_CORTEXM_KINETIS
+                   CYGPKG_HAL_CORTEXM_KINETIS_KWIKSTIK
+                   CYGPKG_IO_SERIAL_FREESCALE_UART_HDR
+                   CYGPKG_IO_SERIAL_FREESCALE_UART
+                   CYGPKG_DEVICES_WALLCLOCK_KINETIS_RTC
+                   CYGPKG_DEVS_FLASH_KINETIS
+                   CYGPKG_IO_I2C
+                   CYGPKG_DEVS_I2C_FREESCALE_I2C
+                 }
+        description "The freescale_kwikstik target provides the packages needed
+        to run eCos on the Freescale KwikStik development board."
+}
+
+target freescale_twr_k60n512_fxm {
+        alias { "Freescale Kinetis TWR-K60N512-FXM" twr_k60n512_fxm }
+        packages { CYGPKG_HAL_CORTEXM
+                   CYGPKG_HAL_CORTEXM_KINETIS
+                   CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60N512_FXM
+                   CYGPKG_HAL_FREESCALE_EDMA
+                   CYGPKG_IO_SERIAL_FREESCALE_UART_HDR
+                   CYGPKG_IO_SERIAL_FREESCALE_UART
+                   CYGPKG_DEVICES_WALLCLOCK_KINETIS_RTC
+                   CYGPKG_DEVS_ETH_PHY
+                   CYGPKG_DEVS_ETH_FREESCALE_ENET
+                   CYGPKG_DEVS_RAM_MICRON_CELLULARRAM
+                   CYGPKG_IO_SPI
+                   CYGPKG_DEVS_SPI_FREESCALE_DSPI
+                   CYGPKG_IO_I2C
+                   CYGPKG_DEVS_I2C_FREESCALE_I2C
+                   CYGPKG_DEVS_DISK_MMC
+                   CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+                   CYGPKG_DEVS_FLASH_SPI_SST25XX
+                   CYGPKG_DEVS_FLASH_SST25XX_FREESCALE_DSPI
+                 }
+        description "
+            The freescale_twr_k60n512_fxm target provides the packages needed
+            to run eCos on the Freescale TWR-K60N512 development system
+            equipped with TWR-FXM external memory module."
+}
+
+target freescale_twr_k70f120m {
+        alias { "Freescale Kinetis TWR-K70F120M" twr_k70f120m }
+        packages { CYGPKG_HAL_CORTEXM
+                   CYGPKG_HAL_CORTEXM_KINETIS
+                   CYGPKG_HAL_CORTEXM_KINETIS_TWR_K70F120M
+                   CYGPKG_HAL_FREESCALE_EDMA
+                   CYGPKG_IO_SERIAL_FREESCALE_UART_HDR
+                   CYGPKG_IO_SERIAL_FREESCALE_UART
+                   CYGPKG_DEVICES_WALLCLOCK_KINETIS_RTC
+                   CYGPKG_DEVS_ETH_PHY
+                   CYGPKG_DEVS_ETH_FREESCALE_ENET
+                   CYGPKG_IO_SPI
+                   CYGPKG_DEVS_SPI_FREESCALE_DSPI
+                   CYGPKG_IO_I2C
+                   CYGPKG_DEVS_I2C_FREESCALE_I2C
+                   CYGPKG_DEVS_DISK_MMC
+                   CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+                   CYGPKG_DEVS_FLASH_KINETIS
+                 }
+        description "The freescale_twr_k70f120m target provides the packages needed
+        to run eCos on the Freescale TWR-k70f120m development system."
+}
+
+target freescale_twr_k60f120m {
+        alias { "Freescale Kinetis TWR-K60F120M" twr_k60f120m }
+        packages { CYGPKG_HAL_CORTEXM
+                   CYGPKG_HAL_CORTEXM_KINETIS
+                   CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60F120M
+                   CYGPKG_HAL_FREESCALE_EDMA
+                   CYGPKG_IO_SERIAL_FREESCALE_UART_HDR
+                   CYGPKG_IO_SERIAL_FREESCALE_UART
+                   CYGPKG_DEVICES_WALLCLOCK_KINETIS_RTC
+                   CYGPKG_DEVS_ETH_PHY
+                   CYGPKG_DEVS_ETH_FREESCALE_ENET
+                   CYGPKG_IO_SPI
+                   CYGPKG_DEVS_SPI_FREESCALE_DSPI
+                   CYGPKG_IO_I2C
+                   CYGPKG_DEVS_I2C_FREESCALE_I2C
+                   CYGPKG_DEVS_DISK_MMC
+                   CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+                   CYGPKG_DEVS_FLASH_KINETIS
+                 }
+        description "The freescale_twr_k60f120m target provides the packages needed
+        to run eCos on the Freescale TWR-k60f120m development system."
+}
+
+package CYGPKG_HAL_CORTEXM_A2FXXX {
+    alias       { "Cortex-M3/Actel Smartfusion A2Fxxx variant HAL"  hal_cortexm_a2fxxx }
+    directory   hal/cortexm/a2fxxx/var
+    script      hal_cortexm_a2fxxx.cdl
+    hardware
+    description "
+        The Actel A2Fxxx HAL package provides the support needed to run
+        eCos and RedBoot on targets based on the Actel A2Fxxx
+        family of microcontrollers."
+}
+
+package CYGPKG_HAL_CORTEXM_A2F200_EVAL {
+    alias       { "Actel A2F200 EVAL HAL" hal_cortexm_a2f200_eval }
+    directory   hal/cortexm/a2fxxx/a2f200_eval
+    script      hal_cortexm_a2f200_eval.cdl
+    hardware
+    description "
+        The Actel A2F200 HAL package provides the support needed to run
+        eCos on the Actel A2F200 EVAL board."
+}
+
+package CYGPKG_DEVS_FLASH_CORTEXM_A2F200_EVAL {
+     alias      { "Actel SmartFusion evaluation board flash support" a2fxxx_eval_flash_driver }
+     hardware
+     directory   devs/flash/cortexm/a2fxxx/a2f200_eval
+     script      flash_a2f200_eval.cdl
+     description  "
+           Flash driver specifics for the Actel SmartFusion evaluation board (A2F200 EVAL)."
+}
+
+package CYGPKG_DEVS_ETH_CORTEXM_A2F200_EVAL {
+    alias        { "Actel Smartfusion ethernet evaluation board support" a2f200_eval_eth_driver }
+    hardware
+    directory     devs/eth/cortexm/a2f200_eval
+    script        a2f200_eval.cdl
+    description   "Ethernet driver specifics for Actel Smartfusion evaluation boards (A2F200 EVAL)."
+}
+
+
+target smartfusion {
+        alias { "Actel SmartFusion evaluation board (A2F200_EVAL)" smartfusion }
+        packages { CYGPKG_HAL_CORTEXM
+                   CYGPKG_HAL_CORTEXM_A2FXXX
+                   CYGPKG_HAL_CORTEXM_A2F200_EVAL
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+                   CYGPKG_IO_SERIAL_CORTEXM_A2FXXX
+                   CYGPKG_IO_I2C
+                   CYGPKG_DEVS_I2C_CORTEXM_A2FXXX
+                   CYGPKG_DEVS_SPI_CORTEXM_A2FXXX
+                   CYGPKG_IO_SPI
+                   CYGPKG_DEVS_FLASH_SPI_AT25DFXXX
+                   CYGPKG_DEVS_FLASH_CORTEXM_A2F200_EVAL
+                   CYGPKG_DEVS_ETH_CORTEXM_A2F200_EVAL
+                   CYGPKG_DEVS_ETH_CORTEXM_A2FXXX
+                   CYGPKG_DEVS_ETH_PHY
+                 }
+        description "
+        The a2f200_eval target provides the packages needed
+        to run eCos on the Actel A2F200 EVAL (Smartfusion) board."
+}
+
+
+# ==========================================================================
+# End of ecos.db
diff --git a/packages/fs/jffs2/current/ChangeLog b/packages/fs/jffs2/current/ChangeLog
--- a/packages/fs/jffs2/current/ChangeLog
+++ b/packages/fs/jffs2/current/ChangeLog
@@ -1,6 +1,12 @@
+2011-02-17  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/jffs2.cdl: Add CYGNUM_FS_JFFS2_TEST_OFFSET and
+	CYGNUM_FS_JFFS2_TEST_LENGTH, which should have been included in change
+	of 2008-11-18.
+
 2009-04-28  John Dallaway  <john@dallaway.org.uk>
 
-	cdl/jffs2.cdl: Use CYGPKG_IO_FILEIO as the parent.
+	* cdl/jffs2.cdl: Use CYGPKG_IO_FILEIO as the parent.
 
 2009-02-22  Andrew Lunn  <andrew.lunn@ascom.ch>
 
diff --git a/packages/fs/jffs2/current/cdl/jffs2.cdl b/packages/fs/jffs2/current/cdl/jffs2.cdl
--- a/packages/fs/jffs2/current/cdl/jffs2.cdl
+++ b/packages/fs/jffs2/current/cdl/jffs2.cdl
@@ -269,21 +269,50 @@ cdl_package CYGPKG_FS_JFFS2 {
     # ----------------------------------------------------------------
     # Tests
 
-    cdl_option CYGPKG_FS_JFFS2_TESTS {
+    cdl_component CYGPKG_FS_JFFS2_TESTS {
 	display "JFFS2 FS tests"
 	flavor  data
 	no_define
 	calculated { "tests/jffs2_1 tests/jffs2_2 tests/jffs2_3" }
             description   "
                 This option specifies the set of tests for the JFFS2    
-                FS package."
+                FS package.
+                If supported by the configuration, these tests will preferentially
+                use a FIS partition (which may be defined using RedBoot) named
+                \"jffs2test\". If that FIS partition does not exist, then no testing
+                will be performed to avoid any risk of corruption of live data.
+                Alternatively if the configuration does not support that activity,
+                a hard coded specification may be set."
+
+        cdl_component CYGPKG_FS_JFFS2_TEST_DEVICE {
+            display         "Fixed Flash test area specs"
+            no_define
+            default_value   !CYGFUN_IO_FLASH_BLOCK_FROM_FIS
+            description     "
+                This component gives specifications of the flash region to use
+                for testing. It usually only applies when specification via FIS is not
+                possible."
+            
+            cdl_option CYGNUM_FS_JFFS2_TEST_OFFSET {
+                display         "Start offset from flash base"
+                flavor          data
+                default_value   CYGNUM_IO_FLASH_TEST_OFFSET
+                description     "
+                    This gives the offset from the base of the first flash device
+                    of where tests may operate.  It is important to set this correctly,
+                    as an incorrect value could allow the tests to write over critical
+                    portions of the FLASH device and possibly render the target
+                    board totally non-functional."
+            }
+            cdl_option CYGNUM_FS_JFFS2_TEST_LENGTH {
+                display         "Test area length"
+                flavor          data
+                default_value   CYGNUM_IO_FLASH_TEST_LENGTH
+                description     "
+                    This gives the length of the region of flash used for testing."
+            }
         }
-    
+    }
 }
 
 # End of jffs2.cdl
-
-
-
-
-
diff --git a/packages/fs/rom/current/ChangeLog b/packages/fs/rom/current/ChangeLog
--- a/packages/fs/rom/current/ChangeLog
+++ b/packages/fs/rom/current/ChangeLog
@@ -1,3 +1,12 @@
+2010-11-29  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/romfs.cdl: Add CYGFUN_FS_ROM_FLASH_BLOCK_DEVICE_LOOKUP option.
+	* support/mk_romfs.c: Fix Win32 build.
+
+2010-11-13  Alexander Aganichev  <aaganichev@gmail.com>
+
+	* src/romfs.c: Added ability to mount a flash block device by name.
+
 2010-02-28  Øyvind Harboe  <oyvind.harboe@zylin.com>
 
 	* src/romfs.c: file name comparison was broken for two files
@@ -185,7 +194,7 @@ 2000-10-25  Richard Panton (richard.pant
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2009 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2009, 2010 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/fs/rom/current/cdl/romfs.cdl b/packages/fs/rom/current/cdl/romfs.cdl
--- a/packages/fs/rom/current/cdl/romfs.cdl
+++ b/packages/fs/rom/current/cdl/romfs.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2009 Free Software Foundation, Inc.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2009, 2010 Free Software Foundation, Inc.
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -41,7 +41,7 @@
 #
 # Author(s):      nickg
 # Original data:  nickg
-# Contributors:   richard.panton@3glab.com
+# Contributors:   richard.panton@3glab.com, jld
 # Date:           2000-08-01
 #
 #####DESCRIPTIONEND####
@@ -101,6 +101,17 @@ cdl_package CYGPKG_FS_ROM {
             fileio already sets it."
     }
 
+    cdl_option CYGFUN_FS_ROM_FLASH_BLOCK_DEVICE_LOOKUP {
+        display "Lookup flash block device names"
+        flavor bool
+        requires CYGPKG_IO_FLASH
+        requires CYGPKG_IO_FLASH_BLOCK_DEVICE
+        default_value 0
+        description "Enables the location of a ROM filesystem to
+            be specified using a flash block device name such as
+            \"/dev/flash/fis/romfs\" in the call to mount()."
+    }
+
     # ----------------------------------------------------------------
     # Tests
 
diff --git a/packages/fs/rom/current/src/romfs.c b/packages/fs/rom/current/src/romfs.c
--- a/packages/fs/rom/current/src/romfs.c
+++ b/packages/fs/rom/current/src/romfs.c
@@ -136,6 +136,12 @@
 #include <cyg/kernel/kapi.h>
 #include <cyg/infra/diag.h>
 
+#if defined(CYGFUN_FS_ROM_FLASH_BLOCK_DEVICE_LOOKUP)
+#include <cyg/io/io.h>
+#include <cyg/io/config_keys.h>
+#include <cyg/io/flash.h>
+#endif
+
 //==========================================================================
 // Eventually we want to eXecute In Place from the ROM in a protected
 // environment, so we'll need executables to be aligned to a boundary
@@ -593,11 +599,32 @@ static int romfs_mount    ( cyg_fstab_en
     if ( !mte->data ) {
 	// If the image address was not in the MTE data word,
 	if ( mte->devname && mte->devname[0] ) {
-            char *addr;
-            // And there's something in the 'hardware device' field,
-	    // then read the address from there.
-	    sscanf( mte->devname, "%p", &addr );
-            disk = (romfs_disk *) addr;
+	    // If a device name specified, lookup flash block device.
+#if defined(CYGFUN_FS_ROM_FLASH_BLOCK_DEVICE_LOOKUP)
+	    if ( mte->devname[0] == '/' ) {
+		Cyg_ErrNo err;
+		cyg_io_handle_t t;
+		cyg_io_flash_getconfig_devaddr_t d;
+		int len;
+		err = cyg_io_lookup(mte->devname, &t);
+		if (err != ENOERR) {
+		    return -err;
+		}
+		len = sizeof(d);
+		err = cyg_io_get_config(t, CYG_IO_GET_CONFIG_FLASH_DEVADDR, &d, &len);
+		if (err != ENOERR) {
+		    return -err;
+		}
+		disk = (romfs_disk *) d.dev_addr;
+	    } else
+#endif
+	    {
+		char *addr;
+		// And there's something in the 'hardware device' field,
+		// then read the address from there.
+		sscanf( mte->devname, "%p", &addr );
+		disk = (romfs_disk *) addr;
+	    }
         }
     } else {
         disk = (romfs_disk *)mte->data;
diff --git a/packages/fs/rom/current/support/mk_romfs.c b/packages/fs/rom/current/support/mk_romfs.c
--- a/packages/fs/rom/current/support/mk_romfs.c
+++ b/packages/fs/rom/current/support/mk_romfs.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2010 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -88,6 +88,14 @@
 // Undefine this if the host filesystem does not support lstat()
 #define HAS_LSTAT
 
+// Win32 definitions
+#ifdef _WIN32
+#undef HAS_LSTAT
+#define S_ISLNK(m) (0)
+typedef unsigned int uid_t;
+typedef unsigned int gid_t;
+#endif
+
 //==========================================================================
 
 // Return (n) aligned to the next (b) byte boundary
@@ -270,6 +278,7 @@ static unsigned long ConvertMode( unsign
     if ( posix_mode & S_IRUSR )  result |= 1<<16;
     if ( posix_mode & S_IWUSR )  result |= 1<<17;
     if ( posix_mode & S_IXUSR )  result |= 1<<18;
+#ifndef _WIN32
     if ( posix_mode & S_IRGRP )  result |= 1<<19;
     if ( posix_mode & S_IWGRP )  result |= 1<<20;
     if ( posix_mode & S_IXGRP )  result |= 1<<21;
@@ -278,6 +287,7 @@ static unsigned long ConvertMode( unsign
     if ( posix_mode & S_IXOTH )  result |= 1<<24;
     if ( posix_mode & S_ISUID )  result |= 1<<25;
     if ( posix_mode & S_ISGID )  result |= 1<<26;
+#endif
     return result;
 }
 
diff --git a/packages/hal/arm/arch/current/ChangeLog b/packages/hal/arm/arch/current/ChangeLog
--- a/packages/hal/arm/arch/current/ChangeLog
+++ b/packages/hal/arm/arch/current/ChangeLog
@@ -1,3 +1,25 @@
+2014-03-14  John Dallaway  <john@dallaway.org.uk>
+
+	* src/mcount.S: Add mcount functions for call-graph profiling.
+	* cdl/hal_arm.cdl: Add option to build mcount functions.
+	[ Bugzilla 1001959 ]
+
+2011-11-23  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/hal_arm.cdl: Add CDL to control whether both IRQs and FIQs
+	are disabled in critical sections, or only IRQs. The default is to
+	disable both and translate any FIQs into IRQs for delivery. The
+	alternative is for FIQs to essentially exist outside eCos.
+
+	* include/hal_arch.h (CPSR_THREAD_INITIAL):
+	* include/hal_intr.h (CPSR_INTR_MASK, HAL_*_INTERRUPTS)
+	(HAL_*_FIQ): Add definitions for separating FIQ from IRQ.
+
+	* src/hal_mk_defs.c (main):
+	* src/vectors.S (start, FIQ, IRQ, spurious_IRQ):
+	(hal_*_interrupts, hal_*_FIQ, __fiq_stack_base): Add support for
+	separating FIQ from IRQ in critical section processing.
+
 2009-03-06  John Dallaway  <john@dallaway.org.uk>
 
 	* cdl/hal_arm.cdl: Merge goals for CYGHWR_THUMB and
@@ -153,6 +175,13 @@ 2006-01-18  Jay Foster    <jay@systech.c
 	* src/context.S (hal_thread_switch_context): Close race condition
 	that could cause corruption of the sp or lr registers.
 
+2005-12-12  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* include/hal_intr.h (HAL_QUERY_INTERRUPTS): Long-standing
+	bug: this is meant to return an old state acceptable to
+	HAL_RESTORE_INTERRUPTS.
+	(HAL_DISABLE_INTERRUPTS): Small but simple optimisation.
+
 2005-04-21  Ian Campbell  <icampbell@arcom.com>
 
 	* src/redboot_linux_exec.c: Added -t option which takes the
@@ -1800,7 +1829,7 @@ 1998-10-16  Bart Veer  <bartv@cygnus.co.
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2009 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2009, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/hal/arm/arch/current/cdl/hal_arm.cdl b/packages/hal/arm/arch/current/cdl/hal_arm.cdl
--- a/packages/hal/arm/arch/current/cdl/hal_arm.cdl
+++ b/packages/hal/arm/arch/current/cdl/hal_arm.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2014 Free Software Foundation, Inc.
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -41,7 +41,7 @@
 #
 # Author(s):      bartv
 # Original data:  gthomas
-# Contributors:
+# Contributors:   jld
 # Date:           1999-06-13
 #
 #####DESCRIPTIONEND####
@@ -59,6 +59,8 @@ cdl_package CYGPKG_HAL_ARM {
         necessary to select a specific target platform HAL
         package."
 
+    implements    CYGINT_PROFILE_HAL_MCOUNT
+
     compile       hal_misc.c context.S arm_stub.c hal_syscall.c
 
     # The "-o file" is a workaround for CR100958 - without it the
@@ -292,6 +294,33 @@ cdl_package CYGPKG_HAL_ARM {
             handlers."
     }
 
+    cdl_option CYGOPT_HAL_ARM_FIQ_DISABLE {
+        display          "Disable FIQs"
+        default_value    1
+        description      "This option causes the HAL to disable both IRQ and FIQ
+                          interrupts during critical sections. Disabling this option
+                          causes eCos to only disable IRQs and puts FIQ
+                          interrupts outside the eCos world where they cannot interact
+                          with eCos in any way. Disabling this option also enables
+                          a set of macros, HAL_DISABLE|ENABLE|RESTORE|QUERY_FIQ,
+                          that provide control over the delivery of FIQs.
+                          The default is for this option to be enabled, which provides
+                          backward compatibility with previous versions of the ARM HAL."
+    }
+
+    cdl_option CYGNUM_HAL_ARM_FIQ_STACK_SIZE {
+        display          "FIQ stack size"
+        active_if        !CYGOPT_HAL_ARM_FIQ_DISABLE
+        flavor           data
+        legal_values     32 to 0x80000000
+        default_value    512
+        description      "This option set the size of the stack used to handle FIQ
+                          interrupts. It is only used if the HAL is not disabling
+                          FIQs during critical sections. Otherwise FIQs are translated
+                          into IRQs and delivered on the standard interrupt stack."
+    }
+    
+    
     cdl_component CYGPKG_REDBOOT_ARM_OPTIONS {
         display       "Redboot for ARM options"
         flavor        none
@@ -355,6 +384,19 @@ cdl_package CYGPKG_HAL_ARM {
 
     }
 
+    cdl_option CYGBLD_HAL_ARM_MCOUNT {
+        display           "Support call-graph profiling"
+        flavor            bool
+        no_define
+        active_if         CYGPKG_PROFILE_GPROF
+        calculated        CYGPKG_PROFILE_CALLGRAPH
+        requires          { CYGHWR_THUMB implies CYGBLD_ARM_ENABLE_THUMB_INTERWORK }
+        compile           mcount.S
+        description       "
+            Calculate whether mcount functions should be built
+            to support call-graph profiling."
+    }
+
     cdl_option CYGBLD_LINKER_SCRIPT {
         display "Linker script"
         flavor data
diff --git a/packages/hal/arm/arch/current/include/hal_arch.h b/packages/hal/arm/arch/current/include/hal_arch.h
--- a/packages/hal/arm/arch/current/include/hal_arch.h
+++ b/packages/hal/arm/arch/current/include/hal_arch.h
@@ -88,8 +88,11 @@
 #define CPSR_MODE_BITS          0x1F
 
 #define CPSR_INITIAL (CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
+#ifdef CYGOPT_HAL_ARM_FIQ_DISABLE
 #define CPSR_THREAD_INITIAL (CPSR_SUPERVISOR_MODE)
-
+#else
+#define CPSR_THREAD_INITIAL (CPSR_SUPERVISOR_MODE|CPSR_FIQ_DISABLE)
+#endif
 //
 // Vector table offsets
 //
diff --git a/packages/hal/arm/arch/current/include/hal_intr.h b/packages/hal/arm/arch/current/include/hal_intr.h
--- a/packages/hal/arm/arch/current/include/hal_intr.h
+++ b/packages/hal/arm/arch/current/include/hal_intr.h
@@ -62,6 +62,8 @@
 
 #include <cyg/infra/cyg_type.h>
 
+#include <cyg/hal/hal_arch.h>
+
 // This is to allow a variant to decide that there is no platform-specific
 // interrupts file; and that in turn can be overridden by a platform that
 // refines the variant's ideas.
@@ -151,51 +153,58 @@ externC cyg_uint32 hal_default_isr(CYG_A
 typedef cyg_uint32 CYG_INTERRUPT_STATE;
 
 //--------------------------------------------------------------------------
+// Interrupt disable mask
+//
+// This is used to control which of IRQ and FIQ is enabled/disabled by
+// the HAL interrupt control macros, and other places in the HAL. 
+
+#ifdef CYGOPT_HAL_ARM_FIQ_DISABLE
+#define CPSR_INTR_MASK          (CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE)
+#else
+#define CPSR_INTR_MASK          (CPSR_IRQ_DISABLE)
+#endif
+
+//--------------------------------------------------------------------------
 // Interrupt control macros
 
 #ifndef __thumb__
-// Note: This disables both FIQ and IRQ interrupts!
 #define HAL_DISABLE_INTERRUPTS(_old_)           \
     asm volatile (                              \
         "mrs %0,cpsr;"                          \
-        "mrs r4,cpsr;"                          \
-        "orr r4,r4,#0xC0;"                      \
+        "orr r4,%0,%1;"                         \
         "msr cpsr,r4"                           \
         : "=r"(_old_)                           \
-        :                                       \
+        : "i"(CPSR_INTR_MASK)                   \
         : "r4"                                  \
         );
 
 #define HAL_ENABLE_INTERRUPTS()                 \
     asm volatile (                              \
         "mrs r3,cpsr;"                          \
-        "bic r3,r3,#0xC0;"                      \
+        "bic r3,r3,%0;"                         \
         "msr cpsr,r3"                           \
         :                                       \
-        :                                       \
+        : "i"(CPSR_INTR_MASK)                   \
         : "r3"                                  \
         );
 
 #define HAL_RESTORE_INTERRUPTS(_old_)           \
     asm volatile (                              \
         "mrs r3,cpsr;"                          \
-        "and r4,%0,#0xC0;"                      \
-        "bic r3,r3,#0xC0;"                      \
+        "and r4,%0,%1;"                         \
+        "bic r3,r3,%1;"                         \
         "orr r3,r3,r4;"                         \
         "msr cpsr,r3"                           \
         :                                       \
-        : "r"(_old_)                            \
+        : "r"(_old_),"i"(CPSR_INTR_MASK)        \
         : "r3", "r4"                            \
         );
 
 #define HAL_QUERY_INTERRUPTS(_old_)             \
     asm volatile (                              \
-        "mrs r4,cpsr;"                          \
-        "and r4,r4,#0xC0;"                      \
-        "eor %0,r4,#0xC0;"                      \
+        "mrs %0,cpsr;"                          \
         : "=r"(_old_)                           \
-        :                                       \
-        : "r4"                                  \
+        : "i"(CPSR_INTR_MASK)                   \
         );
 #else // __thumb__
 
@@ -299,6 +308,26 @@ externC cyg_uint32 hal_query_interrupts(
 #endif // __thumb__
 
 //--------------------------------------------------------------------------
+// FIQ interrupt control
+//
+// If eCos is not masking FIQs then the user can enable/disable them
+// independently.
+
+#ifndef CYGOPT_HAL_ARM_FIQ_DISABLE
+
+externC cyg_uint32 hal_disable_FIQ(void);
+externC void       hal_enable_FIQ(void);
+externC void       hal_restore_FIQ(cyg_uint32);
+externC cyg_uint32 hal_query_FIQ(void);
+
+#define HAL_DISABLE_FIQ(_old_) _old_ = hal_disable_FIQ()
+#define HAL_ENABLE_FIQ() hal_enable_FIQ()
+#define HAL_RESTORE_FIQ(_old_) hal_restore_FIQ(_old_)
+#define HAL_QUERY_FIQ(_old_) _old_ = hal_query_FIQ()
+
+#endif
+
+//--------------------------------------------------------------------------
 // Routine to execute DSRs using separate interrupt stack
 
 #ifdef  CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
diff --git a/packages/hal/arm/arch/current/src/hal_mk_defs.c b/packages/hal/arm/arch/current/src/hal_mk_defs.c
--- a/packages/hal/arm/arch/current/src/hal_mk_defs.c
+++ b/packages/hal/arm/arch/current/src/hal_mk_defs.c
@@ -140,6 +140,8 @@ main(void)
     DEFINE(HAL_BREAKINST_THUMB, HAL_BREAKINST_THUMB);
     DEFINE(HAL_BREAKINST_ARM, HAL_BREAKINST_ARM);
 
+    DEFINE(CPSR_INTR_MASK, CPSR_INTR_MASK);
+    
     return 0;
 }
 
diff --git a/packages/hal/arm/arch/current/src/mcount.S b/packages/hal/arm/arch/current/src/mcount.S
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/arch/current/src/mcount.S
@@ -0,0 +1,140 @@
+/*==========================================================================
+//
+//      mcount.S
+//
+//      ARM mcount implementation
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2014 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):       jld
+// Contributor(s):  
+// Date:            2014-03-14
+// Description:     This file provides mcount functions used for
+//                  call-graph profiling.
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#include "arm.inc"
+
+/*
+// GCC inserts mcount code at the start of every function when compiling
+// with "-pg". For GCC prior to version 4.4 targeting ARM, the following
+// code is inserted:
+// 
+//   mov r12, lr
+//   bl mcount
+//   .word <data pointer>
+//
+// For GCC version 4.4 and later targeting ARM, the following code is
+// inserted:
+//
+//   push { lr }
+//   bl __gnu_mcount_nc
+//
+// We provide implementations of both mcount() and __gnu_mcount_nc() to
+// call the eCos __profile_mcount() function.
+*/
+
+        .syntax unified
+        .arm
+        .globl mcount
+        .section .text.mcount
+        .type mcount, %function
+mcount:
+        // resume execution beyond the data pointer on return to caller
+        add lr, lr, #4
+
+        // caller assumes r0-r3 will be preserved (non-AAPCS), we use
+        // r6 and must preserve lr across our __profile_mcount() call
+        push { r0, r1, r2, r3, r6, lr }
+
+        // set up parameters for __profile_mcount()
+        sub r0, r12, #2
+        bic r0, r0, #1
+        bic r1, lr, #1
+
+        // disable interrupts
+        mrs r6, cpsr
+        orr r2, r6, #CPSR_INTR_MASK
+        msr cpsr, r2
+
+        // call eCos __profile_mcount()
+        // r6 is preserved across the call per AAPCS
+        bl __profile_mcount
+
+        // restore interrupts
+        msr cpsr, r6
+
+        // restore registers and return
+        pop { r0, r1, r2, r3, r6, r12 }
+        bx r12
+
+
+        .globl __gnu_mcount_nc
+        .section .text.__gnu_mcount_nc
+        .type __gnu_mcount_nc, %function
+__gnu_mcount_nc:
+        // caller assumes r0-r3 will be preserved (non-AAPCS), we use
+        // r6 and must preserve lr across our __profile_mcount() call
+        push { r0, r1, r2, r3, r6, lr }
+
+        // set up parameters for __profile_mcount()
+        ldr r0, [ sp, #24 ]
+        sub r0, r0, #2
+        bic r0, r0, #1
+        bic r1, lr, #1
+
+        // disable interrupts
+        mrs r6, cpsr
+        orr r2, r6, #CPSR_INTR_MASK
+        msr cpsr, r2
+
+        // call eCos __profile_mcount()
+        // r6 is preserved across the call per AAPCS
+        bl __profile_mcount
+
+        // restore interrupts
+        msr cpsr, r6
+
+        // restore registers and return
+        pop { r0, r1, r2, r3, r6, r12, lr }
+        bx r12
+
+//==========================================================================
+// end of mcount.S
diff --git a/packages/hal/arm/arch/current/src/vectors.S b/packages/hal/arm/arch/current/src/vectors.S
--- a/packages/hal/arm/arch/current/src/vectors.S
+++ b/packages/hal/arm/arch/current/src/vectors.S
@@ -428,7 +428,12 @@ 2:
         mov     r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_UNDEF_MODE)
         msr     cpsr,r0
         ldr     sp,.__exception_stack
-
+#ifndef CYGOPT_HAL_ARM_FIQ_DISABLE
+        mov     r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_FIQ_MODE)
+        msr     cpsr,r0
+        ldr     sp,.__fiq_stack
+#endif
+        
         // initialize CPSR (machine state register)
         mov     r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
         msr     cpsr,r0
@@ -770,6 +775,18 @@ 2:
 
         .code   32
 FIQ:
+#ifndef CYGOPT_HAL_ARM_FIQ_DISABLE
+        // If we are not disabling FIQs as part of eCos, these will be under
+        // user control. In theory the user should have installed their own
+        // FIQ VSR before enabling them and we should never come here. If
+        // we do there is nothing eCos itself can do because we are outside
+        // the scope of the system. The default action here, then, is to simply
+        // mask FIQs and return.
+        mrs     r8,spsr                 // CPSR at time of interrupt
+        orr	r8,r8,#CPSR_FIQ_DISABLE
+        msr	spsr,r8
+        subs	pc,lr,#4
+#else        
         // We can get here from any non-user mode.
         mrs     r8,spsr                 // CPSR at time of interrupt
         and     r9,r8,#CPSR_MODE_BITS   // isolate pre-interrupt mode
@@ -793,6 +810,7 @@ FIQ:
 
         // now it looks like we got an IRQ instead of an FIQ except that
         // FIQ is disabled so we don't recurse.
+#endif        
 IRQ:
         // Note: I use this exception stack while saving the context because
         // the current SP does not seem to be always valid in this CPU mode.
@@ -804,6 +822,17 @@ IRQ:
         mov     r3,sp
 	
         mrs     r4,cpsr                 // switch to Supervisor Mode
+
+#ifdef CYGOPT_HAL_ARM_FIQ_DISABLE        
+        // Due to a small chance of contention with FIQ,
+        // we should disable FIQ while still in IRQ mode and then
+        // change to SVC mode. This only applies when eCos is masking
+        // FIQ alongside IRQ, otherwise FIQs are outside eCos' control
+        // and the FIQ to IRQ translation doesn't happen.
+        orr     r4,r4,#CPSR_FIQ_DISABLE        
+        msr     cpsr,r4
+#endif        
+        
         bic     r4,r4,#CPSR_MODE_BITS
         // When handling an IRQ we must disable FIQ unless the current 
         // mode in CPSR is IRQ. If we were to get a FIQ while in another 
@@ -812,7 +841,10 @@ IRQ:
         // for example, the stack pointer would be set to the beginning 
         // of the exception_stack clobbering the registers we have just 
         // saved.
-        orr     r4,r4,#CPSR_SUPERVISOR_MODE|CPSR_FIQ_DISABLE
+        // However, if we are allowing the user to handle their own
+        // FIQs, we don't need to do that, since FIQ will not be
+        // translated to IRQ.
+        orr     r4,r4,#CPSR_SUPERVISOR_MODE|CPSR_INTR_MASK
         msr     cpsr,r4
 
         mov     r5,sp                   // save original svc sp
@@ -990,8 +1022,8 @@ FUNC_START_ARM(hal_interrupt_stack_call_
         stmfd   sp!,{r4,r5,lr}
         // Disable interrupts
         mrs     r4,cpsr                 // disable IRQ's
-        orr     r2,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
-        bic     r5,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
+        orr     r2,r4,#CPSR_INTR_MASK
+        bic     r5,r4,#CPSR_INTR_MASK
         msr     cpsr,r2
         // Switch to interrupt stack
         mov     r3,sp                   // save old stack pointer
@@ -1012,7 +1044,7 @@ FUNC_START_ARM(hal_interrupt_stack_call_
 
         // Disable interrupts
         mrs     r1,cpsr                 // disable IRQ's
-        orr     r2,r1,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
+        orr     r2,r1,#CPSR_INTR_MASK
         msr     cpsr,r2
 
         // Move back to the thread stack.
@@ -1036,21 +1068,21 @@ FUNC_START_ARM(hal_interrupt_stack_call_
 
 FUNC_START_ARM(hal_disable_interrupts, r1)
         mrs     r0,cpsr                 // current state
-        orr     r1,r0,#0xC0             // mask both FIQ and IRQ
+        orr     r1,r0,#CPSR_INTR_MASK   // mask interrupts
         msr     cpsr,r1
         bx      lr                      // exit, _old_ in r0        
 
 FUNC_START_ARM(hal_enable_interrupts, r1)
         mrs     r0,cpsr                 // current state
-        bic     r1,r0,#0xC0             // mask both FIQ and IRQ
+        bic     r1,r0,#CPSR_INTR_MASK   // mask interrupts
         msr     cpsr,r1
         bx      lr                      // exit
         
 FUNC_START_ARM(hal_restore_interrupts, r1)
         mrs     r1,cpsr                 // current state
-        bic     r1,r1,#0xC0             // mask out FIQ/IRQ bits
-        and     r0,r0,#0xC0             // keep only FIQ/IRQ
-        orr     r1,r1,r0                // mask both FIQ and IRQ
+        bic     r1,r1,#CPSR_INTR_MASK   // mask out interrupts
+        and     r0,r0,#CPSR_INTR_MASK   // keep only interrupts
+        orr     r1,r1,r0                // mask interrupts
         msr     cpsr,r1
         bx      lr                      // exit        
 
@@ -1060,6 +1092,38 @@ FUNC_START_ARM(hal_query_interrupts, r1)
 
 #endif // __thumb__
 
+#ifndef CYGOPT_HAL_ARM_FIQ_DISABLE
+
+// Functions for controlling FIQ independently of IRQ.
+// These are only present if we are not manipulating FIQs
+// alongside IRQs in the standard interrupt control macros.
+        
+FUNC_START_ARM(hal_disable_FIQ, r1)
+        mrs     r0,cpsr                 // current state
+        orr     r1,r0,#CPSR_FIQ_DISABLE // mask FIQs
+        msr     cpsr,r1
+        bx      lr                      // exit, _old_ in r0        
+
+FUNC_START_ARM(hal_enable_FIQ, r1)
+        mrs     r0,cpsr                 // current state
+        bic     r1,r0,#CPSR_FIQ_DISABLE // mask FIQs
+        msr     cpsr,r1
+        bx      lr                      // exit
+        
+FUNC_START_ARM(hal_restore_FIQ, r1)
+        mrs     r1,cpsr                 // current state
+        bic     r1,r1,#CPSR_FIQ_DISABLE // mask out FIQs
+        and     r0,r0,#CPSR_FIQ_DISABLE // keep only FIQs
+        orr     r1,r1,r0                // mask FIQs
+        msr     cpsr,r1
+        bx      lr                      // exit        
+
+FUNC_START_ARM(hal_query_FIQ, r1)
+        mrs     r0,cpsr                 // current state
+        bx      lr                      // exit, state in r0
+
+#endif
+        
 // Dummy/support functions
 
         .global __gccmain
@@ -1129,7 +1193,9 @@ PTR(__interrupt_stack)
 #ifdef  CYGHWR_HAL_ARM_DUMP_EXCEPTIONS
 PTR(__dump_procs)
 #endif
-
+#ifndef CYGOPT_HAL_ARM_FIQ_DISABLE        
+PTR(__fiq_stack)
+#endif        
 //
 // Identification - useful to find out when a system was configured
 _eCos_id:
@@ -1187,6 +1253,16 @@ hal_interrupt_objects:
         .endr
 __undef_exception_stack:
 
+#ifndef CYGOPT_HAL_ARM_FIQ_DISABLE
+        .balign 16
+__fiq_stack_base: 
+        .rept   CYGNUM_HAL_ARM_FIQ_STACK_SIZE
+        .byte   0
+        .endr
+        .balign 16        
+__fiq_stack:
+#endif
+        
 // Runtime stack used during all interrupt processing
 #ifndef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
 #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096
diff --git a/packages/hal/arm/at91/var/current/ChangeLog b/packages/hal/arm/at91/var/current/ChangeLog
--- a/packages/hal/arm/at91/var/current/ChangeLog
+++ b/packages/hal/arm/at91/var/current/ChangeLog
@@ -1,3 +1,11 @@
+2010-12-17  John Dallaway  <john@dallaway.org.uk>
+
+	* src/timer_tc.c: Implement a profiling timer on TC1.
+	* cdl/hal_arm_at91.cdl: Add CDL option to enable the profiling timer.
+
+2010-05-27 ccoutand <ccoutand@stmi.com>
+	* include/var_io.h: Added ADC defines for AT91_M55800A CPU
+
 2009-06-03 Oliver Munz <oli@snr.ch>
 
  	* Fix the a problem in the kernel delay_us, if the PIT is
@@ -474,7 +482,7 @@ 2001-07-16  Gary Thomas  <gthomas@redhat
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2009 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2009, 2010 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/hal/arm/at91/var/current/cdl/hal_arm_at91.cdl b/packages/hal/arm/at91/var/current/cdl/hal_arm_at91.cdl
--- a/packages/hal/arm/at91/var/current/cdl/hal_arm_at91.cdl
+++ b/packages/hal/arm/at91/var/current/cdl/hal_arm_at91.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2010 Free Software Foundation, Inc.
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -40,7 +40,7 @@
 ######DESCRIPTIONBEGIN####
 #
 # Author(s):      gthomas
-# Contributors:   gthomas, tkoeller, tdrury, nickg
+# Contributors:   gthomas, tkoeller, tdrury, nickg, jld
 # Date:           2001-07-12
 #
 #####DESCRIPTIONEND####
@@ -135,8 +135,8 @@ cdl_package CYGPKG_HAL_ARM_AT91 {
     cdl_interface CYGINT_HAL_ARM_AT91_SERIAL_DBG_HW {
         display     "Platform has the DBG serial port"
         description "
-            Some varients of the AT91 have a dedicated debug serial
-            port. The HALs of such a varient should implement this interface
+            Some variants of the AT91 have a dedicated debug serial
+            port. The HALs of such a variant should implement this interface
             so allowing the serial driver to the compiled"
     }
 
@@ -154,7 +154,7 @@ cdl_package CYGPKG_HAL_ARM_AT91 {
 
         description   "
             The driver for the dedicated DBG UART will be compiled in the
-            varient HAL when this option is enabled."
+            variant HAL when this option is enabled."
     }
 
     cdl_option CYGBLD_HAL_ARM_AT91_SERIAL_UART {
@@ -165,7 +165,7 @@ cdl_package CYGPKG_HAL_ARM_AT91 {
         requires      !CYGBLD_HAL_ARM_AT91_SERIAL_DBG
         description   "        
             The driver for using the UARTS will be compiled in the
-            varient HAL when this option is enabled."
+            variant HAL when this option is enabled."
     }
 
     cdl_component CYGBLD_HAL_ARM_AT91_DCC {
@@ -190,4 +190,20 @@ cdl_package CYGPKG_HAL_ARM_AT91 {
                 the first serial port. "
         }
     }
+
+    cdl_option CYGFUN_HAL_ARM_AT91_PROFILE_TIMER {
+        display       "Use TC1 for gprof profiling"
+        active_if     CYGPKG_PROFILE_GPROF
+        flavor        bool
+        default_value 1
+        requires      !CYGPKG_HAL_ARM_AT91_JTST
+        implements    CYGINT_PROFILE_HAL_TIMER
+        description   "
+            The AT91 variant HAL can provide support for gprof-based
+            profiling. This uses timer TC1 to generate regular interrupts,
+            and the interrupt handler records the PC at the time of the
+            interrupt. However, TC1 is unavailable for this purpose on
+            the JTST platform. Disable this option if you wish to provide
+            an alternative profiling timer implementation."
+    }
 }
diff --git a/packages/hal/arm/at91/var/current/include/var_io.h b/packages/hal/arm/at91/var/current/include/var_io.h
--- a/packages/hal/arm/at91/var/current/include/var_io.h
+++ b/packages/hal/arm/at91/var/current/include/var_io.h
@@ -2671,10 +2671,33 @@
 //=============================================================================
 // Analog to Digital Convertor (ADC)
 
+#if defined(CYGHWR_HAL_ARM_AT91SAM7) || \
+	            defined (CYGHWR_HAL_ARM_AT91_M55800A)
+
+// AT91SAM7 specifics
 #if defined(CYGHWR_HAL_ARM_AT91SAM7)
+#if !defined(AT91_ADC)
+#define AT91_ADC 0xFFFD8000
+#endif
+
+#if !defined(AT91_MAX_ADC_CHAN)
+#define AT91_MAX_ADC_CHAN 8
+#endif
+#endif
 
-#ifndef AT91_ADC
-#define AT91_ADC 0xFFFD8000
+// AT91_M55800A specifics
+#if defined(CYGHWR_HAL_ARM_AT91_M55800A)
+#if !defined(AT91_ADC)
+#define AT91_ADC 0xFFFB0000
+#endif
+
+#if !defined(AT91_ADC1)
+#define AT91_ADC1 0xFFFB4000
+#endif
+
+#if !defined(AT91_MAX_ADC_CHAN)
+#define AT91_MAX_ADC_CHAN 4
+#endif
 #endif
 
 #define AT91_ADC_CR    0x00 // Control
diff --git a/packages/hal/arm/at91/var/current/src/timer_tc.c b/packages/hal/arm/at91/var/current/src/timer_tc.c
--- a/packages/hal/arm/at91/var/current/src/timer_tc.c
+++ b/packages/hal/arm/at91/var/current/src/timer_tc.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2010 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -40,7 +40,7 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):    gthomas
-// Contributors: gthomas, jskov, nickg, tkoeller
+// Contributors: gthomas, jskov, nickg, tkoeller, jld
 // Date:         2001-07-12
 // Purpose:      HAL board support
 // Description:  Implementations of HAL board interfaces
@@ -58,6 +58,11 @@
 #include <cyg/hal/hal_arch.h>           // Register state info
 #include <cyg/hal/hal_intr.h>           // necessary?
 
+#ifdef CYGFUN_HAL_ARM_AT91_PROFILE_TIMER
+#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
+#include <cyg/profile/profile.h>        // __profile_hit()
+#endif
+
 // -------------------------------------------------------------------------
 // Clock support
 
@@ -158,4 +163,57 @@ void hal_delay_us(cyg_int32 usecs)
     } while ((stat & AT91_TC_SR_CPC) == 0);
 }
 
+#ifdef CYGFUN_HAL_ARM_AT91_PROFILE_TIMER
+
+// Use TC1 for profiling
+#define AT91_TC_PROFILE AT91_TC_TC1
+#define HAL_INTERRUPT_PROFILE CYGNUM_HAL_INTERRUPT_TIMER1
+
+// Profiling timer ISR
+static cyg_uint32 profile_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data, HAL_SavedRegisters *regs)
+{
+    cyg_uint32 status;
+
+    HAL_READ_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_SR, status); // Clear interrupt
+    HAL_INTERRUPT_ACKNOWLEDGE(HAL_INTERRUPT_PROFILE);
+    __profile_hit(regs->pc);
+    return CYG_ISR_HANDLED;
+}
+
+// Profiling timer setup
+int hal_enable_profile_timer(int resolution)
+{
+    cyg_uint32 period;
+
+    // Calculate how many timer ticks the requested resolution in
+    // microseconds equates to. We do this calculation in 64 bit
+    // arithmetic to avoid overflow.
+    period = (cyg_uint32)((((cyg_uint64)resolution) *
+        ((cyg_uint64)CYGNUM_HAL_ARM_AT91_CLOCK_SPEED))/32000000LL);
+
+    CYG_ASSERT(period < 0x10000, "Invalid profile timer resolution"); // 16 bits only
+
+    // Attach ISR
+    HAL_INTERRUPT_ATTACH(HAL_INTERRUPT_PROFILE, &profile_isr, 0x1111, 0);
+    HAL_INTERRUPT_UNMASK(HAL_INTERRUPT_PROFILE);
+
+    // Disable counter
+    HAL_WRITE_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_CCR, AT91_TC_CCR_CLKDIS);
+
+    // Set registers
+    HAL_WRITE_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_CMR, AT91_TC_CMR_CPCTRG | // Reset counter on CPC
+                                                          AT91_TC_CMR_CLKS_MCK32); // Use MCLK/32
+    HAL_WRITE_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_RC, period);
+
+    // Start timer
+    HAL_WRITE_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);
+
+    // Enable timer interrupt
+    HAL_WRITE_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_IER, AT91_TC_IER_CPC);
+
+    return resolution;
+}
+
+#endif // CYGFUN_HAL_ARM_AT91_PROFILE_TIMER
+
 // timer_tc.c
diff --git a/packages/hal/arm/lpc24xx/ea2468/current/ChangeLog b/packages/hal/arm/lpc24xx/ea2468/current/ChangeLog
--- a/packages/hal/arm/lpc24xx/ea2468/current/ChangeLog
+++ b/packages/hal/arm/lpc24xx/ea2468/current/ChangeLog
@@ -1,3 +1,18 @@
+2012-04-23  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.ldi:
+	* include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.ldi: Relocate fixed
+	vectors to 0x40000020. Previously, the HAL_VSR_GET/SET macros
+	accessed the wrong locations and didn't have any effect; now both
+	hardware and software have the same idea of where the VSR table
+	is.
+	NOTE: that this renders RAM applications built with this layout
+	incompatible with RedBoot built with the old layout. A new RedBoot
+	needs to be installed.
+
+	* cdl/hal_arm_lpc24xx_ea2468.cdl:
+	* tests/fiq.c: Add FIQ test program.
+
 2010-03-12  Ross Younger <wry@ecoscentric.com>
 
 	* ea_lpc2468_nand.c: Tweak for updated k9 family NAND driver.
diff --git a/packages/hal/arm/lpc24xx/ea2468/current/cdl/hal_arm_lpc24xx_ea2468.cdl b/packages/hal/arm/lpc24xx/ea2468/current/cdl/hal_arm_lpc24xx_ea2468.cdl
--- a/packages/hal/arm/lpc24xx/ea2468/current/cdl/hal_arm_lpc24xx_ea2468.cdl
+++ b/packages/hal/arm/lpc24xx/ea2468/current/cdl/hal_arm_lpc24xx_ea2468.cdl
@@ -322,6 +322,12 @@ cdl_package CYGPKG_HAL_ARM_LPC24XX_EA246
         }
     }
 
+   cdl_option CYGPKG_HAL_ARM_LPC24XX_EA2468_TESTS_EXTRAS {    
+        display       "EA2468 extra tests"
+        default_value 0
+        description   "Enable hand-run tests for EA2468 board."
+    }
+    
     cdl_component CYGHWR_HAL_ARM_LPC2XXX_EA_LPC2468_NAND {
         display         "EA LPC2xxx NAND support"
         parent          CYGPKG_IO_NAND
@@ -383,7 +389,7 @@ cdl_package CYGPKG_HAL_ARM_LPC24XX_EA246
         display "Tests for LPC2468 OEM board HAL"
         flavor  data
         no_define
-        calculated { "tests/i2c_eeprom" }
+        calculated { "tests/i2c_eeprom" . (CYGPKG_HAL_ARM_LPC24XX_EA2468_TESTS_EXTRAS ? " tests/fiq" : "") }
         description   "
             This option specifies the set of tests for the EA2468 
             OEM board HAL."
diff --git a/packages/hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.ldi b/packages/hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.ldi
--- a/packages/hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.ldi
+++ b/packages/hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.ldi
@@ -10,7 +10,7 @@ MEMORY
 SECTIONS
 {
     SECTIONS_BEGIN
-    SECTION_fixed_vectors (sram, 0x40000400, LMA_EQ_VMA)
+    SECTION_fixed_vectors (sram, 0x40000020, LMA_EQ_VMA)
     SECTION_rom_vectors (ram, 0xA0100000, LMA_EQ_VMA)
     SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
     SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
diff --git a/packages/hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.ldi b/packages/hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.ldi
--- a/packages/hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.ldi
+++ b/packages/hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.ldi
@@ -18,7 +18,7 @@ SECTIONS
     SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
     SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
     SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
-    SECTION_fixed_vectors (sram, 0x40000400, LMA_EQ_VMA)
+    SECTION_fixed_vectors (sram, 0x40000020, LMA_EQ_VMA)
     SECTION_data (ram, 0xA0000000, FOLLOWING (.gcc_except_table))
     SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
     CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
diff --git a/packages/hal/arm/lpc24xx/ea2468/current/tests/fiq.c b/packages/hal/arm/lpc24xx/ea2468/current/tests/fiq.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/arm/lpc24xx/ea2468/current/tests/fiq.c
@@ -0,0 +1,182 @@
+//==========================================================================
+//
+//      fiq.c
+//
+//      FIQ interrupt test
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Date:         2012-04-20
+// Purpose:      
+// Description:  FIQ test
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/diag.h>
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+
+#include <cyg/infra/testcase.h>
+
+#include <cyg/kernel/kapi.h>
+
+//==========================================================================
+
+volatile int fiq_count = 0;
+
+void __attribute__ ((interrupt ("FIQ"))) fiq_vsr( void )
+{
+    fiq_count++;
+
+    // Clear interrupt
+    HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_EINT0 );
+}
+
+//==========================================================================
+
+void fiq_test(CYG_ADDRWORD p)
+{
+    volatile int fiq_count0 = 0;
+    volatile int fiq_count1 = 0;
+    volatile cyg_uint32 val1 = 0;
+    cyg_uint32 pinsel = CYGARC_HAL_LPC24XX_REG_PIN_BASE;
+    cyg_uint32 pinsel4;
+    cyg_uint32 vic = CYGARC_HAL_LPC24XX_REG_VIC_BASE;
+    cyg_uint32 intsel;
+    cyg_uint32 gpio = CYGARC_HAL_LPC24XX_REG_FIO_BASE;
+
+    // Configure P2.10 as EINT0
+    HAL_READ_UINT32( pinsel+CYGARC_HAL_LPC24XX_REG_PINSEL4, pinsel4 );
+    pinsel4 &= ~(3<<20);
+    pinsel4 |= (1<<20);
+    HAL_WRITE_UINT32( pinsel+CYGARC_HAL_LPC24XX_REG_PINSEL4, pinsel4 );
+
+    // Configure EINT0 line for falling edge detection
+    HAL_INTERRUPT_CONFIGURE( CYGNUM_HAL_INTERRUPT_EINT0, false, false );
+
+#if 1 
+    // Route EINT0 to FIQ input
+    HAL_READ_UINT32( vic+CYGARC_HAL_LPC24XX_REG_VICINTSELECT, intsel );
+    intsel |= (1<<CYGNUM_HAL_INTERRUPT_EINT0);
+    HAL_WRITE_UINT32( vic+CYGARC_HAL_LPC24XX_REG_VICINTSELECT, intsel );    
+#endif
+    
+    // Install and unmask FIQ VSR
+    HAL_VSR_SET( CYGNUM_HAL_VECTOR_FIQ, fiq_vsr, NULL );
+    HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_EINT0 );
+
+    CYG_TEST_INFO("FIQ test starting");
+        
+    // Enable FIQs
+    HAL_ENABLE_FIQ();
+
+    while(fiq_count1 < 20)
+    {
+        cyg_uint32 val;
+        cyg_uint8 pin;
+
+        HAL_READ_UINT8( gpio+CYGARC_HAL_LPC24XX_REG_FIO2PIN+1, pin );
+        val = 1&(pin>>2);
+        
+        if( val != val1 )
+        {
+            cyg_uint32 qf;
+            HAL_QUERY_FIQ( qf );            
+            //diag_printf("P2.10 %d fiq_count %d qf %08x\n", val, fiq_count, qf );
+            val1 = val;
+        }
+
+
+        if( fiq_count0 != fiq_count )
+        {
+            int dbcount = 10000;
+            int i = dbcount;
+
+            // Crude debouncing: loop here while fiq_count is
+            // changing, only continue when it has been stable for
+            // dbcount loops.
+            while( i-- )
+            {
+                if( fiq_count0 != fiq_count )
+                {
+                    fiq_count0 = fiq_count;
+                    i = dbcount;
+                }
+            }
+            
+            fiq_count1++;
+            diag_printf("FIQ count %3d debounced %2d\n", fiq_count, fiq_count1 );
+        }
+    }
+
+    CYG_TEST_PASS_FINISH("fiq");
+}
+
+//==========================================================================
+
+#define STACK_SIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
+static char stack[STACK_SIZE];
+static cyg_thread thread_data;
+static cyg_handle_t thread_handle;
+
+void
+cyg_start(void)
+{
+    CYG_TEST_INIT();
+
+    cyg_thread_create(10,                // Priority - just a number
+                      fiq_test,          // entry
+                      0,                 // entry parameter
+                      "FIQ test",        // Name
+                      &stack[0],         // Stack
+                      STACK_SIZE,        // Size
+                      &thread_handle,    // Handle
+                      &thread_data       // Thread data structure
+        );
+    cyg_thread_resume(thread_handle);  /* Start it */
+    cyg_scheduler_start();
+}
+
+//==========================================================================
+// EOF
diff --git a/packages/hal/arm/lpc2xxx/olpce2294/current/ChangeLog b/packages/hal/arm/lpc2xxx/olpce2294/current/ChangeLog
--- a/packages/hal/arm/lpc2xxx/olpce2294/current/ChangeLog
+++ b/packages/hal/arm/lpc2xxx/olpce2294/current/ChangeLog
@@ -1,3 +1,13 @@
+2013-05-13  Uwe Kindler <uwe_kindler@web.de>
+
+	* cdl/hal_arm_lpc2xxx_olpce2294.cdl: Add support for all 4 CAN
+	interfaces.
+
+2012-03-07  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* include/hal_platform_setup.h: Fix assembler warning (s suffix on
+	comparison instruction is deprecated), s/cmps/cmp/.
+
 2009-02-02  Sergei Gavrikov <sergei.gavrikov@gmail.com>
 
  	* cdl/hal_arm_lpc2xxx_olpce2294.cdl: Expanded a list the legal baud
diff --git a/packages/hal/arm/lpc2xxx/olpce2294/current/cdl/hal_arm_lpc2xxx_olpce2294.cdl b/packages/hal/arm/lpc2xxx/olpce2294/current/cdl/hal_arm_lpc2xxx_olpce2294.cdl
--- a/packages/hal/arm/lpc2xxx/olpce2294/current/cdl/hal_arm_lpc2xxx_olpce2294.cdl
+++ b/packages/hal/arm/lpc2xxx/olpce2294/current/cdl/hal_arm_lpc2xxx_olpce2294.cdl
@@ -54,6 +54,10 @@ cdl_package CYGPKG_HAL_ARM_LPC2XXX_OLPCE
     define_header hal_arm_lpc2xxx_olpce2294.h
     include_dir   cyg/hal
     hardware
+    implements CYGINT_DEVS_CAN_LPC2XXX_CAN0
+    implements CYGINT_DEVS_CAN_LPC2XXX_CAN1
+    implements CYGINT_DEVS_CAN_LPC2XXX_CAN2
+    implements CYGINT_DEVS_CAN_LPC2XXX_CAN3
     description   "
         The OLPCE2294 HAL package provides the support needed to run
         eCos on Olimex LPC-E2294 development board."
diff --git a/packages/hal/arm/lpc2xxx/olpce2294/current/include/hal_platform_setup.h b/packages/hal/arm/lpc2xxx/olpce2294/current/include/hal_platform_setup.h
--- a/packages/hal/arm/lpc2xxx/olpce2294/current/include/hal_platform_setup.h
+++ b/packages/hal/arm/lpc2xxx/olpce2294/current/include/hal_platform_setup.h
@@ -117,7 +117,7 @@ 1:
 1:
         ldr r3,[r0,#4]!
         str r3,[r1,#4]!
-        cmps r0,r2
+        cmp r0,r2
         bne 1b
 
         ldr r0,=CYGARC_HAL_LPC2XXX_REG_SCB_BASE
diff --git a/packages/hal/arm/lpc2xxx/olpch2294/current/ChangeLog b/packages/hal/arm/lpc2xxx/olpch2294/current/ChangeLog
--- a/packages/hal/arm/lpc2xxx/olpch2294/current/ChangeLog
+++ b/packages/hal/arm/lpc2xxx/olpch2294/current/ChangeLog
@@ -1,3 +1,8 @@
+2012-03-07  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* include/hal_platform_setup.h: Fix assembler warning (s suffix on
+	comparison instruction is deprecated), s/cmps/cmp/.
+
 2009-02-02  Sergei Gavrikov <sergei.gavrikov@gmail.com>
 
  	* cdl/hal_arm_lpc2xxx_olpch2294.cdl: Expanded a list the legal baud
diff --git a/packages/hal/arm/lpc2xxx/olpch2294/current/include/hal_platform_setup.h b/packages/hal/arm/lpc2xxx/olpch2294/current/include/hal_platform_setup.h
--- a/packages/hal/arm/lpc2xxx/olpch2294/current/include/hal_platform_setup.h
+++ b/packages/hal/arm/lpc2xxx/olpch2294/current/include/hal_platform_setup.h
@@ -118,7 +118,7 @@ 1:
 1:
         ldr r3,[r0,#4]!
         str r3,[r1,#4]!
-        cmps r0,r2
+        cmp r0,r2
         bne 1b
 
         ldr r0,=CYGARC_HAL_LPC2XXX_REG_SCB_BASE
diff --git a/packages/hal/arm/lpc2xxx/olpcl2294/current/ChangeLog b/packages/hal/arm/lpc2xxx/olpcl2294/current/ChangeLog
--- a/packages/hal/arm/lpc2xxx/olpcl2294/current/ChangeLog
+++ b/packages/hal/arm/lpc2xxx/olpcl2294/current/ChangeLog
@@ -1,3 +1,22 @@
+2013-09-11  Uwe Kindler <uwe_kindler@web.de>
+
+	* cdl/hal_arm_lpc2xxx_olpcl2294.cdl: Add support for CAN interface 0.
+
+2012-03-07  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* include/hal_platform_setup.h: Fix assembler warning (s suffix on
+	comparison instruction is deprecated), s/cmps/cmp/.
+
+2010-11-03  JF Argentino  <jf.argentino@osean.fr>
+2010-11-24  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/hal_arm_lpc2xxx_olpcl2294.cdl: Add support for LPC-L2294-8M
+	board: new CDL component CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_VARIANT
+	with CDL option CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_RAMSIZE.
+	* include/hal_platform_setup.h: Add support for LPC-L2294-8M board.
+	* include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_{rom,ram}.{h,ldi}: Define
+	RAM size with new CDL option.
+
 2009-02-02  Sergei Gavrikov <sergei.gavrikov@gmail.com>
 
 	* cdl/hal_arm_lpc2xxx_olpcl2294.cdl: Expanded a list the legal baud
diff --git a/packages/hal/arm/lpc2xxx/olpcl2294/current/cdl/hal_arm_lpc2xxx_olpcl2294.cdl b/packages/hal/arm/lpc2xxx/olpcl2294/current/cdl/hal_arm_lpc2xxx_olpcl2294.cdl
--- a/packages/hal/arm/lpc2xxx/olpcl2294/current/cdl/hal_arm_lpc2xxx_olpcl2294.cdl
+++ b/packages/hal/arm/lpc2xxx/olpcl2294/current/cdl/hal_arm_lpc2xxx_olpcl2294.cdl
@@ -3,7 +3,7 @@
 #      hal_arm_lpc2xxx_olpcl2294.cdl
 #
 #      ARM LPC2XXX OLPCL2294 development board package configuration
-#      data
+#      data, for both 1MB and 8MB of external RAM
 #
 # ====================================================================
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
@@ -49,14 +49,15 @@
 # ====================================================================
 
 cdl_package CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294 {
-    display       "Olimex LPC-L2294-1MB development board HAL"
+    display       "Olimex LPC-L2294 development board HAL"
     parent        CYGPKG_HAL_ARM_LPC2XXX
     define_header hal_arm_lpc2xxx_olpcl2294.h
     include_dir   cyg/hal
     hardware
+    implements CYGINT_DEVS_CAN_LPC2XXX_CAN0
     description   "
         The OLPCL2294 HAL package provides the support needed to run
-        eCos on Olimex LPC-L2294-1MB development board."
+        eCos on Olimex LPC-L2294-1MB or LPC-L2294-8MB development board."
 
     compile       olpcl2294_misc.c
 
@@ -71,6 +72,23 @@ cdl_package CYGPKG_HAL_ARM_LPC2XXX_OLPCL
         puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
     }
 
+    cdl_component CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_VARIANT {
+        display        "OLPCL2294 variant used"
+        flavor         data
+        default_value  { "OLPCL2294_1M" }
+        legal_values   { "OLPCL2294_1M" "OLPCL2294_8M" }
+        define -file system.h CYGHWR_OLIMEX_BOARD
+        description    "Choose the OLIMEX LPC-L2294 board variant"
+
+        cdl_option CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_RAMSIZE {
+            display       "External RAM size"
+            flavor        data
+            calculated    { is_substr(CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_VARIANT, "1M") ?
+                                    0x100000 : 0x800000 }
+            description   "The installed RAM size depends on the board variant"
+        }
+    }
+
     cdl_component CYG_HAL_STARTUP {
         display       "Startup type"
         flavor        data
diff --git a/packages/hal/arm/lpc2xxx/olpcl2294/current/include/hal_platform_setup.h b/packages/hal/arm/lpc2xxx/olpcl2294/current/include/hal_platform_setup.h
--- a/packages/hal/arm/lpc2xxx/olpcl2294/current/include/hal_platform_setup.h
+++ b/packages/hal/arm/lpc2xxx/olpcl2294/current/include/hal_platform_setup.h
@@ -119,7 +119,7 @@ 1:
 1:
         ldr r3,[r0,#4]!
         str r3,[r1,#4]!
-        cmps r0,r2
+        cmp r0,r2
         bne 1b
 
         ldr r0,=CYGARC_HAL_LPC2XXX_REG_SCB_BASE
@@ -138,8 +138,9 @@ 1:
         // memories, while memory chips capable of accepting 16 or 32 bit wide
         // data will work with RBLE = 1.
         //
-        // BANK0: 2M FLASH
-        // TE28F160C3BD70 (1024Kx16 x 1, 70nS)
+        // BANK0: FLASH memory
+        //     -TE28F160C3BD70 (1024Kx16 x 1 = 2MB, 70nS) for 1MB RAM version
+        //     -TE28F320C3BD70 (2048Kx16 x 1 = 4MB, 70ns) for 8MB RAM version
         ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG0
         ldr r1,=  (0x3 << 0)    /* IDCY=3, idle timing  */\
                 | (0x4 << 5)    /* WST1=4, read timing  */\
@@ -148,16 +149,28 @@ 1:
                 | (0x1 << 28)   /* MW=1,   16-bits      */
         str r1,[r0]
 
-        // BANK1: 1M RAM
-        // K6R4016V1D (512Kx16 x 2, 10nS)
-        ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG1
+        // BANK1: external RAM
         // Warning: changed these timings, you can fall dramatically the eCos
         // kernel performance. Check it then using the eCos 'tm_basic' test.
+        // TODO A way to make the timing value dependent of CCLK
+        ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG1
+#if defined (CYGHWR_OLIMEX_BOARD_OLPCL2294_1M)
+        // 1MB version uses K6R4016V1D (512Kx16 x 2, 10nS)
         ldr r1,=  (0x0 << 0)    /* IDCY=0, idle cycles  */\
                 | (0x0 << 5)    /* WST1=0, read timing  */\
                 | (0x1 << 10)   /* RBLE=1               */\
                 | (0x0 << 11)   /* WST2=0, write timing */\
                 | (0x2 << 28)   /* MW=2,   32-bits      */
+#elif defined (CYGHWR_OLIMEX_BOARD_OLPCL2294_8M)
+        // 8MB version uses a K1S321611C (2048Kx16 x 2, 70ns)
+        ldr r1,=  (0x3 << 0)    /* IDCY=3, idle cycles TODO */\
+                | (0x4 << 5)    /* WST1=4, read timing  */\
+                | (0x1 << 10)   /* RBLE=1               */\
+                | (0x4 << 11)   /* WST2=4, write timing */\
+                | (0x2 << 28)   /* MW=2,   32-bits      */
+#else
+#error Board not supported, OLIMEX LPC-L2294 1M or 8M only for now.
+#endif
         str r1,[r0]
 
         // BANK2: Ethernet
diff --git a/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_ram.h b/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_ram.h
--- a/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_ram.h
+++ b/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_ram.h
@@ -5,7 +5,7 @@
 #endif
 
 #define CYGMEM_REGION_ram (0x81000000)
-#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_RAMSIZE)
 #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
 
 #ifndef __ASSEMBLER__
@@ -15,5 +15,5 @@ extern char CYG_LABEL_NAME (__heap1) [];
 
 #define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
 
-#define CYGMEM_SECTION_heap1_SIZE (0x81100000 - (size_t) CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
 
diff --git a/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_ram.ldi b/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_ram.ldi
--- a/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_ram.ldi
+++ b/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_ram.ldi
@@ -3,7 +3,7 @@
 MEMORY
 {
     ram0 : ORIGIN = 0x40000000, LENGTH = 0x4000
-    ram  : ORIGIN = 0x81000000, LENGTH = 0x100000
+    ram  : ORIGIN = 0x81000000, LENGTH = CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_RAMSIZE
 }
 
 SECTIONS
diff --git a/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_rom.h b/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_rom.h
--- a/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_rom.h
+++ b/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_rom.h
@@ -8,7 +8,7 @@
 #define CYGMEM_REGION_rom_SIZE (0x00040000)
 #define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
 #define CYGMEM_REGION_ram (0x81000000)
-#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_RAMSIZE)
 #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
 
 #ifndef __ASSEMBLER__
@@ -18,5 +18,5 @@ extern char CYG_LABEL_NAME (__heap1) [];
 
 #define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
 
-#define CYGMEM_SECTION_heap1_SIZE (0x81100000 - (size_t) CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
 
diff --git a/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_rom.ldi b/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_rom.ldi
--- a/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_rom.ldi
+++ b/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_rom.ldi
@@ -3,7 +3,7 @@
 MEMORY
 {
     ram0   : ORIGIN = 0x40000000, LENGTH = 0x4000
-    ram    : ORIGIN = 0x81000000, LENGTH = 0x100000
+    ram    : ORIGIN = 0x81000000, LENGTH = CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_RAMSIZE
     rom    : ORIGIN = 0x00000000, LENGTH = 0x40000
 }
 
diff --git a/packages/hal/arm/lpc2xxx/var/current/ChangeLog b/packages/hal/arm/lpc2xxx/var/current/ChangeLog
--- a/packages/hal/arm/lpc2xxx/var/current/ChangeLog
+++ b/packages/hal/arm/lpc2xxx/var/current/ChangeLog
@@ -1,3 +1,8 @@
+2012-03-13  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* src/lpc2xxx_misc.c: Fix compiler warning about variable that is set
+	but not used.
+
 2009-06-10  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
 
 	* src/hal_diag.c: workaround for a suppressing a compiler warning,
diff --git a/packages/hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c b/packages/hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c
--- a/packages/hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c
+++ b/packages/hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c
@@ -436,7 +436,7 @@ void hal_interrupt_set_level(int vector,
     if (level < 16)
     {
         cyg_uint32 addr_offset =  level << 2;
-        cyg_uint32 reg_val;
+        cyg_uint32 reg_val CYGBLD_ATTRIB_UNUSED;
         
         HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE + 
                         CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL0 + 
diff --git a/packages/hal/common/current/ChangeLog b/packages/hal/common/current/ChangeLog
--- a/packages/hal/common/current/ChangeLog
+++ b/packages/hal/common/current/ChangeLog
@@ -1,3 +1,43 @@
+2013-06-13  Ilija Kocho <ilijak@siva.com.mk>
+
+	* tests/cache.c : Fix compiler warning about variable set but not used.
+	[ Bugzilla 1001865 ]
+
+2012-04-25  Ilija Kocho <ilijak@siva.com.mk>
+
+	* include/hal_stub.h, src/hal_stub.c, src/thread-packets.c:
+	NUMREGS replaced by HAL_STUB_REGISTERS_SIZE in thread-packets.c
+	[Bugzilla 1001558]
+
+2012-03-14  Grant Edwards <grant.b.edwards@gmail.com>
+
+	* src/generic-stub.c (process_query): Fix compiler warning about
+	variable that is set but not used (only used in conditionally
+	compiled code). [ Bugzilla 1001535 ]
+
+2012-03-09  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* src/hal_if.c (hal_ctrlc_check): Fix compiler warning about
+	variable that is set but not used (isr_ret has been removed).
+
+2011-01-13  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal.cdl: Add a CDL interface to control whether interrupt
+	state must be saved. [ Bugzilla 1001111 ]
+	* cdl/debugging.cdl: Implement the new interface within GDB Ctrl-C
+	break options.
+	* src/hal_if.c: Make declaration of the hal_saved_interrupt_state
+	variable conditional on an implementation of the new CDL interface.
+
+2010-11-20  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal.cdl: Suppress -fprofile-arcs (which implies -lgcov) when
+	generating extras.o.
+
+2010-10-09  John Dallaway  <john@dallaway.org.uk>
+
+	* doc/porting.sgml: Delete references to the memory layout editor.
+
 2009-02-02  Bart Veer  <bartv@ecoscentric.com>
 
 	* cdl/hal.cdl: add CYGBLD_GLOBAL_WARNFLAGS, as part of global
@@ -2342,7 +2382,7 @@ 1998-08-18  Nick Garnett  <nickg@cygnus.
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2010, 2011 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/hal/common/current/cdl/debugging.cdl b/packages/hal/common/current/cdl/debugging.cdl
--- a/packages/hal/common/current/cdl/debugging.cdl
+++ b/packages/hal/common/current/cdl/debugging.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2011 Free Software Foundation, Inc.
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -41,7 +41,7 @@
 #
 # Author(s):      jskov
 # Original data:  nickg,jskov,jlarmour
-# Contributors:
+# Contributors:   jld
 # Date:           1999-07-02
 #
 #####DESCRIPTIONEND####
@@ -89,6 +89,7 @@ cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SU
     active_if     CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
     requires      CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
     default_value CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+    implements    CYGINT_HAL_COMMON_SAVED_INTERRUPT_STATE_REQUIRED
     description   "
         This option causes the GDB stub to add a serial interrupt handler
         which will listen for GDB break packets. This lets you stop the
@@ -109,6 +110,7 @@ cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SU
     active_if     { CYGSEM_HAL_USE_ROM_MONITOR || CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS }
     active_if     { CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0 }
     default_value { !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS }
+    implements    CYGINT_HAL_COMMON_SAVED_INTERRUPT_STATE_REQUIRED
     description   "
         This option adds an interrupt handler for the GDB serial line
         which will listen for GDB break packets. This lets you stop the
diff --git a/packages/hal/common/current/cdl/hal.cdl b/packages/hal/common/current/cdl/hal.cdl
--- a/packages/hal/common/current/cdl/hal.cdl
+++ b/packages/hal/common/current/cdl/hal.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2010, 2011 Free Software Foundation, Inc.
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -41,7 +41,7 @@
 #
 # Author(s):      bartv
 # Original data:  nickg,jskov,jlarmour
-# Contributors:   dmoseley
+# Contributors:   dmoseley, jld
 # Date:           1999-06-13
 #
 #####DESCRIPTIONEND####
@@ -69,7 +69,7 @@ cdl_package CYGPKG_HAL {
 
     make -priority 250 {
         <PREFIX>/lib/extras.o: <PREFIX>/lib/libextras.a
-        $(CC) $(CFLAGS) -nostdlib -Wl,-r -T /dev/null -Wl,--whole-archive -o $@ $<
+        $(CC) $(CFLAGS) -fno-profile-arcs -nostdlib -Wl,-r -T /dev/null -Wl,--whole-archive -o $@ $<
     }   
 
     cdl_option CYGBLD_GLOBAL_WARNFLAGS {
@@ -397,7 +397,7 @@ cdl_package CYGPKG_HAL {
 
     # Does platform need special I/O initializations?
     cdl_interface     CYGINT_HAL_PLF_IF_INIT {
-        display       "Platform defined I/O channels."
+        display       "Platform defined I/O channels"
         description   "
           Platforms which provide additional I/O channels can implement
           this interface, indicating that the function plf_if_init()
@@ -406,12 +406,22 @@ cdl_package CYGPKG_HAL {
 
     # Does platform provide IDE I/O macros?
     cdl_interface     CYGINT_HAL_PLF_IF_IDE {
-        display       "Platform IDE I/O support."
+        display       "Platform IDE I/O support"
         description   "
           Platforms which provide IDE controllers can implement
           this interface, indicating that IDE I/O macros are
           available."
     }
+
+    # Does anything require access to saved interrupt state?
+    cdl_interface     CYGINT_HAL_COMMON_SAVED_INTERRUPT_STATE_REQUIRED {
+        display       "Saved interrupt state required"
+        description   "
+          Components requiring access to saved interrupt state via the
+          hal_saved_interrupt_state symbol should implement this
+          interface."
+    }
+
     cdl_option CYGPKG_HAL_GDB_FILEIO {
         display       "File I/O operations via GDB"
         default_value 0
diff --git a/packages/hal/common/current/doc/porting.sgml b/packages/hal/common/current/doc/porting.sgml
--- a/packages/hal/common/current/doc/porting.sgml
+++ b/packages/hal/common/current/doc/porting.sgml
@@ -9,7 +9,7 @@
 <!-- =============================================================== -->
 <!-- ####ECOSDOCCOPYRIGHTBEGIN####                                       -->
 <!-- ===============================================================     -->
-<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. -->
+<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2010 Free Software Foundation, Inc. -->
 <!-- This material may be distributed only subject to the terms          -->
 <!-- and conditions set forth in the Open Publication License, v1.0      -->
 <!-- or later (the latest version is presently available at              -->
@@ -1797,7 +1797,7 @@ RedBoot. You are advised to read all the
 <orderedlist>
 <listitem><para>Copy an existing platform HAL from the same or another
     architecture. Rename the files as necessary to follow the
-    standard: CDL and MLT related files should contain the
+    standard: CDL and memory layout related files should contain the
     &lt;arch&gt;_&lt;variant&gt;_&lt;platform&gt; triplet.</para>
 </listitem>
 
@@ -1817,12 +1817,12 @@ RedBoot. You are advised to read all the
     packages will be added later.</para>
 </listitem>
 
-<listitem><para>Adjust the MLT files in
+<listitem><para>Adjust the memory layout files in
     <filename>include/pkgconf</filename> to match the memory layout on
-    the platform. For initial testing it should be enough to just hand
+    the platform. <!-- For initial testing it should be enough to just hand
     edit .h and .ldi files, but eventually you should generate all
     files using the memory layout editor in the configuration
-    tool. See <xref linkend="hal-porting-platform-memory-layout"> for
+    tool. --> See <xref linkend="hal-porting-platform-memory-layout"> for
     more details.</para>
 </listitem>
 
@@ -2591,9 +2591,13 @@ monitor, then different output formats w
 <section id="hal-porting-platform-memory-layout">
 <TITLE>Platform Memory Layout</TITLE>
 
-<para>The platform memory layout is defined using the Memory
-Configuration Window <!-- [FIXME: ref] --> in the Configuration Tool.</para>
-
+<para>Historically, the platform memory layout was defined using a Memory
+Configuration window in the eCos Configuration Tool (version 1.x).
+However, the memory layout feature was not ported to the wxWidgets version
+of the tool (version 2.0 and later). Memory layouts are currently manipulated
+using a text editor.</para>
+
+<!--
 <note>
 <para>If you do not have access to a Windows machine, you can
 hand edit the <filename>.h</filename> and <filename>.ldi</filename> files to match the
@@ -2601,18 +2605,21 @@ properties of your platform. If you want
 to the eCos community, ask someone on the list to make proper memory
 map files for you.</para>
 </note>
+-->
 
 <section>
 <title>Layout Files</title>
 
-<para>The memory configuration details are saved in three files:</para>
+<para>The memory configuration details are specified in two files:</para>
 
 <variablelist>
+<!--
 <varlistentry>
 <term><filename>.mlt</filename></term>
 	<listitem><para>This is the Configuration Tool save-file. It is only used
 	by the Configuration Tool.</para></listitem>
 </varlistentry>	
+-->
 <varlistentry>
 <term><filename>.ldi</filename></term>
 	<listitem><para>This is the linker script fragment. It defines the memory
@@ -2627,8 +2634,11 @@ map files for you.</para>
 </varlistentry>
 </variablelist>
 
-<para>These three files are generated for each startup-type, since the
-memory details usually differ.</para>
+<para>These files are generated for each startup-type, since the
+memory details usually differ. The layout and structure of new files
+should match those of existing memory layout files to allow for the
+introduction of a new memory layout editor in the future.
+</para>
 
 </section>
 
@@ -2640,8 +2650,8 @@ purposes, making room for exception vect
 startup configurations also need to reserve some space at the bottom
 of the memory map for the ROM monitor.</para>
 
-<para>These reserved areas are named with the prefix "reserved_" which is
-handled specially by the Configuration Tool: instead of referring to a
+<para>These reserved areas are named with the prefix "reserved_" <!-- which is
+handled specially by the Configuration Tool: --> instead of referring to a
 linker macro, the start of the area is labeled and a gap left in the
 memory map.</para>
 
diff --git a/packages/hal/common/current/include/hal_stub.h b/packages/hal/common/current/include/hal_stub.h
--- a/packages/hal/common/current/include/hal_stub.h
+++ b/packages/hal/common/current/include/hal_stub.h
@@ -82,6 +82,15 @@ typedef cyg_int32  int32;
 #endif
 #include <cyg/hal/generic-stub.h>
 
+// Some architectures use registers of different sizes, so NUMREGS
+// alone is not sufficient to size the register save area. For those
+// architectures, HAL_STUB_REGISTERS_SIZE is defined as the number
+// of target_register_t sized elements in the register save area.
+#ifndef HAL_STUB_REGISTERS_SIZE
+#define HAL_STUB_REGISTERS_SIZE NUMREGS
+#endif
+
+
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/packages/hal/common/current/src/generic-stub.c b/packages/hal/common/current/src/generic-stub.c
--- a/packages/hal/common/current/src/generic-stub.c
+++ b/packages/hal/common/current/src/generic-stub.c
@@ -2007,7 +2007,7 @@ process_query (char *pkt)
   else
     {
       char ch ;
-      char * subpkt ;
+      char *subpkt CYGBLD_ATTRIB_UNUSED;
       ch = *pkt ;
       subpkt = pkt + 1 ;
       switch (ch)
diff --git a/packages/hal/common/current/src/hal_if.c b/packages/hal/common/current/src/hal_if.c
--- a/packages/hal/common/current/src/hal_if.c
+++ b/packages/hal/common/current/src/hal_if.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2008, 2011 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -40,7 +40,7 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):   jskov
-// Contributors:jskov, woehler
+// Contributors:jskov, woehler, jld
 // Date:        2000-06-07
 //
 //####DESCRIPTIONEND####
@@ -887,11 +887,13 @@ hal_if_diag_read_char(char *c)
 // CtrlC support
 //=============================================================================
 
+#if CYGINT_HAL_COMMON_SAVED_INTERRUPT_STATE_REQUIRED > 0
+struct Hal_SavedRegisters *hal_saved_interrupt_state;
+#endif
+
 #if defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) \
     || defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
 
-struct Hal_SavedRegisters *hal_saved_interrupt_state;
-
 void
 hal_ctrlc_isr_init(void)
 {
@@ -945,7 +947,7 @@ hal_ctrlc_check(CYG_ADDRWORD vector, CYG
 {
     hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
     int gdb_vector = vector-1;
-    int isr_ret, ctrlc = 0;
+    int ctrlc = 0;
 
     // This check only to avoid crash on older stubs in case of unhandled
     // interrupts. It is a bit messy, but required in a transition period.
@@ -955,7 +957,7 @@ hal_ctrlc_check(CYG_ADDRWORD vector, CYG
         gdb_vector = CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_DBG_ISR_VECTOR);
     }
     if (vector == gdb_vector) {
-        isr_ret = CYGACC_COMM_IF_DBG_ISR(*__chan, &ctrlc, vector, data);
+        CYGACC_COMM_IF_DBG_ISR(*__chan, &ctrlc, vector, data);
         if (ctrlc) {
             cyg_hal_user_break( (CYG_ADDRWORD *)hal_saved_interrupt_state );
             return true;
diff --git a/packages/hal/common/current/src/hal_stub.c b/packages/hal/common/current/src/hal_stub.c
--- a/packages/hal/common/current/src/hal_stub.c
+++ b/packages/hal/common/current/src/hal_stub.c
@@ -83,14 +83,6 @@
 //-----------------------------------------------------------------------------
 // Extra eCos data.
 
-// Some architectures use registers of different sizes, so NUMREGS
-// alone is not suffucient to size the register save area. For those
-// architectures, HAL_STUB_REGISTERS_SIZE is defined as the number
-// of target_register_t sized elements in the register save area.
-#ifndef HAL_STUB_REGISTERS_SIZE
-#define HAL_STUB_REGISTERS_SIZE NUMREGS
-#endif
-
 // Saved registers.
 HAL_SavedRegisters *_hal_registers;
 target_register_t registers[HAL_STUB_REGISTERS_SIZE];
diff --git a/packages/hal/common/current/src/thread-packets.c b/packages/hal/common/current/src/thread-packets.c
--- a/packages/hal/common/current/src/thread-packets.c
+++ b/packages/hal/common/current/src/thread-packets.c
@@ -134,7 +134,7 @@ static void stub_copy_registers(
                            )
 {
   target_register_t * limit ;
-  limit = dest + NUMREGS ;
+  limit = dest + HAL_STUB_REGISTERS_SIZE ;
 
   while (dest < limit)  *dest++ = *src++ ;
 }
@@ -480,9 +480,10 @@ void stub_pkt_currthread(
                                 int bufmax)
 {
   threadref thread ;
+#if PKT_DEBUG
   char * base_out ;
   base_out = outbuf ;
-  
+#endif
   if (dbg_currthread(&thread))
     {
       *outbuf++ = 'Q' ;
diff --git a/packages/hal/common/current/tests/cache.c b/packages/hal/common/current/tests/cache.c
--- a/packages/hal/common/current/tests/cache.c
+++ b/packages/hal/common/current/tests/cache.c
@@ -96,7 +96,7 @@ volatile char m[(HAL_DCACHE_SIZE/HAL_DCA
 static void time0(register cyg_uint32 stride)
 {
     register cyg_uint32 j,k;
-    register char c;
+    register char c CYGBLD_ATTRIB_UNUSED;
 
     diag_printf("stride=%d\n", stride);
 
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/ChangeLog b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/ChangeLog
@@ -0,0 +1,45 @@
+2011-01-18  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* cdl/hal_cortexm_a2f200_eval.cdl:
+	* doc/a2f200e.sgml
+	* src/a2f200_eval_misc.c:
+	* src/platform_i2c.c:
+	* host/memory-map.xml:
+	* host/softconsole_flash_init.txt:
+	* host/softconsole_sram_init.txt:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* include/pkgconf/mlt_cortexm_a2f200_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_a2f200_eval_rom.h:
+	* include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.ldi:
+	* include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.h:
+	* include/pkgconf/mlt_cortexm_a2f200_eval_sram.ldi:
+	* include/pkgconf/mlt_cortexm_a2f200_eval_sram.h:
+	New package -- Actel Smartfusion A2F200 EVAL board HAL.
+	[Bugzilla 1001291]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
+
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/cdl/hal_cortexm_a2f200_eval.cdl b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/cdl/hal_cortexm_a2f200_eval.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/cdl/hal_cortexm_a2f200_eval.cdl
@@ -0,0 +1,328 @@
+##==========================================================================
+##
+##      hal_cortexm_a2f200_eval.cdl
+##
+##      Actel Smartfusion A2F200 EVAL platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ccoutand
+## Date:         2011-02-13
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_A2F200_EVAL {
+    display       "Actel Smartfusion Development Board HAL"
+    doc           ref/hal-cortexm-a2fxxx-a2f200-eval.html
+    parent        CYGPKG_HAL_CORTEXM_A2FXXX
+    define_header hal_cortexm_a2f200_eval.h
+    include_dir   cyg/hal
+    hardware
+    description   "
+        The Actel Smartfusion HAL package provides the support needed to run
+        eCos on the Actel Smartfusion A2F200 EVAL board."
+
+    compile       a2f200_eval_misc.c platform_i2c.c
+
+    requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
+                    (1 == CYGHWR_DEVS_ETH_PHY_DP8384X) }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_a2fxxx.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_a2f200_eval.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M3\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Smartfusion A2F200 EVAL\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
+    cdl_option CYGNUM_DEVS_FLASH_SPI_AT25XXX_DEV0_MAP_ADDR {
+        display       "Base address of the SPI flash device"
+        flavor        data
+        default_value 0x10000000
+        description   "
+            Specifies the base address of the Atmel AT95DFxxx SPI flash."
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Architecture Startup type"
+        flavor        data
+        legal_values  { "SRAM" "ROM" }
+        calculated    { CYG_HAL_PLF_STARTUP == "SRAM" ? "SRAM" : "ROM" }
+        description   "
+            Mapping of CYG_HAL_PLF_STARTUP to CYG_HAL_STARTUP"
+        define -file system.h CYG_HAL_STARTUP
+    }
+
+    cdl_component CYG_HAL_PLF_STARTUP {
+        display       "Platform Startup type"
+        flavor        data
+        default_value {"ROM"}
+        legal_values  {"SRAM" "ROM" "ROM_SOFTCONSOLE"}
+        description   "
+            When targeting the Smartfusion A2F200 EVAL board it is possible 
+            to build the system for either SRAM bootstrap or ROM bootstrap.
+            Select 'SRAM' when building programs to load into SRAM using 
+            on-board debug software such as RedBoot or eCos GDB stubs or via 
+            a JTAG debugger.
+            Select 'ROM' when building a stand-alone application which will 
+            be put into ROM. The 'ROM_SOFTCONSOLE' type allows programs to be 
+            loaded (to 'ROM') and debug using the SoftConsole IDE."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated    { (CYG_HAL_PLF_STARTUP == "SRAM" ) ? "cortexm_a2f200_eval_sram"      :
+                        (CYG_HAL_PLF_STARTUP == "ROM" )  ? "cortexm_a2f200_eval_rom"       :
+                        (CYG_HAL_PLF_STARTUP == "ROM_SOFTCONSOLE" )  ? "cortexm_a2f200_eval_rom_sc" :
+                                                       "undefined" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+                display "Memory layout linker script fragment"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+                display "Memory layout header file"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_H
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+
+    }
+
+    # Both UARTs 0 and 1 are available for diagnostic/debug use.
+    implements CYGINT_HAL_A2FXXX_UART0
+
+    implements      CYGINT_IO_SERIAL_FLOW_CONTROL_HW
+    implements      CYGINT_IO_SERIAL_LINE_STATUS_HW
+    
+    
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The Actel Smartfusion EVAL board has two serial ports. This option
+            chooses which port will be used to connect to a host
+            running GDB."
+     }
+
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Diagnostic serial port"
+         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+         default_value    0
+         description      "
+            The Actel Smartfusion EVAL has two serial ports. This option
+            chooses which port will be used for diagnostic output."
+     }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console port if the
+            console and GDB port are the same."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+	    Global build options including control over
+	    compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" "GDB_stubs" }
+         default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+         parent        CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM monitor.
+             This support changes various eCos semantics such as the encoding
+             of diagnostic output, or the overriding of hardware interrupt
+             vectors.
+             Firstly there is \"Generic\" support which prevents the HAL
+             from overriding the hardware vectors that it does not use, to
+             instead allow an installed ROM monitor to handle them. This is
+             the most basic support which is likely to be common to most
+             implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included in
+             the ROM monitor or boot ROM."
+     }
+
+    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+        display       "Redboot HAL options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+        description   "
+            This option lists the target's requirements for a valid Redboot
+            configuration."
+
+        requires { CYGNUM_REDBOOT_FLASH_BASE == 0x60000000 }
+
+        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+            display       "Build Redboot ROM binary images"
+            active_if     CYGBLD_BUILD_REDBOOT
+            default_value 1
+            no_define
+            description "This option enables the conversion of the Redboot ELF
+                         image to binary image formats suitable for ROM programming."
+
+            make -priority 325 {
+                <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+                $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+                $(OBJCOPY) -O binary $< $@
+            }
+        }
+    }
+
+    cdl_component CYGBLD_HAL_CORTEXM_A2FXXX_EVAL_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+                <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+                <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) -O binary $< $@
+        }
+
+        description "This component causes the ELF image generated by the
+                     build process to be converted to S-Record and binary
+                     files."
+    }
+    
+}
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/doc/a2f200e.sgml b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/doc/a2f200e.sgml
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/doc/a2f200e.sgml
@@ -0,0 +1,814 @@
+<!-- DOCTYPE reference  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                         -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     a2f200e.sgml                                                -->
+<!--                                                                 -->
+<!--     Actel Smartfusion Board Support.                            -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2011 Free Software Foundation, Inc.               -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   ccoutand                                           -->
+<!-- Contact(s):                                                     -->
+<!-- Date:        2011/06/04                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+<part id="hal-cortexm-a2fxxx-a2f200-eval"><title>Actel Smartfusion Board Support</title>
+
+  <!-- {{{ Actel Smartfusion Board Support  -->
+  <chapter id="a2f200-eval-chapter">
+
+      <title>Actel Smartfusion Board Support</title>
+
+      <!-- {{{ Overview -->
+      <refentry id="a2f200-over">
+
+      <refmeta>
+          <refentrytitle>Overview</refentrytitle>
+      </refmeta>
+
+      <refnamediv>
+          <refname>Overview</refname>
+          <refpurpose>Actel Smartfusion Board Support</refpurpose>
+      </refnamediv>
+
+      <refsect1 id="a2f200-eval-overview"><title>Overview</title>
+
+      <para>
+        The Actel Smartfusion evaluation kit uses the A2F200 microcontroller from the 
+        Actel smartfusion family. The SmartFusion devices are a mix of programmable 
+        logic around a ARM cortex-M3 based processor. The SmartFusion has 3 variants: 
+        A2F060, A2F200, A2F500. The main difference between parts are the amount of 
+        RAM, FLASH as well as programmable logic. In addition, the A2F060 does not
+        include the Ethernet controller peripheral.
+        The A2F200 device includes 256KB of internal FLASH (also called Embedded 
+        Non-volatile Memory, ENVM) and 64KB of internal SRAM. 
+        The device has various peripherals such as UART, I2C, SPI, Ethernet MAC, ADC or 
+        DAC as well as the FPGA fabric. 
+        The kit features an OLED graphical display and UART0 is accessible via the 
+        on-board USB to UART converter. The kit also includes a serial flash, the Atmel 
+        AT25DF641 part (8MB memory). 
+        The FPGA fabric uses a non-volatile technology thus removing the 
+        need of additional flash memory for storing the FPGA programming matrix.
+      </para>
+
+      <para>
+        The eCos port targets standalone ROM application. The eCos device drivers include
+        support for the I2C and SPI buses as well as UART and Ethernet Controller. No 
+        device driver is currently available for the ADC/DAC or the In-Application 
+        Programming feature that allows the application to re-program the FLASH or the 
+        FPGA fabric.
+        The Smartfusion (A2Fxxx) HAL includes a timer test application and the A2F200 evaluation 
+        board flash device package includes a test application for the SPI serial flash.
+      </para>
+     </refsect1>
+     <!-- }}} -->
+
+      <!-- {{{ Tools -->
+     <refsect1 id="a2f200-eval-tools"><title>Tools</title>
+
+     <para>
+        For compilation, the official eCos ARM toolchain is required (gcc version 4.3.2). 
+        For debugging, while the board offers a JTAG interface, the HAL was developed using 
+        the SoftConsole IDE supplied from Actel. SoftConsole is an Eclipse based IDE 
+        installed along with the CodeSourcery ARM compiler / debugger.  The ARM GDB and Sprite 
+        utilities from CodeSourcery are used to debug the target. The target includes an on-board 
+        debugger and is connected to the host via a USB cable. GDB interfaces the  
+        on-board debugger through the Actel flashpro driver. Detailed example of a debugging 
+        session is described later in this chapter.
+      </para>
+
+     </refsect1>
+     <!-- }}} -->
+     </refentry>
+     
+
+     <!-- {{{ HAL port -->
+       <refentry id="a2f200-eval-hal">
+      <refmeta>
+          <refentrytitle>HAL and Device Drivers</refentrytitle>
+      </refmeta>
+
+      <refnamediv>
+          <refname>HAL</refname>
+          <refpurpose>Actel HAL and Device Drivers</refpurpose>
+      </refnamediv>
+
+      <!-- {{{ Clocking -->
+     <refsect1 id="a2f200-eval-hal-clock"><title>Clocking</title>
+
+     <para>
+         The internal clock network of the Smarfusion devices includes a large amount of possible 
+         configuration combination. The network has 3 different input clocks (CLKA, CLKB and CLKC), 
+         each of them can be connected to a different clock source such as the main oscillator, the 
+         RC oscillator, the FPGA fabric or the dedicated single-ended or differential IO. The clock
+         network has an internal PLL and 3 global output clocks (CLKGA, CLKGB and CLKGC). The cortex-M3,
+         digital and analog peripherals clocks are derived either from CLKGA or CLKGC through the
+         NGMUX.
+         Due to the large amount of configuration parameters, it is recommended to use the Actel MSS
+         configuration tool to setup the clock network and let the system boot handle the configuration.
+         However, the eCos HAL includes all the required options to setup the clock network. Note that
+         only a limited subset of combinations have been tested.
+     </para>
+
+     </refsect1>
+     <!-- }}} -->
+
+     <!-- {{{ SPI Bus -->
+     <refsect1 id="a2f200-eval-hal-spi"><title>SPI bus</title>
+
+     <para>
+        The Actel AF2xxx microcontroller family has 2 SPI buses available. Each SPI bus has 
+        a certain number of slave select line (called SPI_x_SSx) that are directly driven by 
+        the SPI controller. 
+        The first SPI bus has 4 slave select lines available (SPI_0_SS0 to SPI_0_SS3) while the 
+        second bus has 8 of them (SPI_1_SS0 to SPI_1_SS7). In addition, the eCos SPI driver allows
+        using the GPIO of the microcontroller as slave select lines which is in some cases required. 
+        In the rest of this chapter, the former case is called SPI controlled slave select while 
+        the later is called GPIO controlled slave select
+     </para>
+
+     <para>
+        NOTE: The SPI_x_SSx microcontroller dedicated pins can be used as GPIO, thus, it is possible 
+        to use SPI_0_SS0 as slave select either in SPI or GPIO controlled mode. This is true for all 
+        SPI_x_SSx pins.
+     </para>
+
+     <para>
+        New SPI devices are instantiated using the following macro:
+     </para>
+     <programlisting width=80>
+        #include <filename class="headerfile">&lt;cyg/io/spi.h&gt;</filename>
+        #include <filename class="headerfile">&lt;cyg/io/spi_a2fxxx.h&gt;</filename>
+
+        #define CYG_DEVS_SPI_CORTEXM_A2FXXX_DEVICE(                    \
+                _name_, _bus_, _csnum_, _csgpio_, _proto_, _clpol_,    \
+                _clpha_, _brate_, _csup_dly_, _csdw_dly_, _trbt_dly_)
+
+
+        _name_     is the name of the SPI device. This will be used to 
+                   reference a data structure of type cyg_spi_device 
+                   which can be passed to the SPI driver API without 
+                   needing a cast.
+        _bus_      is the bus number to which this device is attached 
+                   (1 or 2).
+        _csgpio_   when set to false:
+                    - the device slave select line is controlled by the 
+                      SPI controller.
+                   when set to true:
+                    - the device slave select line is a GPIO of the 
+                      processor controlled by the SPI driver.
+        _csnum_    when _csgpio_ is set to false : 
+                    - is the slave select line used for this device, 
+                      numbered from 0.
+                   when _csgpio_ is set to true : 
+                    - is the GPIO number used to drive the device slave 
+                      select line.
+        _proto_    is the SPI bus protocol:
+                    0 -> Motorola SPI Mode (_clpol_ and _clpha_ are 
+                         valid in this mode)
+                    1 -> National Semiconductor MICROWIRE Mode
+                    2 -> Texas Instruments (TI) Synchronous Serial Mode
+        _clpol_    is the SPI bus clock polarity used by the device 
+                   (valid only for Motorola SPI Protocol).
+        _clpha_    is the SPI bus clock phase used by the device 
+                   (valid only for Motorola SPI Protocol).
+        _brate_    is the SPI bus clock baud rate used by the device, 
+                   measured in Hz.
+        _csup_dly_ is the minimum delay between slave select assert and 
+                   transfer start, measured in microseconds.
+        _csdw_dly_ is the minimum delay between transfer end and slave 
+                   select deassert, measured in microseconds.
+        _trbt_dly_ is the minimum delay between consecutive transfers.
+     </programlisting>
+
+     <para>
+        NOTE: _csup_dly_ and _csdw_dly_ are only valid when GPIOs are configured to drive the 
+        slave select line. When the SPI controller drives the slave select line itself, the user 
+        has no control over the exact timing.
+     </para>
+
+     <para>
+        The Actel Smartfusion board features a SPI serial flash (AT25DF641) attached 
+        to the first SPI bus. The SPI flash is connected to the SPI_0_SS0 line, however, to suit 
+        eCos SPI transaction, the line is configured as a general purpose IO and controlled by the 
+        SPI driver.
+     </para>
+
+     <para>
+        The following section describes how the SPI serial flash is declared. The code is located
+        in devs/fash/cortexm/a2fxxx/a2f200_eval/flash_a2f200_eval.c. The required includes are:
+     </para>
+
+     <programlisting width=80>
+        #include <filename class="headerfile">&lt;cyg/io/spi.h&gt;</filename>
+        #include <filename class="headerfile">&lt;cyg/io/at25dfxxx.h&gt;</filename>
+        #include <filename class="headerfile">&lt;cyg/io/spi_a2fxxx.h&gt;</filename>
+     </programlisting>
+
+     <para>
+        The device is defined to be connected on SPI bus 1, using GPIO 19 for slave select.
+        The Motorola protocol (mode 0) is selected with a bus clock speed of 25MHz.
+     </para>
+
+     <programlisting width=80>
+         CYG_DEVS_SPI_CORTEXM_A2FXXX_DEVICE (
+            at25dfxxx_spi_device, 1, 19, true, A2FXXX_SPI_MOTOROLA, 0, 0, 25000000, 1, 1, 1
+         );
+        
+         _bus_      = 1 
+         _csgpio_   = true -> use GPIO
+         _csgpio_   = 19   -> GPIO19 also SPI_0_SS0
+         _proto_    = Motorola Protocol
+         _clpol_    = 0
+         _clpha_    = 0
+         _brate_    = 25MHz
+         _csup_dly  = 1us
+         _csdw_dly_ = 1us
+         _trbt_dly_ = 1us
+     </programlisting>
+
+     <para>
+        From the default CDL, SPI bus 1 uses the DMA channel 0 for outbound and channel 1 for inbound 
+        transfer. SPI bus 2 uses DMA channel 2 and 3 respectively. The DMA channel number are selected 
+        with:
+     </para>
+
+     <programlisting width=80>
+        CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS1_TX_DMA
+        CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS1_RX_DMA 
+        and
+        CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS2_TX_DMA
+        CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS2_RX_DMA 
+     </programlisting>
+
+     </refsect1>
+     <!-- }}} -->
+
+      <!-- {{{ I2C Bus -->
+     <refsect1 id="a2f200-eval-hal-i2c"><title>I2C bus</title>
+
+     <para>
+        The Actel microcontroller family has 2 I2C buses available and the Smartfusion evaluation kit
+        feature an OLED display connected to the first I2C bus with address 0x3C. 
+        The I2C driver is tested using the OLED display, however, the OLED driver is not part of the 
+        eCos HAL. A new I2C bus is instantiated using the following macro:
+     </para>
+
+     <programlisting width=80>
+        #define CYG_A2FXXX_I2C_BUS(                             \
+                _name_,                                         \
+                _init_fn_,                                      \
+                _base_,                                         \
+                _base_bb_,                                      \
+                _periph_,                                       \
+                _isr_vec_,                                      \
+                _isr_pri_)                                      \
+
+        _name_      is the name of the SPI device.
+        _init_fn_   is the I2C initialization function to be called by the C constructor.
+        _base_      is the base address of the I2C peripheral.
+        _base_bb_   is the Bit-Band base address of the I2C peripheral.
+        _periph_    is the peripheral bit identifier for reset/release operation.
+        _isr_vec_   is the peripheral interrupt vector number.
+        _isr_pri_   is the interrupt priority.
+     </programlisting>
+
+     <para>
+        The following section describes how the I2C bus 0 is declared. The code is located in
+        hal/cortexm/a2fxxx/a2f200_eval/current/src/platform_i2c.c. The required includes are:
+     </para>
+
+     <programlisting width=80>
+        #include <filename class="headerfile">&lt;cyg/io/i2c.h&gt;</filename>
+        #include <filename class="headerfile">&lt;cyg/io/i2c_a2fxxx.h&gt;</filename>
+     </programlisting>
+
+     <para>
+        The first part declares the I2C bus 0 and the second part attached a I2C device with address
+        0x3C to the bus.
+     </para>
+
+     <programlisting width=80>
+         CYG_A2FXXX_I2C_BUS(hal_a2fxxx_i2c0_bus,
+                 a2fxxx_i2c0_init,
+                 CYGHWR_HAL_A2FXXX_I2C0,
+                 CYGHWR_HAL_A2FXXX_I2C0_BB,
+                 CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_I2C0,
+                 CYGNUM_HAL_INTERRUPT_I2C0_0,
+                 0x60);
+
+         _name_     = hal_a2fxxx_i2c0_bus
+         _init_fn_  = a2fxxx_i2c0_init
+         _base_     = CYGHWR_HAL_A2FXXX_I2C0                    // Base address
+         _base_bb_  = CYGHWR_HAL_A2FXXX_I2C0_BB                 // for bit-band access
+         _periph_   = CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_I2C0
+         _isr_vec_  = CYGNUM_HAL_INTERRUPT_I2C0_0
+         _isr_pri_  = 0x60
+
+         CYG_I2C_DEVICE(i2c_a2fxxx_oled,
+                 &#38hal_a2fxxx_i2c0_bus,
+                 0x3c,
+                 0,
+                 CYG_I2C_DEFAULT_DELAY);
+     </programlisting>
+
+     </refsect1>
+     <!-- }}} -->
+
+      <!-- {{{ Ethernet Controller -->
+     <refsect1 id="a2f200-eval-hal-eth"><title>Ethernet Controller</title>
+
+     <para>
+         The Ethernet MAC layer of the Actel device is compliant with the RMII 10/100Mbps specification.
+         The development kit interface the DP83848 PHY from National Semiconductor.
+     </para>
+     <para>
+         NOTE: To use the Ethernet interface of the evaluation kit, the FPGA fabric must be programmed.
+         The Ethernet PHY input clock (50MHz) is connected to an IO only accessible from the fabric. It 
+         is therefore required to route the MAC_CLK from the clock network to the IO (T6).
+     </para>
+     <para>
+         Some of the driver configuration parameters accessible from the CDL file are:
+     </para>
+
+     <variablelist>
+     <varlistentry>
+          <term>CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_CHATTER</term>
+          <listitem>
+          <para>
+           Selecting this option will cause the Ethernet driver to print status
+           messages as various Ethernet operations are undertaken. This is option
+           is designed to help debugging the Ethernet driver.
+          </para>
+          </listitem>
+     </varlistentry>
+
+     <varlistentry>
+          <term>CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_PROMISCUOUS</term>
+          <listitem>
+          <para>
+           Selecting this option will set the Ethernet MAC in promiscuous mode, all Ethernet
+           packets will be delivered to the application layer whether or not destinated to the
+           device.
+          </para>
+          </listitem>
+     </varlistentry>
+
+     <varlistentry>
+          <term>CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_BUFSIZE_TX</term>
+          <listitem>
+          <para>
+           This option specifies the size of the internal transmit buffers used
+           for the Ethernet device.
+          </para>
+          </listitem>
+     </varlistentry>
+
+     <varlistentry>
+          <term>CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_BUFSIZE_RX</term>
+          <listitem>
+          <para>
+           This option specifies the size of the internal receive buffers used
+           for the Ethernet device.
+          </para>
+          </listitem>
+     </varlistentry>
+
+     <varlistentry>
+          <term>CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_TxNUM</term>
+          <listitem>
+          <para>
+           This option specifies the number of output buffer packets
+           to be used for the Ethernet device.
+          </para>
+          </listitem>
+     </varlistentry>
+
+     <varlistentry>
+          <term>CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_RxNUM</term>
+          <listitem>
+          <para>
+           This option specifies the number of input buffer packets
+           to be used for the Ethernet device.
+          </para>
+          </listitem>
+     </varlistentry>
+
+     <varlistentry>
+          <term>CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_STATS</term>
+          <listitem>
+          <para>
+           Selecting this option will cause the Ethernet driver to accumulate statistics 
+           provided from the MAC layer.
+          </para>
+          </listitem>
+     </varlistentry>
+     </variablelist>
+
+     </refsect1>
+     <!-- }}} -->
+
+      <!-- {{{ Serial -->
+     <refsect1 id="a2f200-eval-hal-serial"><title>Serial</title>
+
+     <para>
+         The Actel A2Fxxx uses the 16x5x generic serial device driver. The driver is instantiaced through 
+         the CYGPKG_IO_SERIAL_CORTEXM_A2FXXX serial package.
+     </para>
+
+     </refsect1>
+     <!-- }}} -->
+
+      <!-- {{{ DMA -->
+     <refsect1 id="a2f200-eval-hal-dma"><title>DMA</title>
+
+     <para>
+         The eCos HAL offers some basics routines to configure and use the 8 DMA channels
+         available in the Smartfusion chips. It must be noted that all channels are sharing 
+         the same interrupt. The current implementation limits the transfer size to byte 
+         tranfer ( field TRANSFER_SIZE from the CHANNEL_x_CONTROL register ).
+         Currently only the SPI driver makes use of the DMA interface.
+     </para>
+
+     <para>
+         DMA channels are registered / released with <literal>a2fxxx_dma_ch_attach</literal> and 
+         <literal>a2fxxx_dma_ch_detach</literal> respectively:
+     </para>
+
+     <programlisting width=80>
+     cyg_uint32
+     a2fxxx_dma_ch_attach(cyg_uint8 ch, cyg_ISR_t *isr, cyg_DSR_t *dsr, cyg_addrword_t data)
+
+     ch         specify the DMA channel numbered from 0.
+     isr        specify the interrupt ISR to call for this channel.
+     dsr        specify the interrupt DSR to call for this channel.
+     data       data argument passed to the ISR and DSR routine.
+     </programlisting>
+
+     <programlisting width=80>
+     void
+     a2fxxx_dma_ch_detach (cyg_uint8 ch)
+
+     ch         specify the DMA channel number from 0 to 7
+     </programlisting>
+
+
+     <para>
+         DMA channels are configured with <literal>a2fxxx_dma_ch_setup</literal> :
+     </para>
+
+     <programlisting width=80>
+     cyg_uint32
+     a2fxxx_dma_ch_setup(cyg_uint8 ch, cyg_uint8 type, cyg_bool outbound, 
+           cyg_uint8 src_incr, cyg_uint8 dst_incr, cyg_bool pri, cyg_uint8 wr_adj)
+
+     ch         is the DMA channel numbered from 0.
+     type       is the transfer type to be performed. For valid
+                values, check CYGHWR_HAL_A2FXXX_DMA_XFER(_x) in var_io.h.
+     outbound   set to true for transfer out of memory, false for transfer 
+                to memory
+     src_incr   is the memory address increment step for the source. Valid
+                values are 0, 1, 2 and 4 byte(s). 0 can be used for DMA
+                transfer from peripheral FIFO for instance.
+     dst_incr   is the memory address increment step for the destination.
+                Valid values are 0, 1, 2 and 4 byte(s). 0 can be used for 
+                DMA transfer to peripheral FIFO for instance.
+     pri        is the DMA channel priority (true = high , false = low)
+     wr_adj     indicates the number of FCLK periods which the PDMA must wait 
+                after completion of a read or write access to a peripheral
+                before evaluating the out-of-band status signals from that 
+                peripheral for another transfer.
+     </programlisting>
+
+     <para>
+         DMA transfer are initiated using <literal>a2fxxx_dma_xfer</literal> :
+     </para>
+
+     <programlisting width=80>
+     cyg_uint32
+     a2fxxx_dma_xfer (cyg_uint8 ch, cyg_bool polled, cyg_uint32 len, cyg_uint8 *src, 
+                          cyg_uint8 *dst)
+
+     ch         is the DMA channel numbered from 0.
+     polled     set to true to use the DMA channel in polling mode ( no
+                end of tranfer interrupt are raised ).
+     len        select the length of the transfer ( in number of byte
+                transfered ).
+     src        is the start address from which data is to be read during 
+                the next DMA transfer cycle.
+     dst        is the start address from which data is to be written during 
+                the next DMA transfer cycle.
+     </programlisting>
+
+     <para>
+         DMA interrupts are cleared with <literal>a2fxxx_dma_clear_interrupt</literal> and
+         status of the transaction is retreived with <literal>a2fxxx_dma_get_comp_flag</literal> :
+     </para>
+
+     <programlisting width=80>
+     void
+     a2fxxx_dma_clear_interrupt (cyg_uint8 ch)
+
+     cyg_uint8 
+     a2fxxx_dma_get_comp_flag (cyg_uint8 ch)
+
+     ch         is the DMA channel numbered from 0.
+     </programlisting>
+
+     </refsect1>
+     <!-- }}} -->
+
+     </refentry>
+     <!-- }}} -->
+
+
+     <!-- {{{ Configuration -->
+     <refentry id="a2f200-eval-conf">
+     <refmeta>
+         <refentrytitle>Configuration</refentrytitle>
+     </refmeta>
+     <refnamediv>
+         <refname>Configuration</refname>
+         <refpurpose>Configure, compile and debug the application</refpurpose>
+     </refnamediv>
+
+     <refsect1 id="a2f200-eval-conf-ov">
+     <title><!-- <index></index> -->Overview</title>
+     <para>
+        For compilation of the application, the official eCos ARM toolchain is required 
+        (gcc version 4.3.2). 
+        For debugging, it is needed to install the FlashPro utility from Actel as well 
+        as SoftConsole. SoftConsole is an Eclipse based IDE from Microsemi that installs  
+        along with the CodeSourcery ARM toolchain. Both are freely available and require 
+        a Windows OS based host workstation.
+        To use some peripherals such as the Ethernet controller, the FPGA fabric must be
+        configured to route the Ethernet PHY clock from the MAC_CLK. It is recommended to
+        restore the factory image provided from Actel as a starting point in case the user  
+        has already experimented with the fabric.
+     </para>
+     </refsect1>
+     <!-- }}} -->
+
+     <refsect1 id="a2f200-eval-conf-build">
+     <title><!-- <index></index> -->Building the application</title>
+
+     <para>
+         The steps needed to build the HAL library for the Smartfusion evaluation board are:
+     </para>
+     <screen>
+         $ mkdir a2f200_eval
+         $ cd a2f200_eval
+         $ ecosconfig new smartfusion kernel
+         $ ecosconfig resolve
+         $ ecosconfig tree
+         $ make
+     </screen>
+     <para>
+         At the end of the build the <filename
+         class="directory">install/lib</filename> subdirectory should contain the library and linker script and the <filename
+         class="directory">install/include</filename> subdirectory the necessary includes to compile the application.
+     </para>
+
+     <para>
+         The differents startup type available for this platforme are:
+     </para>
+
+     <informaltable frame="all">
+       <tgroup cols="2" colsep="1" rowsep="1" align="left">
+         <thead>
+           <row>
+             <entry>Configuration (HAL_PLF_STARTUP_TYPE)</entry>
+             <entry>Description</entry>
+           </row>
+         </thead>
+         <tbody>
+           <row>
+             <entry>ROM</entry>
+             <entry>Application running from the board's internal flash, LMA = 0x60000000 and VMA = 0x60000000</entry>
+           </row>
+           <row>
+             <entry>SRAM</entry>
+             <entry>Application running from the board's internal RAM, LMA = 0x20000000 and VMA = 0x20000000</entry>
+           </row>
+           <row>
+             <entry>ROM_SOFTCONSOLE</entry>
+             <entry>Application running from the board's internal flash, LMA = 0x60000000 and VMA = 0x00000000</entry>
+           </row>
+         </tbody>
+       </tgroup>
+     </informaltable>
+
+     </refsect1>
+     <!-- }}} -->
+
+     <refsect1 id="a2f200-eval-conf-sys">
+     <title><!-- <index></index> -->System Boot</title>
+
+     <para>
+         The Smartfusion devices boot process is not entirely controlled by the user. The 
+         Embedded Non-volatile Memory contains spare pages that are reserved to store 
+         specific data such as the factory boot code, the manufacturing parameters, the 
+         system boot code or other data such as the Analog block or MSS configuration.
+     </para>
+
+     <para>
+         As described in the device user manual, the device first boots from factory boot
+         code before jumping to the system boot and eventually giving the hand to the user 
+         code, in this case, the eCos ROM application.
+     </para>
+
+     <para>
+         The Actel MSS configuration tool can be used to alter the system boot and the 
+         configuration pages. The ENVM spare pages can then be re-programmed using the 
+         Actel FlashPro utility. The FlashPro utility can also be used to program the 
+         FPGA fabric if required.
+     </para>
+
+     <informaltable frame="all">
+       <tgroup cols="2" colsep="1" rowsep="1" align="left">
+         <thead>
+           <row>
+             <entry>Spare page content</entry>
+             <entry>Address</entry>
+           </row>
+         </thead>
+         <tbody>
+           <row>
+             <entry>Manufacturing parameters</entry>
+             <entry>0x60080000</entry>
+           </row>
+           <row>
+             <entry>Factory boot</entry>
+             <entry>0x60080400</entry>
+           </row>
+           <row>
+             <entry>System Boot</entry>
+             <entry>0x60080800</entry>
+           </row>
+           <row>
+             <entry>Analog block configuration</entry>
+             <entry>0x60081600</entry>
+           </row>
+           <row>
+             <entry>MSS configuration</entry>
+             <entry>0x60081E80</entry>
+           </row>
+         </tbody>
+       </tgroup>
+     </informaltable>
+
+     </refsect1>
+     <!-- }}} -->
+
+     <refsect1 id="a2f200-eval-conf-dbg">
+     <title><!-- <index></index> -->Debugging from console</title>
+
+     <para>
+         Loading of the application to internal FLASH or RAM of the target is done either 
+         using the SoftConsole IDE supplied from Actel or GDB from command line. The later
+         case is described in this paragraph.
+     </para>
+
+     <para>
+         To debug ROM based application, while configuring eCos, select the ROM_SOFTCONSOLE 
+         startup type. The ROM_SOFTCONSOLE startup type is equivalent to a ROM startup but 
+         while the application is loaded at address 0x60000000 (FLASH), it runs and is debugged 
+         from address 0x00000000. This is done by setting the load address (LMA) to 0x60000000 
+         and the virtual address (VMA) to 0x00000000 in the eCos memory layout file. In this 
+         example, the timers test application from the eCos Smartfusion HAL is compiled:
+     </para>
+
+     <screen>
+         $ mkdir a2f200_eval
+         $ cd a2f200_eval
+         $ ecosconfig new smartfusion kernel
+           -> Select ROM_SOFTCONSOLE statup type
+         $ ecosconfig resolve
+         $ ecosconfig tree
+         $ make
+         $ make -s tests IGNORE_LINK_ERRORS=y
+     </screen>
+ 
+     <para>
+        Once the application is compiled, from a Windows command interpreter, start the 
+        actel-keepalive utility:
+     </para>
+
+     <screen>
+         c:> start actel-keepalive actel-keepalive
+     </screen>
+
+     <para>
+        The GDB initialisation sequence located in a2fxxx/a2f200_eval/current/host/softconsole_flash_init.txt
+        is an example of initialisation sequence to use for debugging application located in
+        ROM. For RAM based application, the initialisation sequence from 
+        a2fxxx/a2f200_eval/current/host/softconsole_sram_init.txt shall be used.
+        Make sure to replace the path to the debugger toolchain and the eCos repository first. The GDB
+        initialisation sequence without in-line comments is:
+     </para>
+
+     <screen>
+        set arm fallback-mode thumb
+        target remote | "C:/Program Files (x86)/Microsemi/SoftConsole v3.3/Sourcery-G++/b-
+        in/arm-none-eabi-sprite" flashpro:?cpu=Cortex-M3 "C:/wrk/ecos/packages/hal/cortex-
+        m/a2fxxx/a2f200_eval/current/host"
+        set mem inaccessible-by-default off
+        set *0x40006010 = 0x4C6E55FA
+        set *0xE0042000 = 0
+        set *0xE0042008 = 1
+        set *0xE0042040 = 0x00207FFD
+        set *0xE004203C = 0x00000001
+        set *0xE0042030 = *0xE0042030 & 0xFFFFFFF7
+        set *0xE000ED08 = 0x00000000
+        load
+        set $sp = *0x60080000
+        set $pc = *0x60080004 - 1
+     </screen>
+
+     <para>
+         Start the GDB session to debug the timers test example:
+     </para>
+
+     <screen>
+         C:\root\a2f200_eval>arm-none-eabi-gdb install\tests\hal\cortexm\a2fxxx\var\curren-
+         t\tests\timers
+         GNU gdb (Sourcery G++ Lite Sourcery G++ Lite 2010q1-188 + Actel 1.2) 7.0.50.20100-
+         218-cvs
+         Copyright (C) 2010 Free Software Foundation, Inc.
+         License GPLv3+: GNU GPL version 3 or later &lt;http://gnu.org/licenses/gpl.html&gt;
+         This is free software: you are free to change and redistribute it.
+         There is NO WARRANTY, to the extent permitted by law.  Type "show copying"
+         and "show warranty" for details.
+         This GDB was configured as "--host=i686-mingw32 --target=arm-none-eabi".
+         For bug reporting instructions, please see:
+         &lt;https://support.codesourcery.com/GNUToolchain/&gt;...
+         Reading symbols from c:\root\a2f200_eval\install\tests\hal\cortexm\a2fxxx\var\curren-
+         t\tests\timers...done.
+         (gdb)
+     </screen>
+
+     <para>
+        A typical log from the GDB initialisation sequence is shown here:
+     </para>
+
+     <screen>
+        Remote debugging using | "C:/Program Files (x86)/Microsemi/SoftConsole v3.3/Sourc-
+        ery-G++/bin/arm-none-eabi-sprite" flashpro:?cpu=Cortex-M3 "C:/wrk/ecos/packages/h-
+        al/cortexm/a2fxxx/a2f200_eval/current/host"
+        arm-none-eabi-sprite: Using memory map C:/wrk/ecos/packages/hal/cortexm/a2fxxx/a2f-
+        200_eval/current/host/memory-map.xml
+        arm-none-eabi-sprite: Target reset
+        arm-none-eabi-sprite: Transferring memory map (may cause a delay)
+        0x6008051c in ?? ()
+        Loading section .rom_vectors, size 0x8 lma 0x60000000
+        Loading section .ARM.exidx, size 0x10 lma 0x60000008
+        Loading section .text, size 0x3340 lma 0x60000018
+        Loading section .rodata, size 0x4dc lma 0x60003358
+        Loading section .data, size 0x318 lma 0x6000383c
+        arm-none-eabi-sprite: Using host routines for flash programming
+        arm-none-eabi-sprite: Start of flash programming
+        arm-none-eabi-sprite: Comparing flash memory contents of actel-smartfusion-envm @-
+        0x60000000
+        arm-none-eabi-sprite: Program 0x60000000 sector [0x0,+0x80) unchanged
+        arm-none-eabi-sprite: Program 0x60000000 sector [0x80,+0x80) unchanged
+        arm-none-eabi-sprite: Program 0x60000000 sector [0x100,+0x80) unchanged
+        ....
+        arm-none-eabi-sprite: Program 0x60000000 sector [0x3b00,+0x80) unchanged
+        arm-none-eabi-sprite: End of programming
+        Start address 0x18, load size 15180
+        Transfer rate: 8 KB/sec, 62 bytes/write.
+     </screen>
+
+     </refsect1>
+     <!-- }}} -->
+
+   </refentry>
+   <!-- }}} -->
+     
+  </chapter>
+   <!-- }}} -->
+
+</part>
+
+  
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/memory-map.xml b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/memory-map.xml
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/memory-map.xml
@@ -0,0 +1,16 @@
+<board>
+ <properties>
+  <property name="system-v6-m"/>
+ </properties>
+ <memory-map>
+    <memory-device address="0x60000000" size="256k" type="flash" device="actel-smartfusion-envm">
+      <description>Flash</description>
+    </memory-device>
+    <memory-device address="0x00000000" size="256k" type="rom">
+      <description>ROM</description>
+    </memory-device>
+    <memory-device address="0x20000000" size="64k" type="ram">
+      <description>SRAM</description>
+    </memory-device>
+  </memory-map>
+</board>
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/softconsole_flash_init.txt b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/softconsole_flash_init.txt
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/softconsole_flash_init.txt
@@ -0,0 +1,53 @@
+
+# GDB initialization sequence provided from SoftConsole IDE with slight modification
+# for eCos
+
+# [1] Targeting SmartFusion embedded NVM (envm) @ 0x60000000.
+#     Loads at 0x60000000 but runs/debugs at 0x00000000 (i.e. ld LMA=0x60000000, VMA=0x00000000)
+
+# Make sure 16-bit Thumb mode breakpoint requests are always used.
+set arm fallback-mode thumb
+
+# Invoke debug sprite in Cortex-M3 mode
+#
+# PATH to the arm-none-eabi-sprite utility and eCos repository must be
+# updated according to a particular setup
+target remote | "C:/Program Files (x86)/Microsemi/SoftConsole v3.3/Sourcery-G++/bin/arm-none-eabi-sprite" flashpro:?cpu=Cortex-M3 "C:/wrk/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host"
+
+# Don't restrict memory access to just regions defined in linker script
+set mem inaccessible-by-default off
+
+# Disable the watchdog
+set *0x40006010 = 0x4C6E55FA
+
+# Ensure that eSRAM IS NOT mapped to 0x00000000
+# Clear ESRAM_CONFIG system register bit 0 (COM_ESRAMFWREMAP)
+set *0xE0042000 = 0
+# Ensure that eNVM @ 0x60000000 IS mapped to 0x00000000
+# Set ENVM_REMAP_BASE register COM_ENVMREMAPBASE field to 1
+set *0xE0042008 = 1
+
+# Configure external memory controller to access external RAM.
+
+# Program EMC_CONFIG_0_REG
+set *0xE0042040 = 0x00207FFD
+# Program EMC_MUX_CONFIG_REG
+set *0xE004203C = 0x00000001
+# Program SOFT_RESET_REG
+set *0xE0042030 = *0xE0042030 & 0xFFFFFFF7
+
+#set *0xE0042004 = 0x00000001
+
+# Set temporary breakpoint on main (must be h/w BP for eNVM)
+thb cyg_usert_start
+
+# Specify user application vector table (remapped/mirrored address)
+set *0xE000ED08 = 0x00000000
+
+# Load the program
+load
+
+# Ensure chip boot code runs before transferring control to user application
+# Initialize SP & PC from chip boot vector table
+set $sp = *0x60080000
+set $pc = *0x60080004 - 1
\ No newline at end of file
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/softconsole_sram_init.txt b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/softconsole_sram_init.txt
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/softconsole_sram_init.txt
@@ -0,0 +1,42 @@
+
+# GDB initialization sequence provided from SoftConsole IDE with slight modification
+# for eCos
+
+# [1] Targeting SmartFusion embedded SRAM (esram) @ 0x20000000.
+#     Loads and debugs at 0x20000000 (i.e. ld LMA=VMA=0x20000000).
+
+# Make sure 16-bit Thumb mode breakpoint requests are always used.
+set arm fallback-mode thumb
+
+# PATH to the arm-none-eabi-sprite utility and eCos repository must be
+# updated according to a particular setup
+target remote | "C:/Program Files (x86)/Microsemi/SoftConsole v3.3/Sourcery-G++/bin/arm-none-eabi-sprite" flashpro:?cpu=Cortex-M3 "C:/wrk/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host"
+
+# Don't restrict memory access to just regions defined in linker script
+set mem inaccessible-by-default off
+
+# Disable the watchdog
+set *0x40006010 = 0x4C6E55FA
+
+# Configure external memory controller to access external RAM.
+
+# Program EMC_CONFIG_0_REG
+set *0xE0042040 = 0x00207FFD
+# Program EMC_MUX_CONFIG_REG
+set *0xE004203C = 0x00000001
+# Program SOFT_RESET_REG
+set *0xE0042030 = *0xE0042030 & 0xFFFFFFF7
+
+# Set temporary breakpoint on main (must be s/w BP - Cortex-M3 h/w BPs only below 0x20000000)
+thb cyg_usert_start
+
+# Specify user application vector table
+set *0xE000ED08 = 0x20000400
+
+# Load the program
+load
+
+# Ensure chip boot code runs before transferring control to user application
+# Initialize SP & PC from chip boot vector table
+set $sp = *0x60080000
+set $pc = *0x60080004 - 1
\ No newline at end of file
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom.h b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom.h
@@ -0,0 +1,25 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+// Only to get Redboot to compile..
+#define CYGMEM_REGION_ram (CYGMEM_REGION_sram)
+#define CYGMEM_REGION_ram_SIZE (CYGMEM_REGION_sram_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_sram_ATTR)
+
+#define CYGMEM_REGION_flash (0x60000000)
+#define CYGMEM_REGION_flash_SIZE (0x00040000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram_SIZE+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom.ldi b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom.ldi
@@ -0,0 +1,36 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x60000000, LENGTH = 0x00040000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x60000000, LMA_EQ_VMA)
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000400, FOLLOWING (.got))
+    SECTION_data (sram, ALIGN (0x8), FOLLOWING (.sram))
+    SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + 1024*64;
+
+
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.h b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.h
@@ -0,0 +1,25 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+// Only to get Redboot to compile..
+#define CYGMEM_REGION_ram (CYGMEM_REGION_sram)
+#define CYGMEM_REGION_ram_SIZE (CYGMEM_REGION_sram_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_sram_ATTR)
+
+#define CYGMEM_REGION_flash (0x60000000)
+#define CYGMEM_REGION_flash_SIZE (0x00040000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram_SIZE+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.ldi b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.ldi
@@ -0,0 +1,39 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+#define PLF_FOLLOWING(_section_) FOLLOWING_ALIGNED(_section_, 8)
+
+MEMORY
+{
+    sram    : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash   : ORIGIN = 0x60000000, LENGTH = 0x00040000
+    /* flash mirrored to 0x00000000 */
+    flashm  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flashm, 0x00000000, AT (0x60000000))
+    SECTION_text (flashm, ALIGN (0x8), PLF_FOLLOWING (.rom_vectors))
+    SECTION_fini (flashm, ALIGN (0x8), PLF_FOLLOWING (.text))
+    SECTION_rodata (flashm, ALIGN (0x8), PLF_FOLLOWING (.fini))
+    SECTION_rodata1 (flashm, ALIGN (0x8), PLF_FOLLOWING (.rodata))
+    SECTION_fixup (flashm, ALIGN (0x8), PLF_FOLLOWING (.rodata1))
+    SECTION_gcc_except_table (flashm, ALIGN (0x8), PLF_FOLLOWING (.fixup))
+    SECTION_eh_frame (flashm, ALIGN (0x8), PLF_FOLLOWING (.gcc_except_table))
+    SECTION_got (flashm, ALIGN (0x8), PLF_FOLLOWING (.eh_frame))
+    SECTION_sram (sram, 0x20000400, PLF_FOLLOWING (.got))
+    SECTION_data (sram, ALIGN (0x8), PLF_FOLLOWING (.sram))
+    SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + 1024*64;
+
+
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_sram.h b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_sram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_sram.h
@@ -0,0 +1,25 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGMEM_REGION_sram)
+#define CYGMEM_REGION_ram_SIZE (CYGMEM_REGION_sram_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_sram_ATTR)
+
+#define CYGMEM_REGION_flash (0x60000000)
+#define CYGMEM_REGION_flash_SIZE (0x00040000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_sram.ldi b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_sram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_sram.ldi
@@ -0,0 +1,34 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x60000000, LENGTH = 0x00040000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (sram, 0x20000400, LMA_EQ_VMA)
+    SECTION_RELOCS (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (sram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20010000;
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_arch.h b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_arch.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Original:    nickg (STM32 HAL)
+// Date:        2011-04-03
+// Purpose:     Actel Smartfusion A2F200 EVAL board specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_a2f200_eval.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_intr.h b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_intr.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_intr.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Original:    nickg (STM32 HAL)
+// Date:        2011-04-03
+// Purpose:     Actel Smartfusion A2F200 EVAL board specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_a2f200_eval.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_io.h b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_io.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_io.h
@@ -0,0 +1,74 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Original:    nickg (STM32 HAL)
+// Date:        2011-04-03
+// Purpose:     Actel Smartfusion A2F200 EVAL board specific registers
+// Description: 
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_a2f200_eval.h>
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/src/a2f200_eval_misc.c b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/src/a2f200_eval_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/src/a2f200_eval_misc.c
@@ -0,0 +1,160 @@
+/*==========================================================================
+//
+//      a2f200_eval_misc.c
+//
+//      Cortex-M3 A2F200 EVAL HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Original:    nickg (STM32 HAL)
+// Date:        2011-04-03
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_a2fxxx.h>
+#include <pkgconf/hal_cortexm_a2f200_eval.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+#define TEST_IO 0
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables. 
+
+
+__externC void
+hal_system_init( void )
+{
+}
+
+cyg_uint32 led[7] = {
+    CYGHWR_HAL_A2FXXX_GPIO( 24,  OUT, NONE, DISABLE ),
+    CYGHWR_HAL_A2FXXX_GPIO( 25,  OUT, NONE, DISABLE ),
+    CYGHWR_HAL_A2FXXX_GPIO( 26,  OUT, NONE, DISABLE ),
+    CYGHWR_HAL_A2FXXX_GPIO( 27,  OUT, NONE, DISABLE ),
+};
+
+
+//==========================================================================
+
+__externC void
+hal_platform_init( void )
+{
+#if TEST_IO
+   cyg_uint8 i;
+#endif
+
+#if TEST_IO
+   for(i = 0; i < 4; i++)
+   {
+      CYGHWR_HAL_A2FXXX_GPIO_SET( led[i] );
+      CYGHWR_HAL_A2FXXX_GPIO_OUT( led[i], 1);
+   }
+#endif
+
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct
+{
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+#ifdef CYGMEM_REGION_sram              // On-chip SRAM
+    {
+    CYGMEM_REGION_sram, CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE - 1},
+#endif
+#ifdef CYGMEM_REGION_flash             // On-chip flash
+    {
+    CYGMEM_REGION_flash,
+            CYGMEM_REGION_flash + CYGMEM_REGION_flash_SIZE - 1},
+#endif
+    { 0xE0000000, 0x00000000-1 },      // Cortex-M peripherals
+    { 0x40000000, 0x60000000-1 },      // Smartfusion peripherals
+};
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ )
+    {
+        if( (addr >= hal_data_access[i].start) &&
+            (addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+
+//==========================================================================
+// EOF a2f200_eval_misc.c
diff --git a/packages/hal/cortexm/a2fxxx/a2f200_eval/current/src/platform_i2c.c b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/src/platform_i2c.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/src/platform_i2c.c
@@ -0,0 +1,179 @@
+//==========================================================================
+//
+//      platform_i2c.c
+//
+//      Optional I2C support for Cortex-M3 Actel Smartfusion
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors:
+// Date:         2011-04-08
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+
+//=============================================================================
+//                               INCLUDES
+//=============================================================================
+#include <pkgconf/system.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/hal/hal_endian.h>
+#include <cyg/hal/hal_intr.h>
+
+#ifdef CYGPKG_DEVS_I2C_CORTEXM_A2FXXX
+
+#include <cyg/io/i2c.h>
+#include <cyg/io/i2c_a2fxxx.h>
+
+//=============================================================================
+// Setup I2C bus 0
+//
+static void
+a2fxxx_i2c0_init( struct cyg_i2c_bus *bus )
+{
+    cyg_uint32 scl_io = CYGHWR_HAL_A2FXXX_I2C0_SCL;
+    cyg_uint32 sda_io = CYGHWR_HAL_A2FXXX_I2C0_SDA;
+
+    //
+    // We only need to setup the pins here and
+    // leave the I2C driver to take care of the rest.
+    //
+    CYGHWR_HAL_A2FXXX_GPIO_SET( scl_io );
+    CYGHWR_HAL_A2FXXX_GPIO_SET( sda_io );
+
+    a2fxxx_i2c_init( bus );
+}
+
+
+//-----------------------------------------------------------------------------
+// I2C bus 0
+//
+CYG_A2FXXX_I2C_BUS(hal_a2fxxx_i2c0_bus,
+                 &a2fxxx_i2c0_init,
+                 CYGHWR_HAL_A2FXXX_I2C0,       // Base address
+                 CYGHWR_HAL_A2FXXX_I2C0_BB,    // Bit-band base address
+                 CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_I2C0,
+                 CYGNUM_HAL_INTERRUPT_I2C0_0,
+                 CYGNUM_DEVS_I2C_CORTEXM_A2FXXX_I2C0_ISR_PRIORITY);
+
+
+//-----------------------------------------------------------------------------
+// OLED
+//
+CYG_I2C_DEVICE(i2c_a2fxxx_oled,
+               &hal_a2fxxx_i2c0_bus,
+               0x3c,
+               0,
+               CYG_I2C_DEFAULT_DELAY);
+
+
+#define DELAY 1
+
+// Wrapper to OLED driver
+
+externC cyg_uint32
+a2fxxx_oled_write_first( cyg_uint8 byte )
+{
+    cyg_uint32      result;
+
+    cyg_i2c_transaction_begin( &i2c_a2fxxx_oled );
+
+    result = cyg_i2c_transaction_tx( &i2c_a2fxxx_oled,
+                                     true, ( cyg_uint8 * )&byte, 1, false );
+
+#ifdef CYGPKG_KERNEL
+    cyg_thread_delay( DELAY );
+#endif
+
+    return result;
+}
+
+externC cyg_uint32
+a2fxxx_oled_write_byte( cyg_uint8 byte )
+{
+    cyg_uint32      result;
+
+    result = cyg_i2c_transaction_tx( &i2c_a2fxxx_oled,
+                                     false, ( cyg_uint8 * )&byte, 1, false );
+
+#ifdef CYGPKG_KERNEL
+    cyg_thread_delay( DELAY );
+#endif
+
+    return result;
+}
+
+
+externC cyg_uint32
+a2fxxx_oled_write_array( const cyg_uint8 *array, cyg_uint32 count )
+{
+    cyg_uint32      result;
+
+    result = cyg_i2c_transaction_tx( &i2c_a2fxxx_oled,
+                                     false, array, count, false );
+
+    return result;
+}
+
+
+externC cyg_uint32
+a2fxxx_oled_write_final( cyg_uint8 byte )
+{
+    cyg_uint32      result;
+
+    result = cyg_i2c_transaction_tx( &i2c_a2fxxx_oled,
+                                     false, ( cyg_uint8 * )&byte, 1, true );
+#ifdef CYGPKG_KERNEL
+    cyg_thread_delay( DELAY );
+#endif
+
+    cyg_i2c_transaction_end( &i2c_a2fxxx_oled );
+
+    return result;
+}
+
+#endif // #ifdef CYGPKG_DEVS_I2C_CORTEXM_A2FXXX
+
+//-----------------------------------------------------------------------------
+// EOF platform_i2c.c
diff --git a/packages/hal/cortexm/a2fxxx/var/current/ChangeLog b/packages/hal/cortexm/a2fxxx/var/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/var/current/ChangeLog
@@ -0,0 +1,46 @@
+2012-01-04  Christophe Coutand  <ecos@hotmail.co.uk>
+	* src/hal_dma.c:
+	Fix compiler warning, unused variable in a2fxxx_dma_isr().
+
+2011-06-26  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* cdl/hal_cortexm_a2fxxx.cdl:
+	* cdl/hal_cortexm_a2fxxx_irq.cdl:
+	* include/hal_cache.h:
+	* include/hal_diag.h:
+	* include/plf_stub.h:
+	* include/var_arch.h:
+	* include/variant.inc:
+	* include/var_intr.h:
+	* include/var_io.h:
+	* src/hal_diag.c:
+	* src/hal_dma.c:
+	* src/a2fxxx_misc.c:
+	* tests/timers.c:
+	New package -- Actel SmartFusion Cortex-M3 variant HAL.
+	[Bugzilla 1001291]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
+
diff --git a/packages/hal/cortexm/a2fxxx/var/current/cdl/hal_cortexm_a2fxxx.cdl b/packages/hal/cortexm/a2fxxx/var/current/cdl/hal_cortexm_a2fxxx.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/var/current/cdl/hal_cortexm_a2fxxx.cdl
@@ -0,0 +1,732 @@
+##==========================================================================
+##
+##      hal_cortexm_a2f.cdl
+##
+##      Cortex-M A2F variant HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ccoutand
+## Contributors: 
+## Date:         2011-02-03
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_A2FXXX {
+    display       "Actel Smartfusion A2Fxxx Variant (Cortex-M3)"
+    parent        CYGPKG_HAL_CORTEXM
+    hardware
+    include_dir   cyg/hal
+    define_header hal_cortexm_a2fxxx.h
+    description   "
+        This package provides generic support for the Actel Smarfusiom Cortex-M3 
+        based microcontroller family. It is also necessary to select a platform 
+        HAL package."
+
+    compile       hal_diag.c a2fxxx_misc.c hal_dma.c
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+    requires      { CYGHWR_HAL_CORTEXM == "M3" }
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+
+    cdl_option CYGHWR_HAL_CORTEXM_A2FXXX {
+        display          "Actel Smartfusion A2F variant in use"
+        flavor           data
+        default_value    { "A2F200" }
+        legal_values     { "A2F060" "A2F200" "A2F500" }
+        description      "The Smartfusion has several variants, the main differences
+                          being in the size of on-chip FLASH and SRAM and numbers of
+                          some analog peripherals. This option allows the platform HAL 
+                          to select the specific microcontroller fitted."
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
+        display         "CPU priority levels"
+        flavor          data
+        calculated      5
+        description     "This option defines the number of bits used to
+                         encode the exception priority levels that this
+                         variant of the Cortex-M CPU implements."
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK {
+        display       "Clocking"
+        description   "Select this option to configure the internal 
+                 clock network of the device. Due to large amount of possible combination of 
+                 clock configuration, it is recommended to use the Actel MSS configuration tool
+                 and let the system boot handle the clock settings. Some of the requirement for
+                 setting the clock network of the device are : The On-chip Oscillator 
+                 clock frequency is fixed to 100 MHz and cannot be changed. The Main Crystal
+                 Oscillator clock frequency must be between 1.5 MHz and 20 MHz when the PLL is
+                 used or between 32 KHz and 20 MHz when the PLL is bypassed. The Main Crystal 
+                 Oscillator (RC network configuration) clock frequency must be between 1.5MHz 
+                 and 4 MHz when the PLL is used or between 32 KHz and 4 MHz when the PLL is 
+                 bypassed. For all other sources, the source clock frequency must be between 
+                 1.5 MHz and 176MHz when the PLL is used or between 32 KHz and 250 MHz when the 
+                 PLL is bypassed."
+        flavor         bool
+        default_value  0
+
+        cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKIN {
+            display       "Input clock selection"
+            flavor         none
+            description   "Configure the input clocks of the device."
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKA {
+                display       "Clock A configuration"
+                flavor         bool
+                default_value { CYGHWR_HAL_CORTEXM_A2FXXX_PLL }
+                description   "Configure the clock A input of the device."
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC {
+                    display        "Clock A source"
+                    flavor          data
+                    legal_values    { "AUIN" "AUIP" "ADIP" "GLAINT" "RCOSC" "MOSC" }
+                    default_value   { "RCOSC" }
+                    description   "
+                        Select the clock A source. Valid choices are the main oscillator,
+                        the RC oscillator, the FPGA fabric or the dedicated single-ended or 
+                        differential IOs."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_FREQ {
+                    display         "Clock A frequency in Hz"
+                    flavor           data
+                    legal_values     { 1500000 to 176000000 }
+                    default_value    { CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC == "RCOSC" ? 100000000 : 20000000 }
+                    description   "
+                        Select the clock A source frequency in Hz. Additional restrictions 
+                        of the frequency range apply giving the clock source. It is left to 
+                        the user to take care of not exceeding the limits provided by the 
+                        device user manual."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKB {
+                display       "Clock B configuration"
+                flavor         bool
+                description   "Configure the clock B input of the device."
+                default_value  0
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC {
+                    display       "Clock B source"
+                    flavor         data
+                    legal_values   { "BUIN" "BUIP" "BDIP" "GLBINT" "RCOSC" "MOSC" }
+                    default_value  { "MOSC" }
+                    description   "
+                        Select the clock B source. Valid choices are the main oscillator,
+                        the RC oscillator, the FPGA fabric or the dedicated single-ended or 
+                        differential IOs."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_FREQ {
+                    display         "Clock B frequency in Hz"
+                    flavor           data
+                    legal_values     { 32000 to 350000000 }
+                    default_value    { CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC == "RCOSC" ? 100000000 : 20000000 }
+                    description   "
+                        Select the clock B source frequency in Hz. Additional restrictions 
+                        of the frequency range apply giving the clock source. It is left to 
+                        the user to take care of not exceeding the limits provided by the 
+                        device user manual."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKC {
+                display       "Clock C configuration"
+                flavor         bool
+                description   "Configure the clock C input of the device."
+                default_value  0
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC {
+                    display       "Clock C source"
+                    flavor        data
+                    legal_values  { "CUIN" "CUIP" "CDIP" "GLCINT" "RCOSC" "32KOSC"}
+                    default_value { "RCOSC" }
+                    description   "
+                        Select the clock C source. Valid choices are the main oscillator,
+                        the RC oscillator, the FPGA fabric or the dedicated single-ended or 
+                        differential IOs."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_FREQ {
+                    display         "Clock C frequency in Hz"
+                    flavor          data
+                    legal_values    { 32000 to 350000000 }
+                    default_value   { CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC == "RCOSC" ? 100000000 : 20000000 }
+                    description   "
+                        Select the clock B source frequency in Hz. Additional restrictions 
+                        of the frequency range apply giving the clock source. It is left to 
+                        the user to take care of not exceeding the limits provided by the 
+                        device user manual."
+                }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_PLL {
+            display       "PLL configuration"
+            flavor         bool
+            requires       CYGHWR_HAL_CORTEXM_A2FXXX_CLKA
+            description   "Configure the device PLL."
+            default_value  1
+
+            cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PLL_MULT {
+                display       "PLL Multiplier"
+                flavor         data
+                legal_values  { 1 to 128 }
+                default_value { 1 }
+                description   "
+                    Select the PLL multiplier coefficient (m)."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PLL_DIV {
+                display       "PLL Divider"
+                flavor         data
+                legal_values  { 1 to 128 }
+                default_value { 1 }
+                description   "
+                    Select the PLL divider coefficient (n)."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ {
+                display       "PLL output frequency"
+                flavor        data
+                calculated    { CYGHWR_HAL_CORTEXM_A2FXXX_PLL ? ( CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_FREQ * CYGHWR_HAL_CORTEXM_A2FXXX_PLL_MULT ) / CYGHWR_HAL_CORTEXM_A2FXXX_PLL_DIV : 0 }
+                legal_values  { 22000000 to 350000000 }
+                description   "
+                    Computed PLL output frequency."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FB_DELAY {
+                display       "PLL Feedback delay"
+                flavor        data
+                legal_values  { 0 to 15 }
+                default_value { 0 }
+                description   "
+                    Select the PLL Feedback loop delay. Field FBDLY from user manual. 
+                    Value from 535 to 5560ns."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PLL_XDELAY {
+                display       "PLL Additional delay"
+                flavor        bool
+                default_value 0
+                description   "
+                    Add 2ns additional delay on PLL feedback loop."
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKOUT {
+            display       "Global clock output configuration"
+            flavor         none
+            description   "Configure the Global clocks of the device."
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA {
+                display       "Global clock A configuration"
+                flavor         bool
+                default_value { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT == "CLKGA" }
+                description   "Configure the Global clock A of the device."
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC {
+                    display         "Global clock A source"
+                    flavor           data
+                    legal_values    { "CLKA" "PLL_VCO0" "PLL_VCO90" "PLL_VCO180" "PLL_VCO270" "PLL_VCO0_DL" }
+                    default_value   { "PLL_VCO0" }
+                    requires        { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "CLKA" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKA : CYGHWR_HAL_CORTEXM_A2FXXX_PLL }
+                    description   "
+                        Select the Global clock A source. Valid choices are the PLL output (with different phases)
+                        or the clock A input."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV {
+                    display        "Global clock A divider"
+                    flavor          data
+                    legal_values   { 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 
+                                     10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 16 17 18 19 
+                                     20 21 22 23 24 25 26 27 28 29 30 31 32 }
+                    default_value  { 1 }
+                    description   "
+                        Select the Global clock A divider value."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV10 {
+                    display        "Global clock A divider * 10"
+                    flavor          data
+                    calculated     { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV * 10 }
+                    description   "
+                        Computed Global clock A divider value multiplied by 10."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DELAY {
+                    display        "Global clock A delay line"
+                    flavor          data
+                    legal_values   { 0 to 15 }
+                    default_value  { 0 }
+                    description   "
+                        Select the Global clock A delay value."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_FREQ {
+                    display        "Global clock A Frequency"
+                    flavor          data
+                    legal_values   { 1 to 100000000 }
+                    calculated     { ( CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "PLL_VCO0" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "PLL_VCO90" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "PLL_VCO180" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "PLL_VCO270" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "PLL_VCO0_DL" ) ? ( ( CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV10 ) : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "CLKA" ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV10 ) : 0 }
+                    description   "
+                        Computed Global clock A frequency."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB {
+                display      "Global clock B configuration"
+                flavor        bool
+                description  "Configure the Global clock B of the device."
+                default_value { CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK && CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO != 1 }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC {
+                    display       "Global clock B source"
+                    flavor         data
+                    legal_values  { "CLKB" "CLKGA" "PLL_VCO0" "PLL_VCO90" "PLL_VCO180" "PLL_VCO270" "PLL_VCO0_DL" }
+                    default_value { "PLL_VCO0" }
+                    requires      { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "CLKB" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKB : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "CLKGA" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA : CYGHWR_HAL_CORTEXM_A2FXXX_PLL }
+                    description   "
+                        Select the Global clock B source. Valid choices are the PLL output (with different phases),
+                        the clock B input or the global clock A output."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV {
+                    display       "Global clock B divider"
+                    flavor         data
+                    legal_values   { 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 
+                                     10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 16 17 18 19 
+                                     20 21 22 23 24 25 26 27 28 29 30 31 32 }
+                    default_value { 1 }
+                    description   "
+                        Select the Global clock B divider value."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV10 {
+                    display        "Global clock B divider * 10"
+                    flavor          data
+                    calculated     { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV * 10 }
+                    description   "
+                        Computed Global clock B divider value multiplied by 10."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DELAY {
+                    display       "Global clock B delay line"
+                    flavor         data
+                    legal_values  { 0 to 15 }
+                    default_value { 0 }
+                    description   "
+                        Select the Global clock B delay value."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_FREQ {
+                    display        "Global clock B Frequency"
+                    flavor          data
+                    calculated     { ( CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "PLL_VCO0" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "PLL_VCO90" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "PLL_VCO180" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "PLL_VCO270" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "PLL_VCO0_DL" ) ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ*10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV10 ) : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "CLKB" ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV10 ) : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "CLKGA" ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV10 ) : 0 }
+                    description   "
+                        Computed Global clock B frequency."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC {
+                display       "Global clock C configuration"
+                flavor        bool
+                description   "Configure the Global clock C of the device."
+                default_value { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT == "CLKGC" }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC {
+                    display       "Global clock C source"
+                    flavor         data
+                    legal_values  { "CLKC" "CLKGA" "PLL_VCO0" "PLL_VCO90" "PLL_VCO180" "PLL_VCO270" "PLL_VCO0_DL" }
+                    default_value { "PLL_VCO0" }
+                    requires      { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "CLKC" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKC : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "CLKGA" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA : CYGHWR_HAL_CORTEXM_A2FXXX_PLL }
+                    description   "
+                        Select the Global clock C source. Valid choices are the PLL output (with different phases),
+                        the clock C input or the global clock A output."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV {
+                    display       "Global clock C divider"
+                    flavor         data
+                    legal_values   { 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 
+                                     10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 16 17 18 19 
+                                     20 21 22 23 24 25 26 27 28 29 30 31 32 }
+                    default_value { 1 }
+                    description   "
+                        Select the Global clock C divider value."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV10 {
+                    display        "Global clock C divider * 10"
+                    flavor          data
+                    calculated     { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV * 10 }
+                    description    "
+                        Computed Global clock C divider value multiplied by 10."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DELAY {
+                    display       "Global clock C delay line"
+                    flavor         data
+                    legal_values  { 0 to 15 }
+                    default_value { 0 }
+                    description   "
+                        Select the Global clock C delay value."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_FREQ {
+                    display       "Global clock C Frequency"
+                    flavor         data
+                    calculated     { ( CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "PLL_VCO0" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "PLL_VCO90" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "PLL_VCO180" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "PLL_VCO270" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "PLL_VCO0_DL" ) ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ*10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV10 ) : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "CLKC" ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV10 ) : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "CLKGA" ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV10 ) : 0 }
+                    description   "
+                        Computed Global clock C frequency."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_MSS_FPGA {
+                display      "MSS / FPGA Clock configuration"
+                flavor        none
+                description  "Configure the MSS and Fabric master clock."
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT {
+                    display       "NGMUX output clock"
+                    flavor         data
+                    legal_values  { "CLKGA" "CLKGC" }
+                    default_value { "CLKGA" }
+                    requires      { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT == "CLKGA" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA : ( CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC && CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC != "CLKGA" ) }
+                    description   "
+                        Select the NGMUX output clock. Valid choices are the Global Clock A or C."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ {
+                    display       "NGMUX output clock frequency"
+                    flavor        data
+                    legal_values  { 1 to 100000000 }
+                    calculated    { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT == "CLKGA" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_FREQ : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_FREQ }
+                    description   "
+                        Computed NGMUX output clock frequency."
+                }
+
+                cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK {
+                    display       "Fabric clock configuration"
+                    flavor         bool
+                    default_value  0
+                    description   "Set the Fabric master clock. The Fabric frequency ration
+                        specifies which clock source to be used. For a ration of 1, the fabric 
+                        and MSS clock source are the same. For a ration of 2 of 4, the fabric 
+                        clock source is CLKGB and the ration between CLKGB and the MSS clock must 
+                        be configured by the user to be equal to 2 or 4."
+
+                    cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO {
+                        display       "Fabric to MSS clock ratio"
+                        flavor        data
+                        legal_values  { 1 2 4 }
+                        requires      { CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO != 1 ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB : 1 }
+                        requires      { CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO != 1 ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_FREQ == CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ / CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO : 1 }
+                        default_value { 1 }
+                        description   "
+                            Select the Fabric to MSS clock ratio."
+                    }
+
+                    cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_FREQ {
+                        display       "Fabric clock Frequency"
+                        flavor         data
+                        calculated    { ( CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK && CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO != 1 ) ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_FREQ : ( CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK && CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO == 1 ) ?  CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ  : 0 }
+                        description   "
+                            Computed Fabric clock frequency."
+                    }
+                }
+
+                cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_MSS_CLK {
+                    display       "MSS clock configuration"
+                    flavor         none
+                    description   "Configure the MSS master clock."
+
+                    cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_MSS_CLK_DELAY {
+                        display       "MSS clock delay"
+                        flavor         data
+                        legal_values  { 0 to 15 }
+                        default_value { 0 }
+                        description   "
+                            Select the MSS clock delay. Field FBDLY. Value from 535 to 5560ns."
+                    }
+
+                    cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_ACE_CLK {
+                        display       "ACE clock configuration"
+                        flavor         bool
+                        default_value  0
+                        description   "Configure the ACE master clock."
+
+                        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_ACLK_DIV {
+                           display       "ACE clock divider"
+                            flavor        data
+                            legal_values  { 1 2 4 }
+                            default_value { 1 }
+                            description   "
+                                Select the ACE clock divider value."
+                        }
+
+                        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_ACLK_FREQ {
+                            display       "ACE clock Frequency"
+                            flavor         data
+                            calculated    { CYGHWR_HAL_CORTEXM_A2FXXX_ACE_CLK ? CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ / CYGHWR_HAL_CORTEXM_A2FXXX_ACLK_DIV : 0 }
+                            description   "
+                                Computed ACE clock frequency."
+                        }
+                    }
+
+                    cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_CLK {
+                        display      "PCLK0 clock configuration"
+                        flavor        none
+                        description  "Configure the PCLK0 clock."
+
+                        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_DIV {
+                            display       "PCLK0 clock divider"
+                            flavor        data
+                            legal_values  { 1 2 4 }
+                            default_value { 1 }
+                            description   "
+                                Select PCLK0 clock divider value."
+                        }
+
+                        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_FREQ {
+                            display       "PCLK0 clock Frequency"
+                            flavor         data
+                            calculated    { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ ? CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ / CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_DIV : 0 }
+                            description   "
+                                Computed PCLK0 clock frequency."
+                        }
+                    }
+
+                    cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_CLK {
+                        display       "PCLK1 clock configuration"
+                        flavor         none
+                        description   "Configure the PCLK1 clock."
+                        
+                        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_DIV {
+                            display       "PCLK1 clock divider"
+                            flavor         data
+                            legal_values  { 1 2 4 }
+                            default_value { 1 }
+                            description   "
+                                Select PCLK1 clock divider value."
+                        }
+
+                        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_FREQ {
+                            display       "PCLK1 clock Frequency"
+                            flavor         data
+                            calculated    { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ ? CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ / CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_DIV : 0 }
+                            description   "
+                                Computed PCLK1 clock frequency."
+                        }
+                    }
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_MAC_CLK {
+                display       "Ethernet MAC clock configuration"
+                flavor         bool
+                default_value  0
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_MAC_SRC {
+                    display       "Ethernet MAC clock source"
+                    flavor         data
+                    legal_values  { "CLKGC" "EXTERNAL" }
+                    default_value { "CLKGC" }
+                    requires      { CYGHWR_HAL_CORTEXM_A2FXXX_MAC_SRC == "CLKGC" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC  : 1 }
+                    description   "
+                        Select the Ethernet MAC clock source."
+                }
+            }
+        }
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_DMA {
+        display       "DMA"
+        flavor        none
+        description   "
+            DMA controller configuration."
+
+        cdl_option CYGDBG_HAL_CORTEXM_A2FXXX_DMA_TRACE {
+            display       "Display status messages during DMA operations"
+            flavor        bool
+            default_value 0
+            description   "
+               Selecting this option will cause the DMA driver to print status
+               messages as various DMA operations are undertaken."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_CORTEXM_A2FXXX_CLOCK_CHATTER {
+        display        "Trace clock network configuration."
+        default_value   1
+        flavor          bool
+        description     "
+            Enable debug tracing of the clock configuration."
+    }
+
+    cdl_option CYGSEM_HAL_CORTEXM_A2FXXX_DEFINES_IDLE_THREAD_ACTION {
+        display        "Override IDLE thread action"
+        default_value   1
+        flavor          bool
+        description     "
+            Override IDLE thread action defined by the architectural HAL.
+            The option must be active when running the application from a
+            debugger. The 'WFI' IDLE instruction defined in the architectural
+            HAL leads to software crash when application runs from a debugger."
+    }
+
+    cdl_component  CYGPKG_HAL_CORTEXM_A2FXXX_IO {
+        display         "IO configuration"
+        flavor          bool
+        default_value   0
+        description   "
+                Overwrite the default IO configuration
+        "
+
+        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_IO_WEST_BANK {
+            display       "IO west bank buffer type"
+            legal_values  { "LVCMOS_3V3" "LVCMOS_2V5" "LVCMOS_1V8" "LVCMOS_1V5" }
+            default_value { "LVCMOS_3V3" }
+            flavor        data
+            description   "
+                Select the device west bank IO buffer type to be used.
+            "
+        }
+        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_IO_EAST_BANK {
+            display       "IO east bank buffer type"
+            legal_values  { "LVCMOS_3V3" "LVCMOS_2V5" "LVCMOS_1V8" "LVCMOS_1V5" }
+            default_value { "LVCMOS_3V3" }
+            flavor        data
+            description   "
+                Select the device west bank IO buffer type to be used.
+            "
+        }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR {
+        display    "Variant IRQ priority defaults"
+        no_define
+        flavor     none
+        parent     CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME
+        description "
+            Interrupt priorities defined by the variant HAL"
+        script     hal_cortexm_a2fxxx_irq.cdl
+    }
+
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+        no_define
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+        }
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR
+            description   "The period defined here is something of a fake, it is expressed
+                           in terms of a notional 1MHz clock. The value actually installed
+                           in the hardware is calculated from the current settings of the
+                           clock generation hardware."
+        }
+    }
+
+    cdl_interface CYGINT_HAL_A2FXXX_UART0 {
+        display     "Platform has UART0 serial port"
+        description "The platform has a socket on UART0."
+    }
+
+    cdl_interface CYGINT_HAL_A2FXXX_UART1 {
+        display     "Platform has UART1 serial port"
+        description "The platform has a socket on UART1."
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_A2FXXX_OPTIONS {
+        display "Build options"
+        flavor  none
+        description   "
+        Package specific build options including control over
+        compiler flags used only in building this package."
+
+        cdl_option CYGPKG_HAL_CORTEXM_A2FXXX_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the A2F variant HAL package. These flags are used
+                in addition to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_CORTEXM_A2FXXX_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the A2F variant HAL package. These flags are removed from
+                the set of global flags if present."
+        }
+    }
+
+    cdl_option CYGPKG_HAL_CORTEXM_A2FXXX_TESTS {
+        display "A2F tests"
+        active_if      CYGPKG_KERNEL
+        flavor  data
+        no_define
+        calculated { "tests/timers" }
+        description   "
+            This option specifies the set of tests for the A2F HAL."
+    }
+
+}
\ No newline at end of file
diff --git a/packages/hal/cortexm/a2fxxx/var/current/cdl/hal_cortexm_a2fxxx_irq.cdl b/packages/hal/cortexm/a2fxxx/var/current/cdl/hal_cortexm_a2fxxx_irq.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/var/current/cdl/hal_cortexm_a2fxxx_irq.cdl
@@ -0,0 +1,150 @@
+##==========================================================================
+##
+##      hal_cortexm_a2fxxx_irq.cdl
+##
+##      Cortex-M A2F configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2012 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ccoutand
+## Date:         2012-02-20
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+    cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
+        display       "Clock interrupt ISR priority"
+        flavor         data
+        calculated     0xF0
+        description   "Set clock ISR priority to lowest priority."
+    }
+
+
+    cdl_option CYGNUM_HAL_CORTEXM_A2FXXX_DMA_ISR_PRIORITY {
+        display       "DMA peripheral interrupt ISR priority"
+        flavor         data
+        default_value  0x70
+             legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48
+                0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98
+                0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8
+                0xF0 }
+        description   "
+          Set DMA controller ISR priority."
+     }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_I2C {
+        display "I2C IRQ priorities"
+        flavor none
+        no_define
+
+        cdl_option CYGNUM_DEVS_I2C_CORTEXM_A2FXXX_I2C0_ISR_PRIORITY {
+            display   "I2C bus 0 interrupt priority"
+            flavor     data
+            active_if  CYGPKG_DEVS_I2C_CORTEXM_A2FXXX
+            legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48
+                0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98
+                0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8
+                0xF0 }
+            default_value 0x78
+        }
+
+        cdl_option CYGNUM_DEVS_I2C_CORTEXM_A2FXXX_I2C1_ISR_PRIORITY {
+            display   "I2C bus 1 interrupt priority"
+            flavor     data
+            active_if  CYGPKG_DEVS_I2C_CORTEXM_A2FXXX
+            legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48
+                0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98
+                0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8
+                0xF0 }
+            default_value 0x78
+        }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_ETH {
+        display   "Ethernet IRQ priorities"
+        flavor     none
+        no_define
+
+        cdl_option CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_ISR_SP {
+            display       "Ethernet interrupt ISR priority"
+            active_if      CYGPKG_DEVS_ETH_CORTEXM_A2FXXX
+            flavor         data
+            no_define
+            default_value  0x78
+                legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48
+                    0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98
+                    0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8
+                    0xF0 }
+            description   "
+                  Set the Ethernet controller ISR priority."
+       }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_SERIAL {
+        display   "Serial controller IRQ priorities"
+        flavor     none
+        no_define
+
+        cdl_option CYGNUM_DEVS_SERIAL_CORTEXM_A2FXXX_SERIAL0_ISR_SP {
+            display       "Serial port 0 driver ISR priority"
+            active_if      CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0
+            flavor         data
+            no_define
+            default_value  0x78
+                legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48
+                    0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98
+                    0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8
+                    0xF0 }
+            description   "
+                  Set the serial 0 controller ISR priority."
+       }
+
+        cdl_option CYGNUM_DEVS_SERIAL_CORTEXM_A2FXXX_SERIAL1_ISR_SP {
+            display       "Serial port 1 driver ISR priority"
+            active_if      CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1
+            flavor         data
+            no_define
+            default_value  0x80
+                legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48
+                    0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98
+                    0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8
+                    0xF0 }
+            description   "
+                  Set the serial 1 controller ISR priority."
+       }
+    }
\ No newline at end of file
diff --git a/packages/hal/cortexm/a2fxxx/var/current/include/hal_cache.h b/packages/hal/cortexm/a2fxxx/var/current/include/hal_cache.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/var/current/include/hal_cache.h
@@ -0,0 +1,116 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+//      hal_cache.h
+//
+//      HAL cache control API
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour
+// Contributors: 
+// Date:         2011-00-03
+// Purpose:      Cache control API
+// Description:  The macros defined here provide the HAL APIs for handling
+//               cache control operations.
+//
+//               For the Atcel SmartFusion, these are empty macros as there
+//               is no cache.
+// Usage:
+//               #include <cyg/hal/hal_cache.h>
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//-----------------------------------------------------------------------------
+// Cache dimensions
+
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
diff --git a/packages/hal/cortexm/a2fxxx/var/current/include/hal_diag.h b/packages/hal/cortexm/a2fxxx/var/current/include/hal_diag.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/var/current/include/hal_diag.h
@@ -0,0 +1,91 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+//=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL diagnostics
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Original:    nickg (STM32 HAL)
+// Date:        2011-02-03
+// Purpose:     HAL diagnostics
+// Description:
+// Usage:       #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_if.h>
+
+//-----------------------------------------------------------------------------
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+#define HAL_DIAG_INIT()          hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_)  hal_if_diag_read_char(&_c_)
+
+#else
+
+__externC void hal_a2fxxx_diag_init(void);
+__externC void hal_a2fxxx_diag_putc(char);
+__externC cyg_uint8 hal_a2fxxx_diag_getc(void);
+
+# ifndef HAL_DIAG_INIT
+#  define HAL_DIAG_INIT() hal_a2fxxx_diag_init()
+# endif
+
+# ifndef HAL_DIAG_WRITE_CHAR
+#  define HAL_DIAG_WRITE_CHAR(__c) hal_a2fxxx_diag_putc(__c)
+# endif
+
+# ifndef HAL_DIAG_READ_CHAR
+#  define HAL_DIAG_READ_CHAR(__c) (__c) = hal_a2fxxx_diag_getc()
+# endif
+
+#endif
+
+//-----------------------------------------------------------------------------
+// end of hal_diag.h
+#endif // CYGONCE_HAL_DIAG_H
diff --git a/packages/hal/cortexm/a2fxxx/var/current/include/plf_stub.h b/packages/hal/cortexm/a2fxxx/var/current/include/plf_stub.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/var/current/include/plf_stub.h
@@ -0,0 +1,89 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008
+// Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Contributors:jskov, gthomas, jlarmour
+// Date:        2008-07-30
+// Purpose:     Platform HAL stub support for STM32 variant boards.
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+
+#include <cyg/hal/cortexm_stub.h>           // architecture stub support
+
+#include <cyg/hal/hal_io.h>
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+__externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+
+#define HAL_STUB_PLATFORM_INIT()              CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
diff --git a/packages/hal/cortexm/a2fxxx/var/current/include/var_arch.h b/packages/hal/cortexm/a2fxxx/var/current/include/var_arch.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/var/current/include/var_arch.h
@@ -0,0 +1,66 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+//      var_arch.h
+//
+//      Actel SmartFusion  Cortex-M3 variant architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Date:         2011-01-18
+// Purpose:      Actel SmartFusion Cortex-M3 variant architecture overrides
+// Description:
+// Usage:        #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+
+#include <cyg/hal/plf_arch.h>
+
+#ifdef CYGSEM_HAL_CORTEXM_A2FXXX_DEFINES_IDLE_THREAD_ACTION
+externC void hal_idle_thread_action( cyg_uint32 );
+
+# define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
+#endif
+//-----------------------------------------------------------------------------
+// end of var_arch.h
+#endif // CYGONCE_HAL_VAR_ARCH_H
diff --git a/packages/hal/cortexm/a2fxxx/var/current/include/var_intr.h b/packages/hal/cortexm/a2fxxx/var/current/include/var_intr.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/var/current/include/var_intr.h
@@ -0,0 +1,232 @@
+#ifndef CYGONCE_HAL_VAR_INTR_H
+#define CYGONCE_HAL_VAR_INTR_H
+//==========================================================================
+//
+//      var_intr.h
+//
+//      HAL Interrupt and clock assignments for Smartfusion Cortex-M3 variants
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Date:         2011-01-18
+// Purpose:      Define Interrupt support
+// Description:  The interrupt specifics for Actel Smartfusion Cortex-M3
+//               are defined here.
+//
+// Usage:        #include <cyg/hal/var_intr.h>
+//               However applications should include using <cyg/hal/hal_intr.h>
+//               instead to allow for platform overrides.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/plf_intr.h>
+
+//==========================================================================
+
+#define CYGNUM_HAL_INTERRUPT_WD               (0+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_VR_PSM_5V        (1+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_VR_PSM_3V        (2+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RTC0_0           (3+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RTC0_1           (4+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_MAC0             (5+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_IAP              (6+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ENVM0            (7+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ENVM1            (8+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA              (9+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART0            (10+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART1            (11+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SPI0             (12+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SPI1             (13+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C0_0           (14+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C0_1           (15+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C0_2           (16+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C1_0           (17+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C1_1           (18+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C1_2           (19+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM0_1           (20+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM0_2           (21+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_MSS_CCC_0        (22+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_MSS_CCC_1        (23+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_AHB              (24+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RESERVED0        (25+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RESERVED1        (26+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RESERVED2        (27+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RESERVED3        (28+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RESERVED4        (29+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RESERVED5        (30+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_FAB              (31+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO0            (32+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO1            (33+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO2            (34+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO3            (35+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO4            (36+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO5            (37+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO6            (38+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO7            (39+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO8            (40+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO9            (41+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO10           (42+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO11           (43+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO12           (44+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO13           (45+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO14           (46+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO15           (47+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO16           (48+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO17           (49+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO18           (50+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO19           (51+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO20           (52+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO21           (53+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO22           (54+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO23           (55+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO24           (56+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO25           (57+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO26           (58+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO27           (59+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO28           (60+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO29           (61+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO30           (62+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO31           (63+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG0    (64+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG1    (65+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG2    (66+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG3    (67+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG0    (68+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG1    (69+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG2    (70+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG3    (71+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG0    (72+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG1    (73+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG2    (74+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG3    (75+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_DV      (76+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_DV      (77+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_DV      (78+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_CD      (79+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_CD      (80+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_CD      (81+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_CS      (81+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_CS      (83+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_CS      (84+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP0_FALL   (85+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP1_FALL   (86+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP2_FALL   (87+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP3_FALL   (88+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP4_FALL   (89+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP5_FALL   (90+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP6_FALL   (91+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP7_FALL   (92+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP8_FALL   (93+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP9_FALL   (94+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP10_FALL  (95+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP11_FALL  (96+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP0_RISE   (97+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP1_RISE   (98+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP2_RISE   (99+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP3_RISE   (100+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP4_RISE   (101+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP5_RISE   (102+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP6_RISE   (103+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP7_RISE   (104+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP8_RISE   (105+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP9_RISE   (106+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP10_RISE  (107+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP11_RISE  (108+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_FF      (109+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_FAF     (110+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_FE      (111+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_FF      (112+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_FAF     (113+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_FE      (114+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_FF      (115+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_FAF     (116+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_FE      (117+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG0    (118+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG1    (119+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG2    (120+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG3    (121+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG4    (122+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG5    (123+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG6    (124+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG7    (125+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG8    (126+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG9    (127+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG10   (128+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG11   (129+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG12   (130+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG13   (131+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG14   (132+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG15   (133+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG16   (134+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG17   (135+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG18   (136+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG19   (137+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG20   (138+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG21   (139+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG22   (140+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG23   (141+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG24   (142+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG25   (143+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG26   (144+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG27   (145+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG28   (146+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG29   (147+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG30   (148+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG31   (149+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#ifndef CYGNUM_HAL_INTERRUPT_NVIC_MAX
+#define CYGNUM_HAL_INTERRUPT_NVIC_MAX       (CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG31)
+#endif
+
+#define CYGNUM_HAL_ISR_MIN     0
+#ifndef CYGNUM_HAL_ISR_MAX
+#define CYGNUM_HAL_ISR_MAX     CYGNUM_HAL_INTERRUPT_NVIC_MAX
+#endif
+#define CYGNUM_HAL_ISR_COUNT   (CYGNUM_HAL_ISR_MAX + 1)
+
+#define CYGNUM_HAL_VSR_MIN     0
+#ifndef CYGNUM_HAL_VSR_MAX
+#define CYGNUM_HAL_VSR_MAX     (CYGNUM_HAL_VECTOR_SYS_TICK+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#endif
+#define CYGNUM_HAL_VSR_COUNT   (CYGNUM_HAL_VSR_MAX+1)
+
+
+//----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_INTR_H
+// EOF var_intr.h
diff --git a/packages/hal/cortexm/a2fxxx/var/current/include/var_io.h b/packages/hal/cortexm/a2fxxx/var/current/include/var_io.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/var/current/include/var_io.h
@@ -0,0 +1,1196 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//=============================================================================
+//
+//      var_io.h
+//
+//      Variant specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Date:        2011-02-03
+// Purpose:     Smartfusion Cortex-M3 variant specific registers
+// Description:
+// Usage:       #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal_cortexm_a2fxxx.h>
+
+#include <cyg/hal/plf_io.h>
+
+//=============================================================================
+// Peripherals
+
+#define CYGHWR_HAL_A2FXXX_SC                               0xE0042000
+
+// Device peripherals
+#define CYGHWR_HAL_A2FXXX_UART0                            0x40000000
+#define CYGHWR_HAL_A2FXXX_SPI0                             0x40001000
+#define CYGHWR_HAL_A2FXXX_I2C0                             0x40002000
+#define CYGHWR_HAL_A2FXXX_MAC                              0x40003000
+#define CYGHWR_HAL_A2FXXX_DMA                              0x40004000
+#define CYGHWR_HAL_A2FXXX_TIMER                            0x40005000
+#define CYGHWR_HAL_A2FXXX_WD                               0x40006000
+#define CYGHWR_HAL_A2FXXX_FABRIC_IIC                       0x40007000
+#define CYGHWR_HAL_A2FXXX_UART1                            0x40010000
+#define CYGHWR_HAL_A2FXXX_SPI1                             0x40011000
+#define CYGHWR_HAL_A2FXXX_I2C1                             0x40012000
+#define CYGHWR_HAL_A2FXXX_MSS_GPIO                         0x40013000
+#define CYGHWR_HAL_A2FXXX_RTC                              0x40014000
+#define CYGHWR_HAL_A2FXXX_EFROM                            0x40015000
+#define CYGHWR_HAL_A2FXXX_IAP                              0x40016000
+#define CYGHWR_HAL_A2FXXX_ANALOG_ENGINE                    0x40020000
+#define CYGHWR_HAL_A2FXXX_FPAG_ESRAM                       0x40040000
+#define CYGHWR_HAL_A2FXXX_FPGA                             0x40050000
+#define CYGHWR_HAL_A2FXXX_PERIPH                           0x42000000
+
+// Internal flash (Embedded Non-volatile Memory, ENVM)
+#define CYGHWR_HAL_A2FXXX_ENVM_ARRAY                       0x60000000
+#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES                 0x60080000
+#define CYGHWR_HAL_A2FXXX_ENVM_AUX_BLOCK_A                 0x60084000
+#define CYGHWR_HAL_A2FXXX_ENVM_AUX_BLOCK_SP                0x60088000
+#define CYGHWR_HAL_A2FXXX_ENVM                             0x60100000
+
+// External memory base address
+#define CYGHWR_HAL_A2FXXX_EMEM_TYPE0                       0x70000000
+#define CYGHWR_HAL_A2FXXX_EMEM_TYPE1                       0x74000000
+
+//=============================================================================
+// Bit-Band base address
+#define CYGHWR_HAL_A2FXXX_I2C0_BB                          ( CYGHWR_HAL_A2FXXX_PERIPH + 0x00040000 )
+#define CYGHWR_HAL_A2FXXX_I2C1_BB                          ( CYGHWR_HAL_A2FXXX_PERIPH + 0x00240000 )
+#define CYGHWR_HAL_A2FXXX_MSS_GPIO_BB                      ( CYGHWR_HAL_A2FXXX_PERIPH + 0x00260000 )
+#define CYGHWR_HAL_A2FXXX_MAC_BB                           ( CYGHWR_HAL_A2FXXX_PERIPH + 0x00060000 )
+
+//=============================================================================
+// Device signature and ID registers
+
+#define CYGHWR_HAL_A2FXXX_MCU_ID                           (CYGHWR_HAL_A2FXXX_CORTEXM3 + 0xD00)
+#define CYGHWR_HAL_A2FXXX_MCU_ID_REV(__x)                  ((__x)&0xF)
+#define CYGHWR_HAL_A2FXXX_MCU_PART_NO(__x)                 (((__x)>>4)&0x0FFF)
+#define CYGHWR_HAL_A2FXXX_MCU_VAR_NO(__x)                  (((__x)>>20)&0xF)
+
+
+//=============================================================================
+// System Control
+//
+#define CYGHWR_HAL_A2FXXX_SC_ESRAM_CR                      0x000
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_CR                       0x004
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_REMAP_SYS_CR             0x008
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_REMAP_FAB_CR             0x00C
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_CR              0x010
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_BASE_CR              0x014
+#define CYGHWR_HAL_A2FXXX_SC_AHB_MATRIX_CR                 0x018
+#define CYGHWR_HAL_A2FXXX_SC_MSS_SR                        0x01C
+#define CYGHWR_HAL_A2FXXX_SC_CLR_MSS_SR                    0x020
+#define CYGHWR_HAL_A2FXXX_SC_EFROM_CR                      0x024
+#define CYGHWR_HAL_A2FXXX_SC_IAP_CR                        0x028
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTIRQ_CR                0x02C
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR                0x030
+#define CYGHWR_HAL_A2FXXX_SC_DEVICE_SR                     0x034
+#define CYGHWR_HAL_A2FXXX_SC_SYSTICK_CR                    0x038
+#define CYGHWR_HAL_A2FXXX_SC_EMC_MUX_CR                    0x03C
+#define CYGHWR_HAL_A2FXXX_SC_EMC_CS0_CR                    0x040
+#define CYGHWR_HAL_A2FXXX_SC_EMC_CS1_CR                    0x044
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR                    0x048
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR                0x04C
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR                0x050
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR                0x054
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR                0x058
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_SR                    0x05C
+#define CYGHWR_HAL_A2FXXX_SC_VRPSM_CR                      0x064
+#define CYGHWR_HAL_A2FXXX_SC_FAB_APB_HW_DR                 0x070
+#define CYGHWR_HAL_A2FXXX_SC_LOOPBACK_CR                   0x074
+#define CYGHWR_HAL_A2FXXX_SC_MSS_IO_BANK_CR                0x078
+#define CYGHWR_HAL_A2FXXX_SC_GPIN_SOURCE_CR                0x07C
+#define CYGHWR_HAL_A2FXXX_SC_IOMUX(_x_)                    ( 0x100 + (_x_ << 0x2) )
+
+// Reset register
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_PAD            BIT_(19)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_F2M            BIT_(18)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_FPGA           BIT_(17)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_EXT            BIT_(16)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_IAP            BIT_(15)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_GPIO           BIT_(14)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_ACE            BIT_(13)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_I2C1           BIT_(12)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_I2C0           BIT_(11)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_SPI1           BIT_(10)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_SPI0           BIT_(9)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_UART1          BIT_(8)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_UART0          BIT_(7)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_TIMER          BIT_(6)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_PDMA           BIT_(5)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_MAC            BIT_(4)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_EMC            BIT_(3)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_ESRAM1         BIT_(2)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_ESRAM0         BIT_(1)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_ENVM           BIT_(0)
+
+#define CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(_periph)          CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_##_periph
+
+void hal_a2fxxx_periph_reset( cyg_uint32 );
+void hal_a2fxxx_periph_release( cyg_uint32 );
+
+#define CYGHWR_HAL_A2FXXX_PERIPH_RESET           hal_a2fxxx_periph_reset
+#define CYGHWR_HAL_A2FXXX_PERIPH_RELEASE         hal_a2fxxx_periph_release
+
+#if 0
+#define CYGHWR_HAL_A2FXXX_PERIPH_START(_x)                 \
+{                                                          \
+    volatile int c = 0;                                    \
+    hal_a2fxxx_periph_reset(_x);                           \
+    while( c++ < 20 );                                     \
+    hal_a2fxxx_periph_release(_x);                         \
+}
+#endif
+
+// MSS CLK register
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GLBDIV(_x)         VALUE_(12, ((_x)&0x3))
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_RTCIF(_x)          VALUE_( 8, ((_x)&0xf))
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_ACLKDIV(_x)        VALUE_( 6, ((_x)&0x3))
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK1DIV(_x)       VALUE_( 4, ((_x)&0x3))
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK0DIV(_x)       VALUE_( 2, ((_x)&0x3))
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_PCLK0DIV(_x)   ((_x & 0x000C) >> 2)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_PCLK1DIV(_x)   ((_x & 0x0030) >> 4)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_GLBDIV(_x)     ((_x & 0x0C00) >> 12)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_RMIICLKSEL         BIT_(0)
+
+// MSS CCC DIV register
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIVRST       BIT_(22)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIVHALF      BIT_(21)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIV(_x)      VALUE_(16, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIVRST       BIT_(14)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIVHALF      BIT_(13)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIV(_x)      VALUE_( 8, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIVRST       BIT_(6)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIVHALF      BIT_(5)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIV(_x)      VALUE_( 0, _x)
+
+// MSS CCC MUX register
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_MAINOSCM(_x)   VALUE_(30, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_MAINOSCEN      BIT_(29)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXCFG(_x)   VALUE_(26, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXSEL(_x)   VALUE_(24, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSC        BIT_(22)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(_x)      VALUE_(19, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNCSEL        BIT_(18)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXCSEL         BIT_(17)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATCSEL       BIT_(16)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSB        BIT_(14)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OBMUX(_x)      VALUE_(11, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNBSEL        BIT_(10)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXBSEL         BIT_(9)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATBSEL       BIT_(8)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSA        BIT_(6)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OAMUX(_x)      VALUE_( 3, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNASEL        BIT_(2)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXASEL         BIT_(1)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATASEL       BIT_(0)
+
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLA             0
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLC             1
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLINT           2
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GND             3
+
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKA_SEL(_x_)  \
+({                                                         \
+   cyg_uint32 _i = _x_;                                    \
+   _i;                                                     \
+})
+
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKB_SEL(_x_)  \
+({                                                         \
+   cyg_uint32 _i = _x_;                                    \
+   _i = _i << 8;                                           \
+   _i;                                                     \
+})
+
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKC_SEL(_x_)  \
+({                                                         \
+   cyg_uint32 _i = _x_;                                    \
+   _i = _i << 16;                                          \
+   _i;                                                     \
+})
+
+// MSS CCC PLL register
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_PLLEN          BIT_(31)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_VCOSEL2_1(_x)  VALUE_(23, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_VCOSEL0        BIT_(22)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_XDLYSEL(_x)    VALUE_(21, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBDLY(_x)      VALUE_(16, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBSEL(_x)      VALUE_(14, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBDIV(_x)      VALUE_(7, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FINDIV(_x)     VALUE_(0, _x)
+
+// Delay Configuration Register
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA1(_x)      VALUE_(20, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA0(_x)      VALUE_(15, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYC(_x)       VALUE_(10, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYB(_x)       VALUE_(5, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA(_x)       VALUE_(0, _x)
+
+// CCC Status Register
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_SR_PLL_LOCK_SYNC      BIT_(0)
+
+// ESRAM control register
+#define CYGHWR_HAL_A2FXXX_SC_ESRAM_CR_REMAP                BIT_(0)
+
+// ENVM control register
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_CR_SIX_CYCLE             BIT_(7)
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_CR_PIPE_BYPASS           BIT_(6)
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_CR_REMAP_SIZE(_s_)       VALUE_(0, _s_)
+
+// ENVM re-mapping in system or fabric master space register
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_REMAP_BASE(_b_)          VALUE_(1, _b_)
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_REMAP_EN                 BIT_(0)
+
+// Fabric protect size
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_128B            VALUE_(0, 6)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_2KB             VALUE_(0, 10)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_16KB            VALUE_(0, 13)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_32KB            VALUE_(0, 14)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_64KB            VALUE_(0, 15)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_128KB           VALUE_(0, 16)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_256KB           VALUE_(0, 17)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_512KB           VALUE_(0, 18)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_8MB             VALUE_(0, 22)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_128MB           VALUE_(0, 26)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_2GB             VALUE_(0, 30)
+
+// Fabric protect control register
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_BASE_CR_VAL(_x)      VALUE_( 1, _x)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_BASE_CR_EN           BIT_(0)
+
+// Embedded FlashROM control register
+#define CYGHWR_HAL_A2FXXX_SC_EFROM_CR_SYS_TOPT3_1(_v_)     VALUE_(1, _v_)
+#define CYGHWR_HAL_A2FXXX_SC_EFROM_CR_SYS_TOPT0            BIT_(0)
+
+//=============================================================================
+// DMA
+//
+
+#define CYGHWR_HAL_A2FXXX_DMA_RATIO                         0x0
+#define CYGHWR_HAL_A2FXXX_DMA_BUFFER_STATUS                 0x4
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(_x_)                (0x20 + (_x_ * 0x20))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS(_x_)              (0x24 + (_x_ * 0x20))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BA_SRC(_x_)              (0x28 + (_x_ * 0x20))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BA_DST(_x_)              (0x2C + (_x_ * 0x20))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BA_COUNT(_x_)            (0x30 + (_x_ * 0x20))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BB_SRC(_x_)              (0x34 + (_x_ * 0x20))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BB_DST(_x_)              (0x38 + (_x_ * 0x20))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BB_COUNT(_x_)            (0x3C + (_x_ * 0x20))
+
+// Ratio
+#define CYGHWR_HAL_A2FXXX_DMA_RATIO_HILO(_x_)              VALUE_(0, _x_)
+
+// Buffer status
+#define CYGHWR_HAL_A2FXXX_DMA_BUFFER_STATUS_CHAxx(_x_)     VALUE_( (_x_ << 1), 1)
+#define CYGHWR_HAL_A2FXXX_DMA_BUFFER_STATUS_CHAx(_x_)      VALUE_(((_x_ << 1)+1), 1)
+
+// Channel control
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_PERIPH_SEL(_p_)     VALUE_(23, _p_)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_WR_ADJ(_v_)         VALUE_(14, _v_)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR_4B         VALUE_(12, 0x3)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR_2B         VALUE_(12, 0x2)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR_1B         VALUE_(12, 0x1)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR_0B         VALUE_(12, 0x0)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR(_x_)       VALUE_(12, ((_x_) & 0x3))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR_4B         VALUE_(10, 0x3)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR_2B         VALUE_(10, 0x2)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR_1B         VALUE_(10, 0x1)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR_0B         VALUE_(10, 0x0)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR(_x_)       VALUE_(10, ((_x_) & 0x3))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_HI_PRI          BIT_(9)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPB           BIT_(8)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPA           BIT_(7)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_INTEN               BIT_(6)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_RESET               BIT_(5)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_PAUSE               BIT_(4)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_XFER_WORD           VALUE_(2, 0x2)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_XFER_HWORD          VALUE_(2, 0x1)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_XFER_BYTE           VALUE_(2, 0x0)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DIR                 BIT_(1)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_PERIPH              BIT_(0)
+
+// DMA transfer type
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_UART0              0x0
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_UART0                0x1
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_UART1              0x2
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_UART1                0x3
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_SPI0               0x4
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_SPI0                 0x5
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_SPI1               0x6
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_SPI1                 0x7
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_FPGA               0x8
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_FPGA                 0x9
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_ACE                0x10
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_ACE                  0x11
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_MEMORY                  0xff
+
+#define CYGHWR_HAL_A2FXXX_DMA_XFER(_x)                     CYGHWR_HAL_A2FXXX_DMA_XFER_##_x
+
+#define CYGHWR_HAL_A2FXXX_DMA_GET_SUB_ID(_x)               ((_x>>2) & 0x01)
+
+// Channel status
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS_BUF_SEL           BIT_(2)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS_COMPB             BIT_(1)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS_COMPA             BIT_(0)
+
+// Buffer count
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BA_COUNT_FIELD(_c)       VALUE_(0, _c)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BB_COUNT_FIELD(_c)       VALUE_(0, _c)
+
+#define CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL                  8
+#define CYGHWR_HAL_A2FXXX_DMA_MAX_SUB_CHANNEL              2
+
+// DMA access prototypes
+void             hal_dma_init ( void );
+cyg_uint32       a2fxxx_dma_xfer (cyg_uint8 , cyg_bool , cyg_uint32 len, cyg_uint8* , cyg_uint8* );
+cyg_uint32       a2fxxx_dma_ch_setup (cyg_uint8 , cyg_uint8 , cyg_bool , cyg_uint8 , cyg_uint8 , cyg_bool, cyg_uint8);
+void             a2fxxx_dma_ch_detach (cyg_uint8 );
+void             a2fxxx_dma_update_incr (cyg_uint8 , cyg_bool , cyg_uint8 );
+void             a2fxxx_dma_clear_interrupt (cyg_uint8 );
+cyg_uint8        a2fxxx_dma_get_comp_flag (cyg_uint8 );
+
+#define CYGHWR_HAL_A2FXXX_DMA_OUTBOUND                     true
+#define CYGHWR_HAL_A2FXXX_DMA_INBOUND                      false
+
+//=============================================================================
+// ENVM
+//
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS                      0x00
+#define CYGHWR_HAL_A2FXXX_ENVM_CTRL                        0x04
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ                         0x08
+#define CYGHWR_HAL_A2FXXX_ENVM0_CR                         0x10
+#define CYGHWR_HAL_A2FXXX_ENVM1_CR                         0x14
+#define CYGHWR_HAL_A2FXXX_ENVM0_PAGE_STATUS                0x18
+#define CYGHWR_HAL_A2FXXX_ENVM1_PAGE_STATUS                0x1C
+
+// Status Register
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ILLEGAL_CMD_1        BIT_(31)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_1                    VALUE_(24, 0x3)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_OP_DONE_1            BIT_(23)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ECC2_ERR_1           BIT_(22)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ECC1_ERR_1           BIT_(21)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_OVER_THR_1           BIT_(20)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ERASE_ERR_1          BIT_(19)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_PROG_ERR_1           BIT_(18)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_PROT_ERR_1           BIT_(17)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_BSY_1                BIT_(16)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ILLEGAL_CMD_0        BIT_(15)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_0                    VALUE_( 8, 0x3)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_OP_DONE_0            BIT_(7)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ECC2_ERR_0           BIT_(6)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ECC1_ERR_0           BIT_(5)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_OVER_THR_0           BIT_(4)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ERASE_ERR_0          BIT_(3)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_PROG_ERR_0           BIT_(2)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_PROT_ERR_0           BIT_(1)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_BSY_0                BIT_(0)
+
+// Control Register
+#define CYGHWR_HAL_A2FXXX_ENVM_CTRL_COMMAND(_x_)           VALUE_(24, _x_)
+#define CYGHWR_HAL_A2FXXX_ENVM_CTRL_PAGE_ADDR(_x_)         VALUE_( 0, _x_)
+
+// Interrupt Enable
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ILLEGAL_CMD_1           BIT_(31)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_OP_DONE_1               BIT_(23)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ECC2_ERR_1              BIT_(22)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ECC1_ERR_1              BIT_(21)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_OVER_THR_1              BIT_(20)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ERASE_ERR_1             BIT_(19)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_PROG_ERR_1              BIT_(18)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_PROT_ERR_1              BIT_(17)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ILLEGAL_CMD_0           BIT_(15)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_OP_DONE_0               BIT_(7)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ECC2_ERR_0              BIT_(6)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ECC1_ERR_0              BIT_(5)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_OVER_THR_0              BIT_(4)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ERASE_ERR_0             BIT_(3)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_PROG_ERR_0              BIT_(2)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_PROT_ERR_0              BIT_(1)
+
+// Configuration Register
+#define CYGHWR_HAL_A2FXXX_ENVMx_CR_LOCK                    BIT_(2)
+#define CYGHWR_HAL_A2FXXX_ENVMx_CR_PAGE_LOSS               BIT_(1)
+#define CYGHWR_HAL_A2FXXX_ENVMx_CR_READ_NEXT               BIT_(0)
+
+// Page status
+#define CYGHWR_HAL_A2FXXX_ENVMx_PAGE_STATUS_WCOUNT         VALUE_(8, 0x00ffffffff)
+#define CYGHWR_HAL_A2FXXX_ENVMx_PAGE_STATUS_OVER_THR       BIT_(3)
+#define CYGHWR_HAL_A2FXXX_ENVMx_PAGE_STATUS_RPROT          BIT_(2)
+#define CYGHWR_HAL_A2FXXX_ENVMx_PAGE_STATUS_WPROT          BIT_(1)
+#define CYGHWR_HAL_A2FXXX_ENVMx_PAGE_STATUS_OPROT          BIT_(0)
+
+
+//=============================================================================
+// eSRAM
+//
+
+#define CYGHWR_HAL_A2FXXX_ESRAM_CR                         0xE0002000
+#define CYGHWR_HAL_A2FXXX_AHB_MATRIX_CR                    0xE0002018
+
+#define CYGHWR_HAL_A2FXXX_ESRAM_CR_REMAP                   BIT_(0)
+
+
+//=============================================================================
+// SPI
+//
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL                         0x00
+#define CYGHWR_HAL_A2FXXX_SPI_TXRXDF_SIZE                  0x04
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS                       0x08
+#define CYGHWR_HAL_A2FXXX_SPI_IRQ_CLEAR                    0x0C
+#define CYGHWR_HAL_A2FXXX_SPI_RX                           0x10
+#define CYGHWR_HAL_A2FXXX_SPI_TX                           0x14
+#define CYGHWR_HAL_A2FXXX_SPI_CLK_GEN                      0x18
+#define CYGHWR_HAL_A2FXXX_SPI_SLAVE_SEL                    0x1C
+#define CYGHWR_HAL_A2FXXX_SPI_MIS                          0x20
+#define CYGHWR_HAL_A2FXXX_SPI_RIS                          0x24
+
+// Control Register
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_SPH                     BIT_(25)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_SPO                     BIT_(24)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_COUNT(_x)               VALUE_(8, _x)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_IRQ_TX_UNRRUN           BIT_(7)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_IRQ_RX_OVRFLO           BIT_(6)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_IRQ_TX                  BIT_(5)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_IRQ_RX                  BIT_(4)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_PROTO_NS                VALUE_(2, 0x2)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_PROTO_TI                VALUE_(2, 0x1)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_PROTO_MOTOROLA          VALUE_(2, 0x0)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_MASTER                  BIT_(1)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_EN                      BIT_(0)
+
+// Status Register
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_FIFO_EMPTY_N       BIT_(11)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_FIFO_EMPTY         BIT_(10)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_FIFO_FULL_N        BIT_(9)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_FIFO_FULL          BIT_(8)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_FIFO_EMPTY_N       BIT_(7)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_FIFO_EMPTY         BIT_(6)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_FIFO_FULL_N        BIT_(5)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_FIFO_FULL          BIT_(4)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_UNDERRUN           BIT_(3)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_OVERFLOW           BIT_(2)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_RCED               BIT_(1)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_SENT               BIT_(0)
+
+// Interrupt Clear Register
+#define CYGHWR_HAL_A2FXXX_SPI_IRQ_CLEAR_TXUNDRUN           BIT_(3)
+#define CYGHWR_HAL_A2FXXX_SPI_IRQ_CLEAR_RXOVRFLW           BIT_(2)
+#define CYGHWR_HAL_A2FXXX_SPI_IRQ_CLEAR_RXRDY              BIT_(1)
+#define CYGHWR_HAL_A2FXXX_SPI_IRQ_CLEAR_TXDONE             BIT_(0)
+
+// Masked Interrupt
+#define CYGHWR_HAL_A2FXXX_SPI_MIS_TXUNDRUN                 BIT_(3)
+#define CYGHWR_HAL_A2FXXX_SPI_MIS_RXOVRFLW                 BIT_(2)
+#define CYGHWR_HAL_A2FXXX_SPI_MIS_RXRDY                    BIT_(1)
+#define CYGHWR_HAL_A2FXXX_SPI_MIS_TXDONE                   BIT_(0)
+
+// Raw Interrupt Status
+#define CYGHWR_HAL_A2FXXX_SPI_RIS_TXUNDRUN                 BIT_(3)
+#define CYGHWR_HAL_A2FXXX_SPI_RIS_RXOVRFLW                 BIT_(2)
+#define CYGHWR_HAL_A2FXXX_SPI_RIS_RXRDY                    BIT_(1)
+#define CYGHWR_HAL_A2FXXX_SPI_RIS_TXDONE                   BIT_(0)
+
+// Chip select selection
+#define CYGHWR_HAL_A2FXXX_SPI_CS_SEL(_dev)                 (0x1 << _dev)
+
+// Peripherals IOs mapping
+#define CYGHWR_HAL_A2FXXX_SPI0_DO  CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_DO,   DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI0_DI  CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_DI,   DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI0_CLK CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_CLK,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI0_SS0 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_SS_0, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI0_SS1 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_SS_1, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI0_SS2 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_SS_2, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI0_SS3 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_SS_3, DISABLE )
+
+#define CYGHWR_HAL_A2FXXX_SPI1_DO  CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_DO,   DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_DI  CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_DI,   DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_CLK CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_CLK,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS0 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_0, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS1 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_1, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS2 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_2, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS3 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_3, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS4 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_4, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS5 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_5, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS6 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_6, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS7 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_7, DISABLE )
+
+// This is a special GPIO macro accommodated for SPI slave select
+#define CYGHWR_HAL_A2FXXX_CS_GPIO(                        \
+    __bit,                                                \
+    __mode,                                               \
+    __p_io,                                               \
+    __irq)                                                \
+(                                                         \
+      (__bit << 23) |                                     \
+      (CYGHWR_HAL_A2FXXX_GPIO_MODE_ ## __mode) |          \
+       CYGHWR_HAL_A2FXXX_GPIO_PERIPH_GPIO(__p_io) |       \
+      (CYGHWR_HAL_A2FXXX_GPIO_IRQ_ ## __irq)              \
+)
+
+__externC cyg_uint32 hal_a2fxxx_spi_clock( cyg_uint32 );
+
+//=============================================================================
+// I2C
+//
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL                         0x00
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS                       0x04
+#define CYGHWR_HAL_A2FXXX_I2C_DATA                         0x08
+#define CYGHWR_HAL_A2FXXX_I2C_ADDR                         0x0C
+#define CYGHWR_HAL_A2FXXX_I2C_SMBUS                        0x10
+#define CYGHWR_HAL_A2FXXX_I2C_FREQ                         0x14
+#define CYGHWR_HAL_A2FXXX_I2C_GLITCH                       0x18
+
+// Control Register
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_CR2                     BIT_(7)
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_ENS1                    BIT_(6)
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_STA                     BIT_(5)
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_STO                     BIT_(4)
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_SI                      BIT_(3)
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_AA                      BIT_(2)
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_CR1                     BIT_(1)
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_CR0                     BIT_(0)
+
+// I2C clock divider
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_8                        0x7
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_60                       0x6
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_120                      0x5
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_960                      0x4
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_160                      0x3
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_192                      0x2
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_224                      0x1
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_256                      0x0
+
+// Status Registers
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_START             0x08
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_REPEAT_START      0x10
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_ADDR_ACK          0x18
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_ADDR_NACK         0x20
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_DATA_ACK          0x28
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_DATA_NACK         0x30
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_ARBLOST           0x38
+
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_START             0x08
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_REPEAT_START      0x10
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_ARBLOST           0x38
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_ADDR_ACK          0x40
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_ADDR_NACK         0x48
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_DATA_ACK          0x50
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_DATA_NACK         0x58
+
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRESET                0xD0
+
+// SMB
+#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_RST                    BIT_(7)
+#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_NO                     BIT_(6)
+#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_NI                     BIT_(5)
+#define CYGHWR_HAL_A2FXXX_I2C_SMBALERT_NO                  BIT_(4)
+#define CYGHWR_HAL_A2FXXX_I2C_SMBALERT_NI                  BIT_(3)
+#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_EN                     BIT_(2)
+#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_IRQ_EN                 BIT_(1)
+#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_ALERT_IRQ_EN           BIT_(0)
+
+// Peripherals IOs mapping
+#define CYGHWR_HAL_A2FXXX_I2C0_SDA CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, I2C0_SDA, DISABLE )
+#define CYGHWR_HAL_A2FXXX_I2C0_SCL CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, I2C0_SCL, DISABLE )
+
+#define CYGHWR_HAL_A2FXXX_I2C1_SDA CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, I2C1_SDA, DISABLE )
+#define CYGHWR_HAL_A2FXXX_I2C1_SCL CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, I2C1_SCL, DISABLE )
+
+__externC cyg_uint32 hal_a2fxxx_i2c_clock( cyg_uint32 );
+
+//=============================================================================
+// GPIO
+//
+#define CYGHWR_HAL_A2FXXX_MSS_GPIO_CFG(_io)                (_io << 2)
+#define CYGHWR_HAL_A2FXXX_MSS_GPIO_INT                     0x080
+#define CYGHWR_HAL_A2FXXX_MSS_GPIO_DIN                     0x084
+#define CYGHWR_HAL_A2FXXX_MSS_GPIO_DOUT                    0x088
+
+#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR                   0xe0042078
+#define CYGHWR_HAL_A2FXXX_GPIN_SOURCE_CR                   0xe004207c
+#define CYGHWR_HAL_A2FXXX_IOMUX_CR                         0xe0042100
+
+// CFG
+#define CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(_t)              VALUE_(5, (_t & 0x7))
+#define CYGHWR_HAL_A2FXXX_GPIO_CFG_GPINTEN                 BIT_(3)
+#define CYGHWR_HAL_A2FXXX_GPIO_CFG_OUTBUFEN                BIT_(2)
+#define CYGHWR_HAL_A2FXXX_GPIO_CFG_GPINEN                  BIT_(1)
+#define CYGHWR_HAL_A2FXXX_GPIO_CFG_GPOUTEN                 BIT_(0)
+
+// MSS GPIO
+#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_LVCMOS_3V3           0x0
+#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_LVCMOS_2V5           0x1
+#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_LVCMOS_1V8           0x2
+#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_LVCMOS_1V5           0x3
+
+#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTEAST(_t)        VALUE_(0, (CYGHWR_HAL_A2FXXX_MSS_IO_BANK_##_t & 0x3))
+#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTWEST(_t)        VALUE_(2, (CYGHWR_HAL_A2FXXX_MSS_IO_BANK_##_t & 0x3))
+
+// HAL definitions
+#define CYGHWR_HAL_A2FXXX_GPIO_MODE_IN                     VALUE_(0,0)     // Input mode
+#define CYGHWR_HAL_A2FXXX_GPIO_MODE_OUT                    VALUE_(0,1)     // Output mode
+#define CYGHWR_HAL_A2FXXX_GPIO_MODE_PERIPH                 VALUE_(0,2)     // Peripheral function mode
+
+#define CYGHWR_HAL_A2FXXX_GPIO_PERIPH_IO(_name_)           VALUE_(2, CYGHWR_HAL_A2FXXX_IOMUX_##_name_)
+#define CYGHWR_HAL_A2FXXX_GPIO_PERIPH_GPIO(_id_)           VALUE_(2, (CYGHWR_HAL_A2FXXX_IOMUX_GPIO_0+_id_))
+
+#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_DISABLE                 VALUE_(10,0)     // Interrupt disable
+#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_FALLING_EDGE            VALUE_(10,1)     // Interrupt on falling edge
+#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_RISING_EDGE             VALUE_(10,2)     // Interrupt on rising edge
+#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_BOTH_EDGES              VALUE_(10,3)     // Interrupt on both edges
+#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_LOW_LEVEL               VALUE_(10,4)     // Interrupt on low level
+#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_HIGH_LEVEL              VALUE_(10,5)     // Interrupt on high level
+
+typedef struct
+{
+   cyg_uint32 val;
+} default_io_mux_type;
+
+// IOMUX index setting for peripherals
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_DO                    0
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_DI                    1
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_CLK                   2
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_SS_0                  3
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_TX                   4
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_RX                   5
+#define CYGHWR_HAL_A2FXXX_IOMUX_I2C0_SDA                   6
+#define CYGHWR_HAL_A2FXXX_IOMUX_I2C0_SCL                   7
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_DO                    8
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_DI                    9
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_CLK                   10
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_0                  11
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_TX                   12
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_RX                   13
+#define CYGHWR_HAL_A2FXXX_IOMUX_I2C1_SDA                   14
+#define CYGHWR_HAL_A2FXXX_IOMUX_I2C1_SCL                   15
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_TXD0                  16
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_TXD1                  17
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_RXD0                  18
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_RXD1                  19
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_TXEN                  20
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_CRSDV                 21
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_RXER                  22
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_MDIO                  23
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_MDC                   24
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_0                     25
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_1                     26
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_2                     27
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_3                     28
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_4                     29
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_5                     30
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_6                     31
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_7                     32
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_8                     33
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_9                     34
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_10                    35
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_11                    36
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_12                    37
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_13                    38
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_14                    39
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_15                    40
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_16                    41
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_17                    42
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_18                    43
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_19                    44
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_20                    45
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_21                    46
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_22                    47
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_23                    48
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_24                    49
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_25                    50
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_26                    51
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_27                    52
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_28                    53
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_29                    54
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_30                    55
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_31                    56
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_SS_1                  57
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_SS_2                  58
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_SS_3                  59
+// 60 to 63 not used
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_RTS                  64
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_DTR                  65
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_CTS                  66
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_DSR                  67
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_RI                   68
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_DCD                  69
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_1                  70
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_2                  71
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_3                  72
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_4                  73
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_5                  74
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_6                  75
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_7                  76
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_RTS                  77
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_DTR                  78
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_CTS                  79
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_DSR                  80
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_RI                   81
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_DCD                  82
+#define CYGHWR_HAL_A2FXXX_IOMUX_NONE                       83
+
+// This macro packs the port, bit number, mode, buffer and irq
+// for a GPIO pin into a single word.
+// The packing puts:
+
+#define CYGHWR_HAL_A2FXXX_GPIO(                             \
+    __bit,                                                  \
+    __mode,                                                 \
+    __name,                                                 \
+    __irq)                                                  \
+(                                                           \
+         (__bit << 23) |                                    \
+         (CYGHWR_HAL_A2FXXX_GPIO_MODE_ ## __mode) |         \
+          CYGHWR_HAL_A2FXXX_GPIO_PERIPH_IO(__name) |        \
+         (CYGHWR_HAL_A2FXXX_GPIO_IRQ_ ## __irq)             \
+)
+
+
+// Macros to extract encoded values
+#define CYGHWR_HAL_A2FXXX_GPIO_BIT(__pin)                  (((__pin)>>23) & 0x1F)
+#define CYGHWR_HAL_A2FXXX_GPIO_MODE(__pin)                 ((__pin)&0x0003)
+#define CYGHWR_HAL_A2FXXX_GPIO_IOMUX_IDX(__pin)            ((__pin>>2)  & 0xff)
+#define CYGHWR_HAL_A2FXXX_GPIO_IRQ(__pin)                  ((__pin>>10) & 0x07)
+#define CYGHWR_HAL_A2FXXX_GPIO_NONE                        (0xFFFFFFFF)
+
+__externC void hal_a2fxxx_gpio_set( cyg_uint32 pin );
+__externC void hal_a2fxxx_gpio_out( cyg_uint32 pin, int val );
+__externC void hal_a2fxxx_gpio_in ( cyg_uint32 pin, int *val );
+
+#define CYGHWR_HAL_A2FXXX_GPIO_SET(__pin )        hal_a2fxxx_gpio_set( __pin )
+#define CYGHWR_HAL_A2FXXX_GPIO_OUT(__pin, __val ) hal_a2fxxx_gpio_out( __pin, __val )
+#define CYGHWR_HAL_A2FXXX_GPIO_IN(__pin,  __val ) hal_a2fxxx_gpio_in( __pin, __val )
+
+
+//=============================================================================
+// UART
+//
+#define CYGHWR_HAL_A2FXXX_UART16550_RBR                    0x00
+#define CYGHWR_HAL_A2FXXX_UART16550_THR                    0x00
+#define CYGHWR_HAL_A2FXXX_UART16550_DLR                    0x00
+#define CYGHWR_HAL_A2FXXX_UART16550_DMR                    0x04
+#define CYGHWR_HAL_A2FXXX_UART16550_IER                    0x04
+#define CYGHWR_HAL_A2FXXX_UART16550_IIR                    0x08
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR                    0x08
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR                    0x0C
+#define CYGHWR_HAL_A2FXXX_UART16550_MCR                    0x10
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR                    0x14
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR                    0x18
+#define CYGHWR_HAL_A2FXXX_UART16550_SR                     0x1C
+
+// IER
+#define CYGHWR_HAL_A2FXXX_UART16550_IER_EDSSI              BIT_(3)
+#define CYGHWR_HAL_A2FXXX_UART16550_IER_ELSI               BIT_(2)
+#define CYGHWR_HAL_A2FXXX_UART16550_IER_ETBEI              BIT_(1)
+#define CYGHWR_HAL_A2FXXX_UART16550_IER_ERBFI              BIT_(0)
+
+// IIR (by priority)
+#define CYGHWR_HAL_A2FXXX_UART16550_IIR_MODEM_STATUS       VALUE_(0, 0x0)
+#define CYGHWR_HAL_A2FXXX_UART16550_IIR_THRE               VALUE_(0, 0x2)
+#define CYGHWR_HAL_A2FXXX_UART16550_IIR_CTI                VALUE_(0, 0xC)
+#define CYGHWR_HAL_A2FXXX_UART16550_IIR_RXD                VALUE_(0, 0x4)
+#define CYGHWR_HAL_A2FXXX_UART16550_IIR_RLS                VALUE_(0, 0x6)
+
+// Fifo control
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_RX_TRIG_1BYTE      VALUE_(6, 0x0)
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_RX_TRIG_4BYTE      VALUE_(6, 0x1)
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_RX_TRIG_8BYTE      VALUE_(6, 0x2)
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_RX_TRIG_14BYTE     VALUE_(6, 0x3)
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_EN_TXRX_DY         BIT_(3)
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_CLEAR_TX_FIFO      BIT_(2)
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_CLEAR_RX_FIFO      BIT_(1)
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_RESERVED           BIT_(0)
+
+// Line control
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_DLAB               BIT_(7)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_SB                 BIT_(6)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_SP                 BIT_(5)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_EPS                BIT_(4)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_PEN                BIT_(3)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_STOP_1             VALUE_(2,0)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_STOP_2             VALUE_(2,1)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_WLS_5BITS          VALUE_(0, 0x0)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_WLS_6BITS          VALUE_(0, 0x1)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_WLS_7BITS          VALUE_(0, 0x2)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_WLS_8BITS          VALUE_(0, 0x3)
+
+// MCR register
+#define CYGHWR_HAL_A2FXXX_UART16550_MCR_LOOP               BIT_(4)
+#define CYGHWR_HAL_A2FXXX_UART16550_MCR_OUT2               BIT_(3)
+#define CYGHWR_HAL_A2FXXX_UART16550_MCR_OUT1               BIT_(2)
+#define CYGHWR_HAL_A2FXXX_UART16550_MCR_RTS                BIT_(1)
+#define CYGHWR_HAL_A2FXXX_UART16550_MCR_DTR                BIT_(0)
+
+// LSR register
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_FIER               BIT_(6)
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_TEMT               BIT_(6)
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_THRE               BIT_(5)
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_BI                 BIT_(4)
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_FE                 BIT_(3)
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_PE                 BIT_(2)
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_OE                 BIT_(1)
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_DR                 BIT_(0)
+
+// MSR
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_DCD                BIT_(7)
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_RI                 BIT_(6)
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_DSR                BIT_(5)
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_CTS                BIT_(4)
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_DDCD               BIT_(3)
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_TERI               BIT_(2)
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_DDSR               BIT_(1)
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_DCTS               BIT_(0)
+
+__externC cyg_uint32 hal_a2fxxx_pclk0;
+__externC cyg_uint32 hal_a2fxxx_pclk1;
+
+__externC void hal_a2fxxx_uart_setbaud(cyg_uint32 , cyg_uint32 );
+
+// Consider adding rounding ?
+#define CYG_HAL_CORTEXM_A2FXXX_BAUD_GENERATOR( id, baud )  \
+({                                                         \
+   cyg_uint16 _divider;                                    \
+   if( id == 0 )                                           \
+     _divider = (hal_a2fxxx_pclk0/(baud << 4));            \
+   else                                                    \
+     _divider = (hal_a2fxxx_pclk1/(baud << 4));            \
+   _divider;                                               \
+})
+
+// Peripherals IOs mapping
+#define CYGHWR_HAL_A2FXXX_UART0_TX CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, UART0_TX, DISABLE )
+#define CYGHWR_HAL_A2FXXX_UART0_RX CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, UART0_RX, DISABLE )
+
+#define CYGHWR_HAL_A2FXXX_UART1_TX CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, UART1_TX, DISABLE )
+#define CYGHWR_HAL_A2FXXX_UART1_RX CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, UART1_RX, DISABLE )
+
+
+//=============================================================================
+// Watchdog
+//
+#define CYGHWR_HAL_A2FXXX_WD_VALUE                         0x00
+#define CYGHWR_HAL_A2FXXX_WD_LOAD                          0x04
+#define CYGHWR_HAL_A2FXXX_WD_MVRP                          0x08
+#define CYGHWR_HAL_A2FXXX_WD_REFRESH                       0x0C
+#define CYGHWR_HAL_A2FXXX_WD_ENABLE                        0x10
+#define CYGHWR_HAL_A2FXXX_WD_CTRL                          0x14
+#define CYGHWR_HAL_A2FXXX_WD_STATUS                        0x18
+#define CYGHWR_HAL_A2FXXX_WD_RIS                           0x1C
+#define CYGHWR_HAL_A2FXXX_WD_MIS                           0x20
+
+// Keys
+#define CYGHWR_HAL_A2FXXX_WD_REFRESH_KEY                   0xAC15DE42
+#define CYGHWR_HAL_A2FXXX_WD_DISABLE_KEY                   0x4C6E55FA
+
+
+//=============================================================================
+// Timer
+//
+#define CYGHWR_HAL_A2FXXX_TIMER1   CYGHWR_HAL_A2FXXX_TIMER
+#define CYGHWR_HAL_A2FXXX_TIMER2   (CYGHWR_HAL_A2FXXX_TIMER + 0x18)
+
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_VAL                   0x00
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_LOADVAL               0x04
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_BGLOADVAL             0x08
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL                  0x0c
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_RIS                   0x10
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_MIS                   0x14
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_VAL_U                0x30
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_VAL_L                0x34
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_LOADVAL_U            0x38
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_LOADVAL_L            0x3C
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_BGLOADVAL_U          0x40
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_BGLOADVAL_L          0x44
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_CTRL                 0x48
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_RIS                  0x4C
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_MIS                  0x50
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_MODE                 0x54
+
+// Timer control
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL_INTEN            BIT_(2)
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL_ONESHOT          BIT_(1)
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL_EN               BIT_(0)
+
+// Timer control 64 bits
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_MODE_64BITS          BIT_(0)
+
+
+//=============================================================================
+// MAC
+//
+#if defined(CYGHWR_HAL_CORTEXM_A2FXXX_A2F200) || \
+           defined(CYGHWR_HAL_CORTEXM_A2FXXX_A2F500)
+
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0                         0x00
+#define CYGHWR_HAL_A2FXXX_MAC_CSR1                         0x08
+#define CYGHWR_HAL_A2FXXX_MAC_CSR2                         0x10
+#define CYGHWR_HAL_A2FXXX_MAC_CSR3                         0x18
+#define CYGHWR_HAL_A2FXXX_MAC_CSR4                         0x20
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5                         0x28
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6                         0x30
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7                         0x38
+#define CYGHWR_HAL_A2FXXX_MAC_CSR8                         0x40
+#define CYGHWR_HAL_A2FXXX_MAC_CSR9                         0x48
+#define CYGHWR_HAL_A2FXXX_MAC_CSR10                        0x50
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11                        0x58
+
+// Bus Mode Register (CSR0)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_CLEAR                   0xFE000000
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_SPD                     BIT_(21)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_DBO                     BIT_(20)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_TAP(_x)                 VALUE_(17, (_x & 0x7))
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_PBL(_x)                 VALUE_(8, (_x & 0x2f))
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_BLE                     BIT_(7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_DSL(_x)                 VALUE_(2, (_x & 0x1f))
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_BAR                     BIT_(1)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_SWR                     BIT_(0)
+
+// Transmit Poll Demand Register (CSR1)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR1_TPD(_x)                 VALUE_(0, _x)
+
+// Receive Poll Demand Register (CSR2)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR2_RPD(_x)                 VALUE_(0, _x)
+
+// Receive Descriptor List Base Address Register (CSR3)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR3_RLA(_x)                 VALUE_(0, _x)
+
+// Transmit Descriptor List Base Address Register (CSR4)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR4_TLA(_x)                 VALUE_(0, _x)
+
+// Status and Control Register (CSR5)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_CLOSE_TXD            VALUE_(20, 0x7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_SUSPEND              VALUE_(20, 0x6)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_SETUP_PACKET         VALUE_(20, 0x5)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_XFER                 VALUE_(20, 0x3)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_WAIT_EOT             VALUE_(20, 0x2)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_FETCH_TXD            VALUE_(20, 0x1)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_STOP                 VALUE_(20, 0x0)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_MASK                 VALUE_(20, 0x7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_XFER                 VALUE_(17, 0x7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_CLOSE_RXD            VALUE_(17, 0x5)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_SUSPEND              VALUE_(17, 0x4)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_WAIT_PACKET          VALUE_(17, 0x3)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_WAIT_EOR             VALUE_(17, 0x2)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_FETCH_RXD            VALUE_(17, 0x1)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_STOP                 VALUE_(17, 0x0)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_MASK                 VALUE_(17, 0x7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_NIS                     BIT_(16)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_AIS                     BIT_(15)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_ERI                     BIT_(14)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_GTE                     BIT_(11)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_ETI                     BIT_(10)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RPS                     BIT_(8)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RU                      BIT_(7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RI                      BIT_(6)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_UNF                     BIT_(5)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TU                      BIT_(2)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TPS                     BIT_(1)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TI                      BIT_(0)
+
+// Define MAC state
+#define A2FXXX_MAC_TX_STATE(_x_)   CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_##_x_
+#define A2FXXX_MAC_RX_STATE(_x_)   CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_##_x_
+#define A2FXXX_MAC_TX_STATE_MASK                           VALUE_(20, 0x7)
+#define A2FXXX_MAC_RX_STATE_MASK                           VALUE_(17, 0x7)
+
+// Operation Mode Register (CSR6)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_CLEAR                   0xBF9F1D20
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_RA                      BIT_(30)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_TTM                     BIT_(22)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_SF                      BIT_(21)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_TR(_x)                  VALUE_(14, _x)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_ST                      BIT_(13)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_FD                      BIT_(9)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_PM                      BIT_(7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_PR                      BIT_(6)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_IF                      BIT_(4)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_PB                      BIT_(3)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_HO                      BIT_(2)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_SR                      BIT_(1)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_HP                      BIT_(0)
+
+// Interrupt Enable Register (CSR7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_NIE                     BIT_(16)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_AIE                     BIT_(15)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_ERE                     BIT_(14)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_GTE                     BIT_(11)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_ETE                     BIT_(10)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_RSE                     BIT_(8)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_RUE                     BIT_(7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_RIE                     BIT_(6)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_UNE                     BIT_(5)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_TUE                     BIT_(2)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_TSE                     BIT_(1)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_TIE                     BIT_(0)
+
+// Missed Frames and Overflow Counter Register (CSR8)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR8_OCO                     BIT_(28)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR8_MFO                     BIT_(16)
+
+// RMII Management Interface Register (CSR9)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR9_MDI                     BIT_(19)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR9_MDEN                    BIT_(18)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR9_MDO                     BIT_(17)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR9_MDC                     BIT_(16)
+
+// General-Purpose Timer and Interrupt Mitigation Control Register (CSR11)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11_CS                     BIT_(31)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11_TT(_x)                 VALUE_(27, (_x & 0xf))
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11_NTP(_x)                VALUE_(24, (_x & 0x7))
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11_RT(_x)                 VALUE_(20, (_x & 0xf))
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11_NRP(_x)                VALUE_(17, (_x & 0x7))
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11_CON                    BIT_(16)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11_TIM(_x)                VALUE_(0, _x)
+
+// Receive Descriptors (RDESx)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_OWN                    BIT_(31)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_FF                     BIT_(30)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_FL(_x)                 VALUE_(16, _x)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_ES                     BIT_(15)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_DE                     BIT_(14)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_RF                     BIT_(11)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_MF                     BIT_(10)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_FS                     BIT_(9)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_LS                     BIT_(8)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_TL                     BIT_(7)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_CS                     BIT_(6)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_FT                     BIT_(5)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_RE                     BIT_(3)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_DB                     BIT_(2)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_CE                     BIT_(1)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_ZERO                   BIT_(0)
+
+#define CYGHWR_HAL_A2FXXX_MAC_RDES1_RER                    BIT_(25)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES1_RCH                    BIT_(24)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES1_RBS2(_x)               VALUE_(11, _x)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES1_RBS1(_x)               VALUE_(0, _x)
+
+// Receive Descriptors (TDESx)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_OWN                    BIT_(31)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_ES                     BIT_(15)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_LO                     BIT_(11)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_NC                     BIT_(10)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_LC                     BIT_(9)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_EC                     BIT_(8)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_CC(_x)                 VALUE_(3, _x)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_UF                     BIT_(1)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_DE                     BIT_(0)
+
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_IC                     BIT_(31)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_LS                     BIT_(30)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_FS                     BIT_(29)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_FT1                    BIT_(28)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_SET                    BIT_(27)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_AC                     BIT_(26)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_TER                    BIT_(25)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_TCH                    BIT_(24)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_DPD                    BIT_(23)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_FT0                    BIT_(22)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_TBS2(_x)               VALUE_(11, _x)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_TBS1(_x)               VALUE_(0, _x)
+
+#define CYGHWR_HAL_A2FXXX_MAC0_MDIO   CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_MDIO,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_MDC    CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_MDC,   DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_TXD0   CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_TXD0,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_TXD1   CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_TXD1,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_RXD0   CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_RXD0,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_RXD1   CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_RXD1,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_TXEN   CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_TXEN,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_CRSDV  CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_CRSDV, DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_RXER   CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_RXER,  DISABLE )
+
+#endif
+
+//=============================================================================
+// Spare page
+
+#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_KEY       0x081C
+#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_VERSION   0x0840
+#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_1_3_FCLK  0x162C
+#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_2_x_FCLK  0x1EAC
+
+// System boot key value
+#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_KEY_VALUE 0x4C544341
+
+// System boot version
+#define CYGHWR_HAL_A2FXXX_SYSBOOT_VERSION(_x, _y, _z)        ((_x << 16) | (_y << 8) | (_z))
+
+#define CYGHWR_HAL_A2FXXX_GET_SYSBOOT_VERSION()                                      \
+({                                                                                   \
+   cyg_uint32 _i;                                                                    \
+   cyg_uint32 base = CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES;                             \
+   HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_VERSION, _i);  \
+   _i;                                                                               \
+})
+
+#define CYGHWR_HAL_A2FXXX_GET_SYSBOOT_KEY()                                          \
+({                                                                                   \
+   cyg_uint32 _i;                                                                    \
+   cyg_uint32 base = CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES;                             \
+   HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_KEY, _i);      \
+   _i;                                                                               \
+})
+
+#define CYGHWR_HAL_A2FXXX_GET_SYSBOOT_1_3_FCLK()                                     \
+({                                                                                   \
+   cyg_uint32 _i;                                                                    \
+   cyg_uint32 base = CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES;                             \
+   HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_1_3_FCLK, _i); \
+   _i;                                                                               \
+})
+
+#define CYGHWR_HAL_A2FXXX_GET_SYSBOOT_2_0_FCLK()                                     \
+({                                                                                   \
+   cyg_uint32 _i;                                                                    \
+   cyg_uint32 base = CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES;                             \
+   HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_2_x_FCLK, _i); \
+   _i;                                                                               \
+})
+
+#define CYGHWR_HAL_A2FXXX_BITSET                           0x1
+#define CYGHWR_HAL_A2FXXX_BITCLEAR                         0x0
+//
+//-----------------------------------------------------------------------------
+// end of var_io.h
+#endif // CYGONCE_HAL_VAR_IO_H
diff --git a/packages/hal/cortexm/a2fxxx/var/current/include/variant.inc b/packages/hal/cortexm/a2fxxx/var/current/include/variant.inc
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/var/current/include/variant.inc
@@ -0,0 +1,54 @@
+/*==========================================================================
+//
+//      variant.inc
+//
+//      Variant specific asm definitions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Date:         2008-07-30
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal_cortexm_a2fxxx.h>
+
+//==========================================================================
+// EOF variant.inc
+
diff --git a/packages/hal/cortexm/a2fxxx/var/current/src/a2fxxx_misc.c b/packages/hal/cortexm/a2fxxx/var/current/src/a2fxxx_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/var/current/src/a2fxxx_misc.c
@@ -0,0 +1,1214 @@
+/*==========================================================================
+//
+//      a2f_misc.c
+//
+//      Cortex-M Actel A2F HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors:
+// Date:         2011-02-03
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_a2fxxx.h>
+
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+
+
+//==========================================================================
+// Clock Initialization values
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK
+
+#define CLKx_SRC_CLKA    0
+#define CLKx_SRC_CLKB    1
+#define CLKx_SRC_CLKC    2
+#define CLKx_SRC_CLKGA   3
+#define CLKx_SRC_CLKGB   4
+#define CLKx_SRC_CLKGC   5
+#define CLKx_SRC_CLKGINT 6
+
+#define CLKx_SRC_UIN     0
+#define CLKx_SRC_DIP     1
+#define CLKx_SRC_UIP     4
+#define CLKx_SRC_GLxINT  5
+#define CLKx_SRC_RCOSC   2
+#define CLKx_SRC_MOSC    6
+#define CLKx_SRC_32KOSC  6
+
+// Select source of CLKA
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC_AUIN
+# define CLKA_SRC_SEL CLKx_SRC_UIN
+#elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC_AUIP)
+# define CLKA_SRC_SEL CLKx_SRC_UIP
+#elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC_ADIP)
+# define CLKA_SRC_SEL CLKx_SRC_DIP
+#elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC_GLAINT)
+# define CLKA_SRC_SEL CLKx_SRC_GLxINT
+#elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC_RCOSC)
+# define CLKA_SRC_SEL CLKx_SRC_RCOSC
+#else
+# define CLKA_SRC_SEL CLKx_SRC_MOSC
+#endif
+
+// Select source of CLKB
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKB
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC_BUIN
+#  define CLKB_SRC_SEL CLKx_SRC_UIN
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC_BUIP)
+#  define CLKB_SRC_SEL CLKx_SRC_UIP
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC_BDIP)
+#  define CLKB_SRC_SEL CLKx_SRC_DIP
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC_GLBINT)
+#  define CLKB_SRC_SEL CLKx_SRC_GLxINT
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC_RCOSC)
+#  define CLKB_SRC_SEL CLKx_SRC_RCOSC
+# else
+#  define CLKB_SRC_SEL CLKx_SRC_MOSC
+# endif
+#endif
+
+// Select source of CLKC
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKC
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC_CUIN
+#  define CLKC_SRC_SEL CLKx_SRC_UIN
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC_CUIP)
+#  define CLKC_SRC_SEL CLKx_SRC_UIP
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC_CDIP)
+#  define CLKC_SRC_SEL CLKx_SRC_DIP
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC_GLCINT)
+#  define CLKC_SRC_SEL CLKx_SRC_GLxINT
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC_RCOSC)
+#  define CLKC_SRC_SEL CLKx_SRC_RCOSC
+# else
+#  define CLKC_SRC_SEL CLKx_SRC_32KOSC
+# endif
+#endif
+
+// Select source of CLKGA
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC_CLKA
+#  define CLKGA_SRC_SEL 1
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC_PLL_VCO0)
+#  define CLKGA_SRC_SEL 4
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC_PLL_VCO90)
+#  define CLKGA_SRC_SEL 5
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC_PLL_VCO180)
+#  define CLKGA_SRC_SEL 6
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC_PLL_VCO270)
+#  define CLKGA_SRC_SEL 7
+# else
+#  define CLKGA_SRC_SEL 2
+# endif
+#endif
+
+// Select source of CLKGB
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_CLKB
+#  define CLKGB_SRC_SEL 1
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_CLKGA
+#  define CLKGB_SRC_SEL 3
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_PLL_VCO0)
+#  define CLKGB_SRC_SEL 4
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_PLL_VCO90)
+#  define CLKGB_SRC_SEL 5
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_PLL_VCO180)
+#  define CLKGB_SRC_SEL 6
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_PLL_VCO270)
+#  define CLKGB_SRC_SEL 7
+# else
+#  define CLKGB_SRC_SEL 2
+# endif
+#endif
+
+// Select source of CLKGC
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_CLKC
+#  define CLKGC_SRC_SEL 1
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_CLKGA)
+#  define CLKGC_SRC_SEL 3
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_PLL_VCO0)
+#  define CLKGC_SRC_SEL 4
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_PLL_VCO90)
+#  define CLKGC_SRC_SEL 5
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_PLL_VCO180)
+#  define CLKGC_SRC_SEL 6
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_PLL_VCO270)
+#  define CLKGC_SRC_SEL 7
+# else
+#  define CLKGC_SRC_SEL 2
+# endif
+#endif
+
+#if CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_DIV   == 1
+# define PCLK0DIV 0
+#elif CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_DIV == 2
+# define PCLK0DIV 1
+#else
+# define PCLK0DIV 2
+#endif
+
+#if CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_DIV   == 1
+# define PCLK1DIV 0
+#elif CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_DIV == 2
+# define PCLK1DIV 1
+#else
+# define PCLK1DIV 2
+#endif
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_ACE_CLK
+# if CYGHWR_HAL_CORTEXM_A2FXXX_ACLK_DIV   == 1
+#  define ACLKDIV 0
+# elif CYGHWR_HAL_CORTEXM_A2FXXX_ACLK_DIV == 2
+#  define ACLKDIV 1
+# else
+#  define ACLKDIV 2
+# endif
+#endif
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_PLL
+# if CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ   < 43750000
+#  define PLL_RANGE 0
+# elif CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ < 87500000
+#  define PLL_RANGE 1
+# elif CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ < 175000000
+#  define PLL_RANGE 2
+# else
+#  define PLL_RANGE 3
+# endif
+#endif
+
+#define OXDIV_CLEAR 0x1F
+#define OXMUX_CLEAR 0x07
+#define DLYX_CLEAR  0x1F
+#define DIV_CLEAR   0x03
+
+#endif // CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK
+
+//==========================================================================
+// IO settings
+
+#ifdef CYGPKG_HAL_CORTEXM_A2FXXX_IO
+
+# if defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_WEST_BANK_LVCMOS_3V3)
+# define IO_WEST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTWEST(LVCMOS_3V3)
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_WEST_BANK_LVCMOS_2V5)
+# define IO_WEST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTWEST(LVCMOS_2V5)
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_WEST_BANK_LVCMOS_1V8)
+# define IO_WEST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTWEST(LVCMOS_1V8)
+# else
+# define IO_WEST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTWEST(LVCMOS_1V5)
+# endif
+
+# if defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_EAST_BANK_LVCMOS_3V3)
+# define IO_EAST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTEAST(LVCMOS_3V3)
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_EAST_BANK_LVCMOS_2V5)
+# define IO_EAST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTEAST(LVCMOS_2V5)
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_EAST_BANK_LVCMOS_1V8)
+# define IO_EAST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTEAST(LVCMOS_1V8)
+# else
+# define IO_EAST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTEAST(LVCMOS_1V5)
+# endif
+
+#endif // CYGPKG_HAL_CORTEXM_A2FXXX_IO
+
+
+#ifdef CYGSEM_HAL_CORTEXM_A2FXXX_CLOCK_CHATTER
+# define A2FXXX_CLOCK_TRACE(args...)   diag_printf(args)
+#else
+# define A2FXXX_CLOCK_TRACE(args...)    /* NOOP */
+#endif
+
+
+//==========================================================================
+// Clock frequencies
+//
+// These are set to the frequencies of the various system clocks.
+
+cyg_uint32 hal_a2fxxx_pclk0;           // Peripheral clock (connected to APB_0)
+cyg_uint32 hal_a2fxxx_pclk1;           // Peripheral clock (connected to APB_1)
+cyg_uint32 hal_a2fxxx_aclk;            // Analog Peripheral clock (ADC /DAC etc..)
+cyg_uint32 hal_a2fxxx_pclk_fpga;       // FPGA clock
+
+cyg_uint32 hal_a2fxxx_glb;             // Global Clock B
+cyg_uint32 hal_a2fxxx_glc;             // Global Clock C
+
+cyg_uint32 hal_cortexm_systick_clock;  // NGMUx output or FCLK or SysTick clock
+cyg_uint32 hal_a2fxxx_fclk;            // FCLK
+
+
+//==========================================================================
+// Local prototypes
+
+static void hal_a2fxxx_clk_network_chatter( cyg_uint8 );
+
+static cyg_uint8 hal_start_clocks( void );
+static cyg_uint8 hal_a2fxxx_get_system_boot_clk( void );
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK
+static void hal_a2fxxx_set_clk_network( void );
+static void hal_a2fxxx_set_envm_timing( void );
+static void hal_a2fxxx_set_clkx( cyg_uint8 x, cyg_uint8 src );
+static void hal_a2fxxx_set_clkgx( cyg_uint8 x );
+static void hal_a2fxxx_set_clkgx_default( cyg_uint8 x );
+static void hal_a2fxxx_set_ngmux( cyg_uint8 );
+static cyg_uint8 hal_a2fxxx_get_ngmux( void );
+
+# if defined(CYGHWR_HAL_CORTEXM_A2FXXX_PLL)
+static inline void hal_a2fxxx_set_pll( void );
+# endif
+#endif
+
+
+//==========================================================================
+
+void
+hal_variant_init( void )
+{
+#if !defined(CYG_HAL_STARTUP_RAM)
+    cyg_uint8 sysboot_miss;
+#endif
+    cyg_uint32 base = CYGHWR_HAL_A2FXXX_WD;
+
+    // Disable Watch-dog
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_WD_ENABLE,
+                                           CYGHWR_HAL_A2FXXX_WD_DISABLE_KEY);
+
+#if !defined(CYG_HAL_STARTUP_RAM)
+    sysboot_miss = hal_start_clocks();
+#endif
+
+    // Release GPIO
+    CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(GPIO) );
+
+    // Setup IO banks
+#ifdef CYGPKG_HAL_CORTEXM_A2FXXX_IO
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR, (IO_WEST_BANK | IO_EAST_BANK) );
+#endif
+
+    // Reset UART0
+#if CYGINT_HAL_A2FXXX_UART0>0
+    CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(UART0) );
+#endif
+
+    // Reset UART1
+#if CYGINT_HAL_A2FXXX_UART1>0
+    CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(UART1) );
+#endif
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    hal_if_init();
+#endif
+
+#if !defined(CYG_HAL_STARTUP_RAM)
+    hal_a2fxxx_clk_network_chatter( sysboot_miss );
+#endif
+}
+
+//==========================================================================
+// Setup up system clocks
+//
+// Set up clocks from configuration. In the future this should be extended so
+// that clock rates can be changed at runtime.
+
+static cyg_uint8
+hal_start_clocks( void )
+{
+    if( ! hal_a2fxxx_get_system_boot_clk( ) )
+        return 0;
+
+    //
+    // User has chosen to re-configure the clock network and
+    // overwrite the settings provided by the system boot
+    //
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK
+    hal_a2fxxx_set_clk_network( );
+
+    // Adjust the ENVM timing according to the core clock
+    // frequency
+    hal_a2fxxx_set_envm_timing( );
+#endif
+
+    return 1;
+}
+
+
+//==========================================================================
+// Read clock configuration as setup by the system boot
+
+static cyg_uint8
+hal_a2fxxx_get_system_boot_clk( void )
+{
+    cyg_uint32 sysboot_key, sysboot_ver, clk_cr, clkga0;
+
+    sysboot_ver = CYGHWR_HAL_A2FXXX_GET_SYSBOOT_VERSION();
+    sysboot_key = CYGHWR_HAL_A2FXXX_GET_SYSBOOT_KEY();
+
+    // Verify that the system boot is present, if not we must give up?
+    if( CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_KEY_VALUE
+             != sysboot_key )
+       return 0;
+
+    // Read the MSS CLGA0 frequency value. Address varies with system boot
+    // version
+    if ( sysboot_ver < CYGHWR_HAL_A2FXXX_SYSBOOT_VERSION(2, 0, 0) ) {
+       clkga0 = CYGHWR_HAL_A2FXXX_GET_SYSBOOT_1_3_FCLK();
+    }
+    else {
+       clkga0 = CYGHWR_HAL_A2FXXX_GET_SYSBOOT_2_0_FCLK();
+    }
+
+    // Compute the BUS and fabric clock frequency
+    hal_cortexm_systick_clock = clkga0;
+
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR, clk_cr);
+
+    hal_a2fxxx_pclk0     =
+          clkga0 >> CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_PCLK0DIV( clk_cr );
+    hal_a2fxxx_pclk1     =
+          clkga0 >> CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_PCLK1DIV( clk_cr );
+    hal_a2fxxx_pclk_fpga =
+          clkga0 >> CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_GLBDIV( clk_cr );
+
+    return 1;
+}
+
+
+//==========================================================================
+// Chatter function
+
+static void
+hal_a2fxxx_clk_network_chatter( cyg_uint8 hal_clk_network_chatter )
+{
+    if ( hal_clk_network_chatter == 0 )
+        diag_printf("Actel System Boot Missing\n Clock network configuration failed!!\n");
+
+    A2FXXX_CLOCK_TRACE("Device clock network configuration:\n");
+    A2FXXX_CLOCK_TRACE("Global Clock A (Systick): %d [Hz]\n",
+                                                  hal_cortexm_systick_clock);
+    A2FXXX_CLOCK_TRACE("PCLK0: %d [Hz]\n", hal_a2fxxx_pclk0);
+    A2FXXX_CLOCK_TRACE("PCLK1: %d [Hz]\n", hal_a2fxxx_pclk1);
+}
+
+
+//==========================================================================
+// Setup device clock network
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK
+
+static void
+hal_a2fxxx_set_clk_network( void )
+{
+    cyg_uint32 mss_ccc_mux;
+    cyg_uint32 mss_clk_cr;
+    cyg_uint8  ngmux;
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_PLL
+    cyg_bool   pll = false;
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKA
+    cyg_bool  clka = false;
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKC
+    cyg_bool  clkc = false;
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA
+    cyg_bool  clkga = false;
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC
+    cyg_bool  clkgc = false;
+#endif
+
+    // Find out which CLKGx is currently used as FLCK
+    ngmux = hal_a2fxxx_get_ngmux( );
+
+    //
+    // Start by configuring NGMUX. In the following case, if
+    // the current NGMUX output is already CLKGA, first move
+    // to CLKGC to keep a stable ground otherwise go ahead and
+    // configure CLKGA.
+    //
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_CLKGA
+    if( ngmux == CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLA )
+    {
+        // Setup CLKGC to use the On-Chip RC oscillator and move
+        // the MSS clock to CLKGC. No division factor is applied
+        // therefore FCLK = 100MHz
+
+        // CLKC = RCOSC
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKx_SRC_RCOSC );
+
+        // CLKGC = CLKC
+        hal_a2fxxx_set_clkgx_default( CLKx_SRC_CLKGC );
+
+        // FCLK = CLKGC
+        hal_a2fxxx_set_ngmux( CLKx_SRC_CLKGC );
+    }
+    else {
+        HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                         CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+        mss_ccc_mux &= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(OXMUX_CLEAR);
+        mss_ccc_mux = mss_ccc_mux >> 19;
+
+        // Make sure PLL is bypassed.
+        if ( mss_ccc_mux != 1 ){
+            hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKx_SRC_RCOSC );
+            hal_a2fxxx_set_clkgx_default( CLKx_SRC_CLKGC );
+        }
+    }
+
+    // Now we can configure CLKGA as specified by the
+    // user. Check is PLL should be configured.
+    hal_a2fxxx_set_clkx( CLKx_SRC_CLKA, CLKA_SRC_SEL );
+
+# if defined(CYGHWR_HAL_CORTEXM_A2FXXX_PLL)
+    hal_a2fxxx_set_pll( );
+    pll = true;
+# endif
+
+    // Move to CLKGA
+    hal_a2fxxx_set_clkgx( CLKx_SRC_CLKGA );
+    clka = clkga = true;
+    hal_a2fxxx_set_ngmux( CLKx_SRC_CLKGA );
+
+#endif  // CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_CLKGA
+
+
+    //
+    // In the following case, NGMUX is configured to use CLKGC.
+    // This can be tricky as CLKGC can be routed from CLKGA...
+    //
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_CLKGC
+
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                           CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+    mss_ccc_mux &= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(OXMUX_CLEAR);
+    mss_ccc_mux = mss_ccc_mux >> 19;
+
+    // If CLKGC is not routed form CLKC or if CLKGC is not used
+    // as NGMUX output, proceed to configure CLKGC = CLKC
+    if( ((ngmux == CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLC) && (mss_ccc_mux != 1)) ||
+                (ngmux == CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLA) )
+    {
+
+        // Set CLKC source, use on-chip oscillator as default
+        // value
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_CLKC
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKC_SRC_SEL );
+        clkc = true;
+# else
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKx_SRC_RCOSC );
+# endif
+
+        // Set CLKGC = CLKC
+        hal_a2fxxx_set_clkgx_default( CLKx_SRC_CLKGC );
+
+        // Set NGMUX = CLKGC
+        hal_a2fxxx_set_ngmux( CLKx_SRC_CLKGC );
+
+        // Configure PLL input if in use
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_PLL
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKA, CLKA_SRC_SEL );
+        clka = true;
+# endif
+
+    }
+    else {
+
+        // Set CLKA source, use on-chip oscillator as default
+        // value
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKA
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKA, CLKA_SRC_SEL );
+        clka = true;
+# else
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKA, CLKx_SRC_RCOSC );
+# endif
+
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_CLKC
+        // CLKGA = CLKA
+        hal_a2fxxx_set_clkgx_default( CLKx_SRC_CLKGA );
+
+        // Move NGMUX = CLKGA
+        hal_a2fxxx_set_ngmux( CLKx_SRC_CLKGA );
+
+        // Now we can Configure CLKC
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKC_SRC_SEL );
+# endif
+
+    }
+
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_PLL
+    hal_a2fxxx_set_pll( );
+    pll = true;
+# endif
+
+    clkgc = true;
+    hal_a2fxxx_set_clkgx( CLKx_SRC_CLKGC );
+    hal_a2fxxx_set_ngmux( CLKx_SRC_CLKGC );
+
+#endif // CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_CLKGC
+
+
+    // Configure CLKA
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKA
+    if ( clka == false ){
+       hal_a2fxxx_set_clkx( CLKx_SRC_CLKA, CLKA_SRC_SEL );
+    }
+#endif
+
+    // Configure the PLL
+#if defined(CYGHWR_HAL_CORTEXM_A2FXXX_PLL)
+    if ( pll == false ){
+        hal_a2fxxx_set_pll( );
+    }
+#endif
+
+    // Configure CLKB
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKB
+    hal_a2fxxx_set_clkx( CLKx_SRC_CLKB, CLKB_SRC_SEL );
+#endif
+
+    // Configure CLKC
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKC
+    if ( clkc == false ){
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKC_SRC_SEL );
+    }
+#endif
+
+    // Configure CLKGA
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA
+    if ( clkga == false ){
+        hal_a2fxxx_set_clkgx( CLKx_SRC_CLKA );
+    }
+#endif
+
+    // Configure CLKGB
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB
+    hal_a2fxxx_set_clkgx( CLKx_SRC_CLKB );
+#endif
+
+    // Configure CLKGC
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC
+    if ( clkgc == false ){
+        hal_a2fxxx_set_clkgx( CLKx_SRC_CLKC );
+    }
+#endif
+
+    // Now, configure all MSS clock dividers
+    //
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                           CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                           CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR, mss_clk_cr);
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_ACE_CLK
+    mss_clk_cr &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_ACLKDIV(DIV_CLEAR) );
+    mss_clk_cr |=  ( CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_ACLKDIV(ACLKDIV) );
+#endif
+
+    mss_clk_cr &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK1DIV(DIV_CLEAR) |
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK0DIV(DIV_CLEAR) );
+
+    mss_clk_cr |=  ( CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK1DIV(PCLK1DIV) |
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK0DIV(PCLK0DIV) );
+
+    // Record the different clock frequencies
+    hal_cortexm_systick_clock = CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ;
+    hal_a2fxxx_fclk  = CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ;
+    hal_a2fxxx_pclk0 = CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_FREQ;
+    hal_a2fxxx_pclk1 = CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_FREQ;
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK
+    hal_a2fxxx_pclk_fpga = CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_FREQ;
+#endif
+
+    // Configure the MAC clock
+#if defined(CYGHWR_HAL_CORTEXM_A2FXXX_MAC_CLK) && \
+          defined(CYGHWR_HAL_CORTEXM_A2FXXX_MAC_SRC_CLKGC)
+
+    mss_clk_cr |= CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_RMIICLKSEL;
+
+#elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_MAC_CLK) && \
+          defined(CYGHWR_HAL_CORTEXM_A2FXXX_MAC_SRC_EXTERNAL)
+
+    mss_clk_cr &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_RMIICLKSEL;
+
+#endif
+
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR,
+                      mss_clk_cr);
+
+    // PLL is disable if not in used
+#if !defined(CYGHWR_HAL_CORTEXM_A2FXXX_PLL)
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR, 0x0);
+#endif
+}
+
+
+//==========================================================================
+// Get / Set NGMUX settings
+
+static cyg_uint8
+hal_a2fxxx_get_ngmux( void )
+{
+    cyg_uint32 mss_ccc_mux;
+    cyg_uint8  ngmux_setting;
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+
+    mss_ccc_mux = mss_ccc_mux >> 24;
+    switch( mss_ccc_mux & 0xf ){
+    case  0:
+    case  2:
+    case  4:
+    case  6:
+    case 12:
+        ngmux_setting = CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLA;
+        break;
+    case  1:
+    case  3:
+    case  8:
+    case 10:
+    case 13:
+        ngmux_setting = CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLC;
+        break;
+    case  5:
+    case  7:
+    case  9:
+    case 11:
+    case 14:
+        ngmux_setting = CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLINT;
+        break;
+    default:
+        ngmux_setting = CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GND;
+        break;
+    }
+
+    return ngmux_setting;
+}
+
+
+static void
+hal_a2fxxx_set_ngmux( cyg_uint8 x )
+{
+    cyg_uint32 mss_ccc_mux;
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+
+    // Clear bits
+    mss_ccc_mux &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXSEL(0x3) |
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXCFG(0x3) );
+
+    if( x == CLKx_SRC_CLKGA ){
+        mss_ccc_mux |= ( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXSEL(0) |
+                         CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXCFG(0) );
+    }
+    else if (x == CLKx_SRC_CLKGC ){
+        mss_ccc_mux |= ( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXSEL(1) |
+                         CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXCFG(0) );
+    }
+    else{
+        mss_ccc_mux |= ( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXSEL(2) |
+                         CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXCFG(3) );
+    }
+
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+}
+
+
+//==========================================================================
+// Setup PLL
+
+#if defined(CYGHWR_HAL_CORTEXM_A2FXXX_PLL)
+static inline void
+hal_a2fxxx_set_pll( void )
+{
+    cyg_uint32 x =
+    CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FINDIV((CYGHWR_HAL_CORTEXM_A2FXXX_PLL_DIV-1)) |
+    CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBDIV((CYGHWR_HAL_CORTEXM_A2FXXX_PLL_MULT-1)) |
+    CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBSEL(1) |
+    CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBDLY(CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FB_DELAY) |
+    CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_VCOSEL0 |
+    CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_VCOSEL2_1(PLL_RANGE) |
+    CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_PLLEN;
+
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR, x);
+
+    // Wait PLL lock
+    do {
+        HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_SR, x);
+    } while( (x & CYGHWR_HAL_A2FXXX_SC_MSS_CCC_SR_PLL_LOCK_SYNC) == 0);
+}
+#endif
+
+
+//==========================================================================
+// Setup CLKA, CLKB or CLKC input clock
+
+static void
+hal_a2fxxx_set_clkx( cyg_uint8 x, cyg_uint8 src )
+{
+    cyg_uint32 mss_ccc_mux;
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+    if( x == CLKx_SRC_CLKA ){
+        mss_ccc_mux &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNASEL |
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXASEL  |
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATASEL );
+        mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKA_SEL (src);
+    }
+    else if (x == CLKx_SRC_CLKB ){
+        mss_ccc_mux &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNBSEL |
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXBSEL  |
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATBSEL );
+        mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKB_SEL (src);
+    }
+    else{
+        mss_ccc_mux &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNCSEL |
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXCSEL  |
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATCSEL );
+        mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKC_SEL (src);
+    }
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+}
+
+
+//==========================================================================
+// Setup CLKGA, CLKGB or CLKGC output clock
+
+static void
+hal_a2fxxx_set_clkgx( cyg_uint8 x )
+{
+    cyg_uint32 mss_ccc_mux;
+    cyg_uint32 mss_ccc_dly;
+    cyg_uint32 mss_ccc_div;
+    cyg_uint8  div10;
+    cyg_uint8  div;
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR, mss_ccc_dly);
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR, mss_ccc_div);
+
+    if( x == CLKx_SRC_CLKGA ){
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA
+        // Clear bits
+        mss_ccc_div &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIV(OXDIV_CLEAR) |
+                          CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIVHALF );
+        mss_ccc_dly &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA(DLYX_CLEAR);
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OAMUX(OXMUX_CLEAR);
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSA;
+        // Compute divider
+        div10 = CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV10;
+        div = (cyg_uint8) CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV;
+        if( div10 % 10 ){
+            div += 1;
+            mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIVHALF;
+        }
+        else {
+           div -= 1;
+        }
+        // CLKA = CLGA, bypass MUX
+        if (div == 0 && CLKGA_SRC_SEL == 1) {
+            mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSA;
+        }
+        else {
+            mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OAMUX(CLKGA_SRC_SEL);
+            mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIV(div);
+        }
+        mss_ccc_dly |=
+        CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DELAY);
+#endif
+    }
+    if ( x == CLKx_SRC_CLKGB ){
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB
+        // Clear bits
+        mss_ccc_div &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIV(OXDIV_CLEAR) |
+                          CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIVHALF );
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OBMUX(OXMUX_CLEAR);
+        mss_ccc_dly &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYB(DLYX_CLEAR);
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSB;
+        // Compute divider
+        div10 = CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV10;
+        div = (cyg_uint8) CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV;
+        if( div10 % 10 ){
+            div += 1;
+            mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIVHALF;
+        }
+        else {
+           div -= 1;
+        }
+        // CLKB = CLGB, bypass MUX
+        if (div == 0 && CLKGB_SRC_SEL == 1) {
+            mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSB;
+        }
+        else {
+            mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OBMUX(CLKGB_SRC_SEL);
+            mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIV(div);
+            mss_ccc_dly |=
+            CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYB(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DELAY);
+        }
+#endif
+    }
+    if ( x == CLKx_SRC_CLKGC ){
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC
+        // Clear bits
+        mss_ccc_div &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIV(OXDIV_CLEAR) |
+                          CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIVHALF );
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(OXMUX_CLEAR);
+        mss_ccc_dly &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYC(DLYX_CLEAR);
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSC;
+        // Compute divider
+        div10 = CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV10;
+        div = (cyg_uint8) CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV;
+        if( div10 % 10 ){
+            div += 1;
+            mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIVHALF;
+        }
+        else {
+           div -= 1;
+        }
+        // CLKC = CLGC, bypass MUX
+        if (div == 0 && CLKGC_SRC_SEL == 1) {
+            mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSC;
+        }
+        else {
+            mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(CLKGC_SRC_SEL);
+            mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIV(div);
+        }
+        mss_ccc_dly |=
+        CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYC(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DELAY);
+#endif
+    }
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR, mss_ccc_div);
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR, mss_ccc_dly);
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+}
+
+//==========================================================================
+// Setup CLKGA CLKGC output clock
+
+static void
+hal_a2fxxx_set_clkgx_default( cyg_uint8 x )
+{
+    cyg_uint32 mss_ccc_mux;
+    cyg_uint32 mss_ccc_dly;
+    cyg_uint32 mss_ccc_div;
+
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR, mss_ccc_dly);
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR, mss_ccc_div);
+
+    if( x == CLKx_SRC_CLKGA ){
+        // Clear bits
+        mss_ccc_div &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIV(OXDIV_CLEAR) |
+                          CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIVHALF );
+        mss_ccc_dly &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA(DLYX_CLEAR);
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OAMUX(OXMUX_CLEAR);
+        // CLKGA = CLKA, Division factor = 1 and minimum delay of 535ps
+        mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSA;
+        mss_ccc_dly |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA(0);
+    }
+    if ( x == CLKx_SRC_CLKGC ){
+        // Clear bits
+        mss_ccc_div &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIV(OXDIV_CLEAR) |
+                          CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIVHALF );
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(OXMUX_CLEAR);
+        mss_ccc_dly &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYC(DLYX_CLEAR);
+        // CLKGC = CLKC, Division factor = 1 and minimum delay of 535ps
+        mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSC;
+        mss_ccc_dly |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYC(0);
+    }
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR, mss_ccc_div);
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR, mss_ccc_dly);
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+}
+
+
+//==========================================================================
+// Adjust ENVM timing
+
+static void
+hal_a2fxxx_set_envm_timing( void ) {
+    cyg_uint32 x;
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_ENVM_CR, x);
+    x &= ~CYGHWR_HAL_A2FXXX_SC_ENVM_CR_SIX_CYCLE;
+    if( hal_a2fxxx_fclk <= 80e6 ){
+        x |= CYGHWR_HAL_A2FXXX_SC_ENVM_CR_PIPE_BYPASS;
+    } else {
+        x &= ~CYGHWR_HAL_A2FXXX_SC_ENVM_CR_PIPE_BYPASS;
+    }
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_ENVM_CR, x);
+}
+
+#endif // CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK
+
+
+//==========================================================================
+// Reset modules
+
+__externC void
+hal_a2fxxx_periph_release( cyg_uint32 bit )
+{
+    cyg_uint32 sc, base = CYGHWR_HAL_A2FXXX_SC;
+    HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR, sc );
+    sc &= ~( bit );
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR, sc );
+}
+
+
+__externC void
+hal_a2fxxx_periph_reset( cyg_uint32 bit )
+{
+    cyg_uint32 sc, base = CYGHWR_HAL_A2FXXX_SC;
+    HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR , sc );
+    sc |= ( bit );
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR , sc );
+}
+
+
+//==========================================================================
+// GPIO support
+//
+
+const default_io_mux_type default_io_mux[] = {
+   // SPI0
+   {0x00}, {0x0a}, {0x00}, {0x00},
+   // UART0
+   {0x18}, {0x00},
+   // I2C0
+   {0x00}, {0x00},
+   // SPI1
+   {0x00}, {0x0a}, {0x00}, {0x00},
+   // UART1
+   {0x18}, {0x00},
+   // I2C1
+   {0x00}, {0x00},
+   // MAC0
+   {0x18}, {0x18}, {0x0a}, {0x0a}, {0x18}, {0x0a}, {0x0a}, {0x00}, {0x18},
+   // GPIO
+   {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00},
+   {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00},
+   {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00},
+   {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00},
+   // SPI0 CS
+   {0x00}, {0x00}, {0x00},
+   // Unused
+   {0x00}, {0x00}, {0x00}, {0x00},
+   // UART0 misc
+   {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00},
+   // SPI1 CS
+   {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00},
+   // UART1 misc
+   {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00},
+   {0x0}
+};
+
+// These functions provide configuration and IO for GPIO pins.
+
+__externC void
+hal_a2fxxx_gpio_set( cyg_uint32 pin )
+{
+    cyg_uint32 bit  = CYGHWR_HAL_A2FXXX_GPIO_BIT( pin );
+    cyg_uint32 mode = CYGHWR_HAL_A2FXXX_GPIO_MODE( pin );
+    cyg_uint32 mux  = CYGHWR_HAL_A2FXXX_GPIO_IOMUX_IDX( pin );
+    cyg_uint32 irq  = CYGHWR_HAL_A2FXXX_GPIO_IRQ( pin );
+    cyg_uint32 reg    = 0;
+    cyg_uint32 io_mux = 0;
+
+    if (pin == CYGHWR_HAL_A2FXXX_GPIO_NONE)
+        return;
+
+    if(mode == CYGHWR_HAL_A2FXXX_GPIO_MODE_PERIPH){
+       // Set IOMUX default value for peripheral use
+       io_mux = default_io_mux[mux].val;
+       HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                         CYGHWR_HAL_A2FXXX_SC_IOMUX( mux ), io_mux );
+    } else {
+       // Set GPIO input/ output mode
+       if (mode == CYGHWR_HAL_A2FXXX_GPIO_MODE_OUT) {
+           reg = CYGHWR_HAL_A2FXXX_GPIO_CFG_GPOUTEN |
+                 CYGHWR_HAL_A2FXXX_GPIO_CFG_OUTBUFEN;
+       }
+
+       // Configure IO as interrupt
+       if (irq != CYGHWR_HAL_A2FXXX_GPIO_IRQ_DISABLE) {
+           reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_GPINTEN;
+           if(irq & CYGHWR_HAL_A2FXXX_GPIO_IRQ_FALLING_EDGE)
+              reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(0);
+           else if(irq & CYGHWR_HAL_A2FXXX_GPIO_IRQ_RISING_EDGE)
+              reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(1);
+           else if(irq & CYGHWR_HAL_A2FXXX_GPIO_IRQ_BOTH_EDGES)
+              reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(2);
+           else if(irq & CYGHWR_HAL_A2FXXX_GPIO_IRQ_LOW_LEVEL)
+              reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(3);
+           else
+              reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(4);
+       }
+
+       // Write down result
+       HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_MSS_GPIO +
+                       ( CYGHWR_HAL_A2FXXX_MSS_GPIO_CFG( bit ) ), reg );
+
+       // For GPIO 16 to 31, we must setup the IOMUX
+       // TODO, this is for output only?
+       if( bit > 15 ){
+          bit = bit - 16;
+          io_mux = 0x35;
+          HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                            CYGHWR_HAL_A2FXXX_SC_IOMUX( bit ), io_mux );
+       }
+
+    }
+}
+
+
+__externC void
+hal_a2fxxx_gpio_out( cyg_uint32 pin, int val )
+{
+    cyg_uint32 bit = ( CYGHWR_HAL_A2FXXX_GPIO_BIT(pin) << 2 );
+    cyg_uint32 port =  CYGHWR_HAL_A2FXXX_MSS_GPIO_BB +
+                     ( CYGHWR_HAL_A2FXXX_MSS_GPIO_DOUT << 5 );
+
+    port += bit;
+
+    HAL_WRITE_UINT32( port, val );
+}
+
+
+__externC void
+hal_a2fxxx_gpio_in ( cyg_uint32 pin, int *val )
+{
+    cyg_uint32 bit = ( CYGHWR_HAL_A2FXXX_GPIO_BIT(pin) << 2 );
+    cyg_uint32 port =  CYGHWR_HAL_A2FXXX_MSS_GPIO_BB +
+                     ( CYGHWR_HAL_A2FXXX_MSS_GPIO_DIN << 5 );
+    cyg_uint32 pd;
+
+    port += bit;
+
+    HAL_READ_UINT32( port, pd );
+    *val = 1 ? (bit & pd) : 0;
+}
+
+
+//==========================================================================
+// I2C clock rate
+//
+__externC cyg_uint32
+hal_a2fxxx_i2c_clock( cyg_uint32 base )
+{
+    return ( (base == CYGHWR_HAL_A2FXXX_I2C0) ? hal_a2fxxx_pclk0 : hal_a2fxxx_pclk1 );
+}
+
+
+//==========================================================================
+// SPI clock rate
+//
+__externC cyg_uint32
+hal_a2fxxx_spi_clock( cyg_uint32 base )
+{
+    return ( (base == CYGHWR_HAL_A2FXXX_SPI0) ? hal_a2fxxx_pclk0 : hal_a2fxxx_pclk1 );
+}
+
+
+//==========================================================================
+// UART baud rate
+//
+// Set the baud rate divider of a UART based on the requested rate and
+// the current APB clock settings.
+
+__externC void
+hal_a2fxxx_uart_setbaud(cyg_uint32 base, cyg_uint32 baud)
+{
+    cyg_uint16 divider =
+         CYG_HAL_CORTEXM_A2FXXX_BAUD_GENERATOR( ((base == CYGHWR_HAL_A2FXXX_UART0)? 0 : 1) , baud );
+
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_LCR,
+                                  CYGHWR_HAL_A2FXXX_UART16550_LCR_DLAB);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_DMR, divider >> 8);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_DLR, divider & 0xFF);
+}
+
+
+//==========================================================================
+// Idle thread
+//
+#ifdef CYGSEM_HAL_CORTEXM_A2FXXX_DEFINES_IDLE_THREAD_ACTION
+__externC void
+hal_idle_thread_action( cyg_uint32 count )
+{
+    while(1);
+}
+#endif
+
+//==========================================================================
+// EOF a2fxxx_misc.c
diff --git a/packages/hal/cortexm/a2fxxx/var/current/src/hal_diag.c b/packages/hal/cortexm/a2fxxx/var/current/src/hal_diag.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/var/current/src/hal_diag.c
@@ -0,0 +1,399 @@
+/*=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008, 2011
+// Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Original:    nickg (STM32 HAL)
+// Date:        2011-04-03
+// Purpose:     HAL diagnostic output
+// Description: Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing
+
+#include <cyg/hal/hal_arch.h>           // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_if.h>             // interface API
+#include <cyg/hal/hal_intr.h>           // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h>           // Helper functions
+#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
+
+#include <cyg/hal/var_io.h>             // USART registers
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+    cyg_uint32          uart;
+    CYG_ADDRESS         base;
+    cyg_int32           msec_timeout;
+    int                 isr_vector;
+    cyg_uint32          rxpin;
+    cyg_uint32          txpin;
+    cyg_uint32          baud_rate;
+    int                 irq_state;
+
+} channel_data_t;
+
+
+static channel_data_t a2fxxx_ser_channels[] = {
+#if CYGINT_HAL_A2FXXX_UART0>0
+    { 0,
+      CYGHWR_HAL_A2FXXX_UART0,
+      1000,
+      CYGNUM_HAL_INTERRUPT_UART0,
+      CYGHWR_HAL_A2FXXX_UART0_RX,
+      CYGHWR_HAL_A2FXXX_UART0_TX,
+      CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+#if CYGINT_HAL_A2FXXX_UART1>0
+    { 1,
+      CYGHWR_HAL_A2FXXX_UART1,
+      1000,
+      CYGNUM_HAL_INTERRUPT_UART1,
+      CYGHWR_HAL_A2FXXX_UART1_RX,
+      CYGHWR_HAL_A2FXXX_UART1_TX,
+      CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+};
+
+//-----------------------------------------------------------------------------
+
+static void
+hal_a2fxxx_serial_init_channel(void* __ch_data)
+{
+    channel_data_t *chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS base = chan->base;
+    cyg_uint32 lcr = CYGHWR_HAL_A2FXXX_UART16550_LCR_WLS_8BITS |
+                     CYGHWR_HAL_A2FXXX_UART16550_LCR_STOP_1;
+
+    // Enable the PIO lines for the serial channel
+    CYGHWR_HAL_A2FXXX_GPIO_SET( chan->rxpin );
+    CYGHWR_HAL_A2FXXX_GPIO_SET( chan->txpin );
+
+    // Set baud rate
+    hal_a2fxxx_uart_setbaud( base, chan->baud_rate );
+
+    // 8-1-no parity
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_A2FXXX_UART16550_LCR, lcr );
+
+    // Reset and clear TX/RX FIFO
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_A2FXXX_UART16550_FCR,
+                     CYGHWR_HAL_A2FXXX_UART16550_FCR_CLEAR_TX_FIFO |
+                     CYGHWR_HAL_A2FXXX_UART16550_FCR_CLEAR_RX_FIFO );
+
+}
+
+void
+hal_a2fxxx_serial_putc(void *__ch_data, char c)
+{
+    CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint32 lsr;
+    CYGARC_HAL_SAVE_GP();
+
+     do
+     {
+         HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_LSR, lsr );
+     } while ((lsr & CYGHWR_HAL_A2FXXX_UART16550_LSR_THRE) == 0);
+
+     HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_THR, c );
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool
+hal_a2fxxx_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+    CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint32 lsr;
+    cyg_uint32 c;
+    CYGARC_HAL_SAVE_GP();
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_LSR, lsr );
+
+    if( (lsr & CYGHWR_HAL_A2FXXX_UART16550_LSR_DR) == 0 )
+        return false;
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_RBR, c );
+
+    *ch = (cyg_uint8)c;
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return true;
+}
+
+cyg_uint8
+hal_a2fxxx_serial_getc(void* __ch_data)
+{
+    cyg_uint8 ch;
+    CYGARC_HAL_SAVE_GP();
+
+    while(!hal_a2fxxx_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+    return ch;
+}
+
+//=============================================================================
+// Virtual vector HAL diagnostics
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+static void
+hal_a2fxxx_serial_write(void* __ch_data, const cyg_uint8* __buf,
+                         cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        hal_a2fxxx_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+hal_a2fxxx_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        *__buf++ = hal_a2fxxx_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool
+hal_a2fxxx_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+    int delay_count;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_bool res;
+    CYGARC_HAL_SAVE_GP();
+
+    delay_count = chan->msec_timeout * 100; // delay in 10 us steps
+
+    for(;;) {
+        res = hal_a2fxxx_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+
+        CYGACC_CALL_IF_DELAY_US(10);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static int
+hal_a2fxxx_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base;
+    int ret = 0;
+    cyg_uint32 ier;
+
+    va_list ap;
+
+    CYGARC_HAL_SAVE_GP();
+
+    va_start(ap, __func);
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        chan->irq_state = 1;
+        HAL_INTERRUPT_ACKNOWLEDGE( chan->isr_vector );
+        HAL_INTERRUPT_UNMASK( chan->isr_vector );
+        HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_IER, ier );
+        ier |= CYGHWR_HAL_A2FXXX_UART16550_IER_ERBFI;
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_IER, ier );
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = chan->irq_state;
+        chan->irq_state = 0;
+        HAL_INTERRUPT_MASK( chan->isr_vector );
+        HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_IER, ier );
+        ier &= ~CYGHWR_HAL_A2FXXX_UART16550_IER_ERBFI;
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_IER, ier );
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+    {
+        va_list ap;
+
+        va_start(ap, __func);
+
+        ret = chan->msec_timeout;
+        chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+        va_end(ap);
+    }
+    case __COMMCTL_GETBAUD:
+        ret = chan->baud_rate;
+        break;
+    case __COMMCTL_SETBAUD:
+        chan->baud_rate = va_arg(ap, cyg_int32);
+        // Should we verify this value here?
+        hal_a2fxxx_uart_setbaud( base, chan->baud_rate );
+        ret = 0;
+        break;
+    default:
+        break;
+    }
+    va_end(ap);
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int
+hal_a2fxxx_serial_isr(void *__ch_data, int* __ctrlc,
+                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_uint8 ch;
+
+    CYGARC_HAL_SAVE_GP();
+
+     *__ctrlc = 0;
+
+     if( hal_a2fxxx_serial_getc_nonblock(__ch_data, &ch) )
+     {
+         if( cyg_hal_is_break( (char *)&ch , 1 ) )
+             *__ctrlc = 1;
+     }
+
+    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+
+    CYGARC_HAL_RESTORE_GP();
+    return 1;
+}
+
+static void
+hal_a2fxxx_serial_init(void)
+{
+    hal_virtual_comm_table_t* comm;
+    int cur;
+    int i;
+
+    cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    for( i = 0; i < CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS ; i++ )
+    {
+        hal_a2fxxx_serial_init_channel(&a2fxxx_ser_channels[i]);
+
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+        comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+        CYGACC_COMM_IF_CH_DATA_SET(*comm, &a2fxxx_ser_channels[i]);
+        CYGACC_COMM_IF_WRITE_SET(*comm, hal_a2fxxx_serial_write);
+        CYGACC_COMM_IF_READ_SET(*comm, hal_a2fxxx_serial_read);
+        CYGACC_COMM_IF_PUTC_SET(*comm, hal_a2fxxx_serial_putc);
+        CYGACC_COMM_IF_GETC_SET(*comm, hal_a2fxxx_serial_getc);
+        CYGACC_COMM_IF_CONTROL_SET(*comm, hal_a2fxxx_serial_control);
+        CYGACC_COMM_IF_DBG_ISR_SET(*comm, hal_a2fxxx_serial_isr);
+        CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, hal_a2fxxx_serial_getc_timeout);
+    }
+
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+
+    // set debug channel baud rate if different
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD)
+    a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate =
+        CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD;
+    update_baud_rate( &a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL] );
+#endif
+
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+
+    if (initialized)
+        return;
+
+    initialized = 1;
+
+    hal_a2fxxx_serial_init();
+}
+
+#endif
+
+//=============================================================================
+// Non-Virtual vector HAL diagnostics
+
+#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+void
+hal_a2fxxx_diag_init(void)
+{
+    hal_a2fxxx_serial_init(
+            &a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] );
+}
+
+void
+hal_a2fxxx_diag_putc(char c)
+{
+    hal_a2fxxx_serial_putc(
+            &a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c);
+}
+
+cyg_uint8
+hal_a2fxxx_diag_getc(void)
+{
+    return hal_a2fxxx_serial_getc(
+            &a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] );
+}
+
+
+#endif
+
+//-----------------------------------------------------------------------------
+// End of hal_diag.c
diff --git a/packages/hal/cortexm/a2fxxx/var/current/src/hal_dma.c b/packages/hal/cortexm/a2fxxx/var/current/src/hal_dma.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/var/current/src/hal_dma.c
@@ -0,0 +1,427 @@
+/*==========================================================================
+//
+//      hal_dma.c
+//
+//      Cortex-M Actel A2F DMA channels configuration
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors:
+// Date:         2011-02-03
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_a2fxxx.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+#include <cyg/hal/drv_api.h>
+
+#ifdef CYGDBG_HAL_CORTEXM_A2FXXX_DMA_TRACE
+# define DMA_TRACE(args...) diag_printf(args)
+#else
+# define DMA_TRACE(args...)
+#endif
+
+//-----------------------------------------------------------------------------
+// DMA channel ISR/DSR handling
+
+typedef struct a2fxxx_dma_ch {
+    cyg_ISR_t*      isr;
+    cyg_DSR_t*      dsr;
+    cyg_uint32      isr_ret;
+    cyg_addrword_t  data;
+} a2fxxx_dma_ch;
+
+typedef struct a2fxxx_dma_info {
+    cyg_uint32      init;
+    cyg_uint32      base;
+    cyg_handle_t    interrupt_handle;
+    cyg_interrupt   interrupt_data;
+    a2fxxx_dma_ch   ch[CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL];
+    cyg_uint32      dma_cr[CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL];
+    cyg_uint32      dma_sr;
+} a2fxxx_dma_info;
+
+static a2fxxx_dma_info a2fxxx_dma = {
+    .base = CYGHWR_HAL_A2FXXX_DMA,
+    .init =0,
+};
+
+
+//-----------------------------------------------------------------------------
+// DMA ISR handler
+
+static cyg_uint32
+a2fxxx_dma_isr (cyg_vector_t vector, cyg_addrword_t data)
+{
+    a2fxxx_dma_info *dma = (a2fxxx_dma_info *) data;
+    cyg_uint32 sr = 0;
+    cyg_uint8 i = 0, j = 0;
+
+    HAL_READ_UINT32(dma->base + CYGHWR_HAL_A2FXXX_DMA_BUFFER_STATUS, sr);
+    dma->dma_sr |= sr;
+
+    DMA_TRACE("DMA interrupt, sr 0x%x\n", dma->dma_sr);
+
+    while(i < 16){
+        if( sr & 0x1 ){
+            j = i >> 1;
+            if(dma->ch[j].isr != NULL){
+              dma->ch[j].isr_ret = dma->ch[j].isr(i, dma->ch[j].data);
+            }
+        }
+        sr = sr >> 1; i++;
+    }
+    cyg_drv_interrupt_acknowledge (CYGNUM_HAL_INTERRUPT_DMA);
+    cyg_drv_interrupt_mask (CYGNUM_HAL_INTERRUPT_DMA);
+    return (CYG_ISR_CALL_DSR | CYG_ISR_HANDLED);
+}
+
+
+//-----------------------------------------------------------------------------
+// DMA DSR handler
+
+static void
+a2fxxx_dma_dsr (cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
+{
+    a2fxxx_dma_info *dma = (a2fxxx_dma_info *) data;
+    cyg_uint8 i = 0, j = 0;
+    cyg_uint32 sr;
+
+    cyg_drv_isr_lock ();
+    sr = dma->dma_sr;
+    dma->dma_sr = 0;
+    cyg_drv_isr_unlock ();
+
+    while(i < 16){
+        if( sr & 0x1 ){
+            j = i >> 1;
+            if( (dma->ch[j].dsr != NULL) &&
+                           (dma->ch[j].isr_ret & CYG_ISR_CALL_DSR) ){
+                dma->ch[j].dsr(i, 0, dma->ch[j].data);
+            }
+        }
+        sr = sr >> 1; i++;
+    }
+
+    cyg_drv_interrupt_unmask (CYGNUM_HAL_INTERRUPT_DMA);
+}
+
+
+//-----------------------------------------------------------------------------
+// DMA Initialization
+
+void
+hal_dma_init( void )
+{
+    cyg_uint8 i = 0;
+
+    // Avoid multiple initialization
+    if(a2fxxx_dma.init)
+        return;
+
+    a2fxxx_dma.init = 1;
+
+    // Reset DMA
+    CYGHWR_HAL_A2FXXX_PERIPH_RESET( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(PDMA) );
+
+    // Clear channel ISR / DSR
+    while( i < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL ) {
+        a2fxxx_dma.ch[i].isr    = NULL;
+        a2fxxx_dma.ch[i].dsr    = NULL;
+        a2fxxx_dma.dma_cr[i]    = 0;
+        a2fxxx_dma.ch[i++].data = 0;
+    }
+    a2fxxx_dma.dma_sr = 0;
+
+    // Register DMA interrupt
+    cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_DMA,
+                           CYGNUM_HAL_CORTEXM_A2FXXX_DMA_ISR_PRIORITY,
+                           (cyg_addrword_t)&a2fxxx_dma,
+                           &a2fxxx_dma_isr,
+                           &a2fxxx_dma_dsr,
+                           &(a2fxxx_dma.interrupt_handle),
+                           &(a2fxxx_dma.interrupt_data));
+    cyg_drv_interrupt_attach(a2fxxx_dma.interrupt_handle);
+    cyg_drv_interrupt_acknowledge (CYGNUM_HAL_INTERRUPT_DMA);
+    cyg_drv_interrupt_unmask (CYGNUM_HAL_INTERRUPT_DMA);
+
+    // Release DMA
+    CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(PDMA) );
+
+    // HW initialization
+    i=0;
+    while( i < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL ) {
+        HAL_WRITE_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(i++),
+                         CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_RESET);
+    }
+}
+
+
+//-----------------------------------------------------------------------------
+// Register the DMA sub-channel ISR / DSR
+
+__externC cyg_uint32
+a2fxxx_dma_ch_attach(cyg_uint8 ch, cyg_ISR_t *isr, cyg_DSR_t *dsr,
+                     cyg_addrword_t data)
+{
+    cyg_uint32 res = 1;
+
+    CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL,
+                         "DMA : Channel number out of range (Attach).");
+
+#ifdef CYGPKG_KERNEL
+    cyg_interrupt_disable();
+#endif
+    if( a2fxxx_dma.ch[ch].isr != NULL ||
+        a2fxxx_dma.ch[ch].dsr != NULL || a2fxxx_dma.ch[ch].data != 0 ) {
+        res = 0;
+    } else {
+        a2fxxx_dma.ch[ch].isr  = isr;
+        a2fxxx_dma.ch[ch].dsr  = dsr;
+        a2fxxx_dma.ch[ch].data = data;
+    }
+#ifdef CYGPKG_KERNEL
+    cyg_interrupt_enable();
+#endif
+
+    return res;
+}
+
+
+//-----------------------------------------------------------------------------
+// Update DMA source / destination address increment
+
+__externC void
+a2fxxx_dma_update_incr(cyg_uint8 ch, cyg_bool dst, cyg_uint8 incr)
+{
+    CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL,
+                          "DMA : Channel number out of range (Update).");
+
+    if(dst==false){
+        // Clear bits
+        a2fxxx_dma.dma_cr[ch] &= ~CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR_4B;
+        a2fxxx_dma.dma_cr[ch] |= CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR(incr);
+    }
+    else {
+        // Clear bits
+        a2fxxx_dma.dma_cr[ch] &= ~CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR_4B;
+        a2fxxx_dma.dma_cr[ch] |= CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR(incr);
+    }
+}
+
+
+//-----------------------------------------------------------------------------
+// Setup DMA channel
+//
+// channel      select the DMA channel ID.
+// type         select the transfer type to be performed. For valid
+//              values, check CYGHWR_HAL_A2FXXX_DMA_XFER(_x) in var_io.h.
+// outbound     set to true for transfer out of memory, false for transfer to
+//              memory
+// src_incr     select the memory address increment step for the source. Valid
+//              values are 0, 1, 2 and 4 byte(s). 0 can be used for DMA
+//              transfer from peripheral FIFO for instance.
+// dst_incr     select the memory address increment step for the destination.
+//              Valid values are 0, 1, 2 and 4 byte(s). 0 can be used for DMA
+//              transfer to peripheral FIFO for instance.
+// pri          select the DMA channel priority (true = high , false = low)
+// wr_adj       indicates the number of FCLK periods which the PDMA must wait
+//              after completion of a read or write access to a peripheral before
+//              evaluating the out-of-band status signals from that peripheral
+//              for another transfer
+
+__externC cyg_uint32
+a2fxxx_dma_ch_setup(cyg_uint8 ch, cyg_uint8 type, cyg_bool outbound,
+      cyg_uint8 src_incr, cyg_uint8 dst_incr, cyg_bool pri, cyg_uint8 wr_adj)
+{
+    cyg_uint32 res = 1;
+    cyg_uint32 xfer_type = 0, xfer_dir = 0, xfer_incr =
+                                    CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_XFER_BYTE;
+    a2fxxx_dma.dma_cr[ch] = 0;
+
+    CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL,
+                               "DMA : Channel number out of range (Setup).");
+
+    DMA_TRACE("DMA setup channel %d, direction: %s, type %x, step %d-%d byte(s)\n", ch ,
+             ((outbound==true) ? "outbound" : "inbound"), type, src_incr, dst_incr );
+
+    if( type != CYGHWR_HAL_A2FXXX_DMA_XFER_MEMORY ){
+        xfer_type = CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_PERIPH_SEL(type) |
+                CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_PERIPH;
+    }
+
+    if( outbound == true ){
+        xfer_dir = CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DIR;
+    }
+
+    a2fxxx_dma_update_incr(ch, true, dst_incr);
+    a2fxxx_dma_update_incr(ch, false, src_incr);
+
+    a2fxxx_dma.dma_cr[ch] |= ( xfer_type | xfer_dir |
+          ((pri == true) ? CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_HI_PRI : 0) |
+          CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPA |
+          CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPB |
+          CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_WR_ADJ(wr_adj) |
+          xfer_incr);
+
+    HAL_WRITE_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(ch),
+                                    a2fxxx_dma.dma_cr[ch]);
+
+    return res;
+}
+
+
+//-----------------------------------------------------------------------------
+// Remove DMA channel handler
+
+__externC void
+a2fxxx_dma_ch_detach (cyg_uint8 ch)
+{
+    CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL,
+                              "DMA : Channel number out of range (Detach).");
+
+#ifdef CYGPKG_KERNEL
+    cyg_interrupt_disable();
+#endif
+    a2fxxx_dma.ch[ch].isr  = NULL;
+    a2fxxx_dma.ch[ch].dsr  = NULL;
+    a2fxxx_dma.ch[ch].data = 0;
+#ifdef CYGPKG_KERNEL
+    cyg_interrupt_enable();
+#endif
+}
+
+
+//-----------------------------------------------------------------------------
+// Start DMA transfer
+
+__externC cyg_uint32
+a2fxxx_dma_xfer (cyg_uint8 ch, cyg_bool polled, cyg_uint32 len, cyg_uint8 *src,
+                     cyg_uint8 *dst)
+{
+    cyg_uint32 res = 1;
+    cyg_uint32 src_reg, dst_reg, cnt_reg;
+    cyg_uint32 sub = 0;
+    cyg_haladdress dma_src = (cyg_haladdress) src;
+    cyg_haladdress dma_dst = (cyg_haladdress) dst;
+
+    CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL,
+                           "DMA : Channel number out of range (Transfer).");
+
+    if( polled == true )
+        a2fxxx_dma.dma_cr[ch] &= ~CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_INTEN;
+    else
+        a2fxxx_dma.dma_cr[ch] |= CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_INTEN;
+
+    HAL_WRITE_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(ch),
+                                 a2fxxx_dma.dma_cr[ch]);
+
+    HAL_READ_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS(ch), sub);
+    sub = CYGHWR_HAL_A2FXXX_DMA_GET_SUB_ID( sub );
+
+    src_reg = ((sub == 0) ? CYGHWR_HAL_A2FXXX_DMA_CHx_BA_SRC(ch) :
+                            CYGHWR_HAL_A2FXXX_DMA_CHx_BB_SRC(ch));
+    dst_reg = ((sub == 0) ? CYGHWR_HAL_A2FXXX_DMA_CHx_BA_DST(ch) :
+                            CYGHWR_HAL_A2FXXX_DMA_CHx_BB_DST(ch));
+    cnt_reg = ((sub == 0) ? CYGHWR_HAL_A2FXXX_DMA_CHx_BA_COUNT(ch) :
+                            CYGHWR_HAL_A2FXXX_DMA_CHx_BB_COUNT(ch));
+
+    DMA_TRACE("DMA transfer of length %d on channel %d(%s) - SRC: 0x%x / DST: 0x%x\n",
+                          len, ch, ((sub==0) ? "A" : "B"), dma_src, dma_dst);
+    DMA_TRACE("DMA register address 0x%x / 0x%x\n", src_reg , dst_reg);
+
+    HAL_WRITE_UINT32(a2fxxx_dma.base + src_reg, dma_src);
+    HAL_WRITE_UINT32(a2fxxx_dma.base + dst_reg, dma_dst);
+    HAL_WRITE_UINT32(a2fxxx_dma.base + cnt_reg, len);
+
+    return res;
+}
+
+
+//-----------------------------------------------------------------------------
+// Clear DMA interrupt
+
+void a2fxxx_dma_clear_interrupt (cyg_uint8 ch)
+{
+    cyg_uint32 reg;
+
+    CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL,
+                           "DMA : Channel number out of range (Clear IRQ).");
+
+    DMA_TRACE("DMA status register 0x%x\n",
+                     (a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(ch)));
+
+    HAL_READ_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(ch), reg);
+    reg |= (CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPA |
+            CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPB);
+    HAL_WRITE_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(ch), reg);
+}
+
+
+//-----------------------------------------------------------------------------
+// Clear DMA interrupt
+
+cyg_uint8 a2fxxx_dma_get_comp_flag (cyg_uint8 ch)
+{
+    cyg_uint32 reg;
+
+    CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL,
+                                  "DMA : Channel number out of range (Get).");
+
+    HAL_READ_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS(ch), reg);
+
+    return (reg&0x3);
+}
+
+//-----------------------------------------------------------------------------
+// End of hal_dma.c
diff --git a/packages/hal/cortexm/a2fxxx/var/current/tests/timers.c b/packages/hal/cortexm/a2fxxx/var/current/tests/timers.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/a2fxxx/var/current/tests/timers.c
@@ -0,0 +1,336 @@
+/*=============================================================================
+//
+//      timers.c
+//
+//      Test for Cortex-M3 Actel Smartfusion Timers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg for STM32
+//               ccoutand updated for Cortex-M3 Actel Smartfusion Devices
+// Date:         2011-03-06
+//              
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+
+#if defined(CYGPKG_KERNEL)
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/testcase.h>
+
+//=============================================================================
+// Check all required packages and components are present
+
+#if !defined(CYGPKG_KERNEL) || !defined(CYGPKG_KERNEL_API)
+
+#define NA_MSG  "Configuration insufficient"
+
+#endif
+
+//=============================================================================
+// If everything is present, compile the full test.
+
+#ifndef NA_MSG
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_if.h>
+
+#include <cyg/kernel/kapi.h>
+#include <cyg/infra/diag.h>
+#include <string.h>
+
+//=============================================================================
+
+#define LOOPS      24           // == 2 minutes
+
+#define STACK_SIZE 8000
+
+static int test_stack[(STACK_SIZE/sizeof(int))];
+static cyg_thread test_thread;
+static cyg_handle_t main_thread;
+
+//=============================================================================
+
+struct timer
+{
+    cyg_uint32          timer;
+    cyg_uint32          base;
+    cyg_uint32          vector;
+    cyg_uint32          priority;
+    cyg_uint32          interval;
+
+    cyg_uint32          ticks;
+
+    cyg_uint32          preempt[10];
+
+    cyg_uint32          preempt_dsr[10];
+    cyg_uint32          dsr_count[10];
+
+    cyg_interrupt       interrupt_object;
+    cyg_handle_t        interrupt_handle;
+};
+
+struct timer timers[] =
+{
+    { 1, CYGHWR_HAL_A2FXXX_TIMER1, CYGNUM_HAL_INTERRUPT_TIM0_1, 0x20,     127 },
+    { 2, CYGHWR_HAL_A2FXXX_TIMER2, CYGNUM_HAL_INTERRUPT_TIM0_2, 0x30,     355 },
+    { 0, 0, 0, 0 }
+};
+
+//=============================================================================
+
+volatile cyg_uint32 ticks = 0;
+volatile cyg_uint32 nesting = 0;
+volatile cyg_uint32 max_nesting = 0;
+volatile cyg_uint32 max_nesting_seen = 0;
+volatile cyg_uint32 current = 0;
+volatile cyg_uint32 in_dsr = 0;
+
+//=============================================================================
+
+__externC cyg_uint32 hal_a2fxxx_pclk0;
+
+void init_timer( cyg_uint32 base, cyg_uint32 interval )
+{
+    cyg_uint32 period = hal_a2fxxx_pclk0;
+
+    period = period / 1000000;
+    period = period * interval;
+
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_A2FXXX_TIMER_TIMx_BGLOADVAL, period-1 );
+
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL, \
+            CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL_EN | CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL_INTEN);
+}
+
+//=============================================================================
+
+cyg_uint32 timer_isr( cyg_uint32 vector, CYG_ADDRWORD data )
+{
+    struct timer *t = (struct timer *)data;
+    cyg_uint32 preempt = current;
+    CYG_ADDRWORD base = t->base;
+    cyg_uint32 cnt;
+
+    current = t->timer;
+    t->ticks++;
+    ticks++;
+    t->preempt[preempt]++;
+    nesting++;
+
+    // Count only first ISR to preempt a DSR
+    if( preempt == 0 )
+        t->preempt_dsr[in_dsr]++;
+
+    HAL_WRITE_UINT32(t->base+CYGHWR_HAL_A2FXXX_TIMER_TIMx_RIS, 1 );
+
+    if( nesting > max_nesting )
+        max_nesting = nesting;
+
+    // Loiter here for a proportion of the timer interval to give
+    // other timers the chance to preempt us.
+    do
+    {
+        HAL_READ_UINT32( base+CYGHWR_HAL_A2FXXX_TIMER_TIMx_VAL, cnt );
+    } while( cnt < t->interval/10 );
+
+    nesting--;
+    current = preempt;
+
+    if( (t->ticks % 10) == 0 )
+        return 3;
+    else
+        return 1;
+}
+
+//=============================================================================
+
+void timer_dsr( cyg_uint32 vector, cyg_uint32 count, CYG_ADDRWORD data )
+{
+    struct timer *t = (struct timer *)data;
+    int i;
+
+    in_dsr = t->timer;
+
+    if( count >= 8 )
+        count = 8;
+
+    t->dsr_count[count]++;
+
+    // Loiter for a while
+    for( i = 0; i < t->interval/10; i++)
+        continue;
+
+    in_dsr = 0;
+}
+
+//=============================================================================
+
+void
+timers_test(cyg_addrword_t data)
+{
+    int loops = LOOPS;
+    int i;
+    CYG_INTERRUPT_STATE istate;
+
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Start Timers test");
+
+    CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(TIMER) );
+
+    for( i = 0; timers[i].timer != 0; i++ )
+    {
+        struct timer *t = &timers[i];
+
+        init_timer( t->base, t->interval );
+
+        cyg_interrupt_create( t->vector,
+                              t->priority,
+                              (cyg_addrword_t)t,
+                              timer_isr,
+                              timer_dsr,
+                              &t->interrupt_handle,
+                              &t->interrupt_object
+            );
+
+        cyg_interrupt_attach( t->interrupt_handle );
+        cyg_interrupt_unmask( t->vector );
+
+    }
+
+    while( loops-- )
+    {
+        int j;
+
+        // 5 second delay
+        cyg_thread_delay( 5*100 );
+
+        // Disable interrupts while we print details, otherwise it
+        // comes out very slowly.
+        HAL_DISABLE_INTERRUPTS( istate );
+
+        if( max_nesting > max_nesting_seen )
+            max_nesting_seen = max_nesting;
+
+        diag_printf("\nISRs max_nesting %d max_nesting_seen %d\n", max_nesting, max_nesting_seen );
+        max_nesting = 0;
+
+        diag_printf(" T      Ticks ");
+
+        for( j = 0; j < 9; j++ )
+            diag_printf("%9d ", j );
+        diag_printf("\n");
+
+        for( i = 0; timers[i].timer != 0; i++ )
+        {
+            struct timer *t = &timers[i];
+
+            diag_printf("%2d: %9d ", t->timer, t->ticks );
+
+            for( j = 0; j < 9; j++ )
+                diag_printf("%9d ", t->preempt[j] );
+            diag_printf("\n");
+
+        }
+
+        diag_printf("DSRs\n");
+
+        diag_printf(" T:           ");
+
+        for( j = 0; j < 9; j++ )
+            diag_printf("%9d ", j );
+        diag_printf("\n");
+
+        for( i = 0; timers[i].timer != 0; i++ )
+        {
+            struct timer *t = &timers[i];
+
+            diag_printf("%2d:  preempt: ", t->timer);
+
+            for( j = 0; j < 9; j++ )
+                diag_printf("%9d ", t->preempt_dsr[j] );
+            diag_printf("\n");
+
+            diag_printf("       count: ");
+
+            for( j = 0; j < 9; j++ )
+                diag_printf("%9d ", t->dsr_count[j] );
+            diag_printf("\n");
+        }
+
+        HAL_RESTORE_INTERRUPTS( istate );
+    }
+
+    CYG_TEST_PASS_FINISH("Timers test");
+}
+
+//=============================================================================
+
+void cyg_user_start(void)
+{
+    cyg_thread_create(0,                // Priority
+                      timers_test,
+                      0,
+                      "timers test",    // Name
+                      test_stack,       // Stack
+                      STACK_SIZE,       // Size
+                      &main_thread,     // Handle
+                      &test_thread // Thread data structure
+        );
+    cyg_thread_resume( main_thread);
+}
+
+//=============================================================================
+// Print a message if we cannot run
+
+#else // NA_MSG
+
+void cyg_user_start(void)
+{
+    CYG_TEST_NA(NA_MSG);
+}
+
+#endif // NA_MSG
+
+//=============================================================================
+/* EOF timers.c */
diff --git a/packages/hal/cortexm/arch/current/ChangeLog b/packages/hal/cortexm/arch/current/ChangeLog
--- a/packages/hal/cortexm/arch/current/ChangeLog
+++ b/packages/hal/cortexm/arch/current/ChangeLog
@@ -1,3 +1,133 @@
+2014-05-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/cortexm.ld: Use CYGBLD_HAL_LINKER_GROUPED_LIBS macro.
+	[ Bugzilla 1001989 ]
+
+2014-02-28  John Dallaway  <john@dallaway.org.uk>
+
+	* src/mcount.S: Add mcount functions for call-graph profiling.
+	* cdl/hal_cortexm.cdl: Add option to build mcount functions.
+	[ Bugzilla 1001954 ]
+
+2013-08-25  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_fpu.cdl, include/fpv4_sp_d16_libm.h: Define Cortex-M4F
+	architecture specific builtin mathematical functions.  [ Bugzilla 1001539 ]
+
+2013-04-29  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/cortexm_stub.h: Remove unwanted diag_printf().
+
+2013-02-10  Ilija Kocho  <ilijak@siva.com.mk>
+            Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm.cdl:
+	* cdl/hal_cortexm_fpu.cdl:   New
+	* include/cortexm_core.h:    New
+	* include/cortexm_fpu.h:     New
+	* include/cortexm_regs.h:
+	* include/cortexm_stub.h:
+	* include/fpv4_sp_d16.h:     New
+	* include/hal_arch.h:
+	* include/hal_arch.inc:      New
+	* include/hal_io.h:
+	* src/context.S:
+	* src/cortexm_fpu.c:         New
+	* src/cortexm_stub.c:
+	* src/fpv4_sp_d16.c:         New
+	* src/hal_misc.c:
+	* src/vectors.S:
+	Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
+
+2012-04-23  Ilija Kocho  <ilijak@siva.com.mk>
+
+    * cdl/hal_cortexm.cdl:
+    * include/basetype.h:
+    * include/cortexm_stub.h:
+    * include/hal_arch.h:
+    * include/hal_intr.h:
+    * include/hal_io.h:
+    * src/context.S:
+    * src/cortexm_stub.c:
+    * src/hal_misc.c:
+    * src/vectors.S:
+    Whitespace cleanup [Bugzilla 1001569]
+
+2012-03-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+    * include/hal_intr.h: Fix compiler warning about unused variables.
+    [Bugzilla 1001520]
+
+2012-02-05  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* src/hal_misc.c (hal_reset_vsr): Ensure we only init intr vectors
+	up to top of VSR table.
+
+2011-08-23  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm.cdl: New CDL option CYGIMP_HAL_ARCH_ENDIAN
+	* include/cortexm_endian.h: New file
+	* include/cortexm_regs.h: New file
+	[ Bugzilla 1001275 ]
+
+2011-04-06  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/cortexm.cdl: Remove M1 CPU family from architecture config
+	file (as not supported for now). [Bugzilla 1001186]
+
+2011-04-02  Ilija Kocho  <ilijak@siva.com.mk>
+	* cdl/cortexm.cdl: Add M4 CPU family to CYGHWR_HAL_CORTEXM. Add
+	FPU (Floating Point Unit) interface.
+	* include/hal_io.h: Add CYGHWR_HAL_CORTEXM_M4 to some preprocessor
+	conditions. [Bugzilla 1001186]
+
+2011-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/hal_intr.h: Remove double inclusion of var_intr.h
+	header and include it at proper place. [ Bugzilla 1001184 ]
+
+2011-02-17  John Dallaway  <john@dallaway.org.uk>
+
+	* include/hal_intr.h (HAL_DISABLE_INTERRUPTS): Mark operand as
+	an earlyclobber operand to ensure correct register usage. Issue
+	reported by both Ulrich Holeschak and Stanislav Meduna.
+	[ Bugzilla 1001154 ]
+
+2011-02-16  Ilija Kocho <ilijak@siva.com.mk>
+
+	* src/cortexm.ld: Added USER_SECTION() macro. [Bugzilla 1001142 ]
+
+2011-01-20  Christophe Coutand  <ccoutand@stmi.com>
+
+	* include/hal_intr.h:
+	* cdl/hal_cortexm.cdl:
+	Allow variant or platform to define their own RTC clock. Add
+	CDL entry to select SysTick clock source. [ Bugzilla 1001090 ]
+
+2010-12-28  Ilija Kocho <ilijak@siva.com.mk>
+
+	* include/hal_io.h: conditional VTOR setting.
+
+2011-01-13  John Dallaway  <john@dallaway.org.uk>
+
+	* src/vectors.S (hal_default_interrupt_vsr): Save interrupt state
+	if CYGINT_HAL_COMMON_SAVED_INTERRUPT_STATE_REQUIRED is implemented.
+	[ Bugzilla 1001111 ]
+
+2011-01-02  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/hal_cortexm.cdl: Eliminate some warnings. [ Bugzilla
+	1001083 ]
+
+2010-05-17  Spencer Oliver <spen@spen-soft.co.uk>
+
+	* include/hal_intr.h (HAL_INTERRUPT_STACK_CALL_PENDING_DSRS):
+	* src/hal_misc.c (hal_reset_vsr): Add 0 argument to SWI.
+
+	* src/vectors.S (hal_switch_state_vsr): Eliminate "msr psp,sp",
+	which is now deprecated.
+	(hal_pendable_svc_vsr): Add 0 argument to SWI.
+
 2009-02-27  Simon Kallweit  <simon.kallweit@intefo.ch>
 
 	* include/hal_io.h: Added system control register definitions 
@@ -68,7 +198,7 @@ 2008-10-06  Nick Garnett  <nickg@ecoscen
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2011, 2014 Free Software Foundation, Inc.                        
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl b/packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl
--- a/packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl
+++ b/packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 2008 Free Software Foundation, Inc.                        
+## Copyright (C) 2008, 2011, 2014 Free Software Foundation, Inc.                  
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -39,8 +39,9 @@
 ##==========================================================================
 #######DESCRIPTIONBEGIN####
 ##
-## Author(s):    nickg
-## Date:         2008-07-30
+## Author(s):       nickg
+## Contributor(s):  jld
+## Date:            2008-07-30
 ##
 ######DESCRIPTIONEND####
 ##
@@ -56,6 +57,8 @@ cdl_package CYGPKG_HAL_CORTEXM {
         This package provides generic support for the ARM Cortex-M architecture.
         It is also necessary to select a variant and platform HAL package."
 
+    implements    CYGINT_PROFILE_HAL_MCOUNT
+
     compile       hal_misc.c context.S cortexm_stub.c
 
     requires { CYGHWR_HAL_CORTEXM_BIGENDIAN implies
@@ -76,7 +79,7 @@ cdl_package CYGPKG_HAL_CORTEXM {
 
     make {
         <PREFIX>/lib/target.ld: <PACKAGE>/src/cortexm.ld
-        $(CC) -E -P -Wp,-MD,target.tmp -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
+        $(CC) -E -P -Wp,-MD,target.tmp -xc $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -o $@ $<
         @echo $@ ": \\" > $(notdir $@).deps
         @tail -n +2 target.tmp >> $(notdir $@).deps
         @echo >> $(notdir $@).deps
@@ -98,14 +101,52 @@ cdl_package CYGPKG_HAL_CORTEXM {
     cdl_option CYGHWR_HAL_CORTEXM {
         display          "Cortex-M CPU family"
         flavor           data
-        legal_values     { "M1" "M3" }
+        legal_values     { "M3" "M4" }
         default_value    { "M3" }
         description      "
-            The Cortex-M architecture has two variants at present. The M1 is
-            base on the ARMV6 architecture specification and executes an extended
-            variant of the Thumb instruction set and has some differences in
-            the interrupt controller. The M3 is based on the ARMV7 architecture
-            specification and executes the Thumb2 instruction set."
+            The Cortex-M architecture has two variants at present. The
+            M3 and M4 are based on the ARMV7 architecture specification
+            and execute the Thumb2 instruction set. The M4 in addition
+            to M3 instruction set has SIMD and optional single precision
+            floating point instructions."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE {
+        display          "System tick timer clock"
+        flavor           data
+        legal_values     { "EXTERNAL" "INTERNAL" }
+        default_value    { "EXTERNAL" }
+        description      "Select the Cortex-M system tick timer clock source."
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_FPU {
+        display        "Floating Point Support"
+        flavor         data
+        calculated     { !CYGHWR_HAL_CORTEXM_FPU ? "SOFT" :
+                          "HARD: " . CYGHWR_HAL_CORTEXM_FPU_SWITCH }
+        no_define
+        active_if      { CYGHWR_HAL_CORTEXM == "M4" }
+        description    "
+            Floating point arithmetics can be executed in software or,
+            on devices with floating point unit - FPU, in hardware.
+            FPU is optional on Cortex-M4 architecture, and is present
+            on Cortex-M4F cores."
+
+        script         hal_cortexm_fpu.cdl
+    }
+
+    cdl_option CYGIMP_HAL_ARCH_ENDIAN {
+        display       "Architecture optimized endian functions"
+        flavor        bool
+        default_value 1
+        description   "
+            Cortex-M architecture implements instructions for endian
+            manipulation (byte swapping).  If enabled, this feature
+            can produce shorter and faster code for that."
+
+        define_proc {
+            puts $::cdl_system_header "#define CYGBLD_HAL_ENDIAN_H <cyg/hal/cortexm_endian.h>"
+        }
     }
 
     cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_MAX {
@@ -116,11 +157,23 @@ cdl_package CYGPKG_HAL_CORTEXM {
              Calculate the maximum exception priority that can be set by interrupts.
              Higher priorities are reserved for the DEBUG and SVC traps."
     }
-    
+
+    cdl_option CYGBLD_HAL_CORTEXM_MCOUNT {
+        display           "Support call-graph profiling"
+        flavor            bool
+        no_define
+        active_if         CYGPKG_PROFILE_GPROF
+        calculated        CYGPKG_PROFILE_CALLGRAPH
+        compile           mcount.S
+        description       "
+            Calculate whether mcount functions should be built
+            to support call-graph profiling."
+    }
+
     cdl_option CYGBLD_LINKER_SCRIPT {
         display "Linker script"
         flavor data
-	no_define
+        no_define
         calculated  { "src/cortexm.ld" }
     }
 
@@ -130,7 +183,93 @@ cdl_package CYGPKG_HAL_CORTEXM {
             default_value 8
             description   "
                 This option determines the number of breakpoints supported by the HAL."
-    }    
+    }
+
+    cdl_component CYGBLD_ARCH_CPUFLAGS {
+        display      "Architecture related build flags"
+        flavor data
+        no_define
+
+        calculated { CYGHWR_HAL_CORTEXM == "M3" ? " -mcpu=cortex-m3" :
+                     CYGHWR_HAL_CORTEXM_FPU     ? " -mcpu=cortex-m4" : " " }
+
+        description "This component defines flags that code generation dependent on specific
+            CPU type or CPU features."
+
+        cdl_option CYGBLD_ARCH_CPUFLAGX_M3 {
+            display    "Exclude Cortex-M3 build flag"
+            flavor     data
+            no_define
+
+            calculated { CYGHWR_HAL_CORTEXM_FPU ? "-mcpu=cortex-m3" : "no_exclude" }
+        }
+
+        cdl_option CYGBLD_ARCH_CPUFLAGX_M4 {
+            display    "Exclude Cortex-M4 build flag"
+            flavor     data
+            no_define
+
+            calculated { (CYGHWR_HAL_CORTEXM != "M4") ? "-mcpu=cortex-m4" : "no_exclude" }
+        }
+
+        cdl_component CYGBLD_ARCH_CPUFLAG_FLOAT_ABI {
+            display    "Float ABI build flags"
+            flavor     data
+            no_define
+            calculated { CYGHWR_HAL_CORTEXM_FPU ? " -mfloat-abi=hard" : "" }
+
+            cdl_option CYGBLD_ARCH_CPUFLAGX_FLOAT_ABI {
+                display    "Float ABI flag to exclude"
+                flavor     data
+                no_define
+                calculated { CYGHWR_HAL_CORTEXM_FPU ? "-mfloat-abi=soft" : "-mfloat-abi=hard" }
+            }
+
+            cdl_option CYGBLD_ARCH_CPUFLAGX_HARDSOFT_FLOAT {
+                display    "Alt. float flag to exclude"
+                flavor     data
+                no_define
+                calculated { CYGHWR_HAL_CORTEXM_FPU ? "-msoft-float" : "-mhard-float" }
+            }
+
+            cdl_component CYGBLD_ARCH_CPUFLAG_FPV4SPD16 {
+                display    "FPv4-SP-D16 flags"
+                flavor     data
+                no_define
+                calculated { CYGHWR_HAL_FPV4_SP_D16 ? " -mfpu=fpv4-sp-d16" : "" }
+
+                cdl_option CYGBLD_ARCH_CPUFLAGX_FPV4SPD16 {
+                    display    "Exclude FPv4-SP-D16 flag"
+                    flavor     data
+                    no_define
+                    calculated { CYGHWR_HAL_FPV4_SP_D16 ? "do_not_exclude" : "-mfpu=fpv4-sp-d16" }
+                }
+            }
+        }
+
+        requires {
+            !is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAGX_M3)             &&
+            !is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAGX_M4)             &&
+            !is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAGX_FLOAT_ABI)      &&
+            !is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAGX_HARDSOFT_FLOAT) &&
+            !is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAGX_FPV4SPD16)      &&
+
+            is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAGS)                 &&
+            is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAG_FLOAT_ABI)        &&
+            is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAG_FPV4SPD16)
+        }
+        requires {
+            !is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAGX_M3)             &&
+            !is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAGX_M4)             &&
+            !is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAGX_FLOAT_ABI)      &&
+            !is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAGX_HARDSOFT_FLOAT) &&
+            !is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAGX_FPV4SPD16)      &&
+
+            is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAGS)                 &&
+            is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAG_FLOAT_ABI)        &&
+            is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAG_FPV4SPD16)
+        }
+    }
 }
 
 # EOF hal_cortexm.cdl
diff --git a/packages/hal/cortexm/arch/current/cdl/hal_cortexm_fpu.cdl b/packages/hal/cortexm/arch/current/cdl/hal_cortexm_fpu.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/arch/current/cdl/hal_cortexm_fpu.cdl
@@ -0,0 +1,136 @@
+##==========================================================================
+##
+##      hal_cortexm_fpu.cdl
+##
+##      Cortex-M HAL Floating Point configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2012 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ilijak
+## Date:         2012-03-03
+## Usage:        script hal_cortexm_fpu.cdl
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+    #cdl_component CYGPKG_HAL_CORTEXM_FPU {
+        #display          "Floating Point Unit"
+        #flavor           none
+        #no_define
+
+        cdl_interface CYGINT_HAL_FPV4_SP_D16 {
+            display   "FPU is FPv4-SP-D16"
+            flavor     bool
+            implements CYGINT_HAL_CORTEXM_FPU
+        }
+
+        cdl_interface CYGINT_HAL_CORTEXM_FPU {
+            display  "FPU present."
+            flavor   data
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_FPU {
+            display        "Use hardware FPU"
+            flavor         bool
+            active_if      { CYGINT_HAL_CORTEXM_FPU }
+            default_value  0
+            compile        cortexm_fpu.c
+
+            description "
+                Cortex-M4F cores have a single precision floating point unit.
+                This option enables FPU usage and provides related FPU control
+                options.
+                Hardware FPU enable, implies Cortex-M4 code generation, and
+                build flags shall be set accordingly, including -mcpu=cortex-m4.
+                As a side effect, the Cortex_M4 build flag will remain \(sticky\)
+                even if hardware FPU is subsequently disabled.
+                "
+
+            cdl_option CYGHWR_HAL_CORTEXM_FPU_SWITCH {
+                display       "FPU context switch"
+                flavor data
+                legal_values  { "ALL" "LAZY" "NONE" }
+                default_value { "LAZY" }
+
+                requires { is_active (CYGPKG_KERNEL) implies
+                    CYGTST_KERNEL_SKIP_MULTI_THREAD_FP_TEST ==
+                    (CYGHWR_HAL_CORTEXM_FPU_SWITCH == "NONE") }
+
+                description   "
+                    This option selects the FPU context switching scheme.
+                    Straight-forward behaviour is to save and
+                    restore FPU state on every CPU context save/restore.
+                    While simple, robust and deterministic, this
+                    approach can be expensive if the FPU is used by
+                    few threads. The alternative schemes, available by this
+                    option, are to use hardware features that allow either:
+                    - LAZY: Save FPU context only if the thread makes use of
+                    the FPU. Where only few threads use FPU this should give
+                    shorter average context switching delay compared to ALL
+                    scheme. If more than one threads use FPU, the worst context
+                    switching time is typically worse than the one for ALL
+                    scheme.
+                    - ALL: Save FPU context for all threads. This is a simple
+                    scheme, which if all, or majority of threads use FPU may
+                    give better average context switching time than LAZY.
+                    This scheme also includes Lazy Stacking of FPU state
+                    for exceptions/interrupts.
+                    - NONE: No FPU state saving, this scheme adds no additional
+                    delay for saving of FPU state to context switching, but is
+                    only suitable if maximum one thread uses floating point."
+            }
+
+        cdl_option CYGHWR_HAL_FPV4_SP_D16 {
+            flavor bool
+            active_if { CYGINT_HAL_FPV4_SP_D16 }
+            calculated { CYGINT_HAL_FPV4_SP_D16 && CYGHWR_HAL_CORTEXM_FPU }
+            display     "FPv4-SP-D16"
+            no_define
+            compile     fpv4_sp_d16.c
+
+            define_proc {
+                puts $::cdl_system_header "#define CYGBLD_HAL_LIBM_H <cyg/hal/fpv4_sp_d16_libm.h>"
+            }
+
+            description "
+                FPv4-SP-D16 is ARMv7 architecture single precision floating
+                point unit with 16 double precision / 32 single precision
+                registers. It is found on Cortex-M4F and Cortex-R5 cores."
+        }
+    #}
+
+# EOF hal_cortexm_fpu.cdl
diff --git a/packages/hal/cortexm/arch/current/include/basetype.h b/packages/hal/cortexm/arch/current/include/basetype.h
--- a/packages/hal/cortexm/arch/current/include/basetype.h
+++ b/packages/hal/cortexm/arch/current/include/basetype.h
@@ -47,7 +47,8 @@
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 #define CYG_BYTEORDER           CYG_LSBFIRST    // Little endian
 #define CYG_DOUBLE_BYTEORDER    CYG_LSBFIRST
@@ -68,4 +69,3 @@
 //==========================================================================
 #endif // CYGONCE_HAL_BASETYPE_H
 // End of basetype.h
-
diff --git a/packages/hal/cortexm/arch/current/include/cortexm_core.h b/packages/hal/cortexm/arch/current/include/cortexm_core.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/arch/current/include/cortexm_core.h
@@ -0,0 +1,77 @@
+#ifndef CYGONCE_CORTEXM_CORE_H
+#define CYGONCE_CORTEXM_CORE_H
+//==========================================================================
+//
+//      cortexm_core.h
+//
+//      Cortex-M some core registers
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2012-06-26
+// Description:    Some Cortex-M core register definitions
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+
+// Coprocessor Access Control Register
+#define CYGARC_REG_FPU_CPACR 0xE000ED88
+
+#define CYGARC_REG_FPU_CPACR_ACCESS_DENIED     0
+#define CYGARC_REG_FPU_CPACR_ACCESS_PRIVILEGED 1
+#define CYGARC_REG_FPU_CPACR_ACCESS_RESERVED   2
+#define CYGARC_REG_FPU_CPACR_ACCESS_FULL       (CYGARC_REG_FPU_CPACR_ACCESS_PRIVILEGED | \
+                                               CYGARC_REG_FPU_CPACR_ACCESS_RESERVED)
+
+#define CYGARC_REG_FPU_CPACR_CP10(_access) ((_access) << 20)
+#define CYGARC_REG_FPU_CPACR_CP11(_access) ((_access) << 22)
+
+#define CYGARC_REG_FPU_CPACR_ENABLE                                       \
+           (CYGARC_REG_FPU_CPACR_CP10(CYGARC_REG_FPU_CPACR_ACCESS_FULL) | \
+            CYGARC_REG_FPU_CPACR_CP11(CYGARC_REG_FPU_CPACR_ACCESS_FULL))
+
+// CONTROL register
+// The CONTROL register is not memory mapped. Use CYGARC_MSR() and CYGARC_MRS().
+#define CYGARC_REG_CONTROL_PRIV_M       0x1
+#define CYGARC_REG_CONTROL_SPSEL_M      0x2
+#define CYGARC_REG_CONTROL_FPCA_M       0x4
+
+//==========================================================================
+#endif //CYGONCE_CORTEXM_CORE_H
diff --git a/packages/hal/cortexm/arch/current/include/cortexm_endian.h b/packages/hal/cortexm/arch/current/include/cortexm_endian.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/arch/current/include/cortexm_endian.h
@@ -0,0 +1,77 @@
+#ifndef CYGONCE_CORTEXM_ENDIAN_H
+#define CYGONCE_CORTEXM_ENDIAN_H
+//==========================================================================
+//
+//      cortexm_endian.h
+//
+//      Cortex-M architecture endian conversion macros/functions.
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+//               Sergei Gavrikov
+// Date:         2011-08-20
+// Description:  Endian conversion macros/functions optimized for Cortex-M
+// Usage:        #include <cyg/hal/cortexm_endian.h>
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/cortexm_regs.h>
+
+//===========================================================================
+// Endian operations optimized for Cortex-M architecture.
+
+static __inline__ cyg_uint32 cyg_hal_swap32(cyg_uint32 original)
+{
+    cyg_uint32 swapped;
+    CYGARC_REV(swapped, original);
+    return swapped;
+}
+
+static __inline__ cyg_uint16 cyg_hal_swap16(cyg_uint16 original)
+{
+    cyg_uint16 swapped;
+    CYGARC_REV16(swapped, original);
+    return swapped;
+}
+
+#define CYG_SWAP32(__val) cyg_hal_swap32(__val)
+#define CYG_SWAP16(__val) cyg_hal_swap16(__val)
+
+//==========================================================================
+#endif //CYGONCE_CORTEXM_ENDIAN_H
diff --git a/packages/hal/cortexm/arch/current/include/cortexm_fpu.h b/packages/hal/cortexm/arch/current/include/cortexm_fpu.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/arch/current/include/cortexm_fpu.h
@@ -0,0 +1,98 @@
+#ifndef CYGONCE_CORTEXM_FPU_H
+#define CYGONCE_CORTEXM_FPU_H
+//==========================================================================
+//
+//      cortexm_fpu.h
+//
+//      Cortex-M General Floating Point Unit definitions 
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2012-04-25
+// Description:    Cortex-M4F General Floating Point Unit definitions and macros
+// Usage:          include <cyg/hal/cortexm_fpu.h>
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+
+//===========================================================================
+// Floating Point Unit
+//
+// FPU is optional unit of Cortex-M4
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <cyg/hal/cortexm_core.h>
+
+#ifdef CYGHWR_HAL_CORTEXM_FPU
+
+# if defined CYGSEM_HAL_ROM_MONITOR || defined CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#  define CYGSEM_HAL_DEBUG_FPU
+# endif
+
+# ifdef CYGINT_HAL_FPV4_SP_D16
+#  include <cyg/hal/fpv4_sp_d16.h>
+# else
+#  error "Unknown FPU unit!"
+# endif
+
+#else // CYGHWR_HAL_CORTEXM_FPU
+
+# define CYGARC_CORTEXM_GDB_REG_FPA
+
+# define GDB_STUB_SAVEDREG_FRAME_TYPE(__type) (__type->u.type)
+
+# define HAL_SAVEDREG_AUTO_FRAME_SIZE (8*4)
+
+# define HAL_SAVEDREG_FPU_THREAD_S
+# define HAL_SAVEDREG_MAN_FPU_EXCEPTION_S
+# define HAL_SAVEDREG_AUTO_FPU_EXCEPTION_S
+# define HAL_THREAD_INIT_FPU_CONTEXT(__regs) CYG_EMPTY_STATEMENT
+
+# define GDB_STUB_SAVEDREG_FPU_THREAD_GET(__gdbreg,__regs) CYG_EMPTY_STATEMENT
+# define GDB_STUB_SAVEDREG_FPU_THREAD_SET(__gdbreg,__regs) CYG_EMPTY_STATEMENT
+# define GDB_STUB_SAVEDREG_FPU_EXCEPTION_GET(__gdbreg,__regs) CYG_EMPTY_STATEMENT
+# define GDB_STUB_SAVEDREG_FPU_EXCEPTION_SET(__gdbreg,__regs) CYG_EMPTY_STATEMENT
+
+#endif// CYGHWR_HAL_CORTEXM_FPU
+
+
+//==========================================================================
+#endif //CYGONCE_CORTEXM_FPU_H
diff --git a/packages/hal/cortexm/arch/current/include/cortexm_regs.h b/packages/hal/cortexm/arch/current/include/cortexm_regs.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/arch/current/include/cortexm_regs.h
@@ -0,0 +1,118 @@
+#ifndef CYGONCE_CORTEXM_REGS_H
+#define CYGONCE_CORTEXM_REGS_H
+//==========================================================================
+//
+//      cortexm_regs.h
+//
+//      Cortex-M architecture, special machine instruction wrappers
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+//               Sergei Gavrikov
+// Date:         2011-06-18
+// Description:  C wrappers for some special architecture instructions.
+//
+//####DESCRIPTIONEND####
+//
+//=========================================================================
+
+#ifndef __ASSEMBLER__
+
+//--------------------------------------------------------------------------
+// No operation
+#define CYGARC_NOP() { __asm__ volatile( "nop" ); }
+
+
+//---------------------------------------------------------------------------
+// Change processor state instructions
+
+// Disable / enable interrupts
+#define CYGARC_CPSID( _flags_ ) __asm__ volatile ("cpsid " #_flags_ "\n")
+
+// Enable interrupts and fault handlers (clear FAULTMASK)
+#define CYGARC_CPSIE( _flags_ ) __asm__ volatile ("cpsie " #_flags_ "\n")
+
+//---------------------------------------------------------------------------
+// Byte swapping instructions
+
+// Reverse word
+#define CYGARC_REV( _swapped_, _origin_ ) \
+        __asm__ volatile ("rev %0, %1\n" : "=r"(_swapped_) : "r"(_origin_))
+
+// Reverse halfwords
+#define CYGARC_REV16( _swapped_, _origin_ ) \
+        __asm__ volatile ("rev16 %0, %1\n" : "=r"(_swapped_) : "r"(_origin_))
+
+// Reverse signed halfword
+#define CYGARC_REVSH( _swapped_, _origin_ ) \
+        __asm__ volatile ("revsh %0, %1\n" : "=r"(_swapped_) : "r"(_origin_))
+
+//------------------------------------------------------------------------
+// Barrier instructions
+// Data Synchronization Barrier
+#define CYGARC_DSB() __asm__ volatile( "dsb" )
+// Instruction Synchronization Barrier
+#define CYGARC_ISB() __asm__ volatile( "isb" )
+
+#define HAL_MEMORY_BARRIER() \
+CYG_MACRO_START              \
+    CYGARC_DSB();            \
+    CYGARC_ISB();            \
+CYG_MACRO_END
+
+//----------------------------------------------------------------------------
+// MSR instuctions
+// Special register instructions
+#define CYGARC_MSR(_reg_, _val_) \
+        __asm__ volatile ("msr " #_reg_", %0\n" : : "r"(_val_))
+
+#define CYGARC_MRS(_val_, _reg_) \
+        __asm__ volatile ("mrs %0," #_reg_ "\n" : "=r"(_val_) : )
+
+//----------------------------------------------------------------------------
+// VFP instuctions
+// Special floating point unit register instructions
+#define CYGARC_VMSR(_reg_, _val_) \
+        __asm__ volatile ("vmsr " #_reg_", %0\n" : : "r"(_val_))
+
+#define CYGARC_VMRS(_val_, _reg_) \
+        __asm__ volatile ("vmrs %0," #_reg_ "\n" : "=r"(_val_) : )
+
+#endif // __ASSEMBLER__
+
+//==========================================================================
+#endif // CYGONCE_CORTEXM_REGS_H
diff --git a/packages/hal/cortexm/arch/current/include/cortexm_stub.h b/packages/hal/cortexm/arch/current/include/cortexm_stub.h
--- a/packages/hal/cortexm/arch/current/include/cortexm_stub.h
+++ b/packages/hal/cortexm/arch/current/include/cortexm_stub.h
@@ -10,7 +10,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2012 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -41,57 +41,64 @@
 //==========================================================================
 //#####DESCRIPTIONBEGIN####
 //
-// Author(s):    nickg
+// Author(s):      nickg
+// Contributor(s): ilijak
 // Date:         2008-07-30
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+
+#ifdef CYGHWR_HAL_CORTEXM_FPU
+#include <cyg/hal/cortexm_fpu.h>
+#endif
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-
+#ifndef CYGHWR_HAL_CORTEXM_FPU
 // The ARM has float (and possibly other coprocessor) registers that are
 // larger than it can hold in a target_register_t.
-#define TARGET_HAS_LARGE_REGISTERS
+# define TARGET_HAS_LARGE_REGISTERS
 
 // ARM stub has special needs for register handling (not all regs are the
 // the same size), so special put_register and get_register are provided.
-#define CYGARC_STUB_REGISTER_ACCESS_DEFINED 1
+# define CYGARC_STUB_REGISTER_ACCESS_DEFINED 1
 
-#define NUMREGS    (16+8+2)  // 16 GPR, 8 FPR (unused), 2 PS
-
-#define REGSIZE( _x_ ) (((_x_) < F0 || (_x_) >= FPS) ? 4 : 12)
+# define NUMREGS    (16+8+2)  // 16 GPR, 8 FPR (unused), 2 PS
 
-// Comment out to allow for default gdb stub packet buffer which is larger.
-// #define NUMREGBYTES ((16*4)+(8*12)+(2*4))
+# define REGSIZE( _x_ ) (((_x_) < F0 || (_x_) >= FPS) ? 4 : 12)
 
-#ifndef TARGET_REGISTER_T_DEFINED
-#define TARGET_REGISTER_T_DEFINED
+# ifndef TARGET_REGISTER_T_DEFINED
+#  define TARGET_REGISTER_T_DEFINED
 typedef unsigned long target_register_t;
-#endif
+# endif
 
 enum regnames {
-    R0, R1, R2, R3, R4, R5, R6, R7, 
+    R0, R1, R2, R3, R4, R5, R6, R7,
     R8, R9, R10, FP, IP, SP, LR, PC,
-    F0, F1, F2, F3, F4, F5, F6, F7, 
+    F0, F1, F2, F3, F4, F5, F6, F7,
     FPS, PS
 };
 
-#define HAL_STUB_REGISTERS_SIZE \
- ((sizeof(HAL_CORTEXM_GDB_Registers) + sizeof(target_register_t) - 1) / sizeof(target_register_t))
+#endif // CYGHWR_HAL_CORTEXM_FPU
+
+# define HAL_STUB_REGISTERS_SIZE \
+   ((sizeof(HAL_CORTEXM_GDB_Registers) + sizeof(target_register_t) - 1) / sizeof(target_register_t))
 
-#define PS_N 0x80000000
-#define PS_Z 0x40000000
-#define PS_C 0x20000000
-#define PS_V 0x10000000
+# define PS_N 0x80000000
+# define PS_Z 0x40000000
+# define PS_C 0x20000000
+# define PS_V 0x10000000
 
 typedef enum regnames regnames_t;
 
 //------------------------------------------------------------------------
-    
+
 /* Given a trap value TRAP, return the corresponding signal. */
 extern int __computeSignal (unsigned int trap_number);
 
diff --git a/packages/hal/cortexm/arch/current/include/fpv4_sp_d16.h b/packages/hal/cortexm/arch/current/include/fpv4_sp_d16.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/arch/current/include/fpv4_sp_d16.h
@@ -0,0 +1,285 @@
+#ifndef CYGONCE_FPV4_SP_D16_H
+#define CYGONCE_FPV4_SP_D16_H
+//==========================================================================
+//
+//      fpv4_sp_d16.h
+//
+//      FPv4spD16 Floating Point Unit definitions 
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2012-04-25
+// Description:    FPv4spD16 Floating Point Unit definitions and macros
+// Usage:          include <cyg/hal/fpv4_sp_d16.h>
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+#if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL
+#define CYGARC_CORTEXM_FPU_EXC_AUTOSAVE
+#endif
+
+//===========================================================================
+// Floating-point Context Control Register
+#define CYGARC_REG_FPU_FPCCR 0xE000EF34
+
+#define CYGARC_REG_FPU_FPCCR_LSPACT   0x1
+#define CYGARC_REG_FPU_FPCCR_USER     0x2
+#define CYGARC_REG_FPU_FPCCR_THREAD   0x8
+#define CYGARC_REG_FPU_FPCCR_HFRDY    0x10
+#define CYGARC_REG_FPU_FPCCR_MMRDY    0x20
+#define CYGARC_REG_FPU_FPCCR_BFRDY    0x40
+#define CYGARC_REG_FPU_FPCCR_MONRDY   0x100
+#define CYGARC_REG_FPU_FPCCR_LSPEN    0x40000000
+#define CYGARC_REG_FPU_FPCCR_ASPEN    0x80000000
+
+#define HAL_CORTEXM_FPU_ENABLE()                      \
+CYG_MACRO_START                                       \
+    cyg_uint32 regval;                                \
+    HAL_READ_UINT32(CYGARC_REG_FPU_CPACR, regval);    \
+    regval |= CYGARC_REG_FPU_CPACR_ENABLE;            \
+    HAL_WRITE_UINT32(CYGARC_REG_FPU_CPACR, regval);   \
+    HAL_MEMORY_BARRIER();                             \
+CYG_MACRO_END
+
+#define HAL_CORTEXM_FPU_DISABLE()                     \
+CYG_MACRO_START                                       \
+    cyg_uint32 regval;                                \
+    HAL_READ_UINT32(CYGARC_REG_FPU_CPACR, regval);    \
+    regval &= ~CYGARC_REG_FPU_CPACR_ENABLE;           \
+    HAL_WRITE_UINT32(CYGARC_REG_FPU_CPACR, regval);   \
+    HAL_MEMORY_BARRIER();                             \
+CYG_MACRO_END
+
+#ifndef __ASSEMBLER__
+__externC void hal_init_fpu(void);
+#endif
+
+// Floating-point Context Address Register
+#define CYGARC_REG_FPU_FPCAR 0xE000EF38
+
+// Floating-point Default Status Control Register
+#define CYGARC_REG_FPU_FPDSCR 0xE000EF3C
+
+#define CYGARC_REG_FPU_FPDSCR_FZ            BIT_(24)
+#define CYGARC_REG_FPU_FPDSCR_DN            BIT_(25)
+#define CYGARC_REG_FPU_FPDSCR_AHP           BIT_(26)
+
+#define CYGARC_REG_FPU_FPDSCR_ROUND(__mode) VALUE_(22, (__mode))
+// where __mode is:
+#define CYGARC_REG_FPU_FPDSCR_ROUND_RN      0
+#define CYGARC_REG_FPU_FPDSCR_ROUND_RP      1
+#define CYGARC_REG_FPU_FPDSCR_ROUND_RM      2
+#define CYGARC_REG_FPU_FPDSCR_ROUND_RZ      3
+
+//==========================================================================
+// FPU Context
+#define HAL_SAVEDREGISTERS_WITH_FPU        0x80
+
+#define HAL_SAVEDREGISTERS_THREAD_FPU      (HAL_SAVEDREGISTERS_THREAD | \
+                                            HAL_SAVEDREGISTERS_WITH_FPU)
+
+#define HAL_SAVEDREGISTERS_EXCEPTION_FPU   (HAL_SAVEDREGISTERS_EXCEPTION | \
+                                            HAL_SAVEDREGISTERS_WITH_FPU)
+
+#ifndef CYGARC_CORTEXM_FPU_EXC_AUTOSAVE
+
+// Without automatic contex saving during exception or interrupt
+# define HAL_SAVEDREGISTERS_FPU_THREAD_CONTEXT_SIZE   (HAL_SAVEDREG_THREAD_FPU_N*4+4)
+# define HAL_SAVEDREG_AUTO_FRAME_SIZE                 (8*4)
+
+# define HAL_SAVEDREG_AUTO_FPU_EXCEPTION_S
+
+#else //  !CYGARC_CORTEXM_FPU_EXC_AUTOSAVE
+
+// With automatic contex saving during exception or interrupt enabled
+# if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL
+
+#  define HAL_SAVEDREG_AUTO_EXCEPTION_FPU_N    16
+#  define HAL_SAVEDREG_AUTO_FRAME_SIZE         (8*4 + 16*4 + 4 + 4)
+
+// HAL_SavedRegisters entries for floating point registers
+//     see hal_arch.h for HAL_SavedRegisters definition.
+
+#  define HAL_SAVEDREG_AUTO_FPU_EXCEPTION_S                        \
+            cyg_uint32  s_auto[HAL_SAVEDREG_AUTO_EXCEPTION_FPU_N]; \
+            cyg_uint32  fpscr_auto;                                \
+            cyg_uint32  aligner
+
+# else // defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL
+#  error  "Automatic FPU context saving is not supported in LAZY and NONE modes."
+# endif // defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL
+#endif //  !CYGARC_CORTEXM_FPU_EXC_AUTOSAVE
+
+// Common for AUTOSAVE and non AUTOSAVE
+#if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+
+// HAL_SavedRegisters entries for floating point registers
+//     see hal_arch.h for HAL_SavedRegisters definition.
+
+# define HAL_SAVEDREG_THREAD_FPU_N         32
+# define HAL_SAVEDREG_EXCEPTION_FPU_N      32
+
+# define HAL_SAVEDREG_FPU_THREAD_S                      \
+           cyg_uint32  fpscr;                           \
+           cyg_uint32  s[HAL_SAVEDREG_THREAD_FPU_N]
+
+# define HAL_SAVEDREG_FPU_EXCEPTION_S                   \
+           cyg_uint32  s[HAL_SAVEDREG_EXCEPTION_FPU_N]; \
+           cyg_uint32  fpscr;                           \
+           cyg_uint32  cpacr
+
+// Thread FP context initialization
+# define HAL_THREAD_INIT_FPU_REGS(__regs_p)                                 \
+CYG_MACRO_START                                                             \
+    int __reg_i;                                                            \
+    for(__reg_i = 0; __reg_i < HAL_SAVEDREG_THREAD_FPU_N; __reg_i++)    \
+        (__regs_p)->u.thread.s[__reg_i] = 0;                                \
+CYG_MACRO_END
+
+# define HAL_THREAD_INIT_FPU_CONTEXT(__regs_p)                              \
+CYG_MACRO_START                                                             \
+    HAL_THREAD_INIT_FPU_REGS(__regs_p);                                     \
+    (__regs_p)->u.thread.fpscr = 0;                                         \
+CYG_MACRO_END
+#else //defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+
+#  define HAL_SAVEDREG_FPU_THREAD_S
+#  define HAL_THREAD_INIT_FPU_CONTEXT(__regs) CYG_EMPTY_STATEMENT
+
+#endif //defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+//==========================================================================
+// hal_arch.h GDB stub support
+
+// Register layout expected by GDB VFP
+#ifndef __ASSEMBLER__
+typedef struct {
+    cyg_uint32 gpr[16];
+    cyg_uint32 xpsr;
+    cyg_uint32 s[32];
+    cyg_uint32 fpscr;
+} HAL_CORTEXM_GDB_Registers;
+#endif
+
+#if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+
+# define GDB_STUB_SAVEDREG_FRAME_TYPE(__regs)                        \
+         ((__regs)->u.type & ~HAL_SAVEDREGISTERS_WITH_FPU)
+
+# define GDB_STUB_SAVEDREG_FPU_THREAD_GET(__gdbreg,__regs)           \
+CYG_MACRO_START                                                      \
+    cyg_uint32 reg_i;                                                \
+    for( reg_i = 0; reg_i < HAL_SAVEDREG_THREAD_FPU_N; reg_i++ ) \
+        (__gdbreg)->s[reg_i] = (__regs)->u.thread.s[reg_i];          \
+    (__gdbreg)->fpscr = (__regs)->u.thread.fpscr;                    \
+CYG_MACRO_END
+
+# define GDB_STUB_SAVEDREG_FPU_THREAD_SET(__gdbreg,__regs)           \
+CYG_MACRO_START                                                      \
+    cyg_uint32 reg_i;                                                \
+    for( reg_i = 0; reg_i < HAL_SAVEDREG_THREAD_FPU_N; reg_i++ ) \
+        (__regs)->u.thread.s[reg_i] = (__gdbreg)->s[reg_i];          \
+    (__regs)->u.thread.fpscr = (__gdbreg)->fpscr;                    \
+CYG_MACRO_END
+
+#else //  defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+
+# define GDB_STUB_SAVEDREG_FRAME_TYPE(__regs)              ((__regs)->u.type)
+# define GDB_STUB_SAVEDREG_FPU_THREAD_GET(__gdbreg,__regs) CYG_EMPTY_STATEMENT
+# define GDB_STUB_SAVEDREG_FPU_THREAD_SET(__gdbreg,__regs) CYG_EMPTY_STATEMENT
+
+#endif //  defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+
+#define GDB_STUB_SAVEDREG_FPU_EXCEPTION_GET(__gdbreg,__regs)        \
+CYG_MACRO_START                                                     \
+    cyg_uint32 reg_i;                                               \
+    for( reg_i = 0; reg_i < HAL_SAVEDREG_EXCEPTION_FPU_N; reg_i++ ) \
+        (__gdbreg)->s[reg_i] = (__regs)->u.exception.s[reg_i];      \
+    (__gdbreg)->fpscr = (__regs)->u.exception.fpscr;                \
+CYG_MACRO_END
+
+#define GDB_STUB_SAVEDREG_FPU_EXCEPTION_SET(__gdbreg,__regs)                      \
+CYG_MACRO_START                                                                   \
+    cyg_uint32 reg_i;                                                             \
+    for( reg_i = 0; reg_i < HAL_SAVEDREG_EXCEPTION_FPU_N; reg_i++ )               \
+        (__regs)->u.exception.s[reg_i] = (__gdbreg)->s[reg_i];                    \
+    (__regs)->u.exception.fpscr = (__gdbreg)->fpscr;                              \
+    if(*(cyg_uint32 *)CYGARC_REG_FPU_FPCCR & CYGARC_REG_FPU_FPCCR_ASPEN) {        \
+        for( reg_i = 0; reg_i < HAL_SAVEDREG_AUTO_EXCEPTION_FPU_N; reg_i++ )      \
+            (__regs)->u.exception.s_auto[reg_i] = (__regs)->u.exception.s[reg_i]; \
+        (__regs)->u.exception.fpscr_auto = (__regs)->u.exception.fpscr;           \
+    }                                                                             \
+CYG_MACRO_END
+
+//==========================================================================
+// hal_arch.h Minimal and sensible stack sizes:
+// Override value in hal_arch.h
+#define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * (20+32+4+4))
+
+// GDB stub ==================================================================
+// cortexm_stub.h definitions for FPV4-SP-D16
+
+// The Cortex-M4F double registers are larger then target_register_t.
+#define TARGET_HAS_LARGE_REGISTERS
+
+// Cortex-M4F stub register handling macros
+#define CYGARC_STUB_REGISTER_ACCESS_DEFINED 1
+#define NUMREGS    (FPSCR+1)  // 16 GPR, XPSR, 10 non existent, 16 VFP, FPSCR
+#define REGSIZE( _x_ ) (_x_ <= PC ? 4 :                         \
+                        (_x_ < XPSR ? 0 :                        \
+                         (_x_ == XPSR ? 4 :                      \
+                          (((_x_ >= VD0) && (_x_ <= VD15)) ? 8 : \
+                           (_x_ == FPSCR ? 4 : 0 )))))
+#ifndef __ASSEMBLER__
+# ifndef TARGET_REGISTER_T_DEFINED
+#  define TARGET_REGISTER_T_DEFINED
+typedef unsigned long target_register_t;
+# endif
+
+enum regnames {
+    R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, SP, LR, PC,
+    XPSR = 25,
+    VD0 = 26, VD1, VD2, VD3, VD4, VD5, VD6, VD7,
+    VD8, VD9, VD10, VD11, VD12, VD13, VD14, VD15,
+    FPSCR
+};
+#endif // __ASSEMBLER__
+
+//==========================================================================
+#endif //CYGONCE_FPV4_SP_D16_H
diff --git a/packages/hal/cortexm/arch/current/include/fpv4_sp_d16_libm.h b/packages/hal/cortexm/arch/current/include/fpv4_sp_d16_libm.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/arch/current/include/fpv4_sp_d16_libm.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_FPV4_SP_D16_LIBM_H
+#define CYGONCE_FPV4_SP_D16_LIBM_H
+//==========================================================================
+//
+//      fpv4_sp_d16_libm.h
+//
+//      FPv4spD16 Floating Point Unit mathematical functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2013-06-10
+// Description:    FPv4spD16 Floating Point Unit builtin mathematical functions.
+// Usage:          include <cyg/hal/fpv4_sp_d16_libm.h>
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+#ifdef CYGSEM_LIBM_IEEE_API_INLINE
+
+// Builtin mathematical functions
+#define __ieee754_sqrtf(__x) __builtin_sqrtf(__x)
+
+#endif // CYGSEM_LIBM_IEEE_API_INLINE
+
+//==========================================================================
+#endif //CYGONCE_FPV4_SP_D16_LIBM_H
diff --git a/packages/hal/cortexm/arch/current/include/hal_arch.h b/packages/hal/cortexm/arch/current/include/hal_arch.h
--- a/packages/hal/cortexm/arch/current/include/hal_arch.h
+++ b/packages/hal/cortexm/arch/current/include/hal_arch.h
@@ -10,7 +10,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2012 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -41,19 +41,28 @@
 //==========================================================================
 //#####DESCRIPTIONBEGIN####
 //
-// Author(s):    nickg
-// Date:         2008-07-30
-// Description:  Define architecture abstractions
+// Author(s):      nickg
+// Contributor(s): ilijak
+// Date:           2008-07-30
+// Description:    Define architecture abstractions
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
+
+#ifndef __ASSEMBLER__
 
 #include <pkgconf/system.h>
 #include <pkgconf/hal.h>
 #include <cyg/infra/cyg_type.h>
 
 #include <cyg/hal/var_arch.h>
+#include <cyg/hal/cortexm_regs.h>
+
+#include <cyg/hal/cortexm_fpu.h>
+
+#endif //__ASSEMBLER__
 
 //==========================================================================
 // CPU save state
@@ -63,30 +72,43 @@
 // for each context. This makes the GDB state get/put slightly more
 // complex, but that is a suitable compromise.
 
-typedef struct 
+#define HAL_SAVEDREGISTERS_EXCEPTION    1
+#define HAL_SAVEDREGISTERS_THREAD       2
+#define HAL_SAVEDREGISTERS_INTERRUPT    3
+
+#ifndef __ASSEMBLER__
+
+typedef struct
 {
     union
     {
         cyg_uint32              type;           // State type
 
+        // Thread
         struct
         {
             cyg_uint32          type;           // State type
             cyg_uint32          basepri;        // BASEPRI
             cyg_uint32          sp;             // SP (R13)
+
+            HAL_SAVEDREG_FPU_THREAD_S;          // Floating Point Unit context
+
             cyg_uint32          r[13];          // R0..R12
             cyg_uint32          pc;             // PC/LR
         } thread;
 
+        // Exception
         struct
         {
             cyg_uint32          type;           // State type
             cyg_uint32          vector;         // Exception vector number
             cyg_uint32          basepri;        // BASEPRI
-            
+
             cyg_uint32          r4_11[8];       // Remaining CPU registers
             cyg_uint32          xlr;            // Exception return LR
-            
+#ifdef CYGSEM_HAL_DEBUG_FPU
+            HAL_SAVEDREG_FPU_EXCEPTION_S;   // Floating Point Unit context
+#endif
             // The following are saved and restored automatically by the CPU
             // for exceptions or interrupts.
 
@@ -98,12 +120,15 @@ typedef struct
             cyg_uint32          lr;
             cyg_uint32          pc;
             cyg_uint32          psr;
+
+            HAL_SAVEDREG_AUTO_FPU_EXCEPTION_S; // Floating Point Unit context
         } exception;
 
+        // Interrupt
         struct
         {
             cyg_uint32          type;           // State type
-            
+
             // The following are saved and restored automatically by the CPU
             // for exceptions or interrupts.
 
@@ -115,21 +140,22 @@ typedef struct
             cyg_uint32          lr;
             cyg_uint32          pc;
             cyg_uint32          psr;
-            
+
+            HAL_SAVEDREG_AUTO_FPU_EXCEPTION_S; // Floating Point Unit context
         } interrupt;
     } u;
 
 } HAL_SavedRegisters;
 
-#define HAL_SAVEDREGISTERS_EXCEPTION    1
-#define HAL_SAVEDREGISTERS_THREAD       2
-#define HAL_SAVEDREGISTERS_INTERRUPT    3
-
 //==========================================================================
 // Thread context initialization
 
+#ifndef HAL_THREAD_INIT_FPU_CONTEXT
+#define HAL_THREAD_INIT_FPU_CONTEXT(__regs) CYG_EMPTY_STATEMENT
+#endif
+
 #define HAL_THREAD_INIT_CONTEXT( __sparg, __thread, __entry, __id )     \
-{                                                                       \
+CYG_MACRO_START                                                         \
     register CYG_WORD __sp = ((CYG_WORD)__sparg) & ~7;                  \
     register CYG_WORD *__ep = (CYG_WORD *)(__sp -= sizeof(CYG_WORD));   \
     register HAL_SavedRegisters *__regs;                                \
@@ -139,15 +165,16 @@ typedef struct
     __regs->u.type = HAL_SAVEDREGISTERS_THREAD;                         \
     for( __i = 1; __i < 13; __i++ )                                     \
         __regs->u.thread.r[__i] = 0;                                    \
+    HAL_THREAD_INIT_FPU_CONTEXT(__regs);                                \
     *__ep = (CYG_WORD)(__entry);                                        \
     __regs->u.thread.sp       = (CYG_WORD)(__sp);                       \
     __regs->u.thread.r[0]     = (CYG_WORD)(__thread);                   \
     __regs->u.thread.r[1]     = (CYG_WORD)(__id);                       \
-    __regs->u.thread.r[11]     = (CYG_WORD)(__ep);                      \
+    __regs->u.thread.r[11]    = (CYG_WORD)(__ep);                       \
     __regs->u.thread.pc       = (CYG_WORD)__entry;                      \
     __regs->u.thread.basepri  = 0;                                      \
     __sparg = (CYG_ADDRESS)__regs;                                      \
-}
+CYG_MACRO_END
 
 //==========================================================================
 // Context switch macros.
@@ -168,17 +195,30 @@ typedef struct
 
 //==========================================================================
 // Fetch PC from saved state
-
-#define CYGARC_HAL_GET_PC_REG(__regs,__val)                             \
-{                                                                       \
-    switch( (__regs)->u.type )                                          \
-    {                                                                   \
-    case HAL_SAVEDREGISTERS_THREAD   : (__val) = (__regs)->u.thread.pc; break; \
+#if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || \
+    defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+#define CYGARC_HAL_GET_PC_REG(__regs,__val)                                       \
+{                                                                                 \
+    switch(GDB_STUB_SAVEDREG_FRAME_TYPE(__regs))                                                    \
+    {                                                                             \
+    case HAL_SAVEDREGISTERS_THREAD:    (__val) = (__regs)->u.thread.pc; break;    \
     case HAL_SAVEDREGISTERS_EXCEPTION: (__val) = (__regs)->u.exception.pc; break; \
     case HAL_SAVEDREGISTERS_INTERRUPT: (__val) = (__regs)->u.interrupt.pc; break; \
-    }                                                                   \
+    default: (__val) = 0;                                                         \
+    }                                                                             \
 }
-
+#else
+#define CYGARC_HAL_GET_PC_REG(__regs,__val)                                       \
+{                                                                                 \
+    switch( (__regs)->u.type )                                                    \
+    {                                                                             \
+    case HAL_SAVEDREGISTERS_THREAD   : (__val) = (__regs)->u.thread.pc; break;    \
+    case HAL_SAVEDREGISTERS_EXCEPTION: (__val) = (__regs)->u.exception.pc; break; \
+    case HAL_SAVEDREGISTERS_INTERRUPT: (__val) = (__regs)->u.interrupt.pc; break; \
+    default: (__val) = 0;                                                         \
+    }                                                                             \
+}
+#endif
 //==========================================================================
 // Exception handling function
 // This function is defined by the kernel according to this prototype. It is
@@ -220,7 +260,7 @@ externC void cyg_hal_deliver_exception( 
 // Breakpoint support
 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen
 // if executed.
-// HAL_BREAKINST is the value of the breakpoint instruction and 
+// HAL_BREAKINST is the value of the breakpoint instruction and
 // HAL_BREAKINST_SIZE is its size in bytes.
 
 #define HAL_BREAKINST           0xbebe         // BKPT
@@ -240,7 +280,8 @@ externC void cyg_hal_deliver_exception( 
 //==========================================================================
 // GDB support
 
-// Register layout expected by GDB
+#ifdef CYGARC_CORTEXM_GDB_REG_FPA
+// Register layout expected by GDB FPA
 typedef struct
 {
     cyg_uint32  gpr[16];
@@ -253,8 +294,9 @@ typedef struct
     cyg_uint32  f6[3];
     cyg_uint32  f7[3];
     cyg_uint32  fps;
-    cyg_uint32  ps;
+    cyg_uint32  xpsr;
 } HAL_CORTEXM_GDB_Registers;
+#endif
 
 // Translate a stack pointer as saved by the thread context macros
 // into a pointer to a HAL_SavedRegisters structure. On the Cortex-M
@@ -312,7 +354,9 @@ typedef cyg_uint32 hal_jmp_buf[CYGARC_JM
 #define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 20)
 
 // Stack needed for a context switch
+#if !defined CYGNUM_HAL_STACK_CONTEXT_SIZE
 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 20)
+#endif
 
 // Interrupt + call to ISR, interrupt_end() and the DSR
 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE \
@@ -340,6 +384,7 @@ typedef cyg_uint32 hal_jmp_buf[CYGARC_JM
 #define CYGARC_HAL_SAVE_GP()
 #define CYGARC_HAL_RESTORE_GP()
 
+#endif // __ASSEMBLER__
+
 //==========================================================================
 #endif //CYGONCE_HAL_ARCH_H
-
diff --git a/packages/hal/cortexm/arch/current/include/hal_arch.inc b/packages/hal/cortexm/arch/current/include/hal_arch.inc
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/arch/current/include/hal_arch.inc
@@ -0,0 +1,115 @@
+/*==========================================================================
+//
+//      hal_arch.inc
+//
+//      Cortex-M exception vector macros
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):       ilijak
+// Contributors(s):
+// Date:            2012-07-08
+// Description:     This file defines some GAS macros exception VSRs.
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#ifdef CYGHWR_HAL_CORTEXM_FPU
+
+# ifdef CYGINT_HAL_FPV4_SP_D16
+
+//============================================================================
+// LAZY context switching scheme keeps FPU disabled for the threads that
+// don't use floating point. We need to enable it before we save FPU context
+// in order to avoid Usage Fault exception.
+
+        .macro hal_fpu_enable
+        ldr    r1,=CYGARC_REG_FPU_CPACR
+        ldr    r2,[r1]
+        stmdb  r0!,{r2}           // Save thread's CPACR state
+        orr    r2,#CYGARC_REG_FPU_CPACR_ENABLE
+        str    r2,[r1]
+        .endm
+
+//============================================================================
+// Restore thread's FPU usage state.
+// undo hal_fpu_enable
+
+        .macro hal_fpu_undo_enable
+        ldmia  r0!,{r2}           // Retrieve previous thread's CPACR state
+        ldr    r1,=CYGARC_REG_FPU_CPACR
+        str    r2,[r1]
+        .endm
+
+//============================================================================
+// Store FPU context during exception if FPU was disabled then enamble it.
+
+        .macro hal_fpu_exc_push
+        hal_fpu_enable
+        vmrs         r1,fpscr
+        stmdb        r0!,{r1}
+        vstmdb.f64   r0!,{d0-d15}
+        .endm
+
+//============================================================================
+// Restore FPU context during exception and undo FPU enable.
+
+        .macro hal_fpu_exc_pop
+        vldmia.f64   r0!,{d0-d15}
+        ldmia        r0!,{r1}
+        vmsr         fpscr,r1
+        hal_fpu_undo_enable
+        .endm
+
+//============================================================================
+// Make fake fpu frame for hal_pendable_svc_vsr
+
+        .macro hal_fpu_isr_fake_frame_push
+        sub        r12,#4
+        vmrs       r1,fpscr
+        stmdb      r12!,{r1}
+        vstmdb.f32 r12!,{s0-s15}
+        .endm
+
+# else // CYGINT_HAL_FPV4_SP_D16
+#  error Unknown Floating Point Unit!
+# endif // CYGINT_HAL_FPV4_SP_D16
+
+#endif //CYGHWR_HAL_CORTEXM_FPU
+
+// end of hal_arch.inc
diff --git a/packages/hal/cortexm/arch/current/include/hal_intr.h b/packages/hal/cortexm/arch/current/include/hal_intr.h
--- a/packages/hal/cortexm/arch/current/include/hal_intr.h
+++ b/packages/hal/cortexm/arch/current/include/hal_intr.h
@@ -10,7 +10,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -47,7 +47,8 @@
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 #include <pkgconf/system.h>
 #include <pkgconf/hal.h>
@@ -71,7 +72,7 @@
 #define CYGNUM_HAL_VECTOR_MEMORY_MAN     4      // Memory management (M3)
 #define CYGNUM_HAL_VECTOR_BUS_FAULT      5      // Bus Fault
 #define CYGNUM_HAL_VECTOR_USAGE_FAULT    6      // Usage Fault
-#define CYGNUM_HAL_VECTOR_RESERVED_07    7      
+#define CYGNUM_HAL_VECTOR_RESERVED_07    7
 #define CYGNUM_HAL_VECTOR_RESERVED_08    8
 #define CYGNUM_HAL_VECTOR_RESERVED_09    9
 #define CYGNUM_HAL_VECTOR_RESERVED_10   10
@@ -92,13 +93,18 @@
 #define CYGNUM_HAL_INTERRUPT_SYS_TICK    0
 #define CYGNUM_HAL_INTERRUPT_EXTERNAL    1
 
-#define CYGNUM_HAL_INTERRUPT_RTC        CYGNUM_HAL_INTERRUPT_SYS_TICK
 
 //==========================================================================
 // Include variant definitions here.
 
 #include <cyg/hal/var_intr.h>
 
+// Variant or platform allowed to override these definitions to use
+// a different RTC
+#ifndef CYGNUM_HAL_INTERRUPT_RTC
+#define CYGNUM_HAL_INTERRUPT_RTC        CYGNUM_HAL_INTERRUPT_SYS_TICK
+#endif
+
 //==========================================================================
 // Exception vectors.
 //
@@ -163,7 +169,7 @@ CYG_MACRO_END
 //
 // Interrupt handler/data/object tables plus functions and macros to
 // manipulate them.
- 
+
 __externC volatile CYG_ADDRESS   hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
 __externC volatile CYG_ADDRWORD  hal_interrupt_data    [CYGNUM_HAL_ISR_COUNT];
 __externC volatile CYG_ADDRESS   hal_interrupt_objects [CYGNUM_HAL_ISR_COUNT];
@@ -235,7 +241,7 @@ typedef cyg_uint32  CYG_INTERRUPT_STATE;
         "mrs    %0, basepri             \n"     \
         "mov    r1,%1                   \n"     \
         "msr    basepri,r1              \n"     \
-        : "=r" (__old)                          \
+        : "=&r" (__old)                         \
         :  "r" (CYGNUM_HAL_CORTEXM_PRIORITY_MAX)\
         : "r1"                                  \
         );
@@ -298,7 +304,7 @@ typedef cyg_uint32  CYG_INTERRUPT_STATE;
 {                                                       \
     __asm__ volatile (                                  \
         "ldr     r3,=hal_call_dsrs_vsr          \n"     \
-        "swi                                    \n"     \
+        "swi 0                                  \n"     \
         :                                               \
         :                                               \
         : "r3"                                          \
@@ -321,10 +327,20 @@ typedef cyg_uint32  CYG_INTERRUPT_STATE;
 //==========================================================================
 // Clock control
 //
-// This uses the CPU SysTick timer.
+// This uses the CPU SysTick timer. Variant or platform allowed to override
+// these definitions
+
+#ifndef CYGHWR_HAL_CLOCK_DEFINED
 
 __externC cyg_uint32 hal_cortexm_systick_clock;
 
+// Select the clock source of the system tick timer
+#ifdef CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE_EXTERNAL
+ #define CYGARC_REG_SYSTICK_CSR_CLK_SRC CYGARC_REG_SYSTICK_CSR_CLK_EXT
+#elif defined(CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE_INTERNAL)
+ #define CYGARC_REG_SYSTICK_CSR_CLK_SRC CYGARC_REG_SYSTICK_CSR_CLK_INT
+#endif
+
 #define HAL_CLOCK_INITIALIZE( __period )                                \
 {                                                                       \
     cyg_uint32 __p = __period;                                          \
@@ -333,12 +349,12 @@ typedef cyg_uint32  CYG_INTERRUPT_STATE;
                      __p );                                             \
     HAL_WRITE_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR,    \
                      CYGARC_REG_SYSTICK_CSR_ENABLE      |               \
-                     CYGARC_REG_SYSTICK_CSR_CLK_EXT     );              \
+                     CYGARC_REG_SYSTICK_CSR_CLK_SRC     );              \
 }
 
 #define HAL_CLOCK_RESET( __vector, __period )                           \
 {                                                                       \
-    cyg_uint32 __csr;                                                   \
+    cyg_uint32 __csr CYGBLD_ATTRIB_UNUSED;                              \
     HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, __csr ); \
 }
 
@@ -352,8 +368,20 @@ typedef cyg_uint32  CYG_INTERRUPT_STATE;
     *(__pvalue) = __value;                                              \
 }
 
+#define HAL_CLOCK_READ_NS( __pvalue )                                              \
+CYG_MACRO_START                                                                                  \
+    cyg_uint32 __period, __value;                                                  \
+    HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_RELOAD, __period ); \
+    HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_VALUE, __value );   \
+    __value = (( __period + 1 ) - __value) * 1000;                                          \
+    __value /= (hal_cortexm_systick_clock / 1000000 );                  \
+    *(__pvalue) = __value;                                                         \
+CYG_MACRO_END
+
 #define HAL_CLOCK_LATENCY( __pvalue ) HAL_CLOCK_READ( __pvalue )
 
+#endif // CYGHWR_HAL_CLOCK_DEFINED
+
 //==========================================================================
 // HAL_DELAY_US().
 //
@@ -379,4 +407,3 @@ typedef cyg_uint32  CYG_INTERRUPT_STATE;
 
 //==========================================================================
 #endif //CYGONCE_HAL_INTR_H
-
diff --git a/packages/hal/cortexm/arch/current/include/hal_io.h b/packages/hal/cortexm/arch/current/include/hal_io.h
--- a/packages/hal/cortexm/arch/current/include/hal_io.h
+++ b/packages/hal/cortexm/arch/current/include/hal_io.h
@@ -47,7 +47,8 @@
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 #include <pkgconf/system.h>
 #include <pkgconf/hal.h>
@@ -92,7 +93,7 @@
 
 #define CYGARC_REG_NVIC_BASE                    0xE000E000
 
-#if defined(CYGHWR_HAL_CORTEXM_M3)
+#if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4)
 #define CYGARC_REG_NVIC_TYPE                    0x004
 #endif
 
@@ -117,7 +118,7 @@
 #define CYGARC_REG_NVIC_PR(__intr)              (CYGARC_REG_NVIC_PR0+(__intr))
 
 
-#if defined(CYGHWR_HAL_CORTEXM_M3)
+#if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4)
 
 #define CYGARC_REG_NVIC_CPUID                   0xD00
 #define CYGARC_REG_NVIC_ICSR                    0xD04
@@ -179,7 +180,9 @@
 
 #define CYGARC_REG_NVIC_VTOR_TBLOFF(__o)        VALUE_(7,__o)
 #define CYGARC_REG_NVIC_VTOR_TBLBASE_CODE       0
+#ifndef CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM
 #define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM       BIT_(29)
+#endif
 
 // AI/RCR
 
@@ -213,12 +216,22 @@
 #define CYGARC_REG_NVIC_SHCSR_BUSFAULTACT       BIT_(1)
 #define CYGARC_REG_NVIC_SHCSR_MEMFAULTACT       BIT_(0)
 
+// Usage Fault register
+
+#define CYGARC_REG_UFSR                         0xE000ED2A
+#define CYGARC_REG_UFSR_DIVBYZERO               BIT_(9)
+#define CYGARC_REG_UFSR_UNALIGNED               BIT_(8)
+#define CYGARC_REG_UFSR_NOCP                    BIT_(3)
+#define CYGARC_REG_UFSR_INVPC                   BIT_(2)
+#define CYGARC_REG_UFSR_INVSTATE                BIT_(1)
+#define CYGARC_REG_UFSR_UNDEFINSTR              BIT_(0)
+
 #endif
 
 //==========================================================================
 // Debug registers
 
-#if defined(CYGHWR_HAL_CORTEXM_M3)
+#if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4)
 
 #define CYGARC_REG_DEBUG_BASE                   0xE000EDF0
 
@@ -316,7 +329,7 @@ typedef volatile CYG_ADDRWORD HAL_IO_REG
 //-----------------------------------------------------------------------------
 // 16 bit access.
 // Individual and vectorized access to 16 bit registers.
-    
+
 
 #define HAL_READ_UINT16( _register_, _value_ ) \
         ((_value_) = *((volatile CYG_WORD16 *)(_register_)))
@@ -395,7 +408,7 @@ typedef volatile CYG_ADDRWORD HAL_IO_REG
 
 #endif // !HAL_IO_MACROS_DEFINED
 
-// Enforce a flow "barrier" to prevent optimizing compiler from reordering 
+// Enforce a flow "barrier" to prevent optimizing compiler from reordering
 // operations.
 #define HAL_IO_BARRIER()
 
diff --git a/packages/hal/cortexm/arch/current/src/context.S b/packages/hal/cortexm/arch/current/src/context.S
--- a/packages/hal/cortexm/arch/current/src/context.S
+++ b/packages/hal/cortexm/arch/current/src/context.S
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2012 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -39,13 +39,15 @@
 //==========================================================================
 //#####DESCRIPTIONBEGIN####
 //
-// Author(s):    nickg
-// Date:         2008-07-30
-// Description:  This file contains thread context switch code.
+// Author(s):      nickg, ilijak (FPU support)
+// Contributor(s):
+// Date:           2008-07-30
+// Description:    This file contains thread context switch code.
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 #include <pkgconf/system.h>
 #include <pkgconf/hal.h>
@@ -54,18 +56,150 @@
 #include <pkgconf/kernel.h>
 #endif
 
+#ifdef CYGHWR_HAL_CORTEXM_FPU
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/cortexm_fpu.h>        // Optional Floating Point Unit
+
+#endif
+
 //==========================================================================
 
         .syntax unified
         .thumb
         .text
-        
+
 //==========================================================================
 // Context switch
 //
 // R0 contains a pointer to the SP of the thread to load, R1 contains
-// a pointer to the SP of the current thread.        
-        
+// a pointer to the SP of the current thread.
+
+#ifdef CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+//==========================================================================
+// LAZY Context switch
+//
+// Save the FPU registers only for threads that use FPU.
+//
+
+        .globl  hal_thread_switch_context
+        .thumb
+        .thumb_func
+        .type   hal_thread_switch_context, %function
+hal_thread_switch_context:
+
+        push      {r0-r12,lr}                       // Push all savable register
+        ldr       r7,=CYGARC_REG_FPU_CPACR          //
+        ldr       r6,[r7]
+        tst       r6,#CYGARC_REG_FPU_CPACR_ENABLE   // Is FPU enabled?
+        beq       lazy_float_push                   // N: Be lazy.
+        vmrs      r5,fpscr                          // Y: Save FPU context
+        vpush.f64 {d0-d15}                          //   Push FPU registers
+        push      {r5}                              //   together with FPSCR
+        mov       r2,#HAL_SAVEDREGISTERS_THREAD_FPU // Set state type: thread with FPU
+        b         float_push_join
+   lazy_float_push:
+        mov       r2,#HAL_SAVEDREGISTERS_THREAD
+        sub       sp,#HAL_SAVEDREGISTERS_FPU_THREAD_CONTEXT_SIZE
+   float_push_join:
+        mrs       r3,basepri                        // Get priority base register
+        mov       r4,sp                             // Get SP (for info only)
+        push      {r2-r4}                           // Push them
+        str       sp,[r1]                           // Save SP
+        // Fall through
+
+//--------------------------------------------------------------------------
+// Load context
+//
+// This is used to load a thread context, abandoning the current one. Following
+// function part is the second half of hal_thread_switch_context.
+
+
+        .globl  hal_thread_load_context
+        .thumb
+        .thumb_func
+        .type   hal_thread_load_context, %function
+hal_thread_load_context_common:
+
+        ldr      sp,[r0]                // Load SP
+        pop      {r2-r4}                // Pop type, basepri, SP(discarded) and FPSCR
+        msr      basepri,r3             // Set BASEPRI
+        cmp      r2,#HAL_SAVEDREGISTERS_THREAD_FPU // Is state type a FP thread?
+        beq      real_float_pop // Y:
+                                // N: Be lazy
+        and      r6,#~CYGARC_REG_FPU_CPACR_ENABLE
+        add      sp,#HAL_SAVEDREGISTERS_FPU_THREAD_CONTEXT_SIZE
+        str      r6,[r7]
+        pop      {r0-r12,pc} // Pop all registers and return to an non-FP thread
+
+   real_float_pop: // Restore floating point context for FP thread.
+        orr      r6,#CYGARC_REG_FPU_CPACR_ENABLE
+        pop      {r5}           // Retrieve FPU status register
+        str      r6,[r7]
+        dsb
+        isb
+        vpop.f64 {d0-d15}       // Pestore FPU registers
+        vmsr     fpscr,r5       // Restore FPU status register
+        pop      {r0-r12,pc}    // Pop all registers and return to a FP thread.
+
+// Load context entry point
+// Load context initially needs CPACR register, so it is provided here.
+hal_thread_load_context:
+        ldr      r7,=CYGARC_REG_FPU_CPACR
+        ldr      r6,[r7]
+        b        hal_thread_load_context_common
+
+#elif defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL
+
+//==========================================================================
+// ALL Context switch
+//
+// Save the FPU registers for all threads.
+//
+
+        .globl  hal_thread_switch_context
+        .thumb
+        .thumb_func
+        .type   hal_thread_switch_context, %function
+hal_thread_switch_context:
+
+        push      {r0-r12,lr}                       // Push all savable register
+        vmrs      r5,fpscr
+        mov       r2,#HAL_SAVEDREGISTERS_THREAD_FPU // Set state type == thread
+        vpush.f64 {d0-d15}                          // Push FPU registers
+        sub       r4,sp,#4                          // Get SP (for info only)
+        mrs       r3,basepri                        // Get priority base register
+        push      {r2-r5}                           // Push them
+        str       sp,[r1]                           // Save SP
+        // Fall through
+
+//--------------------------------------------------------------------------
+// Load context
+//
+// This is used to load a thread context, abandoning the current one. This
+// function is also the second half of hal_thread_switch_context.
+
+
+        .globl  hal_thread_load_context
+        .thumb
+        .thumb_func
+        .type   hal_thread_load_context, %function
+hal_thread_load_context:
+
+        ldr      sp,[r0]                // Load SP
+        pop      {r2-r5}                // Pop type, basepri,SP(discarded) and FPSCR
+        msr      basepri,r3             // Set BASEPRI
+        vpop.f64 {d0-d15}               // Pop FPU registers
+        vmsr     fpscr,r5               // and FPU status register
+        pop      {r0-r12,pc}            // Pop all register and return
+
+#else
+
+//==========================================================================
+// NONE Context switch
+//
+// No FPU or NONE context saving scheme. Do not save FPU registers.
+//
+
         .globl  hal_thread_switch_context
         .thumb
         .thumb_func
@@ -77,11 +211,11 @@ hal_thread_switch_context:
         mrs     r3,basepri              // Get priority base register
         mov     r4,sp                   // Get SP (for info only)
         push    {r2-r4}                 // Push them
-        
+
         str     sp,[r1]                 // Save SP
 
         // Fall through
-        
+
 //--------------------------------------------------------------------------
 // Load context
 //
@@ -99,16 +233,18 @@ hal_thread_load_context:
         msr     basepri,r3              // Set BASEPRI
         pop     {r0-r12,pc}             // Pop all register and return
 
-//==========================================================================        
+#endif
+
+//==========================================================================
 //  HAL longjmp, setjmp implementations
-//        
+//
 //  hal_setjmp saves only to callee save registers R4-14
 //  and LR into buffer supplied in r0[arg0].
 
         .globl  hal_setjmp
         .thumb
         .thumb_func
-        .type   hal_setjmp, %function        
+        .type   hal_setjmp, %function
 hal_setjmp:
         mov     r3,sp
         stmea   r0,{r3-r12,r14}
@@ -116,7 +252,7 @@ hal_setjmp:
         bx      lr
 
 //  hal_longjmp loads state from r0[arg0] and returns
-        
+
         .globl  hal_longjmp
         .thumb
         .thumb_func
diff --git a/packages/hal/cortexm/arch/current/src/cortexm.ld b/packages/hal/cortexm/arch/current/src/cortexm.ld
--- a/packages/hal/cortexm/arch/current/src/cortexm.ld
+++ b/packages/hal/cortexm/arch/current/src/cortexm.ld
@@ -6,7 +6,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -42,7 +42,7 @@
 STARTUP(vectors.o)
 ENTRY(reset_vector)
 INPUT(extras.o)
-GROUP(libtarget.a libgcc.a libsupc++.a)
+GROUP(CYGBLD_HAL_LINKER_GROUPED_LIBS)
 
 #if defined(__ARMEB__)
 OUTPUT_FORMAT(elf32-bigarm)
@@ -266,6 +266,13 @@ OUTPUT_FORMAT(elf32-bigarm)
     __bss_end = ABSOLUTE (.); } \
     > _region_
 
+#define USER_SECTION(_name_, _region_,  _vma_, _lma_) \
+    ._name_ _vma_ : _lma_ \
+    { __ ## _name_ ## _start = ABSOLUTE (.); \
+     *(._name_*) \
+    __ ## _name_ ## _end = ABSOLUTE (.); } \
+    > _region_
+
 #define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .);
 
 #include <pkgconf/hal_cortexm.h>
diff --git a/packages/hal/cortexm/arch/current/src/cortexm_fpu.c b/packages/hal/cortexm/arch/current/src/cortexm_fpu.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/arch/current/src/cortexm_fpu.c
@@ -0,0 +1,97 @@
+/*==========================================================================
+//
+//      cortexm_fpu.c
+//
+//      Cortex-M exception vectors
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2012-05-30
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/cortexm_regs.h>       // Special Cortex-M asm instructions
+
+#include <cyg/hal/cortexm_fpu.h>        // Optional Floating Point Unit
+
+#ifdef CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+//============================================================================
+// FPU Usage Fault VSR handler
+// Execution of Floating Point instruction when FPU is disabled
+// generates usage fault exception. In LAZY context switching scheme
+// it is used for detection of FPU usage by threads.
+//
+cyg_uint32 hal_deliver_usagefault_fpu_exception(void) {
+    cyg_uint32 regval;
+
+    HAL_READ_UINT32(CYGARC_REG_FPU_CPACR, regval);
+    if(!((regval & CYGARC_REG_FPU_CPACR_ENABLE) ^ CYGARC_REG_FPU_CPACR_ENABLE)){
+        CYG_FAIL("Usage fault exception other than FPU!!!");
+    } else {
+        HAL_READ_UINT32(CYGARC_REG_UFSR, regval);
+        if(regval & CYGARC_REG_UFSR_NOCP){
+            // Floating point instruction has occured
+            // Enable FPU
+            HAL_CORTEXM_FPU_ENABLE();
+            CYGARC_VMSR(fpscr, 0);
+            HAL_MEMORY_BARRIER();
+            HAL_WRITE_UINT32(CYGARC_REG_UFSR, CYGARC_REG_UFSR_NOCP);
+        } else {
+            CYG_FAIL("Usage fault exception other than FPU/NOCP!!!");
+        }
+    }
+    HAL_READ_UINT32(CYGARC_REG_UFSR, regval);
+    return regval;
+}
+#endif // CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+
+//==========================================================================
+// EOF cortexm_fpu.c
diff --git a/packages/hal/cortexm/arch/current/src/cortexm_stub.c b/packages/hal/cortexm/arch/current/src/cortexm_stub.c
--- a/packages/hal/cortexm/arch/current/src/cortexm_stub.c
+++ b/packages/hal/cortexm/arch/current/src/cortexm_stub.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2012 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -39,12 +39,14 @@
 //==========================================================================
 //#####DESCRIPTIONBEGIN####
 //
-// Author(s):    nickg
-// Date:         2008-07-30
+// Author(s):      nickg
+// Contributor(s): ilijak, jifl
+// Date:           2008-07-30
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 #include <stddef.h>
 
@@ -84,6 +86,8 @@ int __computeSignal (unsigned int trap_n
     case CYGNUM_HAL_VECTOR_NMI:
     case CYGNUM_HAL_VECTOR_SYS_TICK:
         return SIGINT;
+    case CYGNUM_HAL_VECTOR_USAGE_FAULT:
+        return SIGFPE;
     default:
         return SIGTRAP;
     }
@@ -102,7 +106,7 @@ int __get_trap_number (void)
 
 
 //==========================================================================
-/* Set the currently-saved pc register value to PC. */
+// Set the currently-saved pc register value to PC.
 
 void set_pc (target_register_t pc)
 {
@@ -115,37 +119,28 @@ void set_pc (target_register_t pc)
 static int
 reg_offset(regnames_t reg)
 {
-    int base_offset;
-
-    if (reg < F0)
-	return reg * 4;
-
-    base_offset = 16 * 4;
+    int reg_i, offset = 0;
 
-    if (reg < FPS)
-	return base_offset + ((reg - F0) * 12);
-
-    base_offset += (8 * 12);
-
-    if (reg <= PS)
-	return base_offset + ((reg - FPS) * 4);
-
-    return -1;  // Should never happen!
+    for(reg_i = 0; reg_i < NUMREGS; reg_i++) {
+        if(reg_i == reg)
+            break;
+        offset += REGSIZE(reg_i);
+    }
+    return (NUMREGS == reg_i || 0 == REGSIZE(reg_i)) ? -1 : offset;
 }
 
-
 //==========================================================================
 // Return the currently-saved value corresponding to register REG of
 // the exception context.
 
-target_register_t 
+target_register_t
 get_register (regnames_t reg)
 {
     target_register_t val;
     int offset = reg_offset(reg);
 
     if (REGSIZE(reg) > sizeof(target_register_t) || offset == -1)
-	return -1;
+        return -1;
 
     val = _registers[offset/sizeof(target_register_t)];
 
@@ -156,13 +151,13 @@ get_register (regnames_t reg)
 // Store VALUE in the register corresponding to WHICH in the exception
 // context.
 
-void 
+void
 put_register (regnames_t which, target_register_t value)
 {
     int offset = reg_offset(which);
 
     if (REGSIZE(which) > sizeof(target_register_t) || offset == -1)
-	return;
+        return;
 
     _registers[offset/sizeof(target_register_t)] = value;
 }
@@ -178,8 +173,8 @@ get_register_as_bytes (regnames_t which,
     int offset = reg_offset(which);
 
     if (offset != -1) {
-	memcpy (value, (char *)_registers + offset, REGSIZE(which));
-	return 1;
+        memcpy (value, (char *)_registers + offset, REGSIZE(which));
+        return 1;
     }
     return 0;
 }
@@ -195,8 +190,8 @@ put_register_as_bytes (regnames_t which,
     int offset = reg_offset(which);
 
     if (offset != -1) {
-	memcpy ((char *)_registers + offset, value, REGSIZE(which));
-	return 1;
+        memcpy ((char *)_registers + offset, value, REGSIZE(which));
+        return 1;
     }
     return 0;
 }
@@ -229,8 +224,8 @@ void __single_step (void)
 
     // Clear any bits set in DFSR
     base = CYGARC_REG_NVIC_BASE;
-    HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_DFSR, 0xFFFFFFFF );    
-    
+    HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_DFSR, 0xFFFFFFFF );
+
 }
 
 //==========================================================================
@@ -251,7 +246,7 @@ void __clear_single_step (void)
 
     // Clear any bits set in DFSR
     base = CYGARC_REG_NVIC_BASE;
-    HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_DFSR, 0xFFFFFFFF );        
+    HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_DFSR, 0xFFFFFFFF );
 }
 
 //==========================================================================
@@ -287,9 +282,7 @@ int
 void __skipinst (void)
 {
     unsigned long pc = get_register(PC);
-
     pc += 2;
-
     put_register(PC, pc);
 }
 
diff --git a/packages/hal/cortexm/arch/current/src/fpv4_sp_d16.c b/packages/hal/cortexm/arch/current/src/fpv4_sp_d16.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/arch/current/src/fpv4_sp_d16.c
@@ -0,0 +1,105 @@
+//==========================================================================
+//
+//      fpv4_sp_d16.c
+//
+//      FPv4-SP-D16 support
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2012-05-30
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/cortexm_regs.h>       // Special Cortex-M asm instructions
+
+#include <cyg/hal/cortexm_fpu.h>        // Optional Floating Point Unit
+
+
+#define CYGARC_REG_NVIC_ACTLR                   (CYGARC_REG_NVIC_BASE + 0x008)
+#define CYGARC_REG_NVIC_ACTLR_DISFCA            BIT_(8)
+//==========================================================================
+// FPU is disbled upon reset. Dependent on FPU context switching model it
+// may be enabled.
+
+void hal_init_fpu(void)
+{
+    cyg_uint32 regval;
+
+    // Initialize FPU according to context switch model.
+    // Disable FPU so we could access FPCCR
+    HAL_CORTEXM_FPU_DISABLE();
+
+#if defined CYGARC_CORTEXM_FPU_EXC_AUTOSAVE
+    // Enable automatic exception FPU context saving.
+    HAL_READ_UINT32(CYGARC_REG_FPU_FPCCR, regval);
+    regval |= CYGARC_REG_FPU_FPCCR_LSPEN | CYGARC_REG_FPU_FPCCR_ASPEN;
+    HAL_WRITE_UINT32(CYGARC_REG_FPU_FPCCR, regval);
+    HAL_MEMORY_BARRIER();
+#else
+    // Disable automatic exception FPU context saving.
+    CYGARC_MRS(regval, control);
+    regval &= ~CYGARC_REG_CONTROL_FPCA_M;
+    CYGARC_MSR(control, regval);
+    HAL_READ_UINT32(CYGARC_REG_FPU_FPCCR, regval);
+    regval &= ~(CYGARC_REG_FPU_FPCCR_LSPEN | CYGARC_REG_FPU_FPCCR_ASPEN);
+    HAL_WRITE_UINT32(CYGARC_REG_FPU_FPCCR, regval);
+    HAL_MEMORY_BARRIER();
+#endif
+
+#if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_NONE || \
+    defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL
+    // Enable FPU
+    HAL_CORTEXM_FPU_ENABLE();
+    CYGARC_VMSR(fpscr, 0);
+#endif
+}
+
+//==========================================================================
+// EOF fpv4_sp_d16.c
diff --git a/packages/hal/cortexm/arch/current/src/hal_misc.c b/packages/hal/cortexm/arch/current/src/hal_misc.c
--- a/packages/hal/cortexm/arch/current/src/hal_misc.c
+++ b/packages/hal/cortexm/arch/current/src/hal_misc.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2012 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -39,12 +39,14 @@
 //==========================================================================
 //#####DESCRIPTIONBEGIN####
 //
-// Author(s):    nickg
-// Date:         2008-07-30
+// Author(s):      nickg
+// Contributor(s): ilijak
+// Date:           2008-07-30
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 #include <pkgconf/hal.h>
 #include <pkgconf/hal_cortexm.h>
@@ -59,9 +61,12 @@
 
 #include <cyg/hal/hal_arch.h>           // HAL header
 #include <cyg/hal/hal_intr.h>           // HAL header
-
+#include <cyg/hal/cortexm_regs.h>       // Special Cortex-M asm instructions
 #include <cyg/hal/drv_api.h>
 
+#ifdef CYGHWR_HAL_CORTEXM_FPU
+#include <cyg/hal/cortexm_fpu.h>        // Optional Floating Point Unit
+#endif
 
 #if defined(CYGPKG_KERNEL_INSTRUMENT) &&        \
     defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
@@ -81,6 +86,9 @@ typedef cyg_uint32 cyg_isr(cyg_uint32 ve
 __externC void hal_default_svc_vsr( void );
 __externC void hal_pendable_svc_vsr( void );
 __externC void hal_switch_state_vsr( void );
+#ifdef CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+__externC void hal_usagefault_exception_vsr( void );
+#endif
 
 // HAL and eCos functions
 __externC void hal_system_init( void );
@@ -128,9 +136,14 @@ void hal_reset_vsr( void )
     // usually supplied by the platform HAL. Calls to
     // hal_variant_init() and hal_platform_init() later will perform
     // the main initialization.
-    
+
     hal_system_init();
-    
+#if defined CYGHWR_HAL_CORTEXM_FPU
+    // Floating Point Unit is disabled after reset.
+    // Enable it unless for LAZY context switching scheme.
+    hal_init_fpu();
+#endif
+
     // Initialize vector table in base of SRAM.
     {
         register int i;
@@ -140,39 +153,41 @@ void hal_reset_vsr( void )
         // Only install the exception vectors for non-RAM startup. For
         // RAM startup we want these to continue to point to the original
         // VSRs, which will belong to RedBoot or GDB stubs.
-        
+
         for( i = 2; i < 15; i++ )
             hal_vsr_table[i] = (CYG_ADDRESS)hal_default_exception_vsr;
+#endif // !defined(CYG_HAL_STARTUP_RAM)
+        // Always point SVC and PENDSVC vectors to our local versions
 
-#endif
-        // Always point SVC and PENDSVC vectors to our local versions
-        
         hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr;
         hal_vsr_table[CYGNUM_HAL_VECTOR_PENDSV] = (CYG_ADDRESS)hal_pendable_svc_vsr;
+#ifdef CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+        // Install UsageFault and HardFault to trap the FPU usage exceptions.
+        HAL_VSR_SET(CYGNUM_HAL_VECTOR_USAGE_FAULT, hal_usagefault_exception_vsr, NULL);
+        HAL_VSR_SET(CYGNUM_HAL_VECTOR_HARD_FAULT, hal_usagefault_exception_vsr, NULL);
+#endif // CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
 
         // For all startup type, redirect interrupt vectors to our VSR.
         for( i = CYGNUM_HAL_VECTOR_SYS_TICK ;
-             i < CYGNUM_HAL_VECTOR_SYS_TICK + CYGNUM_HAL_VSR_MAX;
+             i < CYGNUM_HAL_VSR_MAX;
              i++ )
             hal_vsr_table[i] = (CYG_ADDRESS)hal_default_interrupt_vsr;
     }
 
-
 #if !defined(CYG_HAL_STARTUP_RAM)
 
     // Ensure that the CPU will use the vector table we have just set
     // up.
 
-# if defined(CYGHWR_HAL_CORTEXM_M3)
+# if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4)
 
-    // On M3 parts, the NVIC contains a vector table base register. We
-    // program this to relocate the vector table base to the base of
-    // SRAM.
-    
+    // On M3 and M4 parts, the NVIC contains a vector table base register.
+    // We program this to relocate the vector table base to the base of SRAM.
+
     HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_VTOR,
                       CYGARC_REG_NVIC_VTOR_TBLOFF(0)|
                       CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM );
-    
+
 # else
 
 #  error Unknown SRAM/VECTAB remap mechanism
@@ -183,14 +198,14 @@ void hal_reset_vsr( void )
     // We don't need to do this for RAM startup since the ROM code
     // will have already done it.
 
-    hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_switch_state_vsr;    
+    hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_switch_state_vsr;
 
-    __asm__ volatile( "swi" );
+    __asm__ volatile( "swi 0" );
 
     hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr;
-    
+
 #endif // !defined(CYG_HAL_STARTUP_RAM)
-    
+
 #if defined(CYG_HAL_STARTUP_ROM)
     // Relocate data from ROM to RAM
     {
@@ -224,13 +239,13 @@ void hal_reset_vsr( void )
     // PendSVC which are lowest priority.
     {
         register int i;
-        
+
         HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR0, 0x00000000 );
         HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR1, 0xFF000000 );
         HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, 0x00FF0000 );
-        
+
         hal_interrupt_handlers[CYGNUM_HAL_INTERRUPT_SYS_TICK] = (CYG_ADDRESS)hal_default_isr;
-        
+
         for( i = 1; i < CYGNUM_HAL_ISR_COUNT; i++ )
         {
             hal_interrupt_handlers[i] = (CYG_ADDRESS)hal_default_isr;
@@ -252,7 +267,7 @@ void hal_reset_vsr( void )
     }
 #endif
 
-#if !defined(CYG_HAL_STARTUP_RAM)    
+#if !defined(CYG_HAL_STARTUP_RAM)
     // Enable Usage, Bus and Mem fault handlers. Do this for ROM and
     // JTAG startups. For RAM startups, this will have already been
     // done by the ROM monitor.
@@ -267,25 +282,25 @@ void hal_reset_vsr( void )
         HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_SHCSR, shcsr );
     }
 #endif
-    
+
     // Call variant and platform init routines
     hal_variant_init();
     hal_platform_init();
 
     // Start up the system clock
     HAL_CLOCK_INITIALIZE( CYGNUM_HAL_RTC_PERIOD );
-            
+
 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
-    
+
     initialize_stub();
-    
+
 #endif
 
 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) || \
     defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
-    
+
     hal_ctrlc_isr_init();
-    
+
 #endif
 
     // Run through static constructors
@@ -316,11 +331,12 @@ void hal_deliver_exception( HAL_SavedReg
     // This is common in discovery code, e.g. checking for a particular
     // device which may generate an exception when probing if the
     // device is not present
+
 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
     if (__mem_fault_handler )
     {
         regs->u.exception.pc = (unsigned long)__mem_fault_handler;
-        return; // Caught an exception inside stubs        
+        return; // Caught an exception inside stubs
     }
 #endif
 
@@ -336,8 +352,8 @@ void hal_deliver_exception( HAL_SavedReg
 #else
 
     CYG_FAIL("Exception!!!");
-    
-#endif    
+
+#endif
 }
 
 //==========================================================================
@@ -357,14 +373,13 @@ void hal_deliver_interrupt( cyg_uint32 v
     register cyg_uint32 isr_result;
     register cyg_isr *isr;
     cyg_bool pendsvc = false;
-    
+
 #if defined(CYGPKG_KERNEL_INSTRUMENT) && \
     defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
     CYG_INSTRUMENT_INTR(RAISE, vector, 0);
 #endif
+    isr = (cyg_isr *)hal_interrupt_handlers[vector];
 
-    isr = (cyg_isr *)hal_interrupt_handlers[vector];
-    
     // Call the ISR
     isr_result = isr( vector, hal_interrupt_data[vector] );
 
@@ -414,10 +429,10 @@ void hal_deliver_interrupt( cyg_uint32 v
 
 __externC void hal_interrupt_end( void )
 {
-#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT    
+#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
     cyg_scheduler_sched_lock++;
 #endif
-    
+
    interrupt_end(0,0,0);
 }
 
@@ -522,7 +537,7 @@ void hal_deliver_interrupt( cyg_uint32 v
         if( t1 < t0 )
             us -= (t1 + CYGNUM_HAL_RTC_PERIOD - t0);
         else
-        	us -= t1 - t0;
+            us -= t1 - t0;
         t0 = t1;
     }
 }
@@ -547,7 +562,7 @@ cyg_hal_invoke_constructors (void)
 {
 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
     static pfunc *p = &CONSTRUCTORS_START;
-    
+
     cyg_hal_stop_constructors = 0;
     for (; p != CONSTRUCTORS_END; NEXT_CONSTRUCTOR(p)) {
         (*p)();
@@ -586,9 +601,8 @@ hal_arch_default_isr(CYG_ADDRWORD vector
 __externC void hal_get_gdb_registers( HAL_CORTEXM_GDB_Registers *gdbreg, HAL_SavedRegisters *regs )
 {
     int i;
-    cyg_uint32 *p = gdbreg->f0;
-    
-    switch( regs->u.type )
+
+    switch(GDB_STUB_SAVEDREG_FRAME_TYPE(regs))
     {
     case HAL_SAVEDREGISTERS_THREAD:
         for( i = 0; i < 13; i++ )
@@ -596,9 +610,11 @@ hal_arch_default_isr(CYG_ADDRWORD vector
         gdbreg->gpr[13] = regs->u.thread.sp;
         gdbreg->gpr[14] = regs->u.thread.pc;
         gdbreg->gpr[15] = regs->u.thread.pc;
-        gdbreg->ps = 0x01000000;
+        gdbreg->xpsr = 0x01000000;
+
+        GDB_STUB_SAVEDREG_FPU_THREAD_GET(gdbreg, regs);
         break;
-            
+
     case HAL_SAVEDREGISTERS_EXCEPTION:
         gdbreg->gpr[0] = regs->u.exception.r0;
         gdbreg->gpr[1] = regs->u.exception.r1;
@@ -610,9 +626,12 @@ hal_arch_default_isr(CYG_ADDRWORD vector
         gdbreg->gpr[13] = ((cyg_uint32)regs)+sizeof(regs->u.exception);
         gdbreg->gpr[14] = regs->u.exception.lr;
         gdbreg->gpr[15] = regs->u.exception.pc;
-        gdbreg->ps = regs->u.exception.psr;
+        gdbreg->xpsr = regs->u.exception.psr;
+#ifdef  CYGSEM_HAL_DEBUG_FPU
+        GDB_STUB_SAVEDREG_FPU_EXCEPTION_GET(gdbreg, regs);
+#endif
         break;
-                
+
     case HAL_SAVEDREGISTERS_INTERRUPT:
         gdbreg->gpr[0] = regs->u.interrupt.r0;
         gdbreg->gpr[1] = regs->u.interrupt.r1;
@@ -622,21 +641,24 @@ hal_arch_default_isr(CYG_ADDRWORD vector
         gdbreg->gpr[13] = ((cyg_uint32)regs)+sizeof(regs->u.interrupt);
         gdbreg->gpr[14] = regs->u.interrupt.lr;
         gdbreg->gpr[15] = regs->u.interrupt.pc;
-        gdbreg->ps = regs->u.interrupt.psr;
+        gdbreg->xpsr = regs->u.interrupt.psr;
         break;
     }
-
+#ifdef CYGARC_CORTEXM_GDB_REG_FPA
     // Clear FP state, which we don't use
-    for( i = 0; i < (8*3+1); i++ )
-        p[i] = 0;
-    
+    {
+        cyg_uint32 *p = gdbreg->f0;
+        for( i = 0; i < (8*3+1); i++ )
+            p[i] = 0;
+    }
+#endif
 }
 
 __externC void hal_set_gdb_registers( HAL_CORTEXM_GDB_Registers *gdbreg, HAL_SavedRegisters *regs )
 {
     int i;
-    
-    switch( regs->u.type )
+
+    switch(GDB_STUB_SAVEDREG_FRAME_TYPE(regs))
     {
     case HAL_SAVEDREGISTERS_THREAD:
         for( i = 0; i < 13; i++ )
@@ -644,8 +666,10 @@ hal_arch_default_isr(CYG_ADDRWORD vector
         regs->u.thread.sp = gdbreg->gpr[13];
         regs->u.thread.pc = gdbreg->gpr[14];
         regs->u.thread.pc = gdbreg->gpr[15];
+
+        GDB_STUB_SAVEDREG_FPU_THREAD_SET(gdbreg, regs);
         break;
-            
+
     case HAL_SAVEDREGISTERS_EXCEPTION:
         regs->u.exception.r0 = gdbreg->gpr[0];
         regs->u.exception.r1 = gdbreg->gpr[1];
@@ -656,9 +680,12 @@ hal_arch_default_isr(CYG_ADDRWORD vector
         regs->u.exception.r12 = gdbreg->gpr[12];
         regs->u.exception.lr = gdbreg->gpr[14];
         regs->u.exception.pc = gdbreg->gpr[15];
-        regs->u.exception.psr = gdbreg->ps;
+        regs->u.exception.psr = gdbreg->xpsr;
+#ifdef  CYGSEM_HAL_DEBUG_FPU
+        GDB_STUB_SAVEDREG_FPU_EXCEPTION_SET(gdbreg, regs);
+#endif
         break;
-                
+
     case HAL_SAVEDREGISTERS_INTERRUPT:
         regs->u.interrupt.r0 = gdbreg->gpr[0];
         regs->u.interrupt.r1 = gdbreg->gpr[1];
@@ -667,7 +694,7 @@ hal_arch_default_isr(CYG_ADDRWORD vector
         regs->u.interrupt.r12 = gdbreg->gpr[12];
         regs->u.interrupt.lr = gdbreg->gpr[14];
         regs->u.interrupt.pc = gdbreg->gpr[15];
-        regs->u.interrupt.psr = gdbreg->ps;
+        regs->u.interrupt.psr = gdbreg->xpsr;
         break;
     }
 }
diff --git a/packages/hal/cortexm/arch/current/src/mcount.S b/packages/hal/cortexm/arch/current/src/mcount.S
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/arch/current/src/mcount.S
@@ -0,0 +1,138 @@
+/*==========================================================================
+//
+//      mcount.S
+//
+//      Cortex-M mcount implementation
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2014 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):       jld
+// Contributor(s):  
+// Date:            2014-02-28
+// Description:     This file provides mcount functions used for
+//                  call-graph profiling.
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#include <pkgconf/hal_cortexm.h>
+
+/*
+// GCC inserts mcount code at the start of every function when compiling
+// with "-pg". For GCC prior to version 4.4 targeting Cortex-M,
+// the following code is inserted:
+// 
+//   mov r12, lr
+//   bl mcount
+//   .word <data pointer>
+//
+// For GCC version 4.4 and later targeting Cortex-M, the following code is
+// inserted:
+//
+//   push { lr }
+//   bl __gnu_mcount_nc
+//
+// We provide implementations of both mcount() and __gnu_mcount_nc() to
+// call the eCos __profile_mcount() function.
+*/
+
+        .syntax unified
+        .globl mcount
+        .section .text.mcount
+        .thumb_func
+mcount:
+        // resume execution beyond the data pointer on return to caller
+        add lr, lr, #4
+
+        // caller assumes r0-r3 will be preserved (non-AAPCS), we use
+        // r6 and must preserve lr across our __profile_mcount() call
+        push { r0, r1, r2, r3, r6, lr }
+
+        // set up parameters for __profile_mcount()
+        sub r0, r12, #2
+        bic r0, r0, #1
+        bic r1, lr, #1
+
+        // disable interrupts
+        mov r2, #CYGNUM_HAL_CORTEXM_PRIORITY_MAX
+        mrs r6, basepri
+        msr basepri, r2
+
+        // call eCos __profile_mcount()
+        // r6 is preserved across the call per AAPCS
+        bl __profile_mcount
+
+        // restore interrupts
+        msr basepri, r6
+
+        // restore registers and return
+        pop { r0, r1, r2, r3, r6, pc }
+
+
+        .globl __gnu_mcount_nc
+        .section .text.__gnu_mcount_nc
+        .thumb_func
+__gnu_mcount_nc:
+        // caller assumes r0-r3 will be preserved (non-AAPCS), we use
+        // r6 and must preserve lr across our __profile_mcount() call
+        push { r0, r1, r2, r3, r6, lr }
+
+        // set up parameters for __profile_mcount()
+        ldr r0, [ sp, #24 ]
+        sub r0, r0, #2
+        bic r0, r0, #1
+        bic r1, lr, #1
+
+        // disable interrupts
+        mov r2, #CYGNUM_HAL_CORTEXM_PRIORITY_MAX
+        mrs r6, basepri
+        msr basepri, r2
+
+        // call eCos __profile_mcount()
+        // r6 is preserved across the call per AAPCS
+        bl __profile_mcount
+
+        // restore interrupts
+        msr basepri, r6
+
+        // restore registers and return
+        pop { r0, r1, r2, r3, r6, r12, lr }
+        bx r12
+
+//==========================================================================
+// end of mcount.S
diff --git a/packages/hal/cortexm/arch/current/src/vectors.S b/packages/hal/cortexm/arch/current/src/vectors.S
--- a/packages/hal/cortexm/arch/current/src/vectors.S
+++ b/packages/hal/cortexm/arch/current/src/vectors.S
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2011, 2012 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -40,6 +40,7 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):    nickg
+// Contributors(s): ilijak
 // Date:         2008-07-30
 // Description:  This file defines the code placed into the exception
 //               vectors. It also contains the first level default VSRs
@@ -48,7 +49,8 @@
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 #include <pkgconf/hal.h>
 #include <pkgconf/hal_cortexm.h>
@@ -56,6 +58,11 @@
 #include <pkgconf/kernel.h>
 #endif
 
+#include <cyg/hal/cortexm_fpu.h>
+#ifdef CYGHWR_HAL_CORTEXM_FPU
+# include <cyg/hal/hal_arch.inc>
+#endif
+
 #include <cyg/hal/variant.inc>
 
 //==========================================================================
@@ -78,10 +85,10 @@ hal_vsr_table_init:
         .long           hal_reset_vsr                   //  1 Reset entry
 
 //==========================================================================
-        
+
         .text
         .thumb
-        
+
 //==========================================================================
 // Fake entry point.
 //
@@ -89,7 +96,7 @@ hal_vsr_table_init:
 // via RedBoot/Stubs or via JTAG the PC will be set to this address.
 // The code here sets up the SP and branches to the reset VSR in
 // emulation of the hardware reset behaviour.
-        
+
         .align  2
         .global reset_vector
         .thumb
@@ -102,7 +109,7 @@ reset_vector:
 
         .pool
 
-#if !defined(CYG_HAL_STARTUP_RAM)        
+#if !defined(CYG_HAL_STARTUP_RAM)
 //==========================================================================
 // State switch VSR
 //
@@ -115,8 +122,8 @@ reset_vector:
 // throw exceptions without corrupting the execution stack. This is
 // only necessary for non-kernel configurations (e.g. RedBoot, Stubs)
 // since kernel configurations will switch to a thread stack before
-// they should throw an exception.        
-        
+// they should throw an exception.
+
         .global hal_switch_state_vsr
         .thumb
         .thumb_func
@@ -125,22 +132,23 @@ hal_switch_state_vsr:
 
         mov     r0,#CYGNUM_HAL_CORTEXM_PRIORITY_MAX
         msr     basepri,r0
-        
+
         mov     r0,#2                   // Set CONTROL register to 2
         msr     control,r0
         isb                             // Insert a barrier
-        
-        msr     psp,sp                  // Copy SP to PSP
+
+        mov     r0,sp
+        msr     psp,r0                  // Copy SP to PSP
 
 #if !defined(CYGPKG_KERNEL)
         sub     sp,#(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE/2)
-#endif        
-        
+#endif
+
         orr     lr,#0xD                 // Adjust return link
         bx      lr                      // Return to init code on PSP now
 
 #endif
-        
+
 //==========================================================================
 // Default exception VSR
 //
@@ -152,7 +160,7 @@ hal_switch_state_vsr:
 // switch elsewhere. However, I know of no code that does anything
 // like this. If there is then this may need treating in the same way
 // as the interrupt end code.
-        
+
         .global hal_default_exception_vsr
         .thumb
         .thumb_func
@@ -160,25 +168,32 @@ hal_switch_state_vsr:
 hal_default_exception_vsr:
 
         mrs     r0,psp                  // Get process stack
+
+#ifdef  CYGSEM_HAL_DEBUG_FPU
+        hal_fpu_exc_push                // Save Floating Point Unit context
+#endif
         sub     r1,r0,#(4*12)           // Make space for saved state
         msr     psp,r1                  // Ensure PSP is up to date
-        
+
         mov     r1,#1                   // R1 = exception state type
         mrs     r2,ipsr                 // R2 = vector number
         mrs     r3,basepri              // R3 = basepri
-        stmfd   r0!,{r1-r11,lr}         // Push type, vector, basepri, r4-11 
-
+        stmfd   r0!,{r1-r11,lr}         // Push type, vector, basepri, r4-11
         mov     r4,r0                   // R4 = saved state pointer
 
         bl      hal_deliver_exception
 
         mov     r0,r4                   // R0 = state saved across call
         ldmfd   r0!,{r1-r11,lr}         // Pop type, vec, basepri, registers and LR
+
+#ifdef  CYGSEM_HAL_DEBUG_FPU
+        hal_fpu_exc_pop                 // Update Floating Point Unit context
+#endif
         msr     psp,r0                  // Restore PSP
         msr     basepri,r3              // Restore basepri
-        
+
         bx      lr                      // Return
-        
+
         .pool
 
 //==========================================================================
@@ -187,7 +202,7 @@ hal_default_exception_vsr:
 // This is a trampoline that translates from the hardware defined entry point
 // to the ISR defined by eCos. The CPU will switch automatically to the main
 // (interrupt) stack with the process state saved on the process stack. Apart
-// from saving a pointer to the interrupt state for Ctrl-C support, and fetching        
+// from saving a pointer to the interrupt state for Ctrl-C support, and fetching
 // the vector number, most of the work is actually done in hal_deliver_interrupt().
 
 
@@ -199,22 +214,20 @@ hal_default_interrupt_vsr:
 
         push    {lr}                    // Save return link
         sub     sp,#4                   // Realign SP to 8 bytes
-        
-#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) || \
-    defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
+
+#if CYGINT_HAL_COMMON_SAVED_INTERRUPT_STATE_REQUIRED > 0
         // If we are supporting Ctrl-C interrupts from GDB, we must squirrel
         // away a pointer to the saved interrupt state here so that we can
-        // plant a breakpoint at some later time. We only need to make a
-        // full interrupt saved state in that case.
+        // plant a breakpoint at some later time.
 
        .extern  hal_saved_interrupt_state
         mrs     r1,psp                  // Get PSP
-        mov     r0,#3                   // Interrupt state type        
+        mov     r0,#3                   // Interrupt state type
         stmfd   r1!,{r0}                // Push interrupt type
         ldr     r12,=hal_saved_interrupt_state
         str     r1,[r12]
 #endif
-        
+
         mrs     r0,ipsr                 // R0 = arg0 = vector number
         sub     r0,#15                  // Adjust to interrupt range
 
@@ -222,7 +235,7 @@ hal_default_interrupt_vsr:
 
         add     sp,#4                   // pop alignment padding
         pop     {pc}                    // Pop LR and return
-        
+
         .pool
 
 //==========================================================================
@@ -234,9 +247,9 @@ hal_default_interrupt_vsr:
 // a fake exception frame onto the PSP which will take us to hal_interrupt_end(),
 // which will make the call. The return link loaded by that frame takes us
 // back to hal_interrupt_end_done which will unwind the real exception
-// frame that is still on the PSP.        
+// frame that is still on the PSP.
 
-        
+
         .global hal_pendable_svc_vsr
         .thumb
         .thumb_func
@@ -244,20 +257,23 @@ hal_default_interrupt_vsr:
 hal_pendable_svc_vsr:
 
         mrs     r12,psp                 // R12 = thread's PSP
-        sub     r0,r12,#0x20            // Make space for frame
+        sub     r0,r12,#HAL_SAVEDREG_AUTO_FRAME_SIZE            // Make space for frame
         msr     psp,r0                  // Put it back
-        
+
+#ifdef CYGARC_CORTEXM_FPU_EXC_AUTOSAVE
+        hal_fpu_isr_fake_frame_push
+#endif // CYGARC_CORTEXM_FPU_EXC_AUTOSAVE
         ldr     r3,=0x01000000          // R3 = PSR = thumb bit set
         ldr     r2,=hal_interrupt_end   // R2 = PC = interrupt end entry point
         ldr     r1,=hal_interrupt_end_done // R1 = LR = restore code
         stmfd   r12!,{r0-r3}            // Save fake R12, LR, PC, PSR
         stmfd   r12!,{r0-r3}            // Save fake R0-R3
-        
+
         bx      lr                      // Return to hal_interrupt_end
 
         .pool
-        
-//==========================================================================                        
+
+//==========================================================================
 // Interrupt end done
 //
 // After calling interrupt end a thread returns here to unstack the
@@ -266,32 +282,32 @@ hal_pendable_svc_vsr:
 // from handler mode, so we use a SWI which will discard its own
 // frame and restore the saved one.
 
-        
+
         .global hal_interrupt_end_done
         .thumb
         .thumb_func
         .type   hal_interrupt_end_done, %function
 hal_interrupt_end_done:
 
-        ldr     r3,=hal_interrupt_end_vsr
-        swi
-        
-//==========================================================================        
+        ldr  r3,=hal_interrupt_end_vsr
+        swi  0
+
+//==========================================================================
 // Interrupt end VSR
 //
 // This is the SVC VSR invoked by hal_interrupt_end_done to restore the
 // original exception frame from a pendable SVC entry. It does this
 // by discarding its own frame and using the one below it on the
 // stack to return.
-        
+
         .global hal_interrupt_end_vsr
         .thumb
         .thumb_func
         .type   hal_interrupt_end_vsr, %function
-hal_interrupt_end_vsr: 
-        
+hal_interrupt_end_vsr:
+
         mrs     r12,psp                 // R12 = thread's PSP
-        add     r12,#32                 // Skip our saved state
+        add     r12,#HAL_SAVEDREG_AUTO_FRAME_SIZE                 // Skip our saved state
         msr     psp,r12                 // Restore thread's PSP
 
         bx      lr                      // And return
@@ -308,7 +324,7 @@ hal_interrupt_end_vsr:
         .thumb
         .thumb_func
         .type   hal_call_dsrs_vsr, %function
-        
+
 hal_call_dsrs_vsr:
 
         .extern cyg_interrupt_call_pending_DSRs
@@ -321,7 +337,7 @@ hal_call_dsrs_vsr:
 // in handler mode. R3 contains the address of a piece of code to run,
 // R0-R2 contain any arguments. Once entered the code is responsible for
 // handling the system state and returning to thread mode.
-//        
+//
 // Note that R0-R3 must be explicitly restored from their stacked
 // copies since a late arriving interrupt can preempt the SVC entry
 // and corrupt these registers before we get here.
@@ -337,6 +353,41 @@ hal_default_svc_vsr:
         bx      r3                      // Jump to routine in R3
 
         .pool
-        
-//==========================================================================        
+
+#ifdef CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+//==========================================================================
+// Usage Fault VSR
+// Note: This VSR is also attached to HardFault vector.
+// At present this VSR is used to detect FPU usage for Lazy context switch.
+// after saving processor context on the process stack call
+// hal_deliver_usagefault_fpu_exception() to do the job and retun result in r0.
+// If result indicates no FPU activity then jump in hal_default_exception_vsr.
+        .global hal_usagefault_exception_vsr
+        .thumb
+        .thumb_func
+        .type   hal_usagefault_exception_vsr, %function
+hal_usagefault_exception_vsr:
+
+        mrs     r0,psp                  // Get process stack
+        sub     r1,r0,#(2*4)            // Make space for saved state
+        msr     psp,r1                  // Ensure PSP is up to date
+        stmfd   r0!,{r4,lr}             // save registers
+        mov     r4,r0                   // R4 = saved state pointer
+
+        bl      hal_deliver_usagefault_fpu_exception
+
+        mov     r1,r4                   // R0 = state saved across call
+        ldmfd   r1!,{r4,lr}             // Restore registers
+        msr     psp,r1                  // Restore PSP
+
+        cmp     r0,#0                   // Exception other than FPU?
+        bne     hal_default_exception_vsr // Y: - process it
+
+        bx      lr                      // N: Return
+
+        .pool
+
+#endif // CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+
+//==========================================================================
 // end of vectors.S
diff --git a/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog b/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog
@@ -0,0 +1,49 @@
+2013-04-09  Tomas Frydrych <tomas@sleepfive.com>
+
+	* cdl/hal_cortexm_kinetis_kwikstik.cdl:
+	* include/plf_io.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/kwikstik_misc.c: Clock gating synchronised with variant.
+	[ Bugzilla 1001814 ]
+
+2012-11-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_kwikstik.cdl:
+	Sync with variant changes due to hardware floating point support.
+	Changed CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM.    [Bugzilla 1001607]
+
+2011-12-15  Tomas Frydrych  <tomas@sleepfive.com>
+
+	* cdl/hal_cortexm_kinetis_kwikstik.cdl:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* src/kwikstik_misc.c:
+	New package -- Freescale Kwikstik board, based on twr_k40x256 board.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011, 2012 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl b/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl
@@ -0,0 +1,297 @@
+##==========================================================================
+##
+##      hal_cortexm_kinetis_kwikstik.cdl
+##
+##      Cortex-M Freescale KwikStik platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 2011, 2012 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later
+## version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with eCos; if not, write to the Free Software Foundation, Inc.,
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+##
+## As a special exception, if other files instantiate templates or use
+## macros or inline functions from this file, or you compile this file
+## and link it with other works to produce a work based on this file,
+## this file does not by itself cause the resulting work to be covered by
+## the GNU General Public License. However the source code for this file
+## must still be made available in accordance with section (3) of the GNU
+## General Public License v2.
+##
+## This exception does not invalidate any other reasons why a work based
+## on this file might be covered by the GNU General Public License.
+## -------------------------------------------
+## ####ECOSGPLCOPYRIGHTEND####
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Tomas Frydrych <tomas@sleepfive.com>
+## Contributor(s): jld
+## Date:         2011-12-15
+## Original:     hal_cortexm_kinetis_twr_k40x256.cdl by Ilija Kocho
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_KINETIS_KWIKSTIK {
+    display       "Freescale Kinetis KwikStik Platform"
+    parent        CYGPKG_HAL_CORTEXM_KINETIS
+    define_header hal_cortexm_kinetis_kwikstik.h
+    include_dir   cyg/hal
+    hardware
+
+    requires      { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies
+        (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) }
+
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 40 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "D" }
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+    requires      { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" ||
+                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT == "X" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == 256 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X"
+                    implies CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 4096 }
+
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART5
+    implements    CYGINT_IO_FREESCALE_I2C1
+    implements    CYGINT_HAL_FREESCALE_UART5
+    implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
+
+
+    description   "
+        The Freescale KwikStik Platform HAL package provides
+        the support needed to run eCos on the KwikStik development
+        system. This package can also be used for other boards that
+        employ a controller from Kinetis families."
+
+    compile       kwikstik_misc.c
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_kwikstik.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Freescale KwikStik\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYG_HAL_STARTUP_ENV {
+        display "Startup type"
+        flavor data
+        no_define
+        calculated {
+            !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP :
+            ((CYG_HAL_STARTUP_PLF == "ByVariant") ?
+            (CYG_HAL_STARTUP . "(Variant)") :
+            (CYG_HAL_STARTUP . "(Platform)"))
+        }
+        description "
+            Startup type configuration defines the system memory layout.
+            Startup type  can be defined by the variant (CYG_HAL_STARTUP_VAR)
+            or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ {
+        display "Platform Reference Clock Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" ||
+                   CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        default_value 4000000
+        legal_values { 32768 4000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP {
+        display "Platform requred XTAL || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 0 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC {
+        display "Platform requred RTC XTAL || C \[pF\]"
+        flavor bool
+        default_value 0
+        parent CYGHWR_HAL_CORTEXM_KINETIS_RTC
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        legal_values 0 to 2
+        default_value   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR board has one serial port fitted to RS232 connector.
+            This optionchooses which port will be used to connect to a host
+            running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display          "Diagnostic serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR has one serial port fitted to RS232 connector.
+            This option chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console
+            port if the console and GDB port are the same."
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        no_define
+        parent  CYGPKG_NONE
+        description   "
+        Global build options including control over
+        compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+            This option controls the global compiler flags which are used to
+            compile all packages by default. Individual packages may define
+            options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+            This option controls the global linker flags. Individual
+            packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a
+            ROM monitor, i.e. applications will be loaded into RAM on the
+            board, and this ROM monitor may process exceptions or interrupts
+            generated from the application. This enables features such as
+            utilizing a separate interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+            Support can be enabled for different varieties of ROM monitor.
+            This support changes various eCos semantics such as the encoding
+            of diagnostic output, or the overriding of hardware interrupt
+            vectors.
+            Firstly there is \"Generic\" support which prevents the HAL
+            from overriding the hardware vectors that it does not use, to
+            instead allow an installed ROM monitor to handle them. This is
+            the most basic support which is likely to be common to most
+            implementations of ROM monitor.
+            \"GDB_stubs\" provides support when GDB stubs are included in
+            the ROM monitor or boot ROM."
+    }
+
+
+    cdl_component CYGBLD_HAL_CORTEXM_KWIKSTIK_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+
+        description "
+            This component causes the ELF image generated by the
+            build process to be converted to S-Record and binary
+            files."
+    }
+}
diff --git a/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_arch.h b/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_arch.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Tomas Frydrych <tomas@sleepfive.com>
+// Original:    Cloned from plf_arch.h for twr-k40x256 board by Ilija Kocho
+// Date:        2011-12-15
+// Purpose:     Kwikstick platform specific architecture overrides
+// Description:
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_kwikstik.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_intr.h b/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_intr.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_intr.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      Tomas Frydrych <tomas@sleepfive.com>
+// Original:       Cloned from plf_intr.h for twr-k40x256 board by Ilija Kocho
+// Date:           2011-12-15
+// Purpose:        Kwikstik platform specific interrupt overrides
+// Description:
+// Usage:          #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_kwikstik.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_io.h b/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_io.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_io.h
@@ -0,0 +1,110 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      Tomas Frydrych <tomas@sleepfive.com>
+// Original:       Based on plf_io.h for twr-k40x256 board by Ilija Kocho
+// Date:           2011-12-15
+// Purpose:        Kwikstik platform specific registers
+// Description:
+// Usage:          #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_kwikstik.h>
+
+
+// UART PINs
+
+#ifndef CYGHWR_HAL_FREESCALE_UART5_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 9, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 8, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RX CYGHWR_HAL_FREESCALE_UART5_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART5_PIN_TX CYGHWR_HAL_FREESCALE_UART5_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_FREESCALE_UART5_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_FREESCALE_UART5_PIN_CTS
+#endif
+
+// LCD
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SLCD_M            0x40000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SLCD_S            30
+
+#ifndef CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M             \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_M |     \
+             CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_M | \
+             CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_M |     \
+             CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_M |     \
+             CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_M |     \
+             CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_M |     \
+             CYGHWR_HAL_KINETIS_SIM_SCGC3_SLCD_M)
+#endif
+
+// I2C pins
+# define CYGHWR_HAL_I2C1_PIN_SDA CYGHWR_HAL_KINETIS_PIN(E, 0, 6, 0)
+# define CYGHWR_HAL_I2C1_PIN_SCL CYGHWR_HAL_KINETIS_PIN(E, 1, 6, 0)
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/packages/hal/cortexm/kinetis/kwikstik/current/src/kwikstik_misc.c b/packages/hal/cortexm/kinetis/kwikstik/current/src/kwikstik_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/kwikstik/current/src/kwikstik_misc.c
@@ -0,0 +1,255 @@
+//==========================================================================
+//
+//      kwikstik_misc.c
+//
+//      Cortex-M4 Kwikstik HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      Tomas Frydrych <tomas@sleepfive.com>
+// Original:       Cloned from twr_k40x256_misc.c by Ilija Kocho
+// Date:           2011-12-15
+// Description:    Miscellaneous code for platform hal.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#include <pkgconf/hal_cortexm_kinetis_kwikstik.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+static inline void hal_misc_init(void);
+
+// DATA and BSS locations
+__externC cyg_uint32 __ram_data_start;
+__externC cyg_uint32 __ram_data_end;
+__externC cyg_uint32 __rom_data_start;
+__externC cyg_uint32 __sram_data_start;
+__externC cyg_uint32 __sram_data_end;
+__externC cyg_uint32 __srom_data_start;
+__externC cyg_uint32 __bss_start;
+__externC cyg_uint32 __bss_end;
+
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_system_init( void )
+{
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
+    hal_wdog_disable();
+    hal_misc_init();
+    hal_start_clocks();
+#endif
+#if defined(CYG_HAL_STARTUP_SRAM) && !defined(CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED)
+    // Note: For CYG_HAL_STARTUP_SRAM, the SRAM_L bank simulates ROM
+    // Relocate data from ROM to RAM
+    {
+        register cyg_uint32 *ram_p, *rom_p;
+        for( ram_p = &__ram_data_start, rom_p = &__rom_data_start;
+             ram_p < &__ram_data_end;
+             ram_p++, rom_p++ )
+            *ram_p = *rom_p;
+    }
+
+    // Relocate data from ROM to SRAM
+    {
+        register cyg_uint32 *ram_p, *sram_p;
+        for( ram_p = &__sram_data_start, sram_p = &__srom_data_start;
+             ram_p < &__sram_data_end;
+             ram_p++, sram_p++ )
+            *ram_p = *sram_p;
+    }
+#endif
+}
+
+//===========================================================================
+// hal_misc_init
+//===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M)
+
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_misc_init(void)
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
+
+    // Enable some peripherals' clocks.
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
+
+    // Disable MPU
+    mpu_p->cesr = 0;
+}
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+    { CYGMEM_REGION_ram,        CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1      },      // Main RAM
+#ifdef CYGMEM_REGION_sram
+    { CYGMEM_REGION_sram,       CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1    },      // On-chip SRAM
+#endif
+#ifdef CYGMEM_REGION_flash
+    { CYGMEM_REGION_flash,      CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1  },      // On-chip flash
+#endif
+#ifdef CYGMEM_REGION_rom
+    { CYGMEM_REGION_rom,        CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1      },      // External flash
+#endif
+#ifdef CYGMEM_REGION_flexnvm
+    { CYGMEM_REGION_flexnvm,    CYGMEM_REGION_flexnvm+CYGMEM_REGION_flexnvm_SIZE-1  },  // On-chip flexnvm (DFlash)
+#endif
+#ifdef CYGMEM_REGION_flexram
+    { CYGMEM_REGION_flexram,    CYGMEM_REGION_flexram+CYGMEM_REGION_flexram_SIZE-1  },  // On-chip flexram
+#endif
+#ifdef CYGMEM_REGION_eeeprom0
+    { CYGMEM_REGION_eeeprom0,    CYGMEM_REGION_eeeprom0+CYGMEM_REGION_eeeprom0_SIZE-1  },  // On-chip Enhanced EEPROM
+#endif
+#ifdef CYGMEM_REGION_eeeprom1
+    { CYGMEM_REGION_eeeprom1,    CYGMEM_REGION_eeeprom0+CYGMEM_REGION_eeeprom1_SIZE-1  },  // On-chip Enhanced EEPROM
+#endif
+    { 0xE0000000,               0x00000000-1                                    },      // Cortex-M peripherals
+    { 0x40000000,               0x60000000-1                                    },      // Chip specific peripherals
+};
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) {
+        if( (addr >= hal_data_access[i].start) &&
+            (addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the on-chip SRAM and external SRAM.
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_sram
+#define CASE_CYGMEM_REGION_SRAM 1
+    case CASE_CYGMEM_REGION_SRAM:
+        *start = (unsigned char *)CYGMEM_REGION_sram;
+        *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
+        break;
+#else
+#define CASE_CYGMEM_REGION_SRAM 0
+#endif
+#ifdef CYGMEM_REGION_flexram
+#define CASE_CYGMEM_REGION_FLEXRAM (CASE_CYGMEM_REGION_SRAM + 1)
+    case CASE_CYGMEM_REGION_FLEXRAM:
+        *start = (unsigned char *)CYGMEM_REGION_flexram;
+        *end = (unsigned char *)(CYGMEM_REGION_flexram +
+                                 CYGMEM_REGION_flexram_SIZE);
+        break;
+#else
+#define CASE_CYGMEM_REGION_FLEXRAM (CASE_CYGMEM_REGION_SRAM)
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+} // cyg_plf_memory_segment()
+
+#endif // CYGPKG_REDBOOT
+
+
+//==========================================================================
+// EOF kwikstik_misc.c
diff --git a/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog b/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog
@@ -0,0 +1,72 @@
+2013-04-09  Tomas Frydrych <tomas@sleepfive.com>
+
+	* cdl/hal_cortexm_kinetis_twr_k40x256.cdl:
+	* include/plf_io.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k40x256_misc.c: Clock gating synchronised with variant.
+	[ Bugzilla 1001814 ]
+
+2012-11-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k40x256.cdl:
+	Sync with variant changes due to hardware floating point support.
+	Changed CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM.    [Bugzilla 1001607]
+
+2012-10-25  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k40x256_misc.c: Initialization for separate SRAM regions
+	synchronized with variant.                  [Bugzilla 1001606]
+
+2012-05-19  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal_cortexm_kinetis_twr_k40x256.cdl: Reference per-package
+	documentation.
+
+2012-05-18  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* doc/twr_k40x512.sgml:
+	New file -- TWR-K40X512 platform documentation. [Bug 1001580]
+
+2012-01-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k40x256.cdl:
+	* include/plf_io.h:
+	* src/twr_k40x256_misc.c:
+	Add entry for DMA, Add CYG_HAL_STARTUP_ENV. Add DSPI pins for SPI1 bus.
+	Updated for early clock start. [Bugzilla 1001450]
+
+2011-08-26  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k40x256.cdl:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* src/twr_k40x256_misc.c:
+	New package -- Freescale TWR-K40X256 board.
+	
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2012 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl b/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl
@@ -0,0 +1,316 @@
+##==========================================================================
+##
+##      hal_cortexm_kinetis_twr_k40x256.cdl
+##
+##      Cortex-M Freescale TWR-K40X256 platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011, 2012 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-07-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K40X256 {
+    display       "Freescale Kinetis TWR-K40X256 Platform"
+    parent        CYGPKG_HAL_CORTEXM_KINETIS
+    define_header hal_cortexm_kinetis_twr_k40x256.h
+    include_dir   cyg/hal
+    doc           ref/kinetis-twr-k40x256.html
+    hardware
+
+    requires      { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies
+        (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) }
+
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 40 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "D" }
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+    requires      { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" ||
+                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT == "X" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == 256 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X"
+                    implies CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 4096 }
+
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART3
+    implements    CYGINT_IO_FREESCALE_I2C0
+    implements    CYGINT_IO_FREESCALE_I2C1
+    
+    implements    CYGINT_HAL_FREESCALE_UART3
+    implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
+
+
+    description   "
+        The Freescale TWR K40X256 Platform HAL package provides
+        the support needed to run eCos on the TWR K40X256 development
+        system. This package can also be used for other boards that
+        employ a controller from Kinetis families."
+
+    compile       twr_k40x256_misc.c
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k40x256.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Freescale TWR-K40X256\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYG_HAL_STARTUP_ENV {
+        display "Startup type"
+        flavor data
+        no_define
+        calculated {
+            !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP :
+            ((CYG_HAL_STARTUP_PLF == "ByVariant") ?
+            (CYG_HAL_STARTUP . "(Variant)") :
+            (CYG_HAL_STARTUP . "(Platform)"))
+        }
+        description "
+            Startup type configuration defines the system memory layout.
+            Startup type  can be defined by the variant (CYG_HAL_STARTUP_VAR)
+            or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ {
+        display "Platform Reference Clock Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" ||
+                   CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        default_value 8000000
+        legal_values { 32768 8000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP {
+        display "Platform requred XTAL || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 0 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC {
+        display "Platform requred RTC XTAL || C \[pF\]"
+        flavor bool
+        default_value 0
+        parent CYGHWR_HAL_CORTEXM_KINETIS_RTC
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        legal_values 0 to 2
+        default_value   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR board has one serial port fitted to RS232 connector.
+            This optionchooses which port will be used to connect to a host
+            running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display          "Diagnostic serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR has one serial port fitted to RS232 connector.
+            This option chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console
+            port if the console and GDB port are the same."
+    }
+
+    cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS {
+        display "MMC Disk SPI bus"
+        flavor data
+        parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+        calculated 1
+
+        requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1
+        implements CYGINT_DEVS_SPI_FREESCALE_DSPI1
+        implements CYGINT_FREESCALE_DSPI1_HAS_MASS
+
+        cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS {
+            display "Device number (CS)"
+            flavor data
+            calculated 0
+            implements CYGINT_FREESCALE_DSPI1_CS0
+        }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        no_define
+        parent  CYGPKG_NONE
+        description   "
+        Global build options including control over
+        compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+            This option controls the global compiler flags which are used to
+            compile all packages by default. Individual packages may define
+            options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+            This option controls the global linker flags. Individual
+            packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a
+            ROM monitor, i.e. applications will be loaded into RAM on the
+            board, and this ROM monitor may process exceptions or interrupts
+            generated from the application. This enables features such as
+            utilizing a separate interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+            Support can be enabled for different varieties of ROM monitor.
+            This support changes various eCos semantics such as the encoding
+            of diagnostic output, or the overriding of hardware interrupt
+            vectors.
+            Firstly there is \"Generic\" support which prevents the HAL
+            from overriding the hardware vectors that it does not use, to
+            instead allow an installed ROM monitor to handle them. This is
+            the most basic support which is likely to be common to most
+            implementations of ROM monitor.
+            \"GDB_stubs\" provides support when GDB stubs are included in
+            the ROM monitor or boot ROM."
+    }
+
+
+    cdl_component CYGBLD_HAL_CORTEXM_TWR_MK40X256_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+
+        description "
+            This component causes the ELF image generated by the
+            build process to be converted to S-Record and binary
+            files."
+    }
+}
diff --git a/packages/hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml b/packages/hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml
@@ -0,0 +1,75 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     twr_k40x256.sgml                                             -->
+<!--                                                                 -->
+<!--     TWR-K40X256 board documentation.                             -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2012 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2012/01/10                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<!--<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>-->
+
+<refentry id="kinetis-twr-k40x256">
+  <refmeta>
+    <refentrytitle>TWR-K40X256-KIT Development kit</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>CYGPKG_HAL_CORTEXM_KINETIS_TWR_K40X256</refname>
+    <refpurpose>eCos Support for the Freescale TWR-K40X256 development kit</refpurpose>
+  </refnamediv>
+
+  <refsect1 id="kinetis-twr-k40x256-description"><title>Description</title>
+    <para>
+    The Freescale TWR-K40X256-KIT is a development kit for <link linkend="hal-cortexm-kinetis-var">
+    Freescale Kinetis</link>  Cortex-M4 based micro-controllers. It covers K40 and K30 microcontroller
+    subfamilies. K40X256 is a high end member comprising 256 KiB FLASH, 256 KiB FlexMemory and  64 KiB SRAM,
+    as well as rich set of communication interfaces including USB, UARTs CAN, SPI and I2C.
+    K40 controllers also feature a Segment LCD controller, a DMA controller and a FlexBus
+    external memory interface. They are mixed signal devices featuring 16 bit ADC and 12 bit DAC. 
+    </para>
+  </refsect1>
+  <refsect1 id="kinetis-twr-k40x256-config"><title>Configuration</title>
+    <refsect2 id="kinetis-twr-k40x256-config-hardware"><title>Hardware Setup</title>
+      <para>
+      No changes to the factory default setup are necessary.
+    </para>
+  <refsect3 id="twr-k40x256-clocking"><title>Clocking</title>
+    <para>
+    The TWR-K40X256 uses an 8MHz crystal as a clock reference which is stated as a requirement in the platform package.
+    </para>
+  </refsect3>  
+  <refsect3 id="twr-k40x256-memory"><title>Memory</title>
+    <para> K40X245 has two 32KiB SRAM banks giving a total of 64KiB on chip SRAM. </para>
+  </refsect3>
+ </refsect2>
+  </refsect1>
+</refentry>
+
+<!-- </part> -->
diff --git a/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_arch.h b/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_arch.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Contributor(s):
+// Date:        2011-02-05
+// Purpose:     TWR-K40X256 platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_intr.h b/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_intr.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-02-05
+// Purpose:     TWR-K40X256 platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h b/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h
@@ -0,0 +1,113 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-02-05
+// Purpose:     TWR-K40X256 platform specific registers
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h>
+
+
+// UART PINs
+
+#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(C, 16, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(C, 17, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_FREESCALE_UART3_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_FREESCALE_UART3_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_FREESCALE_UART3_PIN_CTS
+#endif
+
+
+// DSPI
+// DSPI Pins
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN  CYGHWR_HAL_KINETIS_PIN(E, 3, 2, KINETIS_PIN_SPI1_IN_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 1, 2, KINETIS_PIN_SPI1_OUT_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK  CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_OUT_OPT)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0  CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1  CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2  CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3  CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4  CYGHWR_HAL_KINETIS_PIN_NONE
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5  CYGHWR_HAL_KINETIS_PIN_NONE
+
+// I2C
+// I2C Pins
+
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(B, 2, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(B, 3, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SDA CYGHWR_HAL_KINETIS_PIN(C, 11, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SCL CYGHWR_HAL_KINETIS_PIN(C, 10, 2, 0)
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/packages/hal/cortexm/kinetis/twr_k40x256/current/src/twr_k40x256_misc.c b/packages/hal/cortexm/kinetis/twr_k40x256/current/src/twr_k40x256_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k40x256/current/src/twr_k40x256_misc.c
@@ -0,0 +1,233 @@
+//==========================================================================
+//
+//      twr_k40x256_misc.c
+//
+//      Cortex-M4 TWR-K40X256 EVAL HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2011-02-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+static inline void hal_misc_init(void);
+
+// DATA and BSS locations
+__externC cyg_uint32 __ram_data_start;
+__externC cyg_uint32 __ram_data_end;
+__externC cyg_uint32 __rom_data_start;
+__externC cyg_uint32 __sram_data_start;
+__externC cyg_uint32 __sram_data_end;
+__externC cyg_uint32 __srom_data_start;
+__externC cyg_uint32 __bss_start;
+__externC cyg_uint32 __bss_end;
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_system_init( void )
+{
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
+    hal_wdog_disable();
+    hal_misc_init();
+    hal_start_clocks();
+#endif
+}
+
+//===========================================================================
+// hal_misc_init
+//===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M)
+
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_misc_init(void)
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
+
+    // Enable some peripherals' clocks.
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
+
+    // Disable MPU
+    mpu_p->cesr = 0;
+}
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+    { CYGMEM_REGION_ram,        CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1      },      // Main RAM
+#ifdef CYGMEM_REGION_sram
+    { CYGMEM_REGION_sram,       CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1    },      // On-chip SRAM
+#endif
+#ifdef CYGMEM_REGION_flash
+    { CYGMEM_REGION_flash,      CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1  },      // On-chip flash
+#endif
+#ifdef CYGMEM_REGION_rom
+    { CYGMEM_REGION_rom,        CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1      },      // External flash
+#endif
+#ifdef CYGMEM_REGION_flexnvm
+    { CYGMEM_REGION_flexnvm,    CYGMEM_REGION_flexnvm+CYGMEM_REGION_flexnvm_SIZE-1  },  // On-chip flexnvm (DFlash)
+#endif
+#ifdef CYGMEM_REGION_flexram
+    { CYGMEM_REGION_flexram,    CYGMEM_REGION_flexram+CYGMEM_REGION_flexram_SIZE-1  },  // On-chip flexram
+#endif
+#ifdef CYGMEM_REGION_eeeprom0
+    { CYGMEM_REGION_eeeprom0,    CYGMEM_REGION_eeeprom0+CYGMEM_REGION_eeeprom0_SIZE-1  },  // On-chip Enhanced EEPROM
+#endif
+#ifdef CYGMEM_REGION_eeeprom1
+    { CYGMEM_REGION_eeeprom1,    CYGMEM_REGION_eeeprom0+CYGMEM_REGION_eeeprom1_SIZE-1  },  // On-chip Enhanced EEPROM
+#endif
+    { 0xE0000000,               0x00000000-1                                    },      // Cortex-M peripherals
+    { 0x40000000,               0x60000000-1                                    },      // Chip specific peripherals
+};
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) {
+        if( (addr >= hal_data_access[i].start) &&
+            (addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the on-chip SRAM and external SRAM.
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_sram
+#define CASE_CYGMEM_REGION_SRAM 1
+    case CASE_CYGMEM_REGION_SRAM:
+        *start = (unsigned char *)CYGMEM_REGION_sram;
+        *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
+        break;
+#else
+#define CASE_CYGMEM_REGION_SRAM 0
+#endif
+#ifdef CYGMEM_REGION_flexram
+#define CASE_CYGMEM_REGION_FLEXRAM (CASE_CYGMEM_REGION_SRAM + 1)
+    case CASE_CYGMEM_REGION_FLEXRAM:
+        *start = (unsigned char *)CYGMEM_REGION_flexram;
+        *end = (unsigned char *)(CYGMEM_REGION_flexram +
+                                 CYGMEM_REGION_flexram_SIZE);
+        break;
+#else
+#define CASE_CYGMEM_REGION_FLEXRAM (CASE_CYGMEM_REGION_SRAM)
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+} // cyg_plf_memory_segment()
+
+#endif // CYGPKG_REDBOOT
+
+//==========================================================================
+// EOF twr_k40x256_misc.c
diff --git a/packages/hal/cortexm/kinetis/twr_k60f120m/current/ChangeLog b/packages/hal/cortexm/kinetis/twr_k60f120m/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60f120m/current/ChangeLog
@@ -0,0 +1,39 @@
+2013-07-02  John Dallaway  <john@dallaway.org.uk>
+
+	* doc/twr_k60f120m.sgml: Fix missing </para>.
+
+2013-06-02  Mike Jones <mjones@proclivis.com.>
+
+	* cdl/hal_cortexm_kinetis_twr_k60f120m.cdl: New
+	* doc/twr_k60f120m.sgml: New
+	* include/plf_intr.h: New
+	* include/plf_io.h: New
+	* include/plf_arch.h: New
+	* misc/redboot_K60_ROM_FPU.ecm: New
+	* src/twr_k60f120m_misc.c: New
+
+	Add support for K60F120M [ Bugzilla 1001861 ]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/hal/cortexm/kinetis/twr_k60f120m/current/cdl/hal_cortexm_kinetis_twr_k60f120m.cdl b/packages/hal/cortexm/kinetis/twr_k60f120m/current/cdl/hal_cortexm_kinetis_twr_k60f120m.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60f120m/current/cdl/hal_cortexm_kinetis_twr_k60f120m.cdl
@@ -0,0 +1,399 @@
+##==========================================================================
+##
+##      hal_cortexm_kinetis_twr_k60f120m.cdl
+##
+##      Cortex-M Freescale TWR-K60F120M platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2013 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Contrib(s):   Mike Jones <mjones@proclivis.com>
+## Date:         2013-06-02
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60F120M {
+    display       "Freescale Kinetis TWR-K60F120M Platform"
+    parent        CYGPKG_HAL_CORTEXM_KINETIS
+    define_header hal_cortexm_kinetis_twr_k60f120m.h
+    include_dir   cyg/hal
+    doc           ref/kinetis-twr-k60f120m.html
+    hardware
+    description   "
+        The Freescale TWR K60F120M Platform HAL package provides the support
+        needed to run eCos on the TWR K60F120M development system. This package
+        can also be used for other boards that employ a controller from Kinetis
+        families."
+
+    compile       twr_k60f120m_misc.c
+
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+    requires      { is_active(CYGPKG_DEVS_ETH_FREESCALE_ENET)
+                  implies CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" }
+
+    implements    CYGINT_HAL_CACHE
+
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FPU_DEFAULT == "F" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM_DEFAULT == 60 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 30 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 40 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 50 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 70 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == "1M0" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 }
+    requires      { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies
+                    CYGNUM_DEVS_KINETIS_FLASH_BLOCK_SIZE == 0x1000 }
+    requires      { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies
+                    CYGNUM_DEVS_KINETIS_FLASH_LONGWORD_SIZE == 8 }
+
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART5
+    implements    CYGINT_IO_FREESCALE_I2C0
+
+    implements    CYGINT_HAL_FREESCALE_UART5
+    implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
+
+    implements    CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+    implements    CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1
+    implements    CYGINT_HAL_CORTEXM_KINETIS_150
+
+    requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX == 75000000 }
+    requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX == 75000000 }
+    requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX == 25000000 }
+
+    requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
+        (1 == CYGHWR_DEVS_ETH_PHY_KSZ8041) }
+    requires      { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies
+        (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 32) }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k60f120m.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Freescale TWR-K60F120M\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+        puts $::cdl_system_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 4000000"
+    }
+
+    cdl_component CYG_HAL_STARTUP_ENV {
+        display "Startup type"
+        flavor data
+        no_define
+        calculated {
+            !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP :
+            ((CYG_HAL_STARTUP_PLF == "ByVariant") ?
+            (CYG_HAL_STARTUP . "(Variant)") :
+            (CYG_HAL_STARTUP . "(Platform)"))
+        }
+        description "
+            Startup type configuration defines the system memory layout.
+            Startup type  can be defined by the variant (CYG_HAL_STARTUP_VAR)
+            or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP {
+        display "Platform suggested system frequency setpoint"
+        flavor data
+        no_define
+        legal_values 96000000 100000000 120000000 150000000 200000000
+        default_value 120000000
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP {
+        display "Platform suggested auxiliary frequency setpoint"
+        flavor data
+        no_define
+        legal_values 96000000 100000000 120000000 150000000 200000000
+        default_value 120000000
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ {
+        display "Platgorm XTAL/OSC Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" ||
+                   CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        default_value 50000000
+        legal_values { 12000000 50000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ {
+        display "Platform XTAL1/OSC1 Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "OSC" ||
+                   CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" }
+        default_value 50000000
+        legal_values { 12000000 50000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP {
+        display "Platform requred XTAL || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC1_CAP {
+        display "Platform requred XTAL1 || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP == 20 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC {
+        display "Platform requred RTC XTAL || C \[pF\]"
+        flavor bool
+        default_value 0
+        parent CYGHWR_HAL_CORTEXM_KINETIS_RTC
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        legal_values 0 to 2
+        default_value   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR board has one serial port fitted to RS232 connector.
+            This option chooses which port will be used to connect to a host
+            running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display          "Diagnostic serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR has one serial port fitted to RS232 connector.
+            This option chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console port
+            if the console and GDB port are the same."
+    }
+
+    cdl_option CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK {
+        display "ENET MII MDC clock provided by HAL"
+        flavor data
+        active_if CYGPKG_DEVS_ETH_FREESCALE_ENET
+        parent CYGPKG_DEVS_ETH_FREESCALE_ENET
+        calculated CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS
+        description "
+            ENET needs a clock with typical frequency of up to 2.5 MHz for
+            MII MDC. The input clock, typically provided by HAL, is further
+            divided by ENET according to setting of ENET MSCR register in order to
+            provide frequency within 2.5 MHz range."
+     }
+
+    cdl_option CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT {
+        display "IEEE 1588 Port"
+        active_if CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        parent CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        flavor data
+        default_value { "B" }
+        legal_values { "B" "C" "User" }
+        description "
+            Digital I/O provided by HAL for ENET IEEE 1588 timers."
+    }
+
+    cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS {
+        display "MMC Disk SPI bus"
+        flavor data
+        parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+        calculated 1
+
+        requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1
+        implements CYGINT_DEVS_SPI_FREESCALE_DSPI1
+        implements CYGINT_FREESCALE_DSPI1_HAS_MASS
+        requires  { (is_active(CYGSEM_HAL_DCACHE_STARTUP_MODE)
+                    && CYGINT_DEVS_SPI_DSPI_DMA_USE)
+                    implies CYGSEM_HAL_DCACHE_STARTUP_MODE == "WRITETHRU" }
+
+        cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS {
+            display "Device number (CS)"
+            flavor data
+            legal_values { 0 1 2 3 4 5 }
+            default_value 0
+            implements CYGINT_FREESCALE_DSPI1_CS0
+            implements CYGINT_FREESCALE_DSPI1_CS1
+            implements CYGINT_FREESCALE_DSPI1_CS2
+            implements CYGINT_FREESCALE_DSPI1_CS3
+        }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+            Global build options including control over
+            compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+            Support can be enabled for different varieties of ROM monitor.
+            This support changes various eCos semantics such as the encoding
+            of diagnostic output, or the overriding of hardware interrupt
+            vectors.
+            Firstly there is \"Generic\" support which prevents the HAL
+            from overriding the hardware vectors that it does not use, to
+            instead allow an installed ROM monitor to handle them. This is
+            the most basic support which is likely to be common to most
+            implementations of ROM monitor.
+            \"GDB_stubs\" provides support when GDB stubs are included in
+            the ROM monitor or boot ROM."
+    }
+
+
+    cdl_component CYGBLD_HAL_CORTEXM_TWR_MK60F120M_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+
+        description "
+            This component causes the ELF image generated by the
+            build process to be converted to S-Record and binary
+            files."
+    }
+}
diff --git a/packages/hal/cortexm/kinetis/twr_k60f120m/current/doc/twr_k60f120m.sgml b/packages/hal/cortexm/kinetis/twr_k60f120m/current/doc/twr_k60f120m.sgml
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60f120m/current/doc/twr_k60f120m.sgml
@@ -0,0 +1,113 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     twr_k60f120m.sgml                                        -->
+<!--                                                                 -->
+<!--     TWR-K60F120M board documentation.                        -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2012 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contrib(s):  Mike Jones                                         -->
+<!-- Contact(s):  mjones@proclivis.com                               -->
+<!-- Date:        2013/06/02                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<!--<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>-->
+
+<refentry id="kinetis-twr-k60f120m">
+  <refmeta>
+    <refentrytitle>TWR-K60F120M Development kit</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60F120M</refname>
+    <refpurpose>eCos Support for Freescale TWR-K60F120M development kit</refpurpose>
+  </refnamediv>
+  
+  <refsect1 id="kinetis-twr-k60f120m-description"><title>Description</title>
+    <para>
+    The Freescale TWR-K60F120M is a development kit for <link linkend="hal-cortexm-kinetis-var">
+    Freescale Kinetis</link> Cortex-M4 based micro-controllers. It covers the K60
+    microcontroller subfamily. K60FN1M0 is a high end member comprising on-chip 1 MiB FLASH
+    and 128 KiB SRAM memory as well as a 16 KiB unified cache.
+    K60 parts are equipped with a rich set of communication interfaces including Ethernet USB, UARTs
+    CAN, SPI and I2C. They also have a Graphics controller and a DMA controller, as well as FlexBus and SDRAM
+    external memory interfaces. They are mixed signal devices featuring a 16 bit ADC and a 12 bit DAC. 
+    </para>
+  </refsect1>
+  <refsect1 id="kinetis-twr-k60f120m-config"><title>Configuration</title>
+    <refsect2 id="kinetis-twr-k60f120m-config-hardware"><title>Hardware Setup</title>
+      <refsect3 id="kinetis-twr-k60f120m-config-hardware-cpu"><title>TWR-K60F120M setup</title>
+      <para>
+      Factory jumper settings on TWR-K60F120M are fitted for standalone operation of the board.
+      In order to use it with the Ethernet PHY from TWR-SER, some jumpers have to be changed
+      on both TWR-K60F120M and TWR-SER. Jumper settings for TWR-SER are given in
+      <link linkend="kinetis-twr-k60n512-config">TWR-K60N512 Configuration</link> and here are the TWR-K60F120M
+      settings.
+      </para>
+      <table frame="all"><title>TWR-K60F120M Jumper setting</title>
+        <tgroup cols="3" align="center">
+          <colspec colnum="1" colname="jumper" colwidth="1*" >
+          <colspec colnum="2" colname="jumpset" colwidth="1*" >
+          <colspec colnum="3" colname="desc" colwidth="3*" >
+          <thead>
+            <row>
+              <entry>Jumper</entry>
+              <entry>Setting</entry>
+              <entry>Description</entry>
+            </row>
+          </thead>
+          <tbody>
+            <row>
+              <entry>J18</entry>
+              <entry>ON</entry>
+              <entry>On board 50MHz oscillator is disabled</entry>
+            </row>
+            <row>
+              <entry>J19</entry>
+              <entry>ON</entry>
+              <entry>On board 50MHz oscillator is powered</entry>
+            </row>
+          </tbody>
+        </tgroup>
+      </table>
+      </refsect3>
+    </refsect2>
+    <refsect2 id="kinetis-twr-k60f120m-config-ecos"><title>eCos Configuration</title>
+      <refsect3 id="twr-k60f120m-clocking"><title>Clocking</title>
+      <para>
+      The TWR-K60F120M package defines requirements for the platform clocking.
+      </para>
+      </refsect3>  
+      <refsect3 id="twr-k60f120m-memory"><title>Memory</title>
+      <para>
+      The K60 has two 64 KiB SRAM banks giving a total of 128KiB on chip SRAM.
+      </para>
+      </refsect3>
+    </refsect2>
+  </refsect1>
+</refentry>
+
+<!--</part>-->
diff --git a/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_arch.h b/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_arch.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Ilija Kocho <ilijak@siva.com.mk>
+// Contrib(s):  Mike Jones <mjones@proclivis.com>
+// Date:        2013-06-02
+// Purpose:     TWR-K60F120M platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60f120m.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_intr.h b/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_intr.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Ilija Kocho <ilijak@siva.com.mk>
+// Contrib(s):  Mike Jones <mjones@proclivis.com>
+// Purpose:     TWR-K60F120M platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60f120m.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_io.h b/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_io.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_io.h
@@ -0,0 +1,175 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Ilija Kocho <ilijak@siva.com.mk>
+// Contrib(s):  Mike Jones <mjones@proclivis.com>
+// Date:        2013-06-02
+// Purpose:     TWR-K60F120M platform specific registers
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60f120m.h>
+
+
+// UART PINs
+#ifndef CYGHWR_HAL_FREESCALE_UART5_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 9, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 8, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RX CYGHWR_HAL_FREESCALE_UART5_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART5_PIN_TX CYGHWR_HAL_FREESCALE_UART5_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_FREESCALE_UART5_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_FREESCALE_UART5_PIN_CTS
+#endif
+
+#ifndef CYGHWR_HAL_FREESCALE_UART0_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART0_PIN_RX CYGHWR_HAL_KINETIS_PIN(A, 1, 2, 0)
+# define CYGHWR_HAL_FREESCALE_UART0_PIN_TX CYGHWR_HAL_KINETIS_PIN(A, 2, 2, 0)
+# define CYGHWR_HAL_FREESCALE_UART0_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART0_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# define CYGHWR_IO_FREESCALE_UART0_PIN_RX CYGHWR_HAL_FREESCALE_UART0_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART0_PIN_TX CYGHWR_HAL_FREESCALE_UART0_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART0_PIN_RTS CYGHWR_HAL_FREESCALE_UART0_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART0_PIN_CTS CYGHWR_HAL_FREESCALE_UART0_PIN_CTS
+#endif
+
+// ENET PINs
+
+// MDIO
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDIO    CYGHWR_HAL_KINETIS_PIN(B, 0, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDC     CYGHWR_HAL_KINETIS_PIN(B, 1, 4, 0)
+// Both RMII and MII interface
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXER    CYGHWR_HAL_KINETIS_PIN(A, 5, 4, \
+                                                    CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD1    CYGHWR_HAL_KINETIS_PIN(A, 12, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD0    CYGHWR_HAL_KINETIS_PIN(A, 13, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXEN    CYGHWR_HAL_KINETIS_PIN(A, 15, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD0    CYGHWR_HAL_KINETIS_PIN(A, 16, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD1    CYGHWR_HAL_KINETIS_PIN(A, 17, 4, 0)
+// RMII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_CRS_DV  CYGHWR_HAL_KINETIS_PIN(A, 14, 4, 0)
+// MII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD3     CYGHWR_HAL_KINETIS_PIN(A, 9, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD2     CYGHWR_HAL_KINETIS_PIN(A, 10, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXCLK    CYGHWR_HAL_KINETIS_PIN(A, 11, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD2     CYGHWR_HAL_KINETIS_PIN(A, 24, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXCLK    CYGHWR_HAL_KINETIS_PIN(A, 25, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD3     CYGHWR_HAL_KINETIS_PIN(A, 26, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_CRS      CYGHWR_HAL_KINETIS_PIN(A, 27, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MIIO_TXER     CYGHWR_HAL_KINETIS_PIN(A, 28, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_COL      CYGHWR_HAL_KINETIS_PIN(A, 29, 4, 0)
+// IEEE 1588 timers
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_1588_CLKIN    CYGHWR_HAL_KINETIS_PIN(E, 26, 4, 0)
+
+#if defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_B)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(B, 2, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(B, 3, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(B, 4, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(B, 5, 4, 0)
+#elif defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_C)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(C, 16, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(C, 17, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(C, 18, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(C, 19, 4, 0)
+#endif
+
+// DSPI
+// DSPI Pins
+
+#define KINETIS_PIN_SPI1_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M | \
+                                  CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+#define KINETIS_PIN_SPI1_SCK_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M)
+#define KINETIS_PIN_SPI1_CS_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M | \
+                                  CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+
+#define KINETIS_PIN_SPI1_IN_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+#define KINETIS_PIN_SPI1_0_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN  CYGHWR_HAL_KINETIS_PIN(E, 1, 7, KINETIS_PIN_SPI1_IN_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 3, 7, KINETIS_PIN_SPI1_OUT_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK  CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_SCK_OPT)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0  CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1  CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2  CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3  CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4  CYGHWR_HAL_KINETIS_PIN_NONE
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5  CYGHWR_HAL_KINETIS_PIN_NONE
+
+// I2C
+// I2C Pins
+
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(D, 9, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(D, 8, 2, 0)
+
+# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SDA CYGHWR_HAL_KINETIS_PIN(C, 11, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SCL CYGHWR_HAL_KINETIS_PIN(C, 10, 2, 0)
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
+
diff --git a/packages/hal/cortexm/kinetis/twr_k60f120m/current/misc/redboot_K60_ROM_FPU.ecm b/packages/hal/cortexm/kinetis/twr_k60f120m/current/misc/redboot_K60_ROM_FPU.ecm
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60f120m/current/misc/redboot_K60_ROM_FPU.ecm
@@ -0,0 +1,83 @@
+# Redboot minimal configuration
+# Target: TWR-K60F120M
+# Startup: ROM
+
+
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "RedBoot Kinetis TWR-K60F120M" ;
+    package CYGPKG_IO_FLASH current ;
+    package CYGPKG_IO_ETH_DRIVERS current ;
+};
+
+cdl_option CYGHWR_HAL_CORTEXM_FPU {
+    user_value 1
+};
+
+cdl_option CYGHWR_HAL_CORTEXM_FPU_SWITCH {
+    user_value ALL
+};
+
+cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
+    user_value 1
+};
+
+cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP {
+    user_value 1
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 0
+};
+
+#cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH {
+#    user_value 1
+#};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+    user_value -1
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK {
+    user_value -2
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT {
+    user_value 16
+};
+
+#cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE {
+#    user_value 0x20000
+#};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+    user_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+    user_value ROM
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    user_value 1
+};
+
+cdl_component CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA {
+    user_value 1
+};
diff --git a/packages/hal/cortexm/kinetis/twr_k60f120m/current/src/twr_k60f120m_misc.c b/packages/hal/cortexm/kinetis/twr_k60f120m/current/src/twr_k60f120m_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60f120m/current/src/twr_k60f120m_misc.c
@@ -0,0 +1,252 @@
+//==========================================================================
+//
+//      twr_k60f120m_misc.c
+//
+//      Cortex-M4 TWR-K60N512 EVAL HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      Ilija Kocho <ilijak@siva.com.mk>
+// Contrib(s):     Mike Jones <mjones@proclivis.com>
+// Date:           2013-06-02
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60f120m.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+static inline void hal_misc_init(void);
+
+// DATA and BSS locations
+__externC cyg_uint32 __ram_data_start;
+__externC cyg_uint32 __ram_data_end;
+__externC cyg_uint32 __rom_data_start;
+__externC cyg_uint32 __sram_data_start;
+__externC cyg_uint32 __sram_data_end;
+__externC cyg_uint32 __srom_data_start;
+__externC cyg_uint32 __bss_start;
+__externC cyg_uint32 __bss_end;
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_system_init( void )
+{
+#if !defined(CYG_HAL_STARTUP_RAM)
+    cyghwr_hal_kinetis_pmc_t *pmc_p = CYGHWR_HAL_KINETIS_PMC_P;
+
+    hal_wdog_disable();
+    hal_misc_init();
+
+    // if ACKISO is set you must clear ackiso before calling pll_init
+    //    or pll init hangs waiting for OSC to initialize
+    if(pmc_p->regsc & CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M)
+        pmc_p->regsc |= CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M;
+
+    hal_start_clocks();
+#endif
+}
+
+//===========================================================================
+// hal_misc_init
+//===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M)
+
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_misc_init(void)
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
+
+    // Enable some peripherals' clocks.
+    sim_p->scgc1 |= CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_M;
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
+
+    // Disable MPU
+    mpu_p->cesr = 0;
+}
+
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+    { CYGMEM_REGION_ram,        CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1        }, // System bus RAM partition
+#ifdef CYGMEM_REGION_sram
+    { CYGMEM_REGION_sram,       CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1      }, // On-chip SRAM
+#elif defined CYGMEM_REGION_sram_l
+    { CYGMEM_REGION_sram_l,     CYGMEM_REGION_sram_l+CYGMEM_REGION_sram_l_SIZE-1  }, // On-chip SRAM lower bank
+#endif
+#ifdef CYGMEM_REGION_ramcod
+    { CYGMEM_REGION_ramcod,      CYGMEM_REGION_ramcod+CYGMEM_REGION_ramcod_SIZE-1 }, // Code bus RAM partition
+#endif
+#ifdef CYGMEM_REGION_ramnc
+    { CYGMEM_REGION_ramnc,      CYGMEM_REGION_ramnc+CYGMEM_REGION_ramnc_SIZE-1    }, // Non cachable RAM partition
+#endif
+#ifdef CYGMEM_REGION_flash
+    { CYGMEM_REGION_flash,      CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1    }, // On-chip flash
+#endif
+#ifdef CYGMEM_REGION_rom
+    { CYGMEM_REGION_rom,        CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1        }, // External flash [currently none]
+#endif
+    { 0xE0000000,               0x00000000-1                                      }, // Cortex-M peripherals
+    { 0x40000000,               0x60000000-1                                      }  // Chip specific peripherals
+};
+
+__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) {
+        if( ((CYG_ADDRESS)addr >= hal_data_access[i].start) &&
+            ((CYG_ADDRESS)addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the on-chip SRAM and external SRAM.
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_sram
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_sram;
+        *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
+        break;
+#endif
+#ifdef CYGMEM_REGION_sram_l
+# define CASE_CODE 3
+# define CASE_RAMNC 4
+    case 2:
+        *start = (unsigned char *)CYGMEM_REGION_sram_l;
+        *end = (unsigned char *)(CYGMEM_REGION_sram_l + CYGMEM_REGION_sram_l_SIZE);
+        break;
+#else
+# define CASE_CODE 2
+# define CASE_RAMNC 3
+#endif
+
+#ifdef CYGMEM_REGION_ramcod
+    case CASE_CODE:
+        *start = (unsigned char *)CYGMEM_REGION_ramcod;
+        *end = (unsigned char *)(CYGMEM_REGION_ramcod + CYGMEM_REGION_ramcod_SIZE);
+        break;
+#endif
+
+#ifdef CYGMEM_REGION_ramnc
+    case CASE_RAMNC:
+        *start = (unsigned char *)CYGMEM_REGION_ramnc;
+        *end = (unsigned char *)(CYGMEM_REGION_ramnc + CYGMEM_REGION_ramnc_SIZE);
+        break;
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+} // cyg_plf_memory_segment()
+
+#endif // CYGPKG_REDBOOT
+
+//==========================================================================
+// EOF twr_k60f120m_misc.c
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog b/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog
@@ -0,0 +1,66 @@
+2013-04-09  Tomas Frydrych <tomas@sleepfive.com>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512.cdl:
+	* include/plf_io.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k60n512_misc.c: Clock gating synchronised with variant.
+	[ Bugzilla 1001814 ]
+
+2012-10-25  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k60n512_misc.c: Initialization for separate SRAM regions
+	synchronized with variant.                  [Bugzilla 1001606]
+
+2012-05-19  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512.cdl: Reference per-package
+	documentation.
+
+2012-05-18  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* doc/twr_k60n512.sgml:
+	New file -- TWR-K60N512 platform documentation. [Bug 1001580]
+
+2012-01-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512.cdl:
+	* include/plf_io.h:
+	* src/twr_k60n512_misc.c:
+	Add entry for DMA, Add CYG_HAL_STARTUP_ENV. Add DSPI pins for SPI1 bus.
+	Updated for early clock start.  [Bugzilla 1001450]
+
+2011-03-26  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512.cdl:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* src/twr_k60n512_misc.c:
+	New package -- Freescale TWR-K60N512 board.
+	
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2012 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512/current/cdl/hal_cortexm_kinetis_twr_k60n512.cdl b/packages/hal/cortexm/kinetis/twr_k60n512/current/cdl/hal_cortexm_kinetis_twr_k60n512.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/cdl/hal_cortexm_kinetis_twr_k60n512.cdl
@@ -0,0 +1,332 @@
+##==========================================================================
+##
+##      hal_cortexm_kinetis_twr_k60n512.cdl
+##
+##      Cortex-M Freescale TWR-K60N512 platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011, 2012 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-02-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60N512 {
+    display       "Freescale Kinetis TWR-K60N512 Platform"
+    parent        CYGPKG_HAL_CORTEXM_KINETIS
+    define_header hal_cortexm_kinetis_twr_k60n512.h
+    include_dir   cyg/hal
+    doc           ref/kinetis-twr-k60n512.html
+    hardware
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+    requires      { is_active(CYGPKG_DEVS_ETH_FREESCALE_ENET)
+                  implies CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" }
+
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART3
+    implements    CYGINT_IO_FREESCALE_I2C0
+    
+    implements    CYGINT_HAL_FREESCALE_UART3
+    implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
+
+    description   "
+        The Freescale TWR K60N512 Platform HAL package provides the support
+        needed to run eCos on the TWR K60N512 development system. This package
+        can also be used for other boards that employ a controller from Kinetis
+        families."
+
+    compile       twr_k60n512_misc.c
+
+    requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
+        (1 == CYGHWR_DEVS_ETH_PHY_KSZ8041) }
+    requires      { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies
+        (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k60n512.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Freescale TWR-K60N512\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYG_HAL_STARTUP_ENV {
+        display "Startup type"
+        flavor data
+        no_define
+        calculated {
+            !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP :
+            ((CYG_HAL_STARTUP_PLF == "ByVariant") ?
+            (CYG_HAL_STARTUP . "(Variant)") :
+            (CYG_HAL_STARTUP . "(Platform)"))
+        }
+        description "
+            Startup type configuration defines the system memory layout.
+            Startup type  can be defined by the variant (CYG_HAL_STARTUP_VAR)
+            or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ {
+        display "Platform Clock Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" ||
+                   CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        default_value 50000000
+        legal_values { 25000000 50000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP {
+        display "Platform requred XTAL || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC {
+        display "Platform requred RTC XTAL || C \[pF\]"
+        flavor bool
+        default_value 0
+        parent CYGHWR_HAL_CORTEXM_KINETIS_RTC
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        legal_values 0 to 2
+        default_value   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR board has one serial port fitted to RS232 connector.
+            This option chooses which port will be used to connect to a host
+            running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display          "Diagnostic serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR has one serial port fitted to RS232 connector.
+            This option chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+        This option controls the default baud rate used for the
+        console connection.
+        Note: this should match the value chosen for the GDB port if the
+        diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console port
+            if the console and GDB port are the same."
+    }
+
+    cdl_option CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK {
+        display "ENET MII MDC clock provided by HAL"
+        flavor data
+        active_if CYGPKG_DEVS_ETH_FREESCALE_ENET
+        parent CYGPKG_DEVS_ETH_FREESCALE_ENET
+        calculated CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS
+        description "
+            ENET needs a clock with typical frequency of up to 2.5 MHz for
+            MII MDC. The input clock, typically provided by HAL, is further
+            divided by ENET according to setting of ENET MSCR register in order to
+            provide frequency within 2.5 MHz range."
+     }
+
+    cdl_option CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT {
+        display "IEEE 1588 Port"
+        active_if CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        parent CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        flavor data
+        default_value { "B" }
+        legal_values { "B" "C" "User" }
+        description "
+            Digital I/O provided by HAL for ENET IEEE 1588 timers."
+    }
+
+    cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS {
+        display "MMC Disk SPI bus"
+        flavor data
+        parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+        calculated 1
+
+        requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1
+        implements CYGINT_DEVS_SPI_FREESCALE_DSPI1
+        implements CYGINT_FREESCALE_DSPI1_HAS_MASS
+
+        cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS {
+            display "Device number (CS)"
+            flavor data
+            calculated 0
+            implements CYGINT_FREESCALE_DSPI1_CS0
+        }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+        Global build options including control over
+        compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+            This option controls the global compiler flags which are used to
+            compile all packages by default. Individual packages may define
+            options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+            This option controls the global linker flags. Individual
+            packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+            Support can be enabled for different varieties of ROM monitor.
+            This support changes various eCos semantics such as the encoding
+            of diagnostic output, or the overriding of hardware interrupt
+            vectors.
+            Firstly there is \"Generic\" support which prevents the HAL
+            from overriding the hardware vectors that it does not use, to
+            instead allow an installed ROM monitor to handle them. This is
+            the most basic support which is likely to be common to most
+            implementations of ROM monitor.
+            \"GDB_stubs\" provides support when GDB stubs are included in
+            the ROM monitor or boot ROM."
+    }
+
+
+    cdl_component CYGBLD_HAL_CORTEXM_TWR_MK60N512_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+
+        description "
+            This component causes the ELF image generated by the
+            build process to be converted to S-Record and binary
+            files."
+    }
+}
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512/current/doc/twr_k60n512.sgml b/packages/hal/cortexm/kinetis/twr_k60n512/current/doc/twr_k60n512.sgml
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/doc/twr_k60n512.sgml
@@ -0,0 +1,134 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     twr_k60n512.sgml                                             -->
+<!--                                                                 -->
+<!--     TWR-K60N512 board documentation.                             -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2012 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2012/01/10                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<!--<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>-->
+
+<refentry id="kinetis-twr-k60n512">
+  <refmeta>
+    <refentrytitle>TWR-K60N512-KIT Development kit</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60N512</refname>
+    <refpurpose>eCos Support for the Freescale TWR-K60N512 development kit</refpurpose>
+  </refnamediv>
+
+  <refsect1 id="kinetis-twr-k60n512-description"><title>Description</title>
+    <para>
+    The Freescale TWR-K60N512-KIT is a development kit for <link linkend="hal-cortexm-kinetis-var">
+    Freescale Kinetis</link> Cortex-M4 based microcontrollers.
+    It covers K60, K10 and K20 microcontroller families.
+    K60N512 is a high end member comprising 512 KiB FLASH and 128 KiB SRAM,
+    as well as rich set of communication interfaces inclduing Ethernet USB, UARTs CAN, SPI and I2C.
+    K60 micro-controllres also have a DMA controller and a FlexBus external memory interface.
+    They are mixed signal devices featuring a 16 bit ADC and a 12 bit DAC. 
+    </para>
+  </refsect1>
+
+  <refsect1 id="kinetis-twr-k60n512-config"><title>Configuration</title>
+    <refsect2 id="kinetis-twr-k60n512-config-hardware"><title>Hardware Setup</title>
+      <para>
+      Factory jumper settings on the TWR-K60N512 are fitted for standalone operation of the TWR-K60N512.
+      In order to use it with the Ethernet PHY on TWR-SER, some jumpers have to be changed from their factory
+      settings on both TWR-K60N512 and TWR-SER:
+      </para>
+      <table frame="all"><title>TWR-K60N512 Jumper setting differences from factory settings</title>
+        <tgroup cols="3" align="center">
+          <colspec colnum="1" colname="jumper" colwidth="1*" >
+          <colspec colnum="2" colname="jumpset" colwidth="1*" >
+          <colspec colnum="3" colname="desc" colwidth="3*" >
+        <thead>
+          <row>
+            <entry>Jumper</entry>
+            <entry>Setting</entry>
+            <entry>Description</entry>
+          </row>
+        </thead>
+        <tbody>
+          <row>
+            <entry>J6</entry>
+            <entry>2-3</entry>
+            <entry>Select TWR-SER oscillator as clock source.</entry>
+          </row>
+        </tbody>
+      </tgroup>
+      </table>
+      
+      <table frame="all"><title>TWR-SER Jumper settings differences from factory settings</title>
+      <tgroup cols="3" align="center">
+          <colspec colnum="1" colname="jumper" colwidth="1*" >
+          <colspec colnum="2" colname="jumpset" colwidth="1*" >
+          <colspec colnum="3" colname="desc" colwidth="3*" >
+        <thead>
+          <row>
+            <entry>Jumper</entry>
+            <entry>Setting</entry>
+            <entry>Description</entry>
+          </row>
+        </thead>
+        <tbody>
+          <row>
+            <entry>J2</entry>
+            <entry>3-4</entry>
+            <entry>Ethernet PHY clock select: 50MHz</entry>
+          </row>
+          <row>
+            <entry>J3</entry>
+            <entry>2-3</entry>
+            <entry>Route 50MHz to CLOCKIN0</entry>
+          </row>
+          <row>
+            <entry>J12</entry>
+            <entry>9-10</entry>
+            <entry>Ethernet PHY config: select RMII mode</entry>
+          </row>
+        </tbody>
+      </tgroup>
+    </table>
+     </refsect2>
+    <refsect2 id="kinetis-twr-k60n512-config-ecos"><title>eCos Configuration</title>
+  <refsect3 id="twr-k60n512-clocking"><title>Clocking</title>
+    <para>
+    TWR-K60N512 uses default Kinetis variant clocking.
+    </para>
+  </refsect3>  
+  <refsect3 id="twr-k60n512-memory"><title>Memory</title>
+    <para> K60 has two 64KiB SRAM banks giving a total of 128KiB on chip SRAM. </para>
+  </refsect3>
+ </refsect2>
+  </refsect1>
+</refentry>
+
+<!--</part>-->
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_arch.h b/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_arch.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Contributor(s):
+// Date:        2011-02-05
+// Purpose:     TWR-K60N512 platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_intr.h b/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_intr.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-02-05
+// Purpose:     TWR-K60N512 platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_io.h b/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_io.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_io.h
@@ -0,0 +1,151 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-02-05
+// Purpose:     TWR-K60N512 platform specific registers
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512.h>
+
+
+// UART PINs
+
+#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(C, 16, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(C, 17, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_FREESCALE_UART3_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_FREESCALE_UART3_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_FREESCALE_UART3_PIN_CTS
+#endif
+
+// ENET PINs
+
+// MDIO
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDIO    CYGHWR_HAL_KINETIS_PIN(B, 0, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDC     CYGHWR_HAL_KINETIS_PIN(B, 1, 4, 0)
+// Both RMII and MII interface
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXER    CYGHWR_HAL_KINETIS_PIN(A, 5, 4, \
+                                                    CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD1    CYGHWR_HAL_KINETIS_PIN(A, 12, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD0    CYGHWR_HAL_KINETIS_PIN(A, 13, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXEN    CYGHWR_HAL_KINETIS_PIN(A, 15, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD0    CYGHWR_HAL_KINETIS_PIN(A, 16, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD1    CYGHWR_HAL_KINETIS_PIN(A, 17, 4, 0)
+// RMII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_CRS_DV  CYGHWR_HAL_KINETIS_PIN(A, 14, 4, 0)
+// MII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD3     CYGHWR_HAL_KINETIS_PIN(A, 9, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD2     CYGHWR_HAL_KINETIS_PIN(A, 10, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXCLK    CYGHWR_HAL_KINETIS_PIN(A, 11, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD2     CYGHWR_HAL_KINETIS_PIN(A, 24, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXCLK    CYGHWR_HAL_KINETIS_PIN(A, 25, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD3     CYGHWR_HAL_KINETIS_PIN(A, 26, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_CRS      CYGHWR_HAL_KINETIS_PIN(A, 27, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MIIO_TXER     CYGHWR_HAL_KINETIS_PIN(A, 28, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_COL      CYGHWR_HAL_KINETIS_PIN(A, 29, 4, 0)
+// IEEE 1588 timers
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_1588_CLKIN    CYGHWR_HAL_KINETIS_PIN(E, 26, 4, 0)
+
+#if defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_B)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(B, 2, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(B, 3, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(B, 4, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(B, 5, 4, 0)
+#elif defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_C)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(C, 16, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(C, 17, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(C, 18, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(C, 19, 4, 0)
+#endif
+
+
+// DSPI
+// DSPI Pins
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN  CYGHWR_HAL_KINETIS_PIN(E, 3, 2, KINETIS_PIN_SPI1_IN_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 1, 2, KINETIS_PIN_SPI1_OUT_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK  CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_OUT_OPT)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0  CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1  CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2  CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3  CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4  CYGHWR_HAL_KINETIS_PIN_NONE
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5  CYGHWR_HAL_KINETIS_PIN_NONE
+
+// I2C
+// I2C Pins
+
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(D, 9, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(D, 8, 2, 0)
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512/current/src/twr_k60n512_misc.c b/packages/hal/cortexm/kinetis/twr_k60n512/current/src/twr_k60n512_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/src/twr_k60n512_misc.c
@@ -0,0 +1,208 @@
+//==========================================================================
+//
+//      twr_k60n512_misc.c
+//
+//      Cortex-M4 TWR-K60N512 EVAL HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2011-02-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+static inline void hal_misc_init(void);
+
+// DATA and BSS locations
+__externC cyg_uint32 __ram_data_start;
+__externC cyg_uint32 __ram_data_end;
+__externC cyg_uint32 __rom_data_start;
+__externC cyg_uint32 __sram_data_start;
+__externC cyg_uint32 __sram_data_end;
+__externC cyg_uint32 __srom_data_start;
+__externC cyg_uint32 __bss_start;
+__externC cyg_uint32 __bss_end;
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_system_init( void )
+{
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
+    hal_wdog_disable();
+    hal_misc_init();
+    hal_start_clocks();
+#endif
+}
+
+//===========================================================================
+// hal_misc_init
+//===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M)
+
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_misc_init(void)
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
+
+    // Enable some peripherals' clocks.
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
+
+    // Disable MPU
+    mpu_p->cesr = 0;
+}
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+    { CYGMEM_REGION_ram,        CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1      },      // Main RAM
+#ifdef CYGMEM_REGION_sram
+    { CYGMEM_REGION_sram,       CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1    },      // On-chip SRAM
+#endif
+#ifdef CYGMEM_REGION_flash
+    { CYGMEM_REGION_flash,      CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1  },      // On-chip flash
+#endif
+#ifdef CYGMEM_REGION_rom
+    { CYGMEM_REGION_rom,        CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1      },      // External flash
+#endif
+    { 0xE0000000,               0x00000000-1                                    },      // Cortex-M peripherals
+    { 0x40000000,               0x60000000-1                                    },      // Chip specific peripherals
+};
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) {
+        if( (addr >= hal_data_access[i].start) &&
+            (addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the on-chip SRAM and external SRAM.
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_sram
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_sram;
+        *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
+        break;
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+} // cyg_plf_memory_segment()
+
+#endif // CYGPKG_REDBOOT
+
+//==========================================================================
+// EOF twr_k60n512_misc.c
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog
@@ -0,0 +1,103 @@
+2013-04-28  Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl:
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h: (New)
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi: (New)
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h:
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi:
+	* include/pkgconf/mlt_kinetis_flash_sram2s_ram.h: (Remove)
+	* include/pkgconf/mlt_kinetis_flash_sram2s_ram.ldi: (Remove)
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h:
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi:
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h:
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi:
+	* include/plf_io.h:
+	* misc/redboot_K60_FXM_SST25XX_ROM.ecm: (New)
+	* src/twr_k60n512_fxm_misc.c:
+	Rich memory layout for FlexBus RAM with support for caching.
+	Remove redundant MLT files. [ Bugzilla 1001837 ]
+
+2013-04-09  Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl:
+	* include/plf_io.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k60n512_fxm_misc.c: Clock gating synchronised with variant.
+	[ Bugzilla 1001814 ]
+
+2012-11-06 Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl:
+	Removed (obsolete) implementation of CYGINT_HAL_CORTEXM4_CODE.
+
+2012-10-25  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi:
+	* src/twr_k60n512_misc_fxm.c: Initialization for separate SRAM regions
+	synchronized with variant.                  [Bugzilla 1001606]
+
+2012-01-06 Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl,
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi
+	* /src/twr_k60n512_fxm_misc.c
+	Fixed memory layout for FlexBus memory. Add different pin options
+	[Bugzilla 1001579]
+
+2012-01-06 Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* include/hal_kinetis_flexbus.h
+	* src/twr_k60n512_fxm_misc.c:
+	* include/pkgconf/mltkinetis_flash_sram2s_extram_rom.h
+	* include/pkgconf/mltkinetis_flash_sram2s_extram_rom.ldi
+	* include/pkgconf/mltkinetis_flash_sram2s_jtag.h
+	* include/pkgconf/mltkinetis_flash_sram2s_jtag.ldi
+	* include/pkgconf/mltkinetis_flash_sram2s_ram.h
+	* include/pkgconf/mltkinetis_flash_sram2s_ram.ldi
+	* include/pkgconf/mltkinetis_flash_unisram_extram.h
+	* include/pkgconf/mltkinetis_flash_unisram_extram_jtag.h
+	* include/pkgconf/mltkinetis_flash_unisram_extram_jtag.ldi
+	* include/pkgconf/mltkinetis_flash_unisram_extram.ldi
+	* include/pkgconf/mltkinetis_flash_unisram_extram_ram.h
+	* include/pkgconf/mltkinetis_flash_unisram_extram_ram.ldi
+	* include/pkgconf/mltkinetis_flash_unisram_extram_rom.h
+	* include/pkgconf/mltkinetis_flash_unisram_extram_rom.ldi
+	* include/pkgconf/mltkinetis_flash_unisram_jtag.h
+	* include/pkgconf/mltkinetis_flash_unisram_jtag.ldi
+	* include/pkgconf/mltkinetis_flash_unisram_ram.h
+	* include/pkgconf/mltkinetis_flash_unisram_ram.ldi
+	New package -- Freescale TWR-K60N512-FXM board.  [Bugzilla 1001450]
+	
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl
@@ -0,0 +1,648 @@
+##==========================================================================
+##
+##      hal_cortexm_kinetis_twr_k60n512_fxm.cdl
+##
+##      Cortex-M Freescale TWR-K60N512 + TWR-FXM platform HAL configuration
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 2011 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later
+## version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with eCos; if not, write to the Free Software Foundation, Inc.,
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+##
+## As a special exception, if other files instantiate templates or use
+## macros or inline functions from this file, or you compile this file
+## and link it with other works to produce a work based on this file,
+## this file does not by itself cause the resulting work to be covered by
+## the GNU General Public License. However the source code for this file
+## must still be made available in accordance with section (3) of the GNU
+## General Public License v2.
+##
+## This exception does not invalidate any other reasons why a work based
+## on this file might be covered by the GNU General Public License.
+## -------------------------------------------
+## ####ECOSGPLCOPYRIGHTEND####
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-09-26
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60N512_FXM {
+    display       "Freescale Kinetis TWR-K60N512-FXM Platform"
+    parent        CYGPKG_HAL_CORTEXM_KINETIS
+    define_header hal_cortexm_kinetis_twr_k60n512_fxm.h
+    include_dir   cyg/hal
+    hardware
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+
+    implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
+    implements    CYGINT_IO_FREESCALE_I2C0
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART4
+    implements    CYGINT_HAL_FREESCALE_UART4
+
+    description   "
+    The Freescale TWR K60N512 FXM Platform package provides the support
+    needed to run eCos on the TWR K60N512 development system equipped
+    with TWR-FXM external memory board. This package
+    can also be used for other boards that employ a controller from Kinetis
+    families."
+
+    compile       twr_k60n512_fxm_misc.c
+
+    requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
+        (1 == CYGHWR_DEVS_ETH_PHY_KSZ8041) }
+    requires      { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies
+        (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Freescale TWR-K60N512-FXM\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYG_HAL_STARTUP_ENV {
+        display "Startup type"
+        flavor data
+        no_define
+        calculated {
+            !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP :
+            ((CYG_HAL_STARTUP_PLF == "ByVariant") ?
+            (CYG_HAL_STARTUP . "(Variant)") :
+            (CYG_HAL_STARTUP . "(Platform)"))
+        }
+        description "
+            Startup type configuration defines the system memory layout.
+            Startup type  can be defined by the variant (CYG_HAL_STARTUP_VAR)
+            or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_option CYG_HAL_STARTUP_PLF {
+        display       "By platform"
+        flavor        data
+        parent        CYG_HAL_STARTUP_ENV
+        default_value { "ROM" }
+        legal_values  { "ByVariant" "ROM" "RAM" }
+        requires      { CYG_HAL_STARTUP_PLF != "ByVariant" implies
+                        CYGPKG_HAL_CORTEXM_KINETIS_FBRAM == 1 }
+
+        description   "
+            Startup tupes provided by the platform, in addition to variant
+            startup types.
+            If 'ByVariant' is selected, then startup type shall be selected from
+            the variant (CYG_HAL_STARTUP_VAR). Platform's 'ROM' startup builds
+            application similar to Variant's 'ROM' but using external RAM (FlexBus).
+            'RAM' startup builds application intended for loading by RedBoot into
+            external RAM."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT_PLF {
+        display "Memory layout by platform"
+        flavor data
+        no_define
+        active_if { CYG_HAL_STARTUP_PLF != "ByVariant" }
+        implements CYGINT_HAL_CORTEXM_KINETIS_FBRAM
+        parent  CYGHWR_MEMORY_LAYOUT
+        calculated {
+            (CYG_HAL_STARTUP_PLF == "ByVariant" ) ? "by variant" :
+            (CYG_HAL_STARTUP == "RAM") ? "kinetis_"
+            . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_extram_ram" :
+            (CYG_HAL_STARTUP == "ROM") ? "kinetis_"
+            . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_extram_rom" :
+            "Error!" }
+        description "Combination of 'Startup type' and 'Kinetis member in use'
+        produces the memory layout."
+
+        cdl_option CYGHWR_MEMORY_RAM_RESERVED {
+            display "Reserved RAM space \[Bytes\]"
+            flavor  data
+            legal_values 0 to 0x40000
+            default_value 0x20000
+        }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ {
+        display "Platform Clock Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        default_value 50000000
+        legal_values { 25000000 50000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP {
+        display "Platform requred XTAL || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC {
+        display "Platform requred RTC XTAL || C \[pF\]"
+        flavor bool
+        default_value 1
+        parent CYGHWR_HAL_CORTEXM_KINETIS_RTC
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        legal_values 0 to 2
+        default_value   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+        The TWR board has one serial port fitted to RS232 connector. This option
+        chooses which port will be used to connect to a host
+        running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display          "Diagnostic serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+        The TWR has one serial port fitted to RS232 connector. This option
+        chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+        This option controls the default baud rate used for the
+        console connection.
+        Note: this should match the value chosen for the GDB port if the
+        diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+        This option controls the default baud rate used for the
+        GDB connection.
+        Note: this should match the value chosen for the console port if the
+        console and GDB port are the same."
+    }
+
+    cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS {
+        display "MMC Disk SPI bus"
+        flavor data
+        parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+        calculated 1
+
+        requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1
+        implements CYGINT_DEVS_SPI_FREESCALE_DSPI1
+        implements CYGINT_FREESCALE_DSPI1_HAS_MASS
+
+        cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS {
+            display "Device number (CS)"
+            flavor data
+            calculated 0
+            implements CYGINT_FREESCALE_DSPI1_CS0
+        }
+    }
+
+    cdl_option CYGNUM_DEVS_FLASH_SPI_SST25XX_DEV0_MAP_ADDR {
+        display "SST25XX Flash Mapping Address"
+        flavor data
+        parent CYGHWR_DEVS_FLASH_SPI_SST25XX_DEV0
+        default_value 0xD0000000
+    }
+    cdl_component CYGHWR_DEVS_FLASH_SST25XX_DEV0_SPI_BUS {
+        display "SST25xx SPI bus"
+        flavor data
+        parent CYGHWR_DEVS_FLASH_SPI_SST25XX_DEV0
+        calculated 1
+
+        requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1
+        implements CYGINT_DEVS_SPI_FREESCALE_DSPI1
+
+        cdl_option CYGHWR_DEVS_FLASH_SST25XX_DEV0_SPI_CS {
+            display "Device number (CS)"
+            flavor data
+            calculated 1
+            implements CYGINT_FREESCALE_DSPI1_CS1
+        }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
+    cdl_component CYGPKG_HAL_EXTRN_MEMORY {
+        display "External memory devices"
+        parent CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
+        flavor none
+        active_if {
+            CYGHWR_HAL_KINETIS_FB_CS0 || CYGHWR_HAL_KINETIS_FB_CS1 ||
+            CYGHWR_HAL_KINETIS_FB_CS2 || CYGHWR_HAL_KINETIS_FB_CS3 ||
+            CYGHWR_HAL_KINETIS_FB_CS4 || CYGHWR_HAL_KINETIS_FB_CS5
+        }
+        description "
+        This is a container for  memory devices attached to
+        external bus such as RAM, FLASH, etc."
+    }
+# FlexBus Implementation
+    implements CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS
+    implements CYGINT_HAL_EXTRN_MEMORY
+
+# CS0 Implementation
+    implements CYGINT_HAL_KINETIS_FB_CS0
+    implements CYGINT_DEVS_RAM0_MICRON_CELLULAR
+    requires { is_active(CYGPKG_HAL_CORTEXM_KINETIS_FBRAM) implies
+                         CYGHWR_HAL_KINETIS_FBR_SIZE == CYGHWR_HAL_KINETIS_FB_CS0_SIZE }
+
+    cdl_option CYGHWR_HAL_KINETIS_FB_CS0_AR {
+        display "Base address"
+        flavor data
+        parent CYGHWR_HAL_KINETIS_FB_CS0
+        default_value  0x60000000
+    }
+
+    cdl_option CYGHWR_HAL_KINETIS_FB_CS0_SIZE {
+        display "Size \[Bytes\]"
+        flavor data
+        legal_values  { 0x00040000  0x00400000 CYGHWR_RAM0_MICRON_CELLULAR_SIZE }
+        parent        CYGHWR_HAL_KINETIS_FB_CS0
+        default_value CYGHWR_RAM0_MICRON_CELLULAR_SIZE
+    }
+
+    cdl_option CYGHWR_HAL_KINETIS_FB_CS0_BASE {
+        display "Memory base address"
+        flavor data
+        parent CYGHWR_HAL_KINETIS_FB_CS0
+        calculated CYGHWR_HAL_KINETIS_FB_CS0_AR
+    }
+
+    cdl_component CYGHWR_HAL_KINETIS_FB_CS0_MR {
+        display "Mask register"
+        flavor data
+        parent CYGHWR_HAL_KINETIS_FB_CS0
+        default_value 0x00FF0001
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_MR_WP {
+            display "Write protect"
+            flavor bool
+            default_value 0
+        }
+    }
+
+    cdl_component CYGHWR_HAL_KINETIS_FB_CS0_CR {
+        display "Control register"
+        flavor none
+        parent CYGHWR_HAL_KINETIS_FB_CS0
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_WS {
+            display "Wait states"
+            flavor data
+            default_value 3
+            legal_values 0 to 63
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_BLS {
+            display "Byte lane shift"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_AA {
+            display "Auto acknowledge enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FB_CS0_CR_PSB {
+            display "Port size (bits)"
+            flavor data
+            legal_values { 32 8 16 "-16" }
+            default_value 16
+
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_SWSEN {
+            display "Secondary wait states enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_SWS {
+            display "Secondary wait states"
+            flavor data
+            legal_values 0 to 63
+            default_value 0
+
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_EXALE {
+            display "Extended address latch enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_ASET {
+            display "Address setup"
+            flavor data
+            legal_values { 0 1 2 3 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_RDAH {
+            display "Read address hold or deselect"
+            flavor data
+            legal_values { 0 1 2 3 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_WRAH {
+            display "Write address hold or deselect"
+            flavor data
+            legal_values { 0 1 2 3 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_BEM {
+            display "Byte enable mode"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_BSTR {
+            display "Burst read enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_BSTW {
+            display "Burst write enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 0
+        }
+    }
+
+    cdl_component CYGHWR_HAL_KINETIS_FB_CS0_CR_IS {
+        display "Control register initial setting."
+        flavor none
+        parent CYGHWR_HAL_KINETIS_FB_CS0
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_WS {
+            display "Wait states"
+            flavor data
+            default_value 3
+            legal_values 0 to 63
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_AA {
+            display "Auto acknowledge enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_SWSEN {
+            display "Secondary wait states enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_SWS {
+            display "Secondary wait states"
+            flavor data
+            legal_values 0 to 63
+            default_value 0
+
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_EXALE {
+            display "Extended address latch enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_ASET {
+            display "Address setup"
+            flavor data
+            legal_values { 0 1 2 3 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_RDAH {
+            display "Read address hold or deselect"
+            flavor data
+            legal_values { 0 1 2 3 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_WRAH {
+            display "Write address hold or deselect"
+            flavor data
+            legal_values { 0 1 2 3 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_BEM {
+            display "Byte enable mode"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_BSTR {
+            display "Burst read enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_BSTW {
+            display "Burst write enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 0
+        }
+    }
+# CS0 Implementation End
+# FlexBus  Implementation End
+
+    cdl_option CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE {
+        display "External RAM size"
+        flavor data
+        calculated CYGHWR_HAL_KINETIS_FB_CS0_SIZE
+    }
+
+    cdl_option CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE {
+        display "External RAM base address"
+        flavor data
+        calculated CYGHWR_HAL_KINETIS_FB_CS0_BASE
+    }
+
+    cdl_option CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK {
+        display "ENET MII MDC clock provided by HAL"
+        flavor data
+        active_if CYGPKG_DEVS_ETH_FREESCALE_ENET
+        parent CYGPKG_DEVS_ETH_FREESCALE_ENET
+        calculated CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS
+        description "
+            ENET needs a clock with typical frequency of up to 2.5 MHz for
+            MII MDC. The input clock, typically provided by HAL, is further
+            divided by ENET according to setting of ENET MSCR register in order to
+            provide frequency within 2.5 MHz range."
+     }
+
+    cdl_option CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT {
+        display "IEEE 1588 Port"
+        active_if CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        parent CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        flavor data
+        default_value { "B" }
+        legal_values { "B" "C" "User" }
+        description "
+            Digital I/O provided by HAL for ENET IEEE 1588 timers."
+    }
+
+
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+        Global build options including control over
+        compiler flags, linker flags and choice of toolchain."
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+            This option specifies the command prefix used when
+            invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+            This option controls the global compiler flags which are used to
+            compile all packages by default. Individual packages may define
+            options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+            This option controls the global linker flags. Individual
+            packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+        Enable this option if this program is to be used as a ROM monitor,
+        i.e. applications will be loaded into RAM on the board, and this
+        ROM monitor may process exceptions or interrupts generated from the
+        application. This enables features such as utilizing a separate
+        interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+        Support can be enabled for different varieties of ROM monitor.
+        This support changes various eCos semantics such as the encoding
+        of diagnostic output, or the overriding of hardware interrupt
+        vectors.
+        Firstly there is \"Generic\" support which prevents the HAL
+        from overriding the hardware vectors that it does not use, to
+        instead allow an installed ROM monitor to handle them. This is
+        the most basic support which is likely to be common to most
+        implementations of ROM monitor.
+        \"GDB_stubs\" provides support when GDB stubs are included in
+        the ROM monitor or boot ROM."
+    }
+
+    cdl_component CYGBLD_HAL_CORTEXM_TWR_MK60N512_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+
+        description "This component causes the ELF image generated by the
+        build process to be converted to S-Record and binary
+        files."
+    }
+}
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/hal_kinetis_flexbus.h b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/hal_kinetis_flexbus.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/hal_kinetis_flexbus.h
@@ -0,0 +1,143 @@
+#ifndef CYGONCE_FLEXBUS_H
+#define CYGONCE_FLEXBUS_H
+//=============================================================================
+//
+//      flexbus.h
+//
+//      Kinetis FlexBus specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-08-05
+// Purpose:     Kinetis FlexBus specific registers
+// Description:
+// Usage:       #include <cyg/hal/flexbus.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//--------------------------------------------------------------------------
+// Flexbus pins
+
+#define KINETIS_PIN_FB_OPT CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M
+#define KINETIS_PIN_FB     5
+#define KINETIS_PIN_FB6    6
+
+#define CYGHWR_KINETIS_FB_PIN_AD0  CYGHWR_HAL_KINETIS_PIN(D, 6, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD1  CYGHWR_HAL_KINETIS_PIN(D, 5, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD2  CYGHWR_HAL_KINETIS_PIN(D, 4, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD3  CYGHWR_HAL_KINETIS_PIN(D, 3, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD4  CYGHWR_HAL_KINETIS_PIN(D, 2, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD5  CYGHWR_HAL_KINETIS_PIN(C, 10, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD6  CYGHWR_HAL_KINETIS_PIN(C, 9, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD7  CYGHWR_HAL_KINETIS_PIN(C, 8, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD8  CYGHWR_HAL_KINETIS_PIN(C, 7, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD9  CYGHWR_HAL_KINETIS_PIN(C, 6, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD10 CYGHWR_HAL_KINETIS_PIN(C, 5, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD11 CYGHWR_HAL_KINETIS_PIN(C, 4, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD12 CYGHWR_HAL_KINETIS_PIN(C, 2, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD13 CYGHWR_HAL_KINETIS_PIN(C, 1, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD14 CYGHWR_HAL_KINETIS_PIN(C, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD15 CYGHWR_HAL_KINETIS_PIN(B, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD16 CYGHWR_HAL_KINETIS_PIN(B, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD17 CYGHWR_HAL_KINETIS_PIN(B, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD18 CYGHWR_HAL_KINETIS_PIN(B, 11, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD19 CYGHWR_HAL_KINETIS_PIN(B, 10, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD20 CYGHWR_HAL_KINETIS_PIN(B, 9, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD21 CYGHWR_HAL_KINETIS_PIN(B, 8, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD22 CYGHWR_HAL_KINETIS_PIN(B, 7, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD23 CYGHWR_HAL_KINETIS_PIN(B, 6, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD24 CYGHWR_HAL_KINETIS_PIN(C, 15, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD25 CYGHWR_HAL_KINETIS_PIN(C, 14, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD26 CYGHWR_HAL_KINETIS_PIN(C, 13, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD27 CYGHWR_HAL_KINETIS_PIN(C, 12, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD28 CYGHWR_HAL_KINETIS_PIN(B, 23, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD29 CYGHWR_HAL_KINETIS_PIN(B, 22, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD30 CYGHWR_HAL_KINETIS_PIN(B, 21, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD31 CYGHWR_HAL_KINETIS_PIN(B, 20, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+
+#define CYGHWR_KINETIS_FB_PIN_A16 CYGHWR_HAL_KINETIS_PIN(D, 8, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_A17 CYGHWR_HAL_KINETIS_PIN(D, 9, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_A18 CYGHWR_HAL_KINETIS_PIN(D, 10, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_A19 CYGHWR_HAL_KINETIS_PIN(D, 11, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_A20 CYGHWR_HAL_KINETIS_PIN(D, 12, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_A21 CYGHWR_HAL_KINETIS_PIN(D, 13, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_A22 CYGHWR_HAL_KINETIS_PIN(D, 14, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_A23 CYGHWR_HAL_KINETIS_PIN(D, 15, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+
+#define CYGHWR_KINETIS_FB_PIN_CLKOUT CYGHWR_HAL_KINETIS_PIN(C, 3, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_CLKOUT_OFF                                     \
+            CYGHWR_HAL_KINETIS_PIN(C, 3, CYGHWR_HAL_KINETIS_PORT_PCR_MUX_GPIO, \
+                                         CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+
+#define CYGHWR_KINETIS_FB_PIN_RW CYGHWR_HAL_KINETIS_PIN(C, 11, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_OE CYGHWR_HAL_KINETIS_PIN(B, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+
+// Following pins are additionally multiplexed by FB_CSPMCR
+
+#define CYGHWR_KINETIS_FB_PIN_BE23_16 CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_BE31_24 CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_BE15_8  CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_BE7_0   CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+
+#define CYGHWR_KINETIS_FB_PIN_BLS15_8  CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_BLS7_0   CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_BLS23_16 CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_BLS31_24 CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+
+#define CYGHWR_KINETIS_FB_PIN_CS5 CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_CS4 CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_CS2 CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_CS3 CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_CS1 CYGHWR_HAL_KINETIS_PIN(D, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_CS0 CYGHWR_HAL_KINETIS_PIN(D, 1, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_CS0_LOW  \
+                    CYGHWR_HAL_KINETIS_PIN(D, 1, CYGHWR_HAL_KINETIS_PORT_PCR_MUX_GPIO, \
+                             CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+
+#define CYGHWR_KINETIS_FB_PIN_TSIZ0 CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_TSIZ1 CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_TST   CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_ALE   CYGHWR_HAL_KINETIS_PIN(D, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_TS    CYGHWR_HAL_KINETIS_PIN(D, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+
+#define CYGHWR_KINETIS_FB_PIN_TA    CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+
+//-----------------------------------------------------------------------------
+// end of flexbus.h
+#endif // CYGONCE_FLEXBUS_H
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h
@@ -0,0 +1,32 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
@@ -0,0 +1,41 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE
+    sram   : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000000, LMA_EQ_VMA)
+    SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LMA_EQ_VMA)
+    SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE+CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
+
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h
@@ -0,0 +1,40 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+//#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_BASE)
+//#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE)
+//#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi
@@ -0,0 +1,49 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE
+    sram   : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000000, FOLLOWING (.got))
+    SECTION_data (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h
@@ -0,0 +1,26 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi
@@ -0,0 +1,35 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram   : ORIGIN = CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE, LENGTH = CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE
+    sram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (ram, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h
@@ -0,0 +1,28 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
@@ -0,0 +1,39 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+
+MEMORY
+{
+    sram   : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA)
+    SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LMA_EQ_VMA)
+    SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE + CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h
@@ -0,0 +1,32 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi
@@ -0,0 +1,47 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram   : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got))
+    SECTION_data (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.h b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.h
@@ -0,0 +1,24 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.ldi b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.ldi
@@ -0,0 +1,43 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH security configuration. Must be present at 0x00000400
+    // Warning: Omitting FLASH security configuration or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+    
+    .flash_security 0x00000400 : { KEEP (*(.flash_security)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got))
+    SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_arch.h b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_arch.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Contributor(s):
+// Date:        2011-02-05
+// Purpose:     TWR-K60N512-FXM platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_intr.h b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_intr.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-02-05
+// Purpose:     TWR-K60N512-FXM platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h
@@ -0,0 +1,194 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-02-05
+// Purpose:     TWR-K60N512 platform specific registers
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h>
+
+// UART PINs
+
+#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# if 0
+#  define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 5, 3, 0)
+#  define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 4, 3, 0)
+# elif 0
+#  define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(C, 16, 3, 0)
+#  define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(C, 17, 3, 0)
+# else
+#  define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+#  define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# endif
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# if 0
+#  define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+#  define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_FREESCALE_UART3_PIN_TX
+#  define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_FREESCALE_UART3_PIN_RTS
+#  define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_FREESCALE_UART3_PIN_CTS
+# endif
+#endif
+
+#if 1
+#ifndef CYGHWR_HAL_FREESCALE_UART4_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART4_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 25, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART4_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 24, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART4_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART4_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+
+# define CYGHWR_IO_FREESCALE_UART4_PIN_RX CYGHWR_HAL_FREESCALE_UART4_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART4_PIN_TX CYGHWR_HAL_FREESCALE_UART4_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART4_PIN_RTS CYGHWR_HAL_FREESCALE_UART4_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART4_PIN_CTS CYGHWR_HAL_FREESCALE_UART4_PIN_CTS
+
+#endif
+#endif
+
+
+// ENET PINs
+
+// MDIO
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDIO    CYGHWR_HAL_KINETIS_PIN(B, 0, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDC     CYGHWR_HAL_KINETIS_PIN(B, 1, 4, 0)
+// Both RMII and MII interface
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXER    CYGHWR_HAL_KINETIS_PIN(A, 5, 4, \
+                                                    CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD1    CYGHWR_HAL_KINETIS_PIN(A, 12, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD0    CYGHWR_HAL_KINETIS_PIN(A, 13, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXEN    CYGHWR_HAL_KINETIS_PIN(A, 15, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD0    CYGHWR_HAL_KINETIS_PIN(A, 16, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD1    CYGHWR_HAL_KINETIS_PIN(A, 17, 4, 0)
+// RMII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_CRS_DV  CYGHWR_HAL_KINETIS_PIN(A, 14, 4, 0)
+// MII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD3     CYGHWR_HAL_KINETIS_PIN(A, 9, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD2     CYGHWR_HAL_KINETIS_PIN(A, 10, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXCLK    CYGHWR_HAL_KINETIS_PIN(A, 11, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD2     CYGHWR_HAL_KINETIS_PIN(A, 24, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXCLK    CYGHWR_HAL_KINETIS_PIN(A, 25, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD3     CYGHWR_HAL_KINETIS_PIN(A, 26, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_CRS      CYGHWR_HAL_KINETIS_PIN(A, 27, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MIIO_TXER     CYGHWR_HAL_KINETIS_PIN(A, 28, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_COL      CYGHWR_HAL_KINETIS_PIN(A, 29, 4, 0)
+// IEEE 1588 timers
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_1588_CLKIN    CYGHWR_HAL_KINETIS_PIN(E, 26, 4, 0)
+
+#if defined(CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT_B)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(B, 2, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(B, 3, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(B, 4, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(B, 5, 4, 0)
+#elif defined(CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT_C)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(C, 16, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(C, 17, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(C, 18, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(C, 19, 4, 0)
+#endif
+
+// FlexBus Memory
+#define CYGHWR_HAL_FB_CSPMCR_G1_SEL CYGHWR_HAL_FB_CSPMCR_G1_TS
+#define CYGHWR_HAL_FB_CSPMCR_G2_SEL CYGHWR_HAL_FB_CSPMCR_G2_BE_31_24
+#define CYGHWR_HAL_FB_CSPMCR_G3_SEL CYGHWR_HAL_FB_CSPMCR_G3_BE_23_16
+#define CYGHWR_HAL_FB_CSPMCR_G4_SEL CYGHWR_HAL_FB_CSPMCR_G4_CS2
+#define CYGHWR_HAL_FB_CSPMCR_G5_SEL CYGHWR_HAL_FB_CSPMCR_G5_TA
+
+#define CYGHWR_HAL_FB_CSPMCR_SETSEL (CYGHWR_HAL_FB_CSPMCR_G1_SEL + \
+                                     CYGHWR_HAL_FB_CSPMCR_G2_SEL + \
+                                     CYGHWR_HAL_FB_CSPMCR_G3_SEL + \
+                                     CYGHWR_HAL_FB_CSPMCR_G4_SEL + \
+                                     CYGHWR_HAL_FB_CSPMCR_G5_SEL )
+
+// DSPI
+// DSPI Pins
+
+#define KINETIS_PIN_SPI1_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M)
+
+#define KINETIS_PIN_SPI1_CS_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M)
+
+#define KINETIS_PIN_SPI1_IN_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M |  \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN  CYGHWR_HAL_KINETIS_PIN(E, 3, 2, KINETIS_PIN_SPI1_IN_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 1, 2, KINETIS_PIN_SPI1_OUT_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK  CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_OUT_OPT)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0  CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1  CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2  CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3  CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4  CYGHWR_HAL_KINETIS_PIN_NONE
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5  CYGHWR_HAL_KINETIS_PIN_NONE
+
+// I2C
+// I2C Pins
+
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(D, 9, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(D, 8, 2, 0)
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/misc/redboot_K60_FXM_SST25XX_ROM.ecm b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/misc/redboot_K60_FXM_SST25XX_ROM.ecm
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/misc/redboot_K60_FXM_SST25XX_ROM.ecm
@@ -0,0 +1,81 @@
+# Redboot minimal configuration
+# Target: TWR-K70F120M
+# Startup: ROM with external RAM
+
+
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "RedBoot Kinetis TWR-K60N512-FXM" ;
+    package CYGPKG_IO_FLASH current ;
+    package CYGPKG_IO_ETH_DRIVERS current ;
+};
+
+cdl_component CYGHWR_DEVS_FLASH_SPI_SST25XX_DEV0 {
+    user_value 1
+};
+
+cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP {
+    user_value 100000000
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_SIZE {
+    user_value 16384
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 0
+};
+
+#cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH {
+#    user_value 1
+#};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+    user_value -4
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK {
+    user_value -8
+};
+
+#cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT {
+#    user_value 16
+#};
+
+#cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE {
+#    user_value 0x20000
+#};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+    user_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+    user_value ROM
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    user_value 1
+};
+
+cdl_component CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA {
+    user_value 1
+};
+
+
diff --git a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c
@@ -0,0 +1,446 @@
+//==========================================================================
+//
+//      twr_k60n512_fxm_misc.c
+//
+//      Cortex-M3 TWR-K60N512 EVAL + TWR_FXM HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2011-02-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+#ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
+#include <cyg/hal/hal_kinetis_flexbus.h>
+#include <cyg/devs/ram_micron_cellularram.h>
+
+// Dependent on FlexBus memory properties up to two flexbus setting stages
+// may be needed
+
+// Macro for final setting of CSCR
+// Final settings take place when system clock is completely initialized and
+// it is possible to program FlexBus memory with desired setting.
+#define CYGHWR_HAL_FB_CSCR(__bits,__cs) \
+            VALUE_(CYGHWR_HAL_FB_CSCR_##__bits##_S, \
+                   CYGHWR_HAL_KINETIS_FB_CS##__cs##_CR_##__bits)
+
+#define CYGHWR_HAL_KINETIS_FB_CS_CR(__cs) ( CYGHWR_HAL_FB_CSCR(SWS, __cs)  + \
+         CYGHWR_HAL_FB_CSCR(SWSEN, __cs) + CYGHWR_HAL_FB_CSCR(EXALE, __cs) + \
+         CYGHWR_HAL_FB_CSCR(ASET, __cs)  + CYGHWR_HAL_FB_CSCR(RDAH, __cs)  + \
+         CYGHWR_HAL_FB_CSCR(WRAH, __cs)  + CYGHWR_HAL_FB_CSCR(WS, __cs)    + \
+         CYGHWR_HAL_FB_CSCR(BLS, __cs)   + CYGHWR_HAL_FB_CSCR(AA, __cs)    + \
+         CYGHWR_HAL_FB_CSCR(PS, __cs)    + CYGHWR_HAL_FB_CSCR(BEM, __cs)   + \
+         CYGHWR_HAL_FB_CSCR(BSTR, __cs)  + CYGHWR_HAL_FB_CSCR(BSTW, __cs))
+
+// Macros for initial settings of CSCR
+// Initial settings are used immediately after boot and make it possible to
+// utilize FlexBus memory with it's power-up setting.
+#define CYGHWR_HAL_FB_CSCR_IS(__bits,__cs) \
+            VALUE_(CYGHWR_HAL_FB_CSCR_##__bits##_S, \
+                   CYGHWR_HAL_KINETIS_FB_CS##__cs##_CR_IS_##__bits)
+
+#define CYGHWR_HAL_KINETIS_FB_CS_CR_IS(__cs) ( CYGHWR_HAL_FB_CSCR_IS(SWS, __cs)   + \
+          CYGHWR_HAL_FB_CSCR_IS(SWSEN, __cs) + CYGHWR_HAL_FB_CSCR_IS(EXALE, __cs) + \
+          CYGHWR_HAL_FB_CSCR_IS(ASET, __cs)  + CYGHWR_HAL_FB_CSCR_IS(RDAH, __cs)  + \
+          CYGHWR_HAL_FB_CSCR_IS(WRAH, __cs)  + CYGHWR_HAL_FB_CSCR_IS(WS, __cs)    + \
+          CYGHWR_HAL_FB_CSCR(BLS, __cs)      + CYGHWR_HAL_FB_CSCR_IS(AA, __cs)    + \
+          CYGHWR_HAL_FB_CSCR(PS, __cs)       + CYGHWR_HAL_FB_CSCR_IS(BEM, __cs)   + \
+          CYGHWR_HAL_FB_CSCR_IS(BSTR, __cs)  + CYGHWR_HAL_FB_CSCR_IS(BSTW, __cs))
+
+// Functions for final and initial FlexBus setting
+// Description is with the code below.
+static inline void hal_flexbus_init_initial(void);
+static inline void hal_flexbus_init_final(void);
+#endif //  CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
+
+static inline void hal_misc_init(void);
+
+// DATA and BSS locations
+__externC cyg_uint32 __ram_data_start;
+__externC cyg_uint32 __ram_data_end;
+__externC cyg_uint32 __rom_data_start;
+__externC cyg_uint32 __sram_data_start;
+__externC cyg_uint32 __sram_data_end;
+__externC cyg_uint32 __srom_data_start;
+__externC cyg_uint32 __bss_start;
+__externC cyg_uint32 __bss_end;
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_system_init( void )
+{
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
+    hal_wdog_disable();
+    hal_misc_init();
+# ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
+    {
+        // This delay is needed for Micron RAM wake-up.
+        cyg_uint32 busy_delay;
+        for(busy_delay = 0x100000; busy_delay; busy_delay--)
+            __asm__ volatile ("nop\n");
+
+        hal_flexbus_init_initial();
+
+        hal_start_clocks();
+
+        for(busy_delay = 0x100000; busy_delay; busy_delay--)
+            __asm__ volatile ("nop\n");
+
+        hal_flexbus_init_final();
+    }
+# else
+        hal_start_clocks();
+# endif
+#endif
+}
+
+//===========================================================================
+// hal_misc_init
+//===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M)
+
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_misc_init(void)
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
+
+    // Enable some peripherals' clocks.
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
+
+    // Disable MPU
+    mpu_p->cesr = 0;
+}
+
+#ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
+
+// FlexBus
+
+static const cyg_uint32 const flexbus_pins[] = {
+    CYGHWR_KINETIS_FB_PIN_CLKOUT_OFF,
+
+    CYGHWR_KINETIS_FB_PIN_CS0,
+    CYGHWR_KINETIS_FB_PIN_OE,
+    CYGHWR_KINETIS_FB_PIN_RW,
+# if 0 //(CYGHWR_HAL_KINETIS_FB_CS_CR(0) & CYGHWR_HAL_FB_CSCR_BLS_M)
+    CYGHWR_KINETIS_FB_PIN_BLS7_0,
+    CYGHWR_KINETIS_FB_PIN_BLS15_8,
+# else
+    CYGHWR_KINETIS_FB_PIN_BE23_16,
+    CYGHWR_KINETIS_FB_PIN_BE31_24,
+# endif
+    CYGHWR_KINETIS_FB_PIN_TS,
+
+    CYGHWR_KINETIS_FB_PIN_AD0,
+    CYGHWR_KINETIS_FB_PIN_AD1,
+    CYGHWR_KINETIS_FB_PIN_AD2,
+    CYGHWR_KINETIS_FB_PIN_AD3,
+    CYGHWR_KINETIS_FB_PIN_AD4,
+    CYGHWR_KINETIS_FB_PIN_AD5,
+    CYGHWR_KINETIS_FB_PIN_AD6,
+    CYGHWR_KINETIS_FB_PIN_AD7,
+    CYGHWR_KINETIS_FB_PIN_AD8,
+    CYGHWR_KINETIS_FB_PIN_AD9,
+    CYGHWR_KINETIS_FB_PIN_AD10,
+    CYGHWR_KINETIS_FB_PIN_AD11,
+    CYGHWR_KINETIS_FB_PIN_AD12,
+    CYGHWR_KINETIS_FB_PIN_AD13,
+    CYGHWR_KINETIS_FB_PIN_AD14,
+    CYGHWR_KINETIS_FB_PIN_AD15,
+    CYGHWR_KINETIS_FB_PIN_AD16,
+    CYGHWR_KINETIS_FB_PIN_AD17
+# if CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00040000
+    ,
+    CYGHWR_KINETIS_FB_PIN_AD18,
+    CYGHWR_KINETIS_FB_PIN_AD19,
+    CYGHWR_KINETIS_FB_PIN_AD20,
+    CYGHWR_KINETIS_FB_PIN_AD21
+#  if CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00400000
+    ,
+    CYGHWR_KINETIS_FB_PIN_AD22,
+    CYGHWR_KINETIS_FB_PIN_AD23
+#   if 0 //!(CYGHWR_HAL_KINETIS_FB_CS_CR(0) & CYGHWR_HAL_FB_CSCR_BLS_M)
+    ,
+    CYGHWR_KINETIS_FB_PIN_AD24,
+    CYGHWR_KINETIS_FB_PIN_AD25,
+    CYGHWR_KINETIS_FB_PIN_AD26,
+    CYGHWR_KINETIS_FB_PIN_AD27,
+    CYGHWR_KINETIS_FB_PIN_AD28,
+    CYGHWR_KINETIS_FB_PIN_AD29,
+    CYGHWR_KINETIS_FB_PIN_AD30,
+    CYGHWR_KINETIS_FB_PIN_AD31
+#   endif
+#  endif  // CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00400000
+# endif // CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00040000
+};
+
+static const cyg_uint32 const flexbus_pins_final_diff[] = {
+    CYGHWR_KINETIS_FB_PIN_CLKOUT
+};
+
+// Initialize FlexBus for use until we have main clock.
+// Asynchronous mode.
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_flexbus_init_initial(void)
+{
+    cyghwr_hal_kinetis_fb_t *fb_p = CYGHWR_HAL_KINETIS_FB_P;
+
+    CYGHWR_IO_CLOCK_ENABLE(CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXBUS);
+
+# ifdef CYGHWR_HAL_KINETIS_FB_CS0
+    fb_p->csel[0] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS0_AR,
+              CYGHWR_HAL_KINETIS_FB_CS0_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(0) };
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS1
+    fb_p->csel[1] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS1_AR,
+              CYGHWR_HAL_KINETIS_FB_CS1_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(1) };
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS2
+    fb_p->csel[2] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS2_AR,
+              CYGHWR_HAL_KINETIS_FB_CS2_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(2) };
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS3
+    fb_p->csel[3] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS3_AR,
+              CYGHWR_HAL_KINETIS_FB_CS3_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(3) };
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS4
+    fb_p->csel[4] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS4_AR,
+              CYGHWR_HAL_KINETIS_FB_CS4_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(4) };
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS4
+    fb_p->csel[5] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS5_AR,
+              CYGHWR_HAL_KINETIS_FB_CS5_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(5) };
+# endif
+
+    fb_p->cspmcr = CYGHWR_HAL_FB_CSPMCR_SETSEL;
+
+    HAL_SET_PINS(flexbus_pins);
+}
+
+// Initialize FlexBus to it's normal working condition
+// Synchronous mode with burst support
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_flexbus_init_final(void)
+{
+    cyghwr_hal_kinetis_fb_t *fb_p = CYGHWR_HAL_KINETIS_FB_P;
+
+    // Enable RAM synchronous/burst mode
+    ram_micron_reg_set(CYGHWR_DEVS_RAM_MICRON_BCR,
+                           CYGHWR_RAM0_MICRON_BCR_SETTO,
+                           (cyg_uint16 *)CYGHWR_HAL_KINETIS_FB_CS0_AR,
+                       CYGHWR_RAM0_MICRON_CELLULAR_SIZE);
+
+    // Apply FlexBus clock...
+    HAL_SET_PINS(flexbus_pins_final_diff);
+
+    // ...and final CS setting for burst, etc.
+# ifdef CYGHWR_HAL_KINETIS_FB_CS0
+    fb_p->csel[0].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(0);
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS1
+    fb_p->csel[1].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(1);
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS2
+    fb_p->csel[2].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(2);
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS3
+    fb_p->csel[3].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(3);
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS4
+    fb_p->csel[4].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(4);
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS5
+    fb_p->csel[5].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(5);
+# endif
+}
+
+#endif // CYGHWR_HAL_CORTEXM_KINETIS_FLEXBUS
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+    { CYGMEM_REGION_ram,        CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1        }, // System bus RAM partition
+#if 1 //def CYGMEM_REGION_sram
+    { CYGMEM_REGION_sram,       CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1      }, // On-chip SRAM
+#elif defined CYGMEM_REGION_sram_l
+    { CYGMEM_REGION_sram_l,     CYGMEM_REGION_sram_l+CYGMEM_REGION_sram_l_SIZE-1  }, // On-chip SRAM lower bank
+#endif
+#ifdef CYGMEM_REGION_ramcod
+    { CYGMEM_REGION_ramcod,      CYGMEM_REGION_ramcod+CYGMEM_REGION_ramcod_SIZE-1 }, // Code bus RAM partition
+#endif
+#ifdef CYGMEM_REGION_ramnc
+    { CYGMEM_REGION_ramnc,      CYGMEM_REGION_ramnc+CYGMEM_REGION_ramnc_SIZE-1    }, // Non cachable RAM partition
+#endif
+#ifdef CYGMEM_REGION_flash
+    { CYGMEM_REGION_flash,      CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1    }, // On-chip flash
+#endif
+#ifdef CYGMEM_REGION_rom
+    { CYGMEM_REGION_rom,        CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1        }, // External flash [currently none]
+#endif
+    { 0xE0000000,               0x00000000-1                                      }, // Cortex-M peripherals
+    { 0x40000000,               0x60000000-1                                      }  // Chip specific peripherals
+};
+
+__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) {
+        if( ((CYG_ADDRESS)addr >= hal_data_access[i].start) &&
+            ((CYG_ADDRESS)addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the on-chip SRAM and external RAM.
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_sram
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_sram;
+        *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
+        break;
+#endif
+#ifdef CYGMEM_REGION_sram_l
+# define CASE_CODE 3
+# define CASE_RAMNC 4
+    case 2:
+        *start = (unsigned char *)CYGMEM_REGION_sram_l;
+        *end = (unsigned char *)(CYGMEM_REGION_sram_l + CYGMEM_REGION_sram_l_SIZE);
+        break;
+#else
+# define CASE_CODE 2
+# define CASE_RAMNC 3
+#endif
+
+#ifdef CYGMEM_REGION_ramcod
+    case CASE_CODE:
+        *start = (unsigned char *)CYGMEM_REGION_ramcod;
+        *end = (unsigned char *)(CYGMEM_REGION_ramcod + CYGMEM_REGION_ramcod_SIZE);
+        break;
+#endif
+
+#ifdef CYGMEM_REGION_ramnc
+    case CASE_RAMNC:
+        *start = (unsigned char *)CYGMEM_REGION_ramnc;
+        *end = (unsigned char *)(CYGMEM_REGION_ramnc + CYGMEM_REGION_ramnc_SIZE);
+        break;
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+} // cyg_plf_memory_segment()
+
+#endif // CYGPKG_REDBOOT
+
+//==========================================================================
+// EOF twr_k60n512_fxm_misc.c
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog b/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog
@@ -0,0 +1,110 @@
+2013-04-09  Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
+
+	Add requirement for WRITETHRU data cache startup mode when eDMA is in use.
+	Sync with change in eDMA driver [ Bugzilla 1001838 ]
+
+2013-04-09  Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
+	* include/plf_io.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k70f120m_misc.c: Clock gating synchronised with variant.
+	[ Bugzilla 1001814 ]
+
+2013-03-09  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* misc/redboot_K70_ROM_FPU.ecm: Add ECM file
+
+2012-11-30  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: Sync with variant changes due to
+	hardware floating point support. Implements CYGINT_HAL_FPV4_SP_D16.
+	Changed maximum peripheral bus clocks to 75MHz.
+	[Bugzilla 1001607]
+
+2012-11-04  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi:
+	Recognize 256 Bytes space for virtual vectors in sram.
+
+	* twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
+	Add settings for Kinetis internal flash.  [Bugzilla 1001561]
+
+2012-09-28  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h
+	* current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi
+	* current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h
+	* current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi
+	* src/twr_k70f120m_misc.c:
+	Synchronized with Kinetis variant changes to SDRAM controller support.
+	Memory layouts adapted to separate data and code cacing partitions.
+	                                            [Bugzilla 1001606]
+
+2012-05-19  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: Reference per-package
+	documentation.
+
+2012-05-18  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* doc/twr_k70f120m.sgml:
+	New file -- TWR-K70F120M platform documentation. [Bug 1001580]
+
+2012-05-17  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
+	Bug fix: Do not implement external memory interface if Platform startup is
+	not selected. [ Bugzilla 1001590 ]
+
+2012-02-25  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h:
+	* pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi:
+	* pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h:
+	* pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi:
+	* pkgconf/mlt_kinetis_flash_unisram_extram_ram.h:
+	* pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi:
+	* pkgconf/mlt_kinetis_flash_unisram_extram_rom.h:
+	* pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi:
+	* src/twr_k70f120m_misc.c:	
+	New package -- Freescale TWR-K70F120M board. [Bugzilla 1001579]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl b/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl
@@ -0,0 +1,444 @@
+##==========================================================================
+##
+##      hal_cortexm_kinetis_twr_k70f120m.cdl
+##
+##      Cortex-M Freescale TWR-K70F120M platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2012 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2012-02-25
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K70F120M {
+    display       "Freescale Kinetis TWR-K70F120M Platform"
+    parent        CYGPKG_HAL_CORTEXM_KINETIS
+    define_header hal_cortexm_kinetis_twr_k70f120m.h
+    include_dir   cyg/hal
+    doc           ref/kinetis-twr-k70f120m.html
+    hardware
+    description   "
+        The Freescale TWR K70F120M Platform HAL package provides the support
+        needed to run eCos on the TWR K70F120M development system. This package
+        can also be used for other boards that employ a controller from Kinetis
+        families."
+
+    compile       twr_k70f120m_misc.c
+
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+    requires      { is_active(CYGPKG_DEVS_ETH_FREESCALE_ENET)
+                  implies CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" }
+
+    implements    CYGINT_HAL_CACHE
+
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FPU_DEFAULT == "F" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM_DEFAULT == 70 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 30 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 40 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 50 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == "1M0" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 }
+    requires      { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies
+                    CYGNUM_DEVS_KINETIS_FLASH_BLOCK_SIZE == 0x1000 }
+    requires      { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies
+                    CYGNUM_DEVS_KINETIS_FLASH_LONGWORD_SIZE == 8 }
+
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART2
+    implements    CYGINT_IO_FREESCALE_I2C0
+    
+    implements    CYGINT_HAL_FREESCALE_UART2
+    implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
+    
+    implements    CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+    implements    CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1
+    implements    CYGINT_HAL_CORTEXM_KINETIS_150
+
+    requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX == 75000000 }
+    requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX == 75000000 }
+    requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX == 25000000 }
+
+    requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
+        (1 == CYGHWR_DEVS_ETH_PHY_KSZ8041) }
+    requires      { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies
+        (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 32) }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Freescale TWR-K70F120M\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+        puts $::cdl_system_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 4000000"
+    }
+
+    cdl_component CYG_HAL_STARTUP_ENV {
+        display "Startup type"
+        flavor data
+        no_define
+        calculated {
+            !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP :
+            ((CYG_HAL_STARTUP_PLF == "ByVariant") ?
+            (CYG_HAL_STARTUP . "(Variant)") :
+            (CYG_HAL_STARTUP . "(Platform)"))
+        }
+        description "
+            Startup type configuration defines the system memory layout.
+            Startup type  can be defined by the variant (CYG_HAL_STARTUP_VAR)
+            or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_option CYG_HAL_STARTUP_PLF {
+        display       "By platform"
+        flavor        data
+        parent        CYG_HAL_STARTUP_ENV
+        default_value { "ROM" }
+        legal_values  { "ByVariant" "ROM" "RAM" }
+
+        requires      { CYG_HAL_STARTUP_PLF != "ByVariant" implies
+                        CYGPKG_HAL_CORTEXM_KINETIS_DDRMC == 1 }
+
+        description   "
+            Startup tupes provided by the platform, in addition to variant
+            startup types.
+            If 'ByVariant' is selected, then startup type shall be selected
+            from the variant (CYG_HAL_STARTUP_VAR). Platform's 'ROM' startup
+            builds application similar to Variant's 'ROM' but using external
+            RAM (DDRAM). 'RAM' startup builds application intended for loading
+            by RedBoot into external RAM."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT_PLF {
+        display "Memory layout by platform"
+        flavor data
+        active_if { CYG_HAL_STARTUP_PLF != "ByVariant" }
+        implements CYGINT_HAL_CORTEXM_KINETIS_DDRAM
+        no_define
+        parent  CYGHWR_MEMORY_LAYOUT
+        calculated {
+            (CYG_HAL_STARTUP_PLF == "ByVariant" ) ? "by variant" :
+            (CYG_HAL_STARTUP == "RAM") ? "kinetis_"
+            . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_extram_ram" :
+            (CYG_HAL_STARTUP == "ROM") ? "kinetis_"
+            . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_extram_rom" :
+            "Error!"
+        }
+        description "
+            Combination of 'Startup type' and 'Kinetis member in use'
+            produces the memory layout."
+
+        cdl_option CYGHWR_MEMORY_RAM_RESERVED {
+            display "Reserved RAM space \[Bytes\]"
+            flavor  data
+            legal_values 0 to 0x40000
+            default_value 0x20000
+        }
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP {
+        display "Platform suggested system frequency setpoint"
+        flavor data
+        no_define
+        legal_values 96000000 100000000 120000000 150000000 200000000
+        default_value 120000000
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP {
+        display "Platform suggested auxiliary frequency setpoint"
+        flavor data
+        no_define
+        legal_values 96000000 100000000 120000000 150000000 200000000
+        default_value 120000000
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ {
+        display "Platgorm XTAL/OSC Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" ||
+                   CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        default_value 50000000
+        legal_values { 12000000 50000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ {
+        display "Platform XTAL1/OSC1 Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "OSC" ||
+                   CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" }
+        default_value 50000000
+        legal_values { 12000000 50000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP {
+        display "Platform requred XTAL || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC1_CAP {
+        display "Platform requred XTAL1 || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP == 20 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC {
+        display "Platform requred RTC XTAL || C \[pF\]"
+        flavor bool
+        default_value 0
+        parent CYGHWR_HAL_CORTEXM_KINETIS_RTC
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        legal_values 0 to 2
+        default_value   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR board has one serial port fitted to RS232 connector.
+            This option chooses which port will be used to connect to a host
+            running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display          "Diagnostic serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR has one serial port fitted to RS232 connector.
+            This option chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console port
+            if the console and GDB port are the same."
+    }
+
+    cdl_option CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK {
+        display "ENET MII MDC clock provided by HAL"
+        flavor data
+        active_if CYGPKG_DEVS_ETH_FREESCALE_ENET
+        parent CYGPKG_DEVS_ETH_FREESCALE_ENET
+        calculated CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS
+        description "
+            ENET needs a clock with typical frequency of up to 2.5 MHz for
+            MII MDC. The input clock, typically provided by HAL, is further
+            divided by ENET according to setting of ENET MSCR register in order to
+            provide frequency within 2.5 MHz range."
+     }
+
+    cdl_option CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT {
+        display "IEEE 1588 Port"
+        active_if CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        parent CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        flavor data
+        default_value { "B" }
+        legal_values { "B" "C" "User" }
+        description "
+            Digital I/O provided by HAL for ENET IEEE 1588 timers."
+    }
+
+    cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS {
+        display "MMC Disk SPI bus"
+        flavor data
+        parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+        calculated 1
+
+        requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1
+        implements CYGINT_DEVS_SPI_FREESCALE_DSPI1
+        implements CYGINT_FREESCALE_DSPI1_HAS_MASS
+        requires  { (is_active(CYGSEM_HAL_DCACHE_STARTUP_MODE)
+                    && CYGINT_DEVS_SPI_DSPI_DMA_USE)
+                    implies CYGSEM_HAL_DCACHE_STARTUP_MODE == "WRITETHRU" }
+
+        cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS {
+            display "Device number (CS)"
+            flavor data
+            legal_values { 0 1 2 3 4 5 }
+            default_value 0
+            implements CYGINT_FREESCALE_DSPI1_CS0
+            implements CYGINT_FREESCALE_DSPI1_CS1
+            implements CYGINT_FREESCALE_DSPI1_CS2
+            implements CYGINT_FREESCALE_DSPI1_CS3
+        }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+            Global build options including control over
+            compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+            Support can be enabled for different varieties of ROM monitor.
+            This support changes various eCos semantics such as the encoding
+            of diagnostic output, or the overriding of hardware interrupt
+            vectors.
+            Firstly there is \"Generic\" support which prevents the HAL
+            from overriding the hardware vectors that it does not use, to
+            instead allow an installed ROM monitor to handle them. This is
+            the most basic support which is likely to be common to most
+            implementations of ROM monitor.
+            \"GDB_stubs\" provides support when GDB stubs are included in
+            the ROM monitor or boot ROM."
+    }
+
+
+    cdl_component CYGBLD_HAL_CORTEXM_TWR_MK70F120M_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+
+        description "
+            This component causes the ELF image generated by the
+            build process to be converted to S-Record and binary
+            files."
+    }
+}
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml b/packages/hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml
@@ -0,0 +1,165 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     twr_k70f120m.sgml                                        -->
+<!--                                                                 -->
+<!--     TWR-K70F120M board documentation.                        -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2012 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2012/01/10                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<!--<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>-->
+
+<refentry id="kinetis-twr-k70f120m">
+  <refmeta>
+    <refentrytitle>TWR-K70F120M Development kit</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>CYGPKG_HAL_CORTEXM_KINETIS_TWR_K70F120M</refname>
+    <refpurpose>eCos Support for Freescale TWR-K70F120M development kit</refpurpose>
+  </refnamediv>
+  
+  <refsect1 id="kinetis-twr-k70f120m-description"><title>Description</title>
+    <para>
+    The Freescale TWR-K70F120M is a development kit for <link linkend="hal-cortexm-kinetis-var">
+    Freescale Kinetis</link> Cortex-M4 based micro-controllers. It covers K70, K60, K10 and K20
+    microcontroller subfamilies. K70FN1M0 is a high end member comprising on-chip 1 MiB FLASH
+    and 128 KiB SRAM memory as well as a 16 KiB unified cache.
+    K70 parts are equipped with a rich set of communication interfaces including Ethernet USB, UARTs
+    CAN, SPI and I2C. They also have a Graphics controller and a DMA controller, as well as FlexBus and SDRAM
+    external memory interfaces. They are mixed signal devices featuring a 16 bit ADC and a 12 bit DAC. 
+    </para>
+  </refsect1>
+  <refsect1 id="kinetis-twr-k70f120m-config"><title>Configuration</title>
+    <refsect2 id="kinetis-twr-k70f120m-config-hardware"><title>Hardware Setup</title>
+      <refsect3 id="kinetis-twr-k70f120m-config-hardware-cpu"><title>TWR-K70F120M setup</title>
+      <para>
+      Factory jumper settings on TWR-K70F120M are fitted for standalone operation of the board.
+      In order to use it with the Ethernet PHY from TWR-SER, some jumpers have to be changed
+      on both TWR-K70F120M and TWR-SER. Jumper settings for TWR-SER are given in
+      <link linkend="kinetis-twr-k60n512-config">TWR-K60N512 Configuration</link> and here are the TWR-K70F120M
+      settings.
+      </para>
+      <table frame="all"><title>TWR-K70F120M Jumper setting</title>
+        <tgroup cols="3" align="center">
+          <colspec colnum="1" colname="jumper" colwidth="1*" >
+          <colspec colnum="2" colname="jumpset" colwidth="1*" >
+          <colspec colnum="3" colname="desc" colwidth="3*" >
+          <thead>
+            <row>
+              <entry>Jumper</entry>
+              <entry>Setting</entry>
+              <entry>Description</entry>
+            </row>
+          </thead>
+          <tbody>
+            <row>
+              <entry>J19</entry>
+              <entry>OFF</entry>
+              <entry>On board 50MHz oscillator is not powered</entry>
+            </row>
+          </tbody>
+        </tgroup>
+      </table>
+      </refsect3>
+    </refsect2>
+    <refsect2 id="kinetis-twr-k70f120m-config-ecos"><title>eCos Configuration</title>
+      <refsect3 id="twr-k70f120m-clocking"><title>Clocking</title>
+      <para>
+      The TWR-K70F120M package defines requirements for the platform clocking.
+      </para>
+      </refsect3>  
+      <refsect3 id="twr-k70f120m-memory"><title>Memory</title>
+      <para>
+      The K70 has two 64 KiB SRAM banks giving a total of 128KiB on chip SRAM. In addition, on-board there is
+      128 MiB of external RAM (SDRAM) and 256 MiB of NAND Flash.
+      External RAM is divided in two regions: 
+      </para>
+      <variablelist>
+        <varlistentry>
+          <term>ram</term>
+          <listitem><para> Regular RAM.</para></listitem>
+        </varlistentry>
+        <varlistentry>
+          <term>ramnc</term>
+          <listitem><para>Non cached RAM. This region contains <literal>.noncache</literal> section.</para></listitem>
+        </varlistentry>
+      </variablelist>
+      </refsect3>
+    </refsect2>
+    <refsect2 id="kinetis-twr-k70f120m-memory"><title>Memory layouts</title>
+      <para>
+      Additional platform memory layouts follow the <link linkend="kinetis-var-memory">variant</link>
+      ones only by putting all RAM sections except <literal>.sram</literal> in the <literal>ram</literal> region.
+      The linker file names incorporate the segment <filename>_extram_</filename>.
+      </para>
+      <refsect3 id="kinetis-twr-k70f120m-memory-ldscript-location"><title>Linker 
+      Script Location</title>
+      <para>
+      Linker scripts are found at:
+      <filename class="directory">hal/kinetis/twr-k70f120m/&lt;version&gt;/include/pkgconf</filename>
+      </para>
+      </refsect3>
+      <refsect3 id="kinetis-twr-k70f120m-memory-ldscript-naming"><title>Linker Script Naming</title>
+      <para>
+      Linker script file names have following form:
+      <filename>mlt_kinetis_&lt;NVM&gt;_&lt;SRAM&gt;_&lt;STARTUP_extram.ldi</filename>
+      where <filename>PLF</filename> is an optional extension for platform specific scripts and
+      other segments have meaning as described <link linkend="kinetis-var-table-ldscript-naming">here</link>.
+      </para>
+      </refsect3>
+    </refsect2>
+    <refsect2 id="kinetis-twr-k70f120m-startup"><title>Startup types</title>
+      <para>
+      The platform startup <literal>CYG_HAL_STARTUP_PLF</literal> offers the following startups:
+      </para>
+      <variablelist>
+        <varlistentry>
+          <term><literal>ROM (Platform)</literal></term>
+          <listitem><para>Normal startup for stand-alone operation. The eCos image has to be flashed
+            in internal flash. External RAM is used as main memory.
+            </para>
+            <para>
+            Note: This startup has a name like the one in the variant but generates different images 
+            by invoking a different set of linker scripts.
+            </para></listitem></varlistentry>
+        <varlistentry>
+          <term><literal>RAM (Platform)</literal></term>
+          <listitem><para>The image is loaded in external RAM by means of RedBoot.
+            </para></listitem></varlistentry>
+        <varlistentry>
+          <term><literal>ByVariant</literal></term>
+          <listitem><para>Activates the <link linkend="kinetis-var-startup">variant startup types</link>.
+            </para></listitem></varlistentry>
+      </variablelist>
+    </refsect2>
+  </refsect1>
+</refentry>
+
+<!--</part>-->
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h
@@ -0,0 +1,32 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
@@ -0,0 +1,41 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE
+    sram   : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000000, LMA_EQ_VMA)
+    SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LMA_EQ_VMA)
+    SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE+CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
+
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h
@@ -0,0 +1,40 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+//#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_BASE)
+//#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE)
+//#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi
@@ -0,0 +1,49 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE
+    sram   : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000000, FOLLOWING (.got))
+    SECTION_data (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h
@@ -0,0 +1,28 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
@@ -0,0 +1,39 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+
+MEMORY
+{
+    sram   : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA)
+    SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LMA_EQ_VMA)
+    SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE + CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h
@@ -0,0 +1,32 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi
@@ -0,0 +1,47 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram   : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got))
+    SECTION_data (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_arch.h b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_arch.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Contributor(s):
+// Date:        2012-02-15
+// Purpose:     TWR-K70F120M platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_intr.h b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_intr.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2012-02-25
+// Purpose:     TWR-K70F120M platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h
@@ -0,0 +1,171 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2012-02-25
+// Purpose:     TWR-K70F120M platform specific registers
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h>
+
+
+// UART PINs
+#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(C, 16, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(C, 17, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_FREESCALE_UART3_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_FREESCALE_UART3_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_FREESCALE_UART3_PIN_CTS
+#endif
+
+#ifndef CYGHWR_HAL_FREESCALE_UART2_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART2_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 17, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART2_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 16, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART2_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART2_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# define CYGHWR_IO_FREESCALE_UART2_PIN_RX CYGHWR_HAL_FREESCALE_UART2_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART2_PIN_TX CYGHWR_HAL_FREESCALE_UART2_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART2_PIN_RTS CYGHWR_HAL_FREESCALE_UART2_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART2_PIN_CTS CYGHWR_HAL_FREESCALE_UART2_PIN_CTS
+#endif
+
+// ENET PINs
+
+// MDIO
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDIO    CYGHWR_HAL_KINETIS_PIN(B, 0, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDC     CYGHWR_HAL_KINETIS_PIN(B, 1, 4, 0)
+// Both RMII and MII interface
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXER    CYGHWR_HAL_KINETIS_PIN(A, 5, 4, \
+                                                    CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD1    CYGHWR_HAL_KINETIS_PIN(A, 12, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD0    CYGHWR_HAL_KINETIS_PIN(A, 13, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXEN    CYGHWR_HAL_KINETIS_PIN(A, 15, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD0    CYGHWR_HAL_KINETIS_PIN(A, 16, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD1    CYGHWR_HAL_KINETIS_PIN(A, 17, 4, 0)
+// RMII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_CRS_DV  CYGHWR_HAL_KINETIS_PIN(A, 14, 4, 0)
+// MII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD3     CYGHWR_HAL_KINETIS_PIN(A, 9, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD2     CYGHWR_HAL_KINETIS_PIN(A, 10, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXCLK    CYGHWR_HAL_KINETIS_PIN(A, 11, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD2     CYGHWR_HAL_KINETIS_PIN(A, 24, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXCLK    CYGHWR_HAL_KINETIS_PIN(A, 25, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD3     CYGHWR_HAL_KINETIS_PIN(A, 26, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_CRS      CYGHWR_HAL_KINETIS_PIN(A, 27, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MIIO_TXER     CYGHWR_HAL_KINETIS_PIN(A, 28, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_COL      CYGHWR_HAL_KINETIS_PIN(A, 29, 4, 0)
+// IEEE 1588 timers
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_1588_CLKIN    CYGHWR_HAL_KINETIS_PIN(E, 26, 4, 0)
+
+#if defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_B)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(B, 2, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(B, 3, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(B, 4, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(B, 5, 4, 0)
+#elif defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_C)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(C, 16, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(C, 17, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(C, 18, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(C, 19, 4, 0)
+#endif
+
+// DSPI
+// DSPI Pins
+
+#define KINETIS_PIN_SPI1_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M | \
+                                  CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+#define KINETIS_PIN_SPI1_SCK_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M)
+#define KINETIS_PIN_SPI1_CS_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M | \
+                                  CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+
+#define KINETIS_PIN_SPI1_IN_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+#define KINETIS_PIN_SPI1_0_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN  CYGHWR_HAL_KINETIS_PIN(E, 1, 7, KINETIS_PIN_SPI1_IN_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 3, 7, KINETIS_PIN_SPI1_OUT_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK  CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_SCK_OPT)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0  CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1  CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2  CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3  CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4  CYGHWR_HAL_KINETIS_PIN_NONE
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5  CYGHWR_HAL_KINETIS_PIN_NONE
+
+// I2C
+// I2C Pins
+
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(E, 18, 4, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(E, 19, 4, 0)
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
+
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/misc/redboot_K70_ROM_FPU.ecm b/packages/hal/cortexm/kinetis/twr_k70f120m/current/misc/redboot_K70_ROM_FPU.ecm
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/misc/redboot_K70_ROM_FPU.ecm
@@ -0,0 +1,83 @@
+# Redboot minimal configuration
+# Target: TWR-K70F120M
+# Startup: ROM with external RAM
+
+
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "RedBoot Kinetis TWR-K70F120M" ;
+    package CYGPKG_IO_FLASH current ;
+    package CYGPKG_IO_ETH_DRIVERS current ;
+};
+
+cdl_option CYGHWR_HAL_CORTEXM_FPU {
+    user_value 1
+};
+
+cdl_option CYGHWR_HAL_CORTEXM_FPU_SWITCH {
+    user_value ALL
+};
+
+cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
+    user_value 1
+};
+
+cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP {
+    user_value 1
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 0
+};
+
+#cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH {
+#    user_value 1
+#};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+    user_value -1
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK {
+    user_value -2
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT {
+    user_value 16
+};
+
+#cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE {
+#    user_value 0x20000
+#};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+    user_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+    user_value ROM
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    user_value 1
+};
+
+cdl_component CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA {
+    user_value 1
+};
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c b/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c
@@ -0,0 +1,316 @@
+//==========================================================================
+//
+//      twr_k70f120m_misc.c
+//
+//      Cortex-M4 TWR-K60N512 EVAL HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2012-02-25
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+static inline void hal_misc_init(void);
+
+// DATA and BSS locations
+__externC cyg_uint32 __ram_data_start;
+__externC cyg_uint32 __ram_data_end;
+__externC cyg_uint32 __rom_data_start;
+__externC cyg_uint32 __sram_data_start;
+__externC cyg_uint32 __sram_data_end;
+__externC cyg_uint32 __srom_data_start;
+__externC cyg_uint32 __bss_start;
+__externC cyg_uint32 __bss_end;
+
+#ifdef CYGHWR_HAL_DDR_SYNC_MODE
+#define SYNC_ASYNC 0x3
+#else
+#define SYNC_ASYNC 0
+#endif
+
+#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC
+
+// DDRAM controller setup parameters
+const cyg_uint32 kinetis_ddr_cfg[] = {
+    0x00000400,  // DDR_CR00
+    0x02000031,  // DDR_CR02
+    0x02020506,  // DDR_CR03
+    0x06090202,  // DDR_CR04
+    0x02020302,  // DDR_CR05
+    0x02904002,  // DDR_CR06
+    0x01000303,  // DDR_CR07
+    0x05030201,  // DDR_CR08
+    0x020000c8,  // DDR_CR09
+    0x03003207,  // DDR_CR10
+    0x01000000,  // DDR_CR11
+    0x04920031,  // DDR_CR12
+    0x00000005,  // DDR_CR13
+    0x00C80002,  // DDR_CR14
+    0x00000032,  // DDR_CR15
+    0x00000001,  // DDR_CR16
+    0x00030300,  // DDR_CR20
+    0x00040232,  // DDR_CR21
+    0x00000000,  // DDR_CR22
+    0x00040302,  // DDR_CR23
+    0x0A010201,  // DDR_CR25
+    0x0101FFFF,  // DDR_CR26
+    0x01010101,  // DDR_CR27
+    0x00000003,  // DDR_CR28
+    0x00000000,  // DDR_CR29
+    0x00000001,  // DDR_CR30
+    0x02020101,  // DDR_CR34
+    0x01010201,  // DDR_CR36
+    0x00000200,  // DDR_CR37
+    0x00200000,  // DDR_CR38
+    0x01010020,  // DDR_CR39
+    0x00002000 | SYNC_ASYNC,  // DDR_CR40
+    0x01010020,  // DDR_CR41
+    0x00002000 | SYNC_ASYNC,  // DDR_CR42
+    0x01010020,  // DDR_CR43
+    0x00000000 | SYNC_ASYNC,  // DDR_CR44
+    0x03030303,  // DDR_CR45
+    0x02006401,  // DDR_CR46
+    0x01020202,  // DDR_CR47
+    0x01010064,  // DDR_CR48
+    0x00020101,  // DDR_CR49
+    0x00000064,  // DDR_CR50
+    0x02000602,  // DDR_CR52
+    0x03c80000,  // DDR_CR53
+    0x03c803c8,  // DDR_CR54
+    0x03c803c8,  // DDR_CR55
+    0x020303c8,  // DDR_CR56
+    0x01010002   // DDR_CR57
+};
+#endif // CYGPKG_HAL_CORTEXM_KINETIS_DDRMC
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_system_init( void )
+{
+#if !defined(CYG_HAL_STARTUP_RAM)
+    cyghwr_hal_kinetis_pmc_t *pmc_p = CYGHWR_HAL_KINETIS_PMC_P;
+
+    hal_wdog_disable();
+    hal_misc_init();
+
+    // if ACKISO is set you must clear ackiso before calling pll_init
+    //    or pll init hangs waiting for OSC to initialize
+    if(pmc_p->regsc & CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M)
+        pmc_p->regsc |= CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M;
+
+    hal_start_clocks();
+# ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC
+    HAL_CORTEXM_KINETIS_DDRMC_INIT( kinetis_ddr_cfg );
+# endif // CYGPKG_HAL_CORTEXM_KINETIS_DDRMC
+#endif
+}
+
+//===========================================================================
+// hal_misc_init
+//===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M)
+
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_misc_init(void)
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
+
+    // Enable some peripherals' clocks.
+    sim_p->scgc1 |= CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_M;
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
+
+    // Disable MPU
+    mpu_p->cesr = 0;
+}
+
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+    { CYGMEM_REGION_ram,        CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1        }, // System bus RAM partition
+#ifdef CYGMEM_REGION_sram
+    { CYGMEM_REGION_sram,       CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1      }, // On-chip SRAM
+#elif defined CYGMEM_REGION_sram_l
+    { CYGMEM_REGION_sram_l,     CYGMEM_REGION_sram_l+CYGMEM_REGION_sram_l_SIZE-1  }, // On-chip SRAM lower bank
+#endif
+#ifdef CYGMEM_REGION_ramcod
+    { CYGMEM_REGION_ramcod,      CYGMEM_REGION_ramcod+CYGMEM_REGION_ramcod_SIZE-1 }, // Code bus RAM partition
+#endif
+#ifdef CYGMEM_REGION_ramnc
+    { CYGMEM_REGION_ramnc,      CYGMEM_REGION_ramnc+CYGMEM_REGION_ramnc_SIZE-1    }, // Non cachable RAM partition
+#endif
+#ifdef CYGMEM_REGION_flash
+    { CYGMEM_REGION_flash,      CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1    }, // On-chip flash
+#endif
+#ifdef CYGMEM_REGION_rom
+    { CYGMEM_REGION_rom,        CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1        }, // External flash [currently none]
+#endif
+    { 0xE0000000,               0x00000000-1                                      }, // Cortex-M peripherals
+    { 0x40000000,               0x60000000-1                                      }  // Chip specific peripherals
+};
+
+__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) {
+        if( ((CYG_ADDRESS)addr >= hal_data_access[i].start) &&
+            ((CYG_ADDRESS)addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the on-chip SRAM and external SRAM.
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_sram
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_sram;
+        *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
+        break;
+#endif
+#ifdef CYGMEM_REGION_sram_l
+# define CASE_CODE 3
+# define CASE_RAMNC 4
+    case 2:
+        *start = (unsigned char *)CYGMEM_REGION_sram_l;
+        *end = (unsigned char *)(CYGMEM_REGION_sram_l + CYGMEM_REGION_sram_l_SIZE);
+        break;
+#else
+# define CASE_CODE 2
+# define CASE_RAMNC 3
+#endif
+
+#ifdef CYGMEM_REGION_ramcod
+    case CASE_CODE:
+        *start = (unsigned char *)CYGMEM_REGION_ramcod;
+        *end = (unsigned char *)(CYGMEM_REGION_ramcod + CYGMEM_REGION_ramcod_SIZE);
+        break;
+#endif
+
+#ifdef CYGMEM_REGION_ramnc
+    case CASE_RAMNC:
+        *start = (unsigned char *)CYGMEM_REGION_ramnc;
+        *end = (unsigned char *)(CYGMEM_REGION_ramnc + CYGMEM_REGION_ramnc_SIZE);
+        break;
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+} // cyg_plf_memory_segment()
+
+#endif // CYGPKG_REDBOOT
+
+//==========================================================================
+// EOF twr_k70f120m_misc.c
diff --git a/packages/hal/cortexm/kinetis/var/current/ChangeLog b/packages/hal/cortexm/kinetis/var/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/ChangeLog
@@ -0,0 +1,215 @@
+2014-05-05  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis.cdl:
+	* include/var_io_gpio.h:
+	* src/kinetis_gpio.c:    New
+	Add functions for Kinetis GPIO pin configuration and manipulation.
+	[ Bugzilla 1001981 ]
+
+2014-02-13  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cortexm/kinetis/var/current/include/var_intr.h:
+	Add interrupt numbers for second eDMA controller.
+
+	* cortexm/kinetis/var/current/include/var_io_clkgat.h:
+	Add clock gating for ADC2
+
+	* cortexm/kinetis/var/current/include/var_io_gpio.h:
+	Add GPIO port F.
+
+2013-04-28  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/var_intr.h : Redefine CYGNUM_HAL_INTERRUPT_RTC_RTC because of
+	conflict with same named macro defined in hal_intr.h (Cortex-M architecture).
+	Define some interrrupt numbers, previously reservrd.
+	* include/var_io.h : Upgrade RTC registers. [ Bugzilla 1001904 ]
+
+2013-06-12 Mike Jones <mike@proclivis.com>
+
+	* include/var_io_gpio.h
+	Clean up macros to support interrupts and set/get features.
+	
+2013-04-28  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis.cdl: 
+	* cdl/kinetis_ddram.cdl: (New file)
+	* cdl/kinetis_fbram.cdl: (New file)
+	Add FlexBus RAM configuration and caching, DDRAM CDL moved
+	to a separate file. Updated FlexNVM configuration with 512KiB FlexNVM
+	and 16KiB FlexMemory.
+	* cdl/kinetis_clocking.cdl: CYGINT_HAL_CORTEXM_KINETIS_150
+	moved to hal_cortexm_kinetis.cdl
+	* include/var_io_lmem.h, include/hal_cache.h: Add more cache functions.
+	[ Bugzilla 1001837 ]
+	
+2013-04-09  Tomas Frydrych <tomas@sleepfive.com>
+
+	* cdl/kinetis_irq_scheme.cdl:
+	* include/var_io_devs.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/var_io.h, include/var_io_clkgat.h, include/var_io_devs.h,
+	* src/hal_diag.c, src/kinetis_ddram.c, src/kinetis_misc.c
+	Add clock gating management and API. [ Bugzilla 1001814 ]
+
+2012-11-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis.cdl: Changes to Kinetis part builder related to
+	addition of archhitectural hardware floating point support.
+	CYGHWR_HAL_CORTEXM_KINETIS_FPU and CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM
+	look and feel like other name building options. Added new Kinetis
+	members to part selection.
+	* include/var_io.h, src/kinetis_misc.c: Enumerated PORT F.
+	[Bugzilla 1001607]
+
+2012-11-04  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/var_io.h: Define register access to FTFL module. 
+	Contributed by Nicolas Aujoux at 2012-09-07 [Bugzilla 1001561]
+
+2012-09-28  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* var/current/cdl/hal_cortexm_kinetis.cdl
+	* var/current/cdl/kinetis_clocking.cdl
+	* var/current/doc/kinetis.sgml
+	* var/current/include/hal_cache.h
+	* var/current/include/var_io_ddrmc.h
+	* var/current/include/var_io_lmem.h
+	* var/current/src/kinetis_ddram.c
+	* var/current/src/kinetis_misc.c:
+	Separate data and code caches, as well as text indentation suggested by Jifl.
+	Fixes to cache and SDRAM CDL and functions Improved SDRAM controller
+	support due to better manufacturer documentation: Configurable pad control.
+	                                           [Bugzilla 1001606]
+
+2012-08-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/var_io.h, src/kinetis_misc.c: Add functions and macros
+	for clock gating control to Kinetis.       [Bugzilla 1001642]
+
+2012-05-18  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/hal_cache.h, src/kinetis_misc.c: Provide for cache
+	enablement in RAM startup mode            [Bugzilla 1001606]
+
+2012-05-19  John Dallaway  <john@dallaway.org.uk>
+
+	* doc/kinetis.sgml: Close <para> and <refsect2> blocks.
+	* cdl/hal_cortexm_kinetis.cdl: Reference per-package documentation.
+
+2012-05-18  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* doc/kinetis_begin.sgml:
+	* doc/kinetis_end.sgml:
+	* doc/kinetis.sgml:
+	New files -- Kinetis variant documentation. [Bug 1001580]
+
+2012-05-17  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis.cdl:
+	Bug fix: Do not refer external memory if Platform startup is
+	not selected.  [ Bugzilla 1001590 ]
+
+2012-05-04  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis.cdl:
+	* src/kinetis_clocking.cdl:
+	* src/kinetis_clocking.c:
+	* include/hal_cache.h
+	* include/var_io_lmem.h:
+	* include/var_io_ddrmc.h:
+	* include/var_io_devs.h:
+	* include/var_io.h:
+	* src/kinetis_ddram.c:
+	* src/kinetis_misc.c:
+	Add: Clocking support for PLL1 (K70), DDRAM controller
+	Cache, eDMA - 32 chan. [Bugzilla 1001579]
+
+2012-01-11  Tomas Frydrych <tomas@sleepfive.com>
+
+	* include/var_io.h:
+	Allow for overriding of CYGHWR_HAL_KINETIS_SIM_SCGC?_ALL_M mask
+	from platform definitions.
+
+	* include/var_io_devs.h:
+	Define base pointer for SLCD controller
+
+2012-01-05  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/kinetis_irq_scheme.cdl
+	Centralized IRQ priority scheme.
+
+	* cdl/hal_cortexm_kinetis.cdl:
+	* cdl/kinetis_flexbus.cdl
+	* include/var_io_devs.h:
+	* include/var_io.h:
+	* src/kinetis_clocking.c:
+	* src/kinetis_misc.c:
+	Add I/O defs for eDMA, DSPI. Add flexbus control.
+	CYG_HAL_STARTUP parenthed bt CYG_HAL_STARTUP_ENV.
+	Early clock start [Bugzilla 1001450]
+
+2011-11-15  Tomas Frydrych <tomas@sleepfive.com>
+
+	* include/var_io_gpio.h:
+	Convenience macros for manipulating GPIO pins.
+
+2011-10-19  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis.cdl:
+	* cdl/kinetis_clocking.cdl:
+	* src/hal_diag.c:
+	* src/kinetis_misc.c:
+	* src/kinetis_clocking.c:
+	* include/hal_cache.h:
+	* include/hal_diag.h:
+	* include/plf_stub.h:
+	* include/variant.inc:
+	* include/var_arch.h:
+	* include/var_intr.h:
+	* include/var_io.h:
+	* include/var_io_devs.h:
+	* include/var_io_flexbus.h:
+	* include/pkgconf/mlt_kinetis_flash_sram2s_rom.h
+	* include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi
+	* include/pkgconf/mlt_kinetis_flash_sram2s_sram.h
+	* include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi
+	* include/pkgconf/mlt_kinetis_flash_unisram_rom.h
+	* include/pkgconf/mlt_kinetis_flash_unisram_rom.ldi
+	* include/pkgconf/mlt_kinetis_flash_unisram_sram.h
+	* include/pkgconf/mlt_kinetis_flash_unisram_sram.ldi
+	* include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.h
+	* include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi
+	* include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.h
+	* include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi
+	* include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.h
+	* include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.ldi
+	* include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.h
+	* include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.ldi
+	New package -- Freescale Kinetis variant HAL.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011, 2012 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl b/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl
@@ -0,0 +1,867 @@
+##==========================================================================
+##
+##      hal_cortexm_kinetis.cdl
+##
+##      Cortex-M Freescale Kinetis variant HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2010-12-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_KINETIS {
+    display       "Freescale Kinetis Cortex-M4 Variant"
+    parent        CYGPKG_HAL_CORTEXM
+    doc           ref/hal-cortexm-kinetis-var.html
+    hardware
+    include_dir   cyg/hal
+    define_header hal_cortexm_kinetis.h
+    description   "
+        This package provides generic support for the Freescale Cortex-M4
+        based Kinetis microcontroller family.
+        It is also necessary to select a variant and platform HAL package."
+
+    compile       hal_diag.c kinetis_misc.c kinetis_clocking.c kinetis_gpio.c
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+    requires      { CYGHWR_HAL_CORTEXM == "M4" }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_kinetis.h>"
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS {
+        display          "Kinetis part"
+        flavor           data
+        calculated { "MK" . CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM .
+            CYGHWR_HAL_CORTEXM_KINETIS_FPU . CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM .
+            CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME }
+        description   "
+            Kinetis family has several sub-families, with various peripheral
+            sets and CPU options. Each sub-family consists of several
+            members differing by sizes of on-chip FLASH and SRAM. This
+            control, enables the user to build Kinetis member part and so
+            tailor HAL for a specific microcontroller by selection of
+            microcontroller's properties such as microcontroller sub-family,
+            memory options, etc."
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM {
+            display        "Sub-family"
+            flavor         data
+            no_define
+            default_value  { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM_DEFAULT }
+            legal_values   { 10 11 12 20 21 22 30 40 50 51 60 61 70 }
+            description    "
+                Kinetis family consists of several sub-families differing by
+                features and CPU power."
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM_DEFAULT {
+                display        "Default sub-family"
+                flavor         data
+                no_define
+                default_value  { 60 }
+                legal_values   { 10 11 12 20 21 22 30 40 50 51 60 61 70 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FPU {
+            display       "Floating Point Unit part name option"
+            flavor        data
+            no_define
+            legal_values  { "D" "F" }
+            default_value { CYGHWR_HAL_CORTEXM_KINETIS_FPU_DEFAULT }
+            description   "
+                Select whether the part has Floating Point Unit. \"F\" - stands for
+                parts with FPU, while \"D\" for ones without. Note:
+                Selection of part with FPU does not imply that the FPU is used -
+                CYGHWR_HAL_CORTEXM_FPU activates the FPU."
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FPU_DEFAULT {
+                display       "Default FPU part name option"
+                flavor        data
+                no_define
+                legal_values  { "D" "F" }
+                default_value { "D" }
+            }
+
+            cdl_option CYGIMP_HAL_CORTEXM_KINETIS_FPU {
+                display    "FPU implemented"
+                no_define
+                calculated { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "F" }
+                active_if  { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "F" }
+                implements CYGINT_HAL_FPV4_SP_D16
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM {
+            display        "FlexNVM name option"
+            flavor         data
+            no_define
+            legal_values   { "N" "X" }
+            default_value  { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT }
+            description    "Select whether the part has FlexNVM."
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT {
+                display        "Default FlexNVM name option"
+                flavor         data
+                no_define
+                legal_values   { "N" "X" }
+                default_value  { "N" }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME {
+            display        "Flash name segment"
+            flavor           data
+            no_define
+            legal_values   { 32 64 96 128 256 512 "1M0" }
+            default_value  { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT }
+            description    "
+                Flash size is represented in part name encoded as KiB
+                (e.g. 512) or MiB (e.g. 1M0)."
+
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT {
+                display        "Default Flash name segment"
+                flavor           data
+                no_define
+                legal_values   { 32 64 96 128 256 512 "1M0" }
+                default_value  { 512 }
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_REV {
+            display       "Kinetis revision"
+            flavor        data
+            legal_values  { 1 2 }
+            default_value 1
+            description " Revision"
+        }
+
+        cdl_interface CYGINT_HAL_CORTEXM_KINETIS_150 {
+            display       "Is a 150MHz device"
+            description   "
+                150Mhz and 120MHz devices have some properties different than 100MHz
+                devices of same types. This interface shall be implemented if the
+                device is 150Mhz or 120MHz."
+        }
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
+        display       "CPU exception priority level bits"
+        flavor        data
+        default_value 4
+        description   "
+            This option defines the number of bits used to encode the
+            exception priority levels that this variant of the Cortex-M
+            CPU implements."
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING {
+        display     "Clocking"
+        flavor      data
+        no_define
+        calculated  CYGHWR_HAL_CORTEXM_KINETIS_MCG
+        description "Configure system clock and subsystem clocking."
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP {
+            display      "System frequency clock setpoint"
+            flavor        data
+            legal_values  32768 to 220000000
+            default_value { CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP ?
+                CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP : 96000000 }
+            description "Desired system clock frequency"
+        }
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP {
+            display       "Auxiliary clock frequency setpoint"
+            flavor        data
+            active_if     CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+            legal_values  32768 to 220000000
+            default_value { CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP ?
+                            CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP : 96000000 }
+            description    "Desired auxiliary clock frequency"
+        }
+
+        script kinetis_clocking.cdl
+    }
+
+    cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
+        display       "Clock interrupt ISR priority"
+        flavor        data
+        calculated    CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP
+        description   "Set clock ISR priority. Default setting is lowest priority."
+    }
+
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+        no_define
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+        }
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR
+            description   "
+                The period defined here is something of a fake, it is
+                expressed in terms of a notional 1MHz clock. The value
+                actually installed in the hardware is calculated from
+                the current settings of the clock generation hardware."
+        }
+    }
+
+    cdl_option CYG_HAL_STARTUP_VAR {
+        display      "By variant"
+        flavor        data
+        parent        CYG_HAL_STARTUP_ENV
+        default_value { (CYG_HAL_STARTUP_PLF) && (CYG_HAL_STARTUP_PLF!="ByVariant") ?
+                        "ByPlatform" : "ROM" }
+        legal_values  { "ROM" "SRAM" }
+        active_if     ((!CYG_HAL_STARTUP_PLF) || (CYG_HAL_STARTUP_PLF=="ByVariant"))
+        description   "
+            'ROM' startup builds a stand-alone application which will
+            be placed into flash. SRAM startup builds application
+            intended for loading in on-chip SRAM by means of JTAG/SWD.
+            Note: Variant Startup Type can be overriden/overloaded by
+            Platform Startup Type."
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type calculator"
+        flavor        data
+        parent        CYG_HAL_STARTUP_ENV
+        calculated    { (CYG_HAL_STARTUP_PLF && (CYG_HAL_STARTUP_PLF!="ByVariant")) ?
+                        CYG_HAL_STARTUP_PLF : CYG_HAL_STARTUP_VAR}
+        no_define
+        define        -file system.h CYG_HAL_STARTUP
+        description   "
+            Startup type defines what type of application shall be built.
+            Startup type  can be defined by variant (CYG_HAL_STARTUP_VAR)
+            or platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_CONF {
+        display "FlexNVM configuration"
+        flavor none
+        no_define
+        active_if { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X" }
+        requires {
+            CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB <=
+            CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_EEE {
+            display "Enhanced EEPROM (EEE)"
+            flavor  bool;
+
+            cdl_option CYGHWR_HAL_KINETIS_EEE_SIZE {
+                display      "EEE Size \[Bytes\]"
+                flavor        data
+                legal_values  { 0 32 64 128 256 512 1024 2048 4096
+                    CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 16384 ? 8196 : 0
+                    CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 16384 ? 16384 : 0
+                }
+                default_value CYGHWR_HAL_KINETIS_FLEXRAM_SIZE
+            }
+
+            cdl_component CYGHWR_HAL_KINETIS_EEE_SPLIT {
+                display       "EEE Split ratio"
+                flavor data
+                legal_values  { 0 2 4 8 }
+                default_value 0
+                description "
+                    Enhanced EEPROM is split in two partitions that are
+                    represented by separate sections in MLT files.
+                    The split, CYGHWR_HAL_KINETIS_EEE_SPLIT, represents
+                    partition size ratio where EEE0 partition size is
+                    1/CYGHWR_HAL_KINETIS_EEE_SPLIT of EEE size, and EEE1
+                    is the rest. As a special arrangement
+                    (CYGHWR_HAL_KINETIS_EEE_SPLIT == 0) is a PHONY, where
+                    split equals 2 but in MLT files whole EEE is counted
+                    as a single section."
+
+                cdl_option CYGHWR_HAL_KINETIS_EEE0_SIZE {
+                    display "e_eeprom0 section size \[Bytes\]"
+                    flavor data
+                    calculated { CYGHWR_HAL_KINETIS_EEE_SPLIT > 0 ?
+                        CYGHWR_HAL_KINETIS_EEE_SIZE /
+                        CYGHWR_HAL_KINETIS_EEE_SPLIT :
+                        CYGHWR_HAL_KINETIS_EEE_SIZE }
+                }
+
+                cdl_option CYGHWR_HAL_KINETIS_EEE1_SIZE {
+                    display "e_eeprom1 section size \[Bytes\]"
+                    flavor data
+                    active_if { CYGHWR_HAL_KINETIS_EEE_SPLIT > 0 }
+                    calculated { CYGHWR_HAL_KINETIS_EEE_SIZE -
+                        CYGHWR_HAL_KINETIS_EEE0_SIZE }
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB {
+                display "FlexNVM partition used for EEE \[KiB\]"
+                flavor     data
+                calculated { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB == 512 ?
+                             CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_512_PART_KIB :
+                             CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_256_PART_KIB
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_256_PART_KIB {
+                    display "FlexNVM partition used for EEE \[KiB\]"
+                    flavor data
+                    active_if      CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB == 256
+                    default_value  32
+                    legal_values { 32 64 128 192 224 256 }
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_512_PART_KIB {
+                    display "FlexNVM partition used for EEE \[KiB\]"
+                    flavor data
+                    active_if      CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB == 512
+                    default_value  64
+                    legal_values { 64 128 256 384 448 512 }
+                }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE {
+            display "FlexNVM D Flash"
+            flavor data
+            active_if { CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB <
+                CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB}
+            calculated {
+                1024 * ( CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB -
+                         CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB)
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FLEXRAM_RAM {
+            display "Flexram ordinary RAM"
+            flavor data
+            active_if { !CYGHWR_HAL_CORTEXM_KINETIS_EEE }
+            calculated CYGHWR_HAL_KINETIS_FLEXRAM_SIZE
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FLEXRAM_SIZE {
+            display "Flexram size"
+            flavor data
+            legal_values  { 4096 16384 }
+            default_value CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 70 ? 16384 : 4096
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB {
+            display "FlexNVM size \[KiB\]"
+            flavor data
+            calculated CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB
+        }
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        parent CYG_HAL_STARTUP_ENV
+        calculated {
+            (CYGHWR_MEMORY_LAYOUT_PLF) ? CYGHWR_MEMORY_LAYOUT_PLF :
+            (CYG_HAL_STARTUP == "ROM" ) ? "kinetis_"
+            . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_rom" :
+            (CYG_HAL_STARTUP == "SRAM") ? "kinetis_"
+            . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_sram" :
+            "undefined" }
+        description "
+            Combination of 'Startup type' and 'Kinetis part'
+            produces the memory layout."
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display "Memory layout linker script fragment"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display "Memory layout header file"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED {
+        display  "Unified on chip SRAM region"
+        flavor    bool
+        default_value    { 1 }
+        description "
+            Kinetis have two equal SRAM banks SRAM_L and SRAM_U that
+            occupy consecutive memory blocks with \(possibility for
+            simultaneous\) access from on separate buses.
+            SRAM_L is placed below 0x20000000 and SRAM_U above 0x20000000.
+            This option provides for selection between memory layout with
+            single (unified) (S)RAM region and layout with two separate
+            (S)RAM regions."
+    }
+
+    cdl_option CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION {
+        display "Utilize \".kinetis_misc\" section for HAL"
+        flavor bool
+        default_value { CYG_HAL_STARTUP == "ROM" }
+        active_if { CYG_HAL_STARTUP == "ROM" }
+        description "
+            Kinetis use FLASH locations between 0x400 and 0x40F for FLASH
+            security configuration. This leaves FLASH area below 0x400
+            out of standard linker sections. Special section
+            \".kinetis_misc\" provides linker access to this area.
+            Setting this option instructs linker to place some HAL
+            (variant/platform) \"misc.\" functions in this area."
+    }
+
+    cdl_option CYGOPT_HAL_KINETIS_DIAG_IN_MISC_FLASH_SECTION {
+        display "HAL diag. in \".kinetis_misc\" section"
+        flavor bool
+        active_if CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION
+        default_value 0
+        description "
+        By default only misc. HAL functions are stored in
+        \".kinetis_misc\" section. In addition HAL diagnostc
+        functions may be placed as well."
+    }
+
+    cdl_component CYGHWR_HAL_KINETIS_MEMORY_RESOURCES {
+        display "On chip memory resources"
+        flavor none
+        no_define
+        description "
+        View and manage on-chip memory resources.
+        Output is used for naming of 'mlt' files."
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB {
+            display "On chip Flash option \[KiB\]"
+            flavor data
+            calculated { (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME == "1M0")
+                ? 1024 : CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_KIB {
+            display "Kinetis on chip SRAM size \[KiB\]"
+            flavor data
+            calculated {
+                (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 1024 ||
+                 CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 512)   ? 128 :
+                (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 256)   ? 64 :
+                (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 128)   ? 32 :
+                (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 96 ||
+                 CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 64)    ? 16 :
+                (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 32)    ? 8 :
+                "Unknown"
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_LAYOUT {
+            display "SRAM layout"
+            flavor data
+            no_define
+            calculated { CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED ?
+                "unisram" :
+                "sram2s"
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT {
+            display "On-chip memory layout"
+            flavor data
+            no_define
+            calculated {(CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X" ? "flexnvm_": "flash_")
+                . CYGHWR_HAL_CORTEXM_KINETIS_SRAM_LAYOUT }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_SIZE {
+            display "Kinetis on chip FLASH size"
+            flavor data
+            calculated { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB * 0x400 }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_SRAM_SIZE {
+            display "Kinetis on chip SRAM size"
+            flavor data
+            calculated { CYGHWR_HAL_CORTEXM_KINETIS_SRAM_KIB * 0x400 }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE {
+            display "Kinetis onchip RAM bank size"
+            flavor  data
+            calculated { CYGHWR_HAL_KINETIS_SRAM_SIZE/2 }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLEXNVM_FLASH_SIZE {
+            display "Kinetis on chip FlexNVM FLASH size"
+            flavor data
+            active_if { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X" }
+            calculated { (CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB
+                          - CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB)* 0x400 }
+            }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLEXNVM_FLEXRAM_SIZE {
+            display   "Kinetis on chip FlexRAM size"
+            flavor    data
+            active_if { (CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X") &&
+                !CYGHWR_HAL_CORTEXM_KINETIS_EEE }
+            calculated { CYGHWR_HAL_KINETIS_FLEXRAM_SIZE }
+        }
+    }
+
+    cdl_interface CYGINT_HAL_CACHE {
+        display "Platform has cache"
+        flavor bool
+    }
+
+    cdl_interface CYGINT_HAL_HAS_NONCACHED {
+        display "Platform has non-cached regions"
+        flavor bool
+    }
+
+    cdl_component CYGPKG_HAL_KINETIS_CACHE {
+        display "Cache memory"
+        flavor bool
+
+        default_value CYGINT_HAL_CACHE
+        active_if (CYGINT_HAL_CACHE)
+    }
+
+    cdl_component CYGHWR_HAL_NONCACHED {
+        display "Non cached RAM memory regions"
+        flavor        booldata
+        active_if     CYGINT_HAL_HAS_NONCACHED
+        legal_values  { "\".sram\"" "\".noncache\"" }
+        default_value { "\".noncache\"" }
+        description   "
+            Non cached memory sections may be usful for storage that
+            is unsuitable for caching, such as sharing buffers between
+            the CPU and other bus masters such as DMA, ENET, etc.
+            The  \".sram\" section is located in the internal SRAM,
+            which is is always present and never cached.
+            Additionaly, as an option, a partition of external memory:
+            DDRAM or FlexRAM, if one is present, can be configured
+            non-cached and accommodate \".noncache\" section."
+
+        cdl_option CYGHWR_HAL_ENET_TCD_SECTION {
+            display       "Ethernet buffer descriptor memory section"
+            flavor data
+            legal_values  { "\".sram\"" "\".noncache\"" }
+            default_value { "\".sram\"" }
+
+            description "Ethernet is a bus master so buffers/buffer
+                descriptos must reside in non-cached memory"
+        }
+
+        cdl_option CYGHWR_HAL_ENET_BUF_SECTION {
+            display       "Ethernet buffer memory section"
+            flavor        data
+            legal_values  { "\".sram\"" "\".noncache\"" }
+            default_value { "\".noncache\"" }
+
+            description "Ethernet is a bus master so buffers/buffer
+                descriptos must reside in non-cached memory"
+        }
+
+        cdl_option CYGHWR_HAL_EDMA_TCD_SECTION {
+            display       "eDMA transfer control descriptor memory section"
+            flavor        data
+            legal_values  { "\".sram\"" "\".noncache\"" }
+            default_value { "\".sram\"" }
+
+            description   "eDMA is a bus master so buffers/buffer
+                descriptos must reside in non-cached memory"
+        }
+
+        cdl_option CYGHWR_HAL_EDMA_BUF_SECTION {
+            display       "eDMA buffer memory section"
+            flavor data
+            legal_values  { "\".sram\"" "\".noncache\"" }
+            default_value { "\".noncache\"" }
+
+            description   "eDMA is a bus master so buffers/buffer
+                descriptos must reside in non-cached memory"
+        }
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_DDRAM {
+        display "Platform uses DDRAM"
+        flavor bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides DDRAM and if DDRAM is
+            used on target hardware"
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_DDRMC {
+        display       "DDRAM"
+        flavor bool
+        active_if     CYGINT_HAL_CORTEXM_KINETIS_DDRAM
+        default_value CYGINT_HAL_CORTEXM_KINETIS_DDRAM
+        description   "DDRAM on Kinetis is mirrored at several address ranges.
+                Each mirror has its own caching options that may include:
+                non-cached, write-through and write-back.
+                By eCos configuration, DDRAM is split in 3 partitions:
+                Cached, Non-cached and Code.
+                Cached partition is intended for general purpose main memory.
+                Non-cached partition is convenient for sharing
+                buffers with other bus masters such as Ethernet controller,
+                DMA, etc. Code partition is for executable code."
+
+        requires       CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+        compile        kinetis_ddram.c
+
+        script kinetis_ddram.cdl
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_FBRAM {
+        display "Platform uses FlexBus RAM"
+        flavor bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides FlexBus and if FlexBus is
+            used on target hardware"
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FBRAM {
+        display       "FlexBus RAM"
+        flavor bool
+        active_if     CYGINT_HAL_CORTEXM_KINETIS_FBRAM
+        default_value CYGINT_HAL_CORTEXM_KINETIS_FBRAM
+        requires      CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
+        description   "FBRAM on Kinetis is mirrored at several address ranges.
+                Each mirror has its own caching options that may include:
+                non-cached, write-through and write-back.
+                By eCos configuration, FlexBus RAM is split in 3 partitions:
+                Cached, Non-cached and Code.
+                Cached partition is intended for general purpose main memory.
+                Non-cached partition is convenient for sharing
+                buffers with other bus masters such as Ethernet controller,
+                DMA, etc. Code partition is for executable code."
+
+        script kinetis_fbram.cdl
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS {
+        display     "Platform uses FlexBus"
+        flavor      bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides FlexBus and if FlexBus is
+            used on target hardware"
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS {
+        display       "FlexBus"
+        flavor bool
+        active_if     CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS
+        default_value CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS
+        description   "FlexBus provides access for external memory."
+
+        script        kinetis_flexbus.cdl
+    }
+
+    cdl_component CYGHWR_HAL_KINETIS_FLASH_CONF {
+        display "Flash configuration field"
+        flavor   none
+        no_define
+
+        active_if { CYG_HAL_STARTUP == "ROM" }
+
+        description "
+            The program flash memory contains a 16-byte flash
+            configuration field that stores default protection settings
+            (loaded on reset) and security information that allows the MCU to
+            restrict access to the flash module.
+            Note: Changing some values in Flash configuration field may make
+            flash inaccessible and disable further re-programming of the flash
+            permanently. Consult respective Kinetis' documentation before dealing
+            with the Flash configuration field. Default values are equal
+            to the factory values."
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_BACKDOOR_KEY {
+            display "Backdoor comparison key"
+            flavor data
+            default_value { "\{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff \}" }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FPROT {
+            display "Program flash protection"
+            flavor data
+            default_value { "\{ 0xff, 0xff, 0xff, 0xff \}" }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FSEC {
+            display "Flash security byte"
+            flavor data
+            default_value 0xfe
+
+            description "
+                Note: FSEC default value is deliberately set to
+                0xfe in order to disable chip lockout."
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FOPT {
+            display "Flash nonvolatile option byte"
+            flavor data
+            default_value 0xff
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FDPROT {
+            display "Data flash protection byte"
+            flavor data
+            default_value 0xff
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FEPROT {
+            display "EEPROM protection byte"
+            flavor data
+            default_value 0xff
+        }
+    }
+
+    cdl_option CYGNUM_HAL_KINETIS_MEM_SEGMENTS {
+        display    "RAM memory segments"
+        flavor     data
+        no_define
+        active_if  is_active(CYGBLD_REDBOOT_MAX_MEM_SEGMENTS)
+        requires   { CYGBLD_REDBOOT_MAX_MEM_SEGMENTS >= CYGNUM_HAL_KINETIS_MEM_SEGMENTS }
+
+        calculated {
+            ((CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED ? 1 : 2) +
+            (CYGPKG_HAL_CORTEXM_KINETIS_DDRMC        ? 2 : 0) +
+            (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE  ? 1 : 0) +
+            (CYGPKG_HAL_CORTEXM_KINETIS_FBRAM        ? 2 : 0) +
+            (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE  ? 1 : 0))
+        }
+    }
+
+    for { set ::channel 0 } { $::channel < 6 } { incr ::channel } {
+
+        cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel] {
+            display     "Platform provides UART [set ::channel] HAL"
+            flavor      bool
+            description "
+                This interface will be implemented if the specific
+                controller being used has on-chip UART [set ::channel],
+                and if that UART is accessible on the target hardware."
+        }
+
+        cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel]_RTSCTS {
+            display     "Platform provides HAL for UART[set ::channel] hardware flow control."
+            flavor      bool
+            description "
+                This interface will be implemented if the specific
+                on-chip UART [set ::channel] has RTS/CTS flow control
+                that is accessible on the target hardware."
+        }
+    }
+
+    cdl_interface CYGINT_HAL_DMA {
+        display     "Platform uses DMA"
+        flavor      bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides DMA and if DMA is
+            used on target hardware"
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR {
+        display     "Variant IRQ priority defaults"
+        no_define
+        flavor      none
+        parent      CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME
+        description "
+            Interrupt priorities defined by Kinetis variant"
+        script kinetis_irq_scheme.cdl
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_OPTIONS {
+        display      "Build options"
+        flavor       none
+        no_define
+        description   "
+            Package specific build options including control over
+            compiler flags used only in building this package."
+
+        cdl_option CYGPKG_HAL_CORTEXM_KINETIS_CFLAGS_ADD {
+            display       "Additional compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the Kinetis variant HAL package. These flags
+                are used in addition to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_CORTEXM_KINETIS_CFLAGS_REMOVE {
+            display       "Suppressed compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the Kinetis variant HAL package. These flags
+                are removed from the set of global flags if present."
+        }
+    }
+}
+
+# EOF hal_cortexm_kinetis.cdl
diff --git a/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl
@@ -0,0 +1,978 @@
+##==========================================================================
+##
+##      kinetis_clocking.cdl
+##
+##      Cortex-M Freescale Kinetis Clocking
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-10-19
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+#    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING
+#    display       "Clocking"
+
+    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ {
+        display "System frequency actual value"
+        flavor data
+        calculated {
+            CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC   ?
+            CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC   :
+            CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC   ?
+            CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC   :
+            (CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL ||
+             CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1)   ?
+            CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLLSEL_FREQ_AV:
+            CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_FLL      ?
+            CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV :
+            0
+        }
+        description "Operating system clock frequency."
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG {
+        display "MCG"
+        flavor data
+        no_define
+        calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK . " " .
+            ((CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ+500000)/1000000) . "MHz, " . (
+                  (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "EXT_REFCLK") ?
+                  CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS :
+                  CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC)
+
+        }
+        description "Multipurpose Clock Generator"
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK {
+            display "System clock source"
+            flavor data
+            default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 == 1 ? "PLL1" : "PLL" }
+            legal_values {
+                "PLL" "FLL" "EXT_REFCLK" ( CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 ? "PLL1" : "PLL" )
+            }
+            requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" implies
+                CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL == 1
+            }
+            requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" implies
+                CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 == 1
+            }
+            description "
+                Select one of 3 options for MCG output clock:
+                PLL or FLL oscillator or External reference clock."
+        }
+
+        cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT {
+            display "EXT_REFCLK source clock settings"
+            flavor none
+            no_define
+            active_if {
+                (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK") ||
+                (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "EXT_REFCLK")
+            }
+            description "Set External Reference Clock frequency and type."
+
+            cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT0 {
+                display "External freq ref 0"
+                flavor data
+                no_define
+                calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS . " " .
+                    CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ
+                }
+                cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS {
+                    display "Clock type"
+                    flavor data
+                    default_value { "OSC" }
+                    legal_values { "OSC" "XTAL" "RTC"}
+
+                    requires {
+                        (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC") implies
+                        (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 50000000)
+                    }
+
+                    requires {
+                        (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL") implies
+                        (((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 3000000) &&
+                          (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 32000000)) ||
+                          ((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 32000) &&
+                           (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 40000)))
+                    }
+
+                    requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC")
+                        implies (CYGHWR_HAL_CORTEXM_KINETIS_RTC == 1)
+                    }
+                    requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC")
+                        implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")
+                    }
+                    requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC")
+                        implies (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ == 32768)
+                    }
+
+                    description "
+                    Ext reference can be External oscillator or a crystal
+                    for the on-chip oscillator or Real Time Clock."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ {
+                    display "Clock frequency"
+                    flavor data
+                    legal_values  0 to 50000000
+                    default_value {
+                        is_active(CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ) ?
+                        CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ :
+                        4000000
+                    }
+                    description "External oscillator or crystal reference in Hz."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP {
+                    display "XTAL parallel C \[pF\]"
+                    flavor data
+                    active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+                    legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 }
+                    default_value 0
+                    description "
+                        The oscillator has 4 on-chip capacitors that combined
+                        produce capacitance in parallel to the crystal."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1 {
+                display "External freq ref 1"
+                flavor data
+                no_define
+                active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1
+                calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS . " " .
+                    CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ
+                }
+                cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS {
+                    display "Clock type"
+                    flavor data
+                    default_value { "OSC" }
+                    legal_values { "OSC" "XTAL" }
+
+                    requires {
+                        (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "OSC") implies
+                        (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ <= 50000000)
+                    }
+
+                    requires {
+                        (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL") implies
+                        (((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ >= 3000000) &&
+                          (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ <= 32000000)) ||
+                          ((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ >= 32000) &&
+                           (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ <= 40000)))
+                    }
+
+                   requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC")
+                       implies (CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL == 0)
+                   }
+                   requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC")
+                       implies (CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 == 0)
+                   }
+                   requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC")
+                       implies (CYGHWR_HAL_CORTEXM_KINETIS_RTC == 1)
+                   }
+                   requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC")
+                       implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")
+                   }
+                   requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC")
+                       implies (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ == 32768)
+                   }
+
+                    description "
+                    Ext reference can be External oscillator or a crystal
+                    for the on-chip oscillator or Real Time Clock."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ {
+                    display "Clock frequency"
+                    flavor data
+                    legal_values  0 to 50000000
+                    default_value {
+                        is_active(CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ) ?
+                        CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ :
+                        4000000
+                    }
+                    description "External oscillator or crystal reference in Hz."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP {
+                    display "XTAL parallel C \[pF\]"
+                    flavor data
+                    active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" }
+                    legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 }
+                    default_value 0
+                    description "
+                        The oscillator has 4 on-chip capacitors that combined
+                        produce capacitance in parallel to the crystal."
+                }
+            }
+        }
+
+        cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL {
+            display "FLL / PLL configuration"
+            flavor none
+            no_define
+            description "
+                PLL / FLL parameters are being calculated on a
+                base of required system frequrncy and output as well as
+                reference oscillator/frequency settings."
+
+            cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP {
+                display "PLL/FLL output frequency set point"
+                flavor data
+                legal_values  32768 to 220000000
+                calculated {
+                    ((CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL") ||
+                     (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")) ?
+                        CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP :
+                        CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP
+                }
+                description "Desired PLL output frequency."
+            }
+
+            cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC {
+                display "Reference clock source for FLL or PLL"
+                flavor data
+                default_value { "EXT_REFCLK" }
+
+                requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "INT_RC_32KHZ")
+                    implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")
+                }
+
+                legal_values { "INT_RC_32KHZ" "EXT_REFCLK" "EXT_REFCLK1" }
+                description "
+                PLL/FLL oscillators can use one of external reference
+                clock references as well as Low (32768 Hz) or High (2MHz)
+                Frequency Internal oscillator"
+            }
+
+            cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_PLL1_REFSRC {
+                display "Reference clock source for PLL1"
+                active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+                flavor data
+                default_value { "EXT_REFCLK" }
+
+                legal_values { "EXT_REFCLK" "EXT_REFCLK1" }
+                description "
+                    PLL1 oscillator can use one of 2 external reference clock
+                    references."
+            }
+
+            cdl_component CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ {
+                display "Reference frequency."
+                flavor data
+                calculated { is_active (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT) ?
+                    CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ :
+                    (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC
+                     == "INT_RC_32KHZ" ? 32768 : 2000000 )
+                }
+            }
+
+            cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_FLL {
+                display "FLL oscillator"
+                flavor none
+                no_define
+                active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" ||
+                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" ||
+                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" ||
+                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK"
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE {
+                    display "Reference frequency range"
+                    flavor data
+                    legal_values 0 1 2
+                    calculated {
+                        CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ > 8000000 ? 2 :
+                        CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ >= 1000000 ? 1 :
+                        ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ >= 32000) &&
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ <= 40000)) ? 0 :
+                        -1
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV {
+                    display "Calculated FLL divider"
+                    flavor data
+                    calculated {
+                        CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE >= 1 ?
+                        ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ+32768*16) / (32768*32)) :
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0 ?
+                         ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ+16384) / 32768) : -1)
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG {
+                    display "FLL divider register value"
+                    flavor data
+                    legal_values 0 1 2 3 4 5 6 7
+                    default_value {
+                        CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0 ?
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) :
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) <= 5 ?
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) : 5
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS {
+                    display "DCO Range Select"
+                    flavor data
+                    legal_values 0 1 2 3
+                    default_value {
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 80000000 ? 3 :
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 60000000 ? 2 :
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 40000000 ? 1 : 0
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 {
+                    display "DCO max. frequency with 32768 reference"
+                    flavor data
+                    legal_values { 0 0x80 }
+                    default_value {
+                        ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 96000000) ||
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 72000000) ||
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 48000000) ||
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 9600000)) ?
+                        0x80 : 0x00
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_FLL_FACT {
+                    display "FLL factor"
+                    flavor data
+                    calculated {
+                        (CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 == 0x80) ?
+                        ((CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 0 ) ?  732 :
+                         (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 1 ) ? 1464 :
+                         (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 2 ) ? 2197 : 2929 ) :
+                        ((CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 0 ) ?  640 :
+                         (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 1 ) ? 1280 :
+                         (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 2 ) ? 1920 : 2560 )
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN {
+                    display "DCO input frequency"
+                    flavor data
+                    calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                        ( CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG == 0 ?
+                         ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0) ? 1 : 32 ) :
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG *
+                          ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0) ? 2 : 64)))
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN_CHECK {
+                    display "DCO input frequency check"
+                    flavor data
+                    no_define
+                    legal_values { "OK" "NOK" "not applicable" }
+                    calculated {
+                        CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" ?
+                        ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN >= 31250) &&
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN <= 39063) ?
+                         "OK" : "NOK" ) :
+                        "NotApplicable"
+                    }
+                    active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" }
+                    requires {
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN >= 31250) &&
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN <= 39063)
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV {
+                    display "FLL output frequency actual value"
+                    flavor data
+                    calculated {CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN *
+                        CYGNUM_HAL_CORTEXM_MCG_DCO_FLL_FACT }
+                }
+            }
+
+            cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL {
+                display "PLL oscillator"
+                flavor bool
+                default_value 1
+#                { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" ? 0 : 1 }
+#                active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" ||
+#                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK"
+#                }
+
+                cdl_component CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL {
+                    display "100 Mhz line"
+                    flavor none
+                    no_define
+                    active_if !CYGINT_HAL_CORTEXM_KINETIS_150
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ_X {
+                        display "Phase detector proposed input frequency"
+                        no_define
+                        flavor data
+                        calculated {
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 180000000) ?
+                            3800000 :
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 110000000) ?
+                            3000000 :
+                            !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 3) ? 2000000 :
+                            !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 4) ? 2000000 :
+                            !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 5) ? 2500000 :
+                            300000
+                        }
+                    }
+
+                    cdl_option CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV {
+                        display "PLL External Reference Divider"
+                        flavor data
+                        legal_values 1 to 25
+                        default_value {
+                            CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ_X ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ_X ) : -1
+                        }
+                    }
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ {
+                        display "Phase detector input frequency"
+                        no_define
+                        flavor data
+                        legal_values 2000000 to 4000000
+                        calculated { CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV) : -1
+                        }
+                    }
+
+                    cdl_option CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_VDIV {
+                        display "VCO Divider"
+                        flavor data
+                        legal_values 24 to 55
+                        default_value { CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP /
+                             CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ) : -1
+                        }
+                    }
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_100_MCG_PLL_FREQ_AV {
+                        display "PLL output frequency actual value"
+                        flavor data
+                        calculated { CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV *
+                             CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_VDIV) : -1
+                        }
+                    }
+                }
+
+                cdl_component CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL {
+                    display "150 Mhz line"
+                    flavor none
+                    no_define
+                    active_if CYGINT_HAL_CORTEXM_KINETIS_150
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ_X {
+                        display "Phase detector proposed input frequency"
+                        no_define
+                        flavor data
+                        legal_values 1000000 to 32000000
+                        default_value {
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ == 50000000) ?
+                            (!(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 48000000) ? 50000000/8 : 50000000/5) :
+                            !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 30000000) ? 30000000 :
+                            !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 4000000) ? 4000000 :
+                            5000000
+                        }
+                    }
+
+                    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL {
+                        display "PLL0 Reference Oscillator select"
+                        flavor data
+                        default_value 0
+                        legal_values 0 1
+                    }
+
+                    cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV {
+                        display "PLL External Reference Divider"
+                        flavor data
+                        legal_values 1 to 8
+                        default_value {
+                            CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ_X ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ_X ) : -1
+                        }
+                    }
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ {
+                        display "Phase detector input frequency"
+                        no_define
+                        flavor data
+                        legal_values 1000000 to 32000000
+                        calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV) : -1
+                        }
+                    }
+
+                    cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_VDIV {
+                        display "VCO Divider"
+                        flavor data
+                        legal_values 16 to 47
+                        default_value { CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ ?
+                            ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP /
+                             CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ) * 2) : -1
+                        }
+                    }
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL_FREQ_AV {
+                        display "PLL output frequency actual value"
+                        flavor data
+                        calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV ?
+                            ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV *
+                             CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_VDIV) / 2) : -1
+                        }
+                    }
+                }
+
+                cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV {
+                    display "PLL External Reference Divider"
+                    flavor data
+                    calculated { CYGINT_HAL_CORTEXM_KINETIS_150 ?
+                        CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV :
+                        CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV
+                    }
+                }
+
+                cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV {
+                    display "PLL External Reference Divider"
+                    flavor data
+                    calculated { CYGINT_HAL_CORTEXM_KINETIS_150 ?
+                        (CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_VDIV) :
+                        CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_VDIV
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL_FREQ_AV {
+                    display "PLL output frequency actual value"
+                    flavor data
+                    calculated { CYGINT_HAL_CORTEXM_KINETIS_150 ?
+                        CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL_FREQ_AV :
+                        CYGNUM_HAL_CORTEXM_KINETIS_100_MCG_PLL_FREQ_AV
+                    }
+                }
+            }
+        }
+
+        cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC {
+            display "Internal Reference Clock"
+            flavor data
+            calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC_HI ? 2000000 : 32768 }
+            active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK ==  "INT_REFCLK" }
+
+            cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC_HI {
+                display "Use highh frequency internal osc."
+                flavor bool
+                default_value 1
+            }
+        }
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC {
+            display "External Reference Clock"
+            flavor data
+            calculated CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ
+            active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK ==  "EXT_REFCLK" }
+        }
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_DIST {
+        display "Subsystem clocking"
+        flavor none
+        no_define
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS {
+            display "Peripheral bus"
+            flavor data
+            calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX {
+                display "Frequency limit"
+                flavor data
+                default_value 50000000
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP {
+                display "Calculated value"
+                flavor data
+                default_value {
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <=
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX ?
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ :
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX
+                }
+                legal_values  0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX
+            }
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS {
+                display "Divider"
+                flavor data
+                legal_values 1 to 16
+
+                default_value { !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ %
+                                  CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP)  ?
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP)  :
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP + 1)
+                }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH {
+            display "Flash"
+            flavor data
+            calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX {
+                display "Frequency limit"
+                flavor data
+                default_value 25000000
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP {
+                display "Calculated value"
+                flavor data
+                default_value {
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <=
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX ?
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ :
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX
+                }
+                legal_values  0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX
+            }
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH {
+                display "Divider"
+                flavor data
+                legal_values 1 to 16
+
+                default_value {
+                    !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ %
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP)  ?
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP)  :
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP + 1)
+                }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS {
+            display "Flex bus"
+            flavor data
+            calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX {
+                display "Frequency limit"
+                flavor data
+                default_value 50000000
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP {
+                display "Calculated value"
+                flavor data
+                default_value {
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <=
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX ?
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ :
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX
+                }
+                legal_values  0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX
+            }
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS {
+                display "Divider"
+                flavor data
+                legal_values 1 to 16
+
+                default_value {
+                    !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ %
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP)  ?
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP)  :
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP + 1)
+                }
+            }
+        }
+
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB {
+            display "USB clock"
+            flavor data
+            calculated { CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
+                CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC /
+                CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_MAX {
+                display "Frequency limit"
+                flavor data
+                default_value 48000000
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC {
+                display "Fractional Divider"
+                flavor data
+                legal_values 1 to 2
+                default_value {
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_MAX ? 1 :
+                    ((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN) >
+                     (CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP * 4) ? 1 :
+                     (CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN %
+                      CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP ? 2 : 1))
+                }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV {
+                display "Divider"
+                flavor data
+                legal_values 1 to 8
+                default_value { !((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
+                                   CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC) %
+                                   CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP)  ?
+                    (CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
+                     CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP)  :
+                    ((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
+                      CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC /
+                      CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP) +1)
+                }
+            }
+
+            cdl_option CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN {
+                display "USB divider input frequency"
+                flavor data
+                calculated {
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ
+                }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP {
+                display "Desired"
+                flavor data
+                calculated 48000000
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_TRACECLK {
+            display "Trace clock source"
+            flavor data
+            default_value { "CORE" }
+            legal_values { "CORE" "MCGOUT" }
+
+        }
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT {
+            display "Enable Trace Clock out"
+            flavor bool
+            default_value 0
+        }
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_RTC {
+        display "System uses Real Time Clock"
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_RTC {
+        display "Real Time Clock"
+        flavor bool
+        default_value CYGINT_HAL_CORTEXM_KINETIS_RTC
+
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP {
+            display "RTC XTAL parallel C \[pF\]"
+            flavor data
+            legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28
+                30 32 }
+            default_value 0
+            description "
+                The Real Time Clock oscillator has 4 capacitors that
+                combined produce capacitance in parallel to the crystal."
+        }
+    }
+
+    #   PLL1 and OSC1 Configuration
+    #   PLL1
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 {
+        display "MCG Has PLL1"
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1 {
+        display "MCG Has OSC1"
+    }
+
+    cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 {
+        display "PLL1 oscillator"
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL
+        flavor bool
+        default_value CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+        active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP {
+            display "PLL1 output frequency set point"
+            flavor data
+            legal_values  32768 to 220000000
+            calculated {
+                (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1") ?
+                     CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP :
+                     CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP
+            }
+            description "Desired PLL1 output frequency."
+        }
+
+        cdl_component CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ {
+            display "Reference frequency."
+            flavor data
+            calculated { is_active (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT) ?
+                CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ :
+                (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC
+                 == "INT_RC_32KHZ" ? 32768 : 2000000 )
+            }
+        }
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ_X {
+            display "Phase detector proposed input frequency"
+            no_define
+            flavor data
+            legal_values 1000000 to 32000000
+            default_value {
+                (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ == 50000000) ?
+                (!(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP % 48000000) ? 50000000/8 : 50000000/5) :
+                !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP % 30000000) ? 30000000 :
+                !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP % 4000000) ? 4000000 :
+                5000000
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL {
+            display "PLL10 Reference Oscillator select"
+            flavor data
+            default_value 0
+            legal_values 0 1
+        }
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV {
+            display "PLL1 External Reference Divider"
+            flavor data
+            legal_values 1 to 8
+            default_value {
+                CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ_X ?
+                (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ /
+                 CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ_X ) : -1
+            }
+        }
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ {
+            display "Phase detector input frequency"
+            no_define
+            flavor data
+            legal_values 1000000 to 32000000
+            calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV ?
+                (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ /
+                 CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV) : -1
+            }
+        }
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_VDIV {
+            display "VCO Divider"
+            flavor data
+            legal_values 16 to 47
+            default_value { CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ ?
+                ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP /
+                  CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ) * 2) : -1
+            }
+        }
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL1_FREQ_AV {
+            display "PLL1 output frequency actual value"
+            flavor data
+            calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV ?
+                ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ /
+                  CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV *
+                  CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_VDIV) / 2) : -1
+            }
+        }
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_PRDIV {
+            display "PLL1 External Reference Divider"
+            flavor data
+            calculated CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV
+        }
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_VDIV {
+            display "PLL1 External Reference Divider"
+            flavor data
+            calculated CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_VDIV
+        }
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL1_FREQ_AV {
+            display "PLL1 output frequency actual value"
+            flavor data
+            calculated CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL1_FREQ_AV
+        }
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLLSEL_FREQ_AV {
+        display "Frequency of selected PLL"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL
+        calculated {CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" ?
+            CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL1_FREQ_AV :
+            CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL_FREQ_AV
+        }
+    }
+
+    # EOF kinetis_clocking.cdl
diff --git a/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_ddram.cdl b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_ddram.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_ddram.cdl
@@ -0,0 +1,259 @@
+##==========================================================================
+##
+##      kinetis_ddram.cdl
+##
+##      Cortex-M Freescale Kinetis DDRAM configuration
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2013-04-28
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+#    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_DDRMC {
+#        display       "DDRAM"
+#        flavor bool
+#        active_if     CYGINT_HAL_CORTEXM_KINETIS_DDRAM
+#        default_value CYGINT_HAL_CORTEXM_KINETIS_DDRAM
+#        description   "DDRAM on Kinetis is mirrored at several address ranges.
+#                Each mirror has its own caching options that may include:
+#                non-cached, write-through and write-back.
+#                By eCos configuration, DDRAM is split in 3 partitions:
+#                Cached, Non-cached and Code.
+#                Cached partition is intended for general purpose main memory.
+#                Non-cached partition is convenient for sharing
+#                buffers with other bus masters such as Ethernet controller,
+#                DMA, etc. Code partition is for executable code."
+#
+#        requires       CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+#        compile        kinetis_ddram.c
+
+        cdl_component CYGHWR_HAL_KINETIS_DDR_SIZE_MIB {
+            display       "DDRAM size \[MiB\]"
+            flavor        data
+            default_value 128
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_SIZE {
+                display    "DDRAM size \[Bytes\]"
+                flavor     data
+                calculated { CYGHWR_HAL_KINETIS_DDR_SIZE_MIB * (1024 * 1024) * 0x1 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB {
+            display      "Non-cached DDRAM data partition \[MiB\]"
+            requires     { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB <=
+                           CYGHWR_HAL_KINETIS_DDR_SIZE_MIB }
+            flavor       data
+
+            implements   CYGINT_HAL_HAS_NONCACHED
+
+            legal_values { 1 to (CYGHWR_HAL_KINETIS_DDR_SIZE_MIB - 8) }
+
+            default_value CYGHWR_HAL_KINETIS_DDR_SIZE_MIB / 4
+
+            description "
+                Non-cached DDRAM partition, intended for sharing
+                buffers with other bus masters such as Ethernet controller,
+                DMA, etc."
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE {
+                display    "Non-cached DDRAM size \[Bytes\]"
+                flavor     data
+                calculated { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB
+                             * (1024 * 1024) * 0x1 }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE {
+                display    "Non-cached DDRAM base address"
+                flavor     data
+
+                calculated { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_MIRROR +
+                             CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE +
+                             CYGHWR_HAL_KINETIS_DDR_CODE_SIZE }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_MIRROR {
+                display       "Non-cached DDRAM mirror base"
+                flavor        data
+                no_define
+                calculated    { CYGHWR_HAL_KINETIS_DDR_CACHED_MIRROR == 0x70000000 ?
+                    0x80000000 : 0x70000000 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB {
+            display       "DDRAM code partition \[MiB\]"
+            requires      { CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB <=
+                            CYGHWR_HAL_KINETIS_DDR_SIZE_MIB }
+            flavor        data
+
+            legal_values  { 1 to (CYGHWR_HAL_KINETIS_DDR_SIZE_MIB - 8) }
+
+            default_value CYGHWR_HAL_KINETIS_DDR_SIZE_MIB / 4
+
+            description "
+                DDRAM code partition - for use as program memory.
+                On systems with cache this partition is cached in PC cache.
+                Caching is always write-through"
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_CODE_SIZE {
+                display    "DDRAM code partition size \[Bytes\]"
+                flavor     data
+                calculated { CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB
+                             * (1024 * 1024) * 0x1 }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_CODE_BASE {
+                display    "DDRAM code partition base address"
+                flavor     data
+
+                calculated { 0x08000000 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE_MIB {
+            display    "Cached DDRAM data partition \[MiB\]"
+            flavor     data
+            requires   { CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE_MIB >= 8 }
+            calculated { CYGHWR_HAL_KINETIS_DDR_SIZE_MIB -
+                         CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB -
+                         CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB }
+
+            description "
+                Cached DDRAM data partition - for general use as main data memory.
+                On systems with cache this partition is cached in PS cache.
+                Caching can be either copy-back or write-through and is determined by
+                general cache mode setting."
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE {
+                display    "Cached DDRAM size \[Bytes\]"
+                flavor      data
+                calculated  { (CYGHWR_HAL_KINETIS_DDR_SIZE -
+                              CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE -
+                              CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) * 0x1 }
+                }
+
+                cdl_option CYGHWR_HAL_KINETIS_DDR_CACHED_BASE {
+                    display       "Cached DDRAM base address"
+                    flavor        data
+                    calculated    { CYGHWR_HAL_KINETIS_DDR_CACHED_MIRROR +
+                                    CYGHWR_HAL_KINETIS_DDR_CODE_SIZE }
+                }
+
+                cdl_option CYGHWR_HAL_KINETIS_DDR_CACHE_TYPE {
+                    display     "DDRAM cache type"
+                    flavor       data
+                    calculated  CYGSEM_HAL_DCACHE_STARTUP_MODE
+                    description "DDRAM cache type is determined by general cache setting"
+                }
+
+                cdl_component CYGHWR_HAL_KINETIS_DDR_CACHED_MIRROR {
+                    display         "Cached DDRAM mirror base"
+                    flavor data
+                    no_define
+                    legal_values     { 0x70000000 0x80000000 }
+                    default_value    { 0x70000000 }
+                    description   "
+                        According to Kinetis Reference Manual rev. 2, the DDRAM mirror
+                        mapped at 0x80000000 (supporting write-thru caching only)
+                        is not accesible by ENET, SDH and some other bus masters,
+                        and that the mirror at 0x70000000 (supporting copy-back caching)
+                        is accessible by them.
+                        The practical tests prove that it is the opposite, actually as
+                        it should be.
+                        Until this discrepancy is resolved, this option selects the
+                        default (non)cached mirror and provides the user with possibilty for
+                        manual override.
+                        Note: The behavior may change in future."
+                }
+        }
+
+        cdl_option CYGHWR_HAL_DDR_SYNC_MODE {
+            display       "Use synchronous mode"
+            flavor        bool
+            requires      { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" }
+            default_value { 1 }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_SIM_MCR_DDRBUS {
+            display      "DDRAM bus configuration"
+            flavor        data
+            legal_values  0 1 2 3 6
+            default_value 6
+            description "
+                DDRAM configuration: 0 - LPDDR Half Strength,
+                1 - LPDDR Full Strength, 2 - DDR2 Half Strength,
+                3 - DDR1, 6 - DDR2 Full Strength"
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL {
+            display    "Pad control"
+            flavor     data
+
+            calculated {
+                (CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_ODT << 24) |
+                CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_SPARE_DLY_CTRL |
+                0x00000200
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_ODT {
+                display       "On Die Termination"
+                flavor        data
+                legal_values  { 0 1 2 3 }
+                default_value 1
+
+                description   "On Die Termination \[Ohm\]: 0 - Off, 1 - 75,
+                    2 - 150, 3 - 50"
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_SPARE_DLY_CTRL {
+                display       "Delay chains in spare logic"
+                flavor        data
+                legal_values  { 0 1 2 3 }
+                default_value 3
+
+                description "Delay chains in spare logic: 0 - No buffer, 1 - 4 buffers,
+                    2 - 7 buffers, 11 - 10 buffers"
+            }
+        }
+#    }
+
+# EOF kinetis_ddram.cdl
diff --git a/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_fbram.cdl b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_fbram.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_fbram.cdl
@@ -0,0 +1,205 @@
+##==========================================================================
+##
+##      kinetis_fbram.cdl
+##
+##      Cortex-M Freescale Kinetis FBRAM configuration
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2013-04-28
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+#    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FBRAM {
+#        display       "FlexBus RAM"
+#        flavor bool
+#        active_if     CYGINT_HAL_CORTEXM_KINETIS_DBRAM
+#        default_value CYGINT_HAL_CORTEXM_KINETIS_FBRAM
+#        description   "FlexBus RAM on Kinetis is mirrored at several address ranges.
+#                Each mirror has its own caching options that may include:
+#                non-cached, write-through and write-back.
+#                By eCos configuration, FlexBus RAM is split in 3 partitions:
+#                Cached, Non-cached and Code.
+#                Cached partition is intended for general purpose main memory.
+#                Non-cached partition is convenient for sharing
+#                buffers with other bus masters such as Ethernet controller,
+#                DMA, etc. Code partition is for executable code."
+#
+
+        cdl_option CYGHWR_HAL_KINETIS_FBR_SIZE {
+            display       "FlexBus RAM size \[Bytes\]"
+            flavor        data
+            default_value CYGHWR_HAL_KINETIS_FB_CS0_SIZE ? CYGHWR_HAL_KINETIS_FB_CS0_SIZE * 1 : 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FBR_SIZE_KIB {
+            display       "FlexBus RAM size \[KiB\]"
+            flavor        data
+            calculated    { CYGHWR_HAL_KINETIS_FBR_SIZE / 1024 }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB {
+            display      "Non-cached FlexBus data RAM partition \[KiB\]"
+            requires     { CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB <=
+                           CYGHWR_HAL_KINETIS_FBR_SIZE_KIB }
+            flavor       data
+
+            implements   CYGINT_HAL_HAS_NONCACHED
+
+            legal_values { 64 to (CYGHWR_HAL_KINETIS_FBR_SIZE_KIB - 64) }
+
+            default_value { CYGHWR_HAL_KINETIS_FBR_SIZE_KIB / 4 }
+
+            description "
+                Non-cached FlexBus RAM partition, intended for sharing
+                buffers with other bus masters such as Ethernet controller,
+                DMA, etc."
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE {
+                display    "Non-cached FlexBus RAM size \[Bytes\]"
+                flavor     data
+                calculated { CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB
+                             * 1024 * 0x1 }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE {
+                display    "Non-cached FlexBus RAM base address"
+                flavor     data
+
+                calculated { CYGHWR_HAL_KINETIS_FBR_NON_CACHED_MIRROR +
+                             CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE +
+                             CYGHWR_HAL_KINETIS_FBR_CODE_SIZE }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_NON_CACHED_MIRROR {
+                display       "Non-cached FlexBus RAM mirror base"
+                flavor        data
+                no_define
+                legal_values     { 0x60000000 CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x90000000 : 0x80000000 }
+                default_value    { CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x90000000 :
+                                                                    0x60000000 }
+            }
+
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB {
+            display       "FlexBus RAM code partition \[KiB\]"
+            requires      { CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB <=
+                            CYGHWR_HAL_KINETIS_FBR_SIZE_KIB }
+            flavor        data
+
+            legal_values  { 64 to (CYGHWR_HAL_KINETIS_FBR_SIZE_KIB - 64) }
+
+            default_value { CYGHWR_HAL_KINETIS_FBR_SIZE_KIB / 4 }
+
+            description "
+               FlexBus RAM code partition - for use as program memory.
+               On systems with cache this partition is cached in PC cache
+               and is always write-through"
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_CODE_SIZE {
+                display    "FlexBus RAM code partition size \[Bytes\]"
+                flavor     data
+                calculated { CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB
+                             * 1024 * 0x1 }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_CODE_BASE {
+                display    "FlexBus RAM code partition base address"
+                flavor     data
+
+                legal_values     { 0x60000000
+                                   CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x18000000 :
+                                                                    0x60000000 }
+                default_value { CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x18000000 :
+                                                                 0x60000000 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE_KIB {
+            display    "Cached FlexBus RAM data partition \[KiB\]"
+            flavor     data
+            requires   { CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE_KIB >= 64 }
+            calculated { CYGHWR_HAL_KINETIS_FBR_SIZE_KIB -
+                         CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB -
+                         CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB }
+
+            description "
+               Cached FlexBus RAM data partition - for general use as main data memory.
+               On systems with cache this partition is cached in PS cache.
+               Caching can be either copy-back or write-through and is determined
+               by general cache mode setting."
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE {
+                display    "Cached FlexBus RAM size \[Bytes\]"
+                flavor      data
+                calculated  { (CYGHWR_HAL_KINETIS_FBR_SIZE -
+                              CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE -
+                              CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) * 0x1 }
+                }
+
+                cdl_option CYGHWR_HAL_KINETIS_FBR_CACHED_BASE {
+                    display       "Cached FlexBus RAM base address"
+                    flavor        data
+                    calculated    { CYGHWR_HAL_KINETIS_FBR_CACHED_MIRROR +
+                                    CYGHWR_HAL_KINETIS_FBR_CODE_SIZE }
+                }
+
+                cdl_option CYGHWR_HAL_KINETIS_FBR_CACHE_TYPE {
+                    display     "FlexBus RAM cache type"
+                    flavor       data
+                    calculated  CYGSEM_HAL_DCACHE_STARTUP_MODE
+                    description "FlexBus RAM cache type is determined by general
+                        cache setting"
+                }
+
+                cdl_component CYGHWR_HAL_KINETIS_FBR_CACHED_MIRROR {
+                    display         "Cached FlexBus RAM mirror base"
+                    flavor data
+                    no_define
+                    legal_values     { 0x60000000 CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x90000000 : 0x80000000 }
+                    default_value    { 0x60000000 }
+                    description      "Cached DDRAM base "
+                }
+        }
+
+#    }
+
+# EOF kinetis_fbram.cdl
diff --git a/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_flexbus.cdl b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_flexbus.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_flexbus.cdl
@@ -0,0 +1,84 @@
+##==========================================================================
+##
+##      kinetis_flexbus.cdl
+##
+##      Cortex-M Freescale Kinetis FlexBus
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-12-11
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+#        cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS {
+#        display       "FlexBus"
+
+for { set ::chipsel 0 } { $::chipsel < 6 } { incr ::chipsel } {
+
+    cdl_interface CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] {
+        display     "Platform uses Chip select [set ::chipsel]"
+        flavor      bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides chip select [set ::chipsel], and if
+            that chip select is used on target hardware."
+    }
+
+    cdl_component CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel] {
+        display       "Chip select [set ::chipsel]"
+        flavor        bool
+        active_if     CYGINT_HAL_KINETIS_FB_CS[set ::chipsel]
+        default_value CYGINT_HAL_KINETIS_FB_CS[set ::chipsel]
+        description   "
+            This option includes initialization data for
+            chip select [set ::chipsel]."
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PS {
+            display "Port size (encoded)"
+            flavor data
+            calculated ( \
+               CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 32 ? 0 : \
+               CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 8  ? 1 : \
+               CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 16 ? 2 : 3)
+        }
+    }
+}
+
+
+# EOF kinetis_flexbus.cdl
diff --git a/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl
@@ -0,0 +1,202 @@
+##==========================================================================
+##
+##      kinetis_irq_scheme.cdl
+##
+##      Cortex-M Freescale Kinetis IRQ configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2010-12-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+#    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR {
+#        display "Variant IRQ priority defaults"
+#        no_define
+#        flavor none
+#        parent CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME
+#        description "
+#            Interrupt priorities defined by Kinetis variant"
+
+        cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP {
+            display       "Clock IRQ priority"
+            flavor        data
+            no_define
+            default_value 0xE0
+            description   "Set clock ISR priority. Default setting is lowest priority."
+            legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+
+        }
+
+        cdl_option CYGNUM_DEVS_ETH_FREESCALE_ENET0_INTPRIO_SP {
+            display "Ethernet IRQ priority"
+            flavor data
+            no_define
+            active_if CYGPKG_DEVS_ETH_FREESCALE_ENET
+            legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+            default_value 0xE0
+        }
+
+        cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_UART {
+            display "UART IRQ priorities"
+            flavor none
+            no_define
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_PRIORITY_SP {
+                display "UART0 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART0
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_PRIORITY_SP {
+                display "UART1 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART1
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_PRIORITY_SP {
+                display "UART2 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART2
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_PRIORITY_SP {
+                display "UART3 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART3
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_PRIORITY_SP {
+                display "UART4 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART4
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_PRIORITY_SP {
+                display "UART5 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART5
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+        }
+
+        cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_DSPI {
+            display "DSPI IRQ priorities"
+            flavor none
+            no_define
+
+            cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI0_ISR_PRI_SP {
+                display "DSPI bus 0 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGHWR_DEVS_SPI_FREESCALE_DSPI0
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0xD0
+            }
+
+            cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI1_ISR_PRI_SP {
+                display "DSPI bus 1 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGHWR_DEVS_SPI_FREESCALE_DSPI1
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0xD0
+            }
+
+            cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI2_ISR_PRI_SP {
+                display "DSPI bus 2 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGHWR_DEVS_SPI_FREESCALE_DSPI2
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0xD0
+            }
+        }
+        
+        cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_I2C {
+            display "I2C interrupt priorities"
+            flavor none
+            no_define
+            
+            for { set ::bus 0 } { $::bus < 2 } { incr ::bus } {
+                
+                cdl_option CYGNUM_DEVS_FREESCALE_I2C[set ::bus]_IRQ_PRIORITY {
+                    display       "I2C bus [set ::bus] interrupt priority"
+                    flavor        data
+                    active_if     CYGHWR_DEVS_FREESCALE_I2C[set ::bus]
+                    default_value 0x90
+                    legal_values  { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 
+                        0x90  0xA0 0xB0 0xC0 0xD0 0xE0 }
+                }
+            }
+        }
+
+#    }
+
+
+# EOF kinetis_irq_scheme.cdl
diff --git a/packages/hal/cortexm/kinetis/var/current/doc/kinetis.sgml b/packages/hal/cortexm/kinetis/var/current/doc/kinetis.sgml
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/doc/kinetis.sgml
@@ -0,0 +1,308 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     kinetis.sgml                                                -->
+<!--                                                                 -->
+<!--     KINETIS          documentation.                             -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2012 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2012/01/10                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<!-- <part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title> -->
+
+<refentry id="hal-cortexm-kinetis-var">
+  <refmeta>
+    <refentrytitle>Freescale Kinetis Variant</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname><literal>CYGPKG_HAL_CORTEXM_KINETIS</literal></refname>
+    <refpurpose>eCos Support for Freescale Kinetis Micro-controllers</refpurpose>
+  </refnamediv>
+  
+  <refsect1 id="hal-cortexm-kinetis-var-description"><title>Description</title>
+    <para>
+    Kinetis is a Freescale microcontroller family based on the ARM Cortex-M4 core. The
+    family consists of subfamilies: K10, K20, K30, K40, K50, K60 and K70
+    that gradually add-on performance and features.
+    </para>
+    <para>
+    The Kinetis variant HAL provides generic support for hardware found on some
+    or all Kinetis members. The variant package <literal>CYGPKG_HAL_CORTEXM_KINETIS</literal>
+    provides configurable components that aim to support the complete set of options
+    found in the Kinetis family.
+    </para>
+  </refsect1>
+  <refsect1 id="kinetis-var-sup"><title>What's supported</title>
+    <para>
+    The current Kinetis software includes a Kinetis variant HAL, some Platform BSPs,
+    as well as DMA, UART, Wallclock, Ethernet and SPI support.
+    </para>
+  </refsect1>
+  <refsect1 id="kinetis-var-config"><title>Configuration</title>
+    <para>    Kinetis is a set of families of micro-controllers packed with highly configurable components.
+    In order to facilitate system configuration for the user, the CDL configuration items are organized as a set of
+    expert components. Typically, for a given peripheral, the user chooses the required hardware
+    options and desirable parameters, and the respective CDL configuration options and settings are calculated from these.
+    If it is not possible to achieve exact values, the configurator attempts to provide 
+    approximate settings, then the user can manually do the fine tuning.</para>
+    <refsect2 id="kinetis-var-cpu-select"><title>Kinetis Part Selection</title>
+      <para>
+      Within a family and/or across families the chips are further differentiated by their features
+      such as: optional FPU, amount of memory, etc. The family member options are reflected in the
+      controller naming scheme (see respective Freescale Kinetis product brief(s) and reference manual(s)). 
+      The Kinetis part builder <literal>CYGHWR_HAL_CORTEXM_KINETIS</literal>, respects this naming scheme and
+      enables the user to interactively configure eCos for the desired part by selecting
+      the requested part name segments.
+      Based on user input, the CDL computes the part-specific eCos configuration. This includes calculation
+      of on-chip FLASH and SRAM layout as well as the activation/deactivation of options such as FPU and
+      Ethernet.
+      </para>
+    </refsect2>
+    <refsect2 id="kinetis-var-clocking"><title>Clocking</title>
+      <para>
+      Kinetis is packed with a rich set of clocking options provided by the Multipurpose Clock Generator - MCG.
+      Dependent on the part, MCG can have outlets for one or two external frequency reference sources 
+      <emphasis>OSC</emphasis> and <emphasis>OSC1</emphasis> and one
+      or two PLL oscillators <emphasis>PLL</emphasis> and <emphasis>PLL1</emphasis>.
+      Each of the external frequency reference sources can be either a crystal or external
+      oscillator and associated with either or both PLL oscillators. <emphasis>OSC</emphasis> can also be a
+      reference source for the FLL oscillator.
+      Besides <emphasis>OSC</emphasis> and <emphasis>OSC1</emphasis>, there are additional clock sources
+      including two RC oscillators and a (battery backed) RTC clock with it's own 32768 Hz crystal oscillator.
+      MCG gives the user a wide choice of system and peripheral clock source(s) that can be
+      external clock(s), internal clocks, a PLL or the FLL. An external or on-chip
+      oscillator can be used as a system clock or as a reference for PLL/FLL oscillator(s).
+      </para>
+      <note><para> In the documentation of Kinetis parts with two oscillators, <emphasis>OSC</emphasis>
+      and <emphasis>PLL</emphasis> are described as <emphasis>OSC0</emphasis> and <emphasis>PLL0</emphasis> respectively.
+      </para></note>
+      <para>
+      Clocking component <literal>CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING</literal> provides some expert
+      functionality in order to facilitate clock system configuration. Normally, the user sets requirements:
+      clock source, clock reference, desired core frequency and upper limits for peripheral
+      clock frequencies. The component automatically calculates MCG and other peripheral register
+      settings in order to achieve the required clock frequencies. This setting is not always perfect but
+      fits (exactly or close) for commonly used frequencies. If necessary, the user can fine tune the
+      clock settings interactively using the eCos Configuration Tool.
+      The two clock sources are named:
+      </para>
+      <variablelist>
+        <varlistentry>
+          <term>System clock</term>
+          <listitem><para>The clock source that provides the clock for the Cortex-M core.
+            It may also provide the clock for some peripherals.
+            </para></listitem></varlistentry>
+        <varlistentry>
+          <term>Auxiliary clock</term>
+          <listitem><para>This is optional and may provide a clock for peripherals but not for the Cortex-M core.
+            </para></listitem></varlistentry>
+      </variablelist>
+      <para>
+      The user can select which source is the system clock. The choices for system clock are: <emphasis>PLL</emphasis>,
+      <emphasis>FLL</emphasis>, <emphasis>External reference clock</emphasis> and, when available, <emphasis>PLL1</emphasis>.
+      The auxiliary clock, when available is: <emphasis>PLL</emphasis> if <emphasis>PLL1</emphasis> is selected 
+      for system the clock or <emphasis>PLL1</emphasis> if any other source is selected for the system clock.
+      </para>
+    </refsect2>
+    <refsect2 id="kinetis-var-memory"><title>Memory layouts</title>
+      <para>
+      The memory layouts and startup types which don't employ external memory should be applicable to all
+      Kinetis platforms so they are defined and maintained at the variant level.
+      This is somewhat different than common eCos practice but has some advantages brought by universal,
+      single copy linker scripts for single chip configurations. The linker scripts are further enhanced/generalized
+      by utilization of macros provided by CDL and calculated on the basis of the
+      <link linkend="kinetis-var-cpu-select">selected Kinetis part</link>.
+      </para>
+      <refsect3 id="kinetis-var-memory-ldscript-location"><title>Variant Linker 
+      Script Location</title>
+      <para>
+      Variant linker scripts are found at:
+      <filename class="directory">hal/kinetis/var/&lt;version&gt;/include/pkgconf</filename>
+      </para>
+      </refsect3>
+      <refsect3 id="kinetis-var-memory-ldscript-naming"><title>Linker Script Naming</title>
+      <para>
+      Linker script file names are composed of segments
+      <filename>mlt_kinetis_&lt;NVM&gt;_&lt;SRAM&gt;_&lt;STARTUP&gt;[_&lt;PLF&gt;].ldi</filename>
+      where <filename>PLF</filename> is an optional extension for platform specific scripts and
+      other segments have meanings as described in the following table.
+      </para>
+      <table frame="all" id="kinetis-var-table-ldscript-naming"><title>Linker script name segments</title>
+        <tgroup cols="3" align="center">
+          <colspec colnum="1" colname="segment" colwidth="1*" >
+          <colspec colnum="2" colname="desc" colwidth="2*" >
+          <colspec colnum="3" colname="values" colwidth="1*" >
+          <thead>
+            <row>
+              <entry>Segment</entry>
+              <entry>Description</entry>
+              <entry>Values</entry>
+            </row>
+          </thead>
+          <tbody>
+            <row>
+              <entry><filename>NVM</filename></entry>
+              <entry>Kinetis non-volatile memory configuration</entry>
+              <entry>
+              <filename>flash</filename>,
+              <filename>flexnvm</filename>
+              </entry>
+            </row>
+            <row>
+              <entry><filename>SRAM</filename></entry>
+              <entry>SRAM memory sectioning</entry>
+              <entry>
+              <filename>unisram</filename>,
+              <filename>sram2s</filename>
+              </entry>
+            </row>
+            <row>
+              <entry><filename>STARTUP</filename></entry>
+              <entry>Startup type</entry>
+              <entry>
+              <filename>rom</filename>,
+              <filename>sram</filename>
+              </entry>
+            </row>
+          </tbody>
+        </tgroup>
+      </table>
+      <para>
+      <note><para>Never attempt to flash Kinetis with an image for SRAM startup. SRAM startup images
+      do not contain a <literal>.flash_conf</literal> section so random contents may be written in 
+      flash protection area and lock your Kinetis device. This lock-out can be permanent.
+      </para></note>
+      </para>
+      </refsect3>
+      <refsect3 id="kinetis-var-memory-plf-spec"><title>Platform Specific Memory Layouts</title>
+      <para>
+      Platforms, if needed, can provide their own layouts in addition to the variant ones. Typically
+      they will cover systems with external memory. The <link linkend="kinetis-var-startup">
+      startup type</link> implicitly determines whether variant and platform defined
+      layout shall be used.
+      </para>
+      </refsect3>
+      <refsect3 id="kinetis-var-memory-sram"><title>On-chip SRAM</title>
+      <para>
+      Kinetis on chip SRAM memory consists of two equal banks that occupy consecutive locations anchored
+      below and above <literal>0x20000000</literal>. This fact is reflected in memory layout scripts.
+      There are linker scripts that treat SRAM as a single section (<filename>unisram</filename>) or as
+      2 separate sections (<filename>sram2s</filename>).
+      </para>
+      </refsect3>
+      <refsect3 id="kinetis-var-memory-flash"><title>On-chip FLASH</title>
+      <para>
+      Kinetis on-chip flash contains a special area <literal>[0x400-0x40F]</literal> 
+      that holds the flash security configuration. In order to preserve this area from 
+      accidental writing and at the same time provide regular access,
+      a custom linker section <literal>.flash_conf</literal> is created. In addition, in order
+      to utilize the FLASH pool below <literal>0x400</literal> the <emphasis>USER_SECTION</emphasis> 
+      <literal>.kinetis_misc</literal> is defined. This section typically contains 
+      code parts from <filename>kinetis_misc.c</filename>.
+      </para>
+      </refsect3>
+      <refsect3 id="kinetis-var-memory-cache"><title>Cache</title>
+      <para>
+      Kinetis members with operating frequencies of 120 MHz and 150 MHz are equipped with cache memory.
+      Due to the Harvard architecture, there are two cache memories connected to code 
+      - <emphasis>PC</emphasis> and system - <emphasis>PS</emphasis> buses respectively.
+      Although both modules can cache both instructions and data (unified caches), with the provided
+      memory they act as instruction (<emphasis>PC</emphasis>) and data (<emphasis>PS</emphasis>) caches.
+      </para>
+      <para>
+      A common caching issue is sharing memory resources with bus masters such as DMA, Ethernet controller, etc.
+      In order to keep shared data such as buffers and transfer control descriptors consistent,
+      cached data have to be flushed and/or invalidated. An alternative approach, used here is usage of
+      non-cachable memory for shared data. <literal>CYGHWR_HAL_NON_CACHABLE</literal> provides for
+      the configuration of non-cachable memory. If some bus masters have provision for non-cache able memory,
+      such configuration options can be parenthed by <literal>CYGHWR_HAL_NON_CACHABLE</literal>.
+      </para>
+      </refsect3>
+      </refsect2>
+      <refsect2 id="kinetis-var-startup"><title>Startup types</title>
+        <para>
+        There are <emphasis>two levels</emphasis> of startup type:
+        </para>
+        <variablelist>
+          <varlistentry>
+            <term>Variant <literal>CYG_HAL_STARTUP_VAR</literal></term>
+            <listitem><para>This is always present and provides startup
+              types for systems without external memory.
+              </para></listitem></varlistentry>
+          <varlistentry>
+            <term>Platform <literal>CYG_HAL_STARTUP_PLF</literal></term>
+            <listitem><para>This is optional and is 
+              provided by a platform package. Typically it provides startup types for systems
+              that employ external memory.
+              </para></listitem></varlistentry>
+        </variablelist>
+        <para>
+        </para>
+        <para>
+        When present, the platform startup overloads the variant startup and has precedence over it.
+        User can activate the variant startup by setting platform startup to
+        <literal>ByVariant</literal>.
+        </para>
+        <refsect3 id="kinetis-var-startup-byvariant"><title>Startup types provided variant</title>
+        <para>
+        The following startup types are provided for Kinetis at the variant level:
+        </para>
+        <variablelist>
+          <varlistentry>
+            <term><literal>ROM</literal></term>
+            <listitem><para>Normal startup for stand-alone operation. eCos image has to be flashed
+              in internal flash;
+              </para></listitem></varlistentry>
+          <varlistentry>
+            <term><literal>SRAM</literal></term>
+            <listitem><para>Image is loaded in internal SRAM by means of JTAG/SWD and executed
+              under debugger control.
+              </para></listitem></varlistentry>
+        </variablelist>      
+        <note><para>(IMPORTANT) Never, ever attempt to flash Kinetis with an image for SRAM startup.
+        SRAM startup images do not contain a <literal>.flash_conf</literal> section so random contents
+        may be written to the flash protection area and lock your Kinetis device. This lock-out can be permanent.
+        </para></note>
+        </refsect3>
+      </refsect2>
+      <refsect2 id="kinetis-interrupt-priority-scheme"><title>Interrupt priority scheme</title>
+        <para>
+        In case of multiple simultaneous interrupts, interrupt service request resolution is based
+        on a relative comparison of interrupt priorities, rather than on individual interrupt priority values.
+        <emphasis>Interrupt priority scheme</emphasis> gives a consolidated overview and control
+        of priorities of all interrupt sources. Interrupt priorities can be provided by either variant
+        <literal>CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR</literal>
+        or platform <literal>CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME</literal>.
+        </para>
+      </refsect2>
+    </refsect1>
+    
+  </refentry>
+  
+  <!--</part>-->
diff --git a/packages/hal/cortexm/kinetis/var/current/doc/kinetis_begin.sgml b/packages/hal/cortexm/kinetis/var/current/doc/kinetis_begin.sgml
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/doc/kinetis_begin.sgml
@@ -0,0 +1,37 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     kinetis_begin.sgml                                          -->
+<!--                                                                 -->
+<!--     Kinetis documentation.                                      -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2012 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2012/01/10                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>
diff --git a/packages/hal/cortexm/kinetis/var/current/doc/kinetis_end.sgml b/packages/hal/cortexm/kinetis/var/current/doc/kinetis_end.sgml
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/doc/kinetis_end.sgml
@@ -0,0 +1,37 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     kinetis_end.sgml                                             -->
+<!--                                                                 -->
+<!--     Kinetis documentation.                                      -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2012 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2012/01/10                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+</part>
diff --git a/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h b/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h
@@ -0,0 +1,282 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+//=============================================================================
+//
+//      hal_cache.h
+//
+//      HAL cache control API
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour, ilijak
+// Contributors:
+// Date:         2012-05-02
+// Purpose:      Cache control API
+// Description:  The macros defined here provide the HAL APIs for handling
+//               cache control operations.
+//
+// Usage:
+//               #include <cyg/hal/hal_cache.h>
+//               ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//-----------------------------------------------------------------------------
+// Cache dimensions
+#ifdef CYGINT_HAL_CACHE
+
+// Data cache
+#define HAL_DCACHE_SIZE                 8192    // Size of data cache in bytes
+#define HAL_DCACHE_LINE_SIZE            16      // Size of a data cache line
+#define HAL_DCACHE_WAYS                 2       // Associativity of the cache
+
+// Instruction cache
+#define HAL_ICACHE_SIZE                 8192    // Size of cache in bytes
+#define HAL_ICACHE_LINE_SIZE            16      // Size of a cache line
+#define HAL_ICACHE_WAYS                 2       // Associativity of the cache
+
+#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
+
+#include <cyg/hal/var_io.h>
+#include <cyg/hal/var_io_lmem.h>
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE() HAL_CORTEXM_KINETIS_CACHE_PS_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE() HAL_CORTEXM_KINETIS_CACHE_PS_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL() HAL_CORTEXM_KINETIS_CACHE_PS_INVALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC() HAL_CORTEXM_KINETIS_CACHE_PS_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL() HAL_CORTEXM_KINETIS_CACHE_PS_CLEAR()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_)                         \
+    CYG_MACRO_START                                            \
+        (_state_) = HAL_CORTEXM_KINETIS_CACHE_PS_IS_ENABLED(); \
+    CYG_MACRO_END
+
+// Invalidate cache lines in the given range without writing to memory.
+#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )                  \
+            HAL_CORTEXM_KINETIS_CACHE_PS_INVALIDATE(_base_, _size_)
+
+// Write dirty cache lines to memory and invalidate the cache entries
+#define HAL_DCACHE_FLUSH( _base_ , _size_ )                  \
+            HAL_CORTEXM_KINETIS_CACHE_PS_CLR(_base_, _size_)
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE() HAL_CORTEXM_KINETIS_CACHE_PC_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE() HAL_CORTEXM_KINETIS_CACHE_PC_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL() HAL_CORTEXM_KINETIS_CACHE_PC_INVALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC() HAL_CORTEXM_KINETIS_CACHE_PC_SYNC()
+
+// Purge contents of data cache
+#define HAL_ICACHE_PURGE_ALL() HAL_CORTEXM_KINETIS_CACHE_PC_CLEAR()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_)                         \
+    CYG_MACRO_START                                            \
+        (_state_) = HAL_CORTEXM_KINETIS_CACHE_PC_IS_ENABLED(); \
+    CYG_MACRO_END
+
+// Set the instruction cache refill burst size
+//#define HAL_ICACHE_BURST_SIZE(_size_)
+
+// Load the contents of the given address range into the instruction cache
+// and then lock the cache so that it stays there.
+//#define HAL_ICACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_ICACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_ICACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Instruction cache line control
+
+// Invalidate cache lines in the given range without writing to memory.
+#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )                  \
+            HAL_CORTEXM_KINETIS_CACHE_PC_INVALIDATE(_base_, _size_)
+
+#else // CYGINT_HAL_CACHE
+
+// Data cache
+//#define HAL_DCACHE_SIZE                 0     // Size of data cache in bytes
+//#define HAL_DCACHE_LINE_SIZE            0     // Size of a data cache line
+//#define HAL_DCACHE_WAYS                 0      // Associativity of the cache
+
+// Instruction cache
+//#define HAL_ICACHE_SIZE                 0     // Size of cache in bytes
+//#define HAL_ICACHE_LINE_SIZE            0      // Size of a cache line
+//#define HAL_ICACHE_WAYS                 0      // Associativity of the cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_) \
+    CYG_MACRO_START                    \
+    (_state_) = 0;                     \
+    CYG_MACRO_END
+
+// Set the data cache refill burst size
+//#define HAL_DCACHE_BURST_SIZE(_size_)
+
+// Set the data cache write mode
+//#define HAL_DCACHE_WRITE_MODE( _mode_ )
+
+//#define HAL_DCACHE_WRITETHRU_MODE       0
+//#define HAL_DCACHE_WRITEBACK_MODE       1
+
+// Load the contents of the given address range into the data cache
+// and then lock the cache so that it stays there.
+//#define HAL_DCACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_DCACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_DCACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Data cache line control
+
+// Allocate cache lines for the given address range without reading its
+// contents from memory.
+//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory and invalidate the cache entries
+// for the given address range.
+#define HAL_DCACHE_FLUSH( _base_ , _size_ )
+
+// Invalidate cache lines in the given range without writing to memory.
+#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory for the given address range.
+//#define HAL_DCACHE_STORE( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of reading
+// from it later.
+//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of writing
+// to it later.
+//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
+
+// Allocate and zero the cache lines associated with the given range.
+//#define HAL_DCACHE_ZERO( _base_ , _size_ )
+
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_) \
+    CYG_MACRO_START                    \
+        (_state_) = 0;                 \
+    CYG_MACRO_END
+
+// Set the instruction cache refill burst size
+//#define HAL_ICACHE_BURST_SIZE(_size_)
+
+// Load the contents of the given address range into the instruction cache
+// and then lock the cache so that it stays there.
+//#define HAL_ICACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_ICACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_ICACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Instruction cache line control
+
+// Invalidate cache lines in the given range without writing to memory.
+#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
+
+#endif // CYGINT_HAL_CACHE
+
+// End of hal_cache.h
+#endif // CYGONCE_HAL_CACHE_H
diff --git a/packages/hal/cortexm/kinetis/var/current/include/hal_diag.h b/packages/hal/cortexm/kinetis/var/current/include/hal_diag.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/hal_diag.h
@@ -0,0 +1,92 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+//=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL diagnostics
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      nickg
+// Contributor(s): ilijak
+// Date:           2011-02-05
+// Purpose:        HAL diagnostics
+// Description: 
+// Usage:          #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_if.h>
+
+//-----------------------------------------------------------------------------
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+#define HAL_DIAG_INIT()          hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_)  hal_if_diag_read_char(&_c_)
+
+#else
+
+__externC void hal_plf_diag_init(void);
+__externC void hal_plf_diag_putc(char);
+__externC cyg_uint8 hal_plf_diag_getc(void);
+
+# ifndef HAL_DIAG_INIT
+#  define HAL_DIAG_INIT() hal_plf_diag_init()
+# endif
+
+# ifndef HAL_DIAG_WRITE_CHAR
+#  define HAL_DIAG_WRITE_CHAR(__c) hal_plf_diag_putc(__c)
+# endif
+
+# ifndef HAL_DIAG_READ_CHAR
+#  define HAL_DIAG_READ_CHAR(__c) (__c) = hal_plf_diag_getc()
+# endif
+
+#endif
+
+
+//-----------------------------------------------------------------------------
+// end of hal_diag.h
+#endif // CYGONCE_HAL_DIAG_H
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.h b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.h
@@ -0,0 +1,26 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x20000000)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi
@@ -0,0 +1,45 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE
+    ram  : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    USER_SECTION (code_sram, sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA)
+    SECTION_data (ram, 0x20000000, FOLLOWING (.got))
+    SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.h b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.h
@@ -0,0 +1,22 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram_u (0x20000000)
+#define CYGMEM_REGION_sram_u_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_u_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram_u+CYGMEM_REGION_sram_u_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi
@@ -0,0 +1,35 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram_l  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE
+    sram_u  : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (sram_l, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA)
+    SECTION_RELOCS (sram_l, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (sram_l, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (sram_l, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (sram_u, 0x20000000, LMA_EQ_VMA)
+    SECTION_rodata1 (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.h b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.h
@@ -0,0 +1,22 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.ldi b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.ldi
@@ -0,0 +1,43 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got))
+    SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.h b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.h
@@ -0,0 +1,18 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.ldi b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.ldi
@@ -0,0 +1,34 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (ram, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.h b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.h
@@ -0,0 +1,45 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x20000000)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+# define CYGMEM_REGION_flexnvm (0x10000000)
+# define CYGMEM_REGION_flexnvm_SIZE (CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE)
+# define CYGMEM_REGION_flexnvm_ATTR (CYGMEM_REGION_ATTR_R)
+#endif
+
+#if defined(CYGHWR_HAL_CORTEXM_KINETIS_EEE) && CYGHWR_HAL_CORTEXM_KINETIS_EEE
+#  define CYGMEM_REGION_eeeprom0 (0x14000000)
+#  define CYGMEM_REGION_eeeprom0_SIZE (CYGHWR_HAL_KINETIS_EEE0_SIZE)
+#  define CYGMEM_REGION_eeeprom0_ATTR (CYGMEM_REGION_ATTR_R)
+# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1
+#  define CYGMEM_REGION_eeeprom1 (0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE )
+#  define CYGMEM_REGION_eeeprom1_SIZE (CYGHWR_HAL_KINETIS_EEE1_SIZE)
+#  define CYGMEM_REGION_eeeprom1_ATTR (CYGMEM_REGION_ATTR_R)
+# endif
+#else
+# define CYGMEM_REGION_flexram (0x14000000)
+# define CYGMEM_REGION_flexram_SIZE (CYGHWR_HAL_KINETIS_FLEXRAM_SIZE)
+# define CYGMEM_REGION_flexram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#endif
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi
@@ -0,0 +1,67 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE
+    ram  : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+    flexnvm : ORIGIN = 0x10000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE
+    eeeprom0 : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_EEE0_SIZE
+# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1
+    eeeprom1 : ORIGIN = 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE, LENGTH = CYGHWR_HAL_KINETIS_EEE1_SIZE
+# endif
+#else
+    flexram : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXRAM_SIZE
+#endif
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    USER_SECTION (code_sram, sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA)
+#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+    USER_SECTION(d_flash, flexnvm, 0x10000000 (NOLOAD), LMA_EQ_VMA)
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE
+    USER_SECTION(e_eeprom0, eeeprom0, 0x14000000 (NOLOAD), LMA_EQ_VMA)
+# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1
+    USER_SECTION(e_eeprom1, eeeprom1, 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE (NOLOAD), LMA_EQ_VMA)
+# endif
+#else
+    USER_SECTION(flex_ram, flexram, 0x14000000 (NOLOAD), LMA_EQ_VMA)
+#endif
+    SECTION_data (ram, 0x20000000, FOLLOWING (.got))
+    SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.h b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.h
@@ -0,0 +1,22 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram_u (0x20000000)
+#define CYGMEM_REGION_sram_u_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_u_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram_u+CYGMEM_REGION_sram_u_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi
@@ -0,0 +1,35 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram_l  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE
+    sram_u  : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, LMA_EQ_VMA)
+    SECTION_RELOCS (sram_l, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (sram_l, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (sram_l, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (sram_u, 0x20000000 , LMA_EQ_VMA)
+    SECTION_rodata1 (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.h b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.h
@@ -0,0 +1,42 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+
+#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+# define CYGMEM_REGION_flexnvm (0x10000000)
+# define CYGMEM_REGION_flexnvm_SIZE (CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE)
+# define CYGMEM_REGION_flexnvm_ATTR (CYGMEM_REGION_ATTR_R)
+#endif
+
+#if defined(CYGHWR_HAL_CORTEXM_KINETIS_EEE) && CYGHWR_HAL_CORTEXM_KINETIS_EEE
+#  define CYGMEM_REGION_eeeprom0 (0x14000000)
+#  define CYGMEM_REGION_eeeprom0_SIZE (CYGHWR_HAL_KINETIS_EEE0_SIZE)
+#  define CYGMEM_REGION_eeeprom0_ATTR (CYGMEM_REGION_ATTR_R)
+# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1
+#  define CYGMEM_REGION_eeeprom1 (0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE )
+#  define CYGMEM_REGION_eeeprom1_SIZE (CYGHWR_HAL_KINETIS_EEE1_SIZE)
+#  define CYGMEM_REGION_eeeprom1_ATTR (CYGMEM_REGION_ATTR_R)
+# endif
+#else
+# define CYGMEM_REGION_flexram (0x14000000)
+# define CYGMEM_REGION_flexram_SIZE (CYGHWR_HAL_KINETIS_FLEXRAM_SIZE)
+# define CYGMEM_REGION_flexram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#endif
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.ldi b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.ldi
@@ -0,0 +1,65 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+    flexnvm : ORIGIN = 0x10000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE
+    eeeprom0 : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_EEE0_SIZE
+# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1
+    eeeprom1 : ORIGIN = 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE, LENGTH = CYGHWR_HAL_KINETIS_EEE1_SIZE
+# endif
+#else
+    flexram : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXRAM_SIZE
+#endif
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+    USER_SECTION(d_flash, flexnvm, 0x10000000 (NOLOAD), LMA_EQ_VMA)
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE
+    USER_SECTION(e_eeprom0, eeeprom0, 0x14000000 (NOLOAD), LMA_EQ_VMA)
+# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1
+    USER_SECTION(e_eeprom1, eeeprom1, 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE (NOLOAD), LMA_EQ_VMA)
+# endif
+#else
+    USER_SECTION(flex_ram, flexram, 0x14000000 (NOLOAD), LMA_EQ_VMA)
+#endif
+    SECTION_data (ram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got))
+    SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.h b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.h
@@ -0,0 +1,18 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.ldi b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.ldi
@@ -0,0 +1,34 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (ram, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/packages/hal/cortexm/kinetis/var/current/include/plf_stub.h b/packages/hal/cortexm/kinetis/var/current/include/plf_stub.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/plf_stub.h
@@ -0,0 +1,88 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008,
+//               2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Contributors:jskov, gthomas, jlarmour
+// Date:        2008-07-30
+// Purpose:     Platform HAL stub support for Kinetis variant boards.
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+
+#include <cyg/hal/cortexm_stub.h>           // architecture stub support
+
+#include <cyg/hal/hal_io.h>
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+__externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+
+#define HAL_STUB_PLATFORM_INIT()              CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
diff --git a/packages/hal/cortexm/kinetis/var/current/include/var_arch.h b/packages/hal/cortexm/kinetis/var/current/include/var_arch.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/var_arch.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+//      var_arch.h
+//
+//      Kinetis variant architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, ilijak
+// Date:         2011-02-05
+// Purpose:      Kinetis variant architecture overrides
+// Description: 
+// Usage:        #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+
+#include <cyg/hal/plf_arch.h>
+
+
+//-----------------------------------------------------------------------------
+// end of var_arch.h
+#endif // CYGONCE_HAL_VAR_ARCH_H
diff --git a/packages/hal/cortexm/kinetis/var/current/include/var_intr.h b/packages/hal/cortexm/kinetis/var/current/include/var_intr.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/var_intr.h
@@ -0,0 +1,244 @@
+#ifndef CYGONCE_HAL_VAR_INTR_H
+#define CYGONCE_HAL_VAR_INTR_H
+//==========================================================================
+//
+//      var_intr.h
+//
+//      HAL Interrupt and clock assignments for Kinetis variants
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ilijak
+// Date:          2011-02-05
+// Purpose:       Define Interrupt support
+// Description:   The interrupt specifics for Freescale Kinetis variants are
+//                defined here.
+//
+// Usage:         #include <cyg/hal/var_intr.h>
+//                However applications should include using <cyg/hal/hal_intr.h>
+//                instead to allow for platform overrides.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/plf_intr.h>
+
+//==========================================================================
+
+typedef enum {
+    CYGNUM_HAL_INTERRUPT_DMA0
+        = CYGNUM_HAL_INTERRUPT_EXTERNAL,  // DMA Channel 0 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA1,            // DMA Channel 1 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA2,            // DMA Channel 2 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA3,            // DMA Channel 3 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA4,            // DMA Channel 4 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA5,            // DMA Channel 5 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA6,            // DMA Channel 6 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA7,            // DMA Channel 7 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA8,            // DMA Channel 8 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA9,            // DMA Channel 9 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA10,           // DMA Channel 10 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA11,           // DMA Channel 11 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA12,           // DMA Channel 12 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA13,           // DMA Channel 13 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA14,           // DMA Channel 14 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA15,           // DMA Channel 15 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA_ERROR,       // DMA Error Int
+    CYGNUM_HAL_INTERRUPT_MCM,             // Normal Int
+    CYGNUM_HAL_INTERRUPT_FTFL,            // FTFL Int
+    CYGNUM_HAL_INTERRUPT_READ_COLLISION,  // Read Collision Int
+    CYGNUM_HAL_INTERRUPT_LVD_LVW,         // Low Volt Detect, Low Volt Warn
+    CYGNUM_HAL_INTERRUPT_LLW,             // Low Leakage Wakeup
+    CYGNUM_HAL_INTERRUPT_WDOG,            // WDOG Int
+    CYGNUM_HAL_INTERRUPT_RNGB,            // RNGB Int
+    CYGNUM_HAL_INTERRUPT_I2C0,            // I2C0 int
+    CYGNUM_HAL_INTERRUPT_I2C1,            // I2C1 int
+    CYGNUM_HAL_INTERRUPT_SPI0,            // SPI0 Int
+    CYGNUM_HAL_INTERRUPT_SPI1,            // SPI1 Int
+    CYGNUM_HAL_INTERRUPT_SPI2,            // SPI2 Int
+    CYGNUM_HAL_INTERRUPT_CAN0_ORED_MESSAGE_BUFFER,// CAN0 OR'd Msg Buffs Int
+    CYGNUM_HAL_INTERRUPT_CAN0_BUS_OFF,    // CAN0 Bus Off Int
+    CYGNUM_HAL_INTERRUPT_CAN0_ERROR,      // CAN0 Error Int
+    CYGNUM_HAL_INTERRUPT_CAN0_TX_WARNING, // CAN0 Tx Warning Int
+    CYGNUM_HAL_INTERRUPT_CAN0_RX_WARNING, // CAN0 Rx Warning Int
+    CYGNUM_HAL_INTERRUPT_CAN0_WAKE_UP,    // CAN0 Wake Up Int
+    CYGNUM_HAL_INTERRUPT_CAN0_IMEU,       // CAN0 Ind. Match El Update (IMEU) Int
+    CYGNUM_HAL_INTERRUPT_CAN0_LOST_RX,    // CAN0 Lost Receive Int
+    CYGNUM_HAL_INTERRUPT_CAN1_ORED_MESSAGE_BUFFER, // CAN1 OR'd Msg Buffs Int
+    CYGNUM_HAL_INTERRUPT_CAN1_BUS_OFF,     // CAN1 Bus Off Int
+    CYGNUM_HAL_INTERRUPT_CAN1_ERROR,      // CAN1 Error Int
+    CYGNUM_HAL_INTERRUPT_CAN1_TX_WARNING, // CAN1 Tx Warning Int
+    CYGNUM_HAL_INTERRUPT_CAN1_RX_WARNING, // CAN1 Rx Warning Int
+    CYGNUM_HAL_INTERRUPT_CAN1_WAKE_UP,    // CAN1 Wake Up Int
+    CYGNUM_HAL_INTERRUPT_CAN1_IMEU,       // CAN1 Ind. Match El Update (IMEU) Int
+    CYGNUM_HAL_INTERRUPT_CAN1_LOST_RX,    // CAN1 Lost Receive Int
+    CYGNUM_HAL_INTERRUPT_UART0_RX_TX,     // UART0 Receive/Transmit int
+    CYGNUM_HAL_INTERRUPT_UART0_ERR,       // UART0 Error int
+    CYGNUM_HAL_INTERRUPT_UART1_RX_TX,     // UART1 Receive/Transmit int
+    CYGNUM_HAL_INTERRUPT_UART1_ERR,       // UART1 Error int
+    CYGNUM_HAL_INTERRUPT_UART2_RX_TX,     // UART2 Receive/Transmit int
+    CYGNUM_HAL_INTERRUPT_UART2_ERR,       // UART2 Error int
+    CYGNUM_HAL_INTERRUPT_UART3_RX_TX,     // UART3 Receive/Transmit int
+    CYGNUM_HAL_INTERRUPT_UART3_ERR,       // UART3 Error int
+    CYGNUM_HAL_INTERRUPT_UART4_RX_TX,     // UART4 Receive/Transmit int
+    CYGNUM_HAL_INTERRUPT_UART4_ERR,       // UART4 Error int
+    CYGNUM_HAL_INTERRUPT_UART5_RX_TX,     // UART5 Receive/Transmit int
+    CYGNUM_HAL_INTERRUPT_UART5_ERR,       // UART5 Error int
+    CYGNUM_HAL_INTERRUPT_ADC0,            // ADC0 int
+    CYGNUM_HAL_INTERRUPT_ADC1,            // ADC1 int
+    CYGNUM_HAL_INTERRUPT_CMP0,            // CMP0 int
+    CYGNUM_HAL_INTERRUPT_CMP1,            // CMP1 int
+    CYGNUM_HAL_INTERRUPT_CMP2,            // CMP2 int
+    CYGNUM_HAL_INTERRUPT_FTM0,            // FTM0 fault, overflow and channels int
+    CYGNUM_HAL_INTERRUPT_FTM1,            // FTM1 fault, overflow and channels int
+    CYGNUM_HAL_INTERRUPT_FTM2,            // FTM2 fault, overflow and channels int
+    CYGNUM_HAL_INTERRUPT_CMT,             // CMT int
+    CYGNUM_HAL_INTERRUPT_RTC_RTC,         // RTC int
+    CYGNUM_HAL_INTERRUPT_RTC_SECONDS,     // RTC seconds interrupt
+    CYGNUM_HAL_INTERRUPT_PIT0,            // PIT timer channel 0 int
+    CYGNUM_HAL_INTERRUPT_PIT1,            // PIT timer channel 1 int
+    CYGNUM_HAL_INTERRUPT_PIT2,            // PIT timer channel 2 int
+    CYGNUM_HAL_INTERRUPT_PIT3,            // PIT timer channel 3 int
+    CYGNUM_HAL_INTERRUPT_PDB0,            // PDB0 Int
+    CYGNUM_HAL_INTERRUPT_USB0,            // USB0 int
+    CYGNUM_HAL_INTERRUPT_USBDCD,          // USBDCD Int
+    CYGNUM_HAL_INTERRUPT_ENET_1588_TIMER, // ENET MAC IEEE 1588 Timer Int
+    CYGNUM_HAL_INTERRUPT_ENET_TRANSMIT,   // ENET MAC Transmit Int
+    CYGNUM_HAL_INTERRUPT_ENET_RECEIVE,    // ENET MAC Receive Int
+    CYGNUM_HAL_INTERRUPT_ENET_ERROR,      // ENET MAC Error and miscelaneous Int
+    CYGNUM_HAL_INTERRUPT_I2S0,            // I2S0 Int
+    CYGNUM_HAL_INTERRUPT_SDHC,            // SDHC Int
+    CYGNUM_HAL_INTERRUPT_DAC0,            // DAC0 int
+    CYGNUM_HAL_INTERRUPT_DAC1,            // DAC1 int
+    CYGNUM_HAL_INTERRUPT_TSI0,            // TSI0 Int
+    CYGNUM_HAL_INTERRUPT_MCG,             // MCG Int
+    CYGNUM_HAL_INTERRUPT_LPTIMER,         // LPTimer int
+    CYGNUM_HAL_INTERRUPT_LCD,             // Segment LCD int
+    CYGNUM_HAL_INTERRUPT_PORTA,           // Port A int
+    CYGNUM_HAL_INTERRUPT_PORTB,           // Port B int
+    CYGNUM_HAL_INTERRUPT_PORTC,           // Port C int
+    CYGNUM_HAL_INTERRUPT_PORTD,           // Port D int
+    CYGNUM_HAL_INTERRUPT_PORTE,           // Port E int
+    CYGNUM_HAL_INTERRUPT_PORTF,           // Port F interrupt
+    CYGNUM_HAL_INTERRUPT_DDR,             // DDR interrupt
+    CYGNUM_HAL_INTERRUPT_SWI,             // Software interrupt
+    CYGNUM_HAL_INTERRUPT_NFC,             // NAND flash controller interrupt
+    CYGNUM_HAL_INTERRUPT_USBHS,           // USB high speed OTG interrupt
+    CYGNUM_HAL_INTERRUPT_GLCD,            // Graphical LCD interrupt
+    CYGNUM_HAL_INTERRUPT_CMP3,            // CMP3 interrupt
+    CYGNUM_HAL_INTERRUPT_TAMPER,          // Tamper detect interrupt
+    CYGNUM_HAL_INTERRUPT_Reserved116,     // Reserved interrupt 116
+    CYGNUM_HAL_INTERRUPT_FTM3,            // FTM3 fault, overflow and channels interrupt
+    CYGNUM_HAL_INTERRUPT_ADC2,            // ADC2 interrupt
+    CYGNUM_HAL_INTERRUPT_ADC3,            // ADC3 interrupt
+    CYGNUM_HAL_INTERRUPT_I2S1_TX,         // I2S1 transmit interrupt
+    CYGNUM_HAL_INTERRUPT_I2S1_RX          // I2S1 receive interrupt
+} KinetisExtInterrupt_e;
+
+// DMA16..31 share interrupt vectors with DMA0..15 respectively.
+
+#define    CYGNUM_HAL_INTERRUPT_DMA16  CYGNUM_HAL_INTERRUPT_DMA0
+#define    CYGNUM_HAL_INTERRUPT_DMA17  CYGNUM_HAL_INTERRUPT_DMA1
+#define    CYGNUM_HAL_INTERRUPT_DMA18  CYGNUM_HAL_INTERRUPT_DMA2
+#define    CYGNUM_HAL_INTERRUPT_DMA19  CYGNUM_HAL_INTERRUPT_DMA3
+#define    CYGNUM_HAL_INTERRUPT_DMA20  CYGNUM_HAL_INTERRUPT_DMA4
+#define    CYGNUM_HAL_INTERRUPT_DMA21  CYGNUM_HAL_INTERRUPT_DMA5
+#define    CYGNUM_HAL_INTERRUPT_DMA22  CYGNUM_HAL_INTERRUPT_DMA6
+#define    CYGNUM_HAL_INTERRUPT_DMA23  CYGNUM_HAL_INTERRUPT_DMA7
+#define    CYGNUM_HAL_INTERRUPT_DMA34  CYGNUM_HAL_INTERRUPT_DMA8
+#define    CYGNUM_HAL_INTERRUPT_DMA25  CYGNUM_HAL_INTERRUPT_DMA9
+#define    CYGNUM_HAL_INTERRUPT_DMA26  CYGNUM_HAL_INTERRUPT_DMA10
+#define    CYGNUM_HAL_INTERRUPT_DMA27  CYGNUM_HAL_INTERRUPT_DMA11
+#define    CYGNUM_HAL_INTERRUPT_DMA28  CYGNUM_HAL_INTERRUPT_DMA12
+#define    CYGNUM_HAL_INTERRUPT_DMA29  CYGNUM_HAL_INTERRUPT_DMA13
+#define    CYGNUM_HAL_INTERRUPT_DMA30  CYGNUM_HAL_INTERRUPT_DMA14
+#define    CYGNUM_HAL_INTERRUPT_DMA31  CYGNUM_HAL_INTERRUPT_DMA15
+
+#define CYGNUM_HAL_INTERRUPT_NVIC_MAX (CYGNUM_HAL_INTERRUPT_I2S1_RX)
+
+#define CYGNUM_HAL_ISR_MIN            0
+#define CYGNUM_HAL_ISR_MAX            CYGNUM_HAL_INTERRUPT_I2S1_RX
+#define CYGNUM_HAL_ISR_COUNT          (CYGNUM_HAL_ISR_MAX + 1)
+
+#define CYGNUM_HAL_VSR_MIN            0
+#ifndef CYGNUM_HAL_VSR_MAX
+# define CYGNUM_HAL_VSR_MAX           (CYGNUM_HAL_VECTOR_SYS_TICK+ \
+                                       CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#endif
+
+#define CYGNUM_HAL_VSR_COUNT          (CYGNUM_HAL_VSR_MAX+1)
+
+//==========================================================================
+// Interrupt mask and config for variant-specific devices
+
+// PORT Pin interrupts
+
+#define CYGHWR_HAL_KINETIS_PIN_IRQ_VECTOR(__pin) \
+    (CYGNUM_HAL_INTERRUPT_PORTA + CYGHWR_HAL_KINETIS_PIN_PORT(__pin))
+
+//===========================================================================
+// Interrupt resources exported by HAL to device drivers
+
+// Export Interrupt vectors to serial driver.
+
+#define CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART0_RX_TX
+#define CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART1_RX_TX
+#define CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART2_RX_TX
+#define CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART3_RX_TX
+#define CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART4_RX_TX
+#define CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART5_RX_TX
+
+// Export Interrupt vectors to ENET driver.
+
+#define CYGNUM_FREESCALE_ENET0_1588_TIMER_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_ENET_1588_TIMER
+#define CYGNUM_FREESCALE_ENET0_TRANSMIT_INT_VECTOR   \
+            CYGNUM_HAL_INTERRUPT_ENET_TRANSMIT
+#define CYGNUM_FREESCALE_ENET0_RECEIVE_INT_VECTOR    \
+            CYGNUM_HAL_INTERRUPT_ENET_RECEIVE
+#define CYGNUM_FREESCALE_ENET0_ERROR_INT_VECTOR      \
+            CYGNUM_HAL_INTERRUPT_ENET_ERROR
+
+//----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_INTR_H
+// EOF var_intr.h
diff --git a/packages/hal/cortexm/kinetis/var/current/include/var_io.h b/packages/hal/cortexm/kinetis/var/current/include/var_io.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/var_io.h
@@ -0,0 +1,1206 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//===========================================================================
+//
+//      var_io.h
+//
+//      Variant specific registers
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2011-02-05
+// Purpose:       Kinetis variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+#include <pkgconf/hal_cortexm_kinetis.h>
+
+#include <cyg/hal/plf_io.h>
+
+//===========================================================================
+// Cortex-M architecture
+//---------------------------------------------------------------------------
+//--------------------------------------------------------------------------
+// Cortex-M architecture overrides
+//---------------------------------------------------------------------------
+// VTOR - Vector Table Offset Register
+#ifndef CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM
+#define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM (BIT_(29) -                       \
+                                           CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#endif
+
+//=============================================================================
+// Kinetis system configuration
+//---------------------------------------------------------------------------
+// Utilize Freescale Kinetis flash between startup vectors and 0x400
+// for misc funtions.
+#ifdef CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION
+# define CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR \
+         CYGBLD_ATTRIB_SECTION(".kinetis_misc")
+#else
+# define CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+#endif
+
+//===========================================================================
+// KINETIS FLASH configuration field
+//===========================================================================
+
+// Note: KINETIS FLASH configuration field must be present in Kinetis flash
+//       image and ocupy addresses 0x00000400 to 0x0000040f.
+
+typedef struct cyghwr_hal_kinetis_flash_conf_s {
+    cyg_uint8 backdoor_key[8]; // 0x400 .. 0x407
+    cyg_uint8 fprot[4];        // 0x408 .. 0x40b
+    cyg_uint8 fsec;            // 0x40c
+    cyg_uint8 fopt;            // 0x40d
+    cyg_uint8 feprot;          // 0x40e
+    cyg_uint8 fdprot;          // 0x40f
+} cyghwr_hal_kinetis_flash_conf_t;
+
+__externC const cyghwr_hal_kinetis_flash_conf_t *hal_kinetis_flash_conf_p( void );
+
+//===========================================================================
+// Kinetis Peripherals
+//---------------------------------------------------------------------------
+// Internal Flash
+
+typedef volatile struct cyghwr_hal_kinetis_flash_s {
+    cyg_uint8 fstat;    // Flash status register
+    cyg_uint8 fcnfg;    // Flash configuration register
+    cyg_uint8 fsec;     // Flash security register
+    cyg_uint8 fopt;     // Flash option register
+    cyg_uint8 fccob3;   // Flash common command object registers
+    cyg_uint8 fccob2;
+    cyg_uint8 fccob1;
+    cyg_uint8 fccob0;
+    cyg_uint8 fccob7;
+    cyg_uint8 fccob6;
+    cyg_uint8 fccob5;
+    cyg_uint8 fccob4;
+    cyg_uint8 fccobB;
+    cyg_uint8 fccobA;
+    cyg_uint8 fccob9;
+    cyg_uint8 fccob8;
+    cyg_uint8 fprot3;   // Program flash protection registers
+    cyg_uint8 fprot2;
+    cyg_uint8 fprot1;
+    cyg_uint8 fprot0;
+    cyg_uint8 reserved[2];
+    cyg_uint8 feprot;   // EEPROM Protection register
+    cyg_uint8 fdprot;   // Data flash protection register
+} cyghwr_hal_kinetis_flash_t;
+
+#define CYGHWR_HAL_KINETIS_FLASH_P ((cyghwr_hal_kinetis_flash_t *) 0x40020000)
+
+#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_CCIF_M           0x80
+#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_RDCOLERR_M       0x40
+#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_ACCERR_M         0x20
+#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_FPVIOL_M         0x10
+#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_MGSTAT0_M        0x01
+
+//---------------------------------------------------------------------------
+// Oscillator
+
+#define CYGHWR_HAL_KINETIS_OSC_CR          (0x40065000)
+#define CYGHWR_HAL_KINETIS_OSC_CR_P        ((volatile cyg_uint8*) 0x40065000)
+
+#define CYGHWR_HAL_KINETIS_OSC1_CR         (0x400E5000)
+#define CYGHWR_HAL_KINETIS_OSC1_CR_P       ((volatile cyg_uint8*) 0x400E5000)
+
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC16P_M      0x01
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC16P_S         0
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC8P_M       0x02
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC8P_S          1
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC4P_M       0x04
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC4P_S          2
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC2P_M       0x08
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC2P_S          3
+#define CYGHWR_HAL_KINETIS_OSC_CR_EREFSTEN_M   0x20
+#define CYGHWR_HAL_KINETIS_OSC_CR_EREFSTEN_S      5
+#define CYGHWR_HAL_KINETIS_OSC_CR_ERCLKEN_M    0x80
+#define CYGHWR_HAL_KINETIS_OSC_CR_ERCLKEN_S       7
+
+//---------------------------------------------------------------------------
+// MCG
+
+typedef volatile struct cyghwr_hal_kinetis_mcg_s {
+    cyg_uint8 c1;      // MCG Control 1 Register
+    cyg_uint8 c2;      // MCG Control 2 Register
+    cyg_uint8 c3;      // MCG Control 3 Register
+    cyg_uint8 c4;      // MCG Control 4 Register
+    cyg_uint8 c5;      // MCG Control 5 Register
+    cyg_uint8 c6;      // MCG Control 6 Register
+    cyg_uint8 status;  // MCG Status Register
+    cyg_uint8 mcg_res0;
+#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 1
+    cyg_uint8 atc;     // MCG Auto Trim Control Register
+#elif CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+    cyg_uint8 sc;     // MCG Status and Control Register
+#endif
+    cyg_uint8 mcg_res1;
+    cyg_uint8 atcvh;   // MCG Auto Trim Compare Value High Register
+    cyg_uint8 atcvl;   // MCG Auto Trim Compare Value Low Register
+#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+    cyg_uint8 c7;      // MCG Control 7 Register
+    cyg_uint8 c8;      // MCG Control 8 Register
+#endif
+#if CYGINT_HAL_CORTEXM_KINETIS_150
+    cyg_uint8 c10;     // MCG Control 10 Register
+    cyg_uint8 mcg_res2;
+    cyg_uint8 c11;     // MCG Control 11 Register
+    cyg_uint8 c12;     // MCG Control 12 Register
+    cyg_uint8 s2;      // MCG Status 2 Register
+#endif //CYGINT_HAL_CORTEXM_KINETIS_150
+} cyghwr_hal_kinetis_mcg_t;
+
+#define CYGHWR_HAL_KINETIS_MCG_P  ((cyghwr_hal_kinetis_mcg_t *)0x40064000)
+
+// C1 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C1_IREFSTEN_M    0x01
+#define CYGHWR_HAL_KINETIS_MCG_C1_IREFSTEN_S    0
+#define CYGHWR_HAL_KINETIS_MCG_C1_IRCLKEN_M     0x02
+#define CYGHWR_HAL_KINETIS_MCG_C1_IRCLKEN_S     1
+#define CYGHWR_HAL_KINETIS_MCG_C1_IREFS_M       0x4
+#define CYGHWR_HAL_KINETIS_MCG_C1_IREFS_S       2
+#define CYGHWR_HAL_KINETIS_MCG_C1_FRDIV_M       0x38
+#define CYGHWR_HAL_KINETIS_MCG_C1_FRDIV_S       3
+#define CYGHWR_HAL_KINETIS_MCG_C1_FRDIV(_div_)  \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C1_FRDIV_S, _div_)
+#define CYGHWR_HAL_KINETIS_MCG_C1_CLKS_M        0xC0
+#define CYGHWR_HAL_KINETIS_MCG_C1_CLKS_S        6
+#define CYGHWR_HAL_KINETIS_MCG_C1_CLKS(_clks_)  \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C1_CLKS_S, _clks_)
+enum {
+    CYGHWR_HAL_KINETIS_MCG_C1_CLKS_FLL_PLL,
+    CYGHWR_HAL_KINETIS_MCG_C1_CLKS_INT_REF,
+    CYGHWR_HAL_KINETIS_MCG_C1_CLKS_EXT_REF,
+    CYGHWR_HAL_KINETIS_MCG_C1_CLKS_RESERVED
+};
+// C2 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C2_IRCS_M        0x01
+#define CYGHWR_HAL_KINETIS_MCG_C2_IRCS_S        0
+#define CYGHWR_HAL_KINETIS_MCG_C2_LP_M          0x02
+#define CYGHWR_HAL_KINETIS_MCG_C2_LP_S          1
+#define CYGHWR_HAL_KINETIS_MCG_C2_EREFS_M       0x04
+#define CYGHWR_HAL_KINETIS_MCG_C2_EREFS_S       2
+#define CYGHWR_HAL_KINETIS_MCG_C2_HGO_M         0x08
+#define CYGHWR_HAL_KINETIS_MCG_C2_HGO_S         3
+#define CYGHWR_HAL_KINETIS_MCG_C2_RANGE_M       0x30
+#define CYGHWR_HAL_KINETIS_MCG_C2_RANGE_S       4
+#define CYGHWR_HAL_KINETIS_MCG_C2_RANGE(__v)    \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C2_RANGE_S, __v)
+
+#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+#define CYGHWR_HAL_KINETIS_MCG_C2_LOCRE0_M      0x80
+#define CYGHWR_HAL_KINETIS_MCG_C2_LOCRE0_S      7
+#endif
+// C3 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM_M      0xFF
+#define CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM_S      0
+#define CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM(__v)   \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM_S, __v)
+// C4 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C4_SCFTRIM_M     0x01
+#define CYGHWR_HAL_KINETIS_MCG_C4_SCFTRIM_S     0
+#define CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM_M      0x1E
+#define CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM_S      1
+#define CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM(__v)   \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS_M    0x60
+#define CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS_S    5
+#define CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS(__v) \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_C4_DMX32_M       0x80
+#define CYGHWR_HAL_KINETIS_MCG_C4_DMX32_S       7
+// C5 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_M       0x1F
+#define CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_S       0
+#define CYGHWR_HAL_KINETIS_MCG_C5_PRDIV(__v)    \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_M     0x20
+#define CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_S     5
+#define CYGHWR_HAL_KINETIS_MCG_C5_PLLCLKEN_M    0x40
+#define CYGHWR_HAL_KINETIS_MCG_C5_PLLCLKEN_S    6
+#if CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1
+# define CYGHWR_HAL_KINETIS_MCG_C5_PLLREFSEL0_M  0x80
+# define CYGHWR_HAL_KINETIS_MCG_C5_PLLREFSEL0_S  7
+#endif
+// C6 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C6_VDIV_M        0x1F
+#define CYGHWR_HAL_KINETIS_MCG_C6_VDIV_S        0
+#define CYGHWR_HAL_KINETIS_MCG_C6_VDIV(__v)     \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C6_VDIV_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_C6_CME_M         0x20
+#define CYGHWR_HAL_KINETIS_MCG_C6_CME_S         5
+#define CYGHWR_HAL_KINETIS_MCG_C6_PLLS_M        0x40
+#define CYGHWR_HAL_KINETIS_MCG_C6_PLLS_S        6
+#define CYGHWR_HAL_KINETIS_MCG_C6_LOLIE_M       0x80
+#define CYGHWR_HAL_KINETIS_MCG_C6_LOLIE_S       7
+// S Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_S_IRCST_M        0x01
+#define CYGHWR_HAL_KINETIS_MCG_S_IRCST_S        0
+#define CYGHWR_HAL_KINETIS_MCG_S_OSCINIT_M      0x02
+#define CYGHWR_HAL_KINETIS_MCG_S_OSCINIT_S      1
+#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_M        0x0C
+#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_S        2
+#define CYGHWR_HAL_KINETIS_MCG_S_CLKST(__v)     \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_S_CLKST_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_FLL  CYGHWR_HAL_KINETIS_MCG_S_CLKST(0)
+#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_INT  CYGHWR_HAL_KINETIS_MCG_S_CLKST(1)
+#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT  CYGHWR_HAL_KINETIS_MCG_S_CLKST(2)
+#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_PLL  CYGHWR_HAL_KINETIS_MCG_S_CLKST(3)
+#define CYGHWR_HAL_KINETIS_MCG_S_IREFST_M       0x10
+#define CYGHWR_HAL_KINETIS_MCG_S_IREFST_S       4
+#define CYGHWR_HAL_KINETIS_MCG_S_PLLST_M        0x20
+#define CYGHWR_HAL_KINETIS_MCG_S_PLLST_S        5
+#define CYGHWR_HAL_KINETIS_MCG_S_LOCK_M         0x40
+#define CYGHWR_HAL_KINETIS_MCG_S_LOCK_S         6
+#define CYGHWR_HAL_KINETIS_MCG_S_LOLS_M         0x80
+#define CYGHWR_HAL_KINETIS_MCG_S_LOLS_S         7
+
+#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 1
+// ATC Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMF_M       0x20
+#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMF_S       5
+#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMS_M       0x40
+#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMS_S       6
+#define CYGHWR_HAL_KINETIS_MCG_ATC_ATME_M       0x80
+#define CYGHWR_HAL_KINETIS_MCG_ATC_ATME_S       7
+#elif CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+// SC Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_SC_LOCS0_M       0x01
+#define CYGHWR_HAL_KINETIS_MCG_SC_LOCS0_S       0
+#define CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV_M      0x0E
+#define CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV_S      1
+#define CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV(__v) \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_SC_FLTPRSRV_M    0x10
+#define CYGHWR_HAL_KINETIS_MCG_SC_FLTPRSRV_S    4
+#define CYGHWR_HAL_KINETIS_MCG_SC_ATMF_M        0x20
+#define CYGHWR_HAL_KINETIS_MCG_SC_ATMF_S        5
+#define CYGHWR_HAL_KINETIS_MCG_SC_ATMS_M        0x40
+#define CYGHWR_HAL_KINETIS_MCG_SC_ATMS_S        6
+#define CYGHWR_HAL_KINETIS_MCG_SC_ATME_M        0x80
+#define CYGHWR_HAL_KINETIS_MCG_SC_ATME_S        7
+#endif //  CYGHWR_HAL_CORTEXM_KINETIS_REV
+// ATCVH Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH_M    0xFF
+#define CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH_S    0
+#define CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH(__v) \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH_S, __v)
+// ATCVL Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_M    0xFF
+#define CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_S    0
+#define CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL(__v) \
+VALUE_(CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_S, __v)
+
+#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+// C7 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C7_OSCSEL_M      0x1
+#define CYGHWR_HAL_KINETIS_MCG_C7_OSCSEL_S      0
+// C8 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C8_LOCS1_M       0x1
+#define CYGHWR_HAL_KINETIS_MCG_C8_LOCS1_S       0
+#define CYGHWR_HAL_KINETIS_MCG_C8_CME1_M        0x20
+#define CYGHWR_HAL_KINETIS_MCG_C8_CME1_S        5
+#define CYGHWR_HAL_KINETIS_MCG_C8_LOLRE_M       0x40
+#define CYGHWR_HAL_KINETIS_MCG_C8_LOLRE_S       6
+#define CYGHWR_HAL_KINETIS_MCG_C8_LOCRE1_M      0x80
+#define CYGHWR_HAL_KINETIS_MCG_C8_LOCRE1_S      7
+#endif // CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+
+#if CYGINT_HAL_CORTEXM_KINETIS_150
+
+// C10 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C10_EREFS1_M      0x04
+#define CYGHWR_HAL_KINETIS_MCG_C10_EREFS1_S      2
+#define CYGHWR_HAL_KINETIS_MCG_C10_HGO1_M        0x08
+#define CYGHWR_HAL_KINETIS_MCG_C10_HGO1_S        3
+#define CYGHWR_HAL_KINETIS_MCG_C10_RANGE1_M      0x30
+#define CYGHWR_HAL_KINETIS_MCG_C10_RANGE1_S      4
+#define CYGHWR_HAL_KINETIS_MCG_C10_RANGE1(__v)    \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C10_RANGE1_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_C10_LOCRE0_M      0x80
+#define CYGHWR_HAL_KINETIS_MCG_C10_LOCRE0_S      7
+// C11 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_M       0x7
+#define CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_S       0
+#define CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1(__v)    \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_M        0x10
+#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_S        4
+#define CYGHWR_HAL_KINETIS_MCG_C11_PLLSTEN1_M     0x20
+#define CYGHWR_HAL_KINETIS_MCG_C11_PLLSTEN1_S     5
+#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCLKEN1_M    0x40
+#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCLKEN1_S    6
+# define CYGHWR_HAL_KINETIS_MCG_C11_PLLREFSEL1_M  0x80
+# define CYGHWR_HAL_KINETIS_MCG_C11_PLLREFSEL1_S  7
+// C12 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_M        0x1F
+#define CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_S        0
+#define CYGHWR_HAL_KINETIS_MCG_C12_VDIV1(__v)     \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_C12_CME2_M         0x20
+#define CYGHWR_HAL_KINETIS_MCG_C12_CME2_S         5
+#define CYGHWR_HAL_KINETIS_MCG_C12_LOLIE1_M       0x80
+#define CYGHWR_HAL_KINETIS_MCG_C12_LOLIE1_S       7
+// S2 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_S2_LOCS2_M        0x01
+#define CYGHWR_HAL_KINETIS_MCG_S2_LOCS2_S        0
+#define CYGHWR_HAL_KINETIS_MCG_S2_OSCINIT1_M     0x02
+#define CYGHWR_HAL_KINETIS_MCG_S2_OSCINIT1_S     1
+#define CYGHWR_HAL_KINETIS_MCG_S2_PLLCST_M       0x10
+#define CYGHWR_HAL_KINETIS_MCG_S2_PLLCST_S       4
+#define CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_M        0x40
+#define CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_S        6
+#define CYGHWR_HAL_KINETIS_MCG_S2_LOLS1_M        0x80
+#define CYGHWR_HAL_KINETIS_MCG_S2_LOLS1_S        7
+
+#endif //CYGINT_HAL_CORTEXM_KINETIS_150
+
+
+//---------------------------------------------------------------------------
+// Real Time Clock
+
+typedef volatile struct cyghwr_hal_kinetis_rtc_s {
+    cyg_uint32 tsr;                    // Time Seconds Register
+    cyg_uint32 tpr;                    // Time Prescaler Register
+    cyg_uint32 tar;                    // Time Alarm Register
+    cyg_uint32 tcr;                    // Time Compensation Register
+    cyg_uint32 cr;                     // Control Register
+    cyg_uint32 sr;                     // Status Register
+    cyg_uint32 lr;                     // Lock Register
+    cyg_uint32 ier;                    // Enterrupt Enable Register
+    cyg_uint32 ttsr;                   // Tamper Times Seconds Register
+    cyg_uint32 mer;                    // Monotonic Enable Register
+    cyg_uint32 mclr;                   // Monotonic Counter Low Register
+    cyg_uint32 mchr;                   // Monotonic Counter High Register
+    cyg_uint32 ter;                    // Tamper Enable Register
+    cyg_uint32 tdr;                    // Tamper Detect Register
+    cyg_uint32 ttr;                    // Tamper Trim Register
+    cyg_uint32 tir;                    // Tamper Interrupt Register
+    cyg_uint8 reserved[1984];
+    cyg_uint32 war;                    // Write Access Register
+    cyg_uint32 rar;                    // Read Access Register
+} cyghwr_hal_kinetis_rtc_t;
+
+#define CYGHWR_HAL_KINETIS_RTC_P   ((cyghwr_hal_kinetis_rtc_t *)0x4003D000)
+
+#define CYGHWR_HAL_KINETIS_RTC_TCR_TCR_M (0x000000FF)
+#define CYGHWR_HAL_KINETIS_RTC_TCR_CIR_S 8
+#define CYGHWR_HAL_KINETIS_RTC_TCR_CIR(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_RTC_TCR_CIR_S, _div_)
+#define CYGHWR_HAL_KINETIS_RTC_TCR_CIC_S 16
+#define CYGHWR_HAL_KINETIS_RTC_TCR_TCV_S 24
+
+#define CYGHWR_HAL_KINETIS_RTC_CR_SWR  BIT_(0)
+#define CYGHWR_HAL_KINETIS_RTC_CR_WPE  BIT_(1)
+#define CYGHWR_HAL_KINETIS_RTC_CR_SUP  BIT_(2)
+#define CYGHWR_HAL_KINETIS_RTC_CR_UM   BIT_(3)
+#define CYGHWR_HAL_KINETIS_RTC_CR_OSCE BIT_(8)
+#define CYGHWR_HAL_KINETIS_RTC_CR_CLKO BIT_(9)
+#define CYGHWR_HAL_KINETIS_RTC_CR_SCP \
+        VALUE_(10, (CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP/2))
+
+#define CYGHWR_HAL_KINETIS_RTC_SR_TCE BIT_(4)
+#define CYGHWR_HAL_KINETIS_RTC_SR_TAF BIT_(2)
+#define CYGHWR_HAL_KINETIS_RTC_SR_TOF BIT_(1)
+#define CYGHWR_HAL_KINETIS_RTC_SR_TIF BIT_(0)
+
+//---------------------------------------------------------------------------
+// Watch dog
+
+// WDOG - Peripheral register structure
+typedef volatile struct CygHwr_HAL_Kinetis_wdog_s {
+    cyg_uint16 StCtrlH;    // Status and Control Register High
+    cyg_uint16 StCtrlL;    // Status and Control Register Low
+    cyg_uint16 ToValH;     // Time-out Value Register High
+    cyg_uint16 ToValL;     // Time-out Value Register Low
+    cyg_uint16 WinH;       // Window Register High
+    cyg_uint16 WinL;       // Window Register Low
+    cyg_uint16 Refresh;    // Refresh Register
+    cyg_uint16 Unlock;     // Unlock Register
+    cyg_uint16 TmrOutH;    // Timer Output Register High
+    cyg_uint16 TmrOutL;    // Timer Output Register Low
+    cyg_uint16 RstCnt;     // Reset Count Register
+    cyg_uint16 Presc;      // Prescaler Register
+} CygHwr_HAL_Kinetis_wdog_t;
+
+#define CYGHWR_HAL_KINETIS_WDOG_P ((CygHwr_HAL_Kinetis_wdog_t *)0x40052000)
+
+// STCTRLH Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WDOGEN_M          0x0001
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WDOGEN_S          0
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_CLKSRC_M          0x0002
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_CLKSRC_S          1
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_IRQRSTEN_M        0x0004
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_IRQRSTEN_S        2
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WINEN_M           0x0008
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WINEN_S           3
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_ALLOWUPDATE_M     0x0010
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_ALLOWUPDATE_S     4
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DBGEN_M           0x0020
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DBGEN_S           5
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STOPEN_M          0x0040
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STOPEN_S          6
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WAITEN_M          0x0080
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WAITEN_S          7
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STNDBYEN_M        0x0100
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STNDBYEN_S        8
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTWDOG_M        0x0400
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTWDOG_S        10
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTSEL_M         0x0800
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTSEL_S         11
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL_M         0x3000
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL_S         12
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL(__v)      \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL_S, __v)
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DISTESTWDOG_M     0x4000
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DISTESTWDOG_S     14
+// STCTRLL Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLL_INTFLG_M          0x8000
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLL_INTFLG_S          15
+// TOVALH Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH_M        0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH_S        0
+#define CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH(__v)     \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH_S, __v)
+// TOVALL Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW_M         0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW_S         0
+#define CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW(__v)      \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW_S, __v)
+// WINH Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH_M            0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH_S            0
+#define CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH(__v)         \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH_S, __v)
+// WINL Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW_M             0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW_S             0
+#define CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW(__v)          \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW_S, __v)
+// REFRESH Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH_M     0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH_S     0
+#define CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH(__v)  \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH_S, __v)
+// UNLOCK Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK_M       0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK_S       0
+#define CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK(__v)    \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK_S, __v)
+// TMROUTH Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH_M    0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH_S    0
+#define CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH(__v) \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH_S, __v)
+// TMROUTL Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW_M     0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW_S     0
+#define CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW(__v)  \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW_S, __v)
+// RSTCNT Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT_M           0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT_S           0
+#define CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT(__v)        \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT_S, __v)
+// PRESC Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL_M          0x700
+#define CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL_S          8
+#define CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL(__v)       \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL_S, __v)
+
+#ifndef __ASSEMBLER__
+
+__externC void hal_wdog_unlock(volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p);
+__externC void hal_wdog_disable(void);
+
+#endif // __ASSEMBLER__
+
+//---------------------------------------------------------------------------
+// SIM - System Integration Module
+
+// SIM - Peripheral register structure
+typedef volatile struct cyghwr_hal_kinetis_sim_s {
+    cyg_uint32 sopt1;           // System Options Register 1
+    cyg_uint8  reserved_0[4096];
+    cyg_uint32 sopt2;           // System Options Register 2
+    cyg_uint8  reserved_1[4];
+    cyg_uint32 sopt4;           // System Options Register 4
+    cyg_uint32 sopt5;           // System Options Register 5
+    cyg_uint32 sopt6;           // System Options Register 6
+    cyg_uint32 sopt7;           // System Options Register 7
+    cyg_uint8  Reserved_2[8];
+    cyg_uint32 sdid;            // System Device Identification Register
+    cyg_uint32 scgc1;           // System Clock Gating Control Register 1
+    cyg_uint32 scgc2;           // System Clock Gating Control Register 2
+    cyg_uint32 scgc3;           // System Clock Gating Control Register 3
+    cyg_uint32 scgc4;           // System Clock Gating Control Register 4
+    cyg_uint32 scgc5;           // System Clock Gating Control Register 5
+    cyg_uint32 scgc6;           // System Clock Gating Control Register 6
+    cyg_uint32 scgc7;           // System Clock Gating Control Register 7
+    cyg_uint32 clk_div1;        // System Clock Divider Register 1
+    cyg_uint32 clk_div2;        // System Clock Divider Register 2
+    cyg_uint32 fcfg1;           // Flash Configuration Register 1
+    cyg_uint32 fcfg2;           // Flash Configuration Register 2
+    cyg_uint32 uidh;            // Unique Identification Register High
+    cyg_uint32 uidmh;           // Unique Identification Register Mid-High
+    cyg_uint32 uidml;           // Unique Identification Register Mid Low
+    cyg_uint32 uidl;            // Unique Identification Register Low
+
+    cyg_uint32 clkdiv3;         // System Clock Divider Register 3
+    cyg_uint32 clkdiv4;         // System Clock Divider Register 4
+    cyg_uint32 mcr;             // Misc control register
+} cyghwr_hal_kinetis_sim_t;
+
+#define CYGHWR_HAL_KINETIS_SIM_P ((cyghwr_hal_kinetis_sim_t *) 0x40047000)
+
+// SOPT1 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE_M         0xF000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE_S         12
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE(__val)    \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_OSC32KSEL_M       0x80000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_OSC32KSEL_S       19
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_MS_M              0x800000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_MS_S              23
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBSTBY_M         0x40000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBSTBY_S         30
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBREGEN_M        0x80000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBREGEN_S        31
+// SOPT2 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_MCGCLKSEL_M       0x1
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_MCGCLKSEL_S       0
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL_M            0x300
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL_S            8
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL(__val)       \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_CMTUARTPAD_M      0x800
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_CMTUARTPAD_S      11
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_M     0x1000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_S     12
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_PLLFLLSEL_M       0x10000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_PLLFLLSEL_S       16
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_USBSRC_M          0x40000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_USBSRC_S          18
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC_M         0x300000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC_S         20
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC(__val)    \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC_M          0x3000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC_S          24
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC(__val)     \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC_M         0x30000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC_S         28
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC(__val)    \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC_S, __val)
+// SOPT4 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT0_M        0x1
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT0_S        0
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT1_M        0x2
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT1_S        1
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT2_M        0x4
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT2_S        2
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1FLT0_M        0x10
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1FLT0_S        4
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2FLT0_M        0x100
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2FLT0_S        8
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC_M      0xC0000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC_S      18
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC_M      0x300000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC_S      20
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0CLKSEL_M      0x1000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0CLKSEL_S      24
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CLKSEL_M      0x2000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CLKSEL_S      25
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CLKSEL_M      0x4000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CLKSEL_S      26
+// SOPT5 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC_M      0x3
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC_S      0
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC_M      0xC
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC_S      2
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC_M       0x30
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC_S       4
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC_M      0xC0
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC_S      6
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC_S, __val)
+// SOPT6 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL_M       0x1F000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL_S       24
+#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN_M        0xE0000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN_S        29
+#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN_S, __val)
+// SOPT7 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL_M      0xF
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL_S      0
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0PRETRGSEL_M   0x10
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0PRETRGSEL_S   4
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0ALTTRGEN_M    0x80
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0ALTTRGEN_S    7
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL_M      0xF00
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL_S      8
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1PRETRGSEL_M   0x1000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1PRETRGSEL_S   12
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1ALTTRGEN_M    0x8000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1ALTTRGEN_S    15
+// SDID Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SDID_PINID_M            0xF
+#define CYGHWR_HAL_KINETIS_SIM_SDID_PINID_S            0
+#define CYGHWR_HAL_KINETIS_SIM_SDID_PINID(__val)       \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SDID_PINID_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SDID_FAMID_M            0x70
+#define CYGHWR_HAL_KINETIS_SIM_SDID_FAMID_S            4
+#define CYGHWR_HAL_KINETIS_SIM_SDID_FAMID(__val)       \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SDID_FAMID_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SDID_REVID_M            0xF000
+#define CYGHWR_HAL_KINETIS_SIM_SDID_REVID_S            12
+#define CYGHWR_HAL_KINETIS_SIM_SDID_REVID(__val)       \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SDID_REVID_S, __val)
+
+//---------------------------------------------------------------------------
+// Clock distribution
+// The following encodes the control register and clock bit number
+// into clock configuration descriptor (CLKCD).
+#define CYGHWR_HAL_KINETIS_SIM_SCGC(__reg,__bit) ((((__reg) - 1 ) & 0xF) + \
+                                                  (((__bit) << 8) & 0x1F00))
+
+// Macros to extract encoded values.
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_REG(__clkcd) (((__clkcd) & 0xF))
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_BIT(__clkcd) (((__clkcd) >> 8) & 0x1F)
+
+// Functions and macros to enable/disable clocks.
+#define CYGHWR_HAL_SCGC_NONE (0xFFFFFFFF)
+__externC void hal_clock_enable(cyg_uint32 clkcd);
+__externC void hal_clock_disable(cyg_uint32 clkcd);
+
+#define CYGHWR_HAL_CLOCK_ENABLE(__clkcd) hal_clock_enable(__clkcd)
+#define CYGHWR_HAL_CLOCK_DISABLE(__clkcd) hal_clock_disable(__clkcd)
+
+#include <cyg/hal/var_io_clkgat.h>
+
+// CLKDIV1 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4_M       0xF0000
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4_S       16
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3_M       0xF00000
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3_S       20
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2_M       0xF000000
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2_S       24
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1_M       0xF0000000
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1_S       28
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1_S, __val)
+// CLKDIV2 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBFRAC_M       0x1
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBFRAC_S       0
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV_M        0xE
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV_S        1
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC_M       0xFF00
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC_S       8
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV_M        0xFFF00000
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV_S        20
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV_S, __val)
+// FCFG1 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART_M          0xF00
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART_S          8
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART(__val)     \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE_M          0xF0000
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE_S          16
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE(__val)     \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE_M           0xFF000000
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE_S           24
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE(__val)      \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE_S, __val)
+// FCFG2 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1_M        0x3F0000
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1_S        16
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_PFLSH_M           0x800000
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_PFLSH_S           23
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0_M        0x3F000000
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0_S        24
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_SWAPPFLSH_M       0x80000000
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_SWAPPFLSH_S       31
+// UIDH Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_UIDH_UID_M              0xFFFFFFFF
+#define CYGHWR_HAL_KINETIS_SIM_UIDH_UID_S              0
+#define CYGHWR_HAL_KINETIS_SIM_UIDH_UID(__val)         \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDH_UID_S, __val)
+// UIDMH Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_UIDMH_UID_M             0xFFFFFFFF
+#define CYGHWR_HAL_KINETIS_SIM_UIDMH_UID_S             0
+#define CYGHWR_HAL_KINETIS_SIM_UIDMH_UID(__val)        \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDMH_UID_S, __val)
+// UIDML Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_UIDML_UID_M             0xFFFFFFFF
+#define CYGHWR_HAL_KINETIS_SIM_UIDML_UID_S             0
+#define CYGHWR_HAL_KINETIS_SIM_UIDML_UID(__val)        \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDML_UID_S, __val)
+// UIDL Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_UIDL_UID_M              0xFFFFFFFF
+#define CYGHWR_HAL_KINETIS_SIM_UIDL_UID_S              0
+#define CYGHWR_HAL_KINETIS_SIM_UIDL_UID(__val)         \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDL_UID_S, __val)
+// MCR Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG_M           0xE000
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG_S           5
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG(__val)      \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRDQSDIS_M        0x8
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRDQSDIS_S        3
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRPEN_M           0x4
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRPEN_S           2
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRS_M             0x2
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRS_S             1
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRSREN_M          0x1
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRSREN_S          0
+
+
+
+//--------------------------------------------------------------------------
+// AXBS - Crossbar switch
+
+#define CYGHWR_HAL_KINETIS_AXBS_SLAVES_K    7
+#define CYGHWR_HAL_KINETIS_AXBS_MASTERS_K   8
+
+typedef volatile struct cyghwr_hal_kinetis_axbs_s {
+    volatile struct cyghwr_hal_kinetis_axbs_slave_s {
+        cyg_uint32 prs;
+        cyg_uint32 res0[3];
+        cyg_uint32 crs;
+        cyg_uint32 res1[59];
+    } slave[8];
+    volatile struct cyghwr_hal_kinetis_axbs_master_s {
+        cyg_uint32 res0[64];
+        cyg_uint32 mgprc;
+    } master[8];
+} cyghwr_hal_kinetis_axbs_t;
+
+#define CYGHWR_HAL_KINETIS_AXBS_P ((cyghwr_hal_kinetis_axbs_t *) 0x40004000)
+
+// PRS Fields
+#define CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(_master_) ((_master_) * 4)
+#define CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(_master_) \
+            (0x7 << CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(_master_))
+
+#define CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_PRIO(_master_,_prs)           \
+            (((_prs) & CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(_master_)) >>  \
+             CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(_master_))
+// CRS Fields
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_PARK_M     0x7
+
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_M     0x30
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_S     4
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL(_x_)  (((_x_) << CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_S) & \
+                                                         CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_M)
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_M      0x300
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_S      8
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_ARB(_x_)   (((_x_) << CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_S) & \
+                                                        CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_M)
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_HLP_M      0x40000000
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_RO_M       0x80000000
+
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB(_slave_i,_arb)          \
+CYG_MACRO_START                                                     \
+    cyg_uint32 regval;                                              \
+    cyghwr_hal_kinetis_axbs_t* _axbs_p = CYGHWR_HAL_KINETIS_AXBS_P; \
+    regval = _axbs_p->slave[_slave_i].crs;                          \
+    regval &= ~CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_M;                   \
+    regval |= CYGHWR_HAL_KINETIS_AXBS_CRS_ARB(_arb);                \
+    _axbs_p->slave[_slave_i].crs = regval;                          \
+CYG_MACRO_END
+
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB_RR(_slave_i)    \
+            CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB((_slave_i), 1)
+
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB_FIX(_slave_i)   \
+            CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB((_slave_i), 0)
+
+// MGPCR Bit Fields
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_AXBS_MGPCR_AULB_M  0x7
+
+//---------------------------------------------------------------------------
+// PORT - Peripheral register structure
+
+typedef volatile struct cyghwr_hal_kinetis_port_s {
+    cyg_uint32 pcr[32];      // Pin Control Register n, array
+    cyg_uint32 gpclr;        // Global Pin Control Low Register
+    cyg_uint32 gpchr;        // Global Pin Control High Register
+    cyg_uint8 reserved0[24];
+    cyg_uint32 isfr;         // Interrupt Status Flag Register
+    cyg_uint8 reserved1[28];
+    cyg_uint32 dfer;         // Digital Filter Enable Register
+    cyg_uint32 dfcr;         // Digital Filter Clock Register
+    cyg_uint32 dfwr;         // Digital Filter Width Register
+} cyghwr_hal_kinetis_port_t;
+
+// PORT - Peripheral instance base addresses
+#define CYGHWR_HAL_KINETIS_PORTA_P  ((cyghwr_hal_kinetis_port_t *)0x40049000)
+#define CYGHWR_HAL_KINETIS_PORTB_P  ((cyghwr_hal_kinetis_port_t *)0x4004A000)
+#define CYGHWR_HAL_KINETIS_PORTC_P  ((cyghwr_hal_kinetis_port_t *)0x4004B000)
+#define CYGHWR_HAL_KINETIS_PORTD_P  ((cyghwr_hal_kinetis_port_t *)0x4004C000)
+#define CYGHWR_HAL_KINETIS_PORTE_P  ((cyghwr_hal_kinetis_port_t *)0x4004D000)
+#define CYGHWR_HAL_KINETIS_PORTF_P  ((cyghwr_hal_kinetis_port_t *)0x4004E000)
+
+enum {
+    CYGHWR_HAL_KINETIS_PORTA, CYGHWR_HAL_KINETIS_PORTB,
+    CYGHWR_HAL_KINETIS_PORTC, CYGHWR_HAL_KINETIS_PORTD,
+    CYGHWR_HAL_KINETIS_PORTE, CYGHWR_HAL_KINETIS_PORTF
+};
+
+#define CYGHWR_HAL_KINETIS_PORT(__port, __reg) \
+        (CYGHWR_HAL_KINETIS_PORT##__port##_P)->__reg
+
+// PCR Bit Fields
+#define CYGHWR_HAL_KINETIS_PORT_PCR_PS_M          0x1
+#define CYGHWR_HAL_KINETIS_PORT_PCR_PS_S          0
+#define CYGHWR_HAL_KINETIS_PORT_PCR_PE_M          0x2
+#define CYGHWR_HAL_KINETIS_PORT_PCR_PE_S          1
+#define CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M         0x4
+#define CYGHWR_HAL_KINETIS_PORT_PCR_SRE_S         2
+#define CYGHWR_HAL_KINETIS_PORT_PCR_PFE_M         0x10
+#define CYGHWR_HAL_KINETIS_PORT_PCR_PFE_S         4
+#define CYGHWR_HAL_KINETIS_PORT_PCR_ODE_M         0x20
+#define CYGHWR_HAL_KINETIS_PORT_PCR_ODE_S         5
+#define CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M         0x40
+#define CYGHWR_HAL_KINETIS_PORT_PCR_DSE_S         6
+#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_M         0x700
+#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_S         8
+#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX(__val)    \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_PCR_MUX_S, __val)
+#define CYGHWR_HAL_KINETIS_PORT_PCR_LK_M          0x8000
+#define CYGHWR_HAL_KINETIS_PORT_PCR_LK_S          15
+#define CYGHWR_HAL_KINETIS_PORT_PCR_IRQC_M        0xF0000
+#define CYGHWR_HAL_KINETIS_PORT_PCR_IRQC_S        16
+#define CYGHWR_HAL_KINETIS_PORT_PCR_IRQC(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_PCR_IRQC_S, __val)
+#define CYGHWR_HAL_KINETIS_PORT_PCR_ISF_M         0x1000000
+#define CYGHWR_HAL_KINETIS_PORT_PCR_ISF_S         24
+
+#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_ANALOG    0
+#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_DIS       0
+#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_GPIO      1
+
+#define CYGHWR_HAL_KINETIS_PORT_PCR_ISFR_CLEAR(__port, __pin) \
+        CYGHWR_HAL_KINETIS_PORT(__port, pcr[__pin]) |= BIT_(24)
+
+#define CYGHWR_HAL_KINETIS_PORT_ISFR_CLEAR(__port, __pin)     \
+        CYGHWR_HAL_KINETIS_PORT(__port, isfr) |= BIT_(__pin)
+
+#define CYGHWR_HAL_KINETIS_PIN_CFG(__port, __bit, __mux, __irqc, __cnf) \
+        ((CYGHWR_HAL_KINETIS_PORT##__port << 20) | ((__bit) << 27)      \
+         | CYGHWR_HAL_KINETIS_PORT_PCR_IRQC(__irqc)                     \
+         | CYGHWR_HAL_KINETIS_PORT_PCR_MUX(__mux) | (__cnf))
+
+#define CYGHWR_HAL_KINETIS_PIN(__port, __bit, __mux, __cnf) \
+        CYGHWR_HAL_KINETIS_PIN_CFG(__port, __bit, __mux, 0, __cnf)
+
+#define CYGHWR_HAL_KINETIS_PIN_PORT(__pin) (((__pin) >> 20) & 0x7)
+#define CYGHWR_HAL_KINETIS_PIN_BIT(__pin)  (((__pin) >> 27 ) & 0x1f)
+#define CYGHWR_HAL_KINETIS_PIN_FUNC(__pin) ((__pin) & 0x010f8777)
+#define CYGHWR_HAL_KINETIS_PIN_NONE (0xffffffff)
+
+// GPCLR Bit Fields
+#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD_M      0xFFFF
+#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD_S      0
+#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD_S, __val)
+#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE_M      0xFFFF0000
+#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE_S      16
+#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE_S, __val)
+// GPCHR Bit Fields
+#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD_M      0xFFFF
+#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD_S      0
+#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD_S, __val)
+#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE_M      0xFFFF0000
+#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE_S      16
+#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE_S, __val)
+// ISFR Bit Fields
+#define CYGHWR_HAL_KINETIS_PORT_ISFR_ISF_M        0xFFFFFFFF
+#define CYGHWR_HAL_KINETIS_PORT_ISFR_ISF_S        0
+#define CYGHWR_HAL_KINETIS_PORT_ISFR_ISF(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_ISFR_ISF_S, __val)
+// DFER Bit Fields
+#define CYGHWR_HAL_KINETIS_PORT_DFER_DFE_M        0xFFFFFFFF
+#define CYGHWR_HAL_KINETIS_PORT_DFER_DFE_S        0
+#define CYGHWR_HAL_KINETIS_PORT_DFER_DFE(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_DFER_DFE_S, __val)
+// DFCR Bit Fields
+#define CYGHWR_HAL_KINETIS_PORT_DFCR_CS_M         0x1
+#define CYGHWR_HAL_KINETIS_PORT_DFCR_CS_S         0
+// DFWR Bit Fields
+#define CYGHWR_HAL_KINETIS_PORT_DFWR_FILT_M       0x1F
+#define CYGHWR_HAL_KINETIS_PORT_DFWR_FILT_S       0
+#define CYGHWR_HAL_KINETIS_PORT_DFWR_FILT(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_DFWR_FILT_S, __val)
+
+#ifndef __ASSEMBLER__
+
+// Pin configuration related functions
+__externC void  hal_set_pin_function(cyg_uint32 pin);
+__externC void  hal_dump_pin_function(cyg_uint32 pin);
+__externC void  hal_dump_pin_setting(cyg_uint32 pin);
+
+#endif
+
+#define HAL_SET_PINS(_pin_array) \
+CYG_MACRO_START \
+    const cyg_uint32 *_pin_p; \
+    for(_pin_p = &_pin_array[0]; \
+        _pin_p < &_pin_array[0] + sizeof(_pin_array)/sizeof(_pin_array[0]); \
+        hal_set_pin_function(*_pin_p++)); \
+CYG_MACRO_END
+
+//---------------------------------------------------------------------------
+// PMC Power Management Controller
+
+typedef volatile struct cyghwr_hal_kinetis_pmc_s {
+    cyg_uint8 lvdsc1;   // Low Voltage Detect Status and Control 1 Register
+    cyg_uint8 lvdsc2;   // Low Voltage Detect Status and Control 2 Register
+    cyg_uint8 regsc;    // Regulator Status and Control Register
+} cyghwr_hal_kinetis_pmc_t;
+
+// PMC base address
+#define CYGHWR_HAL_KINETIS_PMC_P  ((cyghwr_hal_kinetis_pmc_t *)0x4007D000)
+
+// LVDSC1 Bit Fields
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV_M      0x3
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV(__val) \
+        ((__val) & CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV_M)
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDRE_M     0x10
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDRE_S     4
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDIE_M     0x20
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDIE_S     5
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDACK_M    0x40
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDACK_S    6
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDF_M      0x80
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDF_S      7
+// LVDSC2 Bit Fields
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV_M      0x3
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV(__val) \
+        ((__val) & CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV_M)
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWIE_M     0x20
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWIE_S     5
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWACK_M    0x40
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWACK_S    6
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWF_M      0x80
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWF_S      7
+// REGSC Bit Fields
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGBE_M       0x1
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGBE_S       0
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_REGONS_M     0x4
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_REGONS_S     2
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M     0x8
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_S     3
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGEN_M       0x10
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGEN_S       4
+
+//---------------------------------------------------------------------------
+// FMC Flash Memory Controller
+
+#define CYGHWR_HAL_KINETIS_FMC_BASE     (0x4001F000)
+#define CYGHWR_HAL_KINETIS_FMC_PFAPR    (CYGHWR_HAL_KINETIS_FMC_BASE)
+#define CYGHWR_HAL_KINETIS_FMC_PFB0CR   (CYGHWR_HAL_KINETIS_FMC_BASE + 4)
+#define CYGHWR_HAL_KINETIS_FMC_PFB1CR   (CYGHWR_HAL_KINETIS_FMC_BASE + 8)
+
+enum {
+    CYGHWR_HAL_KINETIS_FMC_CACHE_W0,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_W1,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_W2,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_W3,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_WAYS
+};
+
+enum {
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S0,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S1,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S2,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S3,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S4,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S5,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S6,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S7,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_SIDES
+};
+
+#define CYGHWR_HAL_KINETIS_FMC_TAG(__way,__side) \
+          (CYGHWR_HAL_KINETIS_FMC_BASE + 0x100 + (__way)*0x20 + (__side)*4)
+#define CYGHWR_HAL_KINETIS_FMC_DATA_U(__way,side) \
+          (CYGHWR_HAL_KINETIS_FMC_BASE + 0x200 + (__way)*0x20 + (__side)*8)
+#define CYGHWR_HAL_KINETIS_FMC_DATA_L(__way,side) \
+          (CYGHWR_HAL_KINETIS_FMC_BASE + 0x204 + (__way)*0x40 + (__side)*8)
+
+#define CYGHWR_HAL_KINETIS_FMC_PFAPR_MPFD_M(__master) (1 << ((__master) + 16))
+enum {
+    CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_NO_ACCESS,
+    CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_RO,
+    CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_WO,
+    CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_RW
+};
+#define CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP(__master, __access) \
+          ((__access) <<(2 * (__master)))
+
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_RWSC_M (0xf0000000)
+
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(__way) ((1 << (__way)) << 24)
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_ALL \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W0) | \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W1) | \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W2) | \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W3)
+
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(__way) ((1 << (__way)) << 20)
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_ALL \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W0) | \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W1) | \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W2) | \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W3)
+
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_SBINV (1 << 19)
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BMW   (7 << 17)
+
+enum{
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_LRU,
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_res0,
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_IND_LRUW01IF23D,
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_IND_LRUW02ID3D
+};
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC   (__cache_repl_con) \
+                                       ((__cache_repl_con) << 5)
+
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BDCE  (0x10)
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BICE  (0x08)
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BDPE  (0x04)
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BIPE  (0x02)
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BSEBE (0x01)
+
+//---------------------------------------------------------------------------
+// MPU Memory Protection unit
+
+typedef volatile struct cyghwr_hal_kinetis_mpu_s {
+    cyg_uint32 cesr;          // Control/Error Status Register
+    cyg_uint8 reserved0[12];
+    struct {
+        cyg_uint32 ear;       // Error Address Register, Slave Port n
+        cyg_uint32 edr;       // Error Detail Register, Slave Port n
+    } slave_port[5];
+    cyg_uint8 reserved1[968];
+    struct {  // Region Descriptors, Word 0..Region Descriptor n, Word 3
+        cyg_uint32 word[4];
+    }reg_desc[12];
+    cyg_uint8 reserved2[832];
+    cyg_uint32 reg_daac[12];  // Region Descriptor Alternate Access Control n
+} cyghwr_hal_kinetis_mpu_t;
+
+#define CYGHWR_HAL_KINETIS_MPU_P  (cyghwr_hal_kinetis_mpu_t *)0x4000d000
+
+//---------------------------------------------------------------------------
+// FlexBus
+#ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
+# include <cyg/hal/var_io_flexbus.h>
+#endif
+
+//----------------------------------------------------------------------------
+// DDRMC - SDRAM controller
+#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC
+# include <cyg/hal/var_io_ddrmc.h>
+#endif
+
+//---------------------------------------------------------------------------
+// GPIO
+#include <cyg/hal/var_io_gpio.h>
+
+//=============================================================================
+// DEVS:
+// Following macros may also be, and usually are borrwed by some device drivers.
+//-----------------------------------------------------------------------------
+#include <cyg/hal/var_io_devs.h>
+
+// End Peripherals
+
+// Some miscelaneous function prototypes
+// Clock related functions are in kinetis_clocking.c
+__externC void hal_start_clocks(void);
+__externC void hal_update_clock_var(void);
+
+//-----------------------------------------------------------------------------
+// end of var_io.h
+
+#endif // CYGONCE_HAL_VAR_IO_H
diff --git a/packages/hal/cortexm/kinetis/var/current/include/var_io_clkgat.h b/packages/hal/cortexm/kinetis/var/current/include/var_io_clkgat.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_clkgat.h
@@ -0,0 +1,336 @@
+#ifndef CYGONCE_HAL_VAR_IOCLKGAT_H
+#define CYGONCE_HAL_VAR_IOCLKGAT_H
+//===========================================================================
+//
+//      var_io_clkgat.h
+//
+//      Kinetis clock gating
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2013-03-17
+// Purpose:       Kinetis clock distribution macros
+// Description:
+// Usage:         This file is included by <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+//---------------------------------------------------------------------------
+// Clock distribution
+
+// SCGC1 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_M            0x20
+#define CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_S            5
+#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_M           0x400
+#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_S           10
+#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_M           0x800
+#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_S           11
+
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_OSC1  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(1, CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART4 \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(1, CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART5 \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(1, CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_S)
+
+// SCGC2 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_M            0x1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_S            0
+#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_M            0x1000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_S            12
+#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_M            0x2000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_S            13
+
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_ENET \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(2, CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DAC0 \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(2, CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DAC1 \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(2, CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_S)
+
+// SCGC3 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGA_M            0x1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGA_S            0
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_M            0x1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_S            0
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_M        0x10
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_S        4
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_NFC_M             0x100
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_NFC_S             8
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_M            0x1000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_S            12
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_M             0x4000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_S             14
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SAI1_M            0x8000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SAI1_S            15
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_M            0x20000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_S            17
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_LCDC_M            0x40000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_LCDC_S            22
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_M            0x1000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_S            24
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM3_M            0x2000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM3_S            25
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_M            0x8000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_S            27
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_M            0x10000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_S            28
+
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_RNGA     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGA_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_RNGB     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXCAN1 \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_NFC      \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_NFC_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_SPI2     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DDR      \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_SAI1     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_SAI1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_SDHC     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_LCDC     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_LCDC_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTM2     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC1     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC3     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_S)
+
+// SCGC4 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_M             0x2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_S             1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_M             0x4
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_S             2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_M            0x40
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_S            6
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_M            0x80
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_S            7
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_M           0x400
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_S           10
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_M           0x800
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_S           11
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_M           0x1000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_S           12
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_M           0x2000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_S           13
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_M          0x40000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_S          18
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_M             0x80000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_S             19
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_M            0x100000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_S            20
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_M            0x10000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_S            28
+
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_EWM    \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_CMT    \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_I2C0   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_I2C1   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART0  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART1  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART2  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART3  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_USBOTG \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_CMP    \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_VREF   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_LLWU   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_S)
+
+// SCGC5 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_M         0x1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_S         0
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_M         0x2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_S         1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICE_M          0x4
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICE_S          2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICESR_M        0x8
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICESR_S        3
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_M             0x20
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_S             5
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M           0x200
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_S           9
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M           0x400
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_S           10
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M           0x800
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_S           11
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M           0x1000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_S           12
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M           0x2000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_S           13
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M           0x4000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_S           14
+
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_LPTIMER   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_REGFILE   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DRYICE    \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICE_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DRYICESR  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICESR_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_TSI       \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTA     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTB     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTC     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTD     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTE     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTF     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_S)
+
+// SCGC6 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_M            0x1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_S            0
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_M          0x2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_S          1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_M         0x2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_S         1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_M         0x4
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_S         2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_M        0x10
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_S        4
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI0_M            0x1000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI0_S            12
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_M            0x2000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_S            13
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_M             0x8000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_S             15
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SAI0_M            0x8000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SAI0_S            15
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_M             0x40000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_S             18
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBHS_M           0x100000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBHS_S           20
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_M          0x200000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_S          21
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_M             0x400000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_S             22
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_M             0x800000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_S             23
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_M            0x1000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_S            24
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_M            0x2000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_S            25
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_M            0x8000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_S            27
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC2_M            0x10000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC2_S            28
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M             0x20000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_S             29
+
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTFL     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX1  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXCAN0 \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_SPI0     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_SPI1     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_I2S      \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_SAI0     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_SAI0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_CRC      \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_USBHS    \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_USBHS_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_USBDCD   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PDB      \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PIT      \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTM0     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTM1     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC0     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC2     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC2_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_RTC      \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_S)
+
+// SCGC7 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_M         0x1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_S         0
+#define CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_M             0x2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_S             1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_M             0x4
+#define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_S             2
+
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXBUS \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(7, CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMA     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(7, CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_MPU     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(7, CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_S)
+
+//-----------------------------------------------------------------------------
+// end of var_io_clkgat.h
+
+#endif // CYGONCE_HAL_VAR_IOCLKGAT_H
diff --git a/packages/hal/cortexm/kinetis/var/current/include/var_io_ddrmc.h b/packages/hal/cortexm/kinetis/var/current/include/var_io_ddrmc.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_ddrmc.h
@@ -0,0 +1,111 @@
+#ifndef CYGONCE_HAL_VAR_IO_DDRMC_H
+#define CYGONCE_HAL_VAR_IO_DDRMC_H
+//===========================================================================
+//
+//      var_io_ddrmc.h
+//
+//      Kinetis DDRam controller specific registers
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2012-03-08
+// Purpose:       Kinetis variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io_ddrmc.h>  // var_io.h includes this file
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+//----------------------------------------------------------------------------
+// DDRMC - SDRAM controller
+
+# define CYGNUM_HAL_KINETIS_DDRMC_CR_N 64  // Number of DDRMC control registers
+
+typedef volatile struct cyghwr_hal_kinetis_ddrmc_s {
+    cyg_uint32 cr[CYGNUM_HAL_KINETIS_DDRMC_CR_N]; // Control registers
+    cyg_uint32 reserved1[32];
+    cyg_uint32 rcr;                               // RCR control register
+    cyg_uint32 reserved2[10];
+    cyg_uint32 pad_ctrl;                          // I/O Pad control register
+} cyghwr_hal_kinetis_ddrmc_t;
+
+# define CYGHWR_HAL_KINETIS_DDRMC_P  ((cyghwr_hal_kinetis_ddrmc_t *)0x400ae000)
+
+// RCR
+# define CYGHWR_HAL_KINETIS_DDRMC_RCR_RST_M 0x40000000
+// PAD CTRL
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_CS0_M 0x03000000
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_CS0_S 20
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT(_x_)  \
+        VALUE_(CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_CS0_S, _x_)
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_DIS 0
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_50  3
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_75  1
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_150 2
+
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_M 0x0000000f
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_S 0
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY(_x_)  \
+        VALUE_(CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_S, _x_)
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_0BUF  0
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_4BUF  1
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_7BUF  2
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_10BUF 3
+
+# define CYGHWR_HAL_KINETIS_DDRMC_CR00_START 0x1
+# define CYGHWR_HAL_KINETIS_DDRMC_CR30_DRAM_INIT_CPL 0x400
+
+# define CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP_M 0x0000ffff
+
+# ifndef CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP
+#  define CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP \
+          (CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG(CYGHWR_HAL_KINETIS_SIM_MCR_DDRBUS)| \
+          (CYGHWR_HAL_KINETIS_SIM_MCR_DDRDQSDIS_M * 0)                         | \
+          (CYGHWR_HAL_KINETIS_SIM_MCR_DDRPEN_M * 1)                            | \
+          (CYGHWR_HAL_KINETIS_SIM_MCR_DDRS_M * 0)                              | \
+          (CYGHWR_HAL_KINETIS_SIM_MCR_DDRSREN_M * 0 ))
+# endif
+
+__externC void hal_cortexm_kinetis_ddrmc_init(const cyg_uint32 src[]);
+# define HAL_CORTEXM_KINETIS_DDRMC_INIT(__inidat) \
+        hal_cortexm_kinetis_ddrmc_init(__inidat)
+__externC void hal_cortexm_kinetis_ddrmc_diag(void);
+
+//-----------------------------------------------------------------------------
+// end of var_io_ddrmc.h
+#endif // CYGONCE_HAL_VAR_IO_DDRMC_H
diff --git a/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h b/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h
@@ -0,0 +1,415 @@
+#ifndef CYGONCE_HAL_VAR_IO_DEVS_H
+#define CYGONCE_HAL_VAR_IO_DEVS_H
+//===========================================================================
+//
+//      var_io_devs.h
+//
+//      Variant specific registers
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2011-02-05
+// Purpose:       Kinetis variant IO provided to various device drivers
+// Description:
+// Usage:         #include <cyg/hal/var_io.h> //var_io.h includes this file
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+//=============================================================================
+// DEVS:
+// Following macros may be, and usually are borrwed by some device drivers.
+
+// Peripheral clock [Hz];
+__externC cyg_uint32 hal_get_peripheral_clock(void);
+
+//-----------------------------------------------------------------------------
+// Freescale UART
+// Borrow some HAL resources to Freescale UART driver
+// UART  macros are used by both:
+//      src/hal_diag.c
+//      devs/serial/<version>/src/ser_freescale_uart.c
+
+#define CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE  0x4006A000
+#define CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE  0x4006B000
+#define CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE  0x4006C000
+#define CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE  0x4006D000
+#define CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE  0x400EA000
+#define CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE  0x400EB000
+
+// UART Clock gating
+
+#define CYGHWR_IO_FREESCALE_UART0_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART0
+#define CYGHWR_IO_FREESCALE_UART1_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART1
+#define CYGHWR_IO_FREESCALE_UART2_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART2
+#define CYGHWR_IO_FREESCALE_UART3_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART3
+#define CYGHWR_IO_FREESCALE_UART4_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART4
+#define CYGHWR_IO_FREESCALE_UART5_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART5
+
+// UART PIN configuration
+// Note: May be overriden by plf_io.h
+
+#define CYGHWR_HAL_KINETIS_PORT_PIN_NONE CYGHWR_HAL_KINETIS_PIN_NONE
+
+#ifndef CYGHWR_IO_FREESCALE_UART0_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART0_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART0_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART0_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART0_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART1_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART1_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART1_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART1_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART1_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART2_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART2_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART2_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART2_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART2_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART3_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART4_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART4_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART4_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART4_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART4_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART5_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART5_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+#endif
+
+// Lend some HAL dependent functions to the UART serial device driver
+
+#ifndef __ASSEMBLER__
+
+# define CYGHWR_IO_FREESCALE_UART_BAUD_SET(__uart_p, _baud_) \
+        hal_freescale_uart_setbaud(__uart_p, _baud_)
+
+# define CYGHWR_IO_FREESCALE_UART_PIN(__pin) \
+        hal_set_pin_function(__pin)
+
+
+// Set baud rate
+__externC void hal_freescale_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud );
+
+#endif
+
+//---------------------------------------------------------------------------
+// ENET
+// Lend some HAL dependent functions to the Ethernet device driver
+#define CYGADDR_IO_ETH_FREESCALE_ENET0_BASE  (0x400C0000)
+// Clock gating
+#define CYGHWR_IO_FREESCALE_ENET0_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_ENET
+
+#ifndef __ASSEMBLER__
+
+# define CYGHWR_IO_FREESCALE_ENET_PIN(__pin) \
+        hal_set_pin_function(__pin)
+
+#endif
+
+//----------------------------------------------------------------------------
+// DSPI
+// Lend some HAL dependent macros to DSPI device driver
+
+// DSPI - Peripheral instance base addresses
+#define CYGADDR_IO_SPI_FREESCALE_DSPI0_P ((cyghwr_devs_freescale_dspi_t*)0x4002C000)
+#define CYGADDR_IO_SPI_FREESCALE_DSPI1_P ((cyghwr_devs_freescale_dspi_t*)0x4002D000)
+#define CYGADDR_IO_SPI_FREESCALE_DSPI2_P ((cyghwr_devs_freescale_dspi_t*)0x400AC000)
+
+#define CYGHWR_IO_SPI_FREESCALE_DSPI_CLOCK hal_get_peripheral_clock();
+
+#define CYGHWR_IO_FREESCALE_DSPI0_CLK  CYGHWR_HAL_KINETIS_SIM_SCGC_SPI0
+#define CYGHWR_IO_FREESCALE_DSPI1_CLK  CYGHWR_HAL_KINETIS_SIM_SCGC_SPI1
+#define CYGHWR_IO_FREESCALE_DSPI2_CLK  CYGHWR_HAL_KINETIS_SIM_SCGC_SPI2
+
+# define CYGHWR_IO_FREESCALE_DSPI_PIN(__pin) hal_set_pin_function(__pin)
+
+#ifndef KINETIS_PIN_SPI0_OUT_OPT
+#define KINETIS_PIN_SPI0_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI0_CS_OPT
+#define KINETIS_PIN_SPI0_CS_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI0_IN_OPT
+#define KINETIS_PIN_SPI0_IN_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M |  \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+#endif
+
+#ifndef KINETIS_PIN_SPI1_OUT_OPT
+#define KINETIS_PIN_SPI1_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI1_CS_OPT
+#define KINETIS_PIN_SPI1_CS_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI1_IN_OPT
+#define KINETIS_PIN_SPI1_IN_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M |  \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+#endif
+#ifndef KINETIS_PIN_SPI2_OUT_OPT
+#define KINETIS_PIN_SPI2_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI2_CS_OPT
+#define KINETIS_PIN_SPI2_CS_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI2_IN_OPT
+#define KINETIS_PIN_SPI2_IN_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M |  \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+#endif
+
+//---------------------------------------------------------------------------
+// I2C
+// Lend some HAL dependent macros to I2C device driver
+// Base pointers
+#define CYGADDR_IO_I2C_FREESCALE_I2C0_BASE  (0x40066000)
+#define CYGADDR_IO_I2C_FREESCALE_I2C1_BASE  (0x40067000)
+// Clocking
+#define CYGHWR_IO_I2C_FREESCALE_I2C_CLOCK hal_get_peripheral_clock()
+#define CYGHWR_IO_FREESCALE_I2C0_CLK  CYGHWR_HAL_KINETIS_SIM_SCGC_I2C0
+#define CYGHWR_IO_FREESCALE_I2C1_CLK  CYGHWR_HAL_KINETIS_SIM_SCGC_I2C1
+// Pins
+# define CYGHWR_IO_FREESCALE_I2C_PIN(__pin) hal_set_pin_function(__pin)
+
+# ifndef CYGHWR_IO_FREESCALE_I2C_FREQUENCY_TABLE
+// Fix an error in Kinetis I2C Manual. There is an unconfirmed
+// error in Kinetis I2C divider and hold value table.
+#if 0 // Values as are in Kinetis Reference Manuals
+#define I2C_FREQ_TABLE_ENTRY_8 28
+#define I2C_FREQ_TABLE_ENTRY_9 32
+#else // Values that give correct result according to measurements
+#define I2C_FREQ_TABLE_ENTRY_8 30
+#define I2C_FREQ_TABLE_ENTRY_9 34
+#endif
+typedef cyg_uint16 dev_i2c_freescale_frequency_entry_t;
+#  define CYGHWR_IO_FREESCALE_I2C_FREQUENCY_TABLE                                    \
+    20, 22, 24, 26, 28, 30, 34, 40, I2C_FREQ_TABLE_ENTRY_8, I2C_FREQ_TABLE_ENTRY_9,  \
+    36, 40, 44, 48, 56, 68, 48, 56, 64,                                              \
+    72, 80, 88, 104, 128, 80, 96, 112, 128, 144, 160, 192, 240, 160, 192, 224,       \
+    256, 288, 320, 384, 480, 320, 384, 448, 512, 576, 640, 768, 960, 640, 768,       \
+    896, 1024, 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840
+
+
+# endif // CYGHWR_IO_FREESCALE_I2C_FREQUENCY_TABLE
+
+// DMA MUX ------------------------------------------------------------------
+// DMAMUX DMA request sources
+#define FREESCALE_DMAMUX_SRC_KINETIS_DISABLE      0
+#define FREESCALE_DMAMUX_SRC_KINETIS_RESERVE      1
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART0R       2
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART0T       3
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART1R       4
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART1T       5
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART2R       6
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART2T       7
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART3R       8
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART3T       9
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART4R      10
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART4T      11
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART5R      12
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART5T      13
+#define FREESCALE_DMAMUX_SRC_KINETIS_I2S0R       14
+#define FREESCALE_DMAMUX_SRC_KINETIS_I3S0T       15
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI0R       16
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI0T       17
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI1R       18
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI1T       19
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI2R       20
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI2T       21
+#define FREESCALE_DMAMUX_SRC_KINETIS_I2C0        22
+#define FREESCALE_DMAMUX_SRC_KINETIS_I2C1        23 // Either I2C1
+#define FREESCALE_DMAMUX_SRC_KINETIS_I2C2        23 // or I2C2
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C0      24
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C1      25
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C2      26
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C3      27
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C4      28
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C5      29
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C6      30
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C7      31
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM1C0      32
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM1C1      33
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM2C0      34
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM2C1      35
+#define FREESCALE_DMAMUX_SRC_KINETIS_1588T0      36
+#define FREESCALE_DMAMUX_SRC_KINETIS_1588T1      37
+#define FREESCALE_DMAMUX_SRC_KINETIS_1588T2      38
+#define FREESCALE_DMAMUX_SRC_KINETIS_1588T3      39
+#define FREESCALE_DMAMUX_SRC_KINETIS_ADC0        40
+#define FREESCALE_DMAMUX_SRC_KINETIS_ADC1        41
+#define FREESCALE_DMAMUX_SRC_KINETIS_CMP0        42
+#define FREESCALE_DMAMUX_SRC_KINETIS_CMP1        43
+#define FREESCALE_DMAMUX_SRC_KINETIS_CMP2        44
+#define FREESCALE_DMAMUX_SRC_KINETIS_DAC0        45
+#define FREESCALE_DMAMUX_SRC_KINETIS_DAC1        46
+#define FREESCALE_DMAMUX_SRC_KINETIS_CMT         47
+#define FREESCALE_DMAMUX_SRC_KINETIS_PDB         48
+#define FREESCALE_DMAMUX_SRC_KINETIS_PORTA       49
+#define FREESCALE_DMAMUX_SRC_KINETIS_PORTB       50
+#define FREESCALE_DMAMUX_SRC_KINETIS_PORTC       51
+#define FREESCALE_DMAMUX_SRC_KINETIS_PORTD       52
+#define FREESCALE_DMAMUX_SRC_KINETIS_PORTE       53
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX0     54
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX1     55
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX2     56
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX3     57
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX4     58
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX5     59
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX6     60
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX7     61
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX8     62
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX9     63
+
+// DMAMUX1 DMA request sources
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DISABLE     0
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE     1
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART0R      2
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART0T      3
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART1R      4
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART1T      5
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART2R      6
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART2T      7
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART3R      8
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART3T      9
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART4R     10
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART4T     11
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART5R     12
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART5T     13
+#define FREESCALE_DMAMUX1_SRC_KINETIS_I2S0R      14
+#define FREESCALE_DMAMUX1_SRC_KINETIS_I3S0T      15
+#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI0R      16
+#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI0T      17
+#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI1R      18
+#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI1T      19
+#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI2R      20
+#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI2T      21
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_22 22
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_23 23
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C0     24
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C1     25
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C2     26
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C3     27
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C4     28
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C5     29
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C6     30
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C7     31
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_32 32
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_33 33
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_34 34
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_35 35
+#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T0     36
+#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T1     37
+#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T2     38
+#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T3     39
+#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC0       40
+#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC1       41
+#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC2       42
+#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC3       43
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_44 44
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DAC0       45
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DAC1       46
+#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP0       47
+#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP1       48
+#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP2       49
+#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP3       50
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_51 51
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_52 52
+#define FREESCALE_DMAMUX1_SRC_KINETIS_PORTF      53
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX0    54
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX1    55
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX2    56
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX3    57
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX4    58
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX5    59
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX6    60
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX7    61
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX8    62
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX9    63
+
+#define FREESCALE_DMAMUX_SRC_SPI0_RX FREESCALE_DMAMUX_SRC_KINETIS_SPI0R
+#define FREESCALE_DMAMUX_SRC_SPI0_TX FREESCALE_DMAMUX_SRC_KINETIS_SPI0T
+#define FREESCALE_DMAMUX_SRC_SPI1_RX FREESCALE_DMAMUX_SRC_KINETIS_SPI1R
+#define FREESCALE_DMAMUX_SRC_SPI1_TX FREESCALE_DMAMUX_SRC_KINETIS_SPI1T
+#define FREESCALE_DMAMUX_SRC_SPI2_RX FREESCALE_DMAMUX_SRC_KINETIS_SPI2R
+#define FREESCALE_DMAMUX_SRC_SPI2_TX FREESCALE_DMAMUX_SRC_KINETIS_SPI2T
+
+//----------------------------------------------------------------------------
+// eDMA
+// Lend some eDMA macros to device driver that use DMA
+
+// Base address
+#define CYGHWR_HAL_FREESCALE_EDMA0_P  ((cyghwr_hal_freescale_edma_t *)0x40008000)
+// DMAMUX base addresses
+#define CYGHWR_HAL_FREESCALE_DMAMUX0_P ((cyghwr_hal_freescale_dmamux_t *) 0x40021000)
+#define CYGHWR_HAL_FREESCALE_DMAMUX1_P ((cyghwr_hal_freescale_dmamux_t *) 0x40022000)
+
+#define CYGHWR_IO_FREESCALE_EDMA0_P CYGHWR_HAL_FREESCALE_EDMA0_P
+#define CYGHWR_IO_FREESCALE_DMAMUX0_P CYGHWR_HAL_FREESCALE_DMAMUX0_P
+#define CYGHWR_IO_FREESCALE_DMAMUX1_P CYGHWR_HAL_FREESCALE_DMAMUX1_P
+
+//Clock distribution
+#define CYGHWR_IO_CLOCK_ENABLE(__scgc) hal_clock_enable(__scgc)
+
+#define CYGHWR_IO_FREESCALE_EDMA0_CLK   CYGHWR_HAL_KINETIS_SIM_SCGC_DMA
+#define CYGHWR_IO_FREESCALE_DMAMUX0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0
+#define CYGHWR_IO_FREESCALE_DMAMUX0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0
+#define CYGHWR_IO_FREESCALE_DMAMUX1_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX1
+//-----------------------------------------------------------------------------
+// end of var_io_devs.h
+#endif // CYGONCE_HAL_VAR_IO_DEVS_H
diff --git a/packages/hal/cortexm/kinetis/var/current/include/var_io_flexbus.h b/packages/hal/cortexm/kinetis/var/current/include/var_io_flexbus.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_flexbus.h
@@ -0,0 +1,173 @@
+#ifndef CYGONCE_HAL_VAR_IO_FLEXBUS_H
+#define CYGONCE_HAL_VAR_IO_FLEXBUS_H
+//===========================================================================
+//
+//      var_io_flexbus.h
+//
+//      Kinetis FlexBus specific registers
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2011-02-05
+// Purpose:       Kinetis variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io.h>  // var_io.h includes this file
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+//---------------------------------------------------------------------------
+// FlexBus
+
+// FlexBus chip select control registers
+typedef struct cyghwr_hal_kinetis_fbcs_s{
+    cyg_uint32 csar;    // Chip select address register
+    cyg_uint32 csmr;    // Chip select mask register
+    cyg_uint32 cscr;    // Chip select control register
+} cyghwr_hal_kinetis_fbcs_t;
+
+#define CYGNUM_HAL_KINETIS_FBCS_N 6 // Kinetis has up to 6 chip selects
+
+// FlexBus control
+typedef volatile struct cyghwr_hal_kinetis_fb_s {
+  cyghwr_hal_kinetis_fbcs_t csel[CYGNUM_HAL_KINETIS_FBCS_N]; //Chip Selects
+  cyg_uint8 reserved[24];
+  cyg_uint32 cspmcr;      //Chip select port multiplexing control register
+} cyghwr_hal_kinetis_fb_t;
+
+#define CYGHWR_HAL_KINETIS_FB_P ((cyghwr_hal_kinetis_fb_t *) 0x4000C000)
+
+// CSAR - Chip Select Address Register
+// CSAR Bit Fields
+#define CYGHWR_HAL_FB_CSAR_BA_M        0xFFFF0000
+#define CYGHWR_HAL_FB_CSAR_BA_S        16
+#define CYGHWR_HAL_FB_CS_AR_BA(__val)  VALUE_(CYGHWR_HAL_FB_CSAR_BA_S, __val)
+
+// CSMR - Chup Select Mask Register
+// CSMR Bit Fields
+#define CYGHWR_HAL_FB_CSMR_V_M         0x1
+#define CYGHWR_HAL_FB_CSMR_V_S         0
+#define CYGHWR_HAL_FB_CSMR_WP_M        0x100
+#define CYGHWR_HAL_FB_CSMR_WP_S        8
+#define CYGHWR_HAL_FB_CSMR_BAM_M       0xFFFF0000
+#define CYGHWR_HAL_FB_CSMR_BAM_S       16
+#define CYGHWR_HAL_FB_CS_MR_BAM(__val) VALUE_(CYGHWR_HAL_FB_CSMR_BAM_S, __val)
+
+// CSCR - Chip Select Control register
+// CSCR Bit Fields
+#define CYGHWR_HAL_FB_CSCR_BSTW_M      0x8
+#define CYGHWR_HAL_FB_CSCR_BSTW_S      3
+#define CYGHWR_HAL_FB_CSCR_BSTR_M      0x10
+#define CYGHWR_HAL_FB_CSCR_BSTR_S      4
+#define CYGHWR_HAL_FB_CSCR_BEM_M       0x20
+#define CYGHWR_HAL_FB_CSCR_BEM_S       5
+#define CYGHWR_HAL_FB_CSCR_PS_M        0xC0
+#define CYGHWR_HAL_FB_CSCR_PS_S        6
+#define CYGHWR_HAL_FB_CSCR_AA_M        0x100
+#define CYGHWR_HAL_FB_CSCR_AA_S        8
+#define CYGHWR_HAL_FB_CSCR_BLS_M       0x200
+#define CYGHWR_HAL_FB_CSCR_BLS_S       9
+#define CYGHWR_HAL_FB_CSCR_WS_M        0xFC00
+#define CYGHWR_HAL_FB_CSCR_WS_S        10
+#define CYGHWR_HAL_FB_CSCR_WRAH_M      0x30000
+#define CYGHWR_HAL_FB_CSCR_WRAH_S      16
+#define CYGHWR_HAL_FB_CSCR_RDAH_M      0xC0000
+#define CYGHWR_HAL_FB_CSCR_RDAH_S      18
+#define CYGHWR_HAL_FB_CSCR_ASET_M      0x300000
+#define CYGHWR_HAL_FB_CSCR_ASET_S      20
+#define CYGHWR_HAL_FB_CSCR_EXALE_M     0x400000
+#define CYGHWR_HAL_FB_CSCR_EXALE_S     22
+#define CYGHWR_HAL_FB_CSCR_SWSEN_M     0x800000
+#define CYGHWR_HAL_FB_CSCR_SWSEN_S     23
+#define CYGHWR_HAL_FB_CSCR_SWS_M       0xFC000000
+#define CYGHWR_HAL_FB_CSCR_SWS_S       26
+
+// CSPMCR Bit Fields
+#define CYGHWR_HAL_FB_CSPMCR_G5_M  0xF000
+#define CYGHWR_HAL_FB_CSPMCR_G5_S  12
+#define CYGHWR_HAL_FB_CSPMCR_G4_M  0xF0000
+#define CYGHWR_HAL_FB_CSPMCR_G4_S  16
+#define CYGHWR_HAL_FB_CSPMCR_G3_M  0xF00000
+#define CYGHWR_HAL_FB_CSPMCR_G3_S  20
+#define CYGHWR_HAL_FB_CSPMCR_G2_M  0xF000000
+#define CYGHWR_HAL_FB_CSPMCR_G2_S  24
+#define CYGHWR_HAL_FB_CSPMCR_G1_M  0xF0000000
+#define CYGHWR_HAL_FB_CSPMCR_G1_S  28
+
+// FlexBus control pin multiplexing
+#define CYGHWR_HAL_FB_CSPMCR(__group, __val) VALUE_(__group, __val)
+
+#define CYGHWR_HAL_FB_CSPMCR_G1_ALE \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G1_S, 0)
+#define CYGHWR_HAL_FB_CSPMCR_G1_CS1 \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G1_S, 1)
+#define CYGHWR_HAL_FB_CSPMCR_G1_TS  \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G1_S, 2)
+
+#define CYGHWR_HAL_FB_CSPMCR_G2_CS4      \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G2_S, 0)
+#define CYGHWR_HAL_FB_CSPMCR_G2_TSIZ0    \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G2_S, 1)
+#define CYGHWR_HAL_FB_CSPMCR_G2_BE_31_24 \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G2_S, 2)
+
+#define CYGHWR_HAL_FB_CSPMCR_G3_CS5      \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G3_S, 0)
+#define CYGHWR_HAL_FB_CSPMCR_G3_TSIZ1    \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G3_S, 1)
+#define CYGHWR_HAL_FB_CSPMCR_G3_BE_23_16 \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G3_S, 2)
+
+#define CYGHWR_HAL_FB_CSPMCR_G4_TST      \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G4_S, 0)
+#define CYGHWR_HAL_FB_CSPMCR_G4_CS2      \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G4_S, 1)
+#define CYGHWR_HAL_FB_CSPMCR_G4_BE_15_8  \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G4_S, 2)
+
+#define CYGHWR_HAL_FB_CSPMCR_G5_TA       \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G5_S, 0)
+#define CYGHWR_HAL_FB_CSPMCR_G5_CS3      \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G5_S, 1)
+#define CYGHWR_HAL_FB_CSPMCR_G5_BE_7_0   \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G5_S, 2)
+
+//-----------------------------------------------------------------------------
+// end of var_io_flexbus.h
+#endif // CYGONCE_HAL_VAR_IO_FLEXBUS_H
diff --git a/packages/hal/cortexm/kinetis/var/current/include/var_io_gpio.h b/packages/hal/cortexm/kinetis/var/current/include/var_io_gpio.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_gpio.h
@@ -0,0 +1,137 @@
+#ifndef CYGONCE_HAL_VAR_IO_GPIO_H
+#define CYGONCE_HAL_VAR_IO_GPIO_H
+//===========================================================================
+//
+//      var_io_gpio.h
+//
+//      Kinetis GPIO
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Tomas Frydrych <tomas@sleepfive.com>
+// Date:          2011-11-14
+// Purpose:       Kinetis variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io.h>  // var_io.h includes this file
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+//---------------------------------------------------------------------------
+// GPIO
+typedef volatile struct cyghwr_hal_kinetis_gpio_s {
+  cyg_uint32 pdor;
+  cyg_uint32 psor;
+  cyg_uint32 pcor;
+  cyg_uint32 ptor;
+  cyg_uint32 pdir;
+  cyg_uint32 pddr;
+} cyghwr_hal_kinetis_gpio_t;
+
+// PTA-PTE base pointers
+#define CYGHWR_HAL_KINETIS_GPIO_PORTA_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF000u)
+#define CYGHWR_HAL_KINETIS_GPIO_PORTB_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF040u)
+#define CYGHWR_HAL_KINETIS_GPIO_PORTC_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF080u)
+#define CYGHWR_HAL_KINETIS_GPIO_PORTD_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF0C0u)
+#define CYGHWR_HAL_KINETIS_GPIO_PORTE_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF100u)
+#define CYGHWR_HAL_KINETIS_GPIO_PORTF_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF140u)
+
+// GPIO register on a given port (register name is lower case)
+#define CYGHWR_HAL_KINETIS_GPIO(__port, __reg)           \
+  (CYGHWR_HAL_KINETIS_GPIO_PORT##__port##_P)->__reg
+
+// Get values for entire port
+#define CYGHWR_HAL_KINETIS_GPIO_GET(__port)              \
+  CYGHWR_HAL_KINETIS_GPIO(__port, pdir)
+
+// Output values for entire port
+#define CYGHWR_HAL_KINETIS_GPIO_PUT(__port, __val)       \
+  CYGHWR_HAL_KINETIS_GPIO(__port, pdor) = __val
+
+// Set values for entire port based on bitmask
+#define CYGHWR_HAL_KINETIS_GPIO_SET(__port, __val)       \
+  CYGHWR_HAL_KINETIS_GPIO(__port, psor) = __val
+
+// Clear values for entire port based on bitmask
+#define CYGHWR_HAL_KINETIS_GPIO_CLEAR(__port, __val)     \
+  CYGHWR_HAL_KINETIS_GPIO(__port, pcor) = __val
+
+// Toggle values for entire port based on bitmask
+#define CYGHWR_HAL_KINETIS_GPIO_TOGGLE(__port, __val)    \
+  CYGHWR_HAL_KINETIS_GPIO(__port, ptor) = __val
+
+// Get value for a single pin on given port
+#define CYGHWR_HAL_KINETIS_GPIO_GET_PIN(__port, __pin)   \
+  (BIT_(__pin) &  CYGHWR_HAL_KINETIS_GPIO_GET(__port))
+
+// Set a single pin on a given register
+#define CYGHWR_HAL_KINETIS_GPIO_SET_PIN(__port, __pin)   \
+  CYGHWR_HAL_KINETIS_GPIO_SET(__port, BIT_(__pin))
+
+// Clear a single pin on a given register
+#define CYGHWR_HAL_KINETIS_GPIO_CLEAR_PIN(__port, __pin) \
+  CYGHWR_HAL_KINETIS_GPIO_CLEAR(__port, BIT_(__pin))
+
+// Toggle a single pin on a given register
+#define CYGHWR_HAL_KINETIS_GPIO_TOGGLE_PIN(__port, __pin)  \
+  CYGHWR_HAL_KINETIS_GPIO_TOGGLE(__port, BIT_(__pin))
+
+// Set pin data direction
+#define CYGHWR_HAL_KINETIS_GPIO_PIN_DDR_OUT(__port, __pin) \
+  CYGHWR_HAL_KINETIS_GPIO(__port, pddr) |= BIT_(__pin)
+
+#define CYGHWR_HAL_KINETIS_GPIO_PIN_DDR_IN(__port, __pin)  \
+  CYGHWR_HAL_KINETIS_GPIO(__port, pddr) &= ~BIT_(__pin)
+
+
+__externC void hal_gpio_pin_ddr_out(cyg_uint32 pin);
+__externC void hal_gpio_pin_ddr_in(cyg_uint32 pin);
+
+__externC cyg_uint32 hal_gpio_get_pin(cyg_uint32 pin);
+
+__externC void hal_gpio_port_clear(cyg_uint32 port_i, cyg_uint32 mask);
+__externC void hal_gpio_port_set(cyg_uint32 port_i, cyg_uint32 mask);
+__externC void hal_gpio_port_toggle(cyg_uint32 port_i, cyg_uint32 mask);
+
+__externC void hal_gpio_pin_clear(cyg_uint32 pin);
+__externC void hal_gpio_pin_set(cyg_uint32 pin);
+__externC void hal_gpio_pin_toggle(cyg_uint32 pin);
+
+//-----------------------------------------------------------------------------
+// end of var_io_gpio.h
+#endif // CYGONCE_HAL_VAR_IO_GPIO_H
diff --git a/packages/hal/cortexm/kinetis/var/current/include/var_io_lmem.h b/packages/hal/cortexm/kinetis/var/current/include/var_io_lmem.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_lmem.h
@@ -0,0 +1,302 @@
+#ifndef CYGONCE_HAL_VAR_IO_LMEM_H
+#define CYGONCE_HAL_VAR_IO_LMEM_H
+//===========================================================================
+//
+//      var_io_lmem.h
+//
+//      Kinetis Local memory controller specific registers
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2012-04-28
+// Purpose:       Kinetis variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io_lmem.h>  // var_io.h includes this file
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+//----------------------------------------------------------------------------
+// LMEM - Local memory controller
+
+typedef volatile struct cyghwr_hal_kinetis_lmem_s {
+    cyg_uint32 ccr;    // Cache control register
+    cyg_uint32 clcr;   // Cache line control register
+    void *csar;        // Cache search address register
+    cyg_uint32 cvr;    // Cache read/write value register
+    cyg_uint8  reserved[16];
+    cyg_uint32 rmr;    // Cache regions mode register
+} cyghwr_hal_kinetis_lmem_t;
+
+#define CYGHWR_HAL_KINETIS_LMEM_PC_P  ((cyghwr_hal_kinetis_lmem_t *) 0xE0082000)
+#define CYGHWR_HAL_KINETIS_LMEM_PS_P  ((cyghwr_hal_kinetis_lmem_t *) 0xE0082800)
+
+// CCR Bit Fields
+#define CYGHWR_HAL_KINETIS_LMEM_CCR_ENCACHE_M          0x1
+#define CYGHWR_HAL_KINETIS_LMEM_CCR_ENWRBUF_M          0x2
+#define CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M            0x1000000
+#define CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M           0x2000000
+#define CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M            0x4000000
+#define CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M           0x8000000
+#define CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M               0x80000000
+
+//CLCR Bit Fields
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M             0x1
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_M       0xFFC
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_S       2
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR(_ca_) \
+            ((_ca_) << CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_S)
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_WSEL_M            0x4000
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_TDSEL_M           0x10000
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCIVB_M           0x100000
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCIMB_M           0x200000
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCWAY_M           0x400000
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_S            24
+
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD(_cmd_) \
+            ((_cmd_) << CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_S)
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_SRCH         0
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_INVAL        1
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_PUSH         2
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_CLR          3
+
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LADSEL_M          0x4000000
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LACC_M            0x8000000
+
+// CSAR Bit Fields
+#define CYGHWR_HAL_KINETIS_LMEM_CSAR_LGO_M             0x1
+#define CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_M         0xFFFFFFFC
+#define CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_S         2
+#define CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR(_adr_) \
+            ((_adr_) << CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_S)
+
+// CCVR Bit Fields
+#define CYGHWR_HAL_KINETIS_LMEM_CCVR_DATA_M            0xFFFFFFFF
+
+// PCCRMR Bit Fields
+
+#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_M           0x3
+#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION(_region_,_mask_) \
+            ((_mask_) << ((15 - (_region_)) * 2))
+
+#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M 0
+#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WT_M 2
+#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WB_M 3
+
+#define CYGHWR_HAL_KINETIS_LMEM_FLASH_0000     0
+#define CYGHWR_HAL_KINETIS_LMEM_DRAM_0800      1
+#define CYGHWR_HAL_KINETIS_LMEM_FLEXNVM_1000   2
+#define CYGHWR_HAL_KINETIS_LMEM_FLEXBUS_1800   3
+#define CYGHWR_HAL_KINETIS_LMEM_SRAM_L         4
+#define CYGHWR_HAL_KINETIS_LMEM_SRAM_U         5
+#define CYGHWR_HAL_KINETIS_LMEM_FLEXBUS_6000   6
+#define CYGHWR_HAL_KINETIS_LMEM_DRAM_7000      7
+#define CYGHWR_HAL_KINETIS_LMEM_DRAM_8000      8
+#define CYGHWR_HAL_KINETIS_LMEM_FLEXBUS_9000   9
+
+#define HAL_CORTEXM_KINETIS_CACHE_PC_ENABLE() \
+            hal_cortexm_kinetis_cache_enable(CYGHWR_HAL_KINETIS_LMEM_PC_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_ENABLE() \
+            hal_cortexm_kinetis_cache_enable(CYGHWR_HAL_KINETIS_LMEM_PS_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PC_DISABLE() \
+            hal_cortexm_kinetis_cache_disable(CYGHWR_HAL_KINETIS_LMEM_PC_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_DISABLE() \
+            hal_cortexm_kinetis_cache_disable(CYGHWR_HAL_KINETIS_LMEM_PS_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PC_INVALL() \
+            hal_cortexm_kinetis_cache_inval(CYGHWR_HAL_KINETIS_LMEM_PC_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_INVALL() \
+            hal_cortexm_kinetis_cache_inval(CYGHWR_HAL_KINETIS_LMEM_PS_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PC_SYNC() \
+            hal_cortexm_kinetis_cache_sync(CYGHWR_HAL_KINETIS_LMEM_PC_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_SYNC() \
+            hal_cortexm_kinetis_cache_sync(CYGHWR_HAL_KINETIS_LMEM_PS_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PC_CLEAR() \
+            hal_cortexm_kinetis_cache_clear(CYGHWR_HAL_KINETIS_LMEM_PC_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_CLEAR() \
+            hal_cortexm_kinetis_cache_clear(CYGHWR_HAL_KINETIS_LMEM_PS_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PC_IS_ENABLED() \
+            hal_cortexm_kinetis_cache_is_enabled(CYGHWR_HAL_KINETIS_LMEM_PC_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_IS_ENABLED() \
+            hal_cortexm_kinetis_cache_is_enabled(CYGHWR_HAL_KINETIS_LMEM_PS_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_SRCH(_base, _size_) \
+        hal_cortexm_kinetis_cache_lines(CYGHWR_HAL_KINETIS_LMEM_PS_P, _base, _size_, \
+                                       CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_SRCH)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_INVALIDATE(_base, _size_) \
+        hal_cortexm_kinetis_cache_lines(CYGHWR_HAL_KINETIS_LMEM_PS_P, _base, _size_, \
+                                       CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_INVAL)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_PUSH(_base, _size_) \
+        hal_cortexm_kinetis_cache_lines(CYGHWR_HAL_KINETIS_LMEM_PS_P, _base, _size_, \
+                                       CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_PUSH)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_CLR(_base, _size_) \
+        hal_cortexm_kinetis_cache_lines(CYGHWR_HAL_KINETIS_LMEM_PS_P, _base, _size_, \
+                                       CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_CLR)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PC_INVALIDATE(_base, _size_) \
+        hal_cortexm_kinetis_cache_lines(CYGHWR_HAL_KINETIS_LMEM_PC_P, _base, _size_, \
+                                       CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_INVAL)
+
+#if defined CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK && defined CYG_HAL_STARTUP_RAM
+
+#define CYGHWR_HAL_KINETIS_CACHE_WAIT(_lmem_p)                            \
+CYG_MACRO_START                                                           \
+    cyg_uint32 prs_tmp, prs_save;                                         \
+    cyg_uint32 m0, m1;                                                    \
+    cyghwr_hal_kinetis_axbs_t* _axbs_p = CYGHWR_HAL_KINETIS_AXBS_P;       \
+    prs_save = prs_tmp = _axbs_p->slave[5].prs;                           \
+    m0 = CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_PRIO(0, prs_tmp);             \
+    m1 = CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_PRIO(1, prs_tmp);             \
+    if(m1 > m0) {                                                         \
+        prs_tmp &= ~(CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(0) |            \
+                     CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(1));            \
+        prs_tmp |= (m0 << CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(1)) | m1;  \
+        _axbs_p->slave[5].prs = prs_tmp;                                  \
+    }                                                                     \
+    while((_lmem_p)->ccr & CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M);             \
+    _axbs_p->slave[5].prs = prs_save;                                     \
+CYG_MACRO_END
+
+#else // CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK
+
+#define CYGHWR_HAL_KINETIS_CACHE_WAIT(_lmem_p)          \
+            while((_lmem_p)->ccr & CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M)
+
+#endif // CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_kinetis_cache_enable(cyghwr_hal_kinetis_lmem_t* lmem_p)
+{
+    lmem_p->ccr = ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_ENCACHE_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_ENWRBUF_M
+                   );
+    CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p);
+}
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_kinetis_cache_disable(cyghwr_hal_kinetis_lmem_t* lmem_p)
+{
+    lmem_p->ccr = 0;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_kinetis_cache_inval(cyghwr_hal_kinetis_lmem_t* lmem_p)
+{
+    lmem_p->ccr |= ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M |
+              CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M |
+              CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M
+              );
+    CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p);
+}
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_kinetis_cache_store(cyghwr_hal_kinetis_lmem_t* lmem_p)
+{
+    lmem_p->ccr |= ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M |
+                     CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M |
+                     CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M
+                    );
+    CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p);
+}
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_kinetis_cache_clear(cyghwr_hal_kinetis_lmem_t* lmem_p)
+{
+    lmem_p->ccr |= ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M
+                   );
+    CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p);
+}
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_kinetis_cache_sync(cyghwr_hal_kinetis_lmem_t* lmem_p)
+{
+    hal_cortexm_kinetis_cache_store(lmem_p);
+    hal_cortexm_kinetis_cache_clear(lmem_p);
+}
+
+CYGBLD_FORCE_INLINE bool
+hal_cortexm_kinetis_cache_is_enabled(cyghwr_hal_kinetis_lmem_t* lmem_p)
+{
+    return lmem_p->ccr & CYGHWR_HAL_KINETIS_LMEM_CCR_ENCACHE_M;
+}
+
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_kinetis_cache_lines(cyghwr_hal_kinetis_lmem_t* lmem_p,
+                               cyg_uint8* addr_p, cyg_uint32 size,
+                               const cyg_uint32 oper)
+{
+    cyg_uint32 line_k;
+    line_k = (((cyg_uint32)addr_p & (HAL_DCACHE_LINE_SIZE-1)) + size) / HAL_DCACHE_LINE_SIZE + 1;
+
+    lmem_p->clcr = CYGHWR_HAL_KINETIS_LMEM_CLCR_LADSEL_M |
+                   CYGHWR_HAL_KINETIS_LMEM_CLCR_TDSEL_M  |
+                   CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD(oper);
+
+    addr_p = (cyg_uint8*)((((cyg_uint32) addr_p) & 0xfffffff0) |
+                          CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M);
+    do {
+        lmem_p->csar = addr_p;
+        while(lmem_p->clcr & CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M);
+        addr_p += HAL_DCACHE_LINE_SIZE;
+    } while(--line_k);
+}
+
+//-----------------------------------------------------------------------------
+// end of var_io_lmem.h
+#endif // CYGONCE_HAL_VAR_IO_LMEM_H
diff --git a/packages/hal/cortexm/kinetis/var/current/include/variant.inc b/packages/hal/cortexm/kinetis/var/current/include/variant.inc
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/include/variant.inc
@@ -0,0 +1,53 @@
+/*==========================================================================
+//
+//      variant.inc
+//
+//      Variant specific asm definitions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, ilijak
+// Date:         2011-02-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal_cortexm_kinetis.h>
+
+//==========================================================================
+// EOF variant.inc
diff --git a/packages/hal/cortexm/kinetis/var/current/src/hal_diag.c b/packages/hal/cortexm/kinetis/var/current/src/hal_diag.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/src/hal_diag.c
@@ -0,0 +1,410 @@
+/*=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Ilija Kocho <ilijak@siva.com.mk>
+// Contributors:
+// Date:        2011-02-04
+// Purpose:     HAL diagnostic input/output
+// Description: Implementations of HAL diagnostic input/output support.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+ */
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+
+#include <cyg/hal/hal_arch.h>           // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_if.h>             // interface API
+#include <cyg/hal/hal_intr.h>           // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h>           // Helper functions
+#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
+#include <cyg/hal/hal_diag.h>
+
+#include <cyg/hal/var_io.h>             //
+#include <cyg/io/ser_freescale_uart.h>  // UART registers
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+    cyg_uint32 uart;
+    CYG_ADDRESS base;
+    cyg_int32 msec_timeout;
+    cyg_int32 isr_vector;
+    cyg_uint32 rx_pin;
+    cyg_uint32 tx_pin;
+    cyg_uint32 clock_gate;
+    cyg_int32 baud_rate;
+    cyg_int32 irq_state;
+} channel_data_t;
+
+channel_data_t plf_ser_channels[] = {
+#ifdef CYGINT_HAL_FREESCALE_UART0
+    { 0, CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART0_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART0_PIN_RX, CYGHWR_HAL_FREESCALE_UART0_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART0_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+#ifdef CYGINT_HAL_FREESCALE_UART1
+    { 1, CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART1_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART1_PIN_RX, CYGHWR_HAL_FREESCALE_UART1_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART1_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+#ifdef CYGINT_HAL_FREESCALE_UART2
+    { 2, CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART2_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART2_PIN_RX, CYGHWR_HAL_FREESCALE_UART2_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART2_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+#ifdef CYGINT_HAL_FREESCALE_UART3
+    { 3, CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART3_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART3_PIN_RX, CYGHWR_HAL_FREESCALE_UART3_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART3_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+#ifdef CYGINT_HAL_FREESCALE_UART4
+    { 4, CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART4_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART4_PIN_RX, CYGHWR_HAL_FREESCALE_UART4_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART4_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+#ifdef CYGINT_HAL_FREESCALE_UART5
+    { 5, CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART5_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART5_PIN_RX, CYGHWR_HAL_FREESCALE_UART5_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART5_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }
+#endif
+};
+
+#if defined(CYGOPT_HAL_KINETIS_DIAG_IN_MISC_FLASH_SECTION) && \
+        CYGOPT_HAL_KINETIS_DIAG_IN_MISC_FLASH_SECTION
+#  define CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR         \
+        CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+#else
+#  define CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+#endif
+
+//-----------------------------------------------------------------------------
+
+void  CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_putc(void *__ch_data, char c);
+
+
+static void  CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_init_channel(void* __ch_data)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS uart_p = chan->base;
+
+    // Bring clock to the device
+    CYGHWR_IO_CLOCK_ENABLE(chan->clock_gate);
+    // Configure PORT pins
+    hal_set_pin_function(chan->rx_pin);
+    hal_set_pin_function(chan->tx_pin);
+
+    // 8-1-no parity.
+    HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C1, 0);
+    CYGHWR_IO_FREESCALE_UART_BAUD_SET(uart_p, chan->baud_rate);
+    // Enable RX and TX
+    HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2,
+                    (CYGHWR_DEV_FREESCALE_UART_C2_TE |
+                     CYGHWR_DEV_FREESCALE_UART_C2_RE));
+}
+
+void  CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_putc(void* __ch_data, char ch_out)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base;
+    cyg_uint32 uart_s1;
+
+    CYGARC_HAL_SAVE_GP();
+
+    do {
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1);
+    } while (!(uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_TDRE));
+
+    HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_out);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* p_ch_in)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base;
+    cyg_uint8 uart_s1;
+    cyg_uint8 ch_in;
+
+    HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1);
+    if (!(uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_RDRF))
+        return false;
+
+    HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_in);
+    *p_ch_in = ch_in;
+
+    return true;
+}
+
+cyg_uint8 CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_getc(void* __ch_data)
+{
+    cyg_uint8 ch;
+    CYGARC_HAL_SAVE_GP();
+
+    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+    return ch;
+}
+
+
+//=============================================================================
+// Virtual vector HAL diagnostics
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+static void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
+                         cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* p_ch_in)
+{
+    int delay_count;
+    cyg_bool res;
+    CYGARC_HAL_SAVE_GP();
+
+    // delay in .1 ms steps
+    delay_count = ((channel_data_t*)__ch_data)->msec_timeout * 10;
+
+    for(;;) {
+        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, p_ch_in);
+        if (res || 0 == delay_count--)
+            break;
+
+        CYGACC_CALL_IF_DELAY_US(100);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS uart_p = ((channel_data_t*)__ch_data)->base;
+    cyg_uint8 ser_port_reg;
+    int ret = 0;
+    va_list ap;
+
+    CYGARC_HAL_SAVE_GP();
+    va_start(ap, __func);
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        chan->irq_state = 1;
+        HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+        HAL_INTERRUPT_UNMASK(chan->isr_vector);
+
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
+        ser_port_reg |= CYGHWR_DEV_FREESCALE_UART_C2_RIE;
+        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
+
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = chan->irq_state;
+        chan->irq_state = 0;
+        HAL_INTERRUPT_MASK(chan->isr_vector);
+
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
+        ser_port_reg &= ~(cyg_uint8)CYGHWR_DEV_FREESCALE_UART_C2_RIE;
+        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+        ret = chan->msec_timeout;
+        chan->msec_timeout = va_arg(ap, cyg_uint32);
+    case __COMMCTL_GETBAUD:
+        ret = chan->baud_rate;
+        break;
+    case __COMMCTL_SETBAUD:
+        chan->baud_rate = va_arg(ap, cyg_int32);
+        // Should we verify this value here?
+        cyg_hal_plf_serial_init_channel(chan);
+        ret = 0;
+        break;
+    default:
+        break;
+    }
+
+    va_end(ap);
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
+                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base;
+    cyg_uint8 uart_s1;
+    int res = 0;
+    cyg_uint8 ch_in;
+    CYGARC_HAL_SAVE_GP();
+
+    *__ctrlc = 0;
+
+    HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1);
+    if (uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_RDRF) {
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_in);
+        if( cyg_hal_is_break( (char *) &ch_in , 1 ) )
+            *__ctrlc = 1;
+
+        res = CYG_ISR_HANDLED;
+    }
+
+    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_init(void)
+{
+    hal_virtual_comm_table_t* comm;
+    int cur;
+    int chan_i;
+
+    cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    // Init channels
+    for(chan_i=0; chan_i<CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS; chan_i++) {
+        cyg_hal_plf_serial_init_channel(&plf_ser_channels[chan_i]);
+
+        // Setup procs in the vector table
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(chan_i);
+        comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+        CYGACC_COMM_IF_CH_DATA_SET(*comm, &plf_ser_channels[chan_i]);
+        CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+        CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+        CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+        CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+        CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+        CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+        CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+    }
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD)
+    plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate =
+        CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD;
+    update_baud_rate( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL] );
+#endif
+}
+
+void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+
+    if (initialized)
+        return;
+    initialized = 1;
+    cyg_hal_plf_serial_init();
+}
+
+#else // !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+//=============================================================================
+// Non-Virtual vector HAL diagnostics
+
+// #if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+void hal_plf_diag_init(void)
+{
+    cyg_hal_plf_serial_init( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] );
+}
+
+void hal_plf_diag_putc(char c)
+{
+    cyg_hal_plf_serial_putc( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c);
+}
+
+cyg_uint8 hal_plf_diag_getc(void)
+{
+    return cyg_hal_plf_serial_getc( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] );
+}
+
+#endif // defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+//-----------------------------------------------------------------------------
+// End of hal_diag.c
diff --git a/packages/hal/cortexm/kinetis/var/current/src/kinetis_clocking.c b/packages/hal/cortexm/kinetis/var/current/src/kinetis_clocking.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_clocking.c
@@ -0,0 +1,463 @@
+//==========================================================================
+//
+//      kinetis_clocking.c
+//
+//      Cortex-M Kinetis HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija kocho <ilijak@siva.com.mk>
+// Date:         2011-10-19
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/cortexm_endian.h>
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+
+#include <cyg/io/ser_freescale_uart.h>
+
+//===========================================================================
+// Forward declarations
+//===========================================================================
+
+cyg_uint32 hal_cortexm_systick_clock;
+cyg_uint32 hal_kinetis_sysclk;
+cyg_uint32 hal_kinetis_busclk;
+
+cyg_uint32 hal_get_cpu_clock(void);
+
+void hal_start_main_clock(void);
+void hal_set_clock_dividers(void);
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_RTC
+void hal_start_rtc_clock(void);
+#endif
+
+
+//==========================================================================
+// Setup up system clocks
+//
+// Set up clocks from configuration. In the future this should be extended so
+// that clock rates can be changed at runtime.
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_start_clocks( void )
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT
+    cyghwr_hal_kinetis_port_t *port_p = CYGHWR_HAL_KINETIS_PORTA_P;
+#endif
+#if !defined(CYG_HAL_STARTUP_RAM)
+# ifdef CYGHWR_HAL_CORTEXM_KINETIS_RTC
+    // Real Time Clock
+    hal_start_rtc_clock();
+# endif
+    hal_set_clock_dividers();
+    // Main clock - MCG
+    hal_start_main_clock();
+#endif
+    // Trace clock
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACECLK_CORE
+    sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_M;
+#else
+    sim_p->sopt2 &= ~CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_M;
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT
+    port_p->pcr[6] = CYGHWR_HAL_KINETIS_PORT_PCR_MUX(0x7);
+#endif
+}
+
+
+#define MCG_WAIT_WHILE(_condition_) do{}while(_condition_)
+
+// Setup MCG
+// Note: Currently only PBE mode is supported and tested.
+
+#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL
+
+// MCG can have 1 or 2 PLL oscillators.
+// PLL0 aka PLL is always present.
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_start_pll0(cyghwr_hal_kinetis_mcg_t *mcg_p)
+{
+    mcg_p->c5 = CYGHWR_HAL_KINETIS_MCG_C5_PRDIV(
+          CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV-1) |
+          CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_M
+# ifdef CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1
+          | CYGHWR_HAL_KINETIS_MCG_C5_PLLREFSEL0_M
+# endif //CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1
+          ;
+# if CYGINT_HAL_CORTEXM_KINETIS_150
+    mcg_p->c6 = CYGHWR_HAL_KINETIS_MCG_C6_VDIV(
+          CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV-16);
+# else
+    mcg_p->c6 = CYGHWR_HAL_KINETIS_MCG_C6_VDIV(
+          CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV-24);
+# endif
+    mcg_p->c5 |= CYGHWR_HAL_KINETIS_MCG_C5_PLLCLKEN_M;
+    MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_LOCK_M));
+}
+#endif //CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL
+
+#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+
+// PLL1 Oscillator is present on some devices.
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_start_pll1(cyghwr_hal_kinetis_mcg_t *mcg_p)
+{
+    mcg_p->c11 = CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_M;
+    mcg_p->c11 = CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1(
+          CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_PRDIV-1) |
+          CYGHWR_HAL_KINETIS_MCG_C11_PLLSTEN1_M
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1
+          | CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_M
+# endif
+# ifdef CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL_1
+          | CYGHWR_HAL_KINETIS_MCG_C11_PLLREFSEL1_M
+# endif
+          ;
+    mcg_p->c12 = CYGHWR_HAL_KINETIS_MCG_C12_VDIV1(
+          CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_VDIV-16);
+    mcg_p->c11 |= CYGHWR_HAL_KINETIS_MCG_C11_PLLCLKEN1_M;
+    MCG_WAIT_WHILE(!(mcg_p->s2 & CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_M));
+}
+#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+
+#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+
+// There are 1 or 2 external oscillators
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_start_ext_ref(void)
+{
+    volatile cyg_uint8 *osc_cr_p = CYGHWR_HAL_KINETIS_OSC_CR_P;
+
+# if defined CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_0 || \
+     defined CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL_0
+#  ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL
+    // Set the oscillator 0
+    *osc_cr_p = CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP / 2;
+#  elif defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_OSC
+    // Select external oscillator
+    *osc_cr_p = CYGHWR_HAL_KINETIS_OSC_CR_ERCLKEN_M |
+          CYGHWR_HAL_KINETIS_OSC_CR_EREFSTEN_M;
+#  endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL
+# endif // CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_0 || ...
+
+# if defined CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1 || \
+     defined CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL_1
+#  ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_XTAL
+    // Set the oscillator 1
+    osc_cr_p = CYGHWR_HAL_KINETIS_OSC1_CR_P;
+    *osc_cr_p = CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP / 2;
+#  elif defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_OSC
+    // Select external oscillator
+    *osc_cr_p = CYGHWR_HAL_KINETIS_OSC1_CR_ERCLKEN_M |
+          CYGHWR_HAL_KINETIS_OSC1_CR_EREFSTEN_M;
+#  endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_XTAL
+# endif // CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1 || ...
+}
+#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_start_main_clock(void)
+{
+    cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P;
+#if defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL ||\
+    defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1 ||\
+    (defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC &&\
+    CYGHWR_HAL_CORTEXM_KINETIS_REV == 1)
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+#endif
+
+#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC
+    // Select RTC clock source for MCG reference
+# if CYGHWR_HAL_CORTEXM_KINETIS_REV == 1
+    sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_MCGCLKSEL_M;
+# elif CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+    mcg_p->c7 |= CYGHWR_HAL_KINETIS_MCG_C7_OSCSEL_M;
+# endif // CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC
+
+#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+    hal_start_ext_ref();
+# endif
+
+#if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \
+    defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \
+    defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) || \
+    defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
+
+    mcg_p->c2 = CYGHWR_HAL_KINETIS_MCG_C2_RANGE(
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE)
+#  ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL
+          | CYGHWR_HAL_KINETIS_MCG_C2_EREFS_M | CYGHWR_HAL_KINETIS_MCG_C2_HGO_M
+#  endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL
+          ;
+
+    mcg_p->c1 = CYGHWR_HAL_KINETIS_MCG_C1_FRDIV(
+        CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG)
+# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \
+     defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \
+     defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
+        |CYGHWR_HAL_KINETIS_MCG_C1_CLKS(CYGHWR_HAL_KINETIS_MCG_C1_CLKS_EXT_REF)
+# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL*
+        ;
+
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL
+    // Wait for oscillator start up
+    MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_OSCINIT_M));
+# endif
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_XTAL
+    // Wait for oscillator 1 start up
+    MCG_WAIT_WHILE(!(mcg_p->s2 & CYGHWR_HAL_KINETIS_MCG_S2_OSCINIT1_M));
+# endif
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+    // Wait for reference clock to switch to external reference
+    MCG_WAIT_WHILE(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_IREFST_M);
+    // Wait for status flags update
+    MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) !=
+#  if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \
+      defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \
+      defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
+            CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT
+#  else
+            CYGHWR_HAL_KINETIS_MCG_S_CLKST_FLL
+#  endif
+            );
+# endif //  CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL
+    // Configure FLL
+    mcg_p->c4 = (mcg_p->c4 & 0x1f) |
+          (CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 |
+           CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS(
+               CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS));
+
+# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL
+
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL
+    hal_start_pll0(mcg_p);
+# endif
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+    hal_start_pll1(mcg_p);
+# endif
+# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL) || \
+     defined(CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1)
+    // Switch to PBE mode
+    mcg_p->c6 |=  CYGHWR_HAL_KINETIS_MCG_C6_PLLS_M;
+
+    MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) !=
+                   CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT);
+    MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_PLLST_M));
+#  ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL
+    MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_LOCK_M));
+#  endif
+#  if defined CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+    MCG_WAIT_WHILE(!(mcg_p->s2 & CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_M));
+#  endif // CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+
+    // Enter PEE mode
+    mcg_p->c1 &= ~CYGHWR_HAL_KINETIS_MCG_C1_CLKS_M;
+    MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) !=
+                   CYGHWR_HAL_KINETIS_MCG_S_CLKST_PLL);
+# endif // defined CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL*
+
+# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \
+     defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \
+     defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
+    sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_PLLFLLSEL_M;
+# endif
+
+#endif // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) ||
+       // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) ||
+       // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) ||
+       // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
+}
+
+cyg_uint32 CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_get_cpu_clock(void)
+{
+    cyg_uint32 freq;
+#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL
+    cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P;
+
+# if CYGINT_HAL_CORTEXM_KINETIS_150
+    freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+          ((mcg_p->c5 & CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_M)+1) *
+          ((mcg_p->c6 & CYGHWR_HAL_KINETIS_MCG_C6_VDIV_M)+16) / 2;
+# else
+    freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+          ((mcg_p->c5 & CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_M)+1) *
+          ((mcg_p->c6 & CYGHWR_HAL_KINETIS_MCG_C6_VDIV_M)+24);
+# endif
+#elif defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1
+    cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P;
+
+    freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+          ((mcg_p->c11 & CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_M)+1) *
+          ((mcg_p->c12 & CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_M)+16) / 2;
+#elif defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL)
+    freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV;
+#elif defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
+    freq = CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC;
+#else // ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_none
+#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_end
+
+    return freq;
+}
+
+
+// Clock dividers provide clock sources for various peripherals.
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_set_clock_dividers(void)
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+
+    sim_p->clk_div1 = CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1(0) |
+          CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2(
+                CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS-1)  |
+          CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3(
+                CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS-1) |
+          CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4(
+                CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH-1);
+
+    sim_p->clk_div2 = CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV(
+                          CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV-1) |
+                          (CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC==2 ?
+                               CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBFRAC_M : 0);
+}
+
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_RTC
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_start_rtc_clock(void)
+{
+    cyghwr_hal_kinetis_rtc_t *rtc_p = CYGHWR_HAL_KINETIS_RTC_P;
+
+    rtc_p->ier=0; // Disable RTC interrupts
+
+    //Start RTC clock if not already started
+    if(!(rtc_p->cr & CYGHWR_HAL_KINETIS_RTC_CR_OSCE)){
+        rtc_p->cr = CYGHWR_HAL_KINETIS_RTC_CR_OSCE |
+              CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP;
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC
+        {
+            volatile cyg_uint32 busycnt;
+            for(busycnt=1000000; busycnt; busycnt--)
+                __asm__ volatile ("nop\n");
+        }
+# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC
+    }
+}
+#endif
+
+
+//==========================================================================
+// UART baud rate
+//
+// Set the baud rate divider of a UART based on the requested rate and
+// the current clock settings.
+
+
+void  CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_freescale_uart_setbaud(cyg_uint32 uart_p, cyg_uint32 baud)
+{
+    cyg_uint32 sbr, brfa;
+    cyg_uint32 regval;
+
+    switch(uart_p) {
+    case CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE:
+    case CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE:
+        sbr = hal_kinetis_sysclk/(16*baud);
+        break;
+    case CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE:
+    case CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE:
+    case CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE:
+    case CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE:
+        sbr = hal_kinetis_busclk/(16*baud);
+        break;
+    default:
+        sbr=0;
+        break;
+    }
+    if(sbr) {
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDH, regval);
+        regval &= 0xE0;
+        regval |= sbr >> 8;
+        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDH, regval);
+        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDL, (sbr & 0xFF));
+        brfa = (((32*hal_kinetis_busclk)/(16*baud))-(32*sbr));
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C4, regval);
+        regval &= 0xE0;
+        regval |= brfa & 0x1f;
+        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C4, regval);
+    }
+}
+
+
+void hal_update_clock_var(void)
+{
+    hal_kinetis_sysclk=hal_get_cpu_clock();
+    hal_kinetis_busclk=hal_kinetis_sysclk /
+          CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS;
+    hal_cortexm_systick_clock=hal_kinetis_sysclk;
+}
+
+
+cyg_uint32 hal_get_peripheral_clock(void)
+{
+    return hal_kinetis_busclk;
+}
+
+//==========================================================================
+// EOF kinetis_clocking.c
diff --git a/packages/hal/cortexm/kinetis/var/current/src/kinetis_ddram.c b/packages/hal/cortexm/kinetis/var/current/src/kinetis_ddram.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_ddram.c
@@ -0,0 +1,129 @@
+//==========================================================================
+//
+//      kinetis_ddram.c
+//
+//      Cortex-M Kinetis HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija kocho <ilijak@siva.com.mk>
+// Date:         2012-03-08
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/cortexm_endian.h>
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+
+// DDRAM Controller
+#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC
+
+// DDRAM controller register indices.
+const cyg_uint8 const kinetis_ddr_reg_ix[] = {
+    0,
+    2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+    20, 21, 22, 23,
+    25, 26, 27, 28, 29, 30,
+    34,
+    36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
+    52, 53, 54, 55, 56, 57
+};
+
+// Initialize DDRAM controller.
+// inidat[] is an array of ordered pairs: (register-index, register-value).
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_cortexm_kinetis_ddrmc_init(const cyg_uint32 inidat[])
+{
+    cyghwr_hal_kinetis_ddrmc_t* ddrmc_p = CYGHWR_HAL_KINETIS_DDRMC_P;
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    volatile cyg_uint32* cr_p;
+    cyg_uint32 cr_ix;
+    cyg_uint32 cr_i;
+    cyg_uint32 regval;
+    
+    CYGHWR_IO_CLOCK_ENABLE(CYGHWR_HAL_KINETIS_SIM_SCGC_DDR);
+
+    regval = sim_p->mcr & ~CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP_M;
+    sim_p->mcr   = regval | CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP;
+
+    ddrmc_p->rcr |= CYGHWR_HAL_KINETIS_DDRMC_RCR_RST_M;
+    ddrmc_p->pad_ctrl = CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL;
+    cr_p = ddrmc_p->cr;
+    for(cr_ix = 0; cr_ix < sizeof(kinetis_ddr_reg_ix); cr_ix++) {
+        cr_i = kinetis_ddr_reg_ix[cr_ix];
+        cr_p[cr_i] = *inidat++;
+    };
+    __asm__ volatile ("nop\n");
+    ddrmc_p->cr[0] |= CYGHWR_HAL_KINETIS_DDRMC_CR00_START;
+    while(!(ddrmc_p->cr[30] & CYGHWR_HAL_KINETIS_DDRMC_CR30_DRAM_INIT_CPL));
+}
+
+void
+hal_cortexm_kinetis_ddrmc_diag(void)
+{
+    cyghwr_hal_kinetis_ddrmc_t* ddrmc_p = CYGHWR_HAL_KINETIS_DDRMC_P;
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    volatile cyg_uint32* cr_p;
+    cyg_uint32 cr_i;
+
+    diag_printf("SCGC3 = 0x%08x, MCR = 0x%08x\n", sim_p->scgc3, sim_p->mcr);
+    diag_printf("RCR= 0x%08x, PAD_CTRL= 0x%08x\n", ddrmc_p->rcr, ddrmc_p->pad_ctrl);
+    cr_p = ddrmc_p->cr;
+    for(cr_i=0; cr_i < 64; cr_i++){
+        diag_printf("  CR%02d = 0x%08x\n", cr_i, cr_p[cr_i]);
+    }
+}
+
+#endif // CYGPKG_HAL_CORTEXM_KINETIS_DDRMC
+
+//==========================================================================
+// EOF kinetis_ddram.c
diff --git a/packages/hal/cortexm/kinetis/var/current/src/kinetis_gpio.c b/packages/hal/cortexm/kinetis/var/current/src/kinetis_gpio.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_gpio.c
@@ -0,0 +1,146 @@
+//==========================================================================
+//
+//      kinetis_gpio.c
+//
+//      Cortex-M Kinetis HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2014 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ilijak
+// Date:         2014-02-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/var_io_gpio.h>
+
+static cyghwr_hal_kinetis_gpio_t * const PortsGPIO[] = {
+    CYGHWR_HAL_KINETIS_GPIO_PORTA_P, CYGHWR_HAL_KINETIS_GPIO_PORTB_P,
+    CYGHWR_HAL_KINETIS_GPIO_PORTC_P, CYGHWR_HAL_KINETIS_GPIO_PORTD_P,
+    CYGHWR_HAL_KINETIS_GPIO_PORTE_P, CYGHWR_HAL_KINETIS_GPIO_PORTF_P
+};
+
+void
+hal_gpio_pin_ddr_out(cyg_uint32 pin){
+    cyghwr_hal_kinetis_gpio_t *port_p;
+
+    if(pin != CYGHWR_HAL_KINETIS_PIN_NONE) {
+        port_p = PortsGPIO[CYGHWR_HAL_KINETIS_PIN_PORT(pin)];
+        port_p->pddr |= BIT_(CYGHWR_HAL_KINETIS_PIN_BIT(pin));
+    }    
+}
+
+void
+hal_gpio_pin_ddr_in(cyg_uint32 pin){
+    cyghwr_hal_kinetis_gpio_t *port_p;
+
+    if(pin != CYGHWR_HAL_KINETIS_PIN_NONE) {
+        port_p = PortsGPIO[CYGHWR_HAL_KINETIS_PIN_PORT(pin)];
+        port_p->pddr &= ~BIT_(CYGHWR_HAL_KINETIS_PIN_BIT(pin));
+    }    
+}
+
+cyg_uint32
+hal_gpio_get_pin(cyg_uint32 pin){
+    cyghwr_hal_kinetis_gpio_t *port_p;
+    cyg_uint32 retval = 0xffffffff;
+    
+    if(pin != CYGHWR_HAL_KINETIS_PIN_NONE) {
+        port_p = PortsGPIO[CYGHWR_HAL_KINETIS_PIN_PORT(pin)];
+        retval = port_p->pdir & BIT_(CYGHWR_HAL_KINETIS_PIN_BIT(pin));
+    }
+    return retval;
+}
+
+
+// GPIO register on a given port (register name is lower case)
+#define CYGHWR_HAL_KINETIS_GPIO_PORT_OPER(__port, __mask, __opreg) \
+CYG_MACRO_START                                                    \
+    cyghwr_hal_kinetis_gpio_t *port_p;                             \
+    port_p = PortsGPIO[__port];                                    \
+    port_p->__opreg = __mask;                                      \
+CYG_MACRO_END
+
+#define CYGHWR_HAL_KINETIS_GPIO_PIN_OPER(__pin, __opreg)                                 \
+CYG_MACRO_START                                                                          \
+if(__pin != CYGHWR_HAL_KINETIS_PIN_NONE)                                                 \
+    CYGHWR_HAL_KINETIS_GPIO_PORT_OPER(CYGHWR_HAL_KINETIS_PIN_PORT(__pin),                \
+                                      BIT_(CYGHWR_HAL_KINETIS_PIN_BIT(__pin)), __opreg); \
+CYG_MACRO_END
+
+// Port operations
+// Bit operations (clear, set or toggle) are performed on port's bits
+// that correspond to set bits in the mask parameter.
+
+void
+hal_gpio_port_clear(cyg_uint32 port_i, cyg_uint32 mask){
+    CYGHWR_HAL_KINETIS_GPIO_PORT_OPER(port_i, mask, pcor);
+}
+
+void
+hal_gpio_port_set(cyg_uint32 port_i, cyg_uint32 mask){
+    CYGHWR_HAL_KINETIS_GPIO_PORT_OPER(port_i, mask, psor);
+}
+
+void
+hal_gpio_port_toggle(cyg_uint32 port_i, cyg_uint32 mask){
+    CYGHWR_HAL_KINETIS_GPIO_PORT_OPER(port_i, mask, ptor);
+}
+
+// Pin operations.
+// Operation is performed to a given pin. Thin is addresses through
+// a pin descriptor. Pin descriptor is typically created with CYGHWR_HAL_KINETIS_PIN_CFG()
+// or CYGHWR_HAL_KINETIS_PIN() [ defined in var_io.h ]
+
+void
+hal_gpio_pin_clear(cyg_uint32 pin){
+    CYGHWR_HAL_KINETIS_GPIO_PIN_OPER(pin, pcor);
+}
+
+void
+hal_gpio_pin_set(cyg_uint32 pin){
+    CYGHWR_HAL_KINETIS_GPIO_PIN_OPER(pin, psor);
+}
+
+void
+hal_gpio_pin_toggle(cyg_uint32 pin){
+    CYGHWR_HAL_KINETIS_GPIO_PIN_OPER(pin, ptor);
+}
+
+// EOF kinetis_gpio.c
diff --git a/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c b/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c
@@ -0,0 +1,309 @@
+//==========================================================================
+//
+//      kinetis_misc.c
+//
+//      Cortex-M Kinetis HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija kocho <ilijak@siva.com.mk>
+// Date:         2011-02-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/cortexm_endian.h>
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+
+#include <cyg/hal/hal_cache.h>
+
+void sst25xx_freescale_dspi_reg(void);
+
+#if defined CYG_HAL_STARTUP_ROM && !defined CYG_HAL_STARTUP_RAM
+
+//===========================================================================
+// KINETIS FLASH configuration field
+//===========================================================================
+
+// Note: KINETIS FLASH configuration field must be present in Kinetis flash
+//       image and ocupy addresses 0x00000400 to 0x0000040f.
+
+// For ".flash_conf" section definition see MLT files.
+
+const cyghwr_hal_kinetis_flash_conf_t CYGHWR_HAL_KINETIS_FLASH_CONF_FIELD
+__attribute__((section(".flash_conf"), used)) = {
+    .backdoor_key = CYGHWR_HAL_KINETIS_FLASH_CONF_BACKDOOR_KEY,
+    .fprot = CYGHWR_HAL_KINETIS_FLASH_CONF_FPROT,
+    .fsec = CYGHWR_HAL_KINETIS_FLASH_CONF_FSEC,
+    .fopt = CYGHWR_HAL_KINETIS_FLASH_CONF_FOPT,
+    .feprot = CYGHWR_HAL_KINETIS_FLASH_CONF_FEPROT,
+    .fdprot = CYGHWR_HAL_KINETIS_FLASH_CONF_FDPROT
+};
+
+const cyghwr_hal_kinetis_flash_conf_t *
+CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_kinetis_flash_conf_p( void )
+{
+    return &CYGHWR_HAL_KINETIS_FLASH_CONF_FIELD;
+}
+
+#endif // defined CYG_HAL_STARTUP_ROM && !defined CYG_HAL_STARTUP_RAM
+
+//=== KINETIS FLASH security configuration END. ============================
+
+#if defined CYGPKG_HAL_KINETIS_CACHE
+
+// Function for demotion of caching memory regions
+static void
+hal_cortexm_kinetis_conf_cache_regions(cyghwr_hal_kinetis_lmem_t* lmem_p,
+                                      cyg_uint32 reg_n, const cyg_uint32 *reg_mode_p)
+{
+    cyg_uint32 region;
+    cyg_uint32 mode;
+    cyg_uint32 regval;
+    cyg_uint32 reg_mode;
+
+    regval = lmem_p->rmr;
+    for(; reg_n; reg_n--){
+        reg_mode = *reg_mode_p++;
+        region = reg_mode >> 16;
+        mode = reg_mode & 0x0000ffff;
+        regval &= ~(0x3 << (15-region)*2);
+        regval |= mode << (15-region)*2;
+    }
+    lmem_p->rmr = regval;
+}
+
+const cyg_uint32 cache_reg_modes_pc[] = {
+    (CYGHWR_HAL_KINETIS_LMEM_DRAM_7000 << 16) |
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M,
+
+    (CYGHWR_HAL_KINETIS_LMEM_DRAM_8000 << 16) |
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M
+};
+
+const cyg_uint32 cache_reg_modes_ps[] = {
+    (CYGHWR_HAL_KINETIS_LMEM_FLASH_0000 << 16) |
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M,
+
+    (CYGHWR_HAL_KINETIS_LMEM_DRAM_0800 << 16) |
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M,
+
+    (CYGHWR_HAL_KINETIS_LMEM_DRAM_7000 << 16) |
+#if defined CYGSEM_HAL_DCACHE_STARTUP_MODE_WRITETHRU
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WT_M,
+#elif defined CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WB_M,
+#else
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M,
+#endif
+
+    (CYGHWR_HAL_KINETIS_LMEM_DRAM_8000 << 16) |
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M
+};
+
+#endif // defined CYGPKG_HAL_KINETIS_CACHE
+
+//==========================================================================
+// Setup variant specific hardware
+//=========================================================================
+
+void hal_variant_init( void )
+{
+#if defined CYGPKG_HAL_KINETIS_CACHE
+# if defined CYG_HAL_STARTUP_RAM
+    register CYG_INTERRUPT_STATE oldints;
+# endif
+#endif
+
+    hal_update_clock_var();
+
+#if defined CYGPKG_HAL_KINETIS_CACHE
+# if defined CYG_HAL_STARTUP_RAM
+    HAL_DISABLE_INTERRUPTS(oldints);
+    HAL_DCACHE_SYNC();
+    HAL_DCACHE_DISABLE();
+    HAL_DCACHE_PURGE_ALL();
+    HAL_ICACHE_DISABLE();
+    HAL_ICACHE_INVALIDATE_ALL();
+# endif // defined CYG_HAL_STARTUP_RAM
+    hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PS_P,
+        sizeof(cache_reg_modes_ps)/sizeof(cache_reg_modes_ps[0]),
+        cache_reg_modes_ps);
+    hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PC_P,
+        sizeof(cache_reg_modes_pc)/sizeof(cache_reg_modes_pc[0]),
+        cache_reg_modes_pc);
+# if defined CYG_HAL_STARTUP_RAM
+    HAL_RESTORE_INTERRUPTS(oldints);
+# endif
+# ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
+    HAL_ICACHE_ENABLE();
+# endif
+# ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
+    HAL_DCACHE_ENABLE();
+# endif
+#endif // defined CYGPKG_HAL_KINETIS_CACHE
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    hal_if_init();
+#endif
+}
+
+//===========================================================================
+// The  WDOG at Freescale Kinetis is enabled after reset. hal_wdog_disable
+// provides functionality for disabling it at startup.
+//===========================================================================
+
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_kinetis_wdog_unlock_simple(volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p)
+{
+    wdog_p->Unlock = 0xC520;
+    wdog_p->Unlock = 0xD928;
+}
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_kinetis_wdog_unlock(volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p)
+{
+    CYGARC_CPSID( i );
+    hal_kinetis_wdog_unlock_simple(wdog_p);
+    CYGARC_CPSIE( i );
+}
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_wdog_disable(void)
+{
+    volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p = CYGHWR_HAL_KINETIS_WDOG_P;
+    hal_kinetis_wdog_unlock_simple(wdog_p);
+    wdog_p->StCtrlH = CYGHWR_HAL_KINETIS_WDOG_STCTRLH_ALLOWUPDATE_M;
+}
+
+//==========================================================================
+// Pin configuration functions
+//
+
+static cyghwr_hal_kinetis_port_t * const Ports[] = {
+    CYGHWR_HAL_KINETIS_PORTA_P, CYGHWR_HAL_KINETIS_PORTB_P,
+    CYGHWR_HAL_KINETIS_PORTC_P, CYGHWR_HAL_KINETIS_PORTD_P,
+    CYGHWR_HAL_KINETIS_PORTE_P, CYGHWR_HAL_KINETIS_PORTF_P
+};
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_set_pin_function(cyg_uint32 pin)
+{
+    cyghwr_hal_kinetis_port_t *port_p;
+
+    if(pin != CYGHWR_HAL_KINETIS_PIN_NONE) {
+        port_p = Ports[CYGHWR_HAL_KINETIS_PIN_PORT(pin)];
+        port_p->pcr[CYGHWR_HAL_KINETIS_PIN_BIT(pin)] =
+              CYGHWR_HAL_KINETIS_PIN_FUNC(pin);
+    }
+}
+
+void
+hal_dump_pin_function(cyg_uint32 pin)
+{
+    cyghwr_hal_kinetis_port_t *port_p;
+
+    if(pin != CYGHWR_HAL_KINETIS_PIN_NONE) {
+        port_p = Ports[CYGHWR_HAL_KINETIS_PIN_PORT(pin)];
+        diag_printf("Port        %d: %p[%d] fun=%x\n",
+            CYGHWR_HAL_KINETIS_PIN_PORT(pin),
+            port_p,
+            CYGHWR_HAL_KINETIS_PIN_BIT(pin),
+            port_p->pcr[CYGHWR_HAL_KINETIS_PIN_BIT(pin)]);
+    }
+}
+
+void
+hal_dump_pin_setting(cyg_uint32 pin)
+{
+    if(pin != CYGHWR_HAL_KINETIS_PIN_NONE) {
+        diag_printf("Pin: 0x%08x Port=%d bit=%d fun=%x\n",
+            pin,
+            CYGHWR_HAL_KINETIS_PIN_PORT(pin),
+            CYGHWR_HAL_KINETIS_PIN_BIT(pin),
+            CYGHWR_HAL_KINETIS_PIN_FUNC(pin));
+    }
+}
+
+//==========================================================================
+// Clock distribution
+//
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_clock_enable(cyg_uint32 desc)
+{
+    volatile cyg_uint32 *scgc_p;
+
+    if(desc != CYGHWR_HAL_SCGC_NONE) {
+        scgc_p = &CYGHWR_HAL_KINETIS_SIM_P->scgc1 +
+                 CYGHWR_HAL_KINETIS_SIM_SCGC_REG(desc);
+        *scgc_p |= 1 << CYGHWR_HAL_KINETIS_SIM_SCGC_BIT(desc);
+    }
+}
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_clock_disable(cyg_uint32 desc)
+{
+    volatile cyg_uint32 *scgc_p;
+
+    if(desc != CYGHWR_HAL_SCGC_NONE) {
+        scgc_p = &CYGHWR_HAL_KINETIS_SIM_P->scgc1 +
+                 CYGHWR_HAL_KINETIS_SIM_SCGC_REG(desc);
+        *scgc_p &= ~(1 << CYGHWR_HAL_KINETIS_SIM_SCGC_BIT(desc));
+    }
+}
+
+//==========================================================================
+// EOF kinetis_misc.c
diff --git a/packages/hal/cortexm/lm3s/ek_lm3s811/current/ChangeLog b/packages/hal/cortexm/lm3s/ek_lm3s811/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/ek_lm3s811/current/ChangeLog
@@ -0,0 +1,39 @@
+2011-02-09  John Dallaway  <john@dallaway.org.uk>
+
+	* doc/ek_lm3s811.sgml: Eliminate underscores in SGML ID strings. They
+	cause problems for some installations of openjade.
+
+	* cdl/hal_cortexm_ek_lm3s811.cdl: Fix documentation filename to match
+	the above change.
+
+2011-01-18  Christophe Coutand  <ccoutand@stmi.com>
+
+	* cdl/hal_cortexm_ek_lm3s811.cdl:
+	* doc/ek_lm3s811.sgml:
+	* src/ek_lm3s811_misc.c:
+	* src/platform_i2c.c:
+	New package -- Stellaris Cortex-M3 EK-LM3S811 platform HAL.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/hal/cortexm/lm3s/ek_lm3s811/current/cdl/hal_cortexm_ek_lm3s811.cdl b/packages/hal/cortexm/lm3s/ek_lm3s811/current/cdl/hal_cortexm_ek_lm3s811.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/ek_lm3s811/current/cdl/hal_cortexm_ek_lm3s811.cdl
@@ -0,0 +1,78 @@
+# ====================================================================
+##
+##      hal_cortexm_ek_lm3s811.cdl
+##
+##      Stellaris Cortex-M3 EK-LM3S811 board platform HAL
+##
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      ccoutand
+# Contributors:   
+# Date:           2011-01-18
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_EK_LM3S811 {
+    display       "Stellaris EK-LM3S811 Development Board HAL"
+    doc           ref/hal-cortexm-lm3s-ek-lm3s811.html
+    parent        CYGPKG_HAL_CORTEXM_LM3S8XX
+    define_header hal_cortexm_ek_lm3s811.h
+    include_dir   cyg/hal
+    hardware
+
+    description   "
+        The EK-LM3S811 HAL package provides the support needed to run
+        eCos on the Stellaris EK-LM3S811 EVAL board."
+
+    compile       ek_lm3s811_misc.c platform_i2c.c
+
+    requires      { CYGHWR_HAL_CORTEXM_LM3S == "LM3S8XX" }
+    requires      { CYGHWR_HAL_CORTEXM_LM3S8XX == "LM3S811" }
+    requires      { CYGNUM_HAL_CORTEXM_LM3S8XX_XTAL_FREQ == 6000000 }
+    requires      { CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT == 1 }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_ek_lm3s811.h>"
+        puts $::cdl_header "#include <pkgconf/hal_cortexm_lm3s8xx.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M3 - LM3S811\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Stellaris EK-LM3S811\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+}
+
+# EOF hal_cortexm_ek_lm3s811.cdl
diff --git a/packages/hal/cortexm/lm3s/ek_lm3s811/current/doc/ek_lm3s811.sgml b/packages/hal/cortexm/lm3s/ek_lm3s811/current/doc/ek_lm3s811.sgml
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/ek_lm3s811/current/doc/ek_lm3s811.sgml
@@ -0,0 +1,140 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     ek_lm3s811.sgml                                             -->
+<!--                                                                 -->
+<!--     ek_lm3s811 board documentation.                             -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2011 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   ccoutand                                           -->
+<!-- Contact(s):  ccoutand                                           -->
+<!-- Date:        2011/01/18                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<part id="hal-cortexm-lm3s-ek-lm3s811"><title>Stellaris EKK-LM3S811 Board Support</title>
+
+<refentry id="lm3s-ek-lm3s811">
+  <refmeta>
+    <refentrytitle>Overview</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>eCos Support for the Stellaris EKK-LM3S811 Board</refname>
+    <refpurpose>Overview</refpurpose>
+  </refnamediv>
+
+  <refsect1 id="lm3s-ek-lm3s811-description"><title>Description</title>
+    <para>
+The Stellaris EKK-LM3S811 evaluation kit uses the Stellaris LM3S811 microcontroller from the 
+800 Series. The LM3S811 is an ARM cortex-M3 based microcontroller with 64KB of FLASH 
+and 8KB of SRAM. The device has various peripherals such as UART, I2C, ADC or Analog
+Comparator. The kit features an OLED graphical display and UART0 is accessible via the 
+on-board USB to UART converter.
+    </para>
+    <para>
+Due to extreme limited RAM ressources (8KB SRAM only), the eCos port targets standalone ROM  
+application using the eCos kernel in single user thread environment. The cortex-M architecture HAL 
+requires a seperate stack to handle interrupts, thus the minimum kernel enable application requires 3 
+stacks. The interrupt stack, the Idle thread stack and the user stack. All stacks are set to the architecture 
+minimum allowed size of CYGNUM_HAL_STACK_SIZE_MINIMUM ( 1360 bytes ). 
+    </para>
+  </refsect1>
+
+  <refsect1 id="lm3s-ek-lm3s811-config"><title>Configuration</title>
+    <para>
+The minimum board configuration includes the Microcontroller HAL alongs with the ADC and I2C device 
+drivers.
+    </para>
+    <variablelist>
+      <varlistentry>
+        <term><varname>LM3S811 Microcontroller</varname></term>
+        <listitem>
+        <para>
+CYGPKG_HAL_CORTEXM_LM3S8XX - The microcontroller configuration 
+requirements are minimal. With the default setup, the microcontroller runs from the 
+external clock source, a crystal of 6MHz. The chip internal PLL generates a fix 
+200MHz clock that is divided down to the default system clock frequency of 50MHz. 
+In this scenario, the device uses full processing power. The system clock divider 
+allows down scaling of the system clock frequency to reduce the overall power 
+consumption of the device. The microcontroller also offers the option to run from an
+internal oscillator. This option has 2 modes, 3MHz or 12MHz. When selecting the
+internal oscillator, the PLL is bypassed. The system clock frequency becomes at
+best 12MHz if no further clock division is applied.
+        </para>
+        </listitem>
+      </varlistentry>
+
+      <varlistentry>
+        <term><varname>I2C Interface</varname></term>
+        <listitem><para>
+CYGPKG_DEVS_I2C_CORTEXM_LM3S - The microcontroller uses the I2C bus 
+to communicate with the SD1300 controller of the OLED 96 x 16 display. The SD1300 
+controller eCos driver is not currently available.
+The I2C is default set to use the low frequency mode ( 100KHz bus clock ). The high 
+frequency mode ( 400 KHz ) is available by changing CYGNUM_HAL_CORTEXM_LM3S_I2C_CLK_SPEED.
+        </para></listitem>
+      </varlistentry>
+      <varlistentry>
+        <term><varname>ADC Interface</varname></term>
+        <listitem><para>
+CYGPKG_DEVS_ADC_CORTEXM_LM3S - The LM3S811 includes 4 ADC channels including an
+optional internal temperature probe. There are many ways to use the on-chip ADC.
+The current eCos driver uses a single sequencer (sequencer 0) to schedule sampling of all 
+channels. This practically means that all channels are sampled from the same trigger, a periodic timer
+interrupt in the current driver. The timer to use
+is selected from CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_SELECT_TIMER, with timer 0 as
+default value. The timer is used in 32 bits periodic mode, therefore cannot be re-used
+for any other user purpose. While the ADC has the possibility to trigger sampling on external 
+IO events, the driver does not offer that flexibility. Finally, the driver only allows measurement of
+single-ended IOs.
+        </para></listitem>
+      </varlistentry>
+    </variablelist>
+  </refsect1>
+
+  <refsect1 id="lm3s-ek-lm3s811-rebuild"><title>Build ROM type applications</title>
+    <para>
+The steps needed to build the HAL library for the EKK-LM3S811 board are:
+    </para>
+    <screen>
+$ mkdir ek_lm3s811
+$ cd ek_lm3s811
+$ ecosconfig new ek-lm3s811 minimal
+$ ecosconfig import $ECOS_REPOSITORY/hal/cortexm/lm3s/ek_lm3s811/current/misc/default_ROM.ecm
+$ ecosconfig resolve
+$ ecosconfig tree
+$ make
+    </screen>
+    <para>
+At the end of the build the <filename
+class="directory">install/lib</filename> subdirectory should contain the library and linker script and the <filename
+class="directory">install/include</filename> subdirectory the necessary includes to compile the application.
+    </para>
+  </refsect1>
+
+
+</refentry>
+
+</part>
diff --git a/packages/hal/cortexm/lm3s/ek_lm3s811/current/src/ek_lm3s811_misc.c b/packages/hal/cortexm/lm3s/ek_lm3s811/current/src/ek_lm3s811_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/ek_lm3s811/current/src/ek_lm3s811_misc.c
@@ -0,0 +1,163 @@
+//==========================================================================
+//
+//      ek_lm3s811_misc.c
+//
+//      Cortex-M3 Stellaris EK-LM3S811 HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Original for STM3210E EVAL: nickg
+//              Updated for EK-LM3S811: ccoutand
+// Date:        2011-01-18
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+
+
+// On-board status LED
+#define CYGHWR_HAL_EK_LM3S811_STATUS_LED \
+        CYGHWR_HAL_LM3S_GPIO( C, 5, OUT, 4_MA, PULLUP, DISABLE )
+
+// OLED regulator control
+#define CYGHWR_HAL_EK_LM3S811_OLED_PWD \
+        CYGHWR_HAL_LM3S_GPIO( D, 7, OUT, NONE, NONE, DISABLE )
+
+
+//==========================================================================
+// Drive OLED power ON/OFF IO
+
+__externC void
+hal_ek_lm3s811_oled_pwd( bool pwd )
+{
+    cyg_uint32      oled_pwd_io = CYGHWR_HAL_EK_LM3S811_OLED_PWD;
+
+    // Power ON regulator
+    if ( pwd == true )
+        CYGHWR_HAL_LM3S_GPIO_OUT( oled_pwd_io, 1 );
+    else
+        CYGHWR_HAL_LM3S_GPIO_OUT( oled_pwd_io, 0 );
+}
+
+
+//==========================================================================
+// Setup platform
+
+__externC void
+hal_platform_init( void )
+{
+    cyg_uint32      led_io = CYGHWR_HAL_EK_LM3S811_STATUS_LED;
+    cyg_uint32      oled_pwd_io = CYGHWR_HAL_EK_LM3S811_OLED_PWD;
+
+    // OLED power switch IO is on port D and user LED on port C
+    CYGHWR_HAL_LM3S_PERIPH_SET( CYGHWR_HAL_LM3S_P_GPIOC, 1 );
+    CYGHWR_HAL_LM3S_PERIPH_SET( CYGHWR_HAL_LM3S_P_GPIOD, 1 );
+    CYGHWR_HAL_LM3S_PERIPH_SET( CYGHWR_HAL_LM3S_P_I2C0, 0 );
+
+    // Status LED -> ON
+    CYGHWR_HAL_LM3S_GPIO_SET( led_io );
+    CYGHWR_HAL_LM3S_GPIO_OUT( led_io, 1 );
+
+    // Shutdown power regulator
+    CYGHWR_HAL_LM3S_GPIO_SET( oled_pwd_io );
+
+    hal_ek_lm3s811_oled_pwd( false );
+}
+
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS     start;             // Region start address
+    CYG_ADDRESS     end;               // End address (last byte)
+} hal_data_access[] = {
+#ifdef CYGMEM_REGION_sram              // On-chip SRAM
+    {
+    CYGMEM_REGION_sram, CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE - 1},
+#endif
+#ifdef CYGMEM_REGION_flash             // On-chip flash
+    {
+    CYGMEM_REGION_flash,
+            CYGMEM_REGION_flash + CYGMEM_REGION_flash_SIZE - 1},
+#endif
+    {
+    0xE0000000, 0x00000000 - 1},       // Cortex-M peripherals
+    {
+    0x40000000, 0x50000000 - 1},       // Stellaris peripherals
+};
+
+__externC int
+cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count )
+{
+    int             i;
+    for( i = 0; i < sizeof( hal_data_access ) / sizeof( hal_data_access[0] );
+         i++ ) {
+        if( ( addr >= hal_data_access[i].start )
+            && ( addr + count ) <= hal_data_access[i].end )
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+
+//==========================================================================
+// EOF ek_lm3s811_misc.c
diff --git a/packages/hal/cortexm/lm3s/ek_lm3s811/current/src/platform_i2c.c b/packages/hal/cortexm/lm3s/ek_lm3s811/current/src/platform_i2c.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/ek_lm3s811/current/src/platform_i2c.c
@@ -0,0 +1,178 @@
+//==========================================================================
+//
+//      platform_i2c.c
+//
+//      Optional I2C support for Cortex-M3 Stellaris EK-LM3S811
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors: 
+// Date:         2011-01-18
+// Purpose:      
+// Description:  
+//              
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+
+//=============================================================================
+//                               INCLUDES
+//=============================================================================
+#include <pkgconf/system.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/hal/hal_endian.h>
+#include <cyg/hal/hal_intr.h>
+
+#ifdef CYGPKG_DEVS_I2C_CORTEXM_LM3S
+
+#include <cyg/io/i2c.h>
+#include <cyg/io/i2c_lm3s.h>
+
+//=============================================================================
+// Setup I2C bus 0
+//
+static void
+lm3s8xx_i2c0_init( struct cyg_i2c_bus *bus )
+{
+    cyg_uint32      scl_io = CYGHWR_HAL_LM3S_I2C_SCL;
+    cyg_uint32      sda_io = CYGHWR_HAL_LM3S_I2C_SDA;
+
+    //
+    // We only need to setup the pins here and
+    // leave the I2C driver to take care of the rest.
+    //
+    CYGHWR_HAL_LM3S_PERIPH_SET( CYGHWR_HAL_LM3S_P_GPIOB, 1 );
+    CYGHWR_HAL_LM3S_GPIO_SET( scl_io );
+    CYGHWR_HAL_LM3S_GPIO_SET( sda_io );
+    lm3s_i2c_init( bus );
+}
+
+
+//-----------------------------------------------------------------------------
+// I2C bus 0
+//
+CYG_LM3S_I2C_BUS(hal_lm3s8xx_i2c0_bus,
+                 &lm3s8xx_i2c0_init,
+                 CYGHWR_HAL_LM3S_I2C_M0,
+                 CYGHWR_HAL_LM3S_P_I2C0,
+                 CYGNUM_HAL_INTERRUPT_I2C,
+                 0x60,
+                 10);
+
+
+//-----------------------------------------------------------------------------
+// OLED
+//
+CYG_I2C_DEVICE(i2c_lm3s8xx_oled,
+               &hal_lm3s8xx_i2c0_bus,
+               0x3d,
+               0,
+               CYG_I2C_DEFAULT_DELAY);
+
+
+#define DELAY 1
+
+// Wrapper to TI OLED driver
+
+externC cyg_uint32
+lm3s8xx_oled_write_first( cyg_uint8 byte )
+{
+    cyg_uint32      result;
+
+    cyg_i2c_transaction_begin( &i2c_lm3s8xx_oled );
+
+    result = cyg_i2c_transaction_tx( &i2c_lm3s8xx_oled,
+                                     true, ( cyg_uint8 * )&byte, 1, false );
+
+#ifdef CYGPKG_KERNEL
+    cyg_thread_delay( DELAY );
+#endif
+
+    return result;
+}
+
+externC cyg_uint32
+lm3s8xx_oled_write_byte( cyg_uint8 byte )
+{
+    cyg_uint32      result;
+
+    result = cyg_i2c_transaction_tx( &i2c_lm3s8xx_oled,
+                                     false, ( cyg_uint8 * )&byte, 1, false );
+
+#ifdef CYGPKG_KERNEL
+    cyg_thread_delay( DELAY );
+#endif
+
+    return result;
+}
+
+
+externC cyg_uint32
+lm3s8xx_oled_write_array( const cyg_uint8 *array, cyg_uint32 count )
+{
+    cyg_uint32      result;
+
+    result = cyg_i2c_transaction_tx( &i2c_lm3s8xx_oled,
+                                     false, array, count, false );
+
+    return result;
+}
+
+
+externC cyg_uint32
+lm3s8xx_oled_write_final( cyg_uint8 byte )
+{
+    cyg_uint32      result;
+
+    result = cyg_i2c_transaction_tx( &i2c_lm3s8xx_oled,
+                                     false, ( cyg_uint8 * )&byte, 1, true );
+#ifdef CYGPKG_KERNEL
+    cyg_thread_delay( DELAY );
+#endif
+
+    cyg_i2c_transaction_end( &i2c_lm3s8xx_oled );
+
+    return result;
+}
+
+#endif // #ifdef CYGPKG_DEVS_I2C_CORTEXM_LM3S
+
+//-----------------------------------------------------------------------------
+// EOF platform_i2c.c
diff --git a/packages/hal/cortexm/lm3s/lm3s8xx/current/ChangeLog b/packages/hal/cortexm/lm3s/lm3s8xx/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/ChangeLog
@@ -0,0 +1,42 @@
+2011-05-04  John Dallaway  <john@dallaway.org.uk>
+
+	* include/plf_io.h: Fix determination when CYGHWR_HAL_LM3S_ADC0_CHAN
+	should be 8. Patch from Anatoly Sokolov. [ Bugzilla 1001222 ]
+
+2011-01-18  Christophe Coutand  <ccoutand@stmi.com>
+
+	* cdl/hal_cortexm_lm3s8xx.cdl:
+	* include/pkgconf/mlt_cortexm_ek_lm3s811_rom.h:
+	* include/pkgconf/mlt_cortexm_ek_lm3s811_rom.ldi:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* misc/default_ROM.ecm:
+	* src/lm3s8xx_misc.c:
+	* tests/timers.c:
+	New package -- Stellaris Cortex M3 800 Series HAL.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
+
diff --git a/packages/hal/cortexm/lm3s/lm3s8xx/current/cdl/hal_cortexm_lm3s8xx.cdl b/packages/hal/cortexm/lm3s/lm3s8xx/current/cdl/hal_cortexm_lm3s8xx.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/cdl/hal_cortexm_lm3s8xx.cdl
@@ -0,0 +1,390 @@
+##==========================================================================
+##
+##    hal_cortexm_lm8xx.cdl
+##
+##    Stellaris Cortex-M3 800 Series variant HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ccoutand
+## Date:         2011-01-18
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_LM3S8XX {
+    display       "Stellaris Cortex-M3 800 Series"
+    parent        CYGPKG_HAL_CORTEXM
+    include_dir   cyg/hal
+    define_header hal_cortexm_lm3s8xx.h
+    hardware
+    description   "
+        This package provides generic support for the Cortex-M3 based
+        Stellaris LM 800 Series microcontroller family.  It is also
+        necessary to select a variant and platform HAL package."
+
+    compile       lm3s8xx_misc.c
+
+    implements    CYGINT_DEVS_I2C_LM3S8XX_BUS_DEVICES
+
+    requires      { CYGHWR_HAL_CORTEXM_LM3S == "LM3S8XX" }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_lm3s.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_CORTEXM_VAR_IO_H"
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LM3S8XX {
+        display       "Stellaris LM 800 Series variant in use"
+        flavor        data
+        default_value { "LM3S811" }
+        legal_values  { "LM3S828" "LM3S818" "LM3S817"
+                        "LM3S815" "LM3S812" "LM3S811"
+                        "LM3S808" "LM3S801" "LM3S800" }
+        description   "
+               The Stellaris 800 Series has several variants, the main
+               difference being the numbers of some peripherals"
+    }
+
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+        no_define
+
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+        }
+
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR
+        }
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value { "ROM" }
+        legal_values  { "ROM" }
+        no_define
+        define -file system.h CYG_HAL_STARTUP
+        description   "
+            With its 8KB of SRAM, the 800 Series devices only allows
+            ROM startup."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display          "Memory layout"
+        flavor data
+        no_define
+        calculated       { (CYG_HAL_STARTUP == "ROM") ? \
+                           "cortexm_lm3s8xx_rom" : "undefined" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display       "Memory layout linker script fragment"
+            flavor        data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated    { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display       "Memory layout header file"
+            flavor        data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated    { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK {
+        display       "Clocking"
+        flavor        none
+        requires      { CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT || \
+                        CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_INT }
+
+        cdl_component CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT {
+            display      "External clock source"
+            active_if     ! CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_INT
+            flavor        bool
+            default_value 1
+
+            cdl_option CYGNUM_HAL_CORTEXM_LM3S8XX_XTAL_FREQ {
+                display       "Crystal frequency in Hz"
+                flavor        data
+                default_value 8000000
+                legal_values  { 1000000 to 8192000 }
+                description   "
+                    Select the external crystal frequency from 1 to
+                    8.192 MHz.  Selecting the internal PLL adds additional
+                    constraints to the external crystal frequency setting.
+                    Check-out CYGHWR_HAL_CORTEXM_LM3S8XX_PLL"
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_INT {
+            display       "Internal clock source"
+            active_if     ! CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT
+            flavor        bool
+            default_value 0
+
+            cdl_option CYGNUM_HAL_CORTEXM_LM3S8XX_CLOCK_INT_FREQ {
+                display       "Internal clock source frequency in Hz"
+                flavor        data
+                default_value 12000000
+                legal_values  { 12000000 3000000 }
+                description   "
+                    Select the internal clock source. The frequency of the
+                    internal clock source can either be 12MHz or 3MHz."
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_LM3S8XX_PLL {
+            display       "Enable PLL"
+            flavor         bool
+            default_value  1
+            active_if      CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT
+
+            cdl_option CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT {
+                display       "PLL input clock frequency"
+                flavor        data
+                calculated    { CYGNUM_HAL_CORTEXM_LM3S8XX_XTAL_FREQ }
+                legal_values  { 3579545 3686400 4000000 4096000 4915200 5000000 \
+                                5120000 6000000 6144000 7372800 8000000 8192000 }
+                description   "
+                    PLL output frequency is fixed to 200 MHz.  Using the
+                    PLL puts more constraints to the external reference
+                    clock. The PLL input clock frequency is not defined
+                    if internal chip reference clock is used."
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK {
+            display       "System Clock frequency"
+            flavor        data
+            calculated    { CYGHWR_HAL_CORTEXM_LM3S8XX_PLL ? ( 200000000 / CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV ) : CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT ? ( CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL_FREQ / CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV ) : ( CYGNUM_HAL_CORTEXM_LM3S8XX_CLOCK_INT_FREQ / CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV ) }
+            legal_values  { 1000000 to 50000000 }
+            description   "
+                The chip system clock frequency is 200 MHz divided
+                by the system clock divider when the PLL is in used,
+                otherwise the frequency value is the chip source clock
+                frequency divided by the system clock divider."
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV {
+            display       "System Clock divider"
+            flavor        data
+            default_value 4
+            legal_values  { 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 }
+            description   "
+                Select the system clock divider."
+        }
+    }
+
+    # UART0 is available for diagnostic/debug use.
+    implements   CYGINT_HAL_CORTEXM_LM3S_UART0
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor        data
+        calculated    1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display       "Debug serial port"
+        active_if      CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        calculated    0
+        description   "
+            This option selects which port will be used to connect to
+            a host running GDB."
+     }
+
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display       "Diagnostic serial port"
+         active_if     CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         calculated    0
+         description   "
+             This option selects which port will be used for diagnostic
+             output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.  Note: this should match the value chosen
+            for the GDB port if the diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the GDB
+            connection.  Note: this should match the value chosen for
+            the console port if the console and GDB port are the same."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display       "Global build options"
+        flavor        none
+        parent        CYGPKG_NONE
+        description   "
+            Global build options including control over compiler flags,
+            linker flags and choice of toolchain."
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display       "Global command prefix"
+            flavor        data
+            no_define
+            default_value { "arm-eabi" }
+            description   "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display       "Global compiler flags"
+            flavor        data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which
+                are used to compile all packages by default. Individual
+                packages may define options which override these global
+                flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display       "Global linker flags"
+            flavor        data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global
+                flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a
+            ROM monitor, i.e. applications will be loaded into RAM on
+            the board, and this ROM monitor may process exceptions or
+            interrupts generated from the application. This enables
+            features such as utilizing a separate interrupt stack when
+            exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" "GDB_stubs" }
+         default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+         parent          CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM
+             monitor.  This support changes various eCos semantics such
+             as the encoding of diagnostic output, or the overriding of
+             hardware interrupt vectors.
+             Firstly there is \"Generic\" support which prevents the
+             HAL from overriding the hardware vectors that it does not
+             use, to instead allow an installed ROM monitor to handle
+             them. This is the most basic support which is likely to be
+             common to most implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included
+             in the ROM monitor or boot ROM."
+    }
+
+    cdl_component CYGBLD_HAL_CORTEXM_LM3S8XX_GDB_STUBS {
+        display       "Create StubROM SREC and binary files"
+        active_if     CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated    1
+        requires      { CYG_HAL_STARTUP == "ROM" }
+        description   "
+            This component causes the ELF image generated by the build
+            process to be converted to S-Record and binary files."
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+    }
+
+    cdl_option CYGPKG_HAL_CORTEXM_LM3S8XX_TESTS {
+        display       "Stellaris Cortex-M3 800 Series tests"
+        active_if     CYGPKG_KERNEL
+        flavor        data
+        no_define
+        calculated    { "tests/timers" }
+        description   "
+            This option specifies the set of tests for the Stellaris
+            Cortex-M3 800 Series HAL."
+    }
+}
+
+# EOF hal_cortex_lm3s8xx.cdl
diff --git a/packages/hal/cortexm/lm3s/lm3s8xx/current/include/pkgconf/mlt_cortexm_lm3s8xx_rom.h b/packages/hal/cortexm/lm3s/lm3s8xx/current/include/pkgconf/mlt_cortexm_lm3s8xx_rom.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/include/pkgconf/mlt_cortexm_lm3s8xx_rom.h
@@ -0,0 +1,19 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00002000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (0x00010000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ram_SIZE (0x00000000)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/lm3s/lm3s8xx/current/include/pkgconf/mlt_cortexm_lm3s8xx_rom.ldi b/packages/hal/cortexm/lm3s/lm3s8xx/current/include/pkgconf/mlt_cortexm_lm3s8xx_rom.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/include/pkgconf/mlt_cortexm_lm3s8xx_rom.ldi
@@ -0,0 +1,34 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00002000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = 0x00010000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000400, FOLLOWING (.got))
+    SECTION_data (sram, ALIGN (0x8), FOLLOWING (.sram))
+    SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + 1024*8;
+
diff --git a/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_arch.h b/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_arch.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_arch.h
@@ -0,0 +1,60 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Date:        2011-01-18
+// Purpose:     Stellaris Cortex-M3 800 Series specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_lm3s8xx.h>
+
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_ARCH_H
+// EOF plf_arch.h
diff --git a/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_intr.h b/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_intr.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_intr.h
@@ -0,0 +1,61 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Date:        2011-01-18
+// Purpose:     Stellaris Cortex-M3 800 Series specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_lm3s8xx.h>
+
+#define CYGNUM_HAL_INTERRUPT_NVIC_MAX       (CYGNUM_HAL_INTERRUPT_FMS)
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_INTR_H
+// EOF plf_intr.h
diff --git a/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_io.h b/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_io.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_io.h
@@ -0,0 +1,153 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Stellaris Cortex-M3 800 Series specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Date:        2011-01-18
+// Purpose:
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+#include <pkgconf/hal_cortexm_lm3s8xx.h>
+
+// Number of IOs on port A / B and C
+#define CYGHWR_HAL_LM3S_GPIOA_IOs                 6
+#define CYGHWR_HAL_LM3S_GPIOB_IOs                 8
+#define CYGHWR_HAL_LM3S_GPIOC_IOs                 8
+
+// Number of IOs on port D and E varies
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S800) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S801)
+#define CYGHWR_HAL_LM3S_GPIOD_IOs                 8
+#define CYGHWR_HAL_LM3S_GPIOE_IOs                 6
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S808) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S828)
+#define CYGHWR_HAL_LM3S_GPIOD_IOs                 4
+#define CYGHWR_HAL_LM3S_GPIOE_IOs                 2
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S811)
+#define CYGHWR_HAL_LM3S_GPIOD_IOs                 8
+#define CYGHWR_HAL_LM3S_GPIOE_IOs                 2
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S812) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S815)
+#define CYGHWR_HAL_LM3S_GPIOD_IOs                 8
+#define CYGHWR_HAL_LM3S_GPIOE_IOs                 4
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S817)|| \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S818)
+#define CYGHWR_HAL_LM3S_GPIOD_IOs                 6
+#define CYGHWR_HAL_LM3S_GPIOE_IOs                 2
+#endif
+
+// UART1
+#define CYGHWR_HAL_LM3S_UART1_TX                  CYGHWR_HAL_LM3S_GPIO( D, 2, PERIPH, NONE, NONE, DISABLE )
+#define CYGHWR_HAL_LM3S_UART1_RX                  CYGHWR_HAL_LM3S_GPIO( D, 3, PERIPH, NONE, NONE, DISABLE )
+#define CYGHWR_HAL_LM3S_P_UART1_GPIO              CYGHWR_HAL_LM3S_P_GPIOD
+
+// Number of ADC channel
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S812) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S815)
+#define CYGHWR_HAL_LM3S_ADC0_CHAN                 2
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S808) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S811)
+#define CYGHWR_HAL_LM3S_ADC0_CHAN                 4
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S817) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S818)
+#define CYGHWR_HAL_LM3S_ADC0_CHAN                 6
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S828) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S808)
+#define CYGHWR_HAL_LM3S_ADC0_CHAN                 8
+#endif
+
+// Number of PWM channel
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S812)
+#define CYGHWR_HAL_LM3S_MAX_PWM_CHAN              2
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S801) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S811) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S815) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S817) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S818)
+#define CYGHWR_HAL_LM3S_PWM_CHAN                  6
+#endif
+
+// Number of I2C channels
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S800) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S801) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S808) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S811) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S815) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S828)
+#define CYGHWR_HAL_LM3S_I2C_CHAN                  1
+// I2C
+#define CYGHWR_HAL_LM3S_I2C_SCL                   CYGHWR_HAL_LM3S_GPIO( B, 3, PERIPH, 2_MA, OP_PULLUP, DISABLE )
+#define CYGHWR_HAL_LM3S_I2C_SDA                   CYGHWR_HAL_LM3S_GPIO( B, 2, PERIPH, 2_MA, OP_PULLUP, DISABLE )
+#endif
+
+// Number of analog Comparator
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S800) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S801) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S815)
+#define CYGHWR_HAL_LM3S_AC_CHAN                   3
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S808) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S811) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S812) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S817) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S818)
+#define CYGHWR_HAL_LM3S_AC_CHAN                   1
+#endif
+
+// Number of Quadrature Encoder Channel
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S801) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S818)
+#define CYGHWR_HAL_LM3S_QEI_CHAN                  1
+#endif
+
+// SSI channel
+#define CYGHWR_HAL_LM3S_SSI_CHAN                  1
+
+// Global timer channel
+#define CYGHWR_HAL_LM3S_GPTIM_CHAN                3
+
+//-----------------------------------------------------------------------------
+#endif //CYGONCE_HAL_PLF_IO_H
+// EOF plf_io.h
diff --git a/packages/hal/cortexm/lm3s/lm3s8xx/current/misc/default_ROM.ecm b/packages/hal/cortexm/lm3s/lm3s8xx/current/misc/default_ROM.ecm
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/misc/default_ROM.ecm
@@ -0,0 +1,22 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    template minimal ;
+    package CYGPKG_KERNEL current ;
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 1536
+};
+
+cdl_option CYGNUM_KERNEL_THREADS_IDLE_STACK_SIZE {
+    user_value 1536
+};
\ No newline at end of file
diff --git a/packages/hal/cortexm/lm3s/lm3s8xx/current/src/lm3s8xx_misc.c b/packages/hal/cortexm/lm3s/lm3s8xx/current/src/lm3s8xx_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/src/lm3s8xx_misc.c
@@ -0,0 +1,246 @@
+//==========================================================================
+//
+//      lm3s8xx_misc.c
+//
+//      Stellaris Cortex-M3 800 Series HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Date:         2010-11-21
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+#include <cyg/hal/var_io.h>
+
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_PLL)
+#if CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 3579545
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL CYGHWR_HAL_LM3S_SC_RCC_XTAL(4)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 3686400
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(5)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 4000000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(6)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 4096000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(7)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 4915200
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(8)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 5000000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(9)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 5120000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(10)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 6000000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(11)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 6144000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(12)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 7372800
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(13)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 8000000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(14)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 8192000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(15)
+#endif
+#endif
+
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_INT)
+#if CYGNUM_HAL_CORTEXM_LM3S8XX_CLOCK_INT_FREQ == 12000000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_OSCSRC_FIELD CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_IOSC
+#else
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_OSCSRC_FIELD CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_IOSC_DIV4
+#endif
+#else
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_OSCSRC_FIELD CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_MOSC
+#endif
+
+#if CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV != 1
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_SC_RCC_SYSDIV_VAL \
+        CYGHWR_HAL_LM3S_SC_RCC_SYSDIV( (CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV-1) );
+#endif
+
+//==========================================================================
+
+void hal_lm3s8xx_periph_set( cyg_uint32 periph, cyg_uint32 on_off );
+
+__externC cyg_uint32 hal_cortexm_systick_clock;
+__externC cyg_uint32 hal_lm3s_sysclk;
+
+//==========================================================================
+// System init
+//
+// This code runs before the DATA is copied from ROM and the BSS cleared,
+// hence it cannot make use of static variables or data tables.
+
+__externC void
+hal_system_init( void )
+{
+}
+
+
+//==========================================================================
+// Setup up system clocks
+//
+void
+hal_start_clocks( void )
+{
+    CYG_ADDRESS     sc = CYGHWR_HAL_LM3S_SC;
+    cyg_uint32      rcc;
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_PLL)
+    cyg_uint32      plllmis = CYGHWR_HAL_LM3S_SC_MISC_PLLLMIS;
+    cyg_uint32      plllris = CYGHWR_HAL_LM3S_SC_RIS_PLLLRIS;
+    volatile cyg_uint16 wait;
+#endif
+
+    // At power up, the LM3S8xx is setup to use external oscillator.
+    // The PLL is powered down and bypass. Same goes for the system
+    // clock divider.
+
+    // For JTAG cold restart, first we make sure the PLL and system
+    // clock divider are bypassed, enable all clock source and shutdown
+    // the PLL.
+
+    HAL_READ_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc );
+
+    rcc &= ~( CYGHWR_HAL_LM3S_SC_RCC_USESYSDIV |
+              CYGHWR_HAL_LM3S_SC_RCC_MOSCDIS |
+              CYGHWR_HAL_LM3S_SC_RCC_IOSCDIS );
+
+    rcc |= CYGHWR_HAL_LM3S_SC_RCC_BYPASS;
+
+    HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc );
+
+    rcc |= ( CYGHWR_HAL_LM3S_SC_RCC_PWRDN | CYGHWR_HAL_LM3S_SC_RCC_OEN );
+
+    HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc );
+
+    // PLL is setup if in use
+    //
+    // The XTAL frequency is configured. The PLL is powered and
+    // its output is enable
+
+    // Setup Clock Source
+    rcc |= CYGHWR_HAL_CORTEXM_LM3S8XX_OSCSRC_FIELD;
+
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_PLL)
+
+    // Clear PLL lock bit
+    HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_MISC, plllmis );
+
+    rcc &= ~( CYGHWR_HAL_LM3S_SC_RCC_XTAL_MASK |
+              ( CYGHWR_HAL_LM3S_SC_RCC_PWRDN ) |
+              ( CYGHWR_HAL_LM3S_SC_RCC_OEN ) );
+
+    rcc |= CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL;
+
+#endif
+
+    HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc );
+
+    //
+    // Setup System Clock divider
+    //
+
+#if CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV != 1
+
+    // Use system clock divider
+    rcc |= CYGHWR_HAL_LM3S_SC_RCC_USESYSDIV;
+
+    // Clear system clock divider bits
+    rcc &= ~CYGHWR_HAL_LM3S_SC_RCC_SYSDIV_MASK;
+
+    // Configure divider
+    rcc |= CYGHWR_HAL_CORTEXM_LM3S8XX_SC_RCC_SYSDIV_VAL;
+
+    HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc );
+
+#endif
+
+    // Wait for PLL lock before feeding the clock to the
+    // device
+
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_PLL)
+
+    // Wait for PLL lock, potentially a dead lock
+    plllris = 0;
+    while ( 0 == ( plllris & CYGHWR_HAL_LM3S_SC_RIS_PLLLRIS ) ) {
+        // Wait
+        for ( wait = 0; wait < ( ( 2 ^ 16 ) - 1 ); wait++ )
+            HAL_READ_UINT32( sc + CYGHWR_HAL_LM3S_SC_RIS, plllris );
+    }
+
+    // Clear bypass bit
+    rcc &= ~CYGHWR_HAL_LM3S_SC_RCC_BYPASS;
+
+    HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc );
+
+#endif
+
+    //
+    // Disable clock source not in use
+    //
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT)
+
+    rcc |= CYGHWR_HAL_LM3S_SC_RCC_IOSCDIS;
+
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_INT)
+
+    rcc |= CYGHWR_HAL_LM3S_SC_RCC_MOSCDIS;
+
+#endif
+
+    HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc );
+
+    hal_cortexm_systick_clock = CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK;
+    hal_lm3s_sysclk = CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK;
+}
+
+//==========================================================================
+// EOF lm3s8xx_misc.c
diff --git a/packages/hal/cortexm/lm3s/lm3s8xx/current/tests/timers.c b/packages/hal/cortexm/lm3s/lm3s8xx/current/tests/timers.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/tests/timers.c
@@ -0,0 +1,359 @@
+//=============================================================================
+//
+//      timers.c
+//
+//      Test for Stellaris Cortex-M3 Device Timers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg for STM32
+//               ccoutand updated for Stellaris Cortex-M3 Devices
+// Date:         2011-01-18
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+
+#if defined(CYGPKG_KERNEL)
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/testcase.h>
+
+//=============================================================================
+// Check all required packages and components are present
+
+#if !defined(CYGPKG_KERNEL) || !defined(CYGPKG_KERNEL_API)
+# define NA_MSG  "Configuration insufficient"
+#endif
+
+//=============================================================================
+// If everything is present, compile the full test.
+
+#ifndef NA_MSG
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_if.h>
+
+#include <cyg/kernel/kapi.h>
+#include <cyg/infra/diag.h>
+#include <string.h>
+
+//=============================================================================
+
+#define LOOPS      24                  // 2 minutes
+#define SINGLE_TIMER 0                 // Full / Single timer test
+
+static int      test_stack[( CYGNUM_HAL_STACK_SIZE_MINIMUM / sizeof( int ) )];
+static cyg_thread test_thread;
+static cyg_handle_t main_thread;
+
+//=============================================================================
+
+struct timer {
+    cyg_uint32      timer;
+    cyg_uint32      base;
+    cyg_uint32      periph;
+    cyg_uint32      vector;
+    cyg_uint32      priority;
+    cyg_uint32      interval;
+
+    cyg_uint32      ticks;
+
+    cyg_uint32      preempt[10];
+
+    cyg_uint32      preempt_dsr[10];
+    cyg_uint32      dsr_count[10];
+
+    cyg_interrupt   interrupt_object;
+    cyg_handle_t    interrupt_handle;
+};
+
+struct timer    timers[] = {
+#if SINGLE_TIMER
+    {1, CYGHWR_HAL_LM3S_GPTIM0, CYGHWR_HAL_LM3S_P_TIMER0,
+     CYGNUM_HAL_INTERRUPT_GTIM0_A, 0x20, 1000},
+#else
+    {1, CYGHWR_HAL_LM3S_GPTIM0, CYGHWR_HAL_LM3S_P_TIMER0,
+     CYGNUM_HAL_INTERRUPT_GTIM0_A, 0x20, 127},
+    {2, CYGHWR_HAL_LM3S_GPTIM1, CYGHWR_HAL_LM3S_P_TIMER1,
+     CYGNUM_HAL_INTERRUPT_GTIM1_A, 0x60, 355},
+    {3, CYGHWR_HAL_LM3S_GPTIM2, CYGHWR_HAL_LM3S_P_TIMER2,
+     CYGNUM_HAL_INTERRUPT_GTIM2_A, 0x80, 731},
+#endif
+    {0, 0, 0, 0}
+};
+
+
+//=============================================================================
+
+volatile cyg_uint32 ticks = 0;
+volatile cyg_uint32 nesting = 0;
+volatile cyg_uint32 max_nesting = 0;
+volatile cyg_uint32 max_nesting_seen = 0;
+volatile cyg_uint32 current = 0;
+volatile cyg_uint32 in_dsr = 0;
+
+
+//=============================================================================
+
+void
+init_timer( cyg_uint32 base, cyg_uint32 periph, cyg_uint32 interval )
+{
+    cyg_uint32      period = CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK;
+
+    CYGHWR_HAL_LM3S_PERIPH_SET( periph, 1 );
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_CTL, 0x0000 );
+
+    period = period / 1000000;
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_TAPR, period );
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_CFG,
+                      CYGHWR_HAL_LM3S_GPTIM_CFG_16BIT );
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_TAMR,
+                      CYGHWR_HAL_LM3S_GPTIM_TAMR_PERIODIC );
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_TAILR, interval );
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_ICR,
+                      CYGHWR_HAL_LM3S_GPTIM_ICR_TATOCINT );
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_IMR,
+                      CYGHWR_HAL_LM3S_GPTIM_IMR_TATOIM );
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_CTL,
+                      CYGHWR_HAL_LM3S_GPTIM_CTL_TAEN );
+}
+
+
+//=============================================================================
+
+cyg_uint32
+timer_isr( cyg_uint32 vector, CYG_ADDRWORD data )
+{
+    struct timer   *t = ( struct timer * )data;
+    cyg_uint32      preempt = current;
+    CYG_ADDRWORD    base = t->base;
+    cyg_uint32      cnt;
+
+    current = t->timer;
+    t->ticks++;
+    ticks++;
+    t->preempt[preempt]++;
+    nesting++;
+
+    // Count only first ISR to preempt a DSR
+    if( preempt == 0 )
+        t->preempt_dsr[in_dsr]++;
+
+    HAL_WRITE_UINT32( t->base + CYGHWR_HAL_LM3S_GPTIM_ICR,
+                      CYGHWR_HAL_LM3S_GPTIM_ICR_TATOCINT );
+
+    if( nesting > max_nesting )
+        max_nesting = nesting;
+
+    // Loiter here for a proportion of the timer interval to give
+    // other timers the chance to preempt us.
+    do {
+        HAL_READ_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_TAR, cnt );
+    } while( cnt < t->interval / 10 );
+
+    nesting--;
+    current = preempt;
+
+    if( ( t->ticks % 10 ) == 0 )
+        return 3;
+    else
+        return 1;
+}
+
+
+//=============================================================================
+
+void
+timer_dsr( cyg_uint32 vector, cyg_uint32 count, CYG_ADDRWORD data )
+{
+    struct timer   *t = ( struct timer * )data;
+    int             i;
+
+    in_dsr = t->timer;
+
+    if( count >= 8 )
+        count = 8;
+
+    t->dsr_count[count]++;
+
+    // Loiter for a while
+    for( i = 0; i < t->interval / 10; i++ )
+        continue;
+
+    in_dsr = 0;
+}
+
+
+//=============================================================================
+
+void
+timers_test( cyg_addrword_t data )
+{
+    int             loops = LOOPS;
+    int             i;
+    CYG_INTERRUPT_STATE istate;
+
+    CYG_TEST_INIT(  );
+
+    CYG_TEST_INFO( "Start Timers test" );
+
+    for( i = 0; timers[i].timer != 0; i++ ) {
+        struct timer   *t = &timers[i];
+
+        init_timer( t->base, t->periph, t->interval );
+
+        cyg_interrupt_create( t->vector,
+                              t->priority,
+                              ( cyg_addrword_t )t,
+                              timer_isr,
+                              timer_dsr,
+                              &t->interrupt_handle, &t->interrupt_object );
+
+        cyg_interrupt_attach( t->interrupt_handle );
+        cyg_interrupt_unmask( t->vector );
+
+    }
+
+    while( loops-- ) {
+        int             j;
+
+        // 5 second delay
+        cyg_thread_delay( 5 * 100 );
+
+        // Disable interrupts while we print details, otherwise it
+        // comes out very slowly.
+        HAL_DISABLE_INTERRUPTS( istate );
+
+        if( max_nesting > max_nesting_seen )
+            max_nesting_seen = max_nesting;
+
+        diag_printf( "\nISRs max_nesting %d max_nesting_seen %d\n",
+                     max_nesting, max_nesting_seen );
+        max_nesting = 0;
+
+        diag_printf( " T      Ticks " );
+
+        for( j = 0; j < 9; j++ )
+            diag_printf( "%9d ", j );
+        diag_printf( "\n" );
+
+        for( i = 0; timers[i].timer != 0; i++ ) {
+            struct timer   *t = &timers[i];
+
+            diag_printf( "%2d: %9d ", t->timer, t->ticks );
+
+            for( j = 0; j < 9; j++ )
+                diag_printf( "%9d ", t->preempt[j] );
+            diag_printf( "\n" );
+
+        }
+
+        diag_printf( "DSRs\n" );
+
+        diag_printf( " T:           " );
+
+        for( j = 0; j < 9; j++ )
+            diag_printf( "%9d ", j );
+        diag_printf( "\n" );
+
+        for( i = 0; timers[i].timer != 0; i++ ) {
+            struct timer   *t = &timers[i];
+
+            diag_printf( "%2d:  preempt: ", t->timer );
+
+            for( j = 0; j < 9; j++ )
+                diag_printf( "%9d ", t->preempt_dsr[j] );
+            diag_printf( "\n" );
+
+            diag_printf( "       count: " );
+
+            for( j = 0; j < 9; j++ )
+                diag_printf( "%9d ", t->dsr_count[j] );
+            diag_printf( "\n" );
+        }
+
+        HAL_RESTORE_INTERRUPTS( istate );
+    }
+
+    CYG_TEST_PASS_FINISH( "Timers test" );
+}
+
+
+//=============================================================================
+
+void
+cyg_user_start( void )
+{
+    cyg_thread_create( 0,              // Priority
+                       timers_test,    //
+                       0,              //
+                       "timers test",  // Name
+                       test_stack,     // Stack
+                       CYGNUM_HAL_STACK_SIZE_MINIMUM,   // Stack size
+                       &main_thread,   // Handle
+                       &test_thread    // Thread data structure
+         );
+    cyg_thread_resume( main_thread );
+}
+
+//=============================================================================
+
+#else // NA_MSG
+
+void
+cyg_user_start( void )
+{
+    CYG_TEST_NA( NA_MSG );
+}
+
+#endif // NA_MSG
+
+//=============================================================================
+// EOF timers.c
diff --git a/packages/hal/cortexm/lm3s/var/current/ChangeLog b/packages/hal/cortexm/lm3s/var/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/var/current/ChangeLog
@@ -0,0 +1,38 @@
+2011-01-18  Christophe Coutand  <ccoutand@stmi.com>
+
+	* cdl/hal_cortexm_lm3s.cdl
+	* include/hal_cache.h:
+	* include/hal_diag.h:
+	* include/plf_stub.h:
+	* include/var_arch.h:
+	* include/variant.inc:
+	* include/var_intr.h:
+	* include/var_io.h:
+	* src/hal_diag.c:
+	* src/lm3s_misc.c:
+	New package -- Stellaris Cortex M3 variant HAL.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
+
diff --git a/packages/hal/cortexm/lm3s/var/current/cdl/hal_cortexm_lm3s.cdl b/packages/hal/cortexm/lm3s/var/current/cdl/hal_cortexm_lm3s.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/var/current/cdl/hal_cortexm_lm3s.cdl
@@ -0,0 +1,123 @@
+##==========================================================================
+##
+##    hal_cortexm_lm3s.cdl
+##
+##    Stellaris Cortex-M3 variant HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ccoutand
+## Date:         2011-01-18
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_LM3S {
+    display       "Stellaris Cortex-M3 from Luminary Micro variant HAL"
+    parent        CYGPKG_HAL_CORTEXM
+    define_header hal_cortexm_lm3s.h
+    include_dir   cyg/hal
+    hardware
+    description   "
+        This package provides generic support for the Cortex-M3 based
+        Stellaris microcontroller family.  It is also necessary to select
+        a variant and platform HAL package."
+
+    compile       hal_diag.c lm3s_misc.c
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+    requires      { CYGHWR_HAL_CORTEXM == "M3" }
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+
+    # Let the architectural HAL see this variant's files
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_CORTEXM_VAR_IO_H"
+        puts $::cdl_system_header "#define CYGBLD_HAL_CORTEXM_VAR_ARCH_H"
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LM3S {
+        display       "Stellaris Cortex-M3 variant in use"
+        flavor        data
+        default_value { "LM3S8XX" }
+        legal_values  { "LM3S8XX" }
+        description   "
+            Currently only supported the Stellaris Cortex-M3 800 Series."
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
+        display       "CPU priority levels"
+        flavor        data
+        calculated    3
+        description   "
+            This option defines the number of bits used to encode the
+            exception priority levels that this variant of the Cortex-M3
+            CPU implements."
+    }
+
+    cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
+        display       "Clock interrupt ISR priority"
+        flavor        data
+        calculated    0xC0
+        description   "
+            Set clock ISR priority to lowest priority."
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_LM3S_UART0 {
+        display       "Platform has UART0 serial port"
+        description   "
+            The platform has a socket on UART0."
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_LM3S_UART1 {
+        display       "Platform has UART1 serial port"
+        description   "
+            The platform has a socket on UART1."
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_LM3S_UART2 {
+        display       "Platform has UART2 serial port"
+        description   "
+            The platform has a socket on UART2."
+    }
+
+}
+
+# EOF hal_cortex_lm3s.cdl
diff --git a/packages/hal/cortexm/lm3s/var/current/include/hal_cache.h b/packages/hal/cortexm/lm3s/var/current/include/hal_cache.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/var/current/include/hal_cache.h
@@ -0,0 +1,66 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+//      hal_cache.h
+//
+//      HAL cache control API
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors: 
+// Date:         2011-01-18
+// Purpose:      Cache control API
+// Description:  The Stellaris LM3S Cortex-M3 microcontroller does not require
+//               cache control. File is kept empty.
+//
+// Usage:
+//               #include <cyg/hal/hal_cache.h>
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
diff --git a/packages/hal/cortexm/lm3s/var/current/include/hal_diag.h b/packages/hal/cortexm/lm3s/var/current/include/hal_diag.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/var/current/include/hal_diag.h
@@ -0,0 +1,88 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+//=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL diagnostics
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Date:        2011-01-18
+// Purpose:     HAL diagnostics
+// Description: 
+// Usage:       #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_if.h>
+
+//-----------------------------------------------------------------------------
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+# define HAL_DIAG_INIT()          hal_if_diag_init()
+# define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+# define HAL_DIAG_READ_CHAR(_c_)  hal_if_diag_read_char(&_c_)
+
+#else
+
+__externC void  hal_lm3s_diag_init(void);
+__externC void  hal_lm3s_diag_putc(char);
+__externC cyg_uint8 hal_lm3s_diag_getc(void);
+
+# ifndef HAL_DIAG_INIT
+#  define HAL_DIAG_INIT() hal_lm3s_diag_init()
+# endif
+
+# ifndef HAL_DIAG_WRITE_CHAR
+#  define HAL_DIAG_WRITE_CHAR(__c) hal_lm3s_diag_putc(__c)
+# endif
+
+# ifndef HAL_DIAG_READ_CHAR
+#  define HAL_DIAG_READ_CHAR(__c) (__c) = hal_lm3s_diag_getc()
+# endif
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_DIAG_H
+// EOF of hal_diag.h
diff --git a/packages/hal/cortexm/lm3s/var/current/include/plf_stub.h b/packages/hal/cortexm/lm3s/var/current/include/plf_stub.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/var/current/include/plf_stub.h
@@ -0,0 +1,88 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Date:        2011-01-18
+// Purpose:     Platform HAL stub support for Stellaris Cortex-M3
+//              variant boards.
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+
+#include <cyg/hal/cortexm_stub.h>       // architecture stub support
+
+#include <cyg/hal/hal_io.h>
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+__externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+
+#define HAL_STUB_PLATFORM_INIT()              CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
diff --git a/packages/hal/cortexm/lm3s/var/current/include/var_arch.h b/packages/hal/cortexm/lm3s/var/current/include/var_arch.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/var/current/include/var_arch.h
@@ -0,0 +1,61 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+//      var_arch.h
+//
+//      Stellaris Cortex-M3 variant architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Date:         2011-01-18
+// Purpose:      Stellaris Cortex-M3 variant architecture overrides
+// Description: 
+// Usage:        #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+
+#include <cyg/hal/plf_arch.h>
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_ARCH_H
+// EOF of var_arch.h
diff --git a/packages/hal/cortexm/lm3s/var/current/include/var_intr.h b/packages/hal/cortexm/lm3s/var/current/include/var_intr.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/var/current/include/var_intr.h
@@ -0,0 +1,119 @@
+#ifndef CYGONCE_HAL_VAR_INTR_H
+#define CYGONCE_HAL_VAR_INTR_H
+//==========================================================================
+//
+//      var_intr.h
+//
+//      HAL Interrupt and clock assignments for Stellaris Cortex-M3 variants
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Date:         2011-01-18
+// Purpose:      Define Interrupt support
+// Description:  The interrupt specifics for Stellaris Cortex-M3
+//               are defined here.
+//              
+// Usage:        #include <cyg/hal/var_intr.h>
+//               However applications should include using <cyg/hal/hal_intr.h>
+//               instead to allow for platform overrides.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/plf_intr.h>
+
+//==========================================================================
+
+#define CYGNUM_HAL_INTERRUPT_GPIOA          (0+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIOB          (1+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIOC          (2+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIOD          (3+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIOE          (4+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART0          (5+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART1          (6+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SSI0           (7+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C            (8+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_PWM0           (10+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_PWM1           (11+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_PWM2           (12+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_QIE            (13+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ADC0_S0        (14+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ADC0_S1        (15+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ADC0_S2        (16+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ADC0_S3        (17+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_WDT            (18+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM0_A        (19+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM0_B        (20+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM1_A        (21+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM1_B        (22+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM2_A        (23+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM2_B        (24+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_AC0            (25+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_AC1            (26+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_AC2            (27+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SCTL           (28+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_FMS            (29+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIOF          (30+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIOG          (31+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIOH          (32+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM3_A        (35+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM3_B        (36+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN0           (39+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ETH0           (42+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_HIM            (43+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#ifndef CYGNUM_HAL_INTERRUPT_NVIC_MAX
+# define CYGNUM_HAL_INTERRUPT_NVIC_MAX      (CYGNUM_HAL_INTERRUPT_HIM)
+#endif
+
+#define CYGNUM_HAL_ISR_MIN                  0
+#ifndef CYGNUM_HAL_ISR_MAX
+# define CYGNUM_HAL_ISR_MAX                 (CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#endif
+#define CYGNUM_HAL_ISR_COUNT                (CYGNUM_HAL_ISR_MAX + 1)
+
+#define CYGNUM_HAL_VSR_MIN                  0
+#ifndef CYGNUM_HAL_VSR_MAX
+# define CYGNUM_HAL_VSR_MAX                 (CYGNUM_HAL_VECTOR_SYS_TICK+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#endif
+#define CYGNUM_HAL_VSR_COUNT                (CYGNUM_HAL_VSR_MAX+1)
+
+
+//----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_INTR_H
+// EOF var_intr.h
diff --git a/packages/hal/cortexm/lm3s/var/current/include/var_io.h b/packages/hal/cortexm/lm3s/var/current/include/var_io.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/var/current/include/var_io.h
@@ -0,0 +1,1371 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//=============================================================================
+//
+//      var_io.h
+//
+//      Variant specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Date:        2011-01-18
+// Purpose:     Stellaris Cortex-M3 variant specific registers
+// Description: 
+// Usage:       #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal_cortexm_lm3s.h>
+
+#include <cyg/hal/plf_io.h>
+
+//=============================================================================
+// Peripherals
+
+#define CYGHWR_HAL_LM3S_FLASH                    0x00000000
+#define CYGHWR_HAL_LM3S_SRAM                     0x20000000
+
+#define CYGHWR_HAL_LM3S_WDT0                     0x40000000
+#define CYGHWR_HAL_LM3S_GPIOA                    0x40004000
+#define CYGHWR_HAL_LM3S_GPIOB                    0x40005000
+#define CYGHWR_HAL_LM3S_GPIOC                    0x40006000
+#define CYGHWR_HAL_LM3S_GPIOD                    0x40007000
+#define CYGHWR_HAL_LM3S_SSI0                     0x40008000
+#define CYGHWR_HAL_LM3S_SSI1                     0x40009000
+#define CYGHWR_HAL_LM3S_UART0                    0x4000C000
+#define CYGHWR_HAL_LM3S_UART1                    0x4000D000
+#define CYGHWR_HAL_LM3S_UART2                    0x4000E000
+#define CYGHWR_HAL_LM3S_I2C_M0                   0x40020000
+#define CYGHWR_HAL_LM3S_I2C_S0                   0x40020800
+#define CYGHWR_HAL_LM3S_GPIOE                    0x40024000
+#define CYGHWR_HAL_LM3S_GPIOF                    0x40025000
+#define CYGHWR_HAL_LM3S_GPIOG                    0x40026000
+#define CYGHWR_HAL_LM3S_GPIOH                    0x40027000
+#define CYGHWR_HAL_LM3S_PWM                      0x40028000
+#define CYGHWR_HAL_LM3S_QEI0                     0x4002C000
+#define CYGHWR_HAL_LM3S_GPTIM0                   0x40030000
+#define CYGHWR_HAL_LM3S_GPTIM1                   0x40031000
+#define CYGHWR_HAL_LM3S_GPTIM2                   0x40032000
+#define CYGHWR_HAL_LM3S_GPTIM3                   0x40033000
+#define CYGHWR_HAL_LM3S_ADC0                     0x40038000
+#define CYGHWR_HAL_LM3S_AC                       0x4003C000
+#define CYGHWR_HAL_LM3S_CAN0                     0x40040000
+#define CYGHWR_HAL_LM3S_ETH0                     0x40048000
+#define CYGHWR_HAL_LM3S_FMC                      0x400FD000
+#define CYGHWR_HAL_LM3S_SC                       0x400FE000
+
+#define CYGHWR_HAL_LM3S_ITM                      0xE0000000
+#define CYGHWR_HAL_LM3S_DWT                      0xE0001000
+#define CYGHWR_HAL_LM3S_FPB                      0xE0002000
+#define CYGHWR_HAL_LM3S_CORTEXM3                 0xE000E000
+#define CYGHWR_HAL_LM3S_TPIU                     0xE0040000
+
+
+//=============================================================================
+// Device signature and ID registers
+
+#define CYGHWR_HAL_LM3S_MCU_ID                   (CYGHWR_HAL_LM3S_CORTEXM3 + 0xD00)
+#define CYGHWR_HAL_LM3S_MCU_ID_REV(__x)          ((__x)&0xF)
+#define CYGHWR_HAL_LM3S_MCU_PART_NO(__x)         (((__x)>>4)&0x0FFF)
+#define CYGHWR_HAL_LM3S_MCU_VAR_NO(__x)          (((__x)>>20)&0xF)
+
+
+//=============================================================================
+// System Control
+
+#define CYGHWR_HAL_LM3S_SC_DID0                  0x000
+#define CYGHWR_HAL_LM3S_SC_DID1                  0x004
+#define CYGHWR_HAL_LM3S_SC_DIC0                  0x008
+#define CYGHWR_HAL_LM3S_SC_DIC1                  0x010
+#define CYGHWR_HAL_LM3S_SC_DIC2                  0x014
+#define CYGHWR_HAL_LM3S_SC_DIC3                  0x018
+#define CYGHWR_HAL_LM3S_SC_DIC4                  0x01c
+#define CYGHWR_HAL_LM3S_SC_PBORCTL               0x030
+#define CYGHWR_HAL_LM3S_SC_LDORCTL               0x034
+#define CYGHWR_HAL_LM3S_SC_SRCR0                 0x040
+#define CYGHWR_HAL_LM3S_SC_SRCR1                 0x044
+#define CYGHWR_HAL_LM3S_SC_SRCR2                 0x048
+#define CYGHWR_HAL_LM3S_SC_RIS                   0x050
+#define CYGHWR_HAL_LM3S_SC_IMC                   0x054
+#define CYGHWR_HAL_LM3S_SC_MISC                  0x058
+#define CYGHWR_HAL_LM3S_SC_RESC                  0x05C
+#define CYGHWR_HAL_LM3S_SC_RCC                   0x060
+#define CYGHWR_HAL_LM3S_SC_PLLCFG                0x064
+#define CYGHWR_HAL_LM3S_SC_RCGC0                 0x100
+#define CYGHWR_HAL_LM3S_SC_RCGC1                 0x104
+#define CYGHWR_HAL_LM3S_SC_RCGC2                 0x108
+#define CYGHWR_HAL_LM3S_SC_SCGC0                 0x110
+#define CYGHWR_HAL_LM3S_SC_SCGC1                 0x114
+#define CYGHWR_HAL_LM3S_SC_SCGC2                 0x118
+#define CYGHWR_HAL_LM3S_SC_DCGC0                 0x120
+#define CYGHWR_HAL_LM3S_SC_DCGC1                 0x124
+#define CYGHWR_HAL_LM3S_SC_DCGC2                 0x128
+#define CYGHWR_HAL_LM3S_SC_FMPRE                 0x130
+#define CYGHWR_HAL_LM3S_SC_FMPPE                 0x134
+#define CYGHWR_HAL_LM3S_SC_USECRL                0x140
+#define CYGHWR_HAL_LM3S_SC_DSLPCLKCFG            0x144
+#define CYGHWR_HAL_LM3S_SC_CLKVCLR               0x150
+#define CYGHWR_HAL_LM3S_SC_LDOARST               0x160
+
+// PBORCTL bits
+#define CYGHWR_HAL_LM3S_SC_PBORCTL_BORWT         BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_PBORCTL_BORIOR        BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_PBORCTL_BORTIM(__x)   VALUE_(2,__x)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_SC_RIS_PLLFRIS           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_RIS_BORRIS            BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_RIS_LDORIS            BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_RIS_MOFRIS            BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_RIS_IOFRIS            BIT_(4)
+#define CYGHWR_HAL_LM3S_SC_RIS_CLFRIS            BIT_(5)
+#define CYGHWR_HAL_LM3S_SC_RIS_PLLLRIS           BIT_(6)
+
+// IMC bits
+#define CYGHWR_HAL_LM3S_SC_IMC_PLLFIM            BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_IMC_BORRIM            BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_IMC_LDOIM             BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_IMC_MOFIM             BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_IMC_IOFIM             BIT_(4)
+#define CYGHWR_HAL_LM3S_SC_IMC_CLIM              BIT_(5)
+#define CYGHWR_HAL_LM3S_SC_IMC_PLLLFIM           BIT_(6)
+
+// MISC bits
+#define CYGHWR_HAL_LM3S_SC_MISC_BORMIS           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_MISC_LDOMIS           BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_MISC_MOFMIS           BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_MISC_IOFMIS           BIT_(4)
+#define CYGHWR_HAL_LM3S_SC_MISC_CLMIS            BIT_(5)
+#define CYGHWR_HAL_LM3S_SC_MISC_PLLLMIS          BIT_(6)
+
+// RESC bits
+#define CYGHWR_HAL_LM3S_SC_RESC_EXT              BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_RESC_POR              BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_RESC_BOR              BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_RESC_WDT              BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_RESC_SW               BIT_(4)
+#define CYGHWR_HAL_LM3S_SC_RESC_LDO              BIT_(5)
+
+// RCC bits
+#define CYGHWR_HAL_LM3S_SC_RCC_MOSCDIS           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_RCC_IOSCDIS           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_RCC_MOSCVER           BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_RCC_IOSCVER           BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_MOSC       VALUE_(4,0)
+#define CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_IOSC       VALUE_(4,1)
+#define CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_IOSC_DIV4  VALUE_(4,2)
+#define CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_MASK       0x00000030
+#define CYGHWR_HAL_LM3S_SC_RCC_XTAL(__x)         VALUE_(6,__x)
+#define CYGHWR_HAL_LM3S_SC_RCC_XTAL_MASK         0x000003C0
+#define CYGHWR_HAL_LM3S_SC_RCC_PLLVER            BIT_(10)
+#define CYGHWR_HAL_LM3S_SC_RCC_BYPASS            BIT_(11)
+#define CYGHWR_HAL_LM3S_SC_RCC_OEN               BIT_(12)
+#define CYGHWR_HAL_LM3S_SC_RCC_PWRDN             BIT_(13)
+#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV2       VALUE_(14, 0x0)
+#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV4       VALUE_(14, 0x1)
+#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV8       VALUE_(14, 0x2)
+#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV16      VALUE_(14, 0x3)
+#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV32      VALUE_(14, 0x4)
+#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV64      VALUE_(14, 0x5)
+#define CYGHWR_HAL_LM3S_SC_RCC_USEPWMDIV         BIT_(20)
+#define CYGHWR_HAL_LM3S_SC_RCC_USESYSDIV         BIT_(22)
+#define CYGHWR_HAL_LM3S_SC_RCC_SYSDIV(__x)       VALUE_(23, __x)
+#define CYGHWR_HAL_LM3S_SC_RCC_SYSDIV_MASK       0x07800000
+#define CYGHWR_HAL_LM3S_SC_RCC_ACG               BIT_(27)
+
+// DSLPCLKCFG bits
+#define CYGHWR_HAL_LM3S_SC_DSLPCLKCFG_IOSC       BIT_(0)
+
+// CLKVCLR bits
+#define CYGHWR_HAL_LM3S_SC_CLKVCLR_VERCLR        BIT_(0)
+
+// LDOARST bits
+#define CYGHWR_HAL_LM3S_SC_LDOARST_BIT           BIT_(0)
+
+// RCGC0 bits
+#define CYGHWR_HAL_LM3S_SC_RCGC0_WDT0            BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_RCGC0_MAXADCSPD_125K  VALUE_(8, 0x0)
+#define CYGHWR_HAL_LM3S_SC_RCGC0_MAXADCSPD_250K  VALUE_(8, 0x1)
+#define CYGHWR_HAL_LM3S_SC_RCGC0_MAXADCSPD_500K  VALUE_(8, 0x2)
+#define CYGHWR_HAL_LM3S_SC_RCGC0_ADC0            BIT_(16)
+#define CYGHWR_HAL_LM3S_SC_RCGC0_PWM0            BIT_(20)
+
+// SCGC0 bits
+#define CYGHWR_HAL_LM3S_SC_SCGC0_WDT0            BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_SCGC0_MAXADCSPD_125K  VALUE_(8, 0x0)
+#define CYGHWR_HAL_LM3S_SC_SCGC0_MAXADCSPD_250K  VALUE_(8, 0x1)
+#define CYGHWR_HAL_LM3S_SC_SCGC0_MAXADCSPD_500K  VALUE_(8, 0x2)
+#define CYGHWR_HAL_LM3S_SC_SCGC0_ADC0            BIT_(16)
+#define CYGHWR_HAL_LM3S_SC_SCGC0_PWM0            BIT_(20)
+
+// DCGC0 bits
+#define CYGHWR_HAL_LM3S_SC_DCGC0_WDT0            BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_DCGC0_ADC0            BIT_(16)
+#define CYGHWR_HAL_LM3S_SC_DCGC0_PWM0            BIT_(20)
+
+// RCGC1 bits
+#define CYGHWR_HAL_LM3S_SC_RCGC1_UART0           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_RCGC1_UART1           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_RCGC1_SSI0            BIT_(4)
+#define CYGHWR_HAL_LM3S_SC_RCGC1_I2C0            BIT_(12)
+#define CYGHWR_HAL_LM3S_SC_RCGC1_TIMER0          BIT_(16)
+#define CYGHWR_HAL_LM3S_SC_RCGC1_TIMER1          BIT_(17)
+#define CYGHWR_HAL_LM3S_SC_RCGC1_TIMER2          BIT_(18)
+#define CYGHWR_HAL_LM3S_SC_RCGC1_COMP0           BIT_(24)
+
+// SCSG1 bits
+#define CYGHWR_HAL_LM3S_SC_SCGC1_UART0           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_SCGC1_UART1           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_SCGC1_SSI0            BIT_(4)
+#define CYGHWR_HAL_LM3S_SC_SCGC1_I2C0            BIT_(12)
+#define CYGHWR_HAL_LM3S_SC_SCGC1_TIMER0          BIT_(16)
+#define CYGHWR_HAL_LM3S_SC_SCGC1_TIMER1          BIT_(17)
+#define CYGHWR_HAL_LM3S_SC_SCGC1_TIMER2          BIT_(18)
+#define CYGHWR_HAL_LM3S_SC_SCGC1_COMP0           BIT_(24)
+
+// DCSG1 bits
+#define CYGHWR_HAL_LM3S_SC_DCGC1_UART0           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_DCGC1_UART1           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_DCGC1_SSI0            BIT_(4)
+#define CYGHWR_HAL_LM3S_SC_DCGC1_I2C0            BIT_(12)
+#define CYGHWR_HAL_LM3S_SC_DCGC1_TIMER0          BIT_(16)
+#define CYGHWR_HAL_LM3S_SC_DCGC1_TIMER1          BIT_(17)
+#define CYGHWR_HAL_LM3S_SC_DCGC1_TIMER2          BIT_(18)
+#define CYGHWR_HAL_LM3S_SC_DCGC1_COMP0           BIT_(24)
+
+// RCGC2 bits
+#define CYGHWR_HAL_LM3S_SC_RCGC2_GPIOA           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_RCGC2_GPIOB           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_RCGC2_GPIOC           BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_RCGC2_GPIOD           BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_RCGC2_GPIOE           BIT_(4)
+
+// SCSG2 bits
+#define CYGHWR_HAL_LM3S_SC_SCGC2_GPIOA           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_SCGC2_GPIOB           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_SCGC2_GPIOC           BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_SCGC2_GPIOD           BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_SCGC2_GPIOE           BIT_(4)
+
+// DCSG2 bits
+#define CYGHWR_HAL_LM3S_SC_DCGC2_GPIOA           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_DCGC2_GPIOB           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_DCGC2_GPIOC           BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_DCGC2_GPIOD           BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_DCGC2_GPIOE           BIT_(4)
+
+// Define peripheral
+#define CYGHWR_HAL_LM3S_PERIPH_GC0               BIT_(31)
+#define CYGHWR_HAL_LM3S_P_WDT0                   ( BIT_(31) | CYGHWR_HAL_LM3S_SC_SCGC0_WDT0 )
+#define CYGHWR_HAL_LM3S_P_ADC0                   ( BIT_(31) | CYGHWR_HAL_LM3S_SC_SCGC0_ADC0 )
+#define CYGHWR_HAL_LM3S_P_PWM                    ( BIT_(31) | CYGHWR_HAL_LM3S_SC_SCGC0_PWM0 )
+#define CYGHWR_HAL_LM3S_PERIPH_GC1               BIT_(30)
+#define CYGHWR_HAL_LM3S_P_UART0                  ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_UART0 )
+#define CYGHWR_HAL_LM3S_P_UART1                  ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_UART1 )
+#define CYGHWR_HAL_LM3S_P_SSI0                   ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_SSI0 )
+#define CYGHWR_HAL_LM3S_P_I2C0                   ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_I2C0 )
+#define CYGHWR_HAL_LM3S_P_TIMER0                 ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_TIMER0 )
+#define CYGHWR_HAL_LM3S_P_TIMER1                 ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_TIMER1 )
+#define CYGHWR_HAL_LM3S_P_TIMER2                 ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_TIMER2 )
+#define CYGHWR_HAL_LM3S_P_COMP0                  ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_COMP0 )
+#define CYGHWR_HAL_LM3S_PERIPH_GC2               BIT_(29)
+#define CYGHWR_HAL_LM3S_P_GPIOA                  ( BIT_(29) | CYGHWR_HAL_LM3S_SC_RCGC2_GPIOA )
+#define CYGHWR_HAL_LM3S_P_GPIOB                  ( BIT_(29) | CYGHWR_HAL_LM3S_SC_RCGC2_GPIOB )
+#define CYGHWR_HAL_LM3S_P_GPIOC                  ( BIT_(29) | CYGHWR_HAL_LM3S_SC_RCGC2_GPIOC )
+#define CYGHWR_HAL_LM3S_P_GPIOD                  ( BIT_(29) | CYGHWR_HAL_LM3S_SC_RCGC2_GPIOD )
+#define CYGHWR_HAL_LM3S_P_GPIOE                  ( BIT_(29) | CYGHWR_HAL_LM3S_SC_RCGC2_GPIOE )
+
+__externC void hal_lm3s_periph_set( cyg_uint32 periph, cyg_uint32 on_off );
+
+#define CYGHWR_HAL_LM3S_PERIPH_SET(__periph, __on_off )  hal_lm3s_periph_set( __periph,  __on_off )
+
+//=============================================================================
+// Watchdog
+
+#define CYGHWR_HAL_LM3S_WDT_LOAD                 0x000
+#define CYGHWR_HAL_LM3S_WDT_VALUE                0x004
+#define CYGHWR_HAL_LM3S_WDT_CTL                  0x008
+#define CYGHWR_HAL_LM3S_WDT_ICR                  0x00c
+#define CYGHWR_HAL_LM3S_WDT_RIS                  0x010
+#define CYGHWR_HAL_LM3S_WDT_MIS                  0x014
+#define CYGHWR_HAL_LM3S_WDT_TEST                 0x418
+#define CYGHWR_HAL_LM3S_WDT_LOCK                 0xc00
+#define CYGHWR_HAL_LM3S_WDT_PID4                 0xfd0
+#define CYGHWR_HAL_LM3S_WDT_PID5                 0xfd4
+#define CYGHWR_HAL_LM3S_WDT_PID6                 0xfd8
+#define CYGHWR_HAL_LM3S_WDT_PID7                 0xfdc
+#define CYGHWR_HAL_LM3S_WDT_PID0                 0xfe0
+#define CYGHWR_HAL_LM3S_WDT_PID1                 0xfe4
+#define CYGHWR_HAL_LM3S_WDT_PID2                 0xfe8
+#define CYGHWR_HAL_LM3S_WDT_PID3                 0xfec
+#define CYGHWR_HAL_LM3S_WDT_PCID0                0xff0
+#define CYGHWR_HAL_LM3S_WDT_PCID1                0xff4
+#define CYGHWR_HAL_LM3S_WDT_PCID2                0xff8
+#define CYGHWR_HAL_LM3S_WDT_PCID3                0xffc
+
+
+#define CYGHWR_HAL_LM3S_WDT_CTL_INTEN            BIT_(0)
+#define CYGHWR_HAL_LM3S_WDT_CTL_RESEN            BIT_(1)
+
+#define CYGHWR_HAL_LM3S_WDT_RIS_RIS              BIT_(0)
+
+#define CYGHWR_HAL_LM3S_WDT_MIS_MIS              BIT_(0)
+
+#define CYGHWR_HAL_LM3S_WDT_TEST_STALL           BIT_(8)
+
+#define CYGHWR_HAL_LM3S_WDT_PID(__x)             ((__x)&0xFF)
+#define CYGHWR_HAL_LM3S_WDT_PCID(__x)            ((__x)&0xFF)
+
+
+//=============================================================================
+// GPIO ports
+
+#define CYGHWR_HAL_LM3S_GPIO_DATA                 0x000
+#define CYGHWR_HAL_LM3S_GPIO_DIR                  0x400
+#define CYGHWR_HAL_LM3S_GPIO_IS                   0x404
+#define CYGHWR_HAL_LM3S_GPIO_IBE                  0x408
+#define CYGHWR_HAL_LM3S_GPIO_IEV                  0x40c
+#define CYGHWR_HAL_LM3S_GPIO_IM                   0x410
+#define CYGHWR_HAL_LM3S_GPIO_RIS                  0x414
+#define CYGHWR_HAL_LM3S_GPIO_MIS                  0x418
+#define CYGHWR_HAL_LM3S_GPIO_ICR                  0x41c
+#define CYGHWR_HAL_LM3S_GPIO_AFSEL                0x420
+#define CYGHWR_HAL_LM3S_GPIO_DR2R                 0x500
+#define CYGHWR_HAL_LM3S_GPIO_DR4R                 0x504
+#define CYGHWR_HAL_LM3S_GPIO_DR8R                 0x508
+#define CYGHWR_HAL_LM3S_GPIO_ODR                  0x50c
+#define CYGHWR_HAL_LM3S_GPIO_PUR                  0x510
+#define CYGHWR_HAL_LM3S_GPIO_PDR                  0x514
+#define CYGHWR_HAL_LM3S_GPIO_SLR                  0x518
+#define CYGHWR_HAL_LM3S_GPIO_DEN                  0x51c
+#define CYGHWR_HAL_LM3S_GPIO_PID4                 0xfd0
+#define CYGHWR_HAL_LM3S_GPIO_PID5                 0xfd4
+#define CYGHWR_HAL_LM3S_GPIO_PID6                 0xfd8
+#define CYGHWR_HAL_LM3S_GPIO_PID7                 0xfdc
+#define CYGHWR_HAL_LM3S_GPIO_PID0                 0xfe0
+#define CYGHWR_HAL_LM3S_GPIO_PID1                 0xfe4
+#define CYGHWR_HAL_LM3S_GPIO_PID2                 0xfe8
+#define CYGHWR_HAL_LM3S_GPIO_PID3                 0xfec
+#define CYGHWR_HAL_LM3S_GPIO_PCID0                0xff0
+#define CYGHWR_HAL_LM3S_GPIO_PCID1                0xff4
+#define CYGHWR_HAL_LM3S_GPIO_PCID2                0xff8
+#define CYGHWR_HAL_LM3S_GPIO_PCID3                0xffc
+
+#define CYGHWR_HAL_LM3S_GPIO_DIR_IN               VALUE_(0,0)     // Input mode
+#define CYGHWR_HAL_LM3S_GPIO_DIR_OUT              VALUE_(0,1)     // Output mode
+
+#define CYGHWR_HAL_LM3S_GPIO_IS_EDGE_SENSE        VALUE_(0,0)     // Interrupt edge sensitive
+#define CYGHWR_HAL_LM3S_GPIO_IS_LEV_SENSE         VALUE_(0,1)     // Interrupt level sensitive
+
+#define CYGHWR_HAL_LM3S_GPIO_IBE_GPIOIEV          VALUE_(0,0)     // Interrupt control from GPIOIEV
+#define CYGHWR_HAL_LM3S_GPIO_IBE_BOTH_EDGE        VALUE_(0,1)     // Both edges can trigger interrupt
+
+#define CYGHWR_HAL_LM3S_GPIO_IEV_LOW              VALUE_(0,0)     // Falling edge or low triggers interrupt
+#define CYGHWR_HAL_LM3S_GPIO_IEV_HIGH             VALUE_(0,1)     // Rising edge or low triggers interrupt
+
+#define CYGHWR_HAL_LM3S_GPIO_IM_MASK              VALUE_(0,0)     // Interrupt is masked
+#define CYGHWR_HAL_LM3S_GPIO_IM_UMASK             VALUE_(0,1)
+
+// HAL definitions
+#define CYGHWR_HAL_LM3S_GPIO_MODE_IN              VALUE_(0,0)     // Input mode
+#define CYGHWR_HAL_LM3S_GPIO_MODE_OUT             VALUE_(0,1)     // Output mode
+#define CYGHWR_HAL_LM3S_GPIO_MODE_PERIPH          VALUE_(0,2)     // Peripheral function mode
+
+#define CYGHWR_HAL_LM3S_GPIO_STRENGTH_NONE        VALUE_(2,0)     // Strength not specified
+#define CYGHWR_HAL_LM3S_GPIO_STRENGTH_2_MA        VALUE_(2,1)     // Strength 2 mA
+#define CYGHWR_HAL_LM3S_GPIO_STRENGTH_4_MA        VALUE_(2,2)     // Strength 4 mA
+#define CYGHWR_HAL_LM3S_GPIO_STRENGTH_8_MA        VALUE_(2,3)     // Strength 8 mA
+
+#define CYGHWR_HAL_LM3S_GPIO_CNF_NONE             VALUE_(4,0)     // Configuration not specified
+#define CYGHWR_HAL_LM3S_GPIO_CNF_PULLUP           VALUE_(4,1)     // Pull-up
+#define CYGHWR_HAL_LM3S_GPIO_CNF_PULLDOWN         VALUE_(4,2)     // Pull-down
+#define CYGHWR_HAL_LM3S_GPIO_CNF_OP               VALUE_(4,3)     // Open-drain
+#define CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLUP        VALUE_(4,4)     // Open-drain / Pull-up
+#define CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLDOWN      VALUE_(4,5)     // Open-drain / Pull-down
+#define CYGHWR_HAL_LM3S_GPIO_CNF_AIN              VALUE_(4,6)     // Analog
+
+#define CYGHWR_HAL_LM3S_GPIO_IRQ_DISABLE          VALUE_(9,0)     // Interrupt disable
+#define CYGHWR_HAL_LM3S_GPIO_IRQ_FALLING_EDGE     VALUE_(9,1)     // Interrupt on falling edge
+#define CYGHWR_HAL_LM3S_GPIO_IRQ_RISING_EDGE      VALUE_(9,2)     // Interrupt on rising edge
+#define CYGHWR_HAL_LM3S_GPIO_IRQ_BOTH_EDGES       VALUE_(9,3)     // Interrupt on both edges
+#define CYGHWR_HAL_LM3S_GPIO_IRQ_LOW_LEVEL        VALUE_(9,4)     // Interrupt on low level
+#define CYGHWR_HAL_LM3S_GPIO_IRQ_HIGH_LEVEL       VALUE_(9,5)     // Interrupt on high level
+
+// This macro packs the port number, bit number, mode, strength, irq and
+// configuration for a GPIO pin into a single word.
+// The packing puts:
+
+#define CYGHWR_HAL_LM3S_GPIO(                                           \
+    __port,                                                             \
+    __bit,                                                              \
+    __mode,                                                             \
+    __strength,                                                         \
+    __cnf,                                                              \
+    __irq)                                                              \
+(                                                                       \
+        (CYGHWR_HAL_LM3S_GPIO ## __port - CYGHWR_HAL_LM3S_GPIOA) |      \
+         (__bit << 24) |                                                \
+         (CYGHWR_HAL_LM3S_GPIO_MODE_ ## __mode) |                       \
+         (CYGHWR_HAL_LM3S_GPIO_STRENGTH_ ## __strength) |               \
+         (CYGHWR_HAL_LM3S_GPIO_IRQ_ ## __irq) |                         \
+         (CYGHWR_HAL_LM3S_GPIO_CNF_ ## __cnf)                           \
+)
+
+// Macros to extract encoded values
+#define CYGHWR_HAL_LM3S_GPIO_PORT(__pin)       (CYGHWR_HAL_LM3S_GPIOA+((__pin)&0x000FF000))
+#define CYGHWR_HAL_LM3S_GPIO_BIT(__pin)        (((__pin)>>24)&0x07)
+#define CYGHWR_HAL_LM3S_GPIO_MODE(__pin)       ((__pin)&0x0003)
+#define CYGHWR_HAL_LM3S_GPIO_STRENGTH(__pin)   ((__pin)&VALUE_(2,3))
+#define CYGHWR_HAL_LM3S_GPIO_CFG(__pin)        ((__pin)&VALUE_(4,7))
+#define CYGHWR_HAL_LM3S_GPIO_IRQ(__pin)        ((__pin)&VALUE_(9,7))
+
+#define CYGHWR_HAL_LM3S_GPIO_NONE              (0xFFFFFFFF)
+
+
+// Functions and macros to configure GPIO ports.
+
+__externC void hal_lm3s_gpio_set( cyg_uint32 pin );
+__externC void hal_lm3s_gpio_out( cyg_uint32 pin, int val );
+__externC void hal_lm3s_gpio_in ( cyg_uint32 pin, int *val );
+
+#define CYGHWR_HAL_LM3S_GPIO_SET(__pin )        hal_lm3s_gpio_set( __pin )
+#define CYGHWR_HAL_LM3S_GPIO_OUT(__pin, __val ) hal_lm3s_gpio_out( __pin, __val )
+#define CYGHWR_HAL_LM3S_GPIO_IN(__pin,  __val ) hal_lm3s_gpio_in( __pin, __val )
+
+
+//=============================================================================
+// UARTs
+
+#define CYGHWR_HAL_LM3S_UART_DR                   0x000
+#define CYGHWR_HAL_LM3S_UART_SR                   0x004
+#define CYGHWR_HAL_LM3S_UART_FR                   0x018
+#define CYGHWR_HAL_LM3S_UART_IBRD                 0x024
+#define CYGHWR_HAL_LM3S_UART_FBRD                 0x028
+#define CYGHWR_HAL_LM3S_UART_LCRH                 0x02c
+#define CYGHWR_HAL_LM3S_UART_CTL                  0x030
+#define CYGHWR_HAL_LM3S_UART_IFLS                 0x034
+#define CYGHWR_HAL_LM3S_UART_IM                   0x038
+#define CYGHWR_HAL_LM3S_UART_RIS                  0x03c
+#define CYGHWR_HAL_LM3S_UART_MIS                  0x040
+#define CYGHWR_HAL_LM3S_UART_ICR                  0x044
+#define CYGHWR_HAL_LM3S_UART_PID4                 0xfd0
+#define CYGHWR_HAL_LM3S_UART_PID5                 0xfd4
+#define CYGHWR_HAL_LM3S_UART_PID6                 0xfd8
+#define CYGHWR_HAL_LM3S_UART_PID7                 0xfdc
+#define CYGHWR_HAL_LM3S_UART_PID0                 0xfe0
+#define CYGHWR_HAL_LM3S_UART_PID1                 0xfe4
+#define CYGHWR_HAL_LM3S_UART_PID2                 0xfe8
+#define CYGHWR_HAL_LM3S_UART_PID3                 0xfec
+#define CYGHWR_HAL_LM3S_UART_PCID0                0xff0
+#define CYGHWR_HAL_LM3S_UART_PCID1                0xff4
+#define CYGHWR_HAL_LM3S_UART_PCID2                0xff8
+#define CYGHWR_HAL_LM3S_UART_PCID3                0xffc
+
+
+// DR Bits
+#define CYGHWR_HAL_LM3S_UART_DR_FE                BIT_(8)
+#define CYGHWR_HAL_LM3S_UART_DR_PE                BIT_(9)
+#define CYGHWR_HAL_LM3S_UART_DR_BE                BIT_(10)
+#define CYGHWR_HAL_LM3S_UART_DR_OE                BIT_(11)
+
+// SR Bits
+#define CYGHWR_HAL_LM3S_UART_SR_FE                BIT_(0)
+#define CYGHWR_HAL_LM3S_UART_SR_PE                BIT_(1)
+#define CYGHWR_HAL_LM3S_UART_SR_BE                BIT_(2)
+#define CYGHWR_HAL_LM3S_UART_SR_OE                BIT_(3)
+
+// FR bits
+#define CYGHWR_HAL_LM3S_UART_FR_BUSY              BIT_(3)
+#define CYGHWR_HAL_LM3S_UART_FR_RXFE              BIT_(4)
+#define CYGHWR_HAL_LM3S_UART_FR_TXFF              BIT_(5)
+#define CYGHWR_HAL_LM3S_UART_FR_RXFF              BIT_(6)
+#define CYGHWR_HAL_LM3S_UART_FR_TXFE              BIT_(7)
+
+// LCRH bits
+#define CYGHWR_HAL_LM3S_UART_LCRH_BRK             BIT_(0)
+#define CYGHWR_HAL_LM3S_UART_LCRH_PEN             BIT_(1)
+#define CYGHWR_HAL_LM3S_UART_LCRH_EPS             BIT_(2)
+#define CYGHWR_HAL_LM3S_UART_LCRH_STP2            BIT_(3)
+#define CYGHWR_HAL_LM3S_UART_LCRH_FEN             BIT_(4)
+#define CYGHWR_HAL_LM3S_UART_LCRH_WLEN(__x)       VALUE_(5,__x)
+#define CYGHWR_HAL_LM3S_UART_LCRH_WLEN_MASK       0x00000060
+#define CYGHWR_HAL_LM3S_UART_LCRH_SPS             BIT_(7)
+
+// CTL bits
+#define CYGHWR_HAL_LM3S_UART_CTL_UARTEN           BIT_(0)
+#define CYGHWR_HAL_LM3S_UART_CTL_LBE              BIT_(7)
+#define CYGHWR_HAL_LM3S_UART_CTL_TXE              BIT_(8)
+#define CYGHWR_HAL_LM3S_UART_CTL_RXE              BIT_(9)
+
+// IFLS bits
+#define CYGHWR_HAL_LM3S_UART_IFLS_RXIFLSEL(__x)   VALUE_(0,__x)
+#define CYGHWR_HAL_LM3S_UART_IFLS_RXIFLSEL_MASK   0x00000007
+#define CYGHWR_HAL_LM3S_UART_IFLS_TXIFLSEL(__x)   VALUE_(3,__x)
+#define CYGHWR_HAL_LM3S_UART_IFLS_TXIFLSEL_MASK   0x00000038
+
+// IM bits
+#define CYGHWR_HAL_LM3S_UART_IM_RXIM              BIT_(4)
+#define CYGHWR_HAL_LM3S_UART_IM_TXIM              BIT_(5)
+#define CYGHWR_HAL_LM3S_UART_IM_RTIM              BIT_(6)
+#define CYGHWR_HAL_LM3S_UART_IM_FEIM              BIT_(7)
+#define CYGHWR_HAL_LM3S_UART_IM_PEIM              BIT_(8)
+#define CYGHWR_HAL_LM3S_UART_IM_BEIM              BIT_(9)
+#define CYGHWR_HAL_LM3S_UART_IM_OEIM              BIT_(10)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_UART_RIS_RXRIS            BIT_(4)
+#define CYGHWR_HAL_LM3S_UART_RIS_TXRIS            BIT_(5)
+#define CYGHWR_HAL_LM3S_UART_RIS_RTRIS            BIT_(6)
+#define CYGHWR_HAL_LM3S_UART_RIS_FERIS            BIT_(7)
+#define CYGHWR_HAL_LM3S_UART_RIS_PERIS            BIT_(8)
+#define CYGHWR_HAL_LM3S_UART_RIS_BERIS            BIT_(9)
+#define CYGHWR_HAL_LM3S_UART_RIS_OERIS            BIT_(10)
+
+// MIS bits
+#define CYGHWR_HAL_LM3S_UART_MIS_RXMIS            BIT_(4)
+#define CYGHWR_HAL_LM3S_UART_MIS_TXMIS            BIT_(5)
+#define CYGHWR_HAL_LM3S_UART_MIS_RTMIS            BIT_(6)
+#define CYGHWR_HAL_LM3S_UART_MIS_FEMIS            BIT_(7)
+#define CYGHWR_HAL_LM3S_UART_MIS_PEMIS            BIT_(8)
+#define CYGHWR_HAL_LM3S_UART_MIS_BEMIS            BIT_(9)
+#define CYGHWR_HAL_LM3S_UART_MIS_OEMIS            BIT_(10)
+
+// ICR bits
+#define CYGHWR_HAL_LM3S_UART_ICR_RXIC             BIT_(4)
+#define CYGHWR_HAL_LM3S_UART_ICR_TXIC             BIT_(5)
+#define CYGHWR_HAL_LM3S_UART_ICR_RTIC             BIT_(6)
+#define CYGHWR_HAL_LM3S_UART_ICR_FEIC             BIT_(7)
+#define CYGHWR_HAL_LM3S_UART_ICR_PEIC             BIT_(8)
+#define CYGHWR_HAL_LM3S_UART_ICR_BEIC             BIT_(9)
+#define CYGHWR_HAL_LM3S_UART_ICR_OEIC             BIT_(10)
+
+// UARTO shall be connected to PortA 0/1 on all device
+#ifndef CYGHWR_HAL_LM3S_UART0_TX
+# define CYGHWR_HAL_LM3S_UART0_TX                 CYGHWR_HAL_LM3S_GPIO( A, 0, PERIPH, NONE, NONE, DISABLE )
+#endif
+#ifndef CYGHWR_HAL_LM3S_UART0_RX
+# define CYGHWR_HAL_LM3S_UART0_RX                 CYGHWR_HAL_LM3S_GPIO( A, 1, PERIPH, NONE, NONE, DISABLE )
+#endif
+#ifndef CYGHWR_HAL_LM3S_P_UART0_GPIO
+# define CYGHWR_HAL_LM3S_P_UART0_GPIO             CYGHWR_HAL_LM3S_P_GPIOA
+#endif
+
+#ifndef __ASSEMBLER__
+
+__externC void hal_lm3s_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud );
+
+#endif
+
+//=============================================================================
+// ADCs
+
+#ifdef CYGHWR_HAL_LM3S_ADC0_CHAN
+
+#define CYGHWR_HAL_LM3S_ADC_ACTSS                 0x0
+#define CYGHWR_HAL_LM3S_ADC_RIS                   0x4
+#define CYGHWR_HAL_LM3S_ADC_IMR                   0x8
+#define CYGHWR_HAL_LM3S_ADC_ISCR                  0xc
+#define CYGHWR_HAL_LM3S_ADC_OSR                   0x10
+#define CYGHWR_HAL_LM3S_ADC_EMUX                  0x14
+#define CYGHWR_HAL_LM3S_ADC_USR                   0x18
+#define CYGHWR_HAL_LM3S_ADC_SSPRI                 0x20
+#define CYGHWR_HAL_LM3S_ADC_PSSI                  0x28
+#define CYGHWR_HAL_LM3S_ADC_SAC                   0x30
+#define CYGHWR_HAL_LM3S_ADC_SS_MUX0               0x40
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0               0x44
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO0              0x48
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO0_SR           0x4c
+#define CYGHWR_HAL_LM3S_ADC_SS_MUX1               0x60
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL1               0x64
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO1              0x68
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO1_SR           0x6c
+#define CYGHWR_HAL_LM3S_ADC_SS_MUX2               0x80
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL2               0x84
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO2              0x88
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO2_SR           0x8c
+#define CYGHWR_HAL_LM3S_ADC_SS_MUX3               0xa0
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL3               0xa4
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO3              0xa8
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO3_SR           0xac
+#define CYGHWR_HAL_LM3S_ADC_TMLB                  0x100
+
+#define CYGHWR_HAL_LM3S_ADC_SAMPLE_SIZE           10
+
+// Active Sample Sequencer
+#define CYGHWR_HAL_LM3S_ADC_ACTSS_ASEN(__x)       VALUE_(((__x)&3),1)
+
+// Raw Interrupt Status
+#define CYGHWR_HAL_LM3S_ADC_RIS_INR(__x)          VALUE_(((__x)&3),1)
+
+// Interrupt Mask Register
+#define CYGHWR_HAL_LM3S_ADC_IMR_MASK(__x)         VALUE_(((__x)&3),1)
+
+// Interrupt Status and Clear Register
+#define CYGHWR_HAL_LM3S_ADC_ISCR_IN(__x)          VALUE_(((__x)&3),1)
+
+// Overflow Status Register
+#define CYGHWR_HAL_LM3S_ADC_OSR_OV(__x)           VALUE_(((__x)&3),1)
+
+// Event Multiplexer Select
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_CTRL(__x)     VALUE_((((__x)&3)<<2),0)
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_AC0(__x)      VALUE_((((__x)&3)<<2),1)
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_EXT(__x)      VALUE_((((__x)&3)<<2),4)
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_TIMER(__x)    VALUE_((((__x)&3)<<2),5)
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_PWM0(__x)     VALUE_((((__x)&3)<<2),6)
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_PWM1(__x)     VALUE_((((__x)&3)<<2),7)
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_PWM2(__x)     VALUE_((((__x)&3)<<2),8)
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_ALWS(__x)     VALUE_((((__x)&3)<<2),15)
+
+// Underflow Status
+#define CYGHWR_HAL_LM3S_ADC_USR_UV(__x)           VALUE_(((__x)&3),1)
+
+// Sample Sequence Priority
+#define CYGHWR_HAL_LM3S_ADC_SSPRI_SS(__x, __y)    VALUE_((((__x)&3)<<2),(__y)&3)
+
+// Processor Sample Sequence Initiate
+#define CYGHWR_HAL_LM3S_ADC_PSSI_SS(__x)          VALUE_(((__x)&3),1)
+
+// Sample Averaging Control
+#define CYGHWR_HAL_LM3S_ADC_SAC_NO_OVER           0x0
+#define CYGHWR_HAL_LM3S_ADC_SAC_2X                0x1
+#define CYGHWR_HAL_LM3S_ADC_SAC_4X                0x2
+#define CYGHWR_HAL_LM3S_ADC_SAC_8X                0x3
+#define CYGHWR_HAL_LM3S_ADC_SAC_16X               0x4
+#define CYGHWR_HAL_LM3S_ADC_SAC_32X               0x5
+#define CYGHWR_HAL_LM3S_ADC_SAC_64X               0x6
+
+// Sample Sequence Input Multiplexer Select 0
+#define CYGHWR_HAL_LM3S_ADC_SS_MUX0_V(_p_, _x_)   VALUE_((((_x_)&3)<<2),_p_)
+#define CYGHWR_HAL_LM3S_ADC_SS_MUX0_M(_x_)        VALUE_((((_x_)&3)<<2), 0x3)
+
+// Sample Sequence Control 0
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D0            BIT_(0)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END0          BIT_(1)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE0           BIT_(2)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS0           BIT_(3)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D1            BIT_(4)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END1          BIT_(5)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE1           BIT_(6)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS1           BIT_(7)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D2            BIT_(8)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END2          BIT_(9)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE2           BIT_(10)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS2           BIT_(11)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D3            BIT_(12)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END3          BIT_(13)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE3           BIT_(14)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS3           BIT_(15)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D4            BIT_(16)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END4          BIT_(17)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE4           BIT_(18)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS4           BIT_(19)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D5            BIT_(20)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END5          BIT_(21)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE5           BIT_(22)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS5           BIT_(23)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D6            BIT_(24)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END6          BIT_(25)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE6           BIT_(26)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS6           BIT_(27)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D7            BIT_(28)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END7          BIT_(29)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE7           BIT_(30)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS7           BIT_(31)
+
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_MASK(_x_)     VALUE_((((_x_)&3)<<2), 0x15)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D(_x_)        VALUE_((((_x_)&3)<<2), 0x1)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END(_x_)      VALUE_((((_x_)&3)<<2), 0x2)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE(_x_)       VALUE_((((_x_)&3)<<2), 0x4)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS(_x_)       VALUE_((((_x_)&3)<<2), 0x8)
+
+// Sequence FIFO Status
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_TPTR       0x0
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_HPTR       0x0
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_EMPTY      BIT_(8)
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_FULL       BIT_(12)
+
+#endif // CYGHWR_HAL_LM3S_ADC0_CHAN
+
+
+//=============================================================================
+// SSI interface register definitions.
+
+#ifdef CYGHWR_HAL_LM3S_SSI_CHAN
+
+#define CYGHWR_HAL_LM3S_SSI_CR0                   0x000
+#define CYGHWR_HAL_LM3S_SSI_CR1                   0x004
+#define CYGHWR_HAL_LM3S_SSI_DR                    0x008
+#define CYGHWR_HAL_LM3S_SSI_SR                    0x00C
+#define CYGHWR_HAL_LM3S_SSI_CPSR                  0x010
+#define CYGHWR_HAL_LM3S_SSI_IM                    0x014
+#define CYGHWR_HAL_LM3S_SSI_RIS                   0x018
+#define CYGHWR_HAL_LM3S_SSI_MIS                   0x01c
+#define CYGHWR_HAL_LM3S_SSI_ICR                   0x020
+#define CYGHWR_HAL_LM3S_SSI_PID4                  0xfd0
+#define CYGHWR_HAL_LM3S_SSI_PID5                  0xfd4
+#define CYGHWR_HAL_LM3S_SSI_PID6                  0xfd8
+#define CYGHWR_HAL_LM3S_SSI_PID7                  0xfdc
+#define CYGHWR_HAL_LM3S_SSI_PID0                  0xfe0
+#define CYGHWR_HAL_LM3S_SSI_PID1                  0xfe4
+#define CYGHWR_HAL_LM3S_SSI_PID2                  0xfe8
+#define CYGHWR_HAL_LM3S_SSI_PID3                  0xfec
+#define CYGHWR_HAL_LM3S_SSI_PCID0                 0xff0
+#define CYGHWR_HAL_LM3S_SSI_PCID1                 0xff4
+#define CYGHWR_HAL_LM3S_SSI_PCID2                 0xff8
+#define CYGHWR_HAL_LM3S_SSI_PCID3                 0xffc
+
+
+// CR0 bits
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_4BIT          VALUE_(0, 0x3)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_5BIT          VALUE_(0, 0x4)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_6BIT          VALUE_(0, 0x5)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_7BIT          VALUE_(0, 0x6)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_8BIT          VALUE_(0, 0x7)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_9BIT          VALUE_(0, 0x8)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_10BIT         VALUE_(0, 0x9)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_11BIT         VALUE_(0, 0xa)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_12BIT         VALUE_(0, 0xb)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_13BIT         VALUE_(0, 0xc)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_14BIT         VALUE_(0, 0xd)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_15BIT         VALUE_(0, 0xe)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_16BIT         VALUE_(0, 0xf)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_MASK          0x0000000f
+#define CYGHWR_HAL_LM3S_SSI_CR0_FRF_FSPIFF        VALUE_(4, 0x0)
+#define CYGHWR_HAL_LM3S_SSI_CR0_FRF_TISSFF        VALUE_(4, 0x1)
+#define CYGHWR_HAL_LM3S_SSI_CR0_FRF_MFF           VALUE_(4, 0x2)
+#define CYGHWR_HAL_LM3S_SSI_CR0_FRF_MASK          0x00000030
+#define CYGHWR_HAL_LM3S_SSI_CR0_SPO               BIT_(6)
+#define CYGHWR_HAL_LM3S_SSI_CR0_SPH               BIT_(7)
+#define CYGHWR_HAL_LM3S_SSI_CR0_SCR(__x)          VALUE_(8, ((__x)&0xff))
+
+// CR1 bits
+#define CYGHWR_HAL_LM3S_SSI_CR1_LBM               BIT_(0)
+#define CYGHWR_HAL_LM3S_SSI_CR1_SSE               BIT_(1)
+#define CYGHWR_HAL_LM3S_SSI_CR1_MS                BIT_(2)
+#define CYGHWR_HAL_LM3S_SSI_CR1_SOD               BIT_(3)
+
+// SR bits
+#define CYGHWR_HAL_LM3S_SSI_SR_TFE                BIT_(0)
+#define CYGHWR_HAL_LM3S_SSI_SR_TNF                BIT_(1)
+#define CYGHWR_HAL_LM3S_SSI_SR_RNE                BIT_(2)
+#define CYGHWR_HAL_LM3S_SSI_SR_RFF                BIT_(3)
+#define CYGHWR_HAL_LM3S_SSI_SR_BSY                BIT_(4)
+
+// IM bits
+#define CYGHWR_HAL_LM3S_SSI_IM_RORIM              BIT_(0)
+#define CYGHWR_HAL_LM3S_SSI_IM_RTIM               BIT_(1)
+#define CYGHWR_HAL_LM3S_SSI_IM_RXIM               BIT_(2)
+#define CYGHWR_HAL_LM3S_SSI_IM_TXIM               BIT_(3)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_SSI_RIS_RORRIS            BIT_(0)
+#define CYGHWR_HAL_LM3S_SSI_RIS_RTRIS             BIT_(1)
+#define CYGHWR_HAL_LM3S_SSI_RIS_RXRIS             BIT_(2)
+#define CYGHWR_HAL_LM3S_SSI_RIS_TXRIS             BIT_(3)
+
+// MIS bits
+#define CYGHWR_HAL_LM3S_SSI_MIS_RORMIS            BIT_(0)
+#define CYGHWR_HAL_LM3S_SSI_MIS_RTMIS             BIT_(1)
+#define CYGHWR_HAL_LM3S_SSI_MIS_RXMIS             BIT_(2)
+#define CYGHWR_HAL_LM3S_SSI_MIS_TXMIS             BIT_(3)
+
+// ICR bits
+#define CYGHWR_HAL_LM3S_SSI_ICR_RORIC             BIT_(0)
+#define CYGHWR_HAL_LM3S_SSI_ICR_RTIC              BIT_(1)
+
+#endif // CYGHWR_HAL_LM3S_SSI_CHAN
+
+//=============================================================================
+// PWM register definitions.
+
+#ifdef CYGHWR_HAL_LM3S_PWM_CHAN
+
+#define CYGHWR_HAL_LM3S_PWM_CTL                   0x000
+#define CYGHWR_HAL_LM3S_PWM_SYNC                  0x004
+#define CYGHWR_HAL_LM3S_PWM_ENABLE                0x008
+#define CYGHWR_HAL_LM3S_PWM_INVERT                0x00c
+#define CYGHWR_HAL_LM3S_PWM_FAULT                 0x010
+#define CYGHWR_HAL_LM3S_PWM_INTEN                 0x014
+#define CYGHWR_HAL_LM3S_PWM_RIS                   0x018
+#define CYGHWR_HAL_LM3S_PWM_ISC                   0x01c
+#define CYGHWR_HAL_LM3S_PWM_STATUS                0x020
+
+#define CYGHWR_HAL_LM3S_PWM0_CTL                  0x040
+#define CYGHWR_HAL_LM3S_PWM0_INTEN                0x044
+#define CYGHWR_HAL_LM3S_PWM0_RIS                  0x048
+#define CYGHWR_HAL_LM3S_PWM0_ISC                  0x04c
+#define CYGHWR_HAL_LM3S_PWM0_LOAD                 0x050
+#define CYGHWR_HAL_LM3S_PWM0_COUNT                0x054
+#define CYGHWR_HAL_LM3S_PWM0_CMPA                 0x058
+#define CYGHWR_HAL_LM3S_PWM0_CMPB                 0x05c
+#define CYGHWR_HAL_LM3S_PWM0_GENA                 0x060
+#define CYGHWR_HAL_LM3S_PWM0_GENB                 0x064
+#define CYGHWR_HAL_LM3S_PWM0_DBCTL                0x068
+#define CYGHWR_HAL_LM3S_PWM0_DBRISE               0x06c
+#define CYGHWR_HAL_LM3S_PWM0_DBFALL               0x070
+
+#define CYGHWR_HAL_LM3S_PWM1_CTL                  0x080
+#define CYGHWR_HAL_LM3S_PWM1_INTEN                0x084
+#define CYGHWR_HAL_LM3S_PWM1_RIS                  0x088
+#define CYGHWR_HAL_LM3S_PWM1_ISC                  0x08c
+#define CYGHWR_HAL_LM3S_PWM1_LOAD                 0x090
+#define CYGHWR_HAL_LM3S_PWM1_COUNT                0x094
+#define CYGHWR_HAL_LM3S_PWM1_CMPA                 0x098
+#define CYGHWR_HAL_LM3S_PWM1_CMPB                 0x09c
+#define CYGHWR_HAL_LM3S_PWM1_GENA                 0x0a0
+#define CYGHWR_HAL_LM3S_PWM1_GENB                 0x0a4
+#define CYGHWR_HAL_LM3S_PWM1_DBCTL                0x0a8
+#define CYGHWR_HAL_LM3S_PWM1_DBRISE               0x0ac
+#define CYGHWR_HAL_LM3S_PWM1_DBFALL               0x0b0
+
+#define CYGHWR_HAL_LM3S_PWM2_CTL                  0x0c0
+#define CYGHWR_HAL_LM3S_PWM2_INTEN                0x0c4
+#define CYGHWR_HAL_LM3S_PWM2_RIS                  0x0c8
+#define CYGHWR_HAL_LM3S_PWM2_ISC                  0x0cc
+#define CYGHWR_HAL_LM3S_PWM2_LOAD                 0x0d0
+#define CYGHWR_HAL_LM3S_PWM2_COUNT                0x0d4
+#define CYGHWR_HAL_LM3S_PWM2_CMPA                 0x0d8
+#define CYGHWR_HAL_LM3S_PWM2_CMPB                 0x0dc
+#define CYGHWR_HAL_LM3S_PWM2_GENA                 0x0e0
+#define CYGHWR_HAL_LM3S_PWM2_GENB                 0x0e4
+#define CYGHWR_HAL_LM3S_PWM2_DBCTL                0x0e8
+#define CYGHWR_HAL_LM3S_PWM2_DBRISE               0x0ec
+#define CYGHWR_HAL_LM3S_PWM2_DBFALL               0x0f0
+
+
+// CTL bits
+#define CYGHWR_HAL_LM3S_PWM_CTL_GSYNC0            BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_CTL_GSYNC1            BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_CTL_GSYNC2            BIT_(2)
+
+// SYNC bits
+#define CYGHWR_HAL_LM3S_PWM_SYNC_SYNC0            BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_SYNC_SYNC1            BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_SYNC_SYNC2            BIT_(2)
+
+// ENABLE bits
+#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM0           BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM1           BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM2           BIT_(2)
+#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM3           BIT_(3)
+#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM4           BIT_(4)
+#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM5           BIT_(5)
+
+// INVERT bits
+#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM0           BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM1           BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM2           BIT_(2)
+#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM3           BIT_(3)
+#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM4           BIT_(4)
+#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM5           BIT_(5)
+
+// FAULT bits
+#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM0            BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM1            BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM2            BIT_(2)
+#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM3            BIT_(3)
+#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM4            BIT_(4)
+#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM5            BIT_(5)
+
+// INTEN bits
+#define CYGHWR_HAL_LM3S_PWM_INTEN_PWM0            BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_INTEN_PWM1            BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_INTEN_PWM2            BIT_(2)
+#define CYGHWR_HAL_LM3S_PWM_INTEN_FAULT           BIT_(16)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_PWM_RIS_PWM0              BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_RIS_PWM1              BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_RIS_PWM2              BIT_(2)
+#define CYGHWR_HAL_LM3S_PWM_RIS_FAULT             BIT_(16)
+
+// ISC bits
+#define CYGHWR_HAL_LM3S_PWM_ISC_PWM0              BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_ISC_PWM1              BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_ISC_PWM2              BIT_(2)
+#define CYGHWR_HAL_LM3S_PWM_ISC_FAULT             BIT_(16)
+
+// STATUS bits
+#define CYGHWR_HAL_LM3S_PWM_STATUS_FAULT          BIT_(0)
+
+// PWMx CTL Bits
+#define CYGHWR_HAL_LM3S_PWMx_CTL_ENABLE           BIT_(0)
+#define CYGHWR_HAL_LM3S_PWMx_CTL_MODE             BIT_(1)
+#define CYGHWR_HAL_LM3S_PWMx_CTL_DEBUG            BIT_(2)
+#define CYGHWR_HAL_LM3S_PWMx_CTL_LOAD_UPD         BIT_(3)
+#define CYGHWR_HAL_LM3S_PWMx_CTL_CMPA_UPD         BIT_(4)
+#define CYGHWR_HAL_LM3S_PWMx_CTL_CMPB_UPD         BIT_(5)
+
+// PWMx INTEN Bits
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_CNT_ZERO       BIT_(0)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_CNT_LOAD       BIT_(1)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_CMPA_UP        BIT_(2)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_CMPA_DOWN      BIT_(3)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_CMPB_UP        BIT_(4)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_CMPB_DOWN      BIT_(5)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CNT_ZERO  BIT_(8)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CNT_LOAD  BIT_(9)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CMPA_UP   BIT_(10)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CMPA_DOWN BIT_(11)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CMPB_UP   BIT_(12)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CMPB_DOWN BIT_(13)
+
+// PWMx RIS Bits
+#define CYGHWR_HAL_LM3S_PWMx_RIS_CNT_ZERO         BIT_(0)
+#define CYGHWR_HAL_LM3S_PWMx_RIS_CNT_LOAD         BIT_(1)
+#define CYGHWR_HAL_LM3S_PWMx_RIS_CMPA_UP          BIT_(2)
+#define CYGHWR_HAL_LM3S_PWMx_RIS_CMPA_DOWN        BIT_(3)
+#define CYGHWR_HAL_LM3S_PWMx_RIS_CMPB_UP          BIT_(4)
+#define CYGHWR_HAL_LM3S_PWMx_RIS_CMPB_DOWN        BIT_(5)
+
+// PWMx ISC Bits
+#define CYGHWR_HAL_LM3S_PWMx_ISC_CNT_ZERO         BIT_(0)
+#define CYGHWR_HAL_LM3S_PWMx_ISC_CNT_LOAD         BIT_(1)
+#define CYGHWR_HAL_LM3S_PWMx_ISC_CMPA_UP          BIT_(2)
+#define CYGHWR_HAL_LM3S_PWMx_ISC_CMPA_DOWN        BIT_(3)
+#define CYGHWR_HAL_LM3S_PWMx_ISC_CMPB_UP          BIT_(4)
+#define CYGHWR_HAL_LM3S_PWMx_ISC_CMPB_DOWN        BIT_(5)
+
+// PWMx GENA Bits
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_ZERO_NONE   VALUE_(0, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_ZERO_INVS   VALUE_(0, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_ZERO_SET0   VALUE_(0, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_ZERO_SET1   VALUE_(0, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_ZERO_MASK   0x00000003
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_LOAD_NONE   VALUE_(2, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_LOAD_INVS   VALUE_(2, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_LOAD_SET0   VALUE_(2, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_LOAD_SET1   VALUE_(2, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_LOAD_MASK   0x0000000c
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_UP_NONE    VALUE_(4, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_UP_INVS    VALUE_(4, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_UP_SET0    VALUE_(4, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_UP_SET1    VALUE_(4, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_UP_MASK    0x00000030
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_DOWN_NONE  VALUE_(6, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_DOWN_INVS  VALUE_(6, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_DOWN_SET0  VALUE_(6, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_DOWN_SET1  VALUE_(6, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_DOWN_MASK  0x000000c0
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_UP_NONE    VALUE_(8, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_UP_INVS    VALUE_(8, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_UP_SET0    VALUE_(8, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_UP_SET1    VALUE_(8, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_UP_MASK    0x00000300
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_DOWN_NONE  VALUE_(10, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_DOWN_INVS  VALUE_(10, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_DOWN_SET0  VALUE_(10, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_DOWN_SET1  VALUE_(10, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_DOWN_MASK  0x00000c00
+
+// PWMx GENB Bits
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_ZERO_NONE   VALUE_(0, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_ZERO_INVS   VALUE_(0, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_ZERO_SET0   VALUE_(0, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_ZERO_SET1   VALUE_(0, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_ZERO_MASK   0x00000003
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_LOAD_NONE   VALUE_(2, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_LOAD_INVS   VALUE_(2, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_LOAD_SET0   VALUE_(2, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_LOAD_SET1   VALUE_(2, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_LOAD_MASK   0x0000000c
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_UP_NONE    VALUE_(4, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_UP_INVS    VALUE_(4, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_UP_SET0    VALUE_(4, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_UP_SET1    VALUE_(4, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_UP_MASK    0x00000030
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_DOWN_NONE  VALUE_(6, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_DOWN_INVS  VALUE_(6, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_DOWN_SET0  VALUE_(6, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_DOWN_SET1  VALUE_(6, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_DOWN_MASK  0x000000c0
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_UP_NONE    VALUE_(8, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_UP_INVS    VALUE_(8, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_UP_SET0    VALUE_(8, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_UP_SET1    VALUE_(8, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_UP_MASK    0x00000300
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_DOWN_NONE  VALUE_(10, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_DOWN_INVS  VALUE_(10, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_DOWN_SET0  VALUE_(10, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_DOWN_SET1  VALUE_(10, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_DOWN_MASK  0x00000c00
+
+// PWMx DBCTL Bits
+#define CYGHWR_HAL_LM3S_PWMx_DBCTL_ENABLE         BIT_(0)
+
+#endif // CYGHWR_HAL_LM3S_PWM_CHAN
+
+
+//=============================================================================
+// Global Timers register definitions.
+
+#define CYGHWR_HAL_LM3S_GPTIM_CFG                 0x000
+#define CYGHWR_HAL_LM3S_GPTIM_TAMR                0x004
+#define CYGHWR_HAL_LM3S_GPTIM_TBMR                0x008
+#define CYGHWR_HAL_LM3S_GPTIM_CTL                 0x00c
+#define CYGHWR_HAL_LM3S_GPTIM_IMR                 0x018
+#define CYGHWR_HAL_LM3S_GPTIM_RIS                 0x01C
+#define CYGHWR_HAL_LM3S_GPTIM_MIS                 0x020
+#define CYGHWR_HAL_LM3S_GPTIM_ICR                 0x024
+#define CYGHWR_HAL_LM3S_GPTIM_TAILR               0x028
+#define CYGHWR_HAL_LM3S_GPTIM_TBILR               0x02c
+#define CYGHWR_HAL_LM3S_GPTIM_TAMATCHR            0x030
+#define CYGHWR_HAL_LM3S_GPTIM_TBMATCHR            0x034
+#define CYGHWR_HAL_LM3S_GPTIM_TAPR                0x038
+#define CYGHWR_HAL_LM3S_GPTIM_TBPR                0x03c
+#define CYGHWR_HAL_LM3S_GPTIM_TAPMR               0x040
+#define CYGHWR_HAL_LM3S_GPTIM_TBPMR               0x044
+#define CYGHWR_HAL_LM3S_GPTIM_TAR                 0x048
+#define CYGHWR_HAL_LM3S_GPTIM_TBR                 0x04c
+
+// CFG bits
+#define CYGHWR_HAL_LM3S_GPTIM_CFG_32BIT           VALUE_(0, 0x0)
+#define CYGHWR_HAL_LM3S_GPTIM_CFG_32BIT_RTC       VALUE_(0, 0x1)
+#define CYGHWR_HAL_LM3S_GPTIM_CFG_16BIT           VALUE_(0, 0x4)
+#define CYGHWR_HAL_LM3S_GPTIM_CFG_MASK            0x00000007
+
+// TAMR bits
+#define CYGHWR_HAL_LM3S_GPTIM_TAMR_ONE_SHOT       VALUE_(0, 0x1)
+#define CYGHWR_HAL_LM3S_GPTIM_TAMR_PERIODIC       VALUE_(0, 0x2)
+#define CYGHWR_HAL_LM3S_GPTIM_TAMR_CAPTURE        VALUE_(0, 0x3)
+#define CYGHWR_HAL_LM3S_GPTIM_TAMR_MASK           0x00000003
+#define CYGHWR_HAL_LM3S_GPTIM_TAMR_TACMR          BIT_(2)
+#define CYGHWR_HAL_LM3S_GPTIM_TAMR_TAAMS          BIT_(3)
+
+// TBMR bits
+#define CYGHWR_HAL_LM3S_GPTIM_TBMR_ONE_SHOT       VALUE_(0, 0x1)
+#define CYGHWR_HAL_LM3S_GPTIM_TBMR_PERIODIC       VALUE_(0, 0x2)
+#define CYGHWR_HAL_LM3S_GPTIM_TBMR_CAPTURE        VALUE_(0, 0x3)
+#define CYGHWR_HAL_LM3S_GPTIM_TBMR_MASK           0x00000003
+#define CYGHWR_HAL_LM3S_GPTIM_TBMR_TBCMR          BIT_(2)
+#define CYGHWR_HAL_LM3S_GPTIM_TBMR_TBAMS          BIT_(3)
+
+// CTL bits
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAEN            BIT_(0)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TASTALL         BIT_(1)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAEVENT_POS     VALUE_(2, 0x0)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAEVENT_NEG     VALUE_(2, 0x1)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAEVENT_BOTH    VALUE_(2, 0x3)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_RTCEN           BIT_(4)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAOTE           BIT_(5)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAPWML          BIT_(6)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBEN            BIT_(8)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBSTALL         BIT_(9)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBEVENT_POS     VALUE_(10, 0x0)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBEVENT_NEG     VALUE_(10, 0x1)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBEVENT_BOTH    VALUE_(10, 0x3)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBOTE           BIT_(13)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBPWML          BIT_(14)
+
+// IMR bits
+#define CYGHWR_HAL_LM3S_GPTIM_IMR_TATOIM          BIT_(0)
+#define CYGHWR_HAL_LM3S_GPTIM_IMR_CAMIM           BIT_(1)
+#define CYGHWR_HAL_LM3S_GPTIM_IMR_CAEIM           BIT_(2)
+#define CYGHWR_HAL_LM3S_GPTIM_IMR_RTCIM           BIT_(3)
+#define CYGHWR_HAL_LM3S_GPTIM_IMR_TBTOIM          BIT_(8)
+#define CYGHWR_HAL_LM3S_GPTIM_IMR_CBMIM           BIT_(9)
+#define CYGHWR_HAL_LM3S_GPTIM_IMR_CBEIM           BIT_(10)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_GPTIM_RIS_TATORIS         BIT_(0)
+#define CYGHWR_HAL_LM3S_GPTIM_RIS_CAMRIS          BIT_(1)
+#define CYGHWR_HAL_LM3S_GPTIM_RIS_CAERIS          BIT_(2)
+#define CYGHWR_HAL_LM3S_GPTIM_RIS_RTCRIS          BIT_(3)
+#define CYGHWR_HAL_LM3S_GPTIM_RIS_TBTORIS         BIT_(8)
+#define CYGHWR_HAL_LM3S_GPTIM_RIS_CBMRIS          BIT_(9)
+#define CYGHWR_HAL_LM3S_GPTIM_RIS_CBERIS          BIT_(10)
+
+// MIS bits
+#define CYGHWR_HAL_LM3S_GPTIM_MIS_TATOMIS         BIT_(0)
+#define CYGHWR_HAL_LM3S_GPTIM_MIS_CAMMIS          BIT_(1)
+#define CYGHWR_HAL_LM3S_GPTIM_MIS_CAEMIS          BIT_(2)
+#define CYGHWR_HAL_LM3S_GPTIM_MIS_RTCMIS          BIT_(3)
+#define CYGHWR_HAL_LM3S_GPTIM_MIS_TBTOMIS         BIT_(8)
+#define CYGHWR_HAL_LM3S_GPTIM_MIS_CBMMIS          BIT_(9)
+#define CYGHWR_HAL_LM3S_GPTIM_MIS_CBEMIS          BIT_(10)
+
+// ICR bits
+#define CYGHWR_HAL_LM3S_GPTIM_ICR_TATOCINT        BIT_(0)
+#define CYGHWR_HAL_LM3S_GPTIM_ICR_CAMCINT         BIT_(1)
+#define CYGHWR_HAL_LM3S_GPTIM_ICR_CAECINT         BIT_(2)
+#define CYGHWR_HAL_LM3S_GPTIM_ICR_RTCCINT         BIT_(3)
+#define CYGHWR_HAL_LM3S_GPTIM_ICR_TBTOCINT        BIT_(8)
+#define CYGHWR_HAL_LM3S_GPTIM_ICR_CBMCINT         BIT_(9)
+#define CYGHWR_HAL_LM3S_GPTIM_ICR_CBECINT         BIT_(10)
+
+cyg_uint32 hal_lm3s_timer_clock( void );
+
+#ifndef __ASSEMBLER__
+
+__externC cyg_uint32 hal_stellaris_lm3s_timer_clock( CYG_ADDRESS base );
+
+#endif
+
+
+//=============================================================================
+// I2C register definitions.
+
+#ifdef CYGHWR_HAL_LM3S_I2C_CHAN
+
+#define CYGHWR_HAL_LM3S_I2C_MSA                   0x000
+#define CYGHWR_HAL_LM3S_I2C_MCS                   0x004
+#define CYGHWR_HAL_LM3S_I2C_MDR                   0x008
+#define CYGHWR_HAL_LM3S_I2C_MTPR                  0x00c
+#define CYGHWR_HAL_LM3S_I2C_MIMR                  0x010
+#define CYGHWR_HAL_LM3S_I2C_MRIS                  0x014
+#define CYGHWR_HAL_LM3S_I2C_MMIS                  0x018
+#define CYGHWR_HAL_LM3S_I2C_MICR                  0x01c
+#define CYGHWR_HAL_LM3S_I2C_MCR                   0x020
+
+#define CYGHWR_HAL_LM3S_I2C_SOAR                  0x000
+#define CYGHWR_HAL_LM3S_I2C_SCSR                  0x004
+#define CYGHWR_HAL_LM3S_I2C_SDR                   0x008
+#define CYGHWR_HAL_LM3S_I2C_SIMR                  0x00c
+#define CYGHWR_HAL_LM3S_I2C_SRIS                  0x010
+#define CYGHWR_HAL_LM3S_I2C_SMIS                  0x014
+#define CYGHWR_HAL_LM3S_I2C_SICR                  0x018
+
+// MSA bits
+#define CYGHWR_HAL_LM3S_I2C_MSA_RS                BIT_(0)
+#define CYGHWR_HAL_LM3S_I2C_MSA_SA(__x)           VALUE_(1, __x)
+
+// MCS bits
+#define CYGHWR_HAL_LM3S_I2C_MCS_BUSY              BIT_(0)
+#define CYGHWR_HAL_LM3S_I2C_MCS_ERR               BIT_(1)
+#define CYGHWR_HAL_LM3S_I2C_MCS_ADRACK            BIT_(2)
+#define CYGHWR_HAL_LM3S_I2C_MCS_DATACK            BIT_(3)
+#define CYGHWR_HAL_LM3S_I2C_MCS_ARBLST            BIT_(4)
+#define CYGHWR_HAL_LM3S_I2C_MCS_IDLE              BIT_(5)
+#define CYGHWR_HAL_LM3S_I2C_MCS_BUSBSY            BIT_(6)
+
+#define CYGHWR_HAL_LM3S_I2C_MCS_RUN               BIT_(0)
+#define CYGHWR_HAL_LM3S_I2C_MCS_START             BIT_(1)
+#define CYGHWR_HAL_LM3S_I2C_MCS_STOP              BIT_(2)
+#define CYGHWR_HAL_LM3S_I2C_MCS_ACK               BIT_(3)
+
+// MIMR bits
+#define CYGHWR_HAL_LM3S_I2C_MIMR_IM               BIT_(0)
+
+// MRIS bits
+#define CYGHWR_HAL_LM3S_I2C_MRIS_RIS              BIT_(0)
+
+// MMIS bits
+#define CYGHWR_HAL_LM3S_I2C_MMIS_MIS              BIT_(0)
+
+// MICR bits
+#define CYGHWR_HAL_LM3S_I2C_MICR_IC               BIT_(0)
+
+// MCR bits
+#define CYGHWR_HAL_LM3S_I2C_MCR_LPBK              BIT_(0)
+#define CYGHWR_HAL_LM3S_I2C_MCR_MFE               BIT_(4)
+#define CYGHWR_HAL_LM3S_I2C_MCR_SFE               BIT_(5)
+
+// SCSR bits
+#define CYGHWR_HAL_LM3S_I2C_SCSR_READ_RREQ        BIT_(0)
+#define CYGHWR_HAL_LM3S_I2C_SCSR_READ_TREQ        BIT_(1)
+#define CYGHWR_HAL_LM3S_I2C_SCSR_READ_FBR         BIT_(2)
+
+#define CYGHWR_HAL_LM3S_I2C_SCSR_WRITE_DA         BIT_(0)
+
+// SIMR bits
+#define CYGHWR_HAL_LM3S_I2C_SIMR_DATAIM           BIT_(0)
+
+// SRIS bits
+#define CYGHWR_HAL_LM3S_I2C_SRIS_DATARIS          BIT_(0)
+
+// SMIS bits
+#define CYGHWR_HAL_LM3S_I2C_SMIS_DATAMIS          BIT_(0)
+
+// SICR bits
+#define CYGHWR_HAL_LM3S_I2C_SICR_DATAMIC          BIT_(0)
+
+__externC cyg_uint32 hal_lm3s_i2c_clock( void );
+
+#endif // CYGHWR_HAL_LM3S_I2C_CHAN
+
+
+//=============================================================================
+// AC register definitions.
+
+#ifdef CYGHWR_HAL_LM3S_AC_CHAN
+
+#define CYGHWR_HAL_LM3S_AC_MIS                    0x000
+#define CYGHWR_HAL_LM3S_AC_RIS                    0x004
+#define CYGHWR_HAL_LM3S_AC_INTEN                  0x008
+#define CYGHWR_HAL_LM3S_AC_REFCTL                 0x010
+#define CYGHWR_HAL_LM3S_AC_STAT0                  0x020
+#define CYGHWR_HAL_LM3S_AC_CTL0                   0x024
+#define CYGHWR_HAL_LM3S_AC_STAT1                  0x040
+#define CYGHWR_HAL_LM3S_AC_CTL1                   0x044
+#define CYGHWR_HAL_LM3S_AC_STAT2                  0x060
+#define CYGHWR_HAL_LM3S_AC_CTL2                   0x064
+
+// MIS bits
+#define CYGHWR_HAL_LM3S_AC_MIS_IN0                BIT_(0)
+#define CYGHWR_HAL_LM3S_AC_MIS_IN1                BIT_(1)
+#define CYGHWR_HAL_LM3S_AC_MIS_IN2                BIT_(2)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_AC_RIS_IN0                BIT_(0)
+#define CYGHWR_HAL_LM3S_AC_RIS_IN1                BIT_(1)
+#define CYGHWR_HAL_LM3S_AC_RIS_IN2                BIT_(2)
+
+// INTEN bits
+#define CYGHWR_HAL_LM3S_AC_INTEN_IN0              BIT_(0)
+#define CYGHWR_HAL_LM3S_AC_INTEN_IN1              BIT_(1)
+#define CYGHWR_HAL_LM3S_AC_INTEN_IN2              BIT_(2)
+
+// REFCTL bits
+#define CYGHWR_HAL_LM3S_AC_REFCTL_RNG             BIT_(8)
+#define CYGHWR_HAL_LM3S_AC_REFCTL_EN              BIT_(9)
+
+// STAT0, STAT1 and STAT2 bits
+#define CYGHWR_HAL_LM3S_AC_STATx_OVAL             BIT_(1)
+
+// CTL0, CTL1 anf CTL2 bits
+#define CYGHWR_HAL_LM3S_AC_CTLx_CINV              BIT_(1)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ISEN_LEV_SENSE    VALUE_(2, 0x0)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ISEN_FALL_EDGE    VALUE_(2, 0x1)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ISEN_RISE_EDGE    VALUE_(2, 0x2)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ISEN_BOTH_EDGE    VALUE_(2, 0x3)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ISLVAL            BIT_(4)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ASRCP_PIN_VAL     VALUE_(9, 0x0)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ASRCP_PIN_VAL_C0  VALUE_(9, 0x1)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ASRCP_IVOLTREF    VALUE_(9, 0x2)
+
+#endif // CYGHWR_HAL_LM3S_AC_CHAN
+
+
+//=============================================================================
+// QEI register definitions.
+
+#ifdef CYGHWR_HAL_LM3S_QEI_CHAN
+
+#define CYGHWR_HAL_LM3S_QEI_CTL                   0x000
+#define CYGHWR_HAL_LM3S_QEI_STAT                  0x004
+#define CYGHWR_HAL_LM3S_QEI_POS                   0x008
+#define CYGHWR_HAL_LM3S_QEI_MAXPOS                0x00c
+#define CYGHWR_HAL_LM3S_QEI_LOAD                  0x010
+#define CYGHWR_HAL_LM3S_QEI_TIME                  0x014
+#define CYGHWR_HAL_LM3S_QEI_COUNT                 0x018
+#define CYGHWR_HAL_LM3S_QEI_SPEED                 0x01c
+#define CYGHWR_HAL_LM3S_QEI_INTEN                 0x020
+#define CYGHWR_HAL_LM3S_QEI_RIS                   0x024
+#define CYGHWR_HAL_LM3S_QEI_ISC                   0x028
+
+// CTL bits
+#define CYGHWR_HAL_LM3S_QEI_CTL_EN                BIT_(0)
+#define CYGHWR_HAL_LM3S_QEI_CTL_SWAP              BIT_(1)
+#define CYGHWR_HAL_LM3S_QEI_CTL_SIGMODE           BIT_(2)
+#define CYGHWR_HAL_LM3S_QEI_CTL_CAPMODE           BIT_(3)
+#define CYGHWR_HAL_LM3S_QEI_CTL_RESMODE           BIT_(4)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELEN             BIT_(5)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_1          VALUE_(6, 0x0)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_2          VALUE_(6, 0x1)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_4          VALUE_(6, 0x2)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_8          VALUE_(6, 0x3)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_16         VALUE_(6, 0x4)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_32         VALUE_(6, 0x5)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_64         VALUE_(6, 0x6)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_128        VALUE_(6, 0x7)
+#define CYGHWR_HAL_LM3S_QEI_CTL_INVA              BIT_(9)
+#define CYGHWR_HAL_LM3S_QEI_CTL_INVB              BIT_(10)
+#define CYGHWR_HAL_LM3S_QEI_CTL_INVI              BIT_(11)
+#define CYGHWR_HAL_LM3S_QEI_CTL_SATLLEN           BIT_(12)
+
+// STAT bits
+#define CYGHWR_HAL_LM3S_QEI_STAT_ERR              BIT_(0)
+#define CYGHWR_HAL_LM3S_QEI_STAT_DIR              BIT_(1)
+
+// INTEN bits
+#define CYGHWR_HAL_LM3S_QEI_INTEN_INTINDEX        BIT_(0)
+#define CYGHWR_HAL_LM3S_QEI_INTEN_INTTIMER        BIT_(1)
+#define CYGHWR_HAL_LM3S_QEI_INTEN_INTDIR          BIT_(2)
+#define CYGHWR_HAL_LM3S_QEI_INTEN_INTERROR        BIT_(3)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_QEI_RIS_INTINDEX          BIT_(0)
+#define CYGHWR_HAL_LM3S_QEI_RIS_INTTIMER          BIT_(1)
+#define CYGHWR_HAL_LM3S_QEI_RIS_INTDIR            BIT_(2)
+#define CYGHWR_HAL_LM3S_QEI_RIS_INTERROR          BIT_(3)
+
+// ISC bits
+#define CYGHWR_HAL_LM3S_QEI_ISC_INTINDEX          BIT_(0)
+#define CYGHWR_HAL_LM3S_QEI_ISC_INTTIMER          BIT_(1)
+#define CYGHWR_HAL_LM3S_QEI_ISC_INTDIR            BIT_(2)
+#define CYGHWR_HAL_LM3S_QEI_ISC_INTERROR          BIT_(3)
+
+#endif // CYGHWR_HAL_LM3S_QEI_CHAN
+
+
+//=============================================================================
+// Flash controller
+
+#define CYGHWR_HAL_LM3S_FMC_FMA                   0x000
+#define CYGHWR_HAL_LM3S_FMC_FMD                   0x004
+#define CYGHWR_HAL_LM3S_FMC_FMC                   0x008
+#define CYGHWR_HAL_LM3S_FMC_FCRIS                 0x00c
+#define CYGHWR_HAL_LM3S_FMC_FCIM                  0x010
+#define CYGHWR_HAL_LM3S_FMC_FCMISC                0x014
+
+// Key value
+#define CYGHWR_HAL_LM3S_FMC_WRKEY                 0xA4420000
+
+// FMC bits
+#define CYGHWR_HAL_LM3S_FMC_FMC_WRITE             BIT_(0)
+#define CYGHWR_HAL_LM3S_FMC_FMC_ERASE             BIT_(1)
+#define CYGHWR_HAL_LM3S_FMC_FMC_MERASE            BIT_(2)
+#define CYGHWR_HAL_LM3S_FMC_FMC_COMT              BIT_(3)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_FMC_FCRIS_ARIS            BIT_(0)
+#define CYGHWR_HAL_LM3S_FMC_FCRIS_PRIS            BIT_(1)
+
+// IM bits
+#define CYGHWR_HAL_LM3S_FMC_FCIM_AMASK            BIT_(0)
+#define CYGHWR_HAL_LM3S_FMC_FCIM_PMASK            BIT_(1)
+
+// MISC bits
+#define CYGHWR_HAL_LM3S_FMC_FCMISC_AMASK          BIT_(0)
+#define CYGHWR_HAL_LM3S_FMC_FCMISC_PMASK          BIT_(0)
+
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_IO_H
+// EOF of var_io.h
diff --git a/packages/hal/cortexm/lm3s/var/current/include/variant.inc b/packages/hal/cortexm/lm3s/var/current/include/variant.inc
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/var/current/include/variant.inc
@@ -0,0 +1,54 @@
+/*==========================================================================
+//
+//      variant.inc
+//
+//      Variant specific asm definitions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Date:         2010-11-23
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal_cortexm_lm3s.h>
+
+//==========================================================================
+// EOF variant.inc
+
diff --git a/packages/hal/cortexm/lm3s/var/current/src/hal_diag.c b/packages/hal/cortexm/lm3s/var/current/src/hal_diag.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/var/current/src/hal_diag.c
@@ -0,0 +1,406 @@
+//=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008, 2010
+// 2011, Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   original: nickg, ccoutand: updated for Stellaris HAL
+// Date:        2011-01-18
+// Purpose:     HAL diagnostic output
+// Description: Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>        // Base types
+#include <cyg/infra/cyg_trac.h>        // Tracing
+
+#include <cyg/hal/hal_arch.h>          // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h>            // IO macros
+#include <cyg/hal/hal_if.h>            // interface API
+#include <cyg/hal/hal_intr.h>          // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h>          // Helper functions
+#include <cyg/hal/drv_api.h>           // CYG_ISR_HANDLED
+
+#include <cyg/hal/var_io.h>            // USART registers
+
+//-----------------------------------------------------------------------------
+typedef struct {
+    cyg_uint32      uart;
+    CYG_ADDRESS     base;
+    cyg_int32       msec_timeout;
+    int             isr_vector;
+    cyg_uint32      rxpin;
+    cyg_uint32      txpin;
+    cyg_uint32      baud_rate;
+    int             irq_state;
+} channel_data_t;
+
+static channel_data_t lm3s_ser_channels[] = {
+#if CYGINT_HAL_CORTEXM_LM3S_UART0>0
+    {0, CYGHWR_HAL_LM3S_UART0, 1000, CYGNUM_HAL_INTERRUPT_UART0,
+     CYGHWR_HAL_LM3S_UART0_RX, CYGHWR_HAL_LM3S_UART0_TX},
+#endif
+#if CYGINT_HAL_CORTEXM_LM3S_UART1>0
+    {1, CYGHWR_HAL_LM3S_UART1, 1000, CYGNUM_HAL_INTERRUPT_UART1,
+     CYGHWR_HAL_LM3S_UART1_RX, CYGHWR_HAL_LM3S_UART1_TX},
+#endif
+};
+
+//-----------------------------------------------------------------------------
+
+static void
+hal_lm3s_serial_init_channel(void *__ch_data)
+{
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    CYG_ADDRESS     base = chan->base;
+    cyg_uint32      lcrh,
+                    ctl;
+
+    // Disable UART
+    HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_CTL, ctl);
+    ctl &= ~(CYGHWR_HAL_LM3S_UART_CTL_UARTEN |
+             CYGHWR_HAL_LM3S_UART_CTL_TXE | CYGHWR_HAL_LM3S_UART_CTL_RXE);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_CTL, ctl);
+
+    // Enable the PIO lines for the serial channel
+    CYGHWR_HAL_LM3S_GPIO_SET(chan->rxpin);
+    CYGHWR_HAL_LM3S_GPIO_SET(chan->txpin);
+
+    // Set up Baud rate
+    chan->baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD;
+    hal_lm3s_uart_setbaud(base, chan->baud_rate);
+
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_FR, 0);
+
+    // 8 bits - 1 stop - Enable FIFO
+    lcrh = CYGHWR_HAL_LM3S_UART_LCRH_WLEN(3) | CYGHWR_HAL_LM3S_UART_LCRH_FEN;
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_LCRH, lcrh);
+
+    // Enable the UART
+    ctl = (CYGHWR_HAL_LM3S_UART_CTL_UARTEN |
+           CYGHWR_HAL_LM3S_UART_CTL_TXE | CYGHWR_HAL_LM3S_UART_CTL_RXE);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_CTL, ctl);
+}
+
+void
+hal_lm3s_serial_putc(void *__ch_data, char c)
+{
+    CYG_ADDRESS     base = ((channel_data_t *) __ch_data)->base;
+    cyg_uint32      sr;
+
+    CYGARC_HAL_SAVE_GP();
+
+    do {
+        HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_FR, sr);
+    } while ((sr & CYGHWR_HAL_LM3S_UART_FR_TXFE) == 0);
+
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_DR, c);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool
+hal_lm3s_serial_getc_nonblock(void *__ch_data, cyg_uint8 *ch)
+{
+    CYG_ADDRESS     base = ((channel_data_t *) __ch_data)->base;
+    cyg_uint32      fr;
+    cyg_uint32      c;
+
+    CYGARC_HAL_SAVE_GP();
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_FR, fr);
+
+    if ((fr & CYGHWR_HAL_LM3S_UART_FR_RXFE))
+        return false;
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_DR, c);
+
+    *ch = (cyg_uint8)c;
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return true;
+}
+
+cyg_uint8
+hal_lm3s_serial_getc(void *__ch_data)
+{
+    cyg_uint8       ch;
+
+    CYGARC_HAL_SAVE_GP();
+
+    while (!hal_lm3s_serial_getc_nonblock(__ch_data, &ch))
+        continue;
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return ch;
+}
+
+//=============================================================================
+// Virtual vector HAL diagnostics
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+static void
+hal_lm3s_serial_write(void *__ch_data, const cyg_uint8 *__buf,
+                      cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while (__len-- > 0)
+        hal_lm3s_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+hal_lm3s_serial_read(void *__ch_data, cyg_uint8 *__buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while (__len-- > 0)
+        *__buf++ = hal_lm3s_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool
+hal_lm3s_serial_getc_timeout(void *__ch_data, cyg_uint8 *ch)
+{
+    int             delay_count;
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    cyg_bool        res;
+
+    CYGARC_HAL_SAVE_GP();
+
+    delay_count = chan->msec_timeout * 100;     // delay in 10 us steps
+
+    for (;;) {
+        res = hal_lm3s_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+
+        CYGACC_CALL_IF_DELAY_US(10);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return res;
+}
+
+static int
+hal_lm3s_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    CYG_ADDRESS     base = ((channel_data_t *) __ch_data)->base;
+    int             ret = 0;
+    cyg_uint32      im;
+
+    va_list         ap;
+
+    CYGARC_HAL_SAVE_GP();
+
+    va_start(ap, __func);
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        chan->irq_state = 1;
+        HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+        HAL_INTERRUPT_UNMASK(chan->isr_vector);
+        HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_IM, im);
+        im |= CYGHWR_HAL_LM3S_UART_IM_RXIM;
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_IM, im);
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = chan->irq_state;
+        chan->irq_state = 0;
+        HAL_INTERRUPT_MASK(chan->isr_vector);
+        HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_IM, im);
+        im &= ~CYGHWR_HAL_LM3S_UART_IM_RXIM;
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_IM, im);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+        {
+            va_list         ap;
+
+            va_start(ap, __func);
+
+            ret = chan->msec_timeout;
+            chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+            va_end(ap);
+        }
+    case __COMMCTL_GETBAUD:
+        ret = chan->baud_rate;
+        break;
+    case __COMMCTL_SETBAUD:
+        chan->baud_rate = va_arg(ap, cyg_int32);
+        // Should we verify this value here?
+        hal_lm3s_uart_setbaud(base, chan->baud_rate);
+        ret = 0;
+        break;
+    default:
+        break;
+    }
+
+    va_end(ap);
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return ret;
+}
+
+static int
+hal_lm3s_serial_isr(void *__ch_data, int *__ctrlc,
+                    CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    cyg_uint8       ch;
+
+    CYGARC_HAL_SAVE_GP();
+
+    *__ctrlc = 0;
+
+    if (hal_lm3s_serial_getc_nonblock(__ch_data, &ch)) {
+        if (cyg_hal_is_break((char *)&ch, 1))
+            *__ctrlc = 1;
+    }
+
+    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return 1;
+}
+
+static void
+hal_lm3s_serial_init(void)
+{
+    hal_virtual_comm_table_t *comm;
+    int             cur;
+    int             i;
+
+    cur =
+        CYGACC_CALL_IF_SET_CONSOLE_COMM
+        (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    for (i = 0; i < CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS; i++) {
+        hal_lm3s_serial_init_channel(&lm3s_ser_channels[i]);
+
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+        comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+        CYGACC_COMM_IF_CH_DATA_SET(*comm, &lm3s_ser_channels[i]);
+        CYGACC_COMM_IF_WRITE_SET(*comm, hal_lm3s_serial_write);
+        CYGACC_COMM_IF_READ_SET(*comm, hal_lm3s_serial_read);
+        CYGACC_COMM_IF_PUTC_SET(*comm, hal_lm3s_serial_putc);
+        CYGACC_COMM_IF_GETC_SET(*comm, hal_lm3s_serial_getc);
+        CYGACC_COMM_IF_CONTROL_SET(*comm, hal_lm3s_serial_control);
+        CYGACC_COMM_IF_DBG_ISR_SET(*comm, hal_lm3s_serial_isr);
+        CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, hal_lm3s_serial_getc_timeout);
+    }
+
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+
+# if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD)
+    // Set debug channel baud rate if different
+    lm3s_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate =
+        CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD;
+    update_baud_rate(&lm3s_ser_channels
+                     [CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]);
+# endif
+
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int      initialized = 0;
+
+    if (initialized)
+        return;
+
+    initialized = 1;
+
+    hal_lm3s_serial_init();
+}
+
+#endif // ifdef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+
+//=============================================================================
+// Non-Virtual vector HAL diagnostics
+
+#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+void
+hal_lm3s_diag_init(void)
+{
+    hal_lm3s_serial_init(&lm3s_ser_channels
+                         [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL]);
+}
+
+void
+hal_lm3s_diag_putc(char c)
+{
+    hal_lm3s_serial_putc(&lm3s_ser_channels
+                         [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c);
+}
+
+cyg_uint8
+hal_lm3s_diag_getc(void)
+{
+    return
+        hal_lm3s_serial_getc(&lm3s_ser_channels
+                             [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL]);
+}
+
+#endif // ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+//-----------------------------------------------------------------------------
+// EOF hal_diag.c
diff --git a/packages/hal/cortexm/lm3s/var/current/src/lm3s_misc.c b/packages/hal/cortexm/lm3s/var/current/src/lm3s_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lm3s/var/current/src/lm3s_misc.c
@@ -0,0 +1,328 @@
+//==========================================================================
+//
+//      lm3s_misc.c
+//
+//      Stellaris Cortex-M3 variant HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Date:         2011-01-18
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+
+#ifdef CYGPKG_KERNEL
+# include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>        // Tracing macros
+#include <cyg/infra/cyg_ass.h>         // Assertion macros
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_if.h>
+
+//==========================================================================
+// Initialization
+//
+__externC void  hal_start_clocks(void);
+
+// Clock computation must be done per Variant basis
+cyg_uint32      hal_cortexm_systick_clock;
+cyg_uint32      hal_lm3s_sysclk;
+
+
+void
+hal_variant_init(void)
+{
+#if !defined(CYG_HAL_STARTUP_RAM)
+    hal_start_clocks();
+#endif
+
+    // All LM3S devices use PORTA 0/1 for UART0
+#if CYGINT_HAL_CORTEXM_LM3S_UART0>0
+    CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART0, 1);
+    CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART0_GPIO, 1);
+#endif
+
+#if CYGINT_HAL_CORTEXM_LM3S_UART1>0
+
+# ifdef CYGHWR_HAL_LM3S_P_UART1_GPIO
+    CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART1, 1);
+    CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART1_GPIO, 1);
+# else
+#  error "Variant/Platform does not specify UART1 GPIO Port"
+# endif
+
+#endif
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    hal_if_init();
+#endif
+}
+
+//==========================================================================
+// GPIO support
+//
+// These functions provide configuration and IO for GPIO pins.
+//
+
+__externC void
+hal_lm3s_gpio_set(cyg_uint32 pin)
+{
+    cyg_uint32      port = CYGHWR_HAL_LM3S_GPIO_PORT(pin);
+    cyg_uint32      bit = (1 << CYGHWR_HAL_LM3S_GPIO_BIT(pin));
+    cyg_uint32      cm = CYGHWR_HAL_LM3S_GPIO_CFG(pin);
+    cyg_uint32      mode = CYGHWR_HAL_LM3S_GPIO_MODE(pin);
+    cyg_uint32      irq = CYGHWR_HAL_LM3S_GPIO_IRQ(pin);
+    cyg_uint32      st = CYGHWR_HAL_LM3S_GPIO_STRENGTH(pin);
+    cyg_uint32      reg,
+                    dir,
+                    im,
+                    dr2r,
+                    dr4r,
+                    dr8r;
+
+    if (pin == CYGHWR_HAL_LM3S_GPIO_NONE)
+        return;
+
+    /*
+     *  Handle IO mode settings
+     */
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_AFSEL, reg);
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DIR, dir);
+
+    HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_AFSEL, (reg & ~(bit)));
+    if (mode == CYGHWR_HAL_LM3S_GPIO_MODE_IN)
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DIR, (dir & ~(bit)));
+    else if (mode == CYGHWR_HAL_LM3S_GPIO_MODE_OUT)
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DIR, (dir | bit));
+    else
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_AFSEL, (reg | bit));
+
+    /*
+     *  Handle IO configuration
+     */
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_ODR, reg);
+    if (cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP ||
+        cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLUP ||
+        cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLDOWN) {
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_ODR, (reg | bit));
+    } else
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_ODR, (reg & ~(bit)));
+
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PUR, reg);
+    if (cm == CYGHWR_HAL_LM3S_GPIO_CNF_PULLUP ||
+        cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLUP) {
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PUR, (reg | bit));
+    } else
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PUR, (reg & ~(bit)));
+
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PDR, reg);
+    if (cm == CYGHWR_HAL_LM3S_GPIO_CNF_PULLDOWN ||
+        cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLDOWN) {
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PDR, (reg | bit));
+    } else
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PDR, (reg & ~(bit)));
+
+    /*
+     *  Handle IO strength
+     */
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, dr2r);
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, dr4r);
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, dr8r);
+    if (st == CYGHWR_HAL_LM3S_GPIO_STRENGTH_2_MA) {
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, (dr4r & ~(bit)));
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, (dr8r & ~(bit)));
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, (dr2r | bit));
+    } else if (st == CYGHWR_HAL_LM3S_GPIO_STRENGTH_4_MA) {
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, (dr2r & ~(bit)));
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, (dr8r & ~(bit)));
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, (dr4r | bit));
+    } else if (st == CYGHWR_HAL_LM3S_GPIO_STRENGTH_8_MA) {
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, (dr2r & ~(bit)));
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, (dr4r & ~(bit)));
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, (dr8r | bit));
+    }
+
+    /*
+     *  Handle interrupt settings
+     */
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IM, im);
+    HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IM, (im & ~(bit)));
+    if (irq != CYGHWR_HAL_LM3S_GPIO_IRQ_DISABLE) {
+        HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IS, reg);
+
+        if (irq == CYGHWR_HAL_LM3S_GPIO_IRQ_LOW_LEVEL ||
+            irq == CYGHWR_HAL_LM3S_GPIO_IRQ_HIGH_LEVEL)
+            HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IS, (reg | bit));
+        else
+            HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IS, (reg & ~(bit)));
+
+        HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IBE, reg);
+        if (irq == CYGHWR_HAL_LM3S_GPIO_IRQ_BOTH_EDGES) {
+            HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IBE, (reg | bit));
+        } else {
+            HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IBE, (reg & ~(bit)));
+
+            HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IEV, reg);
+            if (irq == CYGHWR_HAL_LM3S_GPIO_IRQ_LOW_LEVEL ||
+                irq == CYGHWR_HAL_LM3S_GPIO_IRQ_FALLING_EDGE)
+                HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IEV,
+                                 (reg & ~(bit)));
+            else
+                HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IEV,
+                                 (reg | bit));
+        }
+
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IM, (im | bit));
+    }
+}
+
+__externC void
+hal_lm3s_gpio_out(cyg_uint32 pin, int val)
+{
+    cyg_uint32      port = CYGHWR_HAL_LM3S_GPIO_PORT(pin);
+    int             bit = (1 << CYGHWR_HAL_LM3S_GPIO_BIT(pin));
+
+    port += (CYGHWR_HAL_LM3S_GPIO_DATA + (bit << 2));
+
+    HAL_WRITE_UINT32(port, (val ? bit : 0));
+}
+
+__externC void
+hal_lm3s_gpio_in(cyg_uint32 pin, int *val)
+{
+    cyg_uint32      port = CYGHWR_HAL_LM3S_GPIO_PORT(pin);
+    int             bit = (1 << CYGHWR_HAL_LM3S_GPIO_BIT(pin));
+    cyg_uint32      pd;
+
+    port += (CYGHWR_HAL_LM3S_GPIO_DATA + (bit << 2));
+
+    HAL_READ_UINT32(port, pd);
+    *val = pd;
+}
+
+
+//==========================================================================
+// Peripheral support
+//
+
+__externC void
+hal_lm3s_periph_set(cyg_uint32 periph, cyg_uint32 on_off)
+{
+    cyg_uint32      reg;
+
+    if (CYGHWR_HAL_LM3S_PERIPH_GC0 & periph) {
+        HAL_READ_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC0, reg);
+        if (on_off)
+            reg |= (periph & ~CYGHWR_HAL_LM3S_PERIPH_GC0);
+        else
+            reg &= ~(periph & ~CYGHWR_HAL_LM3S_PERIPH_GC0);
+        HAL_WRITE_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC0, reg);
+    }
+
+    if (CYGHWR_HAL_LM3S_PERIPH_GC1 & periph) {
+        HAL_READ_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC1, reg);
+        if (on_off)
+            reg |= (periph & ~CYGHWR_HAL_LM3S_PERIPH_GC1);
+        else
+            reg &= ~(periph & ~CYGHWR_HAL_LM3S_PERIPH_GC1);
+        HAL_WRITE_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC1, reg);
+    }
+
+    if (CYGHWR_HAL_LM3S_PERIPH_GC2 & periph) {
+        HAL_READ_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC2, reg);
+        if (on_off)
+            reg |= (periph & ~CYGHWR_HAL_LM3S_PERIPH_GC2);
+        else
+            reg &= ~(periph & ~CYGHWR_HAL_LM3S_PERIPH_GC2);
+        HAL_WRITE_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC2, reg);
+    }
+
+}
+
+
+//==========================================================================
+// UART baud rate
+//
+// Set the baud rate divider of a UART based on the requested rate and
+// the current APB clock settings.
+//
+
+__externC void
+hal_lm3s_uart_setbaud(cyg_uint32 base, cyg_uint32 baud)
+{
+    cyg_uint32      int_div,
+                    frac_div;
+
+    int_div = ((((hal_cortexm_systick_clock << 3) / baud) + 1) >> 1);
+
+    frac_div = int_div % 64;
+    int_div = int_div >> 6;
+
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_IBRD, int_div);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_FBRD, frac_div);
+}
+
+
+//==========================================================================
+// I2C clock rate
+//
+__externC cyg_uint32
+hal_lm3s_i2c_clock(void)
+{
+    return hal_lm3s_sysclk;
+}
+
+//==========================================================================
+// Timer clock rate
+//
+__externC cyg_uint32
+hal_lm3s_timer_clock(void)
+{
+    return hal_lm3s_sysclk;
+}
+
+//==========================================================================
+// EOF lm3s_misc_misc.c
diff --git a/packages/hal/cortexm/lpc17xx/lpc1766stk/current/ChangeLog b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/ChangeLog
@@ -0,0 +1,43 @@
+2012-01-16  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx_lpc1766stk.cdl:
+	* include/pkgconf/mlt_cortexm_lpc1766_rom.h:
+	* include/pkgconf/mlt_cortexm_lpc1766_rom.ldi:
+	Recognize In Application Programming (IAP) SRAM field
+	and Valid User Code and Code Read Protection FLASH fields
+	Reported by Bernard Fouché [ Bugzilla 1001395 ] [Bugzilla 1001443 ]
+
+2010-12-12  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx_lpc1766stk.cdl:
+	* include/pkgconf/mlt_cortexm_lpc1766_rom.h:
+	* include/pkgconf/mlt_cortexm_lpc1766_rom.ldi:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* src/lpc1766stk_misc.c:
+	New package -- Olimex LPC1766STK board.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/hal/cortexm/lpc17xx/lpc1766stk/current/cdl/hal_cortexm_lpc17xx_lpc1766stk.cdl b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/cdl/hal_cortexm_lpc17xx_lpc1766stk.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/cdl/hal_cortexm_lpc17xx_lpc1766stk.cdl
@@ -0,0 +1,416 @@
+##==========================================================================
+##
+##      hal_cortexm_lpc17xx_lpc1766stk.cdl
+##
+##      Cortex-M Olimex LPC-1766STK platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ilijak
+## Date:         2010-12-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_LPC17XX_LPC1766STK {
+    display       "Olimex LPC-1700STK Board HAL"
+    parent        CYGPKG_HAL_CORTEXM_LPC17XX
+    define_header hal_cortexm_lpc17xx_lpc1766stk.h
+    include_dir   cyg/hal
+    hardware
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+    implements    CYGINT_IO_SERIAL_LPC24XX_UART0
+    implements    CYGINT_IO_SERIAL_LPC24XX_UART1
+
+    description   "
+        The Olimex LPC-1766STK HAL package provides the support needed
+        to run eCos on the LPC-1766STK board. Also this package can be
+        used for other boards that employ a controller from LPC 176x
+        or LPC 175x families. Use 'LPC17xx member in use' to pick up
+        your device."
+
+    compile       lpc1766stk_misc.c
+
+    requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
+                   (1 == CYGHWR_DEVS_ETH_PHY_KS8721) }
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_lpc17xx.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_lpc17xx_lpc1766stk.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M3\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Olimex LPC-1766STK\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value { "ROM" }
+        legal_values  { "ROM" }
+        no_define
+        define -file system.h CYG_HAL_STARTUP
+        description   "
+            'ROM' startup builds a stand-alone application which will
+            be put into internal flash."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_IAP {
+        display "Reserve RAM for IAP (Bytes)"
+        flavor data
+        legal_values { 0 32 }
+        default_value 32
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display       "Memory layout"
+        flavor        data
+        no_define
+        calculated    { (CYG_HAL_STARTUP == "ROM" ) ? "cortexm_lpc" . CYGHWR_HAL_CORTEXM_LPC17XX  . "_rom" :
+                        "undefined" }
+        description   "
+            Combination of 'Startup type' and 'LPC17xx member in use'
+            produces the memory layout."
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display       "Memory layout linker script fragment"
+            flavor        data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated   { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display       "Memory layout header file"
+            flavor        data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated    { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ {
+        display       "CPU xtal frequency"
+        parent        CYGHWR_HAL_CORTEXM_LPC17XX_CLOCKING
+        flavor        data
+        default_value { 12000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_MAX_CLOCK_SPEED {
+        display       "Max. CPU clock speed"
+        parent        CYGHWR_HAL_CORTEXM_LPC17XX_CLOCKING
+        flavor        data
+        calculated    { (CYGHWR_HAL_CORTEXM_LPC17XX == "1759") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1769") ?  120000000 :
+            100000000 }
+        requires      { CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <=
+            ((CYGHWR_HAL_CORTEXM_LPC17XX == "1759") ||
+             (CYGHWR_HAL_CORTEXM_LPC17XX == "1769") ?  120000000 :
+             100000000) }
+        description   "
+            Highest internal core frequency is dependent on selected
+            chip. "
+    }
+
+    # Both UARTs 0 and 1 are available for diagnostic/debug use.
+    implements CYGINT_HAL_LPC17XX_UART0
+    implements CYGINT_HAL_LPC17XX_UART1
+
+    implements      CYGINT_IO_SERIAL_FLOW_CONTROL_HW
+    implements      CYGINT_IO_SERIAL_LINE_STATUS_HW
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display       "Number of communication channels on the board"
+        flavor        data
+        calculated    2
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display       "Debug serial port"
+        active_if     CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor        data
+        legal_values  0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value 0
+        description   "
+            The Olimex LPC1766STK board has two serial ports. This
+            option chooses which port will be used to connect to a host
+            running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display       "Diagnostic serial port"
+        active_if     CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor        data
+        legal_values  0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value 0
+        description   "
+            The Olimex LPC1766STK has two serial ports. This option
+            chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            Note: this should match the value chosen for the GDB port
+            if the diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console
+            port if the console and GDB port are the same."
+    }
+
+    cdl_component CYGHWR_HAL_LPC_EMAC_RAM_AHB {
+        display       "Ethernet controller AHB SRAM"
+        flavor        none
+        active_if     CYGPKG_DEVS_ETH_ARM_LPC2XXX
+        parent        CYGPKG_DEVS_ETH_ARM_LPC2XXX
+        description   "
+            AHB SRAM allocated for Ethernet controller."
+
+        cdl_option CYGHWR_HAL_LPC_EMAC_MEM_SECTION {
+            display       "Memory section for lwIP buffers."
+            flavor        data
+            default_value { "\".ahb_sram0\"" }
+            legal_values  { "\".ahb_sram0\"" "\".ahb_sram1\"" }
+            description   "
+                Select special section for lwIP p-buffers and heap and
+                provide section name."
+        }
+
+        cdl_option CYGHWR_HAL_LPC_EMAC_BLOCK_SIZE {
+            display       "Block size"
+            flavor        data
+            default_value 0x600
+        }
+    }
+
+    cdl_option CYGDAT_LWIP_MEM_SECTION_NAME {
+        display       "Memory section for lwIP buffers."
+        flavor        data
+        default_value { "\".ahb_sram0\"" }
+        legal_values  { "\".ahb_sram0\"" "\".ahb_sram1\"" }
+        active_if     CYGPKG_NET_LWIP
+        parent        CYGOPT_LWIP_MEM_PLF_SPEC
+        description   "
+            Select special section for lwIP p-buffers and heap and
+            provide section name."
+    }
+
+    cdl_component CYGOPT_LWIP_PLF_MEM_OPT {
+        display       "Platform related lwIP memory constrains"
+        flavor        none
+        no_define
+        active_if     CYGPKG_NET_LWIP
+        parent        CYGOPT_LWIP_MEM_PLF_SPEC
+        description   "
+            Some platform constrains, features and restrictions applied
+            to lwIP network stack."
+
+        cdl_option CYGOPT_LWIP_PLF_MEM_LIMIT_SS0 {
+            display       "lwIP uses the same section as the ethernet controller"
+            no_define
+            flavor        bool
+            default_value is_active(CYGOPT_LWIP_PLF_MEM_LIMIT_SS0)
+
+            active_if     CYGSEM_LWIP_MEM_SECTION
+            active_if     { CYGDAT_LWIP_MEM_SECTION_NAME == CYGHWR_HAL_LPC_EMAC_MEM_SECTION }
+
+            requires      { CYGNUM_LWIP_MEM_SIZE == 1544 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_PBUF ==  4 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB == 6 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB_LISTEN == 2 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_ARP_QUEUE == 5 }
+            requires      { CYGNUM_LWIP_PBUF_POOL_SIZE == 8 }
+
+            requires      { CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS == 3 }
+        }
+
+        cdl_option CYGOPT_LWIP_PLF_MEM_LIMIT_SS1 {
+            display       "lwIP uses different section than the ethernet controller"
+            no_define
+            flavor        bool
+            default_value is_active(CYGOPT_LWIP_PLF_MEM_LIMIT_SS1)
+
+            active_if     CYGSEM_LWIP_MEM_SECTION
+            active_if     { CYGDAT_LWIP_MEM_SECTION_NAME != CYGHWR_HAL_LPC_EMAC_MEM_SECTION }
+
+            requires      { CYGNUM_LWIP_MEM_SIZE == 1600 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_PBUF ==  9 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB == 8 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB_LISTEN == 4 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_ARP_QUEUE == 10 }
+            requires      { CYGNUM_LWIP_PBUF_POOL_SIZE == 13 }
+
+            requires      { CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS == 4 }
+        }
+
+        cdl_option CYGOPT_LWIP_PLF_MEM_LIMIT_NSS {
+            display       "lwIP does not use a special section"
+            no_define
+            flavor        bool
+            default_value is_active(CYGOPT_LWIP_PLF_MEM_LIMIT_NSS)
+
+            active_if     !CYGSEM_LWIP_MEM_SECTION
+
+            requires      { CYGNUM_KERNEL_THREADS_IDLE_STACK_SIZE == 1024 }
+
+            requires      { CYGNUM_LWIP_MEM_SIZE == 884 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_PBUF ==  4 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB == 5 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB_LISTEN == 2 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_ARP_QUEUE == 5 }
+            requires      { CYGNUM_LWIP_PBUF_POOL_SIZE == 7 }
+
+            requires { CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS == 4 }
+        }
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display       "Global build options"
+        flavor        none
+        parent        CYGPKG_NONE
+        description   "
+            Global build options including control over compiler flags,
+            linker flags and choice of toolchain."
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display       "Global command prefix"
+            flavor        data
+            no_define
+            default_value { "arm-eabi" }
+            description   "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display       "Global compiler flags"
+            flavor        data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which
+                are used to compile all packages by default. Individual
+                packages may define options which override these global
+                flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display       "Global linker flags"
+            flavor        data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global
+                flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a
+            ROM monitor, i.e. applications will be loaded into RAM on
+            the board, and this ROM monitor may process exceptions or
+            interrupts generated from the application. This enables
+            features such as utilizing a separate interrupt stack when
+            exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+            Support can be enabled for different varieties of ROM monitor.
+            This support changes various eCos semantics such as the
+            encoding of diagnostic output, or the overriding of hardware
+            interrupt vectors.
+            Firstly there is \"Generic\" support which prevents the HAL
+            from overriding the hardware vectors that it does not use, to
+            instead allow an installed ROM monitor to handle them. This
+            is the most basic support which is likely to be common to
+            most implementations of ROM monitor.
+            \"GDB_stubs\" provides support when GDB stubs are included
+            in the ROM monitor or boot ROM."
+    }
+
+    cdl_component CYGBLD_HAL_CORTEXM_LPC1766STK_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        no_define
+        calculated    1
+        active_if     CYGBLD_BUILD_COMMON_GDB_STUBS
+        requires      { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+
+        description   "
+            This component causes the ELF image generated by the build
+            process to be converted to S-Record and binary files."
+    }
+}
+
+# EOF hal_cortexm_lpc17xx_lpc1766stk.cdl
diff --git a/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.h b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.h
@@ -0,0 +1,30 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x10000000)
+#define CYGMEM_REGION_ram_SIZE (0x00008000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE-CYGHWR_HAL_CORTEXM_LPC17XX_IAP)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ahb_sram_bank0 (0x2007C000)
+#define CYGMEM_REGION_ahb_sram_bank0_SIZE (0x00004000)
+#define CYGMEM_REGION_ahb_sram_bank0_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ahb_sram_bank1 (0x20080000)
+#define CYGMEM_REGION_ahb_sram_bank1_SIZE (0x00004000)
+#define CYGMEM_REGION_ahb_sram_bank1_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (0x00040000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.ldi b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.ldi
@@ -0,0 +1,49 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram  : ORIGIN = 0x10000000, LENGTH = 0x00008000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE-CYGHWR_HAL_CORTEXM_LPC17XX_IAP
+    ahb_sram_bank0  : ORIGIN = 0x2007C000, LENGTH = 0x00004000
+    ahb_sram_bank1  : ORIGIN = 0x20080000, LENGTH = 0x00004000
+    flash : ORIGIN = 0x00000000, LENGTH = 0x00040000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(lpc17xx_misc, flash, 0x00000020, LMA_EQ_VMA)
+    
+    // LPC17xx Code Read Protection field. Must be present at 0x000002FC
+    // Warning: Code Read Protection field or moving it to
+    //          other location may lock LPC17xx controller.
+    // See src/lpc17xx_mis.c for definition
+
+    .lpc17xxcrp 0x2FC : { KEEP (*(.lpc17xxcrp)) } > flash
+    
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    USER_SECTION (ahb_sram0, ahb_sram_bank0, 0x2007C000 (NOLOAD), LMA_EQ_VMA)
+    USER_SECTION (ahb_sram1, ahb_sram_bank1, 0x20080000 (NOLOAD), LMA_EQ_VMA)
+    SECTION_data (ram, 0x10000400, FOLLOWING (.got))
+    SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x10000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x10000000 + 1024*32-CYGHWR_HAL_CORTEXM_LPC17XX_IAP;
+
+
diff --git a/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_arch.h b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_arch.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Contributor(s): ilijak
+// Date:        2010-12-29
+// Purpose:     LPC1766STK platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_lpc17xx_lpc1766stk.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_ARCH_H
+// End of plf_arch.h
diff --git a/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_intr.h b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_intr.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2010-12-29
+// Purpose:     LPC1766STK platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_lpc17xx_lpc1766stk.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_INTR_H
+// End of plf_intr.h
diff --git a/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_io.h b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_io.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_io.h
@@ -0,0 +1,92 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-01-02
+// Purpose:     LPC1766STK platform specific registers
+// Description: 
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_lpc17xx_lpc1766stk.h>
+
+#if (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 20000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM20MHZ)
+#elif (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 40000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM40MHZ)
+#elif (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 60000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM60MHZ)
+#elif (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 80000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM80MHZ)
+#elif (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 100000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM100MHZ)
+#elif (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 120000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM120MHZ)
+#else
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIMSAFE)
+#endif
+
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_IO_H
+// End of plf_io.h
diff --git a/packages/hal/cortexm/lpc17xx/lpc1766stk/current/src/lpc1766stk_misc.c b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/src/lpc1766stk_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/lpc1766stk/current/src/lpc1766stk_misc.c
@@ -0,0 +1,256 @@
+//==========================================================================
+//
+//      lpc1766stk_misc.c
+//
+//      Cortex-M3 LPC1766STK HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      nickg
+// Contributor(s): ilijak
+// Date:           2010-12-22
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_lpc17xx.h>
+#include <pkgconf/hal_cortexm_lpc17xx_lpc1766stk.h>
+#ifdef CYGPKG_KERNEL
+# include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>        // tracing macros
+#include <cyg/infra/cyg_ass.h>         // assertion macros
+
+#include <cyg/hal/hal_arch.h>          // HAL header
+#include <cyg/hal/hal_intr.h>          // HAL header
+static inline void hal_gpio_init(void);
+
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void
+hal_system_init(void)
+{
+#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_SRAM)
+    hal_gpio_init();
+#endif
+
+#if defined(CYG_HAL_STARTUP_ROM)
+    {
+        // Set flash accelerator according to CPU clock speed.
+        cyg_uint32      regval;
+        HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                        CYGHWR_HAL_LPC17XX_REG_FLASHCFG, regval);
+        regval &= ~CYGHWR_HAL_LPC17XX_REG_FLTIM_MASK;
+        regval |= CYGHWR_HAL_LPC17XX_REG_FLASHTIM;
+        HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                         CYGHWR_HAL_LPC17XX_REG_FLASHCFG, regval);
+    }
+#endif
+}
+
+
+//===========================================================================
+// hal_gpio_init
+//===========================================================================
+static inline void
+hal_gpio_init(void)
+{
+    // Enable UART0 and UART1 (has wired flow control and line status lines)
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL0,
+                               (1 /* TXD0 */  << 4) |
+                               (1 /* RXD0 */  << 6) |
+                               (1 /* TXD1 */  << 30)
+        );
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL1,
+                               (1 /* RXD1 */  << 0) |
+                               (1 /* CTS1 */  << 2) |
+                               (1 /* DCD1 */  << 4) |
+                               (1 /* DSR1 */  << 6) |
+                               (1 /* DTR1 */  << 8) |
+                               (1 /* RTS1 */  << 12)
+        );
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL2, 0);
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL3, 0);
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL4, 0);
+#if 0 // not used
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL5, 0);
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL6, 0);
+#endif
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL7, 0);
+#if 0 // not used
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL8, 0);
+#endif
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL9, 0);
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL10, 0);
+}
+
+
+//==========================================================================
+
+__externC void
+hal_platform_init(void)
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS     start;             // Region start address
+    CYG_ADDRESS     end;               // End address (last byte)
+} hal_data_access[] = {
+    {
+    // Main RAM (On-chip SRAM in code area)
+    CYGMEM_REGION_ram, CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - 1},
+#ifdef CYGMEM_REGION_ahb_sram_bank0
+    {
+    // On-chip AHB SRAM bank 0
+    CYGMEM_REGION_ahb_sram_bank0, CYGMEM_REGION_ahb_sram_bank0 + CYGMEM_REGION_ahb_sram_bank0_SIZE - 1},
+#endif
+#ifdef CYGMEM_REGION_ahb_sram_bank1
+    {
+    // On-chip AHB SRAM bank 1
+    CYGMEM_REGION_ahb_sram_bank1, CYGMEM_REGION_ahb_sram_bank1 + CYGMEM_REGION_ahb_sram_bank1_SIZE - 1},
+#endif
+#ifdef CYGMEM_REGION_flash
+    {
+    // On-chip flash
+    CYGMEM_REGION_flash, CYGMEM_REGION_flash + CYGMEM_REGION_flash_SIZE - 1},
+#endif
+#ifdef CYGMEM_REGION_rom
+    {
+    // External flash
+    CYGMEM_REGION_rom, CYGMEM_REGION_rom + CYGMEM_REGION_rom_SIZE - 1},
+#endif
+    {
+    0xE0000000, 0x00000000 - 1},       // Cortex-M peripherals
+    {
+    0x40000000, 0x60000000 - 1},       // Chip specific peripherals
+};
+
+__externC int
+cyg_hal_stub_permit_data_access(CYG_ADDRESS addr, cyg_uint32 count)
+{
+    int             i;
+
+    for (i = 0; i < sizeof(hal_data_access) / sizeof(hal_data_access[0]); i++) {
+        if ((addr >= hal_data_access[i].start) &&
+            (addr + count) <= hal_data_access[i].end)
+            return true;
+    }
+
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the main (S)RAM and peripheral (AHB) SRAM banks.
+
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_ahb_sram_bank0
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_ahb_sram_bank0;
+        *end =
+            (unsigned char *)(CYGMEM_REGION_ahb_sram_bank0 +
+                              CYGMEM_REGION_ahb_sram_bank0_SIZE);
+        break;
+#endif
+#ifdef CYGMEM_REGION_ahb_sram_bank1
+# ifndef CYGMEM_REGION_ahb_sram_bank0
+    case 1:
+# else
+    case 2:
+# endif
+        *start = (unsigned char *)CYGMEM_REGION_ahb_sram_bank1;
+        *end =
+            (unsigned char *)(CYGMEM_REGION_ahb_sram_bank1 +
+                              CYGMEM_REGION_ahb_sram_bank1_SIZE);
+        break;
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+}
+
+#endif // CYGPKG_REDBOOT
+
+
+//==========================================================================
+// EOF lpc1766stk_misc.c
diff --git a/packages/hal/cortexm/lpc17xx/var/current/ChangeLog b/packages/hal/cortexm/lpc17xx/var/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/var/current/ChangeLog
@@ -0,0 +1,61 @@
+2012-01-24  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx.cdl:
+	Fix interrupt minimal priority calculation. [ Bugzilla 1001432 ]
+
+2012-01-16  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx.cdl:
+	* include/var_io.h:
+	* src/lpc17xx_misc.c:
+	Recognize Code Read Protection FLASH field
+	Reported by Bernard Fouché [Bugzilla 1001443 ]
+
+2011-05-13  John Dallaway  <john@dallaway.org.uk>
+
+	* include/var_intr.h: Fix I2C interrupt definitions issue reported
+	by Pavel Glinskii. Also fix CYGNUM_HAL_INTERRUPT_NVIC_MAX from Ilija
+	Kocho.
+
+2011-03-14  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal_cortexm_lpc17xx.cdl: Do not implement the
+	CYGINT_PROFILE_HAL_TIMER interface at present.
+
+2010-12-10  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx.cdl:
+	* include/hal_cache.h:
+	* include/hal_diag.h:
+	* include/plf_stub.h:
+	* include/var_arch.h:
+	* include/variant.inc:
+	* include/var_intr.h:
+	* include/var_io.h:
+	* src/hal_diag.c:
+	* src/lpc17xx_misc.c:
+	New package -- NXP LPC17XX variant HAL.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010, 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/hal/cortexm/lpc17xx/var/current/cdl/hal_cortexm_lpc17xx.cdl b/packages/hal/cortexm/lpc17xx/var/current/cdl/hal_cortexm_lpc17xx.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/var/current/cdl/hal_cortexm_lpc17xx.cdl
@@ -0,0 +1,468 @@
+##==========================================================================
+##
+##      hal_cortexm_lpc17xx.cdl
+##
+##      Cortex-M LPC 1700 variant HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ilijak
+## Date:         2010-12-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_LPC17XX {
+    display       "Cortex-M3 LPC 17XX Variant"
+    parent        CYGPKG_HAL_CORTEXM
+    hardware
+    include_dir   cyg/hal
+    define_header hal_cortexm_lpc17xx.h
+    description   "
+       This package provides generic support for the NXP Cortex-M based
+       LPC17xx microcontroller family.  It is also necessary to select
+       a variant and platform HAL package."
+
+    compile       hal_diag.c lpc17xx_misc.c
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+    requires      { CYGHWR_HAL_CORTEXM == "M3" }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX {
+        display       "LPC17xx member in use"
+        flavor        data
+        default_value { "1766" }
+        legal_values  {
+            "1751" "1752"  "1754" "1756" "1758" "1759" "1763" "1764"
+            "1765" "1766" "1767" "1768" "1769" }
+        description   "
+            The LPC17xx has several variants, the main differences being
+            in the size of on-chip FLASH and SRAM and numbers of some
+            peripherals. This option allows the platform HAL to select
+            the specific microcontroller fitted."
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
+        display       "CPU priority levels"
+        flavor        data
+        calculated    5
+        description   "
+            This option defines the number of bits used to encode the
+            exception priority levels that this variant of the Cortex-M
+            CPU implements."
+    }
+
+    cdl_option CYGNUM_HAL_IRQ_PRIORITY_MIN {
+        display       "minimal interrupt priority"
+        flavor        data
+        no_define
+        calculated      0xFFFF&\
+              ((((1<<CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS)-1)-1)\
+               <<8-CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS)
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CLOCKING {
+        display       "Clocking"
+        flavor        none
+
+        cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_MAIN_CLOCK {
+            display       "Main clock"
+            flavor        none
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_MUL {
+                display       "PLL multiplier"
+                flavor        data
+                legal_values  6 to 32767
+                default_value { 12 }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_DIV {
+                display       "PLL divider"
+                flavor        data
+                legal_values  1 to 32
+                default_value { 1 }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_OUTPUT {
+                display       "PLL output (MHz)"
+                flavor        data
+                legal_values  275000000 to 550000000
+                calculated    { 2 * CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_MUL *
+                    CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_DIV }
+                description   "
+                    Normally the PLL output must be in the range of
+                    275MHz to 550MHz."
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED {
+                display       "CPU clock speed"
+                flavor        data
+                calculated    { 2 * CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_MUL *
+                    CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_DIV /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CPU_CLK_DIV }
+                description   "
+                    The core CPU clock speed is the PLL output divided
+                    by the CPU clock divider."
+
+                cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CPU_CLK_DIV {
+                    display       "CPU clock divider"
+                    flavor        data
+                    legal_values  2 to 256
+                    default_value { 3 }
+                    description   "
+                        The CPU clock divider controls the division of
+                        the PLL output before it is used by the CPU. When
+                        the PLL is bypassed, the division may be by
+                        1. When the PLL is running, the output must be
+                        divided in order to bring the CPU clock frequency
+                        (CCLK) within operating limits. An 8 bit divider
+                        allows a range of options, including slowing
+                        CPU operation to a low rate for temporary power
+                        savings without turning off the PLL."
+                }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_USB_CLOCK {
+            display       "USB clock"
+            flavor        none
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_MUL {
+                display       "PLL multiplier"
+                flavor        data
+                calculated    { 48000000 / CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_DIV {
+                display       "PLL divider"
+                flavor         data
+                legal_values  1 2 3 4
+                default_value { 2 }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_OUTPUT {
+                display       "PLL output (MHz)"
+                flavor        data
+                legal_values  156000000 to 320000000
+                calculated    { 2 * 48000000 *  CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_DIV }
+                description   "
+                    Normally the PLL output must be in the range of
+                    156MHz to 320MHz."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_USB_CLOCK_SPEED {
+                display       "USB clock speed"
+                flavor        data
+                calculated    { 2 * CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_MUL *
+                    CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_DIV }
+                description   "
+                    The USB clock speed is the PLL1 output."
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT {
+            display       "Clock-out option"
+            flavor        bool
+            default_value 0
+
+            description   "
+                This option enables clock output and selects clock source
+                and divider."
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SET {
+                display       "Clock out register setting"
+                flavor        data
+                calculated { (CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SRC |
+                              ((CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_DIV
+                               - (1 && CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT)) << 4) |
+                              (CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT ? 0x100 : 0x0 ))
+                }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL {
+                display       "Clock-out source selector"
+                flavor        data
+                legal_values  { "CPU clock" "Main osc." "RC osc." "USB clock" "RTC osc." }
+                default_value { "CPU clock" }
+                description   "
+                    Select clock out source."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SRC {
+                display       "Clock-out source"
+                flavor        data
+                legal_values  0 1 2 3 4
+                calculated    { CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "CPU clock" ? 0 :
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "Main osc." ? 1 :
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "RC osc."   ? 2 :
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "USB clock" ? 3 :
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "RTC osc."  ? 4 :
+                    0
+                }
+                description   "
+                    Clock-out source index."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_DIV {
+                display       "Clock-out divider"
+                flavor        data
+                legal_values  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+                default_value { 10 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_PER_CLK {
+            display       "Peripherial clocking"
+            flavor        none
+
+            cdl_option CYGHWR_HAL_LPC_RTC_32768HZ {
+                display      "RTC uses 32768 Hz clock"
+                flavor       bool
+                calculated   1
+                description  "
+                    This option has to be defined for LPC microcontrollers
+                    which RTC clock has no other clocking option than
+                    RTC 32768 Hz oscilator."
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CAN_CLK {
+                display       "CAN clock speed"
+                flavor        data
+                calculated    { CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CAN_CLK_DIV }
+                description   "
+                    The CAN clock speed is the CPU clock output divided
+                    by the CAN clock divider."
+
+                cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CAN_CLK_DIV {
+                    display       "CAN clock divider"
+                    flavor        data
+                    legal_values  { 1 2 4 6 }
+                    default_value { 2 }
+                    description   "
+                        This divider selects the peripheral clock for
+                        both CAN channels. The divider divides the CPU
+                        clock to get the clock for the CAN peripherals."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_ADC_CLK {
+                display       "ADC clock speed"
+                flavor        data
+                calculated    { CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_ADC_CLK_DIV }
+                description   "
+                    The ADC clock speed is the CPU clock output divided
+                    by the ADC clock divider."
+
+                cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_ADC_CLK_DIV {
+                    display       "ADC clock divider"
+                    flavor        data
+                    legal_values  { 1 2 4 8 }
+                    default_value { 2 }
+                    description   "
+                        This divider selects the peripheral clock for
+                        on-chip ADC. The ADC clock is the input clock
+                        of the ADC peripheral."
+                }
+            }
+
+            for { set ::channel 0 } { $::channel < 3 } { incr ::channel } {
+                cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_I2C[set ::channel]_CLK {
+                    display       "I2C channel [set ::channel] clock speed"
+                    flavor        data
+                    calculated    CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED / \
+                          CYGHWR_HAL_CORTEXM_LPC17XX_I2C[set ::channel]_CLK_DIV
+                    description   "
+                        The I2C clock speed is the CPU clock output
+                        divided by the I2C clock divider."
+
+                    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_I2C[set ::channel]_CLK_DIV {
+                        display       "I2C channel [set ::channel] clock divider"
+                        flavor        data
+                        legal_values  { 1 2 4 8 }
+                        default_value { 2 }
+                        description   "
+                            This divider selects the peripheral clock
+                            for I2C channel [set ::channel]. The divider
+                            divides the CPU clock to get the clock for
+                            the I2C peripheral."
+                    }
+                }
+            }
+        }
+    }
+
+    cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
+        display       "Clock interrupt ISR priority"
+        flavor        data
+        calculated    CYGNUM_HAL_IRQ_PRIORITY_MIN
+        description   "
+            Set clock ISR priority to lowest priority."
+    }
+
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+        no_define
+
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+        }
+
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR
+            description   "
+                The period defined here is something of a fake, it is
+                expressed in terms of a notional 1MHz clock. The value
+                actually installed in the hardware is calculated from
+                the current settings of the clock generation hardware."
+        }
+    }
+
+    cdl_option CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION {
+        display "Utilize \".lpc17xx_misc\" section for HAL"
+        flavor bool
+        default_value { CYG_HAL_STARTUP == "ROM" }
+        active_if { CYG_HAL_STARTUP == "ROM" }
+        description "
+        Kinetis use FLASH location  0x2fc for FLASH Code Read Protection.
+        This leaves FLASH area below 0x2fc
+            out of standard linker sections. Special section
+            \".lpc17xx_misc\" provides linker access to this area.
+            Setting this option instructs linker to place some HAL
+            (variant/platform) \"misc.\" functions in this area."
+    }
+
+    cdl_interface CYGINT_HAL_LPC17XX_UART0 {
+        display      "Platform has UART0 serial port"
+        description  "
+            The platform has a socket on UART0."
+    }
+
+    cdl_interface CYGINT_HAL_LPC17XX_UART1 {
+        display       "Platform has UART1 serial port"
+        description   "
+            The platform has a socket on UART1."
+    }
+
+    cdl_interface CYGINT_HAL_LPC17XX_UART2 {
+        display       "Platform has UART2 serial port"
+        description   "
+            The platform has a socket on UART2."
+    }
+
+    cdl_interface CYGINT_HAL_LPC17XX_UART3 {
+        display       "Platform has UART3 serial port"
+        description   "
+            The platform has a socket on UART3."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_ENET {
+        display       "LPC 17xx Ethernet check"
+        flavor        bool
+        no_define
+        parent        CYGPKG_DEVS_ETH_ARM_LPC2XXX
+        calculated    {
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1766") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1758") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1764") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1767") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1768") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1769")
+        }
+        requires {
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1766") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1758") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1764") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1767") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1768") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1769")
+        }
+        description   "
+            Check whether the chip has Ethernet controler."
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_LPC17XX_OPTIONS {
+        display       "Build options"
+        flavor        none
+        description   "
+              Package specific build options including control over
+              compiler flags used only in building this package."
+
+        cdl_option CYGPKG_HAL_CORTEXM_LPC17XX_CFLAGS_ADD {
+            display       "Additional compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the LPC17xx variant HAL package. These flags
+                are used in addition to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_CORTEXM_LPC17XX_CFLAGS_REMOVE {
+            display       "Suppressed compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the LPC17xx variant HAL package. These flags
+                are removed from the set of global flags if present."
+        }
+    }
+}
+
+# EOF hal_cortexm_lpc17xx.cdl
diff --git a/packages/hal/cortexm/lpc17xx/var/current/include/hal_cache.h b/packages/hal/cortexm/lpc17xx/var/current/include/hal_cache.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/var/current/include/hal_cache.h
@@ -0,0 +1,110 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+//      hal_cache.h
+//
+//      HAL cache control API
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour
+// Contributors: 
+// Date:         2004-07-23
+// Purpose:      Cache control API
+// Description:  The NXP LPC17XX CPU family does not require cache control.
+//               File is kept empty.
+//
+// Usage:
+//               #include <cyg/hal/hal_cache.h>
+//               ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
diff --git a/packages/hal/cortexm/lpc17xx/var/current/include/hal_diag.h b/packages/hal/cortexm/lpc17xx/var/current/include/hal_diag.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/var/current/include/hal_diag.h
@@ -0,0 +1,89 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+//=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL diagnostics
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.                  
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      nickg
+// Contributor(s): ilijak
+// Date:           2008-07-30
+// Purpose:        HAL diagnostics
+// Description: 
+// Usage:          #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_if.h>
+
+//-----------------------------------------------------------------------------
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+# define HAL_DIAG_INIT()          hal_if_diag_init()
+# define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+# define HAL_DIAG_READ_CHAR(_c_)  hal_if_diag_read_char(&_c_)
+
+#else
+
+__externC void  hal_plf_diag_init(void);
+__externC void  hal_plf_diag_putc(char);
+__externC cyg_uint8 hal_plf_diag_getc(void);
+
+# ifndef HAL_DIAG_INIT
+#  define HAL_DIAG_INIT() hal_plf_diag_init()
+# endif
+
+# ifndef HAL_DIAG_WRITE_CHAR
+#  define HAL_DIAG_WRITE_CHAR(__c) hal_plf_diag_putc(__c)
+# endif
+
+# ifndef HAL_DIAG_READ_CHAR
+#  define HAL_DIAG_READ_CHAR(__c) (__c) = hal_plf_diag_getc()
+# endif
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_DIAG_H
+// End of hal_diag.h
diff --git a/packages/hal/cortexm/lpc17xx/var/current/include/lpc17xx_misc.h b/packages/hal/cortexm/lpc17xx/var/current/include/lpc17xx_misc.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/var/current/include/lpc17xx_misc.h
@@ -0,0 +1,204 @@
+#ifndef CYGONCE_HAL_CORTEXM_LPC17XX_VAR_LPC17XX_MISC_H
+#define CYGONCE_HAL_CORTEXM_LPC17XX_VAR_LPC17XX_MISC_H
+//=============================================================================
+//
+//      lpc17xx_misc.h
+//
+//      HAL misc variant support code for NCP LPC17xx header file
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    andyj 
+// Contributors: jani, ilijak
+// Date:         2010-12-29
+// Purpose:      LPC17XX specific miscellaneous support header file
+// Description: 
+// Usage:        #include <cyg/hal/lpc17xx_misc.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Function to obtain the current processor clock settings
+// Use PCLK identifiers below
+//
+externC cyg_uint32 hal_lpc_get_pclk(cyg_uint32 pclk_id);
+#define CYG_HAL_CORTEXM_LPC17XX_PCLK(_pclkid_) hal_lpc_get_pclk(_pclkid_)
+
+//-----------------------------------------------------------------------------
+// Identifiers for peripheral clock. Use these identifiers with the function
+// hal_get_pclk()
+//
+#define CYNUM_HAL_LPC17XX_PCLK_WDT    0
+#define CYNUM_HAL_LPC17XX_PCLK_TIMER0 1
+#define CYNUM_HAL_LPC17XX_PCLK_TIMER1 2
+#define CYNUM_HAL_LPC17XX_PCLK_UART0  3
+#define CYNUM_HAL_LPC17XX_PCLK_UART1  4
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCLK_PWM0   5
+#endif
+#define CYNUM_HAL_LPC17XX_PCLK_PWM1   6
+#define CYNUM_HAL_LPC17XX_PCLK_I2C0   7
+#define CYNUM_HAL_LPC17XX_PCLK_SPI    8
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCLK_RTC    9
+#endif
+#define CYNUM_HAL_LPC17XX_PCLK_SSP1   10
+#define CYNUM_HAL_LPC17XX_PCLK_DAC    11
+#define CYNUM_HAL_LPC17XX_PCLK_ADC    12
+#define CYNUM_HAL_LPC17XX_PCLK_CAN1   13
+#define CYNUM_HAL_LPC17XX_PCLK_CAN2   14
+#define CYNUM_HAL_LPC17XX_PCLK_ACF    15
+#define CYNUM_HAL_LPC17XX_PCLK_QEI    16
+#define CYNUM_HAL_LPC17XX_PCLK_GPIO   17
+#define CYNUM_HAL_LPC17XX_PCLK_PCB    18
+#define CYNUM_HAL_LPC17XX_PCLK_I2C1   19
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCLK_SSP0   21
+#endif
+#define CYNUM_HAL_LPC17XX_PCLK_TIMER2 22
+#define CYNUM_HAL_LPC17XX_PCLK_TIMER3 23
+#define CYNUM_HAL_LPC17XX_PCLK_UART2  24
+#define CYNUM_HAL_LPC17XX_PCLK_UART3  25
+#define CYNUM_HAL_LPC17XX_PCLK_I2C2   26
+#define CYNUM_HAL_LPC17XX_PCLK_I2S    27
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCLK_MCI    28
+#endif
+#define CYNUM_HAL_LPC17XX_PCLK_RIT    29
+#define CYNUM_HAL_LPC17XX_PCLK_SYSCON 30
+#define CYNUM_HAL_LPC17XX_PCLK_MC     31
+
+
+//-----------------------------------------------------------------------------
+// Function to enable/disable power for certain peripheral
+// Use PCONP identifiers from below
+//
+externC void hal_lpc_set_power(cyg_uint8 pconp_id, int on);
+#define CYG_HAL_CORTEXM_LPC17XX_SET_POWER(_pconp_id_, _on_) \
+        hal_lpc_set_power((_pconp_id_), (_on_))
+
+
+//-----------------------------------------------------------------------------
+// Identifiers for power control, hal_get_pclk()
+//
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER0 1
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER1 2
+#define CYNUM_HAL_LPC17XX_PCONP_UART0  3
+#define CYNUM_HAL_LPC17XX_PCONP_UART1  4
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCONP_PWM0   5
+#endif
+#define CYNUM_HAL_LPC17XX_PCONP_PWM1   6
+#define CYNUM_HAL_LPC17XX_PCONP_I2C0   7
+#define CYNUM_HAL_LPC17XX_PCONP_SPI    8
+#define CYNUM_HAL_LPC17XX_PCONP_RTC    9
+#define CYNUM_HAL_LPC17XX_PCONP_SSP1   10
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCONP_EMC    11
+#endif
+#define CYNUM_HAL_LPC17XX_PCONP_ADC    12
+#define CYNUM_HAL_LPC17XX_PCONP_CAN1   13
+#define CYNUM_HAL_LPC17XX_PCONP_CAN2   14
+#define CYNUM_HAL_LPC17XX_PCONP_GPIO   15
+#define CYNUM_HAL_LPC17XX_PCONP_RIT    16
+#define CYNUM_HAL_LPC17XX_PCONP_MCPWM  17
+#define CYNUM_HAL_LPC17XX_PCONP_QEI    18
+#define CYNUM_HAL_LPC17XX_PCONP_I2C1   19
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCONP_LCD    20
+#endif
+#define CYNUM_HAL_LPC17XX_PCONP_SSP0   21
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER2 22
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER3 23
+#define CYNUM_HAL_LPC17XX_PCONP_UART2  24
+#define CYNUM_HAL_LPC17XX_PCONP_UART3  25
+#define CYNUM_HAL_LPC17XX_PCONP_I2C2   26
+#define CYNUM_HAL_LPC17XX_PCONP_I2S    27
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCONP_SDC    28
+#endif
+#define CYNUM_HAL_LPC17XX_PCONP_GPDMA  29
+#define CYNUM_HAL_LPC17XX_PCONP_ENET   30
+#define CYNUM_HAL_LPC17XX_PCONP_USB    31
+
+
+//-----------------------------------------------------------------------------
+// Configure pin function
+//
+externC void hal_lpc_set_pin_function(cyg_uint8 port, cyg_uint8 pin,
+                                  cyg_uint8 function);
+#define CYG_HAL_CORTEXM_LPC17XX_PIN_CFG(_port_, _pin_, _func_) \
+                hal_lpc_set_pin_function((_port_), (_pin_), (_func_))
+
+
+//-----------------------------------------------------------------------------
+// Macros to derive the baudrate divider values for the internal UARTs
+// The LPC17xx family supports different baudrate clocks for each single
+// UART. So we need a way to calculate the baudrate for each single UART
+// Now we rely on the fact that we use the same baudrate clock for all
+// UARTs and we query only UART0
+//-----------------------------------------------------------------------------
+
+#define CYG_HAL_CORTEXM_LPC17XX_BAUD_GENERATOR(_pclkid_, baud) \
+                (CYG_HAL_CORTEXM_LPC17XX_PCLK(_pclkid_)/((baud)*16))
+
+//-----------------------------------------------------------------------------
+// LPC17XX platform reset (watchdog resets the board)
+//-----------------------------------------------------------------------------
+#if 0
+externC void hal_lpc_watchdog_reset(void);
+
+#define HAL_PLATFORM_RESET() hal_lpc_watchdog_reset()
+#define HAL_PLATFORM_RESET_ENTRY 0
+#endif
+
+
+//-----------------------------------------------------------------------------
+// Compatibility layer for LPC2xxx device drivers
+//-----------------------------------------------------------------------------
+#define CYNUM_HAL_LPC24XX_PCLK_UART0 CYNUM_HAL_LPC17XX_PCLK_UART0
+#define CYNUM_HAL_LPC24XX_PCLK_UART1 CYNUM_HAL_LPC17XX_PCLK_UART1
+#define CYNUM_HAL_LPC24XX_PCLK_UART2 CYNUM_HAL_LPC17XX_PCLK_UART2
+#define CYNUM_HAL_LPC24XX_PCLK_UART3 CYNUM_HAL_LPC17XX_PCLK_UART3
+
+#define CYG_HAL_ARM_LPC24XX_BAUD_GENERATOR(_pclkid_, baud) \
+            CYG_HAL_CORTEXM_LPC17XX_BAUD_GENERATOR(_pclkid_, baud)
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_CORTEXM_LPC17XX_VAR_LPC17XX_MISC_H
+// End of lpc17xx_misc.h
diff --git a/packages/hal/cortexm/lpc17xx/var/current/include/plf_stub.h b/packages/hal/cortexm/lpc17xx/var/current/include/plf_stub.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/var/current/include/plf_stub.h
@@ -0,0 +1,86 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Contributors:jskov, gthomas, jlarmour
+// Date:        2008-07-30
+// Purpose:     Platform HAL stub support for STM32 variant boards.
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+#include <cyg/hal/cortexm_stub.h>       // architecture stub support
+#include <cyg/hal/hal_io.h>
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+__externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+
+#define HAL_STUB_PLATFORM_INIT()              CYG_EMPTY_STATEMENT
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
diff --git a/packages/hal/cortexm/lpc17xx/var/current/include/var_arch.h b/packages/hal/cortexm/lpc17xx/var/current/include/var_arch.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/var/current/include/var_arch.h
@@ -0,0 +1,61 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+//      var_arch.h
+//
+//      STM32 variant architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Date:         2008-07-30
+// Purpose:      LPC17XX variant architecture overrides
+// Description: 
+// Usage:        #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+
+#include <cyg/hal/plf_arch.h>
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_ARCH_H
+// End of var_arch.h
diff --git a/packages/hal/cortexm/lpc17xx/var/current/include/var_intr.h b/packages/hal/cortexm/lpc17xx/var/current/include/var_intr.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/var/current/include/var_intr.h
@@ -0,0 +1,120 @@
+#ifndef CYGONCE_HAL_VAR_INTR_H
+#define CYGONCE_HAL_VAR_INTR_H
+//==========================================================================
+//
+//      var_intr.h
+//
+//      HAL Interrupt and clock assignments for LPC17XX variants
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010, 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ilijak
+// Date:          2010-12-29
+// Purpose:       Define Interrupt support
+// Description:   The interrupt specifics for NXP LPC17XX variants are
+//                defined here.
+//              
+// Usage:         #include <cyg/hal/var_intr.h>
+//                However applications should include using <cyg/hal/hal_intr.h>
+//                instead to allow for platform overrides.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/plf_intr.h>
+
+//==========================================================================
+
+#define CYGNUM_HAL_INTERRUPT_WD      (0+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIMER0  (1+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIMER1  (2+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIMER2  (3+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIMER3  (4+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART0   (5+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART1   (6+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART2   (7+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART3   (8+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_PWM1    (9+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C0    (10+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C1    (11+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C2    (12+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#define CYGNUM_HAL_INTERRUPT_SPI     (13+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SSP0    (14+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SSP1    (15+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#define CYGNUM_HAL_INTERRUPT_PLL0    (16+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RTCDEV  (17+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#define CYGNUM_HAL_INTERRUPT_EINT0   (18+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_EINT1   (19+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_EINT2   (20+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_EINT3   (21+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_AD      (22+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_BOD     (23+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_USB     (24+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN     (25+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA     (26+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2S     (27+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ETH     (28+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RITINT  (29+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_MCPWM   (30+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_QENC    (31+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_PLL1    (32+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_USBAI   (33+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CANWAKE (34+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#define CYGNUM_HAL_INTERRUPT_NVIC_MAX (CYGNUM_HAL_INTERRUPT_CANWAKE)
+
+#define CYGNUM_HAL_ISR_MIN            0
+#define CYGNUM_HAL_ISR_MAX            CYGNUM_HAL_INTERRUPT_CANWAKE
+#define CYGNUM_HAL_ISR_COUNT          (CYGNUM_HAL_ISR_MAX+1)
+
+#define CYGNUM_HAL_VSR_MIN            0
+
+#ifndef CYGNUM_HAL_VSR_MAX
+# define CYGNUM_HAL_VSR_MAX (CYGNUM_HAL_VECTOR_SYS_TICK+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#endif
+
+#define CYGNUM_HAL_VSR_COUNT          (CYGNUM_HAL_VSR_MAX+1)
+
+//==========================================================================
+// Interrupt mask and config for variant-specific devices
+
+//----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_INTR_H
+// EOF var_intr.h
diff --git a/packages/hal/cortexm/lpc17xx/var/current/include/var_io.h b/packages/hal/cortexm/lpc17xx/var/current/include/var_io.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/var/current/include/var_io.h
@@ -0,0 +1,413 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//=============================================================================
+//
+//      var_io.h
+//
+//      Variant specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009 Free Software Foundation, Inc.                  
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ilijak
+// Original data: Uwe Kindler ( LPC24XX port )
+// Date:          2010-12-22
+// Purpose:       LPC17XX variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal_cortexm_lpc17xx.h>
+
+#include <cyg/hal/plf_io.h>
+
+//=============================================================================
+// Peripherals
+
+//=============================================================================
+// Cortex-M architecture register
+
+// VTOR setting
+#ifndef CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM
+#define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM               BIT_(28)
+#endif
+
+//---------------------------------------------------------------------------
+// Utilize LPC17xx flash between startup vectors and 0x2fc
+// for misc funtions.
+#ifdef CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION
+# define CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR \
+         CYGBLD_ATTRIB_SECTION(".lpc17xx_misc")
+#else
+# define CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+#endif
+
+__externC const cyg_uint32* hal_lpc17xx_crp_p(void);
+
+// LPC System Control Block
+#define CYGHWR_HAL_LPC17XX_REG_SCB_BASE                 0x400FC000
+
+// Flash accelerator
+#define CYGHWR_HAL_LPC17XX_REG_FLASHCFG                 0x0000
+#define CYGHWR_HAL_LPC17XX_REG_FLTSET(__tim)            (__tim << 12)
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM20MHZ               0x0
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM40MHZ               0x1
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM60MHZ               0x2
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM80MHZ               0x3
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM100MHZ              0x4
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM120MHZ              0x4
+#define CYGHWR_HAL_LPC17XX_REG_FLTIMSAFE                0x5
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM_MASK               CYGHWR_HAL_LPC17XX_REG_FLTSET(0x0f)
+
+// PLL. Registers are offsets from base of this subsystem
+#define CYGHWR_HAL_LPC17XX_REG_PLL0CON                  0x0080
+#define CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE              (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLC              (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_PLL0CFG                  0x0084
+#define CYGHWR_HAL_LPC17XX_REG_PLL0STAT                 0x0088
+#define CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLLE            (1<<24)
+#define CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLLC            (1<<25)
+#define CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLOCK           (1<<26)
+#define CYGHWR_HAL_LPC17XX_REG_PLL0FEED                 0x008C
+
+#define CYGHWR_HAL_LPC17XX_REG_PLL1CON                  0x00A0
+#define CYGHWR_HAL_LPC17XX_REG_PLL1CFG                  0x00A4
+#define CYGHWR_HAL_LPC17XX_REG_PLL1STAT                 0x00A8
+#define CYGHWR_HAL_LPC17XX_REG_PLL1STAT_PLLE            (1<<8)
+#define CYGHWR_HAL_LPC17XX_REG_PLL1STAT_PLLC            (1<<9)
+#define CYGHWR_HAL_LPC17XX_REG_PLL1STAT_PLOCK           (1<<10)
+#define CYGHWR_HAL_LPC17XX_REG_PLL1FEED                 0x00AC
+
+// Clock source selection register
+#define CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL                0x010C
+#define CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL_IRC            0x00
+#define CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL_MAIN           0x01
+#define CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL_RTC            0x10
+
+#define CYGHWR_HAL_LPC17XX_REG_CCLKCFG                  0x0104
+#define CYGHWR_HAL_LPC17XX_REG_USBCLKCFG                0x0108
+/* #define CYGHWR_HAL_LPC17XX_REG_IRCTRIM                  0x01A4 */
+#define CYGHWR_HAL_LPC17XX_REG_PCLKSEL0                 0x01A8
+#define CYGHWR_HAL_LPC17XX_REG_PCLKSEL1                 0x01AC
+#define CYGHWR_HAL_LPC17XX_REG_INTWAKE                  0x0144
+
+// Power Control
+#define CYGHWR_HAL_LPC17XX_REG_PCON                     0x00C0
+#define CYGHWR_HAL_LPC17XX_REG_PCON_IDL                 (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_PCON_PD                  (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP                    0x00C4
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_TIM0               (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_TIM1               (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_URT0               (1<<3)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_URT1               (1<<4)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_PWM0               (1<<5)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_PWM1               (1<<6)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_I2C0               (1<<7)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_SPI                (1<<8)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_RTC                (1<<9)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_SSP1               (1<<10)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_EMC                (1<<11)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_AD                 (1<<12)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_CAN1               (1<<13)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_CAN2               (1<<14)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_I2C1               (1<<19)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_LCD                (1<<20)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_SSP0               (1<<21)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_TIM2               (1<<22)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_TIM3               (1<<23)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_URT2               (1<<24)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_URT3               (1<<25)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_I2C2               (1<<26)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_I2S                (1<<27)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_SD                 (1<<28)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_DMA                (1<<29)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_ENET               (1<<30)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_USB                (1<<31)
+
+// Utility
+#define CYGHWR_HAL_LPC17XX_REG_CLKOUTCFG                0x01C8
+
+// System control and status register
+#define CYGHWR_HAL_LPC17XX_REG_SCS                      0x01A0
+#define CYGHWR_HAL_LPC17XX_REG_SCS_OSCEN                0x20
+#define CYGHWR_HAL_LPC17XX_REG_SCS_OSCSTAT              0x40
+
+
+//=============================================================================
+// Pin Connect Block (PIN)
+
+#define CYGHWR_HAL_LPC17XX_REG_PIN_BASE                  0x4002C000
+
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL0                   0x000
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL1                   0x004
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL2                   0x008
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL3                   0x00C
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL4                   0x010
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL5                   0x014
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL6                   0x018
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL7                   0x01C
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL8                   0x020
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL9                   0x024
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL10                  0x028
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL11                  0x02C
+
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE0                  0x040
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE1                  0x044
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE2                  0x048
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE3                  0x04C
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE4                  0x050
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE5                  0x054
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE6                  0x058
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE7                  0x05C
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE8                  0x060
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE9                  0x064
+
+#define CYGHWR_HAL_LPC17XX_PIN_SET(_reg, _func) \
+            HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_PIN_BASE + _reg, _func)
+
+#define CYGHWR_HAL_LPC17XX_PIN_GET(_reg, _dst) \
+            HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_PIN_BASE + _reg, _dst)
+
+//=============================================================================
+// UARTs (Ux)
+
+#define CYGHWR_HAL_LPC17XX_REG_UART0_BASE                0x4000C000
+#define CYGHWR_HAL_LPC17XX_REG_UART1_BASE                0x40010000
+#define CYGHWR_HAL_LPC17XX_REG_UART2_BASE                0x40098000
+#define CYGHWR_HAL_LPC17XX_REG_UART3_BASE                0x4009C000
+
+// Registers are offsets from base for each UART
+#define CYGHWR_HAL_LPC17XX_REG_UxRBR                     0x0000 // DLAB=0 read
+#define CYGHWR_HAL_LPC17XX_REG_UxTHR                     0x0000 // DLAB=0 write
+#define CYGHWR_HAL_LPC17XX_REG_UxDLL                     0x0000 // DLAB=1 r/w
+#define CYGHWR_HAL_LPC17XX_REG_UxIER                     0x0004 // DLAB=0
+#define CYGHWR_HAL_LPC17XX_REG_UxIER_RXDATA_INT          (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_UxIER_THRE_INT            (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_UxIER_RXLS_INT            (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_U1IER_RXMS_INT            (1<<3) // U1 only
+#define CYGHWR_HAL_LPC17XX_REG_UxDLM                     0x0004 // DLAB=1
+
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR                     0x0008 // read
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR_IIR0                (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR_IIR1                (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR_IIR2                (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR_IIR3                (1<<3)
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR_FIFOS               (0xB0)
+
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR                     0x0008 // write
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_FIFO_ENA            (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_FIFO_RESET       (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_TX_FIFO_RESET       (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_TRIGGER_0        (0x00)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_TRIGGER_1        (0x40)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_TRIGGER_2        (0x80)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_TRIGGER_3        (0xB0)
+
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR                     0x000C
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_WORD_LENGTH_5       (0x00)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_WORD_LENGTH_6       (0x01)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_WORD_LENGTH_7       (0x02)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_WORD_LENGTH_8       (0x03)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_STOP_1              (0x00)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_STOP_2              (0x04)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_PARITY_ENA          (0x08)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_PARITY_ODD          (0x00)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_PARITY_EVEN         (0x10)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_PARITY_ONE          (0x20)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_PARITY_ZERO         (0x30)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_BREAK_ENA           (0x40)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_DLAB                (0x80)
+
+// Modem Control Register is UART1 only
+#define CYGHWR_HAL_LPC17XX_REG_U1MCR                     0x0010
+#define CYGHWR_HAL_LPC17XX_REG_U1MCR_DTR                 (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_U1MCR_RTS                 (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_U1MCR_LOOPBACK            (1<<4)
+
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR                     0x0014
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_RDR                 (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_OE                  (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_PE                  (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_FE                  (1<<3)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_BI                  (1<<4)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_THRE                (1<<5)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_TEMT                (1<<6)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_RX_FIFO_ERR         (1<<7)
+
+// Modem Status Register is UART1 only
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR                     0x0018
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_DCTS                (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_DDSR                (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_RI_FALL             (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_DDCD                (1<<3)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_CTS                 (1<<4)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_DSR                 (1<<5)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_RI                  (1<<6)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_DCD                 (1<<7)
+
+#define CYGHWR_HAL_LPC17XX_REG_UxSCR                     0x001C
+#define CYGHWR_HAL_LPC17XX_REG_UxACR                     0x0020
+#define CYGHWR_HAL_LPC17XX_REG_U3ICR                     0x0024
+#define CYGHWR_HAL_LPC17XX_REG_UxFDR                     0x0028
+#define CYGHWR_HAL_LPC17XX_REG_UxTER                     0x0030
+
+// RTC
+#define CYGHWR_HAL_LPC17XX_REG_RTC_BASE                   0x40024000
+#define CYGARC_HAL_LPC2XXX_REG_RTC_BASE  CYGHWR_HAL_LPC17XX_REG_RTC_BASE
+
+// Registers are offsets from base of this subsystem
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ILR                    0x0000
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ILR_CIF                (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ILR_ALF                (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CTC                    0x0004
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CCR                    0x0008
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CCR_CLKEN              (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CCR_CTCRST             (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CIIR                   0x000C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_AMR                    0x0010
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CTIME0                 0x0014
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CTIME1                 0x0018
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CTIME2                 0x001C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_SEC                    0x0020
+#define CYGHWR_HAL_LPC17XX_REG_RTC_MIN                    0x0024
+#define CYGHWR_HAL_LPC17XX_REG_RTC_HOUR                   0x0028
+#define CYGHWR_HAL_LPC17XX_REG_RTC_DOM                    0x002C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_DOW                    0x0030
+#define CYGHWR_HAL_LPC17XX_REG_RTC_DOY                    0x0034
+#define CYGHWR_HAL_LPC17XX_REG_RTC_MONTH                  0x0038
+#define CYGHWR_HAL_LPC17XX_REG_RTC_YEAR                   0x003C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALSEC                  0x0060
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALMIN                  0x0064
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALHOUR                 0x0068
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALDOM                  0x006C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALDOW                  0x0070
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALDOY                  0x0074
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALMON                  0x0078
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALYEAR                 0x007C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_PREINT                 0x0080
+#define CYGHWR_HAL_LPC17XX_REG_RTC_PREFRAC                0x0084
+
+// Ethernet (EMAC)
+#define CYGHWR_HAL_LPC17XX_REG_EMAC_BASE                0x50000000
+
+// End Peripherals
+
+#ifndef __ASSEMBLER__
+
+__externC void hal_plf_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud );
+
+//-----------------------------------------------------------------------------
+// Configure pin function
+//
+__externC void  hal_set_pin_function(cyg_uint8 port, cyg_uint8 pin,
+                                     cyg_uint8 function);
+
+//-----------------------------------------------------------------------------
+// Function to enable/disable power for certain peripheral
+// Use PCONP identifiers from below
+//
+externC void hal_lpc_set_power(cyg_uint8 pconp_id, int on);
+
+
+//-----------------------------------------------------------------------------
+// Identifiers for power control, hal_get_pclk()
+//
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER0 1
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER1 2
+#define CYNUM_HAL_LPC17XX_PCONP_UART0  3
+#define CYNUM_HAL_LPC17XX_PCONP_UART1  4
+#define CYNUM_HAL_LPC17XX_PCONP_PWM0   5
+#define CYNUM_HAL_LPC17XX_PCONP_PWM1   6
+#define CYNUM_HAL_LPC17XX_PCONP_I2C0   7
+#define CYNUM_HAL_LPC17XX_PCONP_SPI    8
+#define CYNUM_HAL_LPC17XX_PCONP_RTC    9
+#define CYNUM_HAL_LPC17XX_PCONP_SSP1   10
+#define CYNUM_HAL_LPC17XX_PCONP_EMC    11
+#define CYNUM_HAL_LPC17XX_PCONP_ADC    12
+#define CYNUM_HAL_LPC17XX_PCONP_CAN1   13
+#define CYNUM_HAL_LPC17XX_PCONP_CAN2   14
+#define CYNUM_HAL_LPC17XX_PCONP_I2C1   19
+#define CYNUM_HAL_LPC17XX_PCONP_LCD    20
+#define CYNUM_HAL_LPC17XX_PCONP_SSP0   21
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER2 22
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER3 23
+#define CYNUM_HAL_LPC17XX_PCONP_UART2  24
+#define CYNUM_HAL_LPC17XX_PCONP_UART3  25
+#define CYNUM_HAL_LPC17XX_PCONP_I2C2   26
+#define CYNUM_HAL_LPC17XX_PCONP_I2S    27
+#define CYNUM_HAL_LPC17XX_PCONP_SDC    28
+#define CYNUM_HAL_LPC17XX_PCONP_GPDMA  29
+#define CYNUM_HAL_LPC17XX_PCONP_ENET   30
+#define CYNUM_HAL_LPC17XX_PCONP_USB    31
+
+#endif // ifndef __ASSEMBLER__
+
+
+//-----------------------------------------------------------------------------
+// LPC2xxx compatibility block
+// These definitions enable reusing of compatible LPC2xxx devs.
+
+// UART
+#define CYGARC_HAL_LPC24XX_REG_UART0_BASE CYGHWR_HAL_LPC17XX_REG_UART0_BASE
+#define CYGARC_HAL_LPC24XX_REG_UART1_BASE CYGHWR_HAL_LPC17XX_REG_UART1_BASE
+#define CYGARC_HAL_LPC24XX_REG_UART2_BASE CYGHWR_HAL_LPC17XX_REG_UART2_BASE
+#define CYGARC_HAL_LPC24XX_REG_UART3_BASE CYGHWR_HAL_LPC17XX_REG_UART3_BASE
+
+// RTC
+#define CYGARC_HAL_LPC2XXX_REG_RTC_BASE  CYGHWR_HAL_LPC17XX_REG_RTC_BASE
+
+// Ethernet (EMAC)
+#define CYGARC_HAL_LPC2XXX_REG_EMAC_BASE CYGHWR_HAL_LPC17XX_REG_EMAC_BASE
+
+// System Control Block
+#define CYGARC_HAL_LPC24XX_REG_SCB_BASE      CYGHWR_HAL_LPC17XX_REG_SCB_BASE
+
+// Power Control
+#define CYGARC_HAL_LPC24XX_REG_PCONP         CYGHWR_HAL_LPC17XX_REG_PCONP
+#define CYGARC_HAL_LPC24XX_REG_PCONP_ENET    CYGHWR_HAL_LPC17XX_REG_PCONP_ENET
+
+// Pin Connect Block (PIN)
+#define CYGARC_HAL_LPC24XX_REG_PIN_BASE      CYGHWR_HAL_LPC17XX_REG_PIN_BASE
+#define CYGARC_HAL_LPC24XX_REG_PINSEL2       CYGHWR_HAL_LPC17XX_REG_PINSEL2
+#define CYGARC_HAL_LPC24XX_REG_PINSEL3       CYGHWR_HAL_LPC17XX_REG_PINSEL3
+
+// End of LPC2xxx device compatibiliy block.
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_IO_H
+// End of var_io.h
diff --git a/packages/hal/cortexm/lpc17xx/var/current/include/variant.inc b/packages/hal/cortexm/lpc17xx/var/current/include/variant.inc
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/var/current/include/variant.inc
@@ -0,0 +1,53 @@
+/*==========================================================================
+//
+//      variant.inc
+//
+//      Variant specific asm definitions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, ilijak
+// Date:         2010-12-25
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal_cortexm_lpc17xx.h>
+
+//==========================================================================
+// EOF variant.inc
diff --git a/packages/hal/cortexm/lpc17xx/var/current/src/hal_diag.c b/packages/hal/cortexm/lpc17xx/var/current/src/hal_diag.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/var/current/src/hal_diag.c
@@ -0,0 +1,402 @@
+//=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008, 2010  Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, jani, ilijak
+// Contributors: jskov, gthomas
+// Date:         2010-12-15
+// Purpose:      HAL diagnostic output
+// Description:  Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>        // base types
+#include <cyg/infra/cyg_trac.h>        // tracing
+
+#include <cyg/hal/hal_arch.h>          // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h>            // IO macros
+#include <cyg/hal/hal_if.h>            // interface API
+#include <cyg/hal/hal_intr.h>          // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h>          // Helper functions
+#include <cyg/hal/drv_api.h>           // CYG_ISR_HANDLED
+
+#include <cyg/hal/var_io.h>            // USART registers
+#include <cyg/hal/lpc17xx_misc.h>      // peripheral identifiers
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+    cyg_uint32      uart;
+    CYG_ADDRESS     base;
+    cyg_int32       msec_timeout;
+    int             isr_vector;
+    int             baud_rate;
+    cyg_uint8       periph_id;
+    int             irq_state;
+} channel_data_t;
+
+static channel_data_t lpc17xx_ser_channels[] = {
+#if CYGINT_HAL_LPC17XX_UART0>0
+    {0,
+     CYGHWR_HAL_LPC17XX_REG_UART0_BASE,
+     1000,
+     CYGNUM_HAL_INTERRUPT_UART0,
+     CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD,
+     CYNUM_HAL_LPC17XX_PCLK_UART0},
+#endif
+#if CYGINT_HAL_LPC17XX_UART1>0
+    {1,
+     CYGHWR_HAL_LPC17XX_REG_UART1_BASE,
+     1000,
+     CYGNUM_HAL_INTERRUPT_UART1,
+     CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD,
+     CYNUM_HAL_LPC17XX_PCLK_UART1}
+#endif
+};
+
+#define HAL_PLF_SER_CHANNELS lpc17xx_ser_channels
+
+
+//===========================================================================
+// Initialize diagnostic serial channel
+//===========================================================================
+static void
+hal_plf_serial_init_channel(void *__ch_data)
+{
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    CYG_ADDRESS     base = chan->base;
+
+    hal_plf_uart_setbaud(base, chan->baud_rate);
+
+    // 8-1-no parity.
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxLCR,
+                     CYGHWR_HAL_LPC17XX_REG_UxLCR_WORD_LENGTH_8 |
+                     CYGHWR_HAL_LPC17XX_REG_UxLCR_STOP_1);
+
+    // Reset and enable FIFO
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxFCR,
+                     CYGHWR_HAL_LPC17XX_REG_UxFCR_FIFO_ENA |
+                     CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_FIFO_RESET |
+                     CYGHWR_HAL_LPC17XX_REG_UxFCR_TX_FIFO_RESET);
+}
+
+
+//===========================================================================
+// Write single character
+//===========================================================================
+void
+hal_plf_serial_putc(void *__ch_data, char c)
+{
+    CYG_ADDRESS     base = ((channel_data_t *) __ch_data)->base;
+    cyg_uint32      sr;
+
+    CYGARC_HAL_SAVE_GP();
+
+    do {
+        HAL_READ_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxLSR, sr);
+    } while ((sr & CYGHWR_HAL_LPC17XX_REG_UxLSR_THRE) == 0);
+
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxTHR, c);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool
+hal_plf_serial_getc_nonblock(void *__ch_data, cyg_uint8 *ch)
+{
+    CYG_ADDRESS     base = ((channel_data_t *) __ch_data)->base;
+    cyg_uint32      sr;
+    cyg_uint32      c;
+
+    CYGARC_HAL_SAVE_GP();
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxLSR, sr);
+
+    if ((sr & CYGHWR_HAL_LPC17XX_REG_UxLSR_RDR) == 0)
+        return false;
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxRBR, c);
+
+    *ch = (cyg_uint8)c;
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return true;
+}
+
+cyg_uint8
+hal_plf_serial_getc(void *__ch_data)
+{
+    cyg_uint8       ch;
+
+    CYGARC_HAL_SAVE_GP();
+
+    while (!hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return ch;
+}
+
+//=============================================================================
+// Virtual vector HAL diagnostics
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+static void
+hal_plf_serial_write(void *__ch_data, const cyg_uint8 *__buf,
+                     cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while (__len-- > 0)
+        hal_plf_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+hal_plf_serial_read(void *__ch_data, cyg_uint8 *__buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while (__len-- > 0)
+        *__buf++ = hal_plf_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool
+hal_plf_serial_getc_timeout(void *__ch_data, cyg_uint8 *ch)
+{
+    int             delay_count;
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    cyg_bool        res;
+
+    CYGARC_HAL_SAVE_GP();
+
+    // Delay in 10 us steps
+    delay_count = chan->msec_timeout * 100;
+
+    while(true) {
+        res = hal_plf_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+
+        CYGACC_CALL_IF_DELAY_US(10);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return res;
+}
+
+static int
+hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    CYG_ADDRESS     base = ((channel_data_t *) __ch_data)->base;
+    int             ret = 0;
+
+    va_list         ap;
+
+    CYGARC_HAL_SAVE_GP();
+
+    va_start(ap, __func);
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        chan->irq_state = 1;
+        HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+        HAL_INTERRUPT_UNMASK(chan->isr_vector);
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxIER,
+                         CYGHWR_HAL_LPC17XX_REG_UxIER_RXDATA_INT);
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = chan->irq_state;
+        chan->irq_state = 0;
+        HAL_INTERRUPT_MASK(chan->isr_vector);
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxIER,
+                         CYGHWR_HAL_LPC17XX_REG_UxIER_RXDATA_INT);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+        {
+            va_list         ap;
+
+            va_start(ap, __func);
+
+            ret = chan->msec_timeout;
+            chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+            va_end(ap);
+        }
+    case __COMMCTL_GETBAUD:
+        ret = chan->baud_rate;
+        break;
+    case __COMMCTL_SETBAUD:
+        chan->baud_rate = va_arg(ap, cyg_int32);
+        // Should we verify this value here?
+        hal_plf_uart_setbaud(base, chan->baud_rate);
+        ret = 0;
+        break;
+    default:
+        break;
+    }
+    va_end(ap);
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int
+hal_plf_serial_isr(void *__ch_data, int *__ctrlc,
+                   CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    cyg_uint8       ch;
+
+    CYGARC_HAL_SAVE_GP();
+
+    *__ctrlc = 0;
+
+    if (hal_plf_serial_getc_nonblock(__ch_data, &ch)) {
+        if (cyg_hal_is_break((char *)&ch, 1))
+            *__ctrlc = 1;
+    }
+
+    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return 1;
+}
+
+static void
+hal_plf_serial_init(void)
+{
+    hal_virtual_comm_table_t *comm;
+    int             cur;
+    int             i;
+
+    cur =
+        CYGACC_CALL_IF_SET_CONSOLE_COMM
+        (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    for (i = 0; i < CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS; i++) {
+        hal_plf_serial_init_channel(&lpc17xx_ser_channels[i]);
+
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+        comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+        CYGACC_COMM_IF_CH_DATA_SET(*comm, &lpc17xx_ser_channels[i]);
+        CYGACC_COMM_IF_WRITE_SET(*comm, hal_plf_serial_write);
+        CYGACC_COMM_IF_READ_SET(*comm, hal_plf_serial_read);
+        CYGACC_COMM_IF_PUTC_SET(*comm, hal_plf_serial_putc);
+        CYGACC_COMM_IF_GETC_SET(*comm, hal_plf_serial_getc);
+        CYGACC_COMM_IF_CONTROL_SET(*comm, hal_plf_serial_control);
+        CYGACC_COMM_IF_DBG_ISR_SET(*comm, hal_plf_serial_isr);
+        CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, hal_plf_serial_getc_timeout);
+    }
+
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+
+    // Set debug channel baud rate if different
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD)
+    lpc17xx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate =
+        CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD;
+    update_baud_rate(&lpc17xx_ser_channels
+                     [CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]);
+#endif
+
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int      initialized = 0;
+
+    if (initialized)
+        return;
+
+    initialized = 1;
+
+    hal_plf_serial_init();
+}
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+//=============================================================================
+// Non-Virtual vector HAL diagnostics
+
+#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+void
+hal_plf_diag_init(void)
+{
+    hal_plf_serial_init(&lpc17xx_ser_channels
+                        [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL]);
+}
+
+void
+hal_plf_diag_putc(char c)
+{
+    hal_plf_serial_putc(&lpc17xx_ser_channels
+                        [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c);
+}
+
+cyg_uint8
+hal_plf_diag_getc(void)
+{
+    return
+        hal_plf_serial_getc(&lpc17xx_ser_channels
+                            [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL]);
+}
+
+#endif // if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+//-----------------------------------------------------------------------------
+// End of hal_diag.c
diff --git a/packages/hal/cortexm/lpc17xx/var/current/src/lpc17xx_misc.c b/packages/hal/cortexm/lpc17xx/var/current/src/lpc17xx_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/lpc17xx/var/current/src/lpc17xx_misc.c
@@ -0,0 +1,430 @@
+//==========================================================================
+//
+//      lpc17xx_misc.c
+//
+//      Cortex-M LPC17XX HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, ilijak
+// Date:         2010-12-12
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_lpc17xx.h>
+#ifdef CYGPKG_KERNEL
+# include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>        // tracing macros
+#include <cyg/infra/cyg_ass.h>         // assertion macros
+
+#include <cyg/hal/hal_arch.h>          // HAL header
+#include <cyg/hal/hal_intr.h>          // HAL header
+#include <cyg/hal/hal_if.h>            // HAL header
+
+#include <cyg/hal/lpc17xx_misc.h>
+
+
+//===========================================================================
+//                               DEFINES
+//===========================================================================
+
+cyg_uint32      hal_lpc17xx_sysclk;
+cyg_uint32      hal_cortexm_systick_clock;
+
+cyg_uint32      hal_get_lpc_cpu_clock(void);
+
+void            hal_start_clocks(void);
+
+void            hal_lpc_start_main_clock(void);
+void            hal_lpc_start_usb_clock(void);
+#if defined(CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT)
+void            hal_lpc_clock_out(void);
+#endif
+//==========================================================================
+
+#ifdef CYG_HAL_STARTUP_ROM
+
+//===========================================================================
+// LPC17xx Code Read Protection field field
+//===========================================================================
+
+// Note: LPC17xx Code Read Protection field field must be present in
+//       LPC17xx flash image and ocupy a word at 0x000002FC
+
+// For ".lpc17xx_crp" section definition see MLT files.
+
+const cyg_uint32 LPC17XX_CRP __attribute__((section(".lpc17xxcrp"), used)) = 0xFFFFFFFF;
+
+#endif // CYG_HAL_STARTUP_ROM
+
+const cyg_uint32* hal_lpc17xx_crp_p(void)
+{
+    return &LPC17XX_CRP;
+}
+
+void
+hal_variant_init(void)
+{
+#if 1                                  /* !defined(CYG_HAL_STARTUP_RAM) */
+    hal_start_clocks();
+#endif
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    hal_if_init();
+#endif
+}
+
+//==========================================================================
+// Setup up system clocks
+//
+// Set up clocks from configuration. In the future this should be extended so
+// that clock rates can be changed at runtime.
+
+
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+hal_start_clocks(void)
+{
+    // Main clock - for everything except USB
+    hal_lpc_start_main_clock();
+
+    // USB clock
+    hal_lpc_start_usb_clock();
+
+#if defined CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT
+    hal_lpc_clock_out();
+#endif
+}
+
+
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+hal_lpc_start_main_clock(void)
+{
+    CYG_ADDRESS     scb_base_p;
+    cyg_uint32      regval;
+
+    scb_base_p = CYGHWR_HAL_LPC17XX_REG_SCB_BASE;
+
+    HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0STAT, regval);
+    if (regval & CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLLC) {
+
+        // Enable PLL, disconnected
+        HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0CON,
+                         CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE);
+        HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0xaa);
+        HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0x55);
+    }
+    // Disable PLL, disconnected
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0CON, 0x00);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0x55);
+
+    // Enables main oscillator and wait until it is usable
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_SCS,
+                     CYGHWR_HAL_LPC17XX_REG_SCS_OSCEN);
+    do {
+        HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_SCS, regval);
+    } while (!(regval & CYGHWR_HAL_LPC17XX_REG_SCS_OSCSTAT));
+
+
+    // Select main OSC, 12MHz, as the PLL clock source
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL,
+                     CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL_MAIN);
+
+    // Configure PLL multiplier and pre divider according to configuration
+    // values
+    regval = ((CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_MUL - 1) |
+              (CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_DIV - 1) << 16);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0CFG, regval);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0x55);
+
+    // Enable PLL, disconnected
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0CON,
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0x55);
+
+    // Set CPU clock divider
+    regval = CYGHWR_HAL_CORTEXM_LPC17XX_CPU_CLK_DIV - 1;
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_CCLKCFG, regval);
+
+    // Check lock bit status
+    do {
+        HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0STAT, regval);
+    } while (!(regval & CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLOCK));
+
+    // Connect CPU clock
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0CON,
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE |
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLC);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0x55);
+
+    // Check connect bit status
+    do {
+        HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0STAT, regval);
+    } while (!(regval & CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLLC));
+
+    // Calculate system clock from configuration
+    hal_lpc17xx_sysclk = CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED;
+    hal_cortexm_systick_clock = hal_lpc17xx_sysclk;
+}
+
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+hal_lpc_start_usb_clock(void)
+{
+    CYG_ADDRESS     scb_base_p;
+    cyg_uint32      regval;
+
+    scb_base_p = CYGHWR_HAL_LPC17XX_REG_SCB_BASE;
+
+    // Configure PLL multiplier and pre divider according to
+    // configuration values
+    regval = ((CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_MUL - 1) |
+              (CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_DIV - 1) << 5);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1CFG, regval);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0x55);
+
+    // Enable PLL, disconnected
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1CON,
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0x55);
+
+    do {
+        HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1STAT, regval);
+    } while (!(regval & CYGHWR_HAL_LPC17XX_REG_PLL1STAT_PLOCK));
+
+    // Connect USB clock
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1CON,
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE |
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLC);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0x55);
+
+    // Check connect bit status
+    do {
+        HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1STAT, regval);
+    } while (!(regval & CYGHWR_HAL_LPC17XX_REG_PLL1STAT_PLLC));
+}
+
+#ifdef CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+hal_lpc_clock_out(void)
+{
+    cyg_uint32      regval;
+
+    CYGHWR_HAL_LPC17XX_PIN_GET(CYGHWR_HAL_LPC17XX_REG_PINSEL3, regval);
+    regval &= ~0x00c00000;
+    regval |= 0x00400000;
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL3, regval);
+
+    HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                     CYGHWR_HAL_LPC17XX_REG_CLKOUTCFG,
+                     CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SET);
+}
+#endif // CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT
+
+
+cyg_uint32
+hal_lpc_get_cpu_clock(void)
+{
+    cyg_uint32      regval,
+                    pll0stat_div,
+                    pll0stat_mul,
+                    cclkcfg;
+
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                    CYGHWR_HAL_LPC17XX_REG_PLL0STAT, pll0stat_div);
+    pll0stat_mul = ((pll0stat_div >> 16) & 0xff) + 1;
+    pll0stat_div = 2 * ((pll0stat_div & 0x7fff) + 1);
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                    CYGHWR_HAL_LPC17XX_REG_CCLKCFG, cclkcfg);
+    cclkcfg = (cclkcfg & 0xff) + 1;
+
+    regval =
+        CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ * pll0stat_div / pll0stat_mul /
+        cclkcfg;
+
+    return regval;
+}
+
+
+//===========================================================================
+// Get peripheral clock for a certain peripheral
+//===========================================================================
+cyg_uint32
+hal_lpc_get_pclk(cyg_uint32 pclk_id)
+{
+    static const cyg_uint8 divider_tbl[4] = {
+        4, 1, 2, 8
+    };
+    cyg_uint32      pclkselreg;
+    cyg_uint32      regval;
+    cyg_uint8       divider;
+
+    CYG_ASSERT(pclk_id >= CYNUM_HAL_LPC17XX_PCLK_WDT &&
+               pclk_id <= CYNUM_HAL_LPC17XX_PCLK_SYSCON,
+               "Invalid peripheral clock ID");
+
+    // Decide if we need PCLKSEL0 or PCLKSEL1
+    pclkselreg = ((pclk_id <= CYNUM_HAL_LPC17XX_PCLK_ACF) ?
+                  CYGHWR_HAL_LPC17XX_REG_PCLKSEL0 :
+                  CYGHWR_HAL_LPC17XX_REG_PCLKSEL1);
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE + pclkselreg, regval);
+    regval = (regval >> ((pclk_id & 0xF) << 1)) & 0x03;
+    divider = divider_tbl[regval];
+    if ((8 == divider) && (pclk_id >= CYNUM_HAL_LPC17XX_PCLK_CAN1)
+        && (pclk_id <= CYNUM_HAL_LPC17XX_PCLK_ACF)) {
+        divider = 6;
+    }
+    return CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED / divider;
+}
+
+
+//===========================================================================
+// Set peripheral clock
+//===========================================================================
+void
+hal_lpc_set_pclk(cyg_uint32 peripheral_id, cyg_uint8 divider)
+{
+    static const cyg_uint8 clock_tbl[5] = {
+        0x01,                          // divider 1
+        0x02,                          // divider 2
+        0x00,                          // divider 4
+        0x03,                          // divider 6
+        0x03                           // divider 8
+    };
+    cyg_uint32      clock;
+    cyg_uint32      pclkselreg;
+    cyg_uint32      regval;
+
+    CYG_ASSERT(peripheral_id >= CYNUM_HAL_LPC17XX_PCLK_WDT &&
+               peripheral_id <= CYNUM_HAL_LPC17XX_PCLK_SYSCON,
+               "Invalid peripheral clock ID");
+    CYG_ASSERT(divider <= 8, "Wrong peripheral clock divider value");
+
+    // Decide if we need PCLKSEL0 or PCLKSEL1
+    pclkselreg = (peripheral_id <= CYNUM_HAL_LPC17XX_PCLK_ACF) ?
+        CYGHWR_HAL_LPC17XX_REG_PCLKSEL0 : CYGHWR_HAL_LPC17XX_REG_PCLKSEL1;
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE + pclkselreg, regval);
+    clock = clock_tbl[divider >> 1];
+    regval &= ~(0x03 << ((peripheral_id & 0xF) << 1));
+    regval |= (clock << ((peripheral_id & 0xF) << 1));
+    HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE + pclkselreg, regval);
+}
+
+
+//===========================================================================
+// Set pin function
+//===========================================================================
+void
+hal_lpc_set_pin_function(cyg_uint8 port, cyg_uint8 pin, cyg_uint8 function)
+{
+    cyg_uint32      regval;
+    cyg_uint8       pinsel_reg = port << 1;
+
+    CYG_ASSERT(port <= 4, "Port value out of bounds");
+    CYG_ASSERT(pin <= 31, "Pin value out of bounds");
+    CYG_ASSERT(function <= 3, "Invalid function value");
+
+    pinsel_reg += (pin > 15) ? 1 : 0;
+    pinsel_reg <<= 2;
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_PIN_BASE + pinsel_reg, regval);
+    regval &= ~(0x03 << ((pin & 0xF) << 1));
+    regval |= (function << ((pin & 0xF) << 1));
+    HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_PIN_BASE + pinsel_reg, regval);
+}
+
+//===========================================================================
+// Enable/Disable power for certain peripheral
+//===========================================================================
+void
+hal_lpc_set_power(cyg_uint8 pconp_id, int on)
+{
+    cyg_uint32      regval;
+
+    CYG_ASSERT(pconp_id >= CYNUM_HAL_LPC17XX_PCONP_TIMER0 &&
+               pconp_id <= CYNUM_HAL_LPC17XX_PCONP_USB,
+               "Invalid peripheral power ID");
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                    CYGHWR_HAL_LPC17XX_REG_PCONP, regval);
+    if (on) {
+        regval |= (0x01 << pconp_id);
+    } else {
+        regval &= ~(0x01 << pconp_id);
+    }
+
+    HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                     CYGHWR_HAL_LPC17XX_REG_PCONP, regval);
+}
+
+
+//==========================================================================
+// UART baud rate
+//
+// Set the baud rate divider of a UART based on the requested rate and
+// the current APB clock settings.
+
+void
+hal_plf_uart_setbaud(cyg_uint32 base, cyg_uint32 baud)
+{
+    cyg_uint32      periph_id = CYNUM_HAL_LPC17XX_PCLK_UART0;
+    cyg_uint16      divider;
+
+    if (CYGHWR_HAL_LPC17XX_REG_UART1_BASE == base)
+        periph_id = CYNUM_HAL_LPC17XX_PCLK_UART1;
+    divider = CYG_HAL_CORTEXM_LPC17XX_BAUD_GENERATOR(periph_id, baud);
+    // Set baudrate
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxLCR,
+                     CYGHWR_HAL_LPC17XX_REG_UxLCR_DLAB);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxDLM, divider >> 8);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxDLL, divider & 0xFF);
+}
+
+//==========================================================================
+// EOF lpc17xx_misc.c
diff --git a/packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog b/packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog
+++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog
@@ -1,3 +1,58 @@
+2012-04-20  Ilija Stanislevik  <ilijas@siva.mk>
+
+	* src/stm3210e_eval_eth_enc424j600.c: New file, initialization
+	of optional enc424j600 ethernet over SPI.
+
+	* include/plf_io.h: Add macro for initialization of optional
+	enc424j600 ethernet over SPI.
+
+	* cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Add component
+	enc424j600 ethernet over SPI.
+
+2012-03-23  James Smith  <jsmith@ecoscentric.com>
+
+	* include/plf_io.h: Update GPIO pin definitions to use new PIN
+	wrapper macros. Update to use common SPEED_SPI name for SPI pin
+	speed selection.
+
+2012-02-29  James Smith  <jsmith@ecoscentric.com>
+
+	* src/stm3210e_eval_flash.c: Flash structure needs to be "const"
+	to match header.
+
+2012-01-12  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/plf_io.h: Add SPI and I2C pin and DMA definitions.
+
+2011-12-20  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Just set a requires on
+	RedBoot's number of memory segments to be 2 rather than using a
+	non-configurable option.
+
+2011-12-08  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Indicate to new STM32 variant
+	HAL CDL that this is an F103ZE processor.
+
+2011-01-27  Nick Garnett  <nickg@ecoscentric.com>
+
+	* misc/redboot_JTAG.ecm:
+	* misc/redboot_ROM.ecm: Define CYGNUM_REDBOOT_FLASH_RESERVED_DEVICES
+	to take on-chip flash out of FIS control.
+
+2011-01-01  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3210e_eval.cdl
+	(CYGHWR_HAL_CORTEXM_STM32_FLASH): Should be on by default if generic flash
+	active in configuration.
+
+2010-08-29  John Dallaway  <john@dallaway.org.uk>
+
+	* misc/redboot_JTAG.ecm, misc/redbooot_ROM.ecm:
+	Inhibit the FIS directory entry for RedBoot and management of the
+	internal flash. Issues reported by Carlo Caione.
+
 2010-03-18  Ross Younger  <wry@ecoscentric.com>
 
 	* tests/eccwalk.c: Build fix for changes elsewhere.
@@ -30,6 +85,11 @@ 2009-08-26  Ross Younger  <wry@ecoscentr
 	* src/stm3210e_eval_nand.c: Added support for onboard NAND chip.
 	Based on work by Simon Kallweit.
 
+2009-07-02  Nick Garnett  <nickg@ecoscentric.com>
+
+	* src/stm3210e_eval_misc.c (hal_system_init): Adjust clock enables
+	in line with changes to bit definitions.
+
 2009-02-04  Nick Garnett  <nickg@ecoscentric.com>
 
 	* include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi:
@@ -63,6 +123,18 @@ 2008-11-19  Nick Garnett  <nickg@ecoscen
 	* include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi (hal_startup_stack):
 	Adjust initial stack to top of external SRAM.
 
+2008-10-28  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h:	
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h: Adjust top of
+	RAM to 1MB.
+	
 2008-10-10  Nick Garnett  <nickg@ecoscentric.com>
 
 	* include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi:
@@ -103,7 +175,7 @@ 2008-10-06  Nick Garnett  <nickg@ecoscen
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008, 2009 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.                        
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl b/packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl
+++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 2008 Free Software Foundation, Inc.                        
+## Copyright (C) 2008, 2012 Free Software Foundation, Inc.
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -49,6 +49,8 @@
 cdl_package CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL {
     display       "ST STM3210E EVAL Development Board HAL"
     parent        CYGPKG_HAL_CORTEXM_STM32
+    requires      { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F1" }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_F1 == "F103ZE" }
     define_header hal_cortexm_stm32_stm3210e_eval.h
     include_dir   cyg/hal
     hardware
@@ -84,17 +86,35 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM
             JTAG debugger such as a BDI3000 or PEEDI. The 'SRAM' type allows
             programs to be downloaded via a JTAG debugger into on-chip SRAM."
     }
-    
+
     cdl_component CYGHWR_MEMORY_LAYOUT {
         display "Memory layout"
         flavor data
         no_define
-        calculated    { (CYG_HAL_STARTUP == "RAM" ) ? "cortexm_stm3210e_eval_ram"      :
+        calculated    { (CYG_HAL_STARTUP == "RAM" ) ? 
+                        (CYGMEM_HAL_CORTEXM_STM32_STM3210E_EXTRA_BASE_RAM ?
+                        "cortexm_stm3210e_eval_extrabaseram" : "cortexm_stm3210e_eval_ram")      :
                         (CYG_HAL_STARTUP == "SRAM") ? "cortexm_stm3210e_eval_sram"     :
                         (CYG_HAL_STARTUP == "ROM" ) ? "cortexm_stm3210e_eval_rom"      :
                         (CYG_HAL_STARTUP == "JTAG") ? "cortexm_stm3210e_eval_jtag"     :
                                                       "undefined" }
 
+        cdl_option CYGMEM_HAL_CORTEXM_STM32_STM3210E_EXTRA_BASE_RAM {
+            display       "Additional reserved space at base of RAM"
+            flavor        booldata
+            default_value 0
+            active_if     {CYG_HAL_STARTUP == "RAM"}
+            legal_values  0 to 0x80000
+            description   "
+                If you are using a RedBoot with additional components enabled,
+                such as networking, RedBoot may be occupying additional RAM.
+                In such cases, an eCos application loaded by RedBoot must
+                reserve additional space at the base of RAM to accommodate
+                RedBoot's extra RAM requirements. This option, specified in
+                bytes, allows the amount of extra reserved space to be
+                increased beyond the default."
+        }
+
         cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
                 display "Memory layout linker script fragment"
                 flavor data
@@ -121,13 +141,26 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM
         description     "Main clock input."
     }
 
-    cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH {
-        display         "External NOR flash support"
+    cdl_component CYGHWR_HAL_CORTEXM_STM32_FLASH {
+        display         "Flash support"
         parent          CYGPKG_IO_FLASH
         active_if       CYGPKG_IO_FLASH
-        flavor          none
         compile         -library=libextras.a stm3210e_eval_flash.c
-        description "This option enables support for the external NOR flash device."
+        default_value   1
+        description     "Control flash device support for STM3210E-EVAL board."
+    
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH_INTERNAL {
+            display         "Internal flash support"
+            default_value   1
+            description     "This option enables support for the internal flash device."
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH_NOR {
+            display         "External NOR flash support"
+            default_value   1
+            description     "This option enables support for the external NOR flash device."
+        }
+
     }
 
     # Both UARTs 0 and 1 are available for diagnostic/debug use.
@@ -175,6 +208,12 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM
         description   "
             This option controls the default baud rate used for the
             console connection.
+            RedBoot usess polling to transfer data over this port and
+            might not be able to keep up with baud rates above the
+            default, particularly when doing XYZmodem downloads. The
+            interrupt-driven device driver is able to handle these
+            baud rates, so any high speed application transfers should
+            use that instead.
             Note: this should match the value chosen for the GDB port if the
             diagnostic and GDB port are the same."
     }
@@ -187,11 +226,105 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM
         description   "
             This option controls the default baud rate used for the
             GDB connection.
+            RedBoot usess polling to transfer data over this port and
+            might not be able to keep up with baud rates above the
+            default, particularly when doing XYZmodem downloads. The
+            interrupt-driven device driver is able to handle these
+            baud rates, so any high speed application transfers should
+            use that instead.
             Note: this should match the value chosen for the console port if the
             console and GDB port are the same."
     }
 
-    
+    cdl_component CYGHWR_HAL_CORTEXM_STM32_SPIETH_CONTROLLER {
+        display       "STM3210E support for ENC424J600 SPI ethernet"
+        parent        CYGPKG_DEVS_ETH_ENC424J600
+        active_if     CYGPKG_DEVS_ETH_ENC424J600
+        compile       stm3210e_eval_eth_enc424j600.c
+        flavor        none
+        no_define
+
+        description   "
+            Support for ENC424J600 with STM3210E EVAL board."
+            
+        cdl_option CYGNUM_ETH_SPIETH_HAL_INTERRUPT_VECTOR { 
+            display       "Interrupt vector calculated from pin"
+            parent        CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_VECTOR
+            flavor        data
+            no_define
+            calculated    { "CYGNUM_HAL_INTERRUPT_EXTI" . CYGHWR_HAL_SPIETH_INTERRUPT_PIN } 
+            active_if     CYGINT_IO_ETH_INT_SUPPORT_REQUIRED 
+            description   "
+                Interrupt vector corresponding with external interrupt line used for
+                enc424j600.
+                This value is automatically calculated from CYGHWR_HAL_SPIETH_INTERRUPT_PIN.
+                "
+        } 
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS {
+            display       "SPI bus"
+            flavor        data
+            requires      { (CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS == 1) implies CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1 }
+            requires      { (CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS == 2) implies CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2 }
+            requires      { (CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS == 3) implies CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3 }
+            requires      (CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE==50)
+            legal_values  { 1 2 3 } 
+            default_value 1
+            description   "
+                Select which SPI bus of the STM32 the SPI Ethernet controller
+                is connected to."
+        }
+        
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_CS {
+            display       "Chip select index"
+            flavor        data
+            default_value 0
+            legal_values  0 to 99
+            description   "
+                Enter the index into the array of chip selects to be used as
+                the chip select for the external Ethernet
+                controller connected to the SPI bus. The list of possible chip
+                selects for the selected SPI bus is defined in the STM32 SPI
+                driver's configuration, for example for SPI bus 1:
+                CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1_CS_GPIOS."
+        }
+        
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_SPIETH_INTERRUPT_PORT {
+            display       "Interrupt pin port"
+            active_if     CYGINT_IO_ETH_INT_SUPPORT_REQUIRED 
+            flavor        data
+            legal_values  { "\'A\'" "\'B\'" "\'C\'" "\'D\'" "\'E\'" "\'F\'" "\'G\'" }
+            default_value {"\'G\'"}
+            description   "
+               This selects the GPIO port associated with the interrupt pin
+               connected to the external Ethernet controller."
+        }
+        
+        cdl_option CYGHWR_HAL_SPIETH_INTERRUPT_PIN {
+            display       "Interrupt pin number"
+            active_if     CYGINT_IO_ETH_INT_SUPPORT_REQUIRED 
+            flavor        data
+            legal_values  0 to 15
+            default_value 15
+            description   "
+               This selects the pin number within the GPIO port associated with
+               the interrupt pin connected to the external Ethernet controller."
+        }
+
+        cdl_option CYGNUM_HAL_SPIETH_INTERRUPT_PRIORITY {
+            display       "Interrupt priority"
+            active_if     CYGINT_IO_ETH_INT_SUPPORT_REQUIRED 
+            flavor        data
+            legal_values  { 0xe0 0xd0 0xc0 0xb0 0xa0 0x90 0x80
+                            0x70 0x60 0x50 0x40 0x30 0x20 0x10 0x00}
+            default_value 0xe0
+            description   "
+               Enter the interrupt priority used for the interrupt
+               connected to the external Ethernet controller. A
+               lower number means a higher priority."
+        }
+    }
+
     cdl_component CYGBLD_GLOBAL_OPTIONS {
         display "Global build options"
         flavor  none
@@ -310,15 +443,7 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM
             configuration."
 
         requires { CYGNUM_REDBOOT_FLASH_BASE == 0x64000000 }
-
-        cdl_option CYGPRI_HAL_STM3210E_EVAL_MEM_SEGMENTS {
-            display       "Set RedBoot memory segments"
-            requires      { CYGBLD_REDBOOT_MAX_MEM_SEGMENTS == 3 }
-            no_define
-            calculated    2
-            description   "This CDL option is used to inform RedBoot of the
-                           number of RAM memory segments on this platform."
-        }
+        requires { CYGBLD_REDBOOT_MAX_MEM_SEGMENTS == 2 }
 
         cdl_option CYGBLD_BUILD_REDBOOT_BIN {
             display       "Build Redboot ROM binary images"
@@ -357,7 +482,6 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM
                      build process to be converted to S-Record and binary
                      files."
     }
-    
     cdl_component CYGHWR_HAL_CORTEXM_STM3210E_EVAL_NAND {
         display       "STM3210E EVAL NAND support"
         parent        CYGPKG_IO_NAND
diff --git a/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.h b/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.h
@@ -0,0 +1,21 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x68000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff --git a/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.ldi b/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.ldi
@@ -0,0 +1,36 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00010000
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00080000
+    rom   : ORIGIN = 0x64000000, LENGTH = 0x01000000
+    ram   : ORIGIN = 0x68000000, LENGTH = 0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_sram (sram, 0x20000400, LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, 0x68008000+CYGMEM_HAL_CORTEXM_STM32_STM3210E_EXTRA_BASE_RAM, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x68100000;
diff --git a/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h b/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h
+++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h
@@ -71,6 +71,95 @@
 
 #define HAL_AM29XXXXX_UNCACHED_ADDRESS(__addr) (__addr)
 
+//=============================================================================
+// I2C busses and devices
+
+# define HAL_I2C_EXPORTED_DEVICES                                       \
+    __externC cyg_i2c_bus                  hal_stm32_i2c_bus1;          \
+    __externC cyg_i2c_device               hal_stm32_i2c_temperature;
+
+
+//=============================================================================
+// I2C bus pin configurations
+
+#if defined(CYGHWR_HAL_STM32_I2C1_REMAP)
+#define CYGHWR_HAL_STM32_I2C1_SCL               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  8, NA, OPENDRAIN, NA, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_I2C1_SDA               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  9, NA, OPENDRAIN, NA, AT_LEAST(50) )
+#else
+#define CYGHWR_HAL_STM32_I2C1_SCL               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  6, NA, OPENDRAIN, NA, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_I2C1_SDA               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  7, NA, OPENDRAIN, NA, AT_LEAST(50) )
+#endif
+
+#define CYGHWR_HAL_STM32_I2C1_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 6, 0, M2P )
+#define CYGHWR_HAL_STM32_I2C1_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 7, 0, P2M )
+
+
+#define CYGHWR_HAL_STM32_I2C2_SCL               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 10, NA, OPENDRAIN, NA, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_I2C2_SDA               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 11, NA, OPENDRAIN, NA, AT_LEAST(50) )
+
+#define CYGHWR_HAL_STM32_I2C2_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 4, 0, M2P )
+#define CYGHWR_HAL_STM32_I2C2_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 5, 0, P2M )
+
+//=============================================================================
+// SPI bus pin configurations
+
+// NOTE: The SPEED_SPI manifest is declared by the device driver
+// (e.g. "devs/spi/cortexm/stm32/<vsn>/src/spi_stm32.c") and is not
+// currently defined in a header.
+
+#ifndef CYGHWR_HAL_STM32_SPI1_REMAP
+#define CYGHWR_HAL_STM32_SPI1_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  5, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI1_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A,  6, NA, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI1_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  7, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI1_REMAP_CONFIG      0
+#else
+#define CYGHWR_HAL_STM32_SPI1_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  3, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI1_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B,  4, NA, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI1_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  5, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI1_REMAP_CONFIG      CYGHWR_HAL_STM32_AFIO_MAPR_SPI1_RMP
+#endif
+
+#define CYGHWR_HAL_STM32_SPI1_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 3, 0, M2P )
+#define CYGHWR_HAL_STM32_SPI1_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 2, 0, P2M )
+
+
+#define CYGHWR_HAL_STM32_SPI2_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 13, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI2_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B, 14, NA, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI2_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 15, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI2_REMAP_CONFIG      0
+
+#define CYGHWR_HAL_STM32_SPI2_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 5, 0, M2P )
+#define CYGHWR_HAL_STM32_SPI2_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 4, 0, P2M )
+
+
+
+#ifndef CYGHWR_HAL_STM32_SPI3_REMAP
+#define CYGHWR_HAL_STM32_SPI3_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  3, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI3_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B,  4, NA, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI3_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  5, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI3_REMAP_CONFIG      0
+#else
+#define CYGHWR_HAL_STM32_SPI3_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI3_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C, 11, NA, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI3_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 12, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI3_REMAP_CONFIG      CYGHWR_HAL_STM32_AFIO_MAPR_SPI3_RMP
+#endif
+
+#define CYGHWR_HAL_STM32_SPI3_DMA_TX            CYGHWR_HAL_STM32_DMA( 2, 2, 0, M2P )
+#define CYGHWR_HAL_STM32_SPI3_DMA_RX            CYGHWR_HAL_STM32_DMA( 2, 1, 0, P2M )
+
+
+//=============================================================================
+// Optional enc424j600 Ethernet over SPI
+
+#ifdef CYGPKG_DEVS_ETH_ENC424J600
+struct cyg_netdevtab_entry;
+__externC void cyg_devs_cortexm_stm3210e_enc424j600_init( struct cyg_netdevtab_entry * );
+#define CYG_DEVS_ETH_ENC424J600_PLF_INIT( _tab_ ) \
+			cyg_devs_cortexm_stm3210e_enc424j600_init( _tab_ )
+
+#endif
+
 //-----------------------------------------------------------------------------
 // end of plf_io.h
 #endif // CYGONCE_HAL_PLF_IO_H
diff --git a/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_JTAG.ecm b/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_JTAG.ecm
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_JTAG.ecm
+++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_JTAG.ecm
@@ -62,6 +62,14 @@ cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXE
      user_value 0
 };
 
+cdl_option CYGOPT_REDBOOT_FIS_REDBOOT {
+    user_value 0
+};
+
+cdl_component CYGOPT_REDBOOT_FIS_REDBOOT_POST {
+    user_value 0
+};
+
 cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
     inferred_value 1 <cyg/libc/string/string.h>
 };
@@ -83,3 +91,9 @@ cdl_option CYGBLD_ISO_STRING_STRFUNCS_HE
 };
 
 
+cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_DEVICES {
+    user_value 1 "0x08000000"
+};
+
+
+
diff --git a/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_ROM.ecm b/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_ROM.ecm
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_ROM.ecm
+++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_ROM.ecm
@@ -62,6 +62,14 @@ cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXE
      user_value 0
 };
 
+cdl_option CYGOPT_REDBOOT_FIS_REDBOOT {
+    user_value 0
+};
+
+cdl_component CYGOPT_REDBOOT_FIS_REDBOOT_POST {
+    user_value 0
+};
+
 cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
     inferred_value 1 <cyg/libc/string/string.h>
 };
@@ -83,3 +91,8 @@ cdl_option CYGBLD_ISO_STRING_STRFUNCS_HE
 };
 
 
+cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_DEVICES {
+    user_value 1 "0x08000000"
+};
+
+
diff --git a/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_eth_enc424j600.c b/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_eth_enc424j600.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_eth_enc424j600.c
@@ -0,0 +1,148 @@
+/*==========================================================================
+//
+//      stm3210e_eval_eth_enc424j600.c
+//
+//      Setup for optional enc424j600 Ethernet over SPI
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija Stanislevik
+// Date:         2012-04-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <cyg/hal/hal_io.h>
+
+#include <cyg/io/spi.h>
+#include <cyg/io/spi_stm32.h>
+#include <cyg/io/eth/netdev.h>
+#include <cyg/io/eth/eth_drv.h>
+#include <cyg/io/eth/enc424j600_eth.h>
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+// Set to: 1 for diagnostic printouts; 0 for no diagnostic printouts.
+#define DEBUG_ENC424J600_PLATFORM_INIT 0
+
+// SPI device for communication with enc424j600 Ethernet chip
+#define TRANS8B            false
+#define CLK_IDLE_LOW        0
+#define CLK_PHASE_RISING    0
+
+#define AUX_SPI_CORTEXM_STM32_DEVICE(_name_, _bus_)     \
+    CYG_DEVS_SPI_CORTEXM_STM32_DEVICE(                  \
+        _name_##_spi,                                   \
+        _bus_,                                          \
+        CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_CS,         \
+        TRANS8B,                                        \
+        CLK_IDLE_LOW,                                   \
+        CLK_PHASE_RISING,                               \
+        14000000,                                       \
+        1,                                              \
+        1,                                              \
+        1                                               \
+    )
+
+AUX_SPI_CORTEXM_STM32_DEVICE
+(
+    CYGDAT_IO_ETH_ENC424J600_NAME,
+    CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS
+);
+
+// Code to initialize enc424j600 driver data structure.
+
+void cyg_devs_cortexm_stm3210e_enc424j600_init( struct cyg_netdevtab_entry * netdevtab_entry)
+{
+    struct eth_drv_sc *eth_inst = NULL;          // pointer to device instance
+    enc424j600_priv_data_t *eth_inst_pd = NULL;  // device's private data
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    cyg_uint32 cr;
+    cyg_uint32 backupr;
+#endif
+
+//  Assign SPI device to Ethernet device.
+    eth_inst = netdevtab_entry->device_instance;
+    eth_inst_pd = (enc424j600_priv_data_t *)eth_inst->driver_private;
+
+#if DEBUG_ENC424J600_PLATFORM_INIT & 1
+    diag_printf("%s(): Assigning SPI device to Ethernet device %s.\n",__FUNCTION__, netdevtab_entry->name);
+#endif
+    eth_inst_pd->spi_service_device = (cyg_spi_device *) &CYGDAT_IO_ETH_ENC424J600_NAME_spi_stm32;
+
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+
+// Interrupt output from enc424j600 is connected to one of the pins from ports A-G.
+// Here this pin is marshaled to External Interrupt Controller (EXTI).
+
+#define ENC424J600_INTERRUPT_SOURCE_PIN  CYGHWR_HAL_SPIETH_INTERRUPT_PIN
+#define ENC424J600_EXTICR                ((ENC424J600_INTERRUPT_SOURCE_PIN / 4) * 4 + 8)
+#define ENC424J600_SHIFT_VALUE           ((ENC424J600_INTERRUPT_SOURCE_PIN % 4) * 4)
+
+#if DEBUG_ENC424J600_PLATFORM_INIT & 1
+    diag_printf("%s(): Mapping external interrupt from P%c%d.\n",__FUNCTION__,
+                CYGHWR_HAL_CORTEXM_STM32_SPIETH_INTERRUPT_PORT,
+                ENC424J600_INTERRUPT_SOURCE_PIN);
+#endif
+
+    // Is AFIO clock enabled?
+    HAL_READ_UINT32(CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB2ENR , backupr );
+    if (0 == (backupr & BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_AFIO)))
+    {
+        CYGHWR_HAL_STM32_CLOCK_ENABLE(CYGHWR_HAL_STM32_CLOCK(APB2,AFIO));
+    }
+
+    // Modify External Interrupt Control Register
+    HAL_READ_UINT32(CYGHWR_HAL_STM32_AFIO + ENC424J600_EXTICR , cr );
+    cr |= ((cyg_uint32)0xf << ENC424J600_SHIFT_VALUE);
+    cr &= (((cyg_uint32)(CYGHWR_HAL_CORTEXM_STM32_SPIETH_INTERRUPT_PORT - 'A')
+                            << ENC424J600_SHIFT_VALUE) & 0xffff);
+    HAL_WRITE_UINT32(CYGHWR_HAL_STM32_AFIO + ENC424J600_EXTICR , cr );
+
+    // Restore AFIO clock
+    if (0 == (backupr & BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_AFIO)))
+    {
+        CYGHWR_HAL_STM32_CLOCK_DISABLE(CYGHWR_HAL_STM32_CLOCK(APB2,AFIO));
+    }
+
+#endif  //  #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+}
+
+//==========================================================================
+// EOF stm3210e_eval_eth_enc424j600.c
diff --git a/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_flash.c b/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_flash.c
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_flash.c
+++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_flash.c
@@ -60,12 +60,13 @@
 #include <cyg/hal/hal_io.h>
 
 
+#ifdef CYGHWR_HAL_CORTEXM_STM32_FLASH_INTERNAL
 //--------------------------------------------------------------------------
 // Internal flash
 
 #include <cyg/io/stm32_flash.h>
 
-cyg_stm32_flash_dev hal_stm32_flash_priv;
+const cyg_stm32_flash_dev hal_stm32_flash_priv;
 
 CYG_FLASH_DRIVER(hal_stm32_flash,
                  &cyg_stm32_flash_funs,
@@ -77,6 +78,9 @@ CYG_FLASH_DRIVER(hal_stm32_flash,
                  &hal_stm32_flash_priv
 );
 
+#endif // CYGHWR_HAL_CORTEXM_STM32_FLASH_INTERNAL
+
+#ifdef CYGHWR_HAL_CORTEXM_STM32_FLASH_NOR
 //--------------------------------------------------------------------------
 // There is a Spansion S29GL128P90FFIR20 or a NUMONYX equivalent.
 // These are AMD compatible and with CFI can all be handled by the AMD
@@ -105,5 +109,7 @@ CYG_FLASH_DRIVER(hal_stm3210e_flash,
                  hal_stm3210e_flash_priv.block_info,
                  &hal_stm3210e_flash_priv);
 
+#endif // CYGHWR_HAL_CORTEXM_STM32_FLASH_NOR
+
 //--------------------------------------------------------------------------
 // EOF stm3210e_eval_flash.c
diff --git a/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_misc.c b/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_misc.c
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_misc.c
+++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_misc.c
@@ -76,25 +76,25 @@
 {
     CYG_ADDRESS base;
     
-#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_SRAM)
+#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_ROMINT) | defined(CYG_HAL_STARTUP_SRAM)
     
     // Enable peripheral clocks in RCC
 
     base = CYGHWR_HAL_STM32_RCC;
     
     HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHBENR,
-                     CYGHWR_HAL_STM32_RCC_AHBENR_FSMC |
-                     CYGHWR_HAL_STM32_RCC_AHBENR_FLITF|
-                     CYGHWR_HAL_STM32_RCC_AHBENR_SRAM );
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHBENR_FSMC)  |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHBENR_FLITF) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHBENR_SRAM)  );
 
     HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_APB2ENR,
-                     CYGHWR_HAL_STM32_RCC_APB2ENR_IOPA |
-                     CYGHWR_HAL_STM32_RCC_APB2ENR_IOPB |
-                     CYGHWR_HAL_STM32_RCC_APB2ENR_IOPC |
-                     CYGHWR_HAL_STM32_RCC_APB2ENR_IOPD |
-                     CYGHWR_HAL_STM32_RCC_APB2ENR_IOPE |
-                     CYGHWR_HAL_STM32_RCC_APB2ENR_IOPF |
-                     CYGHWR_HAL_STM32_RCC_APB2ENR_IOPG);
+                     BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPA) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPB) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPC) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPD) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPE) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPF) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPG) );
 
     // Set all unused GPIO lines to input with pull down to prevent
     // them floating and annoying any external hardware.
@@ -237,6 +237,11 @@ cyg_plf_memory_segment(int seg, unsigned
         *start = (unsigned char *)CYGMEM_REGION_sram;
         *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
         break;
+#elif defined(CYGMEM_REGION_xram)
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_xram;
+        *end = (unsigned char *)(CYGMEM_REGION_xram + CYGMEM_REGION_xram_SIZE);
+        break;
 #endif
     default:
         *start = *end = NO_MEMORY;
diff --git a/packages/hal/cortexm/stm32/stm32f4discovery/current/ChangeLog b/packages/hal/cortexm/stm32/stm32f4discovery/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/ChangeLog
@@ -0,0 +1,42 @@
+2013-08-09  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal_cortexm_stm32_stm32f4discovery.cdl: Merge CDL goal
+	expressions to avoid confusing the eCos Configuration Tool during
+	initial inference of STM32 variant HAL options.
+
+2013-06-09  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal_cortexm_stm32_stm32f4discovery.cdl,
+	include/plf_arch.h, include/plf_intr.h, include/plf_io.h,
+	include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.h,
+	include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.ldi,
+	include/pkgconf/mlt_cortexm_stm32f4discovery_rom.h,
+	include/pkgconf/mlt_cortexm_stm32f4discovery_rom.ldi,
+	src/stm32f4discovery_flash.c, src/stm32f4discovery_misc.c,
+	tests/gpio.c, misc/openocd-misc.cfg, doc/stm32f4discovery.sgml:
+	New STM32F4-Discovery platform HAL package. Derived from
+	STM32x0G-EVAL platform HAL package.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/packages/hal/cortexm/stm32/stm32f4discovery/current/cdl/hal_cortexm_stm32_stm32f4discovery.cdl b/packages/hal/cortexm/stm32/stm32f4discovery/current/cdl/hal_cortexm_stm32_stm32f4discovery.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/cdl/hal_cortexm_stm32_stm32f4discovery.cdl
@@ -0,0 +1,289 @@
+##==========================================================================
+##
+##      hal_cortexm_stm32_stm32f4discovery.cdl
+##
+##      Cortex-M STM32F4-Discovery platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2013 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    jld
+## Based on:     stm32x0g_eval CDL by jlarmour
+## Date:         2013-06-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY {
+    display       "STMicroelectronics STM32F4-Discovery board HAL"
+    parent        CYGPKG_HAL_CORTEXM_STM32
+
+    requires      { CYGHWR_HAL_CORTEXM == "M4" }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4" &&
+                    CYGHWR_HAL_CORTEXM_STM32_F4 == "F407VG" }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE == "HSE" }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 8 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL == 336 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV == 2 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV == 7 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 1 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 4 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 2 }
+
+    include_dir   cyg/hal
+    hardware
+    doc           ref/hal-cortexm-stm32f4discovery-part.html
+    description   "
+        The STM32F4-Discovery HAL package provides the support needed to run
+        eCos on the STMicroelectronics STM32F4-Discovery board."
+
+    compile       stm32f4discovery_misc.c
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_stm32.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"STMicroelectronics STM32F4-Discovery\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    # use UART4 at PC10,11 for diagnostic I/O (named UART3 in the STM32 variant HAL)
+    implements CYGINT_HAL_STM32_UART3
+
+    implements CYGINT_HAL_FPV4_SP_D16
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value {"JTAG"}
+        legal_values  {"JTAG" "ROM"}
+        no_define
+        define -file system.h CYG_HAL_STARTUP
+        description   "
+            Select 'JTAG' when building applications to download into on-chip RAM
+            using the on-board ST-LINK/V2 serial wire debugging interface. Select
+            'ROM' when building an application which will be written to on-chip
+            Flash memory for immediate execution on system reset."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated    { (CYG_HAL_STARTUP == "ROM"    ) ? "cortexm_stm32f4discovery_rom"      :
+                        (CYG_HAL_STARTUP == "JTAG"   ) ? "cortexm_stm32f4discovery_jtag"     :
+                                                         "undefined" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+                display "Memory layout linker script fragment"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+                display "Memory layout header file"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_H
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+
+    }
+
+    cdl_option CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK {
+        display         "Input clock frequency"
+        flavor          data
+        default_value   8000000
+        legal_values    0 to 1000000000
+        description     "Main clock input."
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES {
+        display         "Flash read wait states"
+        flavor          data
+        default_value   5
+        legal_values    0 to 7
+        description     "
+            This option gives the number of wait states to use for accessing
+            the flash for reads. The correct setting for this value depends
+            on both the CPU clock (HCLK) frequency and the voltage. Consult
+            the STM32 Flash programming manual (PM0059) for appropriate
+            values for different clock speeds or voltages. The default of
+            5 reflects a supply voltage of 3.3V and HCLK of 168MHz."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH {
+        display         "Flash driver support"
+        parent          CYGPKG_IO_FLASH
+        active_if       CYGPKG_IO_FLASH
+        compile         -library=libextras.a stm32f4discovery_flash.c
+        default_value   1
+        description     "Control flash device support for STM32F4-Discovery board."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        calculated       0
+        description      "
+            The STM32F4-Discovery board has one serial port enabled. This option
+            informs the rest of the system which port will be used to connect
+            to a host running GDB."
+     }
+
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Diagnostic serial port"
+         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         calculated       0
+         description      "
+            The STM32F4-Discovery board has one serial port enabled. This option
+            informs the rest of the system which port will be used for
+            diagnostic output."
+     }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Diagnostic serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 115200
+        description   "
+            This option controls the default baud rate used for the
+            console connection."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "Debug serial port baud rate"
+        flavor        data
+        calculated    CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+            Global build options including control over
+            compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_OPTIONS {
+        display "STM32F4-Discovery HAL build options"
+        flavor  none
+        description   "
+            Package specific build options including control over
+            compiler flags used only in building this HAL package."
+
+        cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "-Werror" }
+            description   "
+                This option modifies the set of compiler flags
+                for building this HAL. These flags are used
+                in addition to the set of global flags."
+        }
+        cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags
+                for building this HAL. These flags are
+                removed from the set of global flags if
+                present."
+        }
+    }
+
+    cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_TESTS {
+        display "STM32F4-Discovery tests"
+        flavor  data
+        no_define
+        calculated { "tests/gpio" }
+        description   "
+            This option specifies the set of tests for the STM32F4-Discovery HAL."
+    }
+
+}
+
+# EOF hal_cortexm_stm32_stm32f4discovery.cdl
diff --git a/packages/hal/cortexm/stm32/stm32f4discovery/current/doc/stm32f4discovery.sgml b/packages/hal/cortexm/stm32/stm32f4discovery/current/doc/stm32f4discovery.sgml
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/doc/stm32f4discovery.sgml
@@ -0,0 +1,215 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     stm32f4discovery.sgml                                       -->
+<!--                                                                 -->
+<!--     STM32F4-Discovery platform HAL documentation                -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2003, 2004, 2008, 2013 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   jld                                                -->
+<!-- Based on:    M5272C3 documentation by bartv                     -->
+<!-- Date:        2013-06-07                                         -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<part id="hal-cortexm-stm32f4discovery-part"><title>STMicroelectronics STM32F4-Discovery Board Support</title>
+
+<refentry id="cortexm-stm32f4discovery">
+  <refmeta>
+    <refentrytitle>Overview</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>eCos Support for the STMicroelectronics STM32F4-Discovery Board</refname>
+    <refpurpose>Overview</refpurpose>
+  </refnamediv>
+
+  <refsect1 id="cortexm-stm32f4discovery-description"><title>Description</title>
+    <para>
+The STMicroelectronics STM32F4-Discovery board has an STM32F407VGT6 Cortex-M4F processor,
+192KiB of on-chip SRAM, 1MiB of on-chip flash memory, plus motion and audio sensors, an
+audio DAC and a connector for the on-chip USB peripheral. The board also
+features an ST-LINK/V2 serial wire debug (SWD) interface.
+    </para>
+    <para>
+For typical eCos development the ST-LINK/V2 interface is connected via USB to a host
+computer running the OpenOCD on-chip debug tool. OpenOCD provides a GDB server enabling
+the download and debuging of eCos applications via the GDB debugger.
+    </para>
+  </refsect1>
+
+  <refsect1 id="cortexm-stm32f4discovery-hardware"><title>Supported Hardware</title>
+    <para>
+By default, eCos will use the 128KiB of contiguous on-chip SRAM, accessible
+at location 0x20000000. On-chip flash memory at 0x08000000 can be optionally
+used for bootable application code. A further 64KiB of core coupled memory (CCM)
+is mapped to location 0x10000000. This memory is not used by eCos but may be used
+for application-defined static data structures such as thread stacks which require no
+initialization other than that performed during eCos startup and application
+execution. Data structures may be assigned to the <varname>.ccm</varname> section
+within CCM memory using the eCos <varname>CYGBLD_ATTRIB_SECTION</varname> macro. For example:
+    </para>
+    <programlisting>char thread_stack[4096] CYGBLD_ATTRIB_SECTION(".ccm");</programlisting>
+    <para>
+There is a serial driver <varname>CYGPKG_IO_SERIAL_CORTEXM_STM32</varname>
+which supports all on-chip UARTs. However, there are no RS232 drivers or
+serial connectors on the board. STM32 UART4 (named UART3 in the eCos serial driver) is
+enabled for use as a diagnostics channel.
+    </para>
+    <para>
+The GPIO ports are enabled and manipulated only as needed
+to access UART4, the LEDs and the push button. eCos does not
+enable the remaining on-chip peripherals.
+    </para>
+  </refsect1>
+  <refsect1 id="cortexm-stm32f4discovery-tools"><title>Tools</title>
+    <para>
+The STM32F4-Discovery board port is intended to work with GNU tools
+configured for an arm-eabi target. The original porting work was performed using
+binutils 2.18.50.20080513, arm-eabi-gcc 4.3.2, arm-eabi-gdb 7.4.1 and OpenOCD 0.6.1.
+    </para>
+  </refsect1>
+</refentry>
+
+<refentry id="cortexm-stm32f4discovery-setup">
+  <refmeta>
+    <refentrytitle>Setup</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>Setup</refname>
+    <refpurpose>Preparing for eCos Development with the STM32F4-Discovery board</refpurpose>
+  </refnamediv>
+
+  <refsect1 id="cortexm-stm32f4discovery-overview"><title>Overview</title>
+    <para>
+In a typical development environment the STM32F4-Discovery board is halted
+on reset using OpenOCD communicating via the ST-LINK/V2 SWD interface. eCos
+applications are configured for JTAG startup, then downloaded to the board
+and executed via the arm-eabi-gdb debugger.
+    </para>
+    <para>
+OpenOCD may be configured for use with the STM32F4-Discovery board using the
+board configuration script <filename>stm32f4discovery.cfg</filename> provided with the tool.
+It is also necessary to define a handler for GDB attach events which will halt the board. A
+suitable OpenOCD script is provided at <filename>misc/openocd-misc.cfg</filename> in the
+STM32F4-Discovery platform HAL package. Both scripts may be specified on the OpenOCD
+command line.
+    </para>
+  </refsect1>
+  <refsect1 id="cortexm-stm32f4discovery-config-diagnostic"><title>Diagnostic output</title>
+    <para>
+For diagnostic output, a SparkFun FTDI 3.3v Basic Breakout board or similar
+may be connected to UART4 of the STM32F4-Discovery board using jumper wires as follows:
+    </para>
+    <informaltable frame="all">
+        <tgroup cols="3" colsep="1" rowsep="1" align="left">
+            <thead>
+	        <row>
+                    <entry>Function</entry>
+                    <entry>STM32F4-Discovery header</entry>
+                    <entry>SparkFun FTDI breakout board socket</entry>
+                </row>
+            </thead>
+            <tbody>
+	        <row>
+                    <entry>UART4 Tx</entry>
+                    <entry>PC10</entry>
+                    <entry>RXI</entry>
+                </row>
+                <row>
+                    <entry>Ground</entry>
+                    <entry>GND</entry>
+                    <entry>GND</entry>
+                </row>
+            </tbody>
+        </tgroup>
+    </informaltable>
+    <para>
+The UART is configured at 115200 baud by default and runs with 8 bits,
+no parity, and 1 stop bit. The baud rate can be changed via the
+configuration option <varname>CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD</varname>.
+    </para>
+  </refsect1>
+</refentry>
+
+<refentry id="cortexm-stm32f4discovery-config">
+  <refmeta>
+    <refentrytitle>Configuration</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>Configuration</refname>
+    <refpurpose>Platform-specific Configuration Options</refpurpose>
+  </refnamediv>
+
+  <refsect1 id="cortexm-stm32f4discovery-config-overview"><title>Overview</title>
+    <para>
+The STM32F4-Discovery platform HAL package is loaded automatically when eCos is
+configured for an STM32F4-Discovery target. It should never be necessary to load
+this package explicitly. Unloading of the package should only occur as a result
+of switching target hardware.
+    </para>
+  </refsect1>
+
+  <refsect1 id="cortexm-stm32f4discovery-config-startup"><title>Startup</title>
+    <para>
+The STM32F4-Discovery platform HAL package supports two startup types which may be
+selected using the configuration option <varname>CYG_HAL_STARTUP</varname>:
+    </para>
+    <variablelist>
+      <varlistentry>
+        <term>JTAG</term>
+        <listitem><para>
+This is the startup type which is normally used during application
+development. <application>arm-eabi-gdb</application> is used to download a JTAG
+startup application into memory via OpenOCD and the ST-LINK/V2 SWD debug interface.
+eCos startup code will perform all necessary hardware initialization.
+        </para></listitem>
+      </varlistentry>
+      <varlistentry>
+        <term>ROM</term>
+        <listitem><para>
+This startup type can be used for finished applications which will
+be programmed into flash at location 0x08000000. It can also be used for
+debugging larger applications which do not fit in available SRAM. The
+application must be programmed to flash using the ST-LINK tool before debugging commences.
+eCos startup code will perform all necessary hardware initialization.
+        </para></listitem>
+      </varlistentry>
+    </variablelist>
+  </refsect1>
+
+  <refsect1 id="cortexm-stm32f4discovery-config-flash"><title>Flash Driver</title>
+    <para>
+The platform HAL package contains flash driver support. This support may be
+activated by loading the eCos flash I/O infrastructure package <varname>CYGPKG_IO_FLASH</varname>.
+    </para>
+  </refsect1>
+
+  <refsect1 id="cortexm-stm32f4discovery-config-clock"><title>System Clock</title>
+    <para>
+By default the system clock interrupts once every 10ms, corresponding
+to a 100Hz clock. This period can be modified using the configuration option
+<varname>CYGNUM_HAL_RTC_PERIOD</varname>.
+    </para>
+  </refsect1>
+</refentry>
+
+</part>
+
+<!-- EOF stm32f4discovery.sgml -->
diff --git a/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.h b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.h
@@ -0,0 +1,21 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x20000000)
+#define CYGMEM_REGION_ram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.ldi b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.ldi
@@ -0,0 +1,43 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram   : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// SRAM is 128k.
+hal_startup_stack = 0x20000000 + 1024*128;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    USER_SECTION (ccm, ccm, 0x10000000, LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, hal_virtual_vector_table_end, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.h b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.h
@@ -0,0 +1,21 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x20000000)
+#define CYGMEM_REGION_ram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.ldi b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.ldi
@@ -0,0 +1,43 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram   : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// SRAM is 128k.
+hal_startup_stack = 0x20000000 + 1024*128;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    USER_SECTION (ccm, ccm, 0x10000000, LMA_EQ_VMA)
+    SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA)
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (ram, hal_virtual_vector_table_end, FOLLOWING (.got))
+    SECTION_data (ram, ALIGN( 0x8), FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_arch.h b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_arch.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_arch.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jld
+// Based on:    stm32x0g_eval overrides by nickg
+// Date:        2013-06-06
+// Purpose:     STM32F4-Discovery platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_intr.h b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_intr.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jld
+// Based on:    stm32x0g_eval overrides by nickg
+// Date:        2013-06-06
+// Purpose:     STM32F4-Discovery platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_io.h b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_io.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_io.h
@@ -0,0 +1,67 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jld
+// Date:        2013-06-06
+// Purpose:     STM32F4-Discovery platform specific registers
+// Description: 
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>
+
+// User LEDs and button
+
+#define CYGHWR_HAL_STM32F4DISCOVERY_LED1 CYGHWR_HAL_STM32_PIN_OUT( D, 12, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32F4DISCOVERY_LED2 CYGHWR_HAL_STM32_PIN_OUT( D, 13, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32F4DISCOVERY_LED3 CYGHWR_HAL_STM32_PIN_OUT( D, 14, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32F4DISCOVERY_LED4 CYGHWR_HAL_STM32_PIN_OUT( D, 15, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32F4DISCOVERY_BTN1 CYGHWR_HAL_STM32_PIN_IN( A, 0, NONE )
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/packages/hal/cortexm/stm32/stm32f4discovery/current/misc/openocd-misc.cfg b/packages/hal/cortexm/stm32/stm32f4discovery/current/misc/openocd-misc.cfg
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/misc/openocd-misc.cfg
@@ -0,0 +1,54 @@
+##==========================================================================
+##
+##      openocd-misc.cfg
+##
+##      Cortex-M STM32F4-Discovery OpenOCD miscellaneous definitions
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2013 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    jld
+## Date:         2013-06-09
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+gdb_memory_map disable
+stm32f4x.cpu configure -event gdb-attach {
+    reset init
+}
+
+# EOF openocd-misc.cfg
diff --git a/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_flash.c b/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_flash.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_flash.c
@@ -0,0 +1,65 @@
+/*==========================================================================
+//
+//      stm32f4discovery_flash.c
+//
+//      Cortex-M4 STM32F4-Discovery Flash setup
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jld
+// Based on:     stm32x0g_eval flash setup by jlarmour
+// Date:         2013-06-06
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <cyg/io/flash_dev.h>
+#include <cyg/io/stm32_flash.h>
+
+CYG_FLASH_DRIVER(hal_stm32_flash,
+                 &cyg_stm32_flash_funs,
+                 0,
+                 0x08000000,
+                 0,
+                 0,
+                 0,
+                 &hal_stm32_flash_priv
+);
+
+//--------------------------------------------------------------------------
+// EOF stm32f4discovery_flash.c
diff --git a/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_misc.c b/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_misc.c
@@ -0,0 +1,147 @@
+/*==========================================================================
+//
+//      stm32f4discovery_misc.c
+//
+//      Cortex-M4 STM32F4-Discovery HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011, 2012, 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jld
+// Based on:     stm32x0g_eval misc setup by jlarmour
+// Date:         2013-06-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_stm32.h>
+#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>
+
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_if.h>
+
+//==========================================================================
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+#if (CYGNUM_CALL_IF_TABLE_SIZE > 64)
+// We force a compilation error for this fatal condition since run-time asserts
+// may not be enabled for the build.
+#error "The CALL_IF_TABLE_SIZE pre-allocation in the linker scripts for this platform need to be updated"
+#endif
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void hal_system_init( void )
+{
+    CYG_ADDRESS base;
+
+    // Enable CCM clock and any required GPIO ports in RCC
+    base = CYGHWR_HAL_STM32_RCC;
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB1ENR,
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_CCMDATARAMEN) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOA) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOC) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOD) );
+
+    // Set unused lines on enabled GPIO ports to input with pull down
+
+    // GPIO Port A - setup PA0 for button, PA9 for LED, PA13,14 for SWD
+    base = CYGHWR_HAL_STM32_GPIOA;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x82A8AAA8 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x28040000 );
+
+    // GPIO Port C - setup PC10,11 for RS232 (UART4)
+    base = CYGHWR_HAL_STM32_GPIOC;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAA0AAAAA );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00A00000 );
+
+    // GPIO Port D - setup PD5,12,13,14,15 for LEDs
+    base = CYGHWR_HAL_STM32_GPIOD;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x00AAA2AA );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x55000400 );
+
+    // Enable flash prefetch buffer, cacheability and set latency to 2 wait states
+    // Latency has to be set before clock is switched to a higher speed
+    {
+        cyg_uint32 acr;
+
+        base = CYGHWR_HAL_STM32_FLASH;
+
+        HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_PRFTEN;
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_DCEN|CYGHWR_HAL_STM32_FLASH_ACR_ICEN;
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES);
+        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+    }
+}
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+#ifdef CYGDBG_USE_ASSERTS
+    __externC char __sram_data_start[];
+#endif
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    // Check the number of VSRs matches the linker script. We can do this
+    // because we intend the VV table to follow the VSR table with no gaps.
+    CYG_ASSERT( (char*)&hal_virtual_vector_table[0] - (char*)&hal_vsr_table >= CYGNUM_HAL_VSR_COUNT*4,
+                "VSR table size does not match" );
+    // Now check the declared start of SRAM data follows the VV table end
+    CYG_ASSERT( (__sram_data_start - (char*)&hal_virtual_vector_table[0]) >= CYGNUM_CALL_IF_TABLE_SIZE*4,
+                "VV table size does not match sram space" );
+#else
+    // Check the VSR table fits below declared start of SRAM data
+    CYG_ASSERT( (__sram_data_start - (char*)&hal_vsr_table[0]) >= CYGNUM_HAL_VSR_COUNT*4,
+                "VSR table size does not match" );
+#endif
+}
+
+//==========================================================================
+// EOF stm32f4discovery_misc.c
diff --git a/packages/hal/cortexm/stm32/stm32f4discovery/current/tests/gpio.c b/packages/hal/cortexm/stm32/stm32f4discovery/current/tests/gpio.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32f4discovery/current/tests/gpio.c
@@ -0,0 +1,73 @@
+/*=============================================================================
+//
+//      gpio.c
+//
+//      Test for STM32F4-Discovery GPIO
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jld
+// Date:         2013-06-07
+//              
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <cyg/infra/testcase.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/var_io.h>
+
+externC void cyg_start(void) {
+    int b, n;
+    CYG_TEST_INIT();
+    CYG_TEST_INFO( "Starting STM32F4-Discovery GPIO test" );
+    CYG_TEST_INFO( "Press and hold user button for slow LED count" );
+    for ( n = 0; n < 0x100; n++ ) {
+    	// display least significant 4 bits of count on user LEDs
+        CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED1, 0 != (n & 0x1) );
+        CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED2, 0 != (n & 0x2) );
+        CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED3, 0 != (n & 0x4) );
+        CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED4, 0 != (n & 0x8) );
+        // extend delay from 125ms to 500ms when user button pressed
+        CYGHWR_HAL_STM32_GPIO_IN( CYGHWR_HAL_STM32F4DISCOVERY_BTN1, &b );
+        HAL_DELAY_US( 125000 * (1 + ( (b & 1) * 3) ) );
+    }
+    CYG_TEST_PASS_FAIL( 1, "STM32F4-Discovery GPIO test" );
+    CYG_TEST_FINISH( "STM32F4-Discovery GPIO test" );
+}
+
+//=============================================================================
+// EOF gpio.c
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/ChangeLog b/packages/hal/cortexm/stm32/stm32x0g_eval/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/ChangeLog
@@ -0,0 +1,199 @@
+2013-04-06  Jerzy Dyrda  <jerzdy@gmail.com>
+
+	* cdl/hal_cortexm_stm32_stm32x0g_eval.cdl: Fix PHY name and
+	added defualt Ethernet interface.
+	* src/stm32x0g_eval_misc.c: Enabled clock for PHY. [ Bugzilla 1001219 ]
+
+2013-03-09  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* misc/redboot_ROM_FPU.ecm: Add ECM for RedBoot with FPU support.
+
+2012-12-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_stm32_stm32x0g_eval.cdl: Implement CYGINT_HAL_FPV4_SP_D16.
+	[Bugzilla 1001607]
+
+2012-03-29  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi:
+	Correct number of VSR table entries.
+	* src/stm32x0g_eval_misc.c (hal_platform_init): Add assertion checks
+	that layout of vector tables at bottom of SRAM is what it should be.
+
+2012-03-29  James Smith  <jsmith@ecoscentric.com>
+
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi:
+	Provide hal_virtual_vector_table_end symbol to allow the
+	SECTION_sram pre-allocation to be minimised to the actual platform
+	requirements.
+
+	* src/stm32x0g_eval_misc.c: Provide #error check on linker script
+	hardwired CYGNUM_CALL_IF_TABLE_SIZE assumption.
+
+2012-03-23  James Smith  <jsmith@ecoscentric.com>
+
+	* include/plf_io.h: Update GPIO pin definitions to use new PIN
+	wrapper macros. Update the I2C lines to specify PULLUP.
+
+2012-03-22  James Smith  <jsmith@ecoscentric.com>
+
+	* include/plf_io.h (CYGHWR_HAL_STM32_ETH_MII_*): Platform specific
+	ethernet pin manifests updated to use new GPIO PIN macros.
+
+2012-03-15  James Smith  <jsmith@ecoscentric.com>
+
+	* cdl/hal_cortexm_stm32_stm32x0g_eval.cdl:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.h:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi:
+	* src/stm32x0g_eval_flash.c:
+	* src/stm32x0g_eval_misc.c:
+	* src/stm32x0g_eval_spi.c:
+	Rename platform from the name "stm3220g_eval" to the generic name
+	"stm32x0g_eval". This is to make it clear that the platform
+	supports both the F2 (STM3220G-EVAL) and F4 (STM3240G-EVAL)
+	platforms. This rename includes renaming of the relevant support
+	source files.
+
+	* include/plf_io.h (HAL_I2C_EXPORTED_DEVICES): Declare I2C bus1
+	for on-board M24C64 device.
+
+2012-02-08  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3220g_eval.cdl
+	(CYGPKG_HAL_CORTEXM_STM32_STM3220G_EVAL_SPI): This should now be a component
+	since it has no children. Also make description match configuration (Aardvark
+	expected to be on bus 2).
+
+2012-02-05  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* misc/redboot_JTAG.ecm, misc/redboot_ROM.ecm: Build in inferences
+	so there's no output on import.
+	* misc/redboot_RAM.ecm: New file. For completeness and to make it
+	easier for RedBoot to update itself.
+	* cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Make comment description of
+	UART selection and naming clearer.
+
+2012-01-31  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* include/plf_io.h: Prototype hal_stm3220_led() for setting board LEDs.
+	* src/stm3220g_eval_misc.c: Choose correct board SRAM memory timings.
+
+2012-01-13  Nick Garnett  <nickg@ecoscentric.com>
+
+	* misc/redboot_ROM.ecm:
+	* misc/redboot_JTAG.ecm: Add CYGPKG_IO_WALLCLOCK package to enable
+	date command for setting on-chip RTC.
+
+2012-01-12  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Add SPI and I2C
+	configuration options.
+
+	* include/plf_io.h: Add SPI and I2C pin and DMA stream definitions.
+
+	* src/stm3220g_eval_spi.c: Add SPI device definition for aardvark
+	board.
+
+2011-12-20  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Just set a requires on
+	RedBoot's number of memory segments to be 2 rather than using a
+	non-configurable option.
+
+2011-12-15  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3220g_eval.cdl
+	(CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES): New option. Configures
+	Flash wait states.
+	(CYGPKG_HAL_CORTEXM_STM32_STM3220G_EVAL_ETH0): New component. Holds
+	options and CDL to configure ethernet support.
+	Change default baud rate to 115200.
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_jtag.h: Add definitions for
+	sram and flash regions.
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_ram.h: Add definitions for
+	flash region.
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_sram.h: Ditto. Also fix
+	external SRAM address.
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_sram.ldi: Fix external SRAM
+	address.
+	* include/plf_io.h: Provide platform specific ethernet pin mappings.
+	(CYGHWR_HAL_STM32_ETH_CONFIGURE_MCO): New macro used to configure MCO1
+	as PHY clock.
+	* misc/redboot_JTAG.ecm, misc/redboot_ROM.ecm: Don't disable
+	CYGOPT_REDBOOT_FIS_REDBOOT nor CYGOPT_REDBOOT_FIS_REDBOOT_POST - there
+	is only one flash here and it does contain RedBoot.
+	* src/stm3220g_eval_flash.c: No longer define private flash structure
+	here. Internal flash support is no longer an option in this file if this
+	file is used at all.
+	* src/stm3220g_eval_misc.c (hal_system_init): Clear FSMC reset bit after
+	reset otherwise it stays there.
+	Configure USART4 TX/RX on PC10/11 otherwise RedBoot can get confused.
+	Set Flash wait states as per configuration.
+	(cyg_plf_memory_segment): Allow for renaming of external SRAM region to
+	xram.
+
+2011-12-12  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Set PLLQ.
+
+2011-12-08  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3220g_eval.cdl:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_jtag.h:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_jtag.ldi:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_ram.h:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_ram.ldi:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_rom.h:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_romint.h:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_romint.ldi:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_sram.h:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_sram.ldi:
+	* misc/redboot_JTAG.ecm:
+	* misc/redboot_ROM.ecm:
+	* src/stm3220g_eval_flash.c:
+	* src/stm3220g_eval_misc.c:
+	New package -- ST STM3220G EVAL board HAL. Derived from STM3210E HAL.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/cdl/hal_cortexm_stm32_stm32x0g_eval.cdl b/packages/hal/cortexm/stm32/stm32x0g_eval/current/cdl/hal_cortexm_stm32_stm32x0g_eval.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/cdl/hal_cortexm_stm32_stm32x0g_eval.cdl
@@ -0,0 +1,473 @@
+##==========================================================================
+##
+##      hal_cortexm_stm32_stm32x0g_eval.cdl
+##
+##      Cortex-M STM32X0G EVAL platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2012 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    jlarmour
+## Based on:     stm3210e CDL by nickg
+## Date:         2011-11-10
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL {
+    display       "ST STM32x0G-EVAL (STM32 20-21-45-46 G-EVAL) Development Board HAL"
+    parent        CYGPKG_HAL_CORTEXM_STM32
+    requires      { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4"))  }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") ? (CYGHWR_HAL_CORTEXM_STM32_F2 == "F207IG") : (CYGHWR_HAL_CORTEXM_STM32_F4 == "F407IG") }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM == "M3") }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM == "M4") }
+    # 25MHz crystal feeds HSE
+    # From STM32F4xx Rev A System Clock Configuration v1.0.1
+    #   SYSCLK          120MHz    168MHz
+    #   ------          ------    ------
+    #   HSE             25MHz     25MHz		fixed input crystal on board : CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK
+    #   PLL_M           25        25		(6bits) main divisor
+    #   PLL_N           240       336		(9bits) main multiplier
+    #   PLL_P           2         2		(2bits) derived from PLL_N : used for SYSCLK (must not exceed F2:120 or F4:168)
+    #   PLL_Q           5         7		(4bits) derived from PLL_N : used for USB OTG FS, SDIO and RNG (must be >= 2)
+    #   AHB Prescaler   1         1
+    #   SYSCLK		120MHz	  168MHz	(((HSE / PLL_M) * PLL_N) / PLL_P)
+    #   HCLK            120MHz    168MHz	(SYSCLK / AHB Prescaler)
+    #   APB1 Prescaler  4         4
+    #   PCLK1		30MHz	  42MHz		(HCLK / APB1 Prescaler)
+    #   APB2 Prescaler  2         2
+    #	PCLK2		60MHz	  84MHz		(HCLK / APB2 Prescaler)
+    #
+    # Must use HSE for the PLL settings below
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE == "HSE" }
+    # F2:
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 15) }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL == 288) }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV == 4) }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV == 10) }
+    # F4:
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 25) }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL == 336) }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV == 2) }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV == 7) }
+    # Common:
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 1 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 4 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 2 }
+
+#    define_header hal_cortexm_stm32_stm32x0g_eval.h
+    include_dir   cyg/hal
+    hardware
+    description   "
+        The STM32x0G EVAL HAL package provides the support needed to run
+        eCos on the ST STM32 20-21-45-46 G-EVAL board."
+
+    compile       stm32x0g_eval_misc.c
+
+    cdl_option CYGPKG_HAL_CORTEXM_STM32_STM3220G_EVAL {
+        display "Platform definitions for STM3220G-EVAL (F2) board."
+	active_if { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2" }
+        no_define
+	calculated 1
+        define_proc {
+            puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+            puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_stm32.h>"
+            puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>"
+            puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M3\""
+            puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"ST STM3220G-EVAL\""
+            puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+        }
+    }
+
+    cdl_option CYGPKG_HAL_CORTEXM_STM32_STM3240G_EVAL {
+        display "Platform definitions for STM3240G-EVAL (F4) board."
+	active_if { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4" }
+        no_define
+	calculated 1
+        define_proc {
+            puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+            puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_stm32.h>"
+            puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>"
+            puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+            puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"ST STM3240G-EVAL\""
+            puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+        }
+        implements    CYGINT_HAL_FPV4_SP_D16
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value {"RAM"}
+        legal_values  {"RAM" "SRAM" "ROM" "ROMINT" "JTAG"}
+        no_define
+        define -file system.h CYG_HAL_STARTUP
+        description   "
+            When targetting the ST STM32X0G EVAL board it is possible to
+            build the system for either RAM bootstrap or ROM bootstrap.
+            Select 'RAM' when building programs to load into RAM using onboard
+            debug software such as RedBoot or eCos GDB stubs.  Select 'ROM'
+            when building a stand-alone application which will be put
+            into ROM. The 'JTAG' type allows programs to be downloaded using a
+            JTAG debugger such as a BDI3000 or PEEDI. The 'SRAM' type allows
+            programs to be downloaded via a JTAG debugger into on-chip SRAM.
+            The 'ROMINT' type supports applications with code in on-chip flash
+            and data/bss in on-chip SRAM, ignoring the external SRAM."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated    { (CYG_HAL_STARTUP == "RAM"    ) ? "cortexm_stm32x0g_eval_ram"      :
+                        (CYG_HAL_STARTUP == "SRAM"   ) ? "cortexm_stm32x0g_eval_sram"     :
+                        (CYG_HAL_STARTUP == "ROM"    ) ? "cortexm_stm32x0g_eval_rom"      :
+                        (CYG_HAL_STARTUP == "ROMINT" ) ? "cortexm_stm32x0g_eval_romint"   :
+                        (CYG_HAL_STARTUP == "JTAG"   ) ? "cortexm_stm32x0g_eval_jtag"     :
+                                                         "undefined" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+                display "Memory layout linker script fragment"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+                display "Memory layout header file"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_H
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+
+    }
+
+    cdl_option CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK {
+        display         "Input Clock frequency"
+        flavor          data
+        default_value   25000000
+        legal_values    0 to 1000000000
+        description     "Main clock input."
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES {
+        display         "Flash read wait states"
+        flavor          data
+        default_value   { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") ? 3 : 5 }
+        legal_values    0 to 7
+        description     "
+            This option gives the number of wait states to use for accessing
+            the flash for reads. The correct setting for this value depends
+            on both the CPU clock (HCLK) frequency and the voltage. Consult
+            the STM32 Flash programming manual (PM0059) for appropriate
+            values for different clock speeds or voltages. The default of
+            3 reflects a supply voltage of 3.3V and HCLK of 120MHz."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH {
+        display         "Flash driver support"
+        parent          CYGPKG_IO_FLASH
+        active_if       CYGPKG_IO_FLASH
+        compile         -library=libextras.a stm32x0g_eval_flash.c
+        default_value   1
+        description     "Control flash device support for STM32X0G-EVAL board."
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_ETH0 {
+        display       "STM32 Ethernet support"
+        description   "
+            Hardware specifics for the ethernet interface provided on the
+            STM32X0G-EVAL board."
+        parent        CYGPKG_IO_ETH_DRIVERS
+        active_if     CYGPKG_IO_ETH_DRIVERS
+        default_value 1
+        requires      CYGPKG_DEVS_ETH_CORTEXM_STM32
+        requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
+                         (1 == CYGHWR_DEVS_ETH_PHY_DP8384X) }
+        requires      { is_active(CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO) implies \
+                            (CYGHWR_DEVS_ETH_CORTEXM_STM32_PHY_CLK_MCO == CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO) }
+        requires      { "MII" == CYGSEM_DEVS_ETH_CORTEXM_STM32_INTF }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO {
+            display         "Use MCO as PHY clock"
+            default_value   1
+            description     "
+                The STM32X0G can use the MCO clock signals as the 25MHz clock for
+                the PHY, or it can use the onboard 25MHz crystal at X1, depending
+                on the setting of jumper J5. This option should be set to reflect
+                the J5 setting."
+        }
+    }
+
+    implements CYGINT_HAL_VIRTUAL_VECTOR_VPRINTF
+
+    # The 9-pin D connector is connected to PC10 and PC11, which are connected to
+    # USART3 or UART4 depending on pin config. The main difference between these
+    # ports is that UART4 doesn't support hardware flow control. This board doesn't
+    # have the flow control lines hooked up anyway, so to save having to fiddle
+    # with ignoring the flow control lines on USART3, we choose to use UART4.
+    # Note that this is UART4 in STM32 speak (counting from 1), but the STM32 port
+    # uses the name UART3 for it (counting from 0). Hrm.
+    implements CYGINT_HAL_STM32_UART3
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        calculated       0
+        description      "
+            The ST STM32X0G EVAL board has one serial port. This option
+            informs the rest of the system which port will be used to connect
+            to a host running GDB."
+     }
+
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Diagnostic serial port"
+         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         calculated       0
+         description      "
+            The ST STM32X0G EVAL has one serial port. This option
+            informs the rest of the system which port will be used for
+            diagnostic output."
+     }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 115200
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            RedBoot usess polling to transfer data over this port and
+            might not be able to keep up with baud rates above the
+            default, particularly when doing XYZmodem downloads. The
+            interrupt-driven device driver is able to handle these
+            baud rates, so any high speed application transfers should
+            use that instead.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 115200
+        # Only one channel on this board so:
+        requires      { CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD == CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            RedBoot usess polling to transfer data over this port and
+            might not be able to keep up with baud rates above the
+            default, particularly when doing XYZmodem downloads. The
+            interrupt-driven device driver is able to handle these
+            baud rates, so any high speed application transfers should
+            use that instead.
+            Note: this should match the value chosen for the console port if the
+            console and GDB port are the same."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+            Global build options including control over
+            compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_OPTIONS {
+        display "STM32X0G HAL build options"
+                flavor  none
+                description   "
+                        Package specific build options including control over
+                        compiler flags used only in building this HAL."
+
+                cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_CFLAGS_ADD {
+                        display "Additional compiler flags"
+                        flavor  data
+                        no_define
+                        default_value { "-Werror" }
+                        description   "
+                                This option modifies the set of compiler flags
+                                for building this HAL. These flags are used
+                                in addition to the set of global flags."
+                        }
+                cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_CFLAGS_REMOVE {
+                        display "Suppressed compiler flags"
+                        flavor  data
+                        no_define
+                        default_value { "" }
+                        description   "
+                                This option modifies the set of compiler flags
+                                for building this HAL. These flags are
+                                removed from the set of global flags if
+                                present."
+                }
+        }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMINT" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" "GDB_stubs" }
+         default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+         parent        CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM monitor.
+             This support changes various eCos semantics such as the encoding
+             of diagnostic output, or the overriding of hardware interrupt
+             vectors.
+             Firstly there is \"Generic\" support which prevents the HAL
+             from overriding the hardware vectors that it does not use, to
+             instead allow an installed ROM monitor to handle them. This is
+             the most basic support which is likely to be common to most
+             implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included in
+             the ROM monitor or boot ROM."
+     }
+
+    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+        display       "Redboot HAL options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+        description   "
+            This option lists the target's requirements for a valid Redboot
+            configuration."
+
+        requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGBLD_REDBOOT_MAX_MEM_SEGMENTS == 2) }
+        requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGBLD_REDBOOT_MAX_MEM_SEGMENTS == 3) }
+
+        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+            display       "Build Redboot ROM binary images"
+            active_if     CYGBLD_BUILD_REDBOOT
+            default_value 1
+            no_define
+            description "This option enables the conversion of the Redboot ELF
+                         image to binary image formats suitable for ROM programming."
+
+            make -priority 325 {
+                <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+                $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+                $(OBJCOPY) -O binary $< $@
+            }
+        }
+    }
+
+    cdl_component CYGBLD_HAL_CORTEXM_STM32X0G_EVAL_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMINT" }
+
+        make -priority 325 {
+                <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+                <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) -O binary $< $@
+        }
+
+        description "This component causes the ELF image generated by the
+                     build process to be converted to S-Record and binary
+                     files."
+    }
+}
+
+# EOF hal_cortexm_stm32_stm32x0g_eval.cdl
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.h b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.h
@@ -0,0 +1,26 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ram (0x64000000)
+#define CYGMEM_REGION_ram_SIZE (0x00200000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi
@@ -0,0 +1,50 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    ram   : ORIGIN = 0x64000000, LENGTH = 0x00200000
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+}
+
+hal_vsr_table = 0x20000000;
+// 97 or 98 entries in this VSR table depending on the processor family
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+hal_virtual_vector_table = hal_vsr_table + 97*4;
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#endif
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// SRAM is 128k.
+hal_startup_stack = 0x20000000 + 1024*128;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_sram (sram, hal_virtual_vector_table_end, LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, 0x64000000, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.h b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.h
@@ -0,0 +1,28 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00020000)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ram (0x64000000)
+#define CYGMEM_REGION_ram_SIZE (0x00200000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi
@@ -0,0 +1,50 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00020000
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    ram   : ORIGIN = 0x64000000, LENGTH = 0x00200000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+}
+
+hal_vsr_table = 0x20000000;
+// 97 or 98 entries in this VSR table depending on the processor family
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+hal_virtual_vector_table = hal_vsr_table + 97*4;
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#endif
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// External SRAM is 2MB
+hal_startup_stack = 0x64200000;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_sram (sram, hal_virtual_vector_table_end, LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, 0x64008000, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.h b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.h
@@ -0,0 +1,26 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ram (0x64000000)
+#define CYGMEM_REGION_ram_SIZE (0x00200000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi
@@ -0,0 +1,51 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    ram   : ORIGIN = 0x64000000, LENGTH = 0x00200000
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+}
+
+
+hal_vsr_table = 0x20000000;
+// 97 or 98 entries in this VSR table depending on the processor family
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+hal_virtual_vector_table = hal_vsr_table + 97*4;
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#endif
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// SRAM is 128k.
+hal_startup_stack = 0x20000000 + 1024*128;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA)
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, hal_virtual_vector_table_end, FOLLOWING (.got))
+    SECTION_data (ram, 0x64000000, FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.h b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.h
@@ -0,0 +1,26 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x20000000)
+#define CYGMEM_REGION_ram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_xram (0x64000000)
+#define CYGMEM_REGION_xram_SIZE (0x00200000)
+#define CYGMEM_REGION_xram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi
@@ -0,0 +1,50 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram   : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    xram  : ORIGIN = 0x64000000, LENGTH = 0x00200000
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+}
+
+hal_vsr_table = 0x20000000;
+// 97 or 98 entries in this VSR table depending on the processor family
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+hal_virtual_vector_table = hal_vsr_table + 97*4;
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#endif
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// SRAM is 128k.
+hal_startup_stack = 0x20000000 + 1024*128;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA)
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (ram, hal_virtual_vector_table_end, FOLLOWING (.got))
+    SECTION_data (ram, ALIGN( 0x8), FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.h b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.h
@@ -0,0 +1,28 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ram (0x64000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi
@@ -0,0 +1,51 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    ram   : ORIGIN = 0x64000000, LENGTH = 0x00200000
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+}
+
+
+hal_vsr_table = 0x20000000;
+// 97 or 98 entries in this VSR table depending on the processor family
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+hal_virtual_vector_table = hal_vsr_table + 97*4;
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#endif
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// SRAM is 128k.
+hal_startup_stack = 0x20000000 + 1024*128;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (sram, hal_virtual_vector_table_end, LMA_EQ_VMA)
+    SECTION_RELOCS (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (sram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_arch.h b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_arch.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_arch.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2008-07-30
+// Purpose:     STM32X0G EVAL platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_intr.h b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_intr.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2008-07-30
+// Purpose:     STM32X0G EVAL platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_io.h b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_io.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_io.h
@@ -0,0 +1,171 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2008-07-30
+// Purpose:     STM32X0G EVAL platform specific registers
+// Description: 
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+// Board LEDs
+
+#define CYGHWR_HAL_STM32X0G_LED1   CYGHWR_HAL_STM32_PIN_OUT( G, 6, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32X0G_LED2   CYGHWR_HAL_STM32_PIN_OUT( G, 8, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32X0G_LED3   CYGHWR_HAL_STM32_PIN_OUT( I, 9, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32X0G_LED4   CYGHWR_HAL_STM32_PIN_OUT( C, 7, PUSHPULL, NONE, LOW )
+
+// A convenience function to set LEDs. Lowest 4 bits of 'c' correspond to the 4 LEDs.
+__externC void hal_stm32x0_led(char c);
+
+//=============================================================================
+// Custom Ethernet pin mappings
+
+#define CYGHWR_HAL_STM32_ETH_MII_TX_CRS         CYGHWR_HAL_STM32_PIN_ALTFN_IN(  H,  2, 11, OPENDRAIN, NONE )
+#define CYGHWR_HAL_STM32_ETH_MII_COL            CYGHWR_HAL_STM32_PIN_ALTFN_IN(  H,  3, 11, OPENDRAIN, NONE )
+#define CYGHWR_HAL_STM32_ETH_MII_RXD2           CYGHWR_HAL_STM32_PIN_ALTFN_IN(  H,  6, 11, OPENDRAIN, NONE )
+#define CYGHWR_HAL_STM32_ETH_MII_RXD3           CYGHWR_HAL_STM32_PIN_ALTFN_IN(  H,  7, 11, OPENDRAIN, NONE )
+#define CYGHWR_HAL_STM32_ETH_MII_TXD3           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  8, 11, PUSHPULL,  NONE, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_RX_ER          CYGHWR_HAL_STM32_PIN_ALTFN_IN(  I, 10, 11, OPENDRAIN, NONE )
+#define CYGHWR_HAL_STM32_ETH_MII_TX_EN          CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G, 11, 11, PUSHPULL,  NONE, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_TXD0           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G, 13, 11, PUSHPULL,  NONE, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_TXD1           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G, 14, 11, PUSHPULL,  NONE, AT_LEAST(50) )
+// NOTE: CYGHWR_HAL_STM32_ETH_MII_PPS_OUT not defined
+
+#define CYGHWR_HAL_STM32_ETH_CONFIGURE_MCO()                            \
+  CYG_MACRO_START                                                       \
+  cyg_uint32 cfgr;                                                      \
+  HAL_READ_UINT32( CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_CFGR, cfgr ); \
+  cfgr &= ~CYGHWR_HAL_STM32_RCC_CFGR_MCO1_MASK;                          \
+  cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSE;                           \
+  cfgr &= ~CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_MASK;                       \
+  cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_1;                          \
+  HAL_WRITE_UINT32( CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_CFGR, cfgr ); \
+  CYG_MACRO_END
+  
+//=============================================================================
+// GPIO pin and DMA definitions for each SPI bus
+
+// NOTE: The SPEED_SPI manifest is declared by the device driver
+// (e.g. "devs/spi/cortexm/stm32/<vsn>/src/spi_stm32.c") and is not
+// currently defined in a header.
+
+#ifndef CYGHWR_HAL_STM32_SPI1_REMAP
+#define CYGHWR_HAL_STM32_SPI1_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  5, 5, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI1_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A,  6, 5, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI1_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  7, 5, PUSHPULL, NONE, SPEED_SPI )
+#else
+#define CYGHWR_HAL_STM32_SPI1_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  3, 5, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI1_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B,  4, 5, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI1_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  5, 5, PUSHPULL, NONE, SPEED_SPI )
+#endif
+#define CYGHWR_HAL_STM32_SPI1_REMAP_CONFIG      0
+
+#define CYGHWR_HAL_STM32_SPI1_DMA_TX            CYGHWR_HAL_STM32_DMA( 2, 3, 3, M2P )
+#define CYGHWR_HAL_STM32_SPI1_DMA_RX            CYGHWR_HAL_STM32_DMA( 2, 0, 3, P2M )
+
+
+
+#define CYGHWR_HAL_STM32_SPI2_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( I, 1, 5, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI2_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  I, 2, 5, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI2_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( I, 3, 5, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI2_REMAP_CONFIG      0
+
+#define CYGHWR_HAL_STM32_SPI2_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 4, 0, M2P )
+#define CYGHWR_HAL_STM32_SPI2_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 3, 0, P2M )
+
+
+    
+#ifndef CYGHWR_HAL_STM32_SPI3_REMAP
+#define CYGHWR_HAL_STM32_SPI3_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  3, 6, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI3_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B,  4, 6, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI3_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  5, 6, PUSHPULL, NONE, SPEED_SPI )
+#else
+#define CYGHWR_HAL_STM32_SPI3_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, 6, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI3_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C, 11, 6, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI3_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 12, 6, PUSHPULL, NONE, SPEED_SPI )
+#endif
+#define CYGHWR_HAL_STM32_SPI3_REMAP_CONFIG      0
+
+#define CYGHWR_HAL_STM32_SPI3_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 2, 0, M2P )
+#define CYGHWR_HAL_STM32_SPI3_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 0, 0, P2M )
+
+
+//=============================================================================
+// GPIO pin and DMA definitions for each I2C bus
+
+#define CYGHWR_HAL_STM32_I2C1_SCL               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  6, 4, OPENDRAIN, PULLUP, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_I2C1_SDA               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  9, 4, OPENDRAIN, PULLUP, AT_LEAST(50) )
+
+#define CYGHWR_HAL_STM32_I2C1_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 7, 1, M2P )
+#define CYGHWR_HAL_STM32_I2C1_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 5, 1, P2M )
+
+#define CYGHWR_HAL_STM32_I2C2_SCL               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 10, 4, OPENDRAIN, PULLUP, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_I2C2_SDA               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 11, 4, OPENDRAIN, PULLUP, AT_LEAST(50) )
+
+#define CYGHWR_HAL_STM32_I2C2_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 7, 7, M2P )
+#define CYGHWR_HAL_STM32_I2C2_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 3, 7, P2M )
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_JTAG.ecm b/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_JTAG.ecm
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_JTAG.ecm
@@ -0,0 +1,87 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    template    redboot ;
+
+    package CYGPKG_IO_FLASH current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+    inferred_value 0 0
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value JTAG
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES {
+    user_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+     user_value 0
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+    inferred_value ROM
+};
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_RAM.ecm b/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_RAM.ecm
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_RAM.ecm
@@ -0,0 +1,83 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    template    redboot ;
+
+    package CYGPKG_IO_FLASH current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 0
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+    inferred_value 0 0
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value RAM
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES {
+    user_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+     user_value 0
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM.ecm b/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM.ecm
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM.ecm
@@ -0,0 +1,87 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    template    redboot ;
+
+    package CYGPKG_IO_FLASH current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+    inferred_value 0 0
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value ROM
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES {
+    user_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+     user_value 0
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+    inferred_value ROM
+};
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM_FPU.ecm b/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM_FPU.ecm
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM_FPU.ecm
@@ -0,0 +1,95 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    template    redboot ;
+
+    package CYGPKG_IO_FLASH current ;
+};
+
+cdl_component CYGHWR_HAL_CORTEXM_FPU {
+    user_value 1
+};
+
+cdl_option CYGHWR_HAL_CORTEXM_FPU_SWITCH {
+    user_value ALL
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+    inferred_value 0 0
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value ROM
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES {
+    user_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+     user_value 0
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+    inferred_value ROM
+};
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_flash.c b/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_flash.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_flash.c
@@ -0,0 +1,68 @@
+/*==========================================================================
+//
+//      stm32x0g_eval_flash.c
+//
+//      Cortex-M3 STM32X0G EVAL Flash setup
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour
+// Date:         2011-12-12
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <cyg/io/flash_dev.h>
+
+//--------------------------------------------------------------------------
+// Internal flash
+
+#include <cyg/io/stm32_flash.h>
+
+CYG_FLASH_DRIVER(hal_stm32_flash,
+                 &cyg_stm32_flash_funs,
+                 0,
+                 0x08000000,
+                 0,
+                 0,
+                 0,
+                 &hal_stm32_flash_priv
+);
+
+//--------------------------------------------------------------------------
+// EOF stm32x0g_eval_flash.c
diff --git a/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_misc.c b/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_misc.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_misc.c
@@ -0,0 +1,404 @@
+/*==========================================================================
+//
+//      stm32x0g_eval_misc.c
+//
+//      Cortex-M3/-M4 STM32X0G EVAL HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011, 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour based on stm3210e by nickg
+// Date:         2008-07-30
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_stm32.h>
+#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include CYGHWR_MEMORY_LAYOUT_H         // Memory regions
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+
+//==========================================================================
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+#if (CYGNUM_CALL_IF_TABLE_SIZE > 64)
+// We force a compilation error for this fatal condition since run-time asserts
+// may not be enabled for the build.
+#error "The CALL_IF_TABLE_SIZE pre-allocation in the linker scripts for this platform need to be updated"
+#endif
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void hal_system_init( void )
+{
+    CYG_ADDRESS base;
+
+    // Enable peripheral clocks in RCC
+
+    base = CYGHWR_HAL_STM32_RCC;
+
+    // All GPIO ports
+    // FIXME: this should be done in variant HAL at point of gpio_set
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB1ENR,
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) // enable CCM clock
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_CCMDATARAMEN) |
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOA) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOB) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOC) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOD) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOE) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOF) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOG) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOH) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOI) );
+
+    // Enable FSMC
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB3ENR,
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB3ENR_FSMC) );
+
+#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_ROMINT) | defined(CYG_HAL_STARTUP_SRAM)
+
+    // Reset FSMC in case it was already enabled. This should set
+    // all regs back to default documented values, so we don't need
+    // to do any precautionary resets.
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB3RSTR,
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB3ENR_FSMC) );
+    // Bring out of reset:
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB3RSTR, 0 );
+#endif
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO)
+    // Use HSE clock as the MCO1 clock signals for PHY
+    {
+        cyg_uint32 acr;
+
+        HAL_READ_UINT32(base + CYGHWR_HAL_STM32_RCC_CFGR, acr);
+        acr |= CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSE |
+            CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_1;
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_STM32_RCC_CFGR, acr);
+    }
+#endif
+
+    // Set all unused GPIO lines to input with pull down to prevent
+    // them floating and annoying any external hardware.
+
+    // GPIO Ports C..I reset GPIOx_MODER to 0x00000000
+    // GPIO Ports A..I reset GPIOx_OTYPER to 0x00000000
+    // CPIO Ports A,C..I reset GPIOx_OSPEEDR to 0x00000000
+    // GPIO Ports C..I reset GPIOx_PUPDR to 0x00000000
+
+    // GPIO Port A resets GPIOA_MODER to 0xA8000000
+    // GPIO Port A resets GPIOA_PUPDR to 0x64000000
+    // GPIO Port A keeps the default JTAG pins on PA13,14,15
+    base = CYGHWR_HAL_STM32_GPIOA;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x02AAAAAA );
+
+    // GPIO Port B resets GPIOB_MODER to 0x00000280
+    // GPIO Port B resets GPIOB_OSPEEDR to 0x000000C0
+    // GPIO Port B resets GPIOB_PUPDR to 0x00000100
+    // GPIO Port B keeps the default JTAG pins on PB3,4
+    base = CYGHWR_HAL_STM32_GPIOB;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAAAAA82A );
+
+    // GPIO Port C - setup PC7 for LED4 as GPIO out, RS232 (USART4) on PC10,11.
+    // Rest stay default, with pulldowns on all except PC14,15 (OSC32)
+    // just in case that is important.
+
+    base = CYGHWR_HAL_STM32_GPIOC;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0x00008800 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x0A0A2AAA );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00A04000 );
+
+    // GPIO Port D - setup FSMC for SRAM (PD0-1,3-15) and MicroSDcard (PD2) alternate functions
+    base = CYGHWR_HAL_STM32_GPIOD;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0xCCCCCCCC );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0xCCCCCCCC );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0xAAAAAAAA );
+    // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz
+
+    // GPIO Port E - setup FSMC alternate function. PE0-1,3-4,7-15.
+    // But not PE5 (A21), PE6(A22), PE2(A23) which are not connected to SRAM.
+    base = CYGHWR_HAL_STM32_GPIOE;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0xC00CC0CC );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0xCCCCCCCC );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x00002820 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0xAAAA828A );
+    // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz
+
+    // GPIO Port F - setup FSMC alternate function. PF0-5,12-15.
+    // But not PF6-11 which aren't connected to SRAM.
+    base = CYGHWR_HAL_STM32_GPIOF;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0x00CCCCCC );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0xCCCC0000 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x00AAA000 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0xAA000AAA );
+    // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz
+
+    // GPIO Port G - setup FSMC alternate function. PG0-5,9,10.
+    // Other FSMC pins not connected to SRAM.
+    // LED1 is PG6, LED2 is PG8, so set as GPIO out.
+    base = CYGHWR_HAL_STM32_GPIOG;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0x00CCCCCC );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0x00000CC0 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAA808000 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00291AAA );
+    // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz
+
+    // GPIO Port H stays default, with pulldowns on all except PH0,1 (OSC) just in case that is important.
+    base = CYGHWR_HAL_STM32_GPIOH;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAAAAAAA0 );
+
+    // GPIO Port I - setup PI9 for LED3 as GPIO out, rest stay default, with pulldowns
+    base = CYGHWR_HAL_STM32_GPIOI;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAAA2AAAA );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00040000 );
+
+
+    // Set up FSMC NOR/SRAM bank 2 for SRAM
+
+    base = CYGHWR_HAL_STM32_FSMC;
+
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+    // NOTEs:
+    // - The "STM32 20-21-45-46 G-EVAL" boards we have are populated with the
+    //   IS61WV102416BLL-10MLI part and not the Cypress CY7C1071DV33 part.
+    // - The F4[01][57]xx devices can operate upto 168MHz (or 144MHz) so maximum HCLK
+    //   timing of 6ns (or 6.94444ns).
+    //
+    // NOTE: The code does NOT set BWTR2 for SRAM write-cycle timing (so will be
+    // the default reset value of 0x0FFFFFFF) since BCRx:EXTMOD bit is NOT set.
+
+    // TODO:IMPROVE: Derive values based on CLK settings. The following "fixed"
+    // values are based on a 168MHz SYSCLK:
+
+    // BCR2 = MBKEN | MWID=0b01 (16bits) | WREN
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR2, 0x00001015 );
+
+    // BTR2:
+    //   ADDSET=3 (3 HCLK cycles)
+    //   ADDHLD=0 (SRAM:do not care)
+    //   DATAST=6 (6 HCLK cycles)
+    //   BUSTURN=1 (1 HCLK cycle)
+    //   CLKDIV=0 (SRAM:do not care)
+    //   DATLAT=0 (SRAM:do not care)
+    //   ACCMOD=0 (access mode A)
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR2, 0x00010603 );
+#else // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR2, 0x00001011 );
+    // SRAM timings for the fitted CY7C1071DV33-12BAXI async SRAM
+    // We could try and make this depend on hclk as it should, but that's
+    // probably overkill for now. With an hclk of 120MHz, each hclk period
+    // is 8.33ns, so we just use that. This might mean being slightly
+    // suboptimal at lower configured hclk speeds.
+    // It's tricky to get the waveforms in the STM32 FSMC docs and the SRAM
+    // datasheet, to match up, so there's a small amount of guess work involved
+    // here. From the SRAM datasheet, ADDSET should be at least 7ns (tHZWE), and
+    // DATAST should be at least 9ns (tPWE) plus one HCLK (from Fig 397 in FSMC
+    // docs showing Mode 1 write accesses). This gives ADDSET=1 and
+    // DATAST=3.
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR2, 0x00000301 );
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2
+
+    // Enable flash prefetch buffer, cacheability and set latency to 2 wait states.
+    // Latency has to be set before clock is switched to a higher speed.
+    {
+        cyg_uint32 acr;
+
+        base = CYGHWR_HAL_STM32_FLASH;
+
+        HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_PRFTEN;
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_DCEN|CYGHWR_HAL_STM32_FLASH_ACR_ICEN;
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES);
+        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+    }
+}
+
+//==========================================================================
+
+// Set LEDs 1-4 to lowest 4 bits of supplied char.
+__externC void hal_stm32x0_led(char c)
+{
+    CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED1, 0 != (c&1) );
+    CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED2, 0 != (c&2) );
+    CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED3, 0 != (c&4) );
+    CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED4, 0 != (c&8) );
+}
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+#ifdef CYGDBG_USE_ASSERTS
+    __externC char __sram_data_start[];
+#endif
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    // Check the number of VSRs matches the linker script. We can do this
+    // because we intend the VV table to follow the VSR table with no gaps.
+    CYG_ASSERT( (char*)&hal_virtual_vector_table[0] - (char*)&hal_vsr_table >= CYGNUM_HAL_VSR_COUNT*4,
+                "VSR table size does not match" );
+    // Now check the declared start of SRAM data follows the VV table end
+    CYG_ASSERT( (__sram_data_start - (char*)&hal_virtual_vector_table[0]) >= CYGNUM_CALL_IF_TABLE_SIZE*4,
+                "VV table size does not match sram space" );
+#else
+    // Check the VSR table fits below declared start of SRAM data
+    CYG_ASSERT( (__sram_data_start - (char*)&hal_vsr_table[0]) >= CYGNUM_HAL_VSR_COUNT*4,
+                "VSR table size does not match" );
+#endif
+    hal_stm32x0_led(1);
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct
+{
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+    { CYGMEM_REGION_ram,        CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1      },      // External SRAM
+#ifdef CYGMEM_REGION_sram
+    { CYGMEM_REGION_sram,       CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1    },      // On-chip SRAM
+#endif
+#ifdef CYGMEM_REGION_flash
+    { CYGMEM_REGION_flash,      CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1  },      // On-chip flash
+#endif
+    { 0xE0000000,               0x00000000-1                                    },      // Cortex-M peripherals
+    { 0x40000000,               0x60000000-1                                    },      // STM32 peripherals
+    { 0xA0000000,               0xA0001000-1                                    },      // FSMC control
+#ifdef CYGMEM_REGION_ccm
+    { CYGMEM_REGION_ccm,        CYGMEM_REGION_ccm+CYGMEM_REGION_ccm_SIZE-1      },      // On-chip (close-coupled) SRAM
+#endif
+};
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ )
+    {
+        if( (addr >= hal_data_access[i].start) &&
+            (addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the on-chip SRAM and external SRAM.
+
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_sram
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_sram;
+        *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
+        break;
+#elif defined(CYGMEM_REGION_xram)
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_xram;
+        *end = (unsigned char *)(CYGMEM_REGION_xram + CYGMEM_REGION_xram_SIZE);
+        break;
+#endif
+#ifdef CYGMEM_REGION_ccm
+    case 2:
+        *start = (unsigned char *)CYGMEM_REGION_ccm;
+        *end = (unsigned char *)(CYGMEM_REGION_ccm + CYGMEM_REGION_ccm_SIZE);
+        break;
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+} // cyg_plf_memory_segment()
+
+#endif // CYGPKG_REDBOOT
+
+
+//==========================================================================
+// EOF stm32x0g_eval_misc.c
diff --git a/packages/hal/cortexm/stm32/var/current/ChangeLog b/packages/hal/cortexm/stm32/var/current/ChangeLog
--- a/packages/hal/cortexm/stm32/var/current/ChangeLog
+++ b/packages/hal/cortexm/stm32/var/current/ChangeLog
@@ -1,17 +1,299 @@
+2014-02-28  John Dallaway  <john@dallaway.org.uk>
+
+	* src/stm32_misc.c: Ensure TIM2 clock enabled when profiling.
+	[Bugzilla 1001953]
+
+2013-04-06  Jerzy Dyrda  <jerzdy@gmail.com>
+
+	* include/var_io_eth.h: 
+	* include/var_io.h: Update ETH macros for F4 device. [ Bugzilla 1001219 ]
+
+2013-01-19  John Dallaway  <john@dallaway.org.uk>
+
+	* include/var_io.h: Fix CYGHWR_HAL_STM32_UART6 definition.
+
+2012-04-23  James Smith  <jsmith@ecoscentric.com>
+
+	* include/var_io_pins.h (CYGHWR_HAL_STM32_PIN_IN): Removed
+	spurious parameter since the API for this macro should match the
+	F2/F4 (HIPERFORMANCE) definition.
+
+	* include/var_io_eth.h: Update F1 ETH_MII
+	CYGHWR_HAL_STM32_PIN_IN() usage to reflect correct API.
+
+2012-04-13  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* include/var_io.h:
+	Added definitions, CYGHWR_HAL_STM32_USB_CLOCK, 
+	CYGHWR_HAL_STM32_CAN1_CLOCK and CYGHWR_HAL_STM32_CAN2_CLOCK 
+
+2012-03-27  James Smith  <jsmith@ecoscentric.com>
+
+	* tests/timers.c (TIMER_PRI): Add macro and manifests to allow
+	easy manipulation of the base and delta between the timer
+	priorities being tested.
+
+2012-03-23  James Smith  <jsmith@ecoscentric.com>
+
+	* include/var_io_usart.h: Provide common/shared UART pin
+	definitions for F1, F2 and F4 devices using the new PIN wrapper
+	macros. The RTS pin definitions for all STM32F families now use
+	GPIO output since the driver uses software controlled
+	RTS. Previously the F2/F4 defined the RTS pins as ALTFN.
+
+	* include/var_io.h: Provide common/shared ADC pin definitions for
+	F1, F2 and F4 devices using the new PIN_ANALOG() wrapper macro.
+
+	* include/var_io_eth.h: Provide common MII pin definitions using
+	the new PIN wrapper macros. Also remove MII_REMAP which was
+	incorrectly using the wrong manifests (STM3210C-EVAL networking
+	would not work) since decision taken that "plf_io.h" should
+	contain board specific I/O pin mapping.
+
+	* cdl/hal_cortexm_stm32.cdl: Remove CYGPKG_HAL_STM32_ETH and
+	sub-option CYGHWR_HAL_STM32_ETH_MII_REMAP since ethernet pin
+	mapping now present in platform specific "plf_io.h" header.
+
+2012-03-22  James Smith  <jsmith@ecoscentric.com>
+
+	* include/var_io_pins.h: Provide "common" wrapper macros
+	CYGHWR_HAL_STM32_PIN_OUT, CYGHWR_HAL_STM32_PIN_ALTFN_OUT,
+	CYGHWR_HAL_STM32_PIN_IN, CYGHWR_HAL_STM32_PIN_ALTFN_IN and
+	CYGHWR_HAL_STM32_PIN_ANALOG for defining I/O pins to allow the
+	same (where applicable) source calls to be used regardless of
+	whether the target is F1 or HIPERFORMANCE (F2/F4).
+
+	* cdl/hal_cortexm_stm32.cdl: Remove CYGPKG_HAL_STM32_ETH and
+	sub-option CYGHWR_HAL_STM32_ETH_MII_REMAP since ethernet pin
+	mapping now present in platform specific "plf_io.h" header.
+
+2012-03-21  James Smith  <jsmith@ecoscentric.com>
+
+	* include/var_io_pins.h: Provide similar support for F1 family
+	devices as available for F2/F4 family devices by adding AT_LEAST
+	and AT_MOST macros for specifying OUTPUT pin speed limits, and
+	providing generic LOW, MED and FAST manifests to hide the actual
+	device speed.
+
+	* src/stm32_misc.c (hal_stm32_gpio_set): Use
+	CYGHWR_HAL_STM32_GPIO_CNFMODE_SET macro instead of explicit
+	bitmask manipulation for seeting F1 CRL/CRH.
+
+2012-03-15  James Smith  <jsmith@ecoscentric.com>
+
+	* src/stm32_misc.c:
+	* src/stm32_dma.c:
+	* src/hal_diag.c:
+	* include/var_io_usart.h:
+	* include/var_io_pins.h:
+	* include/var_io_eth.h:
+	* include/var_io.h:
+	* include/var_intr.h:
+	* include/var_dma.h: Use HIPERFORMANCE manifest to add support for
+	F4 devices.
+
+	* cdl/hal_cortexm_stm32.cdl: Many minor changes to support
+	Cortex-M4 and STM32F4 devices.
+
+	* tests/timers.c (timers): Add TIM8_UP_TIM13 to the set of timers
+	tested for those platforms where it is defined.
+
+2012-03-13  James Smith  <jsmith@ecoscentric.com>
+
+	* include/var_io.h (HAL_AARDVARK_CHECK_I2C): Macro for specific
+	STM32 F1 devices that suffer from an I2C/FSMC errata to allow the
+	Aardvark test cases to operate. Added STM32F4 RTC manifests.
+
+2012-02-28  James Smith  <jsmith@ecoscentric.com>
+
+	* src/stm32_dma.c (hal_stm32_dma_disable): Add new function to
+	allow temporary disable of DMA stream for circular mode
+	configurations.
+
+	* include/var_dma.h: Added prototype for newly added
+	hal_stm32_dma_disable() function.
+
+2012-02-28  James Smith  <jsmith@ecoscentric.com>
+
+	* src/stm32_dma.c (hal_stm32_dma_isr): Do not disable the stream
+	when configured for circular mode.
+
+2012-02-24  James Smith  <jsmith@ecoscentric.com>
+
+	* include/var_io.h: Provide manifests covering STM32F2 ADC
+	support.
+
+	* include/var_intr.h: Provide explicit DMA2 CH4 and CH5 manifests
+	for non-connectivity devices (e.g. STM3210E-EVAL target).
+
+	* include/var_dma.h:
+	* src/stm32_dma.c (hal_stm32_dma_configure_circular): Provide
+	function to enable/disable DMA circular mode, and provide
+	prototype in header and documentation.
+
+2012-02-17  James Smith  <jsmith@ecoscentric.com>
+
+	* include/var_io_pins.h: Fix F2 MODE_SET and OSPEED_SET macros to
+	correctly mask register field bits.
+
+2012-01-20  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/var_intr.h (CYGNUM_HAL_VSR_MAX): Reverse an earlier
+	change to this value.
+
+2012-01-13  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/var_io.h: Add shifts for RTC TR and DR register fields.
+
+2012-01-12  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/var_intr.h: Reorganize vectors 43-49 so they are defined
+	correctly for F2 devices.
+
+	* include/var_io.h: Tidy up DMA defines. Move I2C and SPI pin and
+	DMA channel definitions out to platform HALs.
+
+	* include/var_io_pins.h (CYGHWR_HAL_STM32_GPIO_PUPD_SET): Fix
+	buglet in register clear code.
+
+	* cdl/hal_cortexm_stm32.cdl:
+	* include/var_dma.h:
+	* src/stm32_dma.c: Add DMA API.
+
+2011-12-15  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32.cdl (CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY):
+	Rather than list every F2 part, just say all F2 since we don't yet know
+	of F2 parts that don't have connectivity.
+	(CYGHWR_HAL_STM32_ETH_MII_REMAP): Allow pin remapping to be configurable
+	as a standard setting, alternate mapping, or provided by the platform.
+	* include/var_io.h: Add MCO1_MASK/MCO2_MASK and
+	MCO1PRE_MASK/MCO2PRE_MASK defns. Add CYGHWR_HAL_STM32_FLASH_CR_PSIZE()
+	to make flash parallelism easier to set.
+	* include/var_io_eth.h: Fix MACMIIAR_CR_MASK define.
+	Allow specification (and checking) of MACMIIAR_CR to set MDC clock
+	according to defined MHz ranges - this allows it to vary between
+	processors.
+	Support above CYGHWR_HAL_STM32_ETH_MII_REMAP changes.
+	Add alternate mappings for F2 eth pins (although it's a different
+	subset to F1.
+
+2011-12-12  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* src/stm32_misc.c (hal_start_clocks): Remove unnecessary fiddling
+	after RCC reset. Avoid overflow from PLL multiplier. Handle PLLQ
+	and RTCPRE on F2.
+
+	* include/var_io.h (CYGHWR_HAL_STM32_RCC_CFGR_RTCPRE): Add set macro
+	separate from mask.
+
+	* cdl/hal_cortexm_stm32.cdl: Improve clock option descriptions. Add
+	CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV.
+
+2011-12-08  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32.cdl: Add selections for processors in F2
+	family, and allow discrimination between those and F1.
+	* include/var_intr.h: Modify and add to interrupt list for F2.
+	(HAL_VAR_INTERRUPT_{MASK,UNMASK,ACKNOWLEDGE,CONFIGURE ): Update
+	EXTI interrupts that need special mapping for F2.
+	* include/var_io.h: Many additions and changes for F2. To avoid
+	an unmanageable size, split out GPIO/pin config, USART and ETH
+	peripheral definitions into new files.
+	* include/var_io_pins.h: New file for GPIO and pin configuration.
+	* include/var_io_usart.h: New file for USART definitions.
+	* include/var_io_eth.h: New file for Ethernet peripheral definitions.
+	* src/hal_diag.c: Allow for new style pin remapping used by F2
+	while still allowing F1 to work.
+	Support USART6 (which we call UART5).
+	(hal_stm32_serial_init_channel): Only use AFIO on F1.
+	* src/stm32_misc.c (hal_stm32_gpio_{set,out,in}): Support new GPIO
+	pin setting.
+	(hal_stm32_uart_setbaud): Support UART6 (called UART5 in CDL).
+	(hal_enable_profile_timer): Ensure timer peripheral (defaulting to TIM6)
+	has its clock enabled.
+
+2011-10-07  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/var_io.h: Separate FSMC and ETH register definitions,
+	which seem to have got a little mixed together at some point.
+
+2011-02-03  Alan Bowman  <alan.bowman@datong.co.uk>
+
+	* include/var_io.h: Fix CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_*
+	definitions. [ Bugzilla 1001137 ]
+
+2011-01-21  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/stm32_misc.c (hal_start_clocks): Added optional calculation of
+	hal_cortexm_systick_clock when 'internal' clock source is selected.
+
+2011-01-13  John Dallaway  <john@dallaway.org.uk>
+
+	* src/stm32_misc.c: Implement a profiling timer on TIM2.
+	* cdl/hal_cortexm_stm32.cdl: Add CDL option to enable the profiling
+	timer.
+
+2011-01-13  Nick Garnett  <nickg@ecoscentric.com>
+
+	* src/stm32_misc.c (hal_start_clocks): Correct bit clear operation
+	when disabling external clock.
+
 2009-10-26  Ross Younger  <wry@ecoscentric.com>
 
 	* include/var_io.h: Minor corrections to the FSMC register defs.
 
+2009-10-22  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/hal_cortexm_stm32.cdl:
+	* include/var_io.h: Add remap configuration for SPI busses.
+
 2009-08-10  Simon Kallweit  <simon.kallweit@intefo.ch>
 
 	* include/var_io.h: Added more register definitions for FSMC
 
+2009-07-02  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/hal_cortexm_stm32.cdl: Add remap configuration for UARTS.
+
+	* include/var_io.h (CYGHWR_HAL_STM32_AFIO_CLOCK): Add AFIO clock control.
+	(CYGHWR_HAL_STM32_UART*_REMAP_CONFIG): Add remap support for UARTS.
+
+	* src/hal_diag.c (channel_data_t, hal_stm32_serial_init_channel):
+	Add support for UART remapping.
+
+2009-06-29  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/var_io.h (CYGHWR_HAL_STM32_ETH): Add support for
+	ethernet device on connectivity line devices.
+	Add device clock control support.
+
+	* include/var_intr.h:
+	* cdl/hal_cortexm_stm32.cdl: Add support for connectivity line
+	devices.
+
+	* src/stm32_misc.c (hal_variant_init): Remove default enable of
+	all device clocks.
+	(hal_stm32_clock_enable, hal_stm32_clock_disable): Add routines to
+	enable individual device clocks.
+
+	* src/hal_diag.c (stm32_ser_channels)
+	(hal_stm32_serial_init_channel): Add clock enable support.
+
 2009-04-17  Simon Kallweit  <simon.kallweit@intefo.ch>
 
 	* src/hal_diag.c (hal_stm32_serial_getc_timeout): Fix for higher
 	baudrates. The original version lost bytes due to the long
 	timeout.
 
+2009-03-23  Nick Garnett  <nickg@ecoscentric.com>
+
+	* src/stm32_misc.c (hal_variant_init): Add write to AHBENR
+	register to enable all AHB based devices.
+
+	* include/var_io.h (CYGHWR_HAL_STM32_IWDG_*): Add defines for
+	independent watchdog.
+
 2009-02-27  Simon Kallweit  <simon.kallweit@intefo.ch>
 
 	* include/var_io.h:
@@ -103,7 +385,7 @@ 2008-10-06  Nick Garnett  <nickg@ecoscen
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008, 2009 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2009, 2011, 2013, 2014 Free Software Foundation, Inc.                        
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/hal/cortexm/stm32/var/current/cdl/hal_cortexm_stm32.cdl b/packages/hal/cortexm/stm32/var/current/cdl/hal_cortexm_stm32.cdl
--- a/packages/hal/cortexm/stm32/var/current/cdl/hal_cortexm_stm32.cdl
+++ b/packages/hal/cortexm/stm32/var/current/cdl/hal_cortexm_stm32.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 2008 Free Software Foundation, Inc.                        
+## Copyright (C) 2008, 2011 Free Software Foundation, Inc.                        
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -40,6 +40,7 @@
 #######DESCRIPTIONBEGIN####
 ##
 ## Author(s):    nickg
+## Contributors: jld
 ## Date:         2008-07-30
 ##
 ######DESCRIPTIONEND####
@@ -47,7 +48,7 @@
 ##==========================================================================
 
 cdl_package CYGPKG_HAL_CORTEXM_STM32 {
-    display       "Cortex-M3 STM32 Variant"
+    display       "Cortex-M3/-M4 STM32 Variant"
     parent        CYGPKG_HAL_CORTEXM
     hardware
     include_dir   cyg/hal
@@ -57,7 +58,7 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32 {
         microcontroller family.
         It is also necessary to select a variant and platform HAL package."
 
-    compile       hal_diag.c stm32_misc.c
+    compile       hal_diag.c stm32_misc.c stm32_dma.c
 
     implements    CYGINT_HAL_DEBUG_GDB_STUBS
     implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
@@ -65,15 +66,24 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32 {
     implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
     implements    CYGINT_PROFILE_HAL_TIMER
 
-    requires      { CYGHWR_HAL_CORTEXM == "M3" }
+    requires      { (CYGHWR_HAL_CORTEXM == "M3") || (CYGHWR_HAL_CORTEXM == "M4") }
+
+    cdl_component CYGHWR_HAL_CORTEXM_STM32_SELECTION {
+        display          "STM32 processor selection"
+        no_define
+        flavor           none
+        description      "
+            The options within this component allow you to select which STM32
+            processor is in use."
+
 
     cdl_option CYGHWR_HAL_CORTEXM_STM32 {
-        display          "STM32 variant in use"
+            display          "STM32 processor variant in use"
         flavor           data
-        default_value    {"F103ZE"}
-        legal_values     {"F103RC" "F103VC" "F103ZC"
-                          "F103RD" "F103VD" "F103ZD"
-                          "F103RE" "F103VE" "F103ZE" }
+            default_value    { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F1") ? CYGHWR_HAL_CORTEXM_STM32_F1 : \
+                               (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") ? CYGHWR_HAL_CORTEXM_STM32_F2 : \
+			       CYGHWR_HAL_CORTEXM_STM32_F4 }
+            # At some point we'll add the L1, etc. here.
         description      "The STM32 has several variants, the main differences
                           being in the size of on-chip FLASH and SRAM
                           and numbers of some peripherals. This option
@@ -81,6 +91,103 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32 {
                           microcontroller fitted."
     }
                           
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_FAMILY {
+            display          "Processor family in use"
+            flavor           data
+            default_value    { "F1" }
+            legal_values     { "F1" "F2" "F4" }
+	    # NOTE: F1/F2 imply CYGHWR_HAL_CORTEXM_M3 and F4 implies CYGHWR_HAL_CORTEXM_M4
+            description      "
+                Which family of STM32 processors is in use. This will
+                usually be the leading part of the processor model name."
+        }
+
+	# NOTE: This allows later L1 support to still select "FAMILY_HIPERFORMANCE" if the I/O is the same:
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE {
+            display     "Part belongs to ST Hi-Performance family"
+	    active_if   { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") }
+	    calculated  { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") }
+            description "
+	        Indicates that this part conforms to the I/O
+		definitions for the Hi-Performance family of
+		devices. Currently this includes the STM32 F2 and F4
+		devices."
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_F1 {
+            display          "F1 processor family selection"
+            flavor           data
+            active_if        { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F1" }
+            default_value    {"F103ZE"}
+            legal_values     {"F103RC" "F103VC" "F103ZC"
+                              "F103RD" "F103VD" "F103ZD"
+                              "F103RE" "F103VE" "F103ZE"
+                              "F105R8" "F105V8"
+                              "F105RB" "F105VB"
+                              "F105RC" "F105VC"
+                              "F107RB" "F107VB"
+                              "F107RC" "F107VC"
+                             }
+            requires         { CYGHWR_HAL_CORTEXM_STM32 == CYGHWR_HAL_CORTEXM_STM32_F1 }
+            description "
+                This option specifies which member of the STM32F1 family is
+                in use."
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_F2 {
+            display          "F2 processor family selection"
+            flavor           data
+            active_if        { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2" }
+            default_value    {"F207IG"}
+            legal_values     {"F205RB" "F205RC" "F205RE" "F205RF" "F205RG"
+                              "F205VB" "F205VC" "F205VE" "F205VF" "F205VG"
+                              "F205ZB" "F205ZC" "F205ZE" "F205ZF" "F205ZG"
+                              "F207VB" "F207VC" "F207VE" "F207VF" "F207VG"
+                              "F207ZB" "F207ZC" "F207ZE" "F207ZF" "F207ZG"
+                              "F207IB" "F207IC" "F207IE" "F207IF" "F207IG"
+                             }
+            requires         { CYGHWR_HAL_CORTEXM_STM32 == CYGHWR_HAL_CORTEXM_STM32_F2 }
+            description "
+                This option specifies which member of the STM32F2 family is
+                in use."
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_F4 {
+            display          "F4 processor family selection"
+            flavor           data
+            active_if        { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4" }
+            default_value    {"F407IG"}
+            # NOTEs: The "F4xxxE" parts have 512MB on-chip flash and
+            # the "F4xxxG" parts have 1MB on-chip flash. The "F41xxx"
+            # parts have CRYPTO support.
+            legal_values     {"F405RG" "F405VG" "F405ZG"
+                              "F415RG" "F415VG" "F415ZG"
+                              "F407IG" "F407VG" "F407ZG"
+                              "F407IE" "F407VE" "F407ZE"
+                              "F417IG" "F417VG" "F417ZG"
+                              "F417IE" "F417VE" "F417ZE"
+                             }
+            requires         { CYGHWR_HAL_CORTEXM_STM32 == CYGHWR_HAL_CORTEXM_STM32_F4 }
+            description "
+                This option specifies which member of the STM32F4 family is
+                in use."
+        }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY {
+        display         "Part belongs to connectivity family"
+        default_value   { (CYGHWR_HAL_CORTEXM_STM32 == "F105R8") || (CYGHWR_HAL_CORTEXM_STM32 == "F105V8") ||
+                          (CYGHWR_HAL_CORTEXM_STM32 == "F105RB") || (CYGHWR_HAL_CORTEXM_STM32 == "F105VB") ||
+                          (CYGHWR_HAL_CORTEXM_STM32 == "F105RC") || (CYGHWR_HAL_CORTEXM_STM32 == "F105VC") ||
+                          (CYGHWR_HAL_CORTEXM_STM32 == "F107RB") || (CYGHWR_HAL_CORTEXM_STM32 == "F107VB") ||
+                          (CYGHWR_HAL_CORTEXM_STM32 == "F107RC") || (CYGHWR_HAL_CORTEXM_STM32 == "F107VC") ||
+                          (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4")
+                        }
+        description     "Indicates that this part belongs to the connectivity
+                         family of devices. These have slightly different interrupt
+                         and GPIO layouts to the original STM32 F103 devices."
+    }
+    
     cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
         display         "CPU priority levels"
         flavor          data
@@ -94,20 +201,62 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32 {
    
     cdl_component CYGHWR_HAL_CORTEXM_STM32_CLOCK {
         display         "Clock setup calculations"
-        default_value   1
+        flavor          none
+        no_define
         
         cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE {
             display         "PLL input source"
             flavor          data
             default_value   { "HSE" }
-            legal_values    { "HSI_HALF" "HSE" "HSE_HALF" }
+            legal_values    { "HSI" "HSE" }
+            description     "
+                This sets whether the PLL will be driven by the external
+                high-speed clock (HSE), or internal high-speed clock (HSI)."
         }
 
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV {
+            display         "PLL pre-divider"
+            flavor          data
+            default_value   1
+            legal_values    1 to 63
+            requires        { !CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV <= 2) }
+            requires        { (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F1") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV <= 16) }
+            requires        { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F1") && (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE == "HSI")) implies \
+                                  (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 2) }
+            requires        { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F4")) implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV >= 2) }
+            description     "
+               This option corresponds to the divider used before input to the PLL.
+               On non-connectivity parts, you can only divide by 2 or 1. On other
+               F1 parts, if using HSI as the clock source, then that is automatically
+               divided by 2. If using HSE as the clock source, then this value corresponds
+               to the PREDIV1 field of register RCC_CFGR2. On F2 and F4 parts, this value
+               corresponds to the PLLM field of RCC_PLLCFGR."
+        }
+
+
         cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL {
             display         "PLL multiplier"
             flavor          data
             default_value   9
-            legal_values    2 to 16
+            legal_values    2 to 432
+            requires        { (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F1") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL <= 16) }
+            requires        { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F4")) implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL <= 432) }
+            description     "
+                This value is used to multiply up the PLL input. On the F1 it corresponds
+                to the PLLMUL field of RCC_CFGR. On the F2 and F4 it corresponds to the PLLN
+                field of RCC_PLLCFGR."
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV {
+            display         "SYSCLK divider"
+            flavor          data
+            active_if       { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F4")) }
+            default_value   4
+            legal_values    { 2 4 6 8 }
+            description     "
+                This value is used to divide down the PLL output for use as
+                the SYSCLK clock. This corresponds to the PLLP field of
+                RCC_PLLCFGR"
         }
 
         cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV {
@@ -115,6 +264,7 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32 {
             flavor          data
             default_value   1
             legal_values    { 1 2 4 8 16 64 128 256 512 }
+            description     "Divider for AHB"
         }
         
         cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV {
@@ -122,6 +272,7 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32 {
             flavor          data
             default_value   2
             legal_values    { 1 2 4 8 16 }
+            description     "Divider for APB1"
         }
 
         cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV {
@@ -129,6 +280,20 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32 {
             flavor          data
             default_value   1
             legal_values    { 1 2 4 8 16 }
+            description     "Divider for APB2"
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV {
+            display         "PLLQ divider"
+            flavor          data
+            active_if       { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F4")) }
+            default_value   10
+            legal_values    4 to 15
+            description     "
+               This PLL divider is used in the F2 and F4 families to divide down the
+               PLL output clock (VCO clock) for use by the USB OTG FS, SDIO
+               and RNG peripherals. USB OTG FS requires a 48MHz clock and
+               other peripherals require a clock no greater than 48MHz."
         }
     }
 
@@ -190,6 +355,86 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32 {
         description "The platform has a socket on UART4."
     }
     
+    cdl_interface CYGINT_HAL_STM32_UART5 {
+        display     "Platform has UART5 serial port"
+        description "The platform has a socket on UART5."
+    }
+
+    cdl_option CYGHWR_HAL_STM32_UART0_REMAP {
+        display       "Remap UART0 (USART1) pins"
+        default_value 0
+
+        description   "Remap UART0 (USART1) to alternate set of pins.
+                       This will usually be set by the platform
+                       HAL to reflect the configuration of the hardware."
+    }
+
+    cdl_option CYGHWR_HAL_STM32_UART1_REMAP {
+        display       "Remap UART1 (USART2) pins"
+        default_value 0
+
+        description   "Remap UART1 (USART2) to alternate set of pins.
+                       This will usually be set by the platform
+                       HAL to reflect the configuration of the hardware."
+    }
+
+    cdl_option CYGHWR_HAL_STM32_UART2_REMAP {
+        display       "Remap UART2 (USART3) pins"
+        flavor        data
+        default_value { "NONE" }
+        legal_values  { "NONE" "PARTIAL" "FULL" }
+
+        description   "Remap UART2 (USART3) to alternate set of pins.
+                       This will usually be set by the platform
+                       HAL to reflect the configuration of the hardware."
+    }
+
+    cdl_option CYGHWR_HAL_STM32_I2C1_REMAP {
+        display       "Remap I2C bus 1 pins"
+        default_value 0
+
+        description   "Remap I2C bus 1 to alternate set of pins.
+                       This will usually be set by the platform
+                       HAL to reflect the configuration of the hardware."
+    }
+
+    cdl_option CYGHWR_HAL_STM32_SPI1_REMAP {
+        display       "Remap SPI bus 1 pins"
+        active_if     CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+        default_value 0
+
+        description   "Remap SPI bus 1 to alternate set of pins.
+                       This will usually be set by the platform
+                       HAL to reflect the configuration of the hardware."
+    }
+
+    cdl_option CYGHWR_HAL_STM32_SPI3_REMAP {
+        display       "Remap SPI bus 3 pins"
+        active_if     CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+        default_value 0
+
+        description   "Remap SPI bus 3 to alternate set of pins.
+                       This will usually be set by the platform
+                       HAL to reflect the configuration of the hardware.
+                       This option is only available on connectivity line
+                       devices."
+    }
+
+    cdl_option CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER {
+        display       "Use TIM2 for gprof profiling"
+        active_if     CYGPKG_PROFILE_GPROF
+        flavor        bool
+        default_value 1
+        implements    CYGINT_PROFILE_HAL_TIMER
+        implements    CYGINT_HAL_COMMON_SAVED_INTERRUPT_STATE_REQUIRED
+        description   "
+            The STM32 variant HAL can provide support for gprof-based
+            profiling. This uses timer TIM2 to generate regular interrupts,
+            and the interrupt handler records the PC at the time of the
+            interrupt. Disable this option if you wish to provide
+            an alternative profiling timer implementation."
+    }
+
     cdl_component CYGPKG_HAL_CORTEXM_STM32_OPTIONS {
         display "Build options"
         flavor  none
@@ -231,3 +476,5 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32 {
     }
     
 }
+
+# EOF hal_cortexm_stm32.cdl
diff --git a/packages/hal/cortexm/stm32/var/current/include/var_dma.h b/packages/hal/cortexm/stm32/var/current/include/var_dma.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/var/current/include/var_dma.h
@@ -0,0 +1,146 @@
+#ifndef CYGONCE_HAL_VAR_DMA_H
+#define CYGONCE_HAL_VAR_DMA_H
+//=============================================================================
+//
+//      var_dma.h
+//
+//      STM32 DMA support
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2011-12-07
+// Purpose:     STM32 DMA support
+// Description: 
+// Usage:       #include <cyg/hal/var_dma.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal_cortexm_stm32.h>
+
+#include <cyg/hal/drv_api.h>
+
+//=============================================================================
+// DMA stream descriptors
+
+#define CYGHWR_HAL_STM32_DMA_MODE_P2M           0
+#define CYGHWR_HAL_STM32_DMA_MODE_M2P           1
+#define CYGHWR_HAL_STM32_DMA_MODE_M2M           2
+
+
+// DMA descriptor. Packs interrupt vector, controller, stream and
+// channel IDs together with the mode into a 32 bit descriptor.
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_DMA( __ctlr, __stream, __chan, __mode )        \
+    (((CYGNUM_HAL_INTERRUPT_DMA##__ctlr##_CH##__stream)<<16) |         \
+     ((CYGHWR_HAL_STM32_DMA_MODE_##__mode)<<12) |                       \
+     ((__chan)<<8) | ((__stream)<<4) | ((__ctlr)<<0))
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_DMA( __ctlr, __stream, __chan, __mode )        \
+    (((CYGNUM_HAL_INTERRUPT_DMA##__ctlr##_STR##__stream)<<16) |         \
+     ((CYGHWR_HAL_STM32_DMA_MODE_##__mode)<<12) |                       \
+     ((__chan)<<8) | ((__stream)<<4) | ((__ctlr)<<0))
+#else
+#error "Undefined STM32 family"
+#endif
+
+#define CYGHWR_HAL_STM32_DMA_INTERRUPT( __desc )  (((__desc)>>16)&0xFFFF)
+#define CYGHWR_HAL_STM32_DMA_MODE( __desc )       (((__desc)>>12)&0xF)
+#define CYGHWR_HAL_STM32_DMA_CHANNEL( __desc )    (((__desc)>>8)&0xF)
+#define CYGHWR_HAL_STM32_DMA_STREAM( __desc )     (((__desc)>>4)&0xF)
+#define CYGHWR_HAL_STM32_DMA_CONTROLLER( __desc ) (((__desc)>>0)&0xF)
+
+//=============================================================================
+// API
+
+#ifndef __ASSEMBLER__
+
+typedef struct hal_stm32_dma_stream hal_stm32_dma_stream;
+
+typedef void hal_stm32_dma_callback( hal_stm32_dma_stream *stream, cyg_uint32 count, CYG_ADDRWORD data );
+
+struct hal_stm32_dma_stream
+{
+    // These fields need to be initialized before calling
+    // hal_stm32_dma_init(). This can usually be done statically, when
+    // defining an containing data structure.
+    
+    cyg_uint32                  desc;           // stream descriptor
+    hal_stm32_dma_callback      *callback;      // Callback function
+    CYG_ADDRWORD                data;           // Client private data
+
+    
+    // Runtime data
+    
+    CYG_ADDRWORD                ctlr;           // Controller base address
+    CYG_ADDRWORD                stream;         // Stream/channel index
+
+    cyg_uint32                  ccr;            // Channel control register value
+    cyg_bool                    active;         // Channel active
+    cyg_uint32                  count;          // Bytes left to transfer
+    
+    cyg_interrupt               interrupt;      // DMA interrupt object
+    cyg_handle_t                handle;         // Interrupt handle
+};
+
+
+__externC void hal_stm32_dma_init( hal_stm32_dma_stream *stream, int pri );
+
+__externC void hal_stm32_dma_delete( hal_stm32_dma_stream *stream );
+
+__externC void hal_stm32_dma_disable( hal_stm32_dma_stream *stream );
+
+__externC void hal_stm32_dma_poll( hal_stm32_dma_stream *stream );
+
+__externC void hal_stm32_dma_configure( hal_stm32_dma_stream *stream, int tfr_size,
+                                        cyg_bool no_minc, cyg_bool polled  );
+
+__externC void hal_stm32_dma_configure_circular( hal_stm32_dma_stream *stream,
+                                                 cyg_bool enable);
+
+__externC void hal_stm32_dma_start( hal_stm32_dma_stream *stream, void *memory,
+                                    CYG_ADDRESS peripheral, cyg_uint32 size );
+
+__externC void hal_stm32_dma_show( hal_stm32_dma_stream *stream );
+
+#endif // __ASSEMBLER__
+
+#endif // CYGONCE_HAL_VAR_DMA_H
+//-----------------------------------------------------------------------------
+// end of var_dma.h
diff --git a/packages/hal/cortexm/stm32/var/current/include/var_intr.h b/packages/hal/cortexm/stm32/var/current/include/var_intr.h
--- a/packages/hal/cortexm/stm32/var/current/include/var_intr.h
+++ b/packages/hal/cortexm/stm32/var/current/include/var_intr.h
@@ -4,7 +4,7 @@
 //
 //      var_intr.h
 //
-//      HAL Interrupt and clock assignments for STR7XX variants
+//      HAL Interrupt and clock assignments for STM32 variants
 //
 //==========================================================================
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
@@ -42,9 +42,9 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):    nickg
-// Date:         2008-07-30
+// Date:         2008-10-06
 // Purpose:      Define Interrupt support
-// Description:  The interrupt specifics for ST STR7XX variants are
+// Description:  The interrupt specifics for ST STM32 variants are
 //               defined here.
 //              
 // Usage:        #include <cyg/hal/var_intr.h>
@@ -63,7 +63,12 @@
 #define CYGNUM_HAL_INTERRUPT_WWDG               ( 0+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_PVD                ( 1+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_TAMPER             ( 2+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TAMP_STAMP         ( 2+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name - also timestamps
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGNUM_HAL_INTERRUPT_RTC_GLOBAL         ( 3+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGNUM_HAL_INTERRUPT_RTC_WKUP           ( 3+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#endif
 #define CYGNUM_HAL_INTERRUPT_FLASH              ( 4+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_RCC                ( 5+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_EXTI0              ( 6+CYGNUM_HAL_INTERRUPT_EXTERNAL)
@@ -72,25 +77,41 @@
 #define CYGNUM_HAL_INTERRUPT_EXTI3              ( 9+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 
 #define CYGNUM_HAL_INTERRUPT_EXTI4              (10+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_DMA1_CH1           (11+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_DMA1_CH2           (12+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_DMA1_CH3           (13+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_DMA1_CH4           (14+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_DMA1_CH5           (15+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_DMA1_CH6           (16+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_DMA1_CH7           (17+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_ADC1_2             (18+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA1_CH1           (11+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR0          (11+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA1_CH2           (12+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR1          (12+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA1_CH3           (13+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR2          (13+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA1_CH4           (14+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR3          (14+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA1_CH5           (15+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR4          (15+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA1_CH6           (16+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR5          (16+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA1_CH7           (17+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR6          (17+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_ADC1_2             (18+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 only has ADC1+2
+#define CYGNUM_HAL_INTERRUPT_ADC1_2_3           (18+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has ADC1+2+3
+#define CYGNUM_HAL_INTERRUPT_ADC                (18+CYGNUM_HAL_INTERRUPT_EXTERNAL) // More generic name
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGNUM_HAL_INTERRUPT_USB_HP             (19+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_CAN_TX             (19+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#endif
+#define CYGNUM_HAL_INTERRUPT_CAN1_TX            (19+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGNUM_HAL_INTERRUPT_USB_LP             (20+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_CAN_RX0            (20+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_CAN_RX1            (21+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_CAN_SCE            (22+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#endif
+#define CYGNUM_HAL_INTERRUPT_CAN1_RX0           (20+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN1_RX1           (21+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN1_SCE           (22+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_EXTI9_5            (23+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_TIM1_BRK           (24+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM1_BRK_TIM9      (24+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM9
 #define CYGNUM_HAL_INTERRUPT_TIM1_UP            (25+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM1_UP_TIM10      (25+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM10
 #define CYGNUM_HAL_INTERRUPT_TIM1_TRG           (26+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM1_TRG_COM_TIM11 (26+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM11
 #define CYGNUM_HAL_INTERRUPT_TIM1_CC            (27+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_TIM2               (28+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_TIM3               (29+CYGNUM_HAL_INTERRUPT_EXTERNAL)
@@ -108,28 +129,105 @@
 
 #define CYGNUM_HAL_INTERRUPT_EXTI15_10          (40+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_RTC_ALARM          (41+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGNUM_HAL_INTERRUPT_USB_WAKEUP         (42+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGNUM_HAL_INTERRUPT_OTG_FS_WKUP        (42+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#endif
+#ifndef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
 #define CYGNUM_HAL_INTERRUPT_TIM8_BRK           (43+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_TIM8_UP            (44+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_TIM8_TRG           (45+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_TIM8_CC            (46+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGNUM_HAL_INTERRUPT_ADC3               (47+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#endif
 #define CYGNUM_HAL_INTERRUPT_FSMC               (48+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_SDIO               (49+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#else
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGNUM_HAL_INTERRUPT_TIM8_BRK_TIM12     (43+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM12
+#define CYGNUM_HAL_INTERRUPT_TIM8_UP_TIM13      (44+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM13
+#define CYGNUM_HAL_INTERRUPT_TIM8_TRG_COM_TIM14 (45+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM13
+#define CYGNUM_HAL_INTERRUPT_TIM8_CC            (46+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR7          (47+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_FSMC               (48+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SDIO               (49+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#endif
+#endif
 
 #define CYGNUM_HAL_INTERRUPT_TIM5               (50+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_SPI3               (51+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_UART4              (52+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_UART5              (53+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 #define CYGNUM_HAL_INTERRUPT_TIM6               (54+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM6_DAC           (54+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because also DAC1+2 underrun
 #define CYGNUM_HAL_INTERRUPT_TIM7               (55+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_DMA2_CH1           (56+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_DMA2_CH2           (57+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_DMA2_CH3           (58+CYGNUM_HAL_INTERRUPT_EXTERNAL)
-#define CYGNUM_HAL_INTERRUPT_DMA2_CH4_5         (59+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA2_CH1           (56+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR0          (56+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA2_CH2           (57+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR1          (57+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA2_CH3           (58+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR2          (58+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+
+#ifndef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+# error Support does not yet exist for F2 or F4 without connectivity
+#endif
+
+#define CYGNUM_HAL_INTERRUPT_DMA2_CH4           (59+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA2_CH5           (CYGNUM_HAL_INTERRUPT_DMA2_CH4) // As per RM0008 datasheet 3.3.6 note
 
 #define CYGNUM_HAL_INTERRUPT_NVIC_MAX           (59+CYGNUM_HAL_INTERRUPT_EXTERNAL)
 
+#else
+
+#define CYGNUM_HAL_INTERRUPT_DMA2_CH4           (59+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR3          (59+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+
+#define CYGNUM_HAL_INTERRUPT_DMA2_CH5           (60+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR4          (60+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_ETH                (61+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ETH_WAKEUP         (62+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN2_TX            (63+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN2_RX0           (64+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN2_RX1           (65+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN2_SCE           (66+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGNUM_HAL_INTERRUPT_USB_FS             (67+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_NVIC_MAX           (67+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGNUM_HAL_INTERRUPT_OTG_FS             (67+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR5          (68+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR6          (69+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR7          (70+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART6              (71+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C3_EV            (72+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C3_ER            (73+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_OTG_HS_EP1_OUT     (74+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_OTG_HS_EP1_IN      (75+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_OTG_HS_WKUP        (76+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_OTG_HS             (77+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DCMI               (78+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CRYP               (79+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_HASH_RNG           (80+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+# define CYGNUM_HAL_INTERRUPT_HASH_FPU          (81+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+# define CYGNUM_HAL_INTERRUPT_NVIC_MAX          (81+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+# define CYGNUM_HAL_INTERRUPT_NVIC_MAX          (80+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#else
+# error "Support does not yet exist for this FAMILY_HIPERFORMANCE configuration"
+#endif
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#endif // ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+
 #define CYGNUM_HAL_INTERRUPT_EXTI5              ( 1+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
 #define CYGNUM_HAL_INTERRUPT_EXTI6              ( 2+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
 #define CYGNUM_HAL_INTERRUPT_EXTI7              ( 3+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
@@ -155,6 +253,45 @@
 //==========================================================================
 // Interrupt mask and config for variant-specific devices
 
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define HAL_VAR_PERIPH_EXTI_MAP_FAMILY                                  \
+    case CYGNUM_HAL_INTERRUPT_PVD:                                      \
+        __v =  16;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_RTC_ALARM:                                \
+        __v =  17;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_USB_WAKEUP:                               \
+        __v =  18;                                                      \
+        break;
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define HAL_VAR_PERIPH_EXTI_MAP_FAMILY                                  \
+    case CYGNUM_HAL_INTERRUPT_PVD:                                      \
+        __v =  16;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_RTC_ALARM:                                \
+        __v =  17;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_OTG_FS_WKUP:                              \
+        __v =  18;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_ETH_WAKEUP:                               \
+        __v =  19;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_OTG_HS_WKUP:                              \
+        __v =  20;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_TAMP_STAMP:                               \
+        __v =  21;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_RTC_WKUP:                                 \
+        __v =  22;                                                      \
+        break;
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
 #define HAL_VAR_INTERRUPT_MASK( __vector )                              \
 {                                                                       \
     cyg_int32 __v = -1;                                                 \
@@ -173,17 +310,7 @@
         __v =  __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5;               \
         break;                                                          \
                                                                         \
-    case CYGNUM_HAL_INTERRUPT_PVD:                                      \
-        __v =  16;                                                      \
-        break;                                                          \
-                                                                        \
-    case CYGNUM_HAL_INTERRUPT_RTC_ALARM:                                \
-        __v =  17;                                                      \
-        break;                                                          \
-                                                                        \
-    case CYGNUM_HAL_INTERRUPT_USB_WAKEUP:                               \
-        __v =  18;                                                      \
-        break;                                                          \
+    HAL_VAR_PERIPH_EXTI_MAP_FAMILY                                      \
     }                                                                   \
                                                                         \
     if( __v >= 0 )                                                      \
@@ -217,17 +344,7 @@
                           CYGARC_REG_NVIC_IBIT(CYGNUM_HAL_INTERRUPT_EXTI15_10-CYGNUM_HAL_INTERRUPT_EXTERNAL) ); \
         break;                                                          \
                                                                         \
-    case CYGNUM_HAL_INTERRUPT_PVD:                                      \
-        __v =  16;                                                      \
-        break;                                                          \
-                                                                        \
-    case CYGNUM_HAL_INTERRUPT_RTC_ALARM:                                \
-        __v =  17;                                                      \
-        break;                                                          \
-                                                                        \
-    case CYGNUM_HAL_INTERRUPT_USB_WAKEUP:                               \
-        __v =  18;                                                      \
-        break;                                                          \
+    HAL_VAR_PERIPH_EXTI_MAP_FAMILY                                      \
     }                                                                   \
                                                                         \
     if( __v >= 0 )                                                      \
@@ -259,17 +376,7 @@
         __v =  __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5;               \
         break;                                                          \
                                                                         \
-    case CYGNUM_HAL_INTERRUPT_PVD:                                      \
-        __v =  16;                                                      \
-        break;                                                          \
-                                                                        \
-    case CYGNUM_HAL_INTERRUPT_RTC_ALARM:                                \
-        __v =  17;                                                      \
-        break;                                                          \
-                                                                        \
-    case CYGNUM_HAL_INTERRUPT_USB_WAKEUP:                               \
-        __v =  18;                                                      \
-        break;                                                          \
+    HAL_VAR_PERIPH_EXTI_MAP_FAMILY                                      \
     }                                                                   \
                                                                         \
     if( __v >= 0 )                                                      \
@@ -297,17 +404,7 @@
         __v =  __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5;               \
         break;                                                          \
                                                                         \
-    case CYGNUM_HAL_INTERRUPT_PVD:                                      \
-        __v =  16;                                                      \
-        break;                                                          \
-                                                                        \
-    case CYGNUM_HAL_INTERRUPT_RTC_ALARM:                                \
-        __v =  17;                                                      \
-        break;                                                          \
-                                                                        \
-    case CYGNUM_HAL_INTERRUPT_USB_WAKEUP:                               \
-        __v =  18;                                                      \
-        break;                                                          \
+    HAL_VAR_PERIPH_EXTI_MAP_FAMILY                                      \
     }                                                                   \
                                                                         \
     if(( __v >= 0 ) && !(__level) )                                     \
diff --git a/packages/hal/cortexm/stm32/var/current/include/var_io.h b/packages/hal/cortexm/stm32/var/current/include/var_io.h
--- a/packages/hal/cortexm/stm32/var/current/include/var_io.h
+++ b/packages/hal/cortexm/stm32/var/current/include/var_io.h
@@ -10,7 +10,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008, 2009 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2009, 2013 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -44,7 +44,7 @@
 // Author(s):   nickg
 // Date:        2008-07-30
 // Purpose:     STM32 variant specific registers
-// Description: 
+// Description:
 // Usage:       #include <cyg/hal/var_io.h>
 //
 //####DESCRIPTIONEND####
@@ -64,6 +64,11 @@
 #define CYGHWR_HAL_STM32_TIM5           0x40000C00
 #define CYGHWR_HAL_STM32_TIM6           0x40001000
 #define CYGHWR_HAL_STM32_TIM7           0x40001400
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_TIM12          0x40001800
+#define CYGHWR_HAL_STM32_TIM13          0x40001C00
+#define CYGHWR_HAL_STM32_TIM14          0x40002000
+#endif
 #define CYGHWR_HAL_STM32_RTC            0x40002800
 #define CYGHWR_HAL_STM32_WWDG           0x40002C00
 #define CYGHWR_HAL_STM32_IWDG           0x40003000
@@ -75,12 +80,22 @@
 #define CYGHWR_HAL_STM32_UART5          0x40005000
 #define CYGHWR_HAL_STM32_I2C1           0x40005400
 #define CYGHWR_HAL_STM32_I2C2           0x40005800
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGHWR_HAL_STM32_USB            0x40005C00
 #define CYGHWR_HAL_STM32_USB_CAN_SRAM   0x40006000
-#define CYGHWR_HAL_STM32_BXCAN          0x40006400
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_I2C3           0x40005C00
+#endif
+#define CYGHWR_HAL_STM32_BXCAN1         0x40006400
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_BXCAN2         0x40006800
+#endif
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGHWR_HAL_STM32_BKP            0x40006C00
+#endif
 #define CYGHWR_HAL_STM32_PWR            0x40007000
 #define CYGHWR_HAL_STM32_DAC            0x40007400
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGHWR_HAL_STM32_AFIO           0x40010000
 #define CYGHWR_HAL_STM32_EXTI           0x40010400
 #define CYGHWR_HAL_STM32_GPIOA          0x40010800
@@ -93,7 +108,21 @@
 #define CYGHWR_HAL_STM32_ADC1           0x40012400
 #define CYGHWR_HAL_STM32_ADC2           0x40012800
 #define CYGHWR_HAL_STM32_TIM1           0x40012C00
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_TIM1           0x40010000
+#define CYGHWR_HAL_STM32_PWM1           0x40010000
+#define CYGHWR_HAL_STM32_TIM8           0x40010400
+#define CYGHWR_HAL_STM32_PWM2           0x40010400
+#define CYGHWR_HAL_STM32_UART1          0x40011000
+#define CYGHWR_HAL_STM32_UART6          0x40011400
+#define CYGHWR_HAL_STM32_ADC1           0x40012000
+#define CYGHWR_HAL_STM32_ADC2           CYGHWR_HAL_STM32_ADC1 + 0x0100
+#define CYGHWR_HAL_STM32_ADC3           CYGHWR_HAL_STM32_ADC1 + 0x0200
+#define CYGHWR_HAL_STM32_ADC_COMMON     CYGHWR_HAL_STM32_ADC1 + 0x0300
+#define CYGHWR_HAL_STM32_SDIO           0x40012C00
+#endif
 #define CYGHWR_HAL_STM32_SPI1           0x40013000
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGHWR_HAL_STM32_TIM8           0x40013400
 #define CYGHWR_HAL_STM32_UART1          0x40013800
 #define CYGHWR_HAL_STM32_ADC3           0x40013C00
@@ -102,8 +131,42 @@
 #define CYGHWR_HAL_STM32_DMA2           0x40020400
 #define CYGHWR_HAL_STM32_RCC            0x40021000
 #define CYGHWR_HAL_STM32_FLASH          0x40022000
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_SYSCFG         0x40013800
+#define CYGHWR_HAL_STM32_EXTI           0x40013C00
+#define CYGHWR_HAL_STM32_TIM9           0x40014000
+#define CYGHWR_HAL_STM32_TIM10          0x40014400
+#define CYGHWR_HAL_STM32_TIM11          0x40014800
+#define CYGHWR_HAL_STM32_GPIOA          0x40020000
+#define CYGHWR_HAL_STM32_GPIOB          0x40020400
+#define CYGHWR_HAL_STM32_GPIOC          0x40020800
+#define CYGHWR_HAL_STM32_GPIOD          0x40020C00
+#define CYGHWR_HAL_STM32_GPIOE          0x40021000
+#define CYGHWR_HAL_STM32_GPIOF          0x40021400
+#define CYGHWR_HAL_STM32_GPIOG          0x40021800
+#define CYGHWR_HAL_STM32_GPIOH          0x40021C00
+#define CYGHWR_HAL_STM32_GPIOI          0x40022000
+#endif
 #define CYGHWR_HAL_STM32_CRC            0x40023000
-
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_RCC            0x40023800
+#define CYGHWR_HAL_STM32_FLASH          0x40023C00
+#define CYGHWR_HAL_STM32_BKPSRAM        0x40024000
+#define CYGHWR_HAL_STM32_DMA1           0x40026000
+#define CYGHWR_HAL_STM32_DMA2           0x40026400
+#endif
+#define CYGHWR_HAL_STM32_ETH            0x40028000
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_USB_OTG_HS     0x40040000
+#endif
+#define CYGHWR_HAL_STM32_USB_OTG_FS     0x50000000
+#define CYGHWR_HAL_STM32_OTG            CYGHWR_HAL_STM32_USB_OTG_FS // compatibility define. Deprecated.
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_DCMI           0x50050000
+#define CYGHWR_HAL_STM32_CRYP           0x50060000
+#define CYGHWR_HAL_STM32_HASH           0x50060400
+#define CYGHWR_HAL_STM32_RNG            0x50060800
+#endif
 #define CYGHWR_HAL_STM32_FSMC           0xA0000000
 
 //=============================================================================
@@ -125,6 +188,7 @@
 // Not all registers are described here
 
 #define CYGHWR_HAL_STM32_RCC_CR                 0x00
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGHWR_HAL_STM32_RCC_CFGR               0x04
 #define CYGHWR_HAL_STM32_RCC_CIR                0x08
 #define CYGHWR_HAL_STM32_RCC_APB2RSTR           0x0C
@@ -134,6 +198,32 @@
 #define CYGHWR_HAL_STM32_RCC_APB1ENR            0x1C
 #define CYGHWR_HAL_STM32_RCC_BDCR               0x20
 #define CYGHWR_HAL_STM32_RCC_CSR                0x24
+# ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+#define CYGHWR_HAL_STM32_RCC_AHBRSTR            0x28
+#define CYGHWR_HAL_STM32_RCC_CFGR2              0x2C
+# endif
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR            0x04
+#define CYGHWR_HAL_STM32_RCC_CFGR               0x08
+#define CYGHWR_HAL_STM32_RCC_CIR                0x0C
+#define CYGHWR_HAL_STM32_RCC_AHB1RSTR           0x10
+#define CYGHWR_HAL_STM32_RCC_AHB2RSTR           0x14
+#define CYGHWR_HAL_STM32_RCC_AHB3RSTR           0x18
+#define CYGHWR_HAL_STM32_RCC_APB1RSTR           0x20
+#define CYGHWR_HAL_STM32_RCC_APB2RSTR           0x24
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR            0x30
+#define CYGHWR_HAL_STM32_RCC_AHB2ENR            0x34
+#define CYGHWR_HAL_STM32_RCC_AHB3ENR            0x38
+#define CYGHWR_HAL_STM32_RCC_APB1ENR            0x40
+#define CYGHWR_HAL_STM32_RCC_APB2ENR            0x44
+#define CYGHWR_HAL_STM32_RCC_AHB1LPENR          0x50
+#define CYGHWR_HAL_STM32_RCC_AHB2LPENR          0x54
+#define CYGHWR_HAL_STM32_RCC_AHB3LPENR          0x58
+#define CYGHWR_HAL_STM32_RCC_APB1LPENR          0x60
+#define CYGHWR_HAL_STM32_RCC_APB2LPENR          0x64
+#define CYGHWR_HAL_STM32_RCC_BDCR               0x70
+#define CYGHWR_HAL_STM32_RCC_CSR                0x74
+#endif
 
 #define CYGHWR_HAL_STM32_RCC_CR_HSION           BIT_(0)
 #define CYGHWR_HAL_STM32_RCC_CR_HSIRDY          BIT_(1)
@@ -145,6 +235,26 @@
 #define CYGHWR_HAL_STM32_RCC_CR_CSSON           BIT_(19)
 #define CYGHWR_HAL_STM32_RCC_CR_PLLON           BIT_(24)
 #define CYGHWR_HAL_STM32_RCC_CR_PLLRDY          BIT_(25)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_RCC_CR_PLLI2SON        BIT_(26)
+#define CYGHWR_HAL_STM32_RCC_CR_PLLI2SRDY       BIT_(27)
+#endif
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLM(__m)  VALUE_(0,__m)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLM_MASK  MASK_(0,6)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLN(__n)  VALUE_(6,__n)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLN_MASK  MASK_(6,9)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP(__p)  VALUE_(16,((__p)>>1)-1 )
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_2     VALUE_(16,0)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_4     VALUE_(16,1)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_6     VALUE_(16,2)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_8     VALUE_(16,3)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLSRC_HSI VALUE_(22,0)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLSRC_HSE VALUE_(22,1)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLQ(__q)  VALUE_(24,__q)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLQ_MASK  MASK_(24,4)
+#endif
 
 #define CYGHWR_HAL_STM32_RCC_CFGR_SW_HSI        VALUE_(0,0)
 #define CYGHWR_HAL_STM32_RCC_CFGR_SW_HSE        VALUE_(0,1)
@@ -163,16 +273,17 @@
 #define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_128      VALUE_(4,13)
 #define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_256      VALUE_(4,14)
 #define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_512      VALUE_(4,15)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_1       VALUE_(8,0)
 #define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_2       VALUE_(8,4)
 #define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_4       VALUE_(8,5)
 #define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_8       VALUE_(8,6)
 #define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_16      VALUE_(8,7)
 #define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_1       VALUE_(11,0)
-#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_2       VALUE_(11,0)
-#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_4       VALUE_(11,0)
-#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_8       VALUE_(11,0)
-#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_16      VALUE_(11,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_2       VALUE_(11,4)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_4       VALUE_(11,5)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_8       VALUE_(11,6)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_16      VALUE_(11,7)
 #define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_2      VALUE_(14,0)
 #define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_4      VALUE_(14,1)
 #define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_6      VALUE_(14,2)
@@ -180,6 +291,7 @@
 #define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_XXX    VALUE_(14,3)
 #define CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_HSI    0
 #define CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_HSE    BIT_(16)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_PREDIV1 BIT_(16)
 #define CYGHWR_HAL_STM32_RCC_CFGR_PLLXTPRE      BIT_(17)
 #define CYGHWR_HAL_STM32_RCC_CFGR_PLLMUL(__x)   VALUE_(18,(__x)-2)
 #define CYGHWR_HAL_STM32_RCC_CFGR_USBPRE        BIT_(22)
@@ -188,63 +300,228 @@
 #define CYGHWR_HAL_STM32_RCC_CFGR_MCO_HSI       VALUE_(24,5)
 #define CYGHWR_HAL_STM32_RCC_CFGR_MCO_HSE       VALUE_(24,6)
 #define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL       VALUE_(24,7)
-
-
-#define CYGHWR_HAL_STM32_RCC_AHBENR_DMA1        BIT_(0)
-#define CYGHWR_HAL_STM32_RCC_AHBENR_DMA2        BIT_(1)
-#define CYGHWR_HAL_STM32_RCC_AHBENR_SRAM        BIT_(2)
-#define CYGHWR_HAL_STM32_RCC_AHBENR_FLITF       BIT_(4)
-#define CYGHWR_HAL_STM32_RCC_AHBENR_CRC         BIT_(6)
-#define CYGHWR_HAL_STM32_RCC_AHBENR_FSMC        BIT_(8)
-#define CYGHWR_HAL_STM32_RCC_AHBENR_SDIO        BIT_(10)
+# ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL2      VALUE_(24,8)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL3_HALF VALUE_(24,9)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_XT1       VALUE_(24,10)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL3      VALUE_(24,11)
+#define CYGHWR_HAL_STM32_RCC_CR_PLL2ON          BIT_(26)
+#define CYGHWR_HAL_STM32_RCC_CR_PLL2RDY         BIT_(27)
+# endif
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_1       VALUE_(10,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_2       VALUE_(10,4)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_4       VALUE_(10,5)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_8       VALUE_(10,6)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_16      VALUE_(10,7)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_1       VALUE_(13,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_2       VALUE_(13,4)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_4       VALUE_(13,5)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_8       VALUE_(13,6)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_16      VALUE_(13,7)
+#define CYGHWR_HAL_STM32_RCC_CFGR_RTCPRE(__x)   VALUE_(16,__x)
+#define CYGHWR_HAL_STM32_RCC_CFGR_RTCPRE_MASK   MASK_(16,5)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_MASK     MASK_(21,2)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSI      VALUE_(21,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_LSE      VALUE_(21,1)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSE      VALUE_(21,2)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_PLL      VALUE_(21,3)
+#define CYGHWR_HAL_STM32_RCC_CFGR_I2SSRC_PLLI2S VALUE_(23,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_I2SSRC_EXT    VALUE_(23,1)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_MASK  MASK_(24,3)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_1     VALUE_(24,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_2     VALUE_(24,4)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_3     VALUE_(24,5)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_4     VALUE_(24,6)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_5     VALUE_(24,7)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_MASK  MASK_(27,3)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_1     VALUE_(27,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_2     VALUE_(27,4)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_3     VALUE_(27,5)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_4     VALUE_(27,6)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_5     VALUE_(27,7)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_MASK     MASK_(30,2)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_SYSCLK   VALUE_(30,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_PLLI2S   VALUE_(30,1)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_HSE      VALUE_(30,2)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_PLL      VALUE_(30,3)
+#endif
 
-#define CYGHWR_HAL_STM32_RCC_APB2ENR_AFIO       BIT_(0)
-#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPA       BIT_(2)
-#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPB       BIT_(3)
-#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPC       BIT_(4)
-#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPD       BIT_(5)
-#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPE       BIT_(6)
-#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPF       BIT_(7)
-#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPG       BIT_(8)
-#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC1       BIT_(9)
-#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC2       BIT_(10)
-#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM1       BIT_(11)
-#define CYGHWR_HAL_STM32_RCC_APB2ENR_SPI1       BIT_(12)
-#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM8       BIT_(13)
-#define CYGHWR_HAL_STM32_RCC_APB2ENR_UART1      BIT_(14)
-#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC3       BIT_(15)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_DMA1        (0)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_DMA2        (1)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_SRAM        (2)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_FLITF       (4)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_CRC         (6)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_FSMC        (8)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_SDIO        (10)
+#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+#define CYGHWR_HAL_STM32_RCC_AHBENR_OTGFS       (12)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_ETHMAC      (14)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_ETHMACTX    (15)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_ETHMACRX    (16)
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_RCC_AHBRSTR_OTGFSRST   BIT_(12)
+#define CYGHWR_HAL_STM32_RCC_AHBRSTR_ETHMACRST  BIT_(14)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_RCC_AHB1RSTR_ETHMACRST BIT_(25)
+#endif
+#endif
+
+// Note that the following are bit numbers, not masks. They should
+// either be used with the CYGHWR_HAL_STM32_CLOCK() macro or used to
+// shift a 1, perhaps using the BIT_() macro.
+//
+// Note that in the F2/F4 families, the bit positions in the LP registers are
+// the same.
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_AFIO       (0)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPA       (2)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPB       (3)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPC       (4)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPD       (5)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPE       (6)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPF       (7)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPG       (8)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC1       (9)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC2       (10)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM1       (11)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_SPI1       (12)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM8       (13)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_UART1      (14)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC3       (15)
 
 
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM2       BIT_(0)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM3       BIT_(1)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM4       BIT_(2)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM5       BIT_(3)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM6       BIT_(4)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM7       BIT_(5)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_WWDG       BIT_(11)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI2       BIT_(14)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI3       BIT_(15)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART2      BIT_(17)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART3      BIT_(18)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART4      BIT_(19)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART5      BIT_(20)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C1       BIT_(21)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C2       BIT_(22)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_USB        BIT_(23)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN        BIT_(25)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_BKP        BIT_(27)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_PWR        BIT_(28)
-#define CYGHWR_HAL_STM32_RCC_APB1ENR_DAC        BIT_(29)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM2       (0)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM3       (1)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM4       (2)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM5       (3)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM6       (4)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM7       (5)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_WWDG       (11)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI2       (14)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI3       (15)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART2      (17)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART3      (18)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART4      (19)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART5      (20)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C1       (21)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C2       (22)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_USB        (23)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN1       (25)
+#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN2       (26)
+#endif
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_BKP        (27)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_PWR        (28)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_DAC        (29)
+
+#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV1(__x)     VALUE_(0,__x)
+#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV2(__x)     VALUE_(4,__x)
+#define CYGHWR_HAL_STM32_RCC_CFGR2_PLL2MUL(__x)     VALUE_(8,__x)
+#define CYGHWR_HAL_STM32_RCC_CFGR2_PLL3MUL(__x)     VALUE_(12,__x)
+#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV1SRC_HSE   0
+#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV1SRC_PLL2  BIT_(16)
+#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S2SRC_SYSCLK   0
+#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S2SRC_PLL3     BIT_(17)
+#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S3SRC_SYSCLK   0
+#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S3SRC_PLL3     BIT_(18)
+#endif
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOA       (0)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOB       (1)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOC       (2)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOD       (3)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOE       (4)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOF       (5)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOG       (6)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOH       (7)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOI       (8)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_CRC        (12)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_BKPSRAM    (18)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_CCMDATARAMEN (20)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_DMA1       (21)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_DMA2       (22)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMAC     (25)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMACTX   (26)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMACRX   (27)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMACPTP  (28)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_OTGHS      (29)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_OTGHSULPI  (30)
 
-#define CYGHWR_HAL_STM32_RCC_CSR_LSION          BIT_(0)
-#define CYGHWR_HAL_STM32_RCC_CSR_LSIRDY         BIT_(1)
-#define CYGHWR_HAL_STM32_RCC_CSR_RMVF           BIT_(24)
-#define CYGHWR_HAL_STM32_RCC_CSR_PINRSTF        BIT_(26)
-#define CYGHWR_HAL_STM32_RCC_CSR_PORRSTF        BIT_(27)
-#define CYGHWR_HAL_STM32_RCC_CSR_SFTRSTF        BIT_(28)
-#define CYGHWR_HAL_STM32_RCC_CSR_IWDGRSTF       BIT_(29)
-#define CYGHWR_HAL_STM32_RCC_CSR_WWDGRSTF       BIT_(30)
-#define CYGHWR_HAL_STM32_RCC_CSR_LPWRRSTF       BIT_(31)
+#define CYGHWR_HAL_STM32_RCC_AHB2ENR_DCMI        (0)
+#define CYGHWR_HAL_STM32_RCC_AHB2ENR_CRYP        (4)
+#define CYGHWR_HAL_STM32_RCC_AHB2ENR_HASH        (5)
+#define CYGHWR_HAL_STM32_RCC_AHB2ENR_RNG         (6)
+#define CYGHWR_HAL_STM32_RCC_AHB2ENR_OTGFS       (7)
+
+#define CYGHWR_HAL_STM32_RCC_AHB3ENR_FSMC        (0)
+
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM2        (0)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM3        (1)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM4        (2)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM5        (3)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM6        (4)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM7        (5)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM12       (6)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM13       (7)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM14       (8)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_WWDG       (11)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI2       (14)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI3       (15)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART2      (17)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART3      (18)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART4      (19)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART5      (20)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C1       (21)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C2       (22)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C3       (23)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN1       (25)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN2       (26)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_PWR        (28)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_DAC        (29)
+
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM1        (0)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM8        (1)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_UART1       (4)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_UART6       (5)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC1        (8)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC2        (9)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC3       (10)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_SDIO       (11)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_SPI1       (12)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_SYSCFG     (14)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM9       (16)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM10      (17)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM11      (18)
+
+#endif
+
+// The following encodes the control register and clock bit number
+// into a 32 bit descriptor.
+#define CYGHWR_HAL_STM32_CLOCK( __reg, __pin )                  \
+            ((CYGHWR_HAL_STM32_RCC_##__reg##ENR) |              \
+             ((CYGHWR_HAL_STM32_RCC_##__reg##ENR_##__pin)<<16))
+
+// Macros to extract encoded values.
+#define CYGHWR_HAL_STM32_CLOCK_REG( __desc ) ((__desc)&0xFF)
+#define CYGHWR_HAL_STM32_CLOCK_PIN( __desc ) (((__desc)>>16)&0xFF)
+
+// Functions and macros to enable/disable clocks.
+
+__externC void hal_stm32_clock_enable( cyg_uint32 desc );
+__externC void hal_stm32_clock_disable( cyg_uint32 desc );
+
+#define CYGHWR_HAL_STM32_CLOCK_ENABLE( __desc ) hal_stm32_clock_enable( __desc )
+#define CYGHWR_HAL_STM32_CLOCK_DISABLE( __desc ) hal_stm32_clock_disable( __desc )
+
 
 #define CYGHWR_HAL_STM32_RCC_BDCR_LSEON         BIT_(0)
 #define CYGHWR_HAL_STM32_RCC_BDCR_LSERDY        BIT_(1)
@@ -257,9 +534,32 @@
 #define CYGHWR_HAL_STM32_RCC_BDCR_RTCEN         BIT_(15)
 #define CYGHWR_HAL_STM32_RCC_BDCR_BDRST         BIT_(16)
 
+#define CYGHWR_HAL_STM32_RCC_CSR_LSION          BIT_(0)
+#define CYGHWR_HAL_STM32_RCC_CSR_LSIRDY         BIT_(1)
+#define CYGHWR_HAL_STM32_RCC_CSR_RMVF           BIT_(24)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_RCC_CSR_BORRSTF        BIT_(25)
+#endif
+#define CYGHWR_HAL_STM32_RCC_CSR_PINRSTF        BIT_(26)
+#define CYGHWR_HAL_STM32_RCC_CSR_PORRSTF        BIT_(27)
+#define CYGHWR_HAL_STM32_RCC_CSR_SFTRSTF        BIT_(28)
+#define CYGHWR_HAL_STM32_RCC_CSR_IWDGRSTF       BIT_(29)
+#define CYGHWR_HAL_STM32_RCC_CSR_WWDGRSTF       BIT_(30)
+#define CYGHWR_HAL_STM32_RCC_CSR_LPWRRSTF       BIT_(31)
+
+
+// Miscellaneous clock control bits
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_CLOCK_BKP              CYGHWR_HAL_STM32_CLOCK( APB1, BKP )
+#endif
+
+#define CYGHWR_HAL_STM32_CLOCK_PWR              CYGHWR_HAL_STM32_CLOCK( APB1, PWR )
+
 //=============================================================================
 // Realtime Clock
 
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGHWR_HAL_STM32_RTC_CRH                0x00
 #define CYGHWR_HAL_STM32_RTC_CRL                0x04
 #define CYGHWR_HAL_STM32_RTC_PRLH               0x08
@@ -286,6 +586,190 @@
 #define CYGHWR_HAL_STM32_RTC_CRL_CNF            BIT_(4)
 #define CYGHWR_HAL_STM32_RTC_CRL_RTOFF          BIT_(5)
 
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_RTC_TR                 0x00
+#define CYGHWR_HAL_STM32_RTC_DR                 0x04
+#define CYGHWR_HAL_STM32_RTC_CR                 0x08
+#define CYGHWR_HAL_STM32_RTC_ISR                0x0C
+#define CYGHWR_HAL_STM32_RTC_PRER               0x10
+#define CYGHWR_HAL_STM32_RTC_WUTR               0x14
+#define CYGHWR_HAL_STM32_RTC_CALIBR             0x18
+#define CYGHWR_HAL_STM32_RTC_ALRMAR             0x1C
+#define CYGHWR_HAL_STM32_RTC_ALRMBR             0x20
+#define CYGHWR_HAL_STM32_RTC_WPR                0x24
+#define CYGHWR_HAL_STM32_RTC_TSTR               0x30
+#define CYGHWR_HAL_STM32_RTC_TSDR               0x34
+#define CYGHWR_HAL_STM32_RTC_TAFCR              0x40
+#define CYGHWR_HAL_STM32_RTC_BKxR(_x)           (0x50 + 4*(_x))
+
+#define CYGHWR_HAL_STM32_RTC_TR_SU              MASK_(0,4)
+#define CYGHWR_HAL_STM32_RTC_TR_SU_SHIFT        0
+#define CYGHWR_HAL_STM32_RTC_TR_ST              MASK_(4,3)
+#define CYGHWR_HAL_STM32_RTC_TR_ST_SHIFT        4
+#define CYGHWR_HAL_STM32_RTC_TR_MNU             MASK_(8,4)
+#define CYGHWR_HAL_STM32_RTC_TR_MNU_SHIFT       8
+#define CYGHWR_HAL_STM32_RTC_TR_MNT             MASK_(12,3)
+#define CYGHWR_HAL_STM32_RTC_TR_MNT_SHIFT       12
+#define CYGHWR_HAL_STM32_RTC_TR_HU              MASK_(16,4)
+#define CYGHWR_HAL_STM32_RTC_TR_HU_SHIFT        16
+#define CYGHWR_HAL_STM32_RTC_TR_HT              MASK_(20,2)
+#define CYGHWR_HAL_STM32_RTC_TR_HT_SHIFT        20
+#define CYGHWR_HAL_STM32_RTC_TR_AM              VALUE_(22, 0)
+#define CYGHWR_HAL_STM32_RTC_TR_PM              VALUE_(22, 1)
+
+#define CYGHWR_HAL_STM32_RTC_DR_DU              MASK_(0,4)
+#define CYGHWR_HAL_STM32_RTC_DR_DU_SHIFT        0
+#define CYGHWR_HAL_STM32_RTC_DR_DT              MASK_(4,2)
+#define CYGHWR_HAL_STM32_RTC_DR_DT_SHIFT        4
+#define CYGHWR_HAL_STM32_RTC_DR_MU              MASK_(8,4)
+#define CYGHWR_HAL_STM32_RTC_DR_MU_SHIFT        8
+#define CYGHWR_HAL_STM32_RTC_DR_MT              BIT_(12)
+#define CYGHWR_HAL_STM32_RTC_DR_MT_SHIFT        12
+#define CYGHWR_HAL_STM32_RTC_DR_WDU_MON         VALUE_(13,1)
+#define CYGHWR_HAL_STM32_RTC_DR_WDU_TUE         VALUE_(13,2)
+#define CYGHWR_HAL_STM32_RTC_DR_WDU_WED         VALUE_(13,3)
+#define CYGHWR_HAL_STM32_RTC_DR_WDU_THU         VALUE_(13,4)
+#define CYGHWR_HAL_STM32_RTC_DR_WDU_FRI         VALUE_(13,5)
+#define CYGHWR_HAL_STM32_RTC_DR_WDU_SAT         VALUE_(13,6)
+#define CYGHWR_HAL_STM32_RTC_DR_WDU_SUN         VALUE_(13,7)
+#define CYGHWR_HAL_STM32_RTC_DR_YU              MASK_(16,4)
+#define CYGHWR_HAL_STM32_RTC_DR_YU_SHIFT        16
+#define CYGHWR_HAL_STM32_RTC_DR_YT              MASK_(20,4)
+#define CYGHWR_HAL_STM32_RTC_DR_YT_SHIFT        20
+
+#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_16      VALUE_(0,0)
+#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_8       VALUE_(0,1)
+#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_4       VALUE_(0,2)
+#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_2       VALUE_(0,3)
+#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_CK_SPRE VALUE_(0,4)
+#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_CK_SPRE_PLUS_216 VALUE_(0,6)
+#define CYGHWR_HAL_STM32_RTC_CR_TSEDGE          BIT_(3)
+#define CYGHWR_HAL_STM32_RTC_CR_REFCKON         BIT_(4)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGHWR_HAL_STM32_RTC_CR_BYPSHAD         BIT_(5)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGHWR_HAL_STM32_RTC_CR_FMT             BIT_(6)
+#define CYGHWR_HAL_STM32_RTC_CR_DCE             BIT_(7)
+#define CYGHWR_HAL_STM32_RTC_CR_ALRAE           BIT_(8)
+#define CYGHWR_HAL_STM32_RTC_CR_ALRBE           BIT_(9)
+#define CYGHWR_HAL_STM32_RTC_CR_WUTE            BIT_(10)
+#define CYGHWR_HAL_STM32_RTC_CR_TSE             BIT_(11)
+#define CYGHWR_HAL_STM32_RTC_CR_ALRAIE          BIT_(12)
+#define CYGHWR_HAL_STM32_RTC_CR_ALRBIE          BIT_(13)
+#define CYGHWR_HAL_STM32_RTC_CR_WUTIE           BIT_(14)
+#define CYGHWR_HAL_STM32_RTC_CR_TSIE            BIT_(15)
+#define CYGHWR_HAL_STM32_RTC_CR_ADD1H           BIT_(16)
+#define CYGHWR_HAL_STM32_RTC_CR_SUB1H           BIT_(17)
+#define CYGHWR_HAL_STM32_RTC_CR_BKP             BIT_(18)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGHWR_HAL_STM32_RTC_CR_COSEL           BIT_(19)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGHWR_HAL_STM32_RTC_CR_POL             BIT_(20)
+#define CYGHWR_HAL_STM32_RTC_CR_OSEL_DISABLE    VALUE_(21, 0)
+#define CYGHWR_HAL_STM32_RTC_CR_OSEL_ALRAOE     VALUE_(21, 1)
+#define CYGHWR_HAL_STM32_RTC_CR_OSEL_ALRBOE     VALUE_(21, 2)
+#define CYGHWR_HAL_STM32_RTC_CR_OSEL_WUOE       VALUE_(21, 3)
+#define CYGHWR_HAL_STM32_RTC_CR_OSEL_COE        BIT_(23)
+
+#define CYGHWR_HAL_STM32_RTC_ISR_ALRAWF         BIT_(0)
+#define CYGHWR_HAL_STM32_RTC_ISR_ALRBWF         BIT_(1)
+#define CYGHWR_HAL_STM32_RTC_ISR_WUTWF          BIT_(2)
+#define CYGHWR_HAL_STM32_RTC_ISR_INITS          BIT_(4)
+#define CYGHWR_HAL_STM32_RTC_ISR_RSF            BIT_(5)
+#define CYGHWR_HAL_STM32_RTC_ISR_INITF          BIT_(6)
+#define CYGHWR_HAL_STM32_RTC_ISR_INIT           BIT_(7)
+#define CYGHWR_HAL_STM32_RTC_ISR_ALRAF          BIT_(8)
+#define CYGHWR_HAL_STM32_RTC_ISR_ALRBF          BIT_(9)
+#define CYGHWR_HAL_STM32_RTC_ISR_WUTF           BIT_(10)
+#define CYGHWR_HAL_STM32_RTC_ISR_TSF            BIT_(11)
+#define CYGHWR_HAL_STM32_RTC_ISR_TSOVF          BIT_(12)
+#define CYGHWR_HAL_STM32_RTC_ISR_TAMP1F         BIT_(13)
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+#define CYGHWR_HAL_STM32_RTC_PRER_PREDIV_S      MASK_(0,13)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGHWR_HAL_STM32_RTC_ISR_SHPF           BIT_(3)
+#define CYGHWR_HAL_STM32_RTC_ISR_TAMP2F         BIT_(14)
+#define CYGHWR_HAL_STM32_RTC_ISR_RECALPF        BIT_(16)
+#define CYGHWR_HAL_STM32_RTC_PRER_PREDIV_S      MASK_(0,15)
+#endif
+#define CYGHWR_HAL_STM32_RTC_PRER_PREDIV_A      MASK_(16,7)
+
+// RTC_WUTR defines omitted
+// RTC_CALIBR defines omitted
+// RTC_ALRMAR defines omitted
+// RTC_ALRMBR defines omitted
+
+#define CYGHWR_HAL_STM32_RTC_WPR_KEY            MASK_(0,8)
+#define CYGHWR_HAL_STM32_RTC_WPR_KEY1           0xCA
+#define CYGHWR_HAL_STM32_RTC_WPR_KEY2           0x53
+
+// RTC_TSTR defines omitted, but layout identical to RTC_TR
+// RTC_TSDR defines omitted, but layout identical to RTC_DR except for omission of year fields
+// RTC_TAFCR defines omitted
+// No relevant RTC_BKPxR defines.
+
+// RCC clock is selected within wallclock driver, so no define here.
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+
+//=============================================================================
+// System configuration controller - F2 and F4 only
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+// Register offsets
+#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP          0x00
+#define CYGHWR_HAL_STM32_SYSCFG_PMC             0x04
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICR1         0x08
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICR2         0x0C
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICR3         0x10
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICR4         0x14
+#define CYGHWR_HAL_STM32_SYSCFG_CMPCR           0x20
+
+// Register definitions
+
+#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_MAINFLASH VALUE_(0,0)
+#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_SYSFLASH  VALUE_(0,1)
+#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_FSMC1     VALUE_(0,2)
+#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_SRAM      VALUE_(0,3)
+
+#define CYGHWR_HAL_STM32_SYSCFG_PMC_MII          VALUE_(23,0)
+#define CYGHWR_HAL_STM32_SYSCFG_PMC_RMII         VALUE_(23,1)
+
+// FIXME: The below EXTI bits should be merged with the F1 defines in
+// var_io_pins.h to provide a common interface
+
+// The following macro allows the four EXTICR registers to be indexed
+// as CYGHWR_HAL_STM32_SYSCFG_EXTICR(1) to CYGHWR_HAL_STM32_SYSCFG_EXTICR(4)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICR(__x)      (4*((__x)-1)+0x08)
+
+// The following macros are used to generate the bitfields for setting up
+// external interrupts.  For example, CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTC(12)
+// will generate the bitfield which when ORed into the EXTICR4 register will
+// set up C12 as the external interrupt pin for the EXTI12 interrupt.
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTA(__x) VALUE_(4*((__x)&3),0)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTB(__x) VALUE_(4*((__x)&3),1)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTC(__x) VALUE_(4*((__x)&3),2)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTD(__x) VALUE_(4*((__x)&3),3)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTE(__x) VALUE_(4*((__x)&3),4)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTF(__x) VALUE_(4*((__x)&3),5)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTG(__x) VALUE_(4*((__x)&3),6)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTH(__x) VALUE_(4*((__x)&3),7)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_MASK(__x)  VALUE_(4*((__x)&3),0xF)
+
+#define CYGHWR_HAL_STM32_SYSCFG_CMPCR_CMP_DIS      VALUE_(0,0)
+#define CYGHWR_HAL_STM32_SYSCFG_CMPCR_CMP_ENA      VALUE_(0,1)
+#define CYGHWR_HAL_STM32_SYSCFG_CMPCR_READY        BIT_(8)
+
+// SYSCFG clock control
+
+#define CYGHWR_HAL_STM32_SYSCFG_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB2, SYSCFG )
+
+#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+
 //=============================================================================
 // External interrupt controller
 
@@ -299,162 +783,44 @@
 #define CYGHWR_HAL_STM32_EXTI_BIT(__b)          BIT_(__b)
 
 //=============================================================================
-// GPIO ports
-
-#define CYGHWR_HAL_STM32_GPIO_CRL               0x00
-#define CYGHWR_HAL_STM32_GPIO_CRH               0x04
-#define CYGHWR_HAL_STM32_GPIO_IDR               0x08
-#define CYGHWR_HAL_STM32_GPIO_ODR               0x0C
-#define CYGHWR_HAL_STM32_GPIO_BSRR              0x10
-#define CYGHWR_HAL_STM32_GPIO_BRR               0x14
-#define CYGHWR_HAL_STM32_GPIO_LCKR              0x18
-
-#define CYGHWR_HAL_STM32_GPIO_MODE_IN           VALUE_(0,0)     // Input mode
-#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ    VALUE_(0,1)     // Output mode, max 10MHz
-#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ     VALUE_(0,2)     // Output mode, max 2MHz
-#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ    VALUE_(0,3)     // Output mode, max 50MHz
-
-#define CYGHWR_HAL_STM32_GPIO_CNF_AIN           VALUE_(2,0)     // Analog input
-#define CYGHWR_HAL_STM32_GPIO_CNF_FIN           VALUE_(2,1)     // Floating input
-#define CYGHWR_HAL_STM32_GPIO_CNF_PULL          VALUE_(2,2)     // Input with pull up/down
-#define CYGHWR_HAL_STM32_GPIO_CNF_RESV          VALUE_(2,3)     // Reserved
-
-#define CYGHWR_HAL_STM32_GPIO_CNF_GPOPP         VALUE_(2,0)     // GP output push/pull
-#define CYGHWR_HAL_STM32_GPIO_CNF_GPOOD         VALUE_(2,1)     // GP output open drain
-#define CYGHWR_HAL_STM32_GPIO_CNF_AOPP          VALUE_(2,2)     // Alt output push/pull
-#define CYGHWR_HAL_STM32_GPIO_CNF_AOOD          VALUE_(2,3)     // Alt output open drain
-
-
-// Alternative, more readable, config names
-// Inputs
-#define CYGHWR_HAL_STM32_GPIO_CNF_ANALOG        CYGHWR_HAL_STM32_GPIO_CNF_AIN
-#define CYGHWR_HAL_STM32_GPIO_CNF_FLOATING      CYGHWR_HAL_STM32_GPIO_CNF_FIN
-#define CYGHWR_HAL_STM32_GPIO_CNF_PULLDOWN      (CYGHWR_HAL_STM32_GPIO_CNF_PULL)
-#define CYGHWR_HAL_STM32_GPIO_CNF_PULLUP        (CYGHWR_HAL_STM32_GPIO_CNF_PULL|CYGHWR_HAL_STM32_GPIO_PULLUP)
-// Outputs
-#define CYGHWR_HAL_STM32_GPIO_CNF_OUT_OPENDRAIN CYGHWR_HAL_STM32_GPIO_CNF_GPOOD
-#define CYGHWR_HAL_STM32_GPIO_CNF_OUT_PUSHPULL  CYGHWR_HAL_STM32_GPIO_CNF_GPOPP
-#define CYGHWR_HAL_STM32_GPIO_CNF_ALT_OPENDRAIN CYGHWR_HAL_STM32_GPIO_CNF_AOOD
-#define CYGHWR_HAL_STM32_GPIO_CNF_ALT_PUSHPULL  CYGHWR_HAL_STM32_GPIO_CNF_AOPP
-
-
-// This macro packs the port number, bit number, mode and
-// configuration for a GPIO pin into a single word. The packing puts
-// the mode and config in the ls 5 bits, the bit number in 16:20 and
-// the offset of the GPIO port from GPIOA in bits 8:15. The port, mode
-// and config are only specified using the last component of the names
-// to keep definitions short.
-
-#define CYGHWR_HAL_STM32_GPIO(__port, __bit, __mode, __cnf )            \
-            ((CYGHWR_HAL_STM32_GPIO##__port - CYGHWR_HAL_STM32_GPIOA) | \
-             (__bit<<16) |                                              \
-             (CYGHWR_HAL_STM32_GPIO_MODE_##__mode) |                    \
-             (CYGHWR_HAL_STM32_GPIO_CNF_##__cnf))
-
-// Macros to extract encoded values
-#define CYGHWR_HAL_STM32_GPIO_PORT(__pin)       (CYGHWR_HAL_STM32_GPIOA+((__pin)&0x0000FF00))
-#define CYGHWR_HAL_STM32_GPIO_BIT(__pin)        (((__pin)>>16)&0x1F)
-#define CYGHWR_HAL_STM32_GPIO_CFG(__pin)        ((__pin)&0xF)
-#define CYGHWR_HAL_STM32_GPIO_PULLUP            BIT_(4)
-
-
-#define CYGHWR_HAL_STM32_GPIO_NONE      (0xFFFFFFFF)
-
-// Functions and macros to configure GPIO ports.
-
-__externC void hal_stm32_gpio_set( cyg_uint32 pin );
-__externC void hal_stm32_gpio_out( cyg_uint32 pin, int val );
-__externC void hal_stm32_gpio_in ( cyg_uint32 pin, int *val );
-
-#define CYGHWR_HAL_STM32_GPIO_SET(__pin ) hal_stm32_gpio_set( __pin )
-#define CYGHWR_HAL_STM32_GPIO_OUT(__pin, __val ) hal_stm32_gpio_out( __pin, __val )
-#define CYGHWR_HAL_STM32_GPIO_IN(__pin,  __val ) hal_stm32_gpio_in( __pin, __val )
-
-//=============================================================================
-// Alternate I/O configuration registers.
-
-#define CYGHWR_HAL_STM32_AFIO_EVCR              0x00
-#define CYGHWR_HAL_STM32_AFIO_MAPR              0x04
-#define CYGHWR_HAL_STM32_AFIO_EXTICR1           0x08
-#define CYGHWR_HAL_STM32_AFIO_EXTICR2           0x0C
-#define CYGHWR_HAL_STM32_AFIO_EXTICR3           0x10
-#define CYGHWR_HAL_STM32_AFIO_EXTICR4           0x14
-
-// The following macro allows the four ETXICR registers to be indexed
-// as CYGHWR_HAL_STM32_AFIO_EXTICR(1) to CYGHWR_HAL_STM32_AFIO_EXTICR(4)
-#define CYGHWR_HAL_STM32_AFIO_EXTICR(__x)       (4*((__x)-1)+0x08)
-
-#define CYGHWR_HAL_STM32_AFIO_EVCR_PIN(__x)     VALUE_(0,(__x))
-#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTA        VALUE_(4,0) 
-#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTB        VALUE_(4,1) 
-#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTC        VALUE_(4,2) 
-#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTD        VALUE_(4,3) 
-#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTE        VALUE_(4,4)
-#define CYGHWR_HAL_STM32_AFIO_EVCR_EVOE         BIT_(7) 
-
-#define CYGHWR_HAL_STM32_AFIO_MAPR_SPI1_RMP     BIT_(0)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_I2C1_RMP     BIT_(1)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_URT1_RMP     BIT_(2)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_URT2_RMP     BIT_(3)
-
-#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_NO_RMP  VALUE_(4,0)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_P1_RMP  VALUE_(4,1)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_FL_RMP  VALUE_(4,3)
-
-#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_NO_RMP  VALUE_(6,0)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_P1_RMP  VALUE_(6,1)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_FL_RMP  VALUE_(6,3)
-
-#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_NO_RMP  VALUE_(8,0)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_P1_RMP  VALUE_(8,1)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_P2_RMP  VALUE_(8,2)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_FL_RMP  VALUE_(8,3)
-
-#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_NO_RMP  VALUE_(10,0)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_P2_RMP  VALUE_(10,2)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_FL_RMP  VALUE_(10,3)
-
-#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM4_RMP     BIT_(12)
-
-#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_NO_RMP   VALUE_(13,0)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_FL1_RMP  VALUE_(13,2)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_FL2_RMP  VALUE_(13,3)
-
-#define CYGHWR_HAL_STM32_AFIO_MAPR_PD01_RMP     BIT_(15)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM5CH4_RMP  BIT_(16)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC1EINJ_RMP BIT_(17)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC1EREG_RMP BIT_(18)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC2EINJ_RMP BIT_(19)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC2EREG_RMP BIT_(20)
-
-#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_FULL     VALUE_(24,0)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_NORST    VALUE_(24,1)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPEN   VALUE_(24,2)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPDIS  VALUE_(24,4)
-#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_MASK     VALUE_(24,7)
-
-// The following macros are used to generate the bitfields for setting up
-// external interrupts.  For example, CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTC(12)
-// will generate the bitfield which when ORed into the EXTICR4 register will
-// set up C12 as the external interrupt pin for the EXTI12 interrupt.
-#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTA(__x) VALUE_(4*((__x)&3),0)
-#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTB(__x) VALUE_(4*((__x)&3),1)
-#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTC(__x) VALUE_(4*((__x)&3),2)
-#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTD(__x) VALUE_(4*((__x)&3),3)
-#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTE(__x) VALUE_(4*((__x)&3),4)
-#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTF(__x) VALUE_(4*((__x)&3),5)
-#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTG(__x) VALUE_(4*((__x)&3),6)
-#define CYGHWR_HAL_STM32_AFIO_EXTICRX_MASK(__x)  VALUE_(4*((__x)&3),0xF)
+// GPIO ports and pin configuration. Include separate header file for this
+// to avoid this header getting unmanageable.
+#include <cyg/hal/var_io_pins.h>
 
 //=============================================================================
 // DMA controller register definitions.
 
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
 #define CYGHWR_HAL_STM32_DMA_ISR                0x00
 #define CYGHWR_HAL_STM32_DMA_IFCR               0x04
 
+#define CYGHWR_HAL_STM32_DMA_ISR_REG(__chan)    CYGHWR_HAL_STM32_DMA_ISR
+#define CYGHWR_HAL_STM32_DMA_IFCR_REG(__chan)   CYGHWR_HAL_STM32_DMA_IFCR
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_DMA_LISR               0x00
+#define CYGHWR_HAL_STM32_DMA_HISR               0x04
+#define CYGHWR_HAL_STM32_DMA_LIFCR              0x08
+#define CYGHWR_HAL_STM32_DMA_HIFCR              0x0C
+
+#define CYGHWR_HAL_STM32_DMA_ISR_REG(__stream)  ((__stream)>3 ?               \
+                                                 CYGHWR_HAL_STM32_DMA_HISR :  \
+                                                 CYGHWR_HAL_STM32_DMA_LISR)
+#define CYGHWR_HAL_STM32_DMA_IFCR_REG(__stream) ((__stream)>3 ?               \
+                                                 CYGHWR_HAL_STM32_DMA_HIFCR : \
+                                                 CYGHWR_HAL_STM32_DMA_LIFCR)
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+
 // The following macros allow access to the per-channel DMA registers, indexed
-// by channel number.  Valid channel numbers are 1 to 7 for DMA1 and 1 to 5
-// for DMA2.
+// by channel number. For F1 parts there is no concept of a stream - each entry
+// has a fixed relationship to the corresponding channel.
+// Valid channel/stream numbers are 1 to 7 for DMA1 and 1 to 5 for DMA2 on F1
+// parts, 1 to 7 for DMA2 streams on F2/F4 parts.
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGHWR_HAL_STM32_DMA_CCR(__x)           (0x14*(__x)-0x0C)
 #define CYGHWR_HAL_STM32_DMA_CNDTR(__x)         (0x14*(__x)-0x08)
 #define CYGHWR_HAL_STM32_DMA_CPAR(__x)          (0x14*(__x)-0x04)
@@ -471,6 +837,51 @@
 #define CYGHWR_HAL_STM32_DMA_IFCR_CHTIF(__x)    BIT_(4*(__x)-2)
 #define CYGHWR_HAL_STM32_DMA_IFCR_CTEIF(__x)    BIT_(4*(__x)-1)
 #define CYGHWR_HAL_STM32_DMA_IFCR_MASK(__x)     VALUE_(4*(__x)-4,0xF)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_DMA_SCR(__x)           (0x18*(__x)+0x10)
+#define CYGHWR_HAL_STM32_DMA_SNDTR(__x)         (0x18*(__x)+0x14)
+#define CYGHWR_HAL_STM32_DMA_SPAR(__x)          (0x18*(__x)+0x18)
+#define CYGHWR_HAL_STM32_DMA_SM0AR(__x)         (0x18*(__x)+0x1C)
+#define CYGHWR_HAL_STM32_DMA_SM1AR(__x)         (0x18*(__x)+0x20)
+#define CYGHWR_HAL_STM32_DMA_SFCR(__x)          (0x18*(__x)+0x24)
+
+// For now at least we implement an identity mapping between
+// streams and channels.
+#define CYGHWR_HAL_STM32_DMA_CCR(__x)           CYGHWR_HAL_STM32_DMA_SCR(__x)
+#define CYGHWR_HAL_STM32_DMA_CNDTR(__x)         CYGHWR_HAL_STM32_DMA_SNDTR(__x)
+#define CYGHWR_HAL_STM32_DMA_CPAR(__x)          CYGHWR_HAL_STM32_DMA_SPAR(__x)
+#define CYGHWR_HAL_STM32_DMA_CMAR(__x)          CYGHWR_HAL_STM32_DMA_SM0AR(__x)
+#define CYGHWR_HAL_STM32_DMA_CM0AR(__x)         CYGHWR_HAL_STM32_DMA_SM0AR(__x)
+#define CYGHWR_HAL_STM32_DMA_CM1AR(__x)         CYGHWR_HAL_STM32_DMA_SM1AR(__x)
+
+// This selects which region of an isr register to use for a stream
+#define CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x)  ( ((__x)&0x3) == 3 ? 22 : \
+                                               ((__x)&0x3) == 2 ? 16 : \
+                                               ((__x)&0x3) == 1 ? 6 : 0 )
+
+#define CYGHWR_HAL_STM32_DMA_ISR_FEIF(__x)      BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) )
+#define CYGHWR_HAL_STM32_DMA_ISR_DMEIF(__x)     BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 2 )
+#define CYGHWR_HAL_STM32_DMA_ISR_TEIF(__x)      BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 3 )
+#define CYGHWR_HAL_STM32_DMA_ISR_HTIF(__x)      BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 4 )
+#define CYGHWR_HAL_STM32_DMA_ISR_TCIF(__x)      BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 5 )
+
+#define CYGHWR_HAL_STM32_DMA_ISR_MASK(__x)      VALUE_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x), 0x3f )
+
+// This selects which region of an ifcr register to use for a stream.
+// Happens to be laid out the same as the isr, so reuse.
+#define CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x)    CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x)
+
+#define CYGHWR_HAL_STM32_DMA_IFCR_CFEIF(__x)    BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) )
+#define CYGHWR_HAL_STM32_DMA_IFCR_CDMEIF(__x)   BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 2 )
+#define CYGHWR_HAL_STM32_DMA_IFCR_CTEIF(__x)    BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 3 )
+#define CYGHWR_HAL_STM32_DMA_IFCR_CHTIF(__x)    BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 4 )
+#define CYGHWR_HAL_STM32_DMA_IFCR_CTCIF(__x)    BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 5 )
+#define CYGHWR_HAL_STM32_DMA_IFCR_MASK(__x)     VALUE_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x), 0x3f )
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 
 #define CYGHWR_HAL_STM32_DMA_CCR_EN             BIT_(0)
 #define CYGHWR_HAL_STM32_DMA_CCR_TCIE           BIT_(1)
@@ -486,126 +897,86 @@
 #define CYGHWR_HAL_STM32_DMA_CCR_MSIZE8         VALUE_(10,0)
 #define CYGHWR_HAL_STM32_DMA_CCR_MSIZE16        VALUE_(10,1)
 #define CYGHWR_HAL_STM32_DMA_CCR_MSIZE32        VALUE_(10,2)
+#define CYGHWR_HAL_STM32_DMA_CCR_PL(__x)        VALUE_(12,__x)
 #define CYGHWR_HAL_STM32_DMA_CCR_PLLOW          VALUE_(12,0)
 #define CYGHWR_HAL_STM32_DMA_CCR_PLMEDIUM       VALUE_(12,1)
 #define CYGHWR_HAL_STM32_DMA_CCR_PLHIGH         VALUE_(12,2)
 #define CYGHWR_HAL_STM32_DMA_CCR_PLMAX          VALUE_(12,3)
 #define CYGHWR_HAL_STM32_DMA_CCR_MEM2MEM        BIT_(14)
 
+// F2/F4 compatibility combinations to control transfer source/dest
+#define CYGHWR_HAL_STM32_DMA_CCR_P2MEM          0
+#define CYGHWR_HAL_STM32_DMA_CCR_MEM2P          CYGHWR_HAL_STM32_DMA_CCR_DIR
+
+// Clock enable bits
+
+#define CYGHWR_HAL_STM32_DMA1_CLOCK             CYGHWR_HAL_STM32_CLOCK( AHB, DMA1 )
+#define CYGHWR_HAL_STM32_DMA2_CLOCK             CYGHWR_HAL_STM32_CLOCK( AHB, DMA2 )
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_DMA_CCR_EN             BIT_(0)
+#define CYGHWR_HAL_STM32_DMA_CCR_DMEIE          BIT_(1)
+#define CYGHWR_HAL_STM32_DMA_CCR_TEIE           BIT_(2)
+#define CYGHWR_HAL_STM32_DMA_CCR_HTIE           BIT_(3)
+#define CYGHWR_HAL_STM32_DMA_CCR_TCIE           BIT_(4)
+#define CYGHWR_HAL_STM32_DMA_CCR_PFCTRL         BIT_(5)
+#define CYGHWR_HAL_STM32_DMA_CCR_P2MEM          VALUE_(6,0)
+#define CYGHWR_HAL_STM32_DMA_CCR_MEM2P          VALUE_(6,1)
+#define CYGHWR_HAL_STM32_DMA_CCR_MEM2MEM        VALUE_(6,2)
+
+#define CYGHWR_HAL_STM32_DMA_CCR_CIRC           BIT_(8)
+#define CYGHWR_HAL_STM32_DMA_CCR_PINC           BIT_(9)
+#define CYGHWR_HAL_STM32_DMA_CCR_MINC           BIT_(10)
+#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE8         VALUE_(11,0)
+#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE16        VALUE_(11,1)
+#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE32        VALUE_(11,2)
+#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE8         VALUE_(13,0)
+#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE16        VALUE_(13,1)
+#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE32        VALUE_(13,2)
+#define CYGHWR_HAL_STM32_DMA_CCR_PINCOS         BIT_(15)
+#define CYGHWR_HAL_STM32_DMA_CCR_PL(__x)        VALUE_(16,__x)
+#define CYGHWR_HAL_STM32_DMA_CCR_PLLOW          VALUE_(16,0)
+#define CYGHWR_HAL_STM32_DMA_CCR_PLMEDIUM       VALUE_(16,1)
+#define CYGHWR_HAL_STM32_DMA_CCR_PLHIGH         VALUE_(16,2)
+#define CYGHWR_HAL_STM32_DMA_CCR_PLMAX          VALUE_(16,3)
+#define CYGHWR_HAL_STM32_DMA_CCR_DBM            BIT_(18)
+#define CYGHWR_HAL_STM32_DMA_CCR_CT             BIT_(19)
+#define CYGHWR_HAL_STM32_DMA_CCR_PBURST1        VALUE_(21,0)
+#define CYGHWR_HAL_STM32_DMA_CCR_PBURST4        VALUE_(21,1)
+#define CYGHWR_HAL_STM32_DMA_CCR_PBURST8        VALUE_(21,2)
+#define CYGHWR_HAL_STM32_DMA_CCR_PBURST16       VALUE_(21,3)
+#define CYGHWR_HAL_STM32_DMA_CCR_MBURST1        VALUE_(23,0)
+#define CYGHWR_HAL_STM32_DMA_CCR_MBURST4        VALUE_(23,1)
+#define CYGHWR_HAL_STM32_DMA_CCR_MBURST8        VALUE_(23,2)
+#define CYGHWR_HAL_STM32_DMA_CCR_MBURST16       VALUE_(23,3)
+#define CYGHWR_HAL_STM32_DMA_CCR_CHSEL(__x)     VALUE_(25,__x)
+
+#define CYGHWR_HAL_STM32_DMA_FCR_FTH_QUARTER    VALUE_(0,0) // FIFO threshold selection
+#define CYGHWR_HAL_STM32_DMA_FCR_FTH_HALF       VALUE_(0,1)
+#define CYGHWR_HAL_STM32_DMA_FCR_FTH_3QUARTER   VALUE_(0,2)
+#define CYGHWR_HAL_STM32_DMA_FCR_FTH_FULL       VALUE_(0,3)
+#define CYGHWR_HAL_STM32_DMA_FCR_DMDIS          BIT_(2)
+#define CYGHWR_HAL_STM32_DMA_FCR_FS_LTQUARTER   VALUE_(3,0) // LT==less than
+#define CYGHWR_HAL_STM32_DMA_FCR_FS_LTHALF      VALUE_(3,1)
+#define CYGHWR_HAL_STM32_DMA_FCR_FS_LT3QUARTER  VALUE_(3,2)
+#define CYGHWR_HAL_STM32_DMA_FCR_FS_LTFULL      VALUE_(3,3)
+#define CYGHWR_HAL_STM32_DMA_FCR_FS_EMPTY       VALUE_(3,4)
+#define CYGHWR_HAL_STM32_DMA_FCR_FS_FULL        VALUE_(3,5)
+#define CYGHWR_HAL_STM32_DMA_FCR_FEIE           BIT_(7)
+
+// Clock enable bits
+
+#define CYGHWR_HAL_STM32_DMA1_CLOCK             CYGHWR_HAL_STM32_CLOCK( AHB1, DMA1 )
+#define CYGHWR_HAL_STM32_DMA2_CLOCK             CYGHWR_HAL_STM32_CLOCK( AHB1, DMA2 )
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
 //=============================================================================
 // UARTs
-
-#define CYGHWR_HAL_STM32_UART_SR                0x00
-#define CYGHWR_HAL_STM32_UART_DR                0x04
-#define CYGHWR_HAL_STM32_UART_BRR               0x08
-#define CYGHWR_HAL_STM32_UART_CR1               0x0C
-#define CYGHWR_HAL_STM32_UART_CR2               0x10
-#define CYGHWR_HAL_STM32_UART_CR3               0x14
-#define CYGHWR_HAL_STM32_UART_GTPR              0x18
-
-// SR Bits
-
-#define CYGHWR_HAL_STM32_UART_SR_PE             BIT_(0)
-#define CYGHWR_HAL_STM32_UART_SR_FE             BIT_(1)
-#define CYGHWR_HAL_STM32_UART_SR_NE             BIT_(2)
-#define CYGHWR_HAL_STM32_UART_SR_ORE            BIT_(3)
-#define CYGHWR_HAL_STM32_UART_SR_IDLE           BIT_(4)
-#define CYGHWR_HAL_STM32_UART_SR_RXNE           BIT_(5)
-#define CYGHWR_HAL_STM32_UART_SR_TC             BIT_(6)
-#define CYGHWR_HAL_STM32_UART_SR_TXE            BIT_(7)
-#define CYGHWR_HAL_STM32_UART_SR_LBD            BIT_(8)
-#define CYGHWR_HAL_STM32_UART_SR_CTS            BIT_(9)
-
-// BRR bits
-
-#define CYGHWR_HAL_STM32_UART_DR_DIVF(__f)      VALUE_(0,__f)
-#define CYGHWR_HAL_STM32_UART_DR_DIVM(__m)      VALUE_(4,__m)
-
-// CR1 bits
-
-#define CYGHWR_HAL_STM32_UART_CR1_SBK           BIT_(0)
-#define CYGHWR_HAL_STM32_UART_CR1_RWU           BIT_(1)
-#define CYGHWR_HAL_STM32_UART_CR1_RE            BIT_(2)
-#define CYGHWR_HAL_STM32_UART_CR1_TE            BIT_(3)
-#define CYGHWR_HAL_STM32_UART_CR1_IDLEIE        BIT_(4)
-#define CYGHWR_HAL_STM32_UART_CR1_RXNEIE        BIT_(5)
-#define CYGHWR_HAL_STM32_UART_CR1_TCIE          BIT_(6)
-#define CYGHWR_HAL_STM32_UART_CR1_TXEIE         BIT_(7)
-#define CYGHWR_HAL_STM32_UART_CR1_PEIE          BIT_(8)
-#define CYGHWR_HAL_STM32_UART_CR1_PS_EVEN       0
-#define CYGHWR_HAL_STM32_UART_CR1_PS_ODD        BIT_(9)
-#define CYGHWR_HAL_STM32_UART_CR1_PCE           BIT_(10)
-#define CYGHWR_HAL_STM32_UART_CR1_WAKE          BIT_(11)
-#define CYGHWR_HAL_STM32_UART_CR1_M_8           0
-#define CYGHWR_HAL_STM32_UART_CR1_M_9           BIT_(12)
-#define CYGHWR_HAL_STM32_UART_CR1_UE            BIT_(13)
-
-// CR2 bits
+// Include separate header file for this to avoid this header getting unmanageable.
 
-#define CYGHWR_HAL_STM32_UART_CR2_ADD(__a)      VALUE_(0,__a)
-#define CYGHWR_HAL_STM32_UART_CR2_LBDL          BIT_(5)
-#define CYGHWR_HAL_STM32_UART_CR2_LBDIE         BIT_(6)
-#define CYGHWR_HAL_STM32_UART_CR2_LBCL          BIT_(8)
-#define CYGHWR_HAL_STM32_UART_CR2_CPHA          BIT_(9)
-#define CYGHWR_HAL_STM32_UART_CR2_CPOL          BIT_(10)
-#define CYGHWR_HAL_STM32_UART_CR2_CLKEN         BIT_(11)
-#define CYGHWR_HAL_STM32_UART_CR2_STOP_1        VALUE_(12,0)
-#define CYGHWR_HAL_STM32_UART_CR2_STOP_0_5      VALUE_(12,1)
-#define CYGHWR_HAL_STM32_UART_CR2_STOP_2        VALUE_(12,2)
-#define CYGHWR_HAL_STM32_UART_CR2_STOP_1_5      VALUE_(12,3)
-#define CYGHWR_HAL_STM32_UART_CR2_LINEN         BIT_(14)
-
-// CR3 bits
-
-#define CYGHWR_HAL_STM32_UART_CR3_EIE           BIT_(0)
-#define CYGHWR_HAL_STM32_UART_CR3_IREN          BIT_(1)
-#define CYGHWR_HAL_STM32_UART_CR3_IRLP          BIT_(2)
-#define CYGHWR_HAL_STM32_UART_CR3_HDSEL         BIT_(3)
-#define CYGHWR_HAL_STM32_UART_CR3_NACK          BIT_(4)
-#define CYGHWR_HAL_STM32_UART_CR3_SCEN          BIT_(5)
-#define CYGHWR_HAL_STM32_UART_CR3_DMAR          BIT_(6)
-#define CYGHWR_HAL_STM32_UART_CR3_DMAT          BIT_(7)
-#define CYGHWR_HAL_STM32_UART_CR3_RTSE          BIT_(8)
-#define CYGHWR_HAL_STM32_UART_CR3_CTSE          BIT_(9)
-#define CYGHWR_HAL_STM32_UART_CR3_CTSIE         BIT_(10)
-
-// GTPR fields
-
-#define CYGHWR_HAL_STM32_UART_GTPR_PSC(__p)     VALUE_(0,__p)
-#define CYGHWR_HAL_STM32_UART_GTPR_GT(__g)      VALUE_(8,__g)
-
-// UART GPIO pins
-
-#define CYGHWR_HAL_STM32_UART1_RX               CYGHWR_HAL_STM32_GPIO( A, 10, IN        , FLOATING      )
-#define CYGHWR_HAL_STM32_UART1_TX               CYGHWR_HAL_STM32_GPIO( A,  9, OUT_50MHZ , ALT_PUSHPULL  )
-#define CYGHWR_HAL_STM32_UART1_CTS              CYGHWR_HAL_STM32_GPIO( A, 11, IN        , FLOATING      )
-#define CYGHWR_HAL_STM32_UART1_RTS              CYGHWR_HAL_STM32_GPIO( A, 12, OUT_50MHZ , OUT_PUSHPULL  )
-
-#define CYGHWR_HAL_STM32_UART2_RX               CYGHWR_HAL_STM32_GPIO( A,  3, IN        , FLOATING      )
-#define CYGHWR_HAL_STM32_UART2_TX               CYGHWR_HAL_STM32_GPIO( A,  2, OUT_50MHZ , ALT_PUSHPULL  )
-#define CYGHWR_HAL_STM32_UART2_CTS              CYGHWR_HAL_STM32_GPIO( A,  0, IN        , FLOATING      )
-#define CYGHWR_HAL_STM32_UART2_RTS              CYGHWR_HAL_STM32_GPIO( A,  1, OUT_50MHZ , OUT_PUSHPULL  )
-
-#define CYGHWR_HAL_STM32_UART3_RX               CYGHWR_HAL_STM32_GPIO( B, 11, IN        , FLOATING      )
-#define CYGHWR_HAL_STM32_UART3_TX               CYGHWR_HAL_STM32_GPIO( B, 10, OUT_50MHZ , ALT_PUSHPULL  )
-#define CYGHWR_HAL_STM32_UART3_CTS              CYGHWR_HAL_STM32_GPIO( B, 13, IN        , FLOATING      )
-#define CYGHWR_HAL_STM32_UART3_RTS              CYGHWR_HAL_STM32_GPIO( B, 14, OUT_50MHZ , OUT_PUSHPULL  )
-
-#define CYGHWR_HAL_STM32_UART4_RX               CYGHWR_HAL_STM32_GPIO( C, 11, IN        , FLOATING      )
-#define CYGHWR_HAL_STM32_UART4_TX               CYGHWR_HAL_STM32_GPIO( C, 10, OUT_50MHZ , ALT_PUSHPULL  )
-#define CYGHWR_HAL_STM32_UART4_CTS              CYGHWR_HAL_STM32_GPIO_NONE
-#define CYGHWR_HAL_STM32_UART4_RTS              CYGHWR_HAL_STM32_GPIO_NONE
-
-#define CYGHWR_HAL_STM32_UART5_RX               CYGHWR_HAL_STM32_GPIO( C,  2, IN        , FLOATING      )
-#define CYGHWR_HAL_STM32_UART5_TX               CYGHWR_HAL_STM32_GPIO( C, 12, OUT_50MHZ , ALT_PUSHPULL  )
-#define CYGHWR_HAL_STM32_UART5_CTS              CYGHWR_HAL_STM32_GPIO_NONE
-#define CYGHWR_HAL_STM32_UART5_RTS              CYGHWR_HAL_STM32_GPIO_NONE
-
-#ifndef __ASSEMBLER__
-
-__externC void hal_stm32_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud );
-
-#endif
+#include <cyg/hal/var_io_usart.h>
 
 //=============================================================================
 // ADCs
@@ -645,18 +1016,33 @@
 #define CYGHWR_HAL_STM32_ADC_CR1_DISCEN         BIT_(11)
 #define CYGHWR_HAL_STM32_ADC_CR1_JDISCEN        BIT_(12)
 #define CYGHWR_HAL_STM32_ADC_CR1_DISCNUM(__x)   VALUE_(13,(__x))
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGHWR_HAL_STM32_ADC_CR1_DUALMODE(__x)  VALUE_(16,(__x))
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
 #define CYGHWR_HAL_STM32_ADC_CR1_JAWDEN         BIT_(22)
 #define CYGHWR_HAL_STM32_ADC_CR1_AWDEN          BIT_(23)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ADC_CR1_OVRIE          BIT_(26)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE
+
+
 
 // CR2 fields
 
 #define CYGHWR_HAL_STM32_ADC_CR2_ADON           BIT_(0)
 #define CYGHWR_HAL_STM32_ADC_CR2_CONT           BIT_(1)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGHWR_HAL_STM32_ADC_CR2_CAL            BIT_(2)
 #define CYGHWR_HAL_STM32_ADC_CR2_RSTCAL         BIT_(3)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
 #define CYGHWR_HAL_STM32_ADC_CR2_DMA            BIT_(8)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ADC_CR2_DDS            BIT_(9)
+#define CYGHWR_HAL_STM32_ADC_CR2_EOCS           BIT_(10)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE
+
 #define CYGHWR_HAL_STM32_ADC_CR2_ALIGN          BIT_(11)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGHWR_HAL_STM32_ADC_CR2_JEXTSEL(__x)   VALUE_(12,(__x))
 #define CYGHWR_HAL_STM32_ADC_CR2_JEXTTRIG       BIT_(15)
 #define CYGHWR_HAL_STM32_ADC_CR2_EXTSEL(__x)    VALUE_(17,(__x))
@@ -664,9 +1050,74 @@
 #define CYGHWR_HAL_STM32_ADC_CR2_JSWSTART       BIT_(21)
 #define CYGHWR_HAL_STM32_ADC_CR2_SWSTART        BIT_(22)
 #define CYGHWR_HAL_STM32_ADC_CR2_TSVREFE        BIT_(23)
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ADC_CR2_JEXTSEL(__x)   VALUE_(16,(__x))
+#define CYGHWR_HAL_STM32_ADC_CR2_JEXTEN(__x)    VALUE_(20,(__x))
+#define CYGHWR_HAL_STM32_ADC_CR2_JSWSTART       BIT_(22)
+#define CYGHWR_HAL_STM32_ADC_CR2_EXTSEL(__x)    VALUE_(24,(__x))
+#define CYGHWR_HAL_STM32_ADC_CR2_EXTEN(__x)     VALUE_(28,(__x))
+#define CYGHWR_HAL_STM32_ADC_CR2_SWSTART        BIT_(30)
+#endif
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+// On F1 devices ADC1 and ADC3 have different external event sets for regular groups
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM1_CC1       (0)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM1_CC2       (1)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM1_CC3       (2)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM2_CC2       (3)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM3_TRGO      (4)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM4_CC4       (5)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM8_TRGO      (6) // For high- and XL-density devices
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_SWSTART        (7)
+
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM3_CC1       (0)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM2_CC3       (1)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM1_CC3       (2)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM8_CC1       (3)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM8_TRGO      (4)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM5_CC1       (5)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM5_CC3       (6)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_SWSTART        (7)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM1_CC1    (0)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM1_CC2    (1)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM1_CC3    (2)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_CC2    (3)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_CC3    (4)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_CC4    (5)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_TRGO   (6)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM3_CC1    (7)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM3_TRGO   (8)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM4_CC4    (9)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM5_CC1    (10)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM5_CC2    (11)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM5_CC3    (12)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM8_CC1    (13)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM8_TRGO   (14)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_EXTI        (15) // line 11
+
+#define CYGHWR_HAL_STM32_ADC_EXTEN_DISABLED     (0)
+#define CYGHWR_HAL_STM32_ADC_EXTEN_EDGE_RISE    (1)
+#define CYGHWR_HAL_STM32_ADC_EXTEN_EDGE_FALL    (2)
+#define CYGHWR_HAL_STM32_ADC_EXTEN_EDGE_BOTH    (3)
+
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE
 
 // SMPRx fields
 
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+// F1 : SMPR1 17..10 : SMPR2 9..0
+#define CYGHWR_HAL_STM32_ADC_SMPR1_NUM_CHANNELS (8)
+#define CYGHWR_HAL_STM32_ADC_SMPR2_NUM_CHANNELS (10)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+// F2/F4 : SMPR1 18..10 : SMPR2 9..0
+#define CYGHWR_HAL_STM32_ADC_SMPR1_NUM_CHANNELS (9)
+#define CYGHWR_HAL_STM32_ADC_SMPR2_NUM_CHANNELS (10)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE
+
 #define CYGHWR_HAL_STM32_ADC_SMPRx_SMP(__x, __y) VALUE_((__x) * 3, (__y))
 
 // SQRx fields
@@ -680,32 +1131,52 @@
 
 // ADC GPIO pins
 
-#define CYGHWR_HAL_STM32_ADC123_IN0             CYGHWR_HAL_STM32_GPIO( A, 0,  IN, ANALOG )
-#define CYGHWR_HAL_STM32_ADC123_IN1             CYGHWR_HAL_STM32_GPIO( A, 1,  IN, ANALOG )
-#define CYGHWR_HAL_STM32_ADC123_IN2             CYGHWR_HAL_STM32_GPIO( A, 2,  IN, ANALOG )
-#define CYGHWR_HAL_STM32_ADC123_IN3             CYGHWR_HAL_STM32_GPIO( A, 3,  IN, ANALOG )
+// F1/F2/F4 GPIO inputs have 16 channels (0..15).
+// ADC1 has extra internal sources, which for F1 and HIPERFORMANCE (F2/F4)
+// devices respectively have 18 (0..17) and 19 (0..18) available sources.
+
+// Internal (non-GPIO) channels (ADC1 only):
+// - ADC1_IN16 temperature      F1/F2/F4
+// - ADC1_IN17 Vrefint          F1/F2/F4
+// - ADC1_IN18 Vbat             F2/F4
 
-#define CYGHWR_HAL_STM32_ADC12_IN4              CYGHWR_HAL_STM32_GPIO( A, 4,  IN, ANALOG )
-#define CYGHWR_HAL_STM32_ADC12_IN5              CYGHWR_HAL_STM32_GPIO( A, 5,  IN, ANALOG )
-#define CYGHWR_HAL_STM32_ADC12_IN6              CYGHWR_HAL_STM32_GPIO( A, 6,  IN, ANALOG )
-#define CYGHWR_HAL_STM32_ADC12_IN7              CYGHWR_HAL_STM32_GPIO( A, 7,  IN, ANALOG )
+#define CYGHWR_HAL_STM32_ADC123_IN0             CYGHWR_HAL_STM32_PIN_ANALOG( A, 0 )
+#define CYGHWR_HAL_STM32_ADC123_IN1             CYGHWR_HAL_STM32_PIN_ANALOG( A, 1 )
+#define CYGHWR_HAL_STM32_ADC123_IN2             CYGHWR_HAL_STM32_PIN_ANALOG( A, 2 )
+#define CYGHWR_HAL_STM32_ADC123_IN3             CYGHWR_HAL_STM32_PIN_ANALOG( A, 3 )
 
-#define CYGHWR_HAL_STM32_ADC12_IN8              CYGHWR_HAL_STM32_GPIO( B, 0,  IN, ANALOG )
-#define CYGHWR_HAL_STM32_ADC12_IN9              CYGHWR_HAL_STM32_GPIO( B, 1,  IN, ANALOG )
+#define CYGHWR_HAL_STM32_ADC12_IN4              CYGHWR_HAL_STM32_PIN_ANALOG( A, 4 )
+#define CYGHWR_HAL_STM32_ADC12_IN5              CYGHWR_HAL_STM32_PIN_ANALOG( A, 5 )
+#define CYGHWR_HAL_STM32_ADC12_IN6              CYGHWR_HAL_STM32_PIN_ANALOG( A, 6 )
+#define CYGHWR_HAL_STM32_ADC12_IN7              CYGHWR_HAL_STM32_PIN_ANALOG( A, 7 )
+
+#define CYGHWR_HAL_STM32_ADC12_IN8              CYGHWR_HAL_STM32_PIN_ANALOG( B, 0 )
+#define CYGHWR_HAL_STM32_ADC12_IN9              CYGHWR_HAL_STM32_PIN_ANALOG( B, 1 )
 
-#define CYGHWR_HAL_STM32_ADC3_IN4               CYGHWR_HAL_STM32_GPIO( F, 6,  IN, ANALOG )
-#define CYGHWR_HAL_STM32_ADC3_IN5               CYGHWR_HAL_STM32_GPIO( F, 7,  IN, ANALOG )
-#define CYGHWR_HAL_STM32_ADC3_IN6               CYGHWR_HAL_STM32_GPIO( F, 8,  IN, ANALOG )
-#define CYGHWR_HAL_STM32_ADC3_IN7               CYGHWR_HAL_STM32_GPIO( F, 9,  IN, ANALOG )
-#define CYGHWR_HAL_STM32_ADC3_IN8               CYGHWR_HAL_STM32_GPIO( F, 10, IN, ANALOG )
+#define CYGHWR_HAL_STM32_ADC3_IN4               CYGHWR_HAL_STM32_PIN_ANALOG( F, 6 )
+#define CYGHWR_HAL_STM32_ADC3_IN5               CYGHWR_HAL_STM32_PIN_ANALOG( F, 7 )
+#define CYGHWR_HAL_STM32_ADC3_IN6               CYGHWR_HAL_STM32_PIN_ANALOG( F, 8 )
+#define CYGHWR_HAL_STM32_ADC3_IN7               CYGHWR_HAL_STM32_PIN_ANALOG( F, 9 )
+#define CYGHWR_HAL_STM32_ADC3_IN8               CYGHWR_HAL_STM32_PIN_ANALOG( F, 10 )
+
+#define CYGHWR_HAL_STM32_ADC123_IN10            CYGHWR_HAL_STM32_PIN_ANALOG( C, 0 )
+#define CYGHWR_HAL_STM32_ADC123_IN11            CYGHWR_HAL_STM32_PIN_ANALOG( C, 1 )
+#define CYGHWR_HAL_STM32_ADC123_IN12            CYGHWR_HAL_STM32_PIN_ANALOG( C, 2 )
+#define CYGHWR_HAL_STM32_ADC123_IN13            CYGHWR_HAL_STM32_PIN_ANALOG( C, 3 )
 
-#define CYGHWR_HAL_STM32_ADC123_IN10            CYGHWR_HAL_STM32_GPIO( C, 0,  IN, ANALOG )
-#define CYGHWR_HAL_STM32_ADC123_IN11            CYGHWR_HAL_STM32_GPIO( C, 1,  IN, ANALOG )
-#define CYGHWR_HAL_STM32_ADC123_IN12            CYGHWR_HAL_STM32_GPIO( C, 2,  IN, ANALOG )
-#define CYGHWR_HAL_STM32_ADC123_IN13            CYGHWR_HAL_STM32_GPIO( C, 3,  IN, ANALOG )
+#define CYGHWR_HAL_STM32_ADC12_IN14             CYGHWR_HAL_STM32_PIN_ANALOG( C, 4 )
+#define CYGHWR_HAL_STM32_ADC12_IN15             CYGHWR_HAL_STM32_PIN_ANALOG( C, 5)
 
-#define CYGHWR_HAL_STM32_ADC12_IN14             CYGHWR_HAL_STM32_GPIO( C, 4,  IN, ANALOG )
-#define CYGHWR_HAL_STM32_ADC12_IN15             CYGHWR_HAL_STM32_GPIO( C, 5,  IN, ANALOG )
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+// Following ADC3 channels not-mapped on F1 devices
+#define CYGHWR_HAL_STM32_ADC3_IN9        CYGHWR_HAL_STM32_GPIO_NONE
+#define CYGHWR_HAL_STM32_ADC3_IN14       CYGHWR_HAL_STM32_GPIO_NONE
+#define CYGHWR_HAL_STM32_ADC3_IN15       CYGHWR_HAL_STM32_GPIO_NONE
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ADC3_IN9        CYGHWR_HAL_STM32_PIN_ANALOG( F, 3 )
+#define CYGHWR_HAL_STM32_ADC3_IN14       CYGHWR_HAL_STM32_PIN_ANALOG( F, 4 )
+#define CYGHWR_HAL_STM32_ADC3_IN15       CYGHWR_HAL_STM32_PIN_ANALOG( F, 5 )
+#endif
 
 // ADC1 GPIO pin aliases
 
@@ -751,14 +1222,75 @@
 #define CYGHWR_HAL_STM32_ADC3_IN1               CYGHWR_HAL_STM32_ADC123_IN1
 #define CYGHWR_HAL_STM32_ADC3_IN2               CYGHWR_HAL_STM32_ADC123_IN2
 #define CYGHWR_HAL_STM32_ADC3_IN3               CYGHWR_HAL_STM32_ADC123_IN3
-// Inputs 4 - 8 are already defined
-#define CYGHWR_HAL_STM32_ADC3_IN9               CYGHWR_HAL_STM32_GPIO_NONE
+// Inputs 4 - 9 are already defined
 #define CYGHWR_HAL_STM32_ADC3_IN10              CYGHWR_HAL_STM32_ADC123_IN10
 #define CYGHWR_HAL_STM32_ADC3_IN11              CYGHWR_HAL_STM32_ADC123_IN11
 #define CYGHWR_HAL_STM32_ADC3_IN12              CYGHWR_HAL_STM32_ADC123_IN12
 #define CYGHWR_HAL_STM32_ADC3_IN13              CYGHWR_HAL_STM32_ADC123_IN13
-#define CYGHWR_HAL_STM32_ADC3_IN14              CYGHWR_HAL_STM32_GPIO_NONE
-#define CYGHWR_HAL_STM32_ADC3_IN15              CYGHWR_HAL_STM32_GPIO_NONE
+// Inputs 14 - 15 are already defined
+
+// ADC Clock control pins
+
+#define CYGHWR_HAL_STM32_ADC1_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, ADC1 )
+#define CYGHWR_HAL_STM32_ADC2_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, ADC2 )
+#define CYGHWR_HAL_STM32_ADC3_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, ADC3 )
+
+// F2/F4 only: Common configuration registers based from CYGHWR_HAL_STM32_ADC_COMMON
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ADC_CSR  0x00
+#define CYGHWR_HAL_STM32_ADC_CCR  0x04
+#define CYGHWR_HAL_STM32_ADC_CDR  0x08
+
+// CSR
+#define CYGHWR_HAL_STM32_ADC_CSR_AWD            BIT_(0)
+#define CYGHWR_HAL_STM32_ADC_CSR_EOC            BIT_(1)
+#define CYGHWR_HAL_STM32_ADC_CSR_JEOC           BIT_(2)
+#define CYGHWR_HAL_STM32_ADC_CSR_JSTRT          BIT_(3)
+#define CYGHWR_HAL_STM32_ADC_CSR_STRT           BIT_(4)
+#define CYGHWR_HAL_STM32_ADC_CSR_OVR            BIT_(5)
+
+#define CYGHWR_HAL_STM32_ADC1_CSR_AWD            CYGHWR_HAL_STM32_ADC_CSR_AWD
+#define CYGHWR_HAL_STM32_ADC1_CSR_EOC            CYGHWR_HAL_STM32_ADC_CSR_EOC
+#define CYGHWR_HAL_STM32_ADC1_CSR_JEOC           CYGHWR_HAL_STM32_ADC_CSR_JEOC
+#define CYGHWR_HAL_STM32_ADC1_CSR_JSTRT          CYGHWR_HAL_STM32_ADC_CSR_JSTRT
+#define CYGHWR_HAL_STM32_ADC1_CSR_STRT           CYGHWR_HAL_STM32_ADC_CSR_STRT
+#define CYGHWR_HAL_STM32_ADC1_CSR_OVR            CYGHWR_HAL_STM32_ADC_CSR_OVR
+
+#define CYGHWR_HAL_STM32_ADC2_CSR_AWD            (CYGHWR_HAL_STM32_ADC_CSR_AWD << 8)
+#define CYGHWR_HAL_STM32_ADC2_CSR_EOC            (CYGHWR_HAL_STM32_ADC_CSR_EOC << 8)
+#define CYGHWR_HAL_STM32_ADC2_CSR_JEOC           (CYGHWR_HAL_STM32_ADC_CSR_JEOC << 8)
+#define CYGHWR_HAL_STM32_ADC2_CSR_JSTRT          (CYGHWR_HAL_STM32_ADC_CSR_JSTRT << 8)
+#define CYGHWR_HAL_STM32_ADC2_CSR_STRT           (CYGHWR_HAL_STM32_ADC_CSR_STRT << 8)
+#define CYGHWR_HAL_STM32_ADC2_CSR_OVR            (CYGHWR_HAL_STM32_ADC_CSR_OVR << 8)
+
+#define CYGHWR_HAL_STM32_ADC3_CSR_AWD            (CYGHWR_HAL_STM32_ADC_CSR_AWD << 16)
+#define CYGHWR_HAL_STM32_ADC3_CSR_EOC            (CYGHWR_HAL_STM32_ADC_CSR_EOC << 16)
+#define CYGHWR_HAL_STM32_ADC3_CSR_JEOC           (CYGHWR_HAL_STM32_ADC_CSR_JEOC << 16)
+#define CYGHWR_HAL_STM32_ADC3_CSR_JSTRT          (CYGHWR_HAL_STM32_ADC_CSR_JSTRT << 16)
+#define CYGHWR_HAL_STM32_ADC3_CSR_STRT           (CYGHWR_HAL_STM32_ADC_CSR_STRT << 16)
+#define CYGHWR_HAL_STM32_ADC3_CSR_OVR            (CYGHWR_HAL_STM32_ADC_CSR_OVR << 16)
+
+#define CYGHWR_HAL_STM32_ADC_CSR_ADC1(__csr) ((__csr) >> 0)
+#define CYGHWR_HAL_STM32_ADC_CSR_ADC2(__csr) ((__csr) >> 8)
+#define CYGHWR_HAL_STM32_ADC_CSR_ADC3(__csr) ((__csr) >> 16)
+
+// CCR
+#define CYGHWR_HAL_STM32_ADC_CCR_MULTI_XXX     VALUE_(0,0x1F)
+#define CYGHWR_HAL_STM32_ADC_CCR_DELAY_XXX     VALUE_(8,0xF)
+#define CYGHWR_HAL_STM32_ADC_CCR_DDS           BIT_(13)
+#define CYGHWR_HAL_STM32_ADC_CCR_DMA_XXX       VALUE_(14,0x3)
+#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_2      VALUE_(16,0x0)
+#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_4      VALUE_(16,0x1)
+#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_6      VALUE_(16,0x2)
+#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_8      VALUE_(16,0x3)
+#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_XXX    VALUE_(16,0x3)
+#define CYGHWR_HAL_STM32_ADC_CCR_VBATE         BIT_(22)
+#define CYGHWR_HAL_STM32_ADC_CCR_TSVREFE       BIT_(23)
+
+// CDR
+#define CYGHWR_HAL_STM32_ADC_CDR_DATA1_XXX    VALUE_(0,0xFFFF)
+#define CYGHWR_HAL_STM32_ADC_CDR_DATA2_XXX    VALUE_(16,0xFFFF)
+#endif
 
 //=============================================================================
 // SPI interface register definitions.
@@ -825,17 +1357,105 @@
 #define CYGHWR_HAL_STM32_SPI_I2SPR_ODD          BIT_(8)
 #define CYGHWR_HAL_STM32_SPI_I2SPR_MCKOE        BIT_(9)
 
+// Clock control definitions for each SPI bus
+
+#define CYGHWR_HAL_STM32_SPI1_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, SPI1 )
+#define CYGHWR_HAL_STM32_SPI2_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, SPI2 )
+#define CYGHWR_HAL_STM32_SPI3_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, SPI3 )
+
+//=============================================================================
+// I2C busses
+
+#define CYGHWR_HAL_STM32_I2C_CR1                0x00
+#define CYGHWR_HAL_STM32_I2C_CR2                0x04
+#define CYGHWR_HAL_STM32_I2C_OAR1               0x08
+#define CYGHWR_HAL_STM32_I2C_OAR2               0x0C
+#define CYGHWR_HAL_STM32_I2C_DR                 0x10
+#define CYGHWR_HAL_STM32_I2C_SR1                0x14
+#define CYGHWR_HAL_STM32_I2C_SR2                0x18
+#define CYGHWR_HAL_STM32_I2C_CCR                0x1C
+#define CYGHWR_HAL_STM32_I2C_TRISE              0x20
+
+#define CYGHWR_HAL_STM32_I2C_CR1_PE             BIT_(0)
+#define CYGHWR_HAL_STM32_I2C_CR1_SMBUS          BIT_(1)
+#define CYGHWR_HAL_STM32_I2C_CR1_SMBTYPE        BIT_(3)
+#define CYGHWR_HAL_STM32_I2C_CR1_ENARP          BIT_(4)
+#define CYGHWR_HAL_STM32_I2C_CR1_ENPEC          BIT_(5)
+#define CYGHWR_HAL_STM32_I2C_CR1_ENGC           BIT_(6)
+#define CYGHWR_HAL_STM32_I2C_CR1_NOSTRETCH      BIT_(7)
+#define CYGHWR_HAL_STM32_I2C_CR1_START          BIT_(8)
+#define CYGHWR_HAL_STM32_I2C_CR1_STOP           BIT_(9)
+#define CYGHWR_HAL_STM32_I2C_CR1_ACK            BIT_(10)
+#define CYGHWR_HAL_STM32_I2C_CR1_POS            BIT_(11)
+#define CYGHWR_HAL_STM32_I2C_CR1_PEC            BIT_(12)
+#define CYGHWR_HAL_STM32_I2C_CR1_ALERT          BIT_(13)
+#define CYGHWR_HAL_STM32_I2C_CR1_SWRST          BIT_(15)
+
+
+#define CYGHWR_HAL_STM32_I2C_CR2_FREQ(__x)      VALUE_(0,__x)
+#define CYGHWR_HAL_STM32_I2C_CR2_FREQ_MASK      MASK_(0,6)
+#define CYGHWR_HAL_STM32_I2C_CR2_ITERREN        BIT_(8)
+#define CYGHWR_HAL_STM32_I2C_CR2_ITEVTEN        BIT_(9)
+#define CYGHWR_HAL_STM32_I2C_CR2_ITBUFEN        BIT_(10)
+#define CYGHWR_HAL_STM32_I2C_CR2_DMAEN          BIT_(11)
+#define CYGHWR_HAL_STM32_I2C_CR2_LAST           BIT_(12)
+
+// OAR1 and OAR2 omitted, we only support master mode
+
+#define CYGHWR_HAL_STM32_I2C_SR1_SB             BIT_(0)
+#define CYGHWR_HAL_STM32_I2C_SR1_ADDR           BIT_(1)
+#define CYGHWR_HAL_STM32_I2C_SR1_BTF            BIT_(2)
+#define CYGHWR_HAL_STM32_I2C_SR1_ADD10          BIT_(3)
+#define CYGHWR_HAL_STM32_I2C_SR1_STOPF          BIT_(4)
+#define CYGHWR_HAL_STM32_I2C_SR1_RxNE           BIT_(6)
+#define CYGHWR_HAL_STM32_I2C_SR1_TxE            BIT_(7)
+#define CYGHWR_HAL_STM32_I2C_SR1_BERR           BIT_(8)
+#define CYGHWR_HAL_STM32_I2C_SR1_ARLO           BIT_(9)
+#define CYGHWR_HAL_STM32_I2C_SR1_AF             BIT_(10)
+#define CYGHWR_HAL_STM32_I2C_SR1_OVR            BIT_(11)
+#define CYGHWR_HAL_STM32_I2C_SR1_PECERR         BIT_(12)
+#define CYGHWR_HAL_STM32_I2C_SR1_TIMEOUT        BIT_(14)
+#define CYGHWR_HAL_STM32_I2C_SR1_SMBALERT       BIT_(15)
+
+
+#define CYGHWR_HAL_STM32_I2C_SR2_MSL            BIT_(0)
+#define CYGHWR_HAL_STM32_I2C_SR2_BUSY           BIT_(1)
+#define CYGHWR_HAL_STM32_I2C_SR2_TRA            BIT_(2)
+#define CYGHWR_HAL_STM32_I2C_SR2_GENCALL        BIT_(4)
+#define CYGHWR_HAL_STM32_I2C_SR2_SMBDEFAULT     BIT_(5)
+#define CYGHWR_HAL_STM32_I2C_SR2_SMBHOST        BIT_(6)
+#define CYGHWR_HAL_STM32_I2C_SR2_DUALF          BIT_(7)
+#define CYGHWR_HAL_STM32_I2C_SR2_PEC            MASK_(7,8)
+
+#define CYGHWR_HAL_STM32_I2C_CCR_CCR(__x)       VALUE_(0,__x)
+#define CYGHWR_HAL_STM32_I2C_CCR_CCR_MASK       MASK_(0,12)
+#define CYGHWR_HAL_STM32_I2C_CCR_DUTY_2         0
+#define CYGHWR_HAL_STM32_I2C_CCR_DUTY_16_9      BIT_(14)
+#define CYGHWR_HAL_STM32_I2C_CCR_STD            0
+#define CYGHWR_HAL_STM32_I2C_CCR_FAST           BIT_(15)
+
+#define CYGHWR_HAL_STM32_I2C_TRISE_VAL(__x)     VALUE_(0,__x)
+#define CYGHWR_HAL_STM32_I2C_TRISE_MASK         MASK_(0,6)
+
+// Clock control definitions for each I2C bus
+
+#define CYGHWR_HAL_STM32_I2C1_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, I2C1 )
+#define CYGHWR_HAL_STM32_I2C2_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, I2C2 )
+
+
 //=============================================================================
 // USB interface register definitions.
 
-#define CYGHWR_HAL_STM32_USB_EP0R               0x00 
-#define CYGHWR_HAL_STM32_USB_EP1R               0x04 
-#define CYGHWR_HAL_STM32_USB_EP2R               0x08 
-#define CYGHWR_HAL_STM32_USB_EP3R               0x0C 
-#define CYGHWR_HAL_STM32_USB_EP4R               0x10 
-#define CYGHWR_HAL_STM32_USB_EP5R               0x14 
-#define CYGHWR_HAL_STM32_USB_EP6R               0x18 
-#define CYGHWR_HAL_STM32_USB_EP7R               0x1C 
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+#define CYGHWR_HAL_STM32_USB_EP0R               0x00
+#define CYGHWR_HAL_STM32_USB_EP1R               0x04
+#define CYGHWR_HAL_STM32_USB_EP2R               0x08
+#define CYGHWR_HAL_STM32_USB_EP3R               0x0C
+#define CYGHWR_HAL_STM32_USB_EP4R               0x10
+#define CYGHWR_HAL_STM32_USB_EP5R               0x14
+#define CYGHWR_HAL_STM32_USB_EP6R               0x18
+#define CYGHWR_HAL_STM32_USB_EP7R               0x1C
 
 #define CYGHWR_HAL_STM32_USB_CNTR               0x40
 #define CYGHWR_HAL_STM32_USB_ISTR               0x44
@@ -911,6 +1531,12 @@
 #define CYGHWR_HAL_STM32_USB_DADDR_ADD(__x)     VALUE_(0,(__x))
 #define CYGHWR_HAL_STM32_USB_DADDR_EF           BIT_(7)
 
+#define CYGHWR_HAL_STM32_USB_CLOCK              CYGHWR_HAL_STM32_CLOCK( APB1, USB )
+
+#endif // if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+// USB in F2/F4 parts is completely different. Definitions will be provided when implemented.
+
 //=============================================================================
 // Timers
 //
@@ -955,6 +1581,24 @@
 
 #define CYGHWR_HAL_STM32_TIM_EGR_UG             BIT_(0)
 
+// Clock control pins
+#define CYGHWR_HAL_STM32_TIM1_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, TIM1 )
+#define CYGHWR_HAL_STM32_TIM2_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, TIM2 )
+#define CYGHWR_HAL_STM32_TIM3_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, TIM3 )
+#define CYGHWR_HAL_STM32_TIM4_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, TIM4 )
+#define CYGHWR_HAL_STM32_TIM5_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, TIM5 )
+#define CYGHWR_HAL_STM32_TIM6_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, TIM6 )
+#define CYGHWR_HAL_STM32_TIM7_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, TIM7 )
+#define CYGHWR_HAL_STM32_TIM8_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, TIM8 )
+#if 0
+#define CYGHWR_HAL_STM32_TIM9_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, TIM9 )
+#define CYGHWR_HAL_STM32_TIM10_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB2, TIM10 )
+#define CYGHWR_HAL_STM32_TIM11_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB2, TIM11 )
+#define CYGHWR_HAL_STM32_TIM12_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB1, TIM12 )
+#define CYGHWR_HAL_STM32_TIM13_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB1, TIM13 )
+#define CYGHWR_HAL_STM32_TIM14_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB1, TIM14 )
+#endif
+
 #ifndef __ASSEMBLER__
 
 __externC cyg_uint32 hal_stm32_timer_clock( CYG_ADDRESS base );
@@ -962,6 +1606,34 @@
 #endif
 
 //=============================================================================
+// Independent Watchdog
+
+#define CYGHWR_HAL_STM32_IWDG_KR                0x00
+#define CYGHWR_HAL_STM32_IWDG_PR                0x04
+#define CYGHWR_HAL_STM32_IWDG_RLR               0x08
+#define CYGHWR_HAL_STM32_IWDG_SR                0x0C
+
+#define CYGHWR_HAL_STM32_IWDG_KR_RESET          0xAAAA
+#define CYGHWR_HAL_STM32_IWDG_KR_ACCESS         0x5555
+#define CYGHWR_HAL_STM32_IWDG_KR_START          0xCCCC
+
+#define CYGHWR_HAL_STM32_IWDG_PR_4              0
+#define CYGHWR_HAL_STM32_IWDG_PR_8              1
+#define CYGHWR_HAL_STM32_IWDG_PR_16             2
+#define CYGHWR_HAL_STM32_IWDG_PR_32             3
+#define CYGHWR_HAL_STM32_IWDG_PR_64             4
+#define CYGHWR_HAL_STM32_IWDG_PR_128            5
+#define CYGHWR_HAL_STM32_IWDG_PR_256            6
+
+#define CYGHWR_HAL_STM32_IWDG_SR_PVU            BIT_(0)
+#define CYGHWR_HAL_STM32_IWDG_SR_RVU            BIT_(1)
+
+// Clock control
+
+//#define CYGHWR_HAL_STM32_IWDG_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, IWDG )
+
+
+//=============================================================================
 // Flash controller
 
 #define CYGHWR_HAL_STM32_FLASH_ACR              0x00
@@ -969,9 +1641,13 @@
 #define CYGHWR_HAL_STM32_FLASH_OPTKEYR          0x08
 #define CYGHWR_HAL_STM32_FLASH_SR               0x0C
 #define CYGHWR_HAL_STM32_FLASH_CR               0x10
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGHWR_HAL_STM32_FLASH_AR               0x14
 #define CYGHWR_HAL_STM32_FLASH_OBR              0x1C
 #define CYGHWR_HAL_STM32_FLASH_WRPR             0x20
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_FLASH_OPTCR            0x14
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
 
 // Key values
 
@@ -981,19 +1657,47 @@
 // ACR fields
 
 #define CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(__x) VALUE_(0,__x)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
 #define CYGHWR_HAL_STM32_FLASH_ACR_HLFCYA       BIT_(3)
 #define CYGHWR_HAL_STM32_FLASH_ACR_PRFTBE       BIT_(4)
 #define CYGHWR_HAL_STM32_FLASH_ACR_PRFTBS       BIT_(5)
 
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_FLASH_ACR_PRFTEN       BIT_(8)
+#define CYGHWR_HAL_STM32_FLASH_ACR_ICEN         BIT_(9)
+#define CYGHWR_HAL_STM32_FLASH_ACR_DCEN         BIT_(10)
+#define CYGHWR_HAL_STM32_FLASH_ACR_ICRST        BIT_(11)
+#define CYGHWR_HAL_STM32_FLASH_ACR_DCRST        BIT_(12)
+
+#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
 // SR fields
 
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
 #define CYGHWR_HAL_STM32_FLASH_SR_BSY           BIT_(0)
 #define CYGHWR_HAL_STM32_FLASH_SR_PGERR         BIT_(2)
 #define CYGHWR_HAL_STM32_FLASH_SR_WRPRTERR      BIT_(4)
 #define CYGHWR_HAL_STM32_FLASH_SR_EOP           BIT_(5)
 
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_FLASH_SR_EOP           BIT_(0)
+#define CYGHWR_HAL_STM32_FLASH_SR_OPERR         BIT_(1)
+#define CYGHWR_HAL_STM32_FLASH_SR_WRPERR        BIT_(4)
+#define CYGHWR_HAL_STM32_FLASH_SR_PGAERR        BIT_(5)
+#define CYGHWR_HAL_STM32_FLASH_SR_PGPERR        BIT_(6)
+#define CYGHWR_HAL_STM32_FLASH_SR_PGSERR        BIT_(7)
+#define CYGHWR_HAL_STM32_FLASH_SR_BSY           BIT_(16)
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
 // CR fields
 
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
 #define CYGHWR_HAL_STM32_FLASH_CR_PG            BIT_(0)
 #define CYGHWR_HAL_STM32_FLASH_CR_PER           BIT_(1)
 #define CYGHWR_HAL_STM32_FLASH_CR_MER           BIT_(2)
@@ -1005,13 +1709,38 @@
 #define CYGHWR_HAL_STM32_FLASH_CR_ERRIE         BIT_(10)
 #define CYGHWR_HAL_STM32_FLASH_CR_EOPIE         BIT_(12)
 
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_FLASH_CR_PG            BIT_(0)
+#define CYGHWR_HAL_STM32_FLASH_CR_SER           BIT_(1)
+#define CYGHWR_HAL_STM32_FLASH_CR_MER           BIT_(2)
+#define CYGHWR_HAL_STM32_FLASH_CR_SNB(__x)      (((__x)&0xf) << 3)
+#define CYGHWR_HAL_STM32_FLASH_CR_SNB_MASK      MASK_(3,4)
+#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE(__x)    ( (__x) == 8 ? VALUE_(8,0) : \
+                                                  (__x) == 16 ? VALUE_(8,1) : \
+                                                  (__x) == 32 ? VALUE_(8,2) : \
+                                                  VALUE_(8,3) )
+#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_8       VALUE_(8,0)
+#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_16      VALUE_(8,1)
+#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_32      VALUE_(8,2)
+#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_64      VALUE_(8,3)
+#define CYGHWR_HAL_STM32_FLASH_CR_STRT          BIT_(16)
+#define CYGHWR_HAL_STM32_FLASH_CR_EOPIE         BIT_(24)
+#define CYGHWR_HAL_STM32_FLASH_CR_ERRIE         BIT_(25)
+#define CYGHWR_HAL_STM32_FLASH_CR_LOCK          BIT_(31)
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
 // OBR fields
-
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 #define CYGHWR_HAL_STM32_FLASH_OBR_OPTERR       BIT_(0)
 #define CYGHWR_HAL_STM32_FLASH_OBR_RDPRT        BIT_(1)
 #define CYGHWR_HAL_STM32_FLASH_OBR_WDG_SW       BIT_(2)
 #define CYGHWR_HAL_STM32_FLASH_OBR_nRST_STOP    BIT_(3)
 #define CYGHWR_HAL_STM32_FLASH_OBR_nRST_STDBY   BIT_(4)
+#endif
+
+// F2/F4 FLASH_OPTCR not defined as our flash driver doesn't use it.
 
 //=============================================================================
 // Power control
@@ -1028,13 +1757,28 @@
 #define CYGHWR_HAL_STM32_PWR_CR_PVDE            BIT_(4)
 #define CYGHWR_HAL_STM32_PWR_CR_PLS_XXX         VALUE_(5,7)
 #define CYGHWR_HAL_STM32_PWR_CR_DBP             BIT_(8)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_PWR_CR_FPDS            BIT_(9)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGHWR_HAL_STM32_PWR_CR_VOS             BIT_(14)
+#endif // (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE
 
 // CSR fields
 
 #define CYGHWR_HAL_STM32_PWR_CSR_WUF            BIT_(0)
 #define CYGHWR_HAL_STM32_PWR_CSR_SBF            BIT_(1)
 #define CYGHWR_HAL_STM32_PWR_CSR_PVDO           BIT_(2)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_PWR_CSR_BRR            BIT_(3)
+#endif
 #define CYGHWR_HAL_STM32_PWR_CSR_EWUP           BIT_(8)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_PWR_CSR_BRE            BIT_(9)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGHWR_HAL_STM32_PWR_CSR_VOSRDY         BIT_(14)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE
 
 // Functions and macros to reset the backup domain as well as
 // enable/disable backup domain write protection.
@@ -1088,14 +1832,14 @@
 #define CYGHWR_HAL_STM32_FSMC_PATT3             0x8C
 #define CYGHWR_HAL_STM32_FSMC_ECCR3             0x94
 
-#define CYGHWR_HAL_STM32_FSMC_PCR4              0xC0
-#define CYGHWR_HAL_STM32_FSMC_SR4               0xC4
-#define CYGHWR_HAL_STM32_FSMC_PMEM4             0xC8
-#define CYGHWR_HAL_STM32_FSMC_PATT4             0xCC
+#define CYGHWR_HAL_STM32_FSMC_PCR4              0xA0
+#define CYGHWR_HAL_STM32_FSMC_SR4               0xA4
+#define CYGHWR_HAL_STM32_FSMC_PMEM4             0xA8
+#define CYGHWR_HAL_STM32_FSMC_PATT4             0xAC
 
 #define CYGHWR_HAL_STM32_FSMC_PIO4              0xB0
 
-
+#define CYGHWR_HAL_STM32_FSMC_BANK1_BASE        0x60000000
 #define CYGHWR_HAL_STM32_FSMC_BANK2_BASE        0x70000000
 #define CYGHWR_HAL_STM32_FSMC_BANK3_BASE        0x80000000
 #define CYGHWR_HAL_STM32_FSMC_BANK4_BASE        0x90000000
@@ -1111,6 +1855,7 @@
 #define CYGHWR_HAL_STM32_FSMC_PCR_PWID_8        VALUE_(4,0)
 #define CYGHWR_HAL_STM32_FSMC_PCR_PWID_16       VALUE_(4,1)
 #define CYGHWR_HAL_STM32_FSMC_PCR_ECCEN         BIT_(6)
+// FIXME: I don't see where ADLOW comes from? It's not in F1, F2 or F4. -Jifl
 #define CYGHWR_HAL_STM32_FSMC_PCR_ADLOW         BIT_(8)
 #define CYGHWR_HAL_STM32_FSMC_PCR_TCLR(__x)     VALUE_(9,__x)
 #define CYGHWR_HAL_STM32_FSMC_PCR_TAR(__x)      VALUE_(13,__x)
@@ -1131,6 +1876,56 @@
 #define CYGHWR_HAL_STM32_FSMC_SR_IFEN           BIT_(5)
 #define CYGHWR_HAL_STM32_FSMC_SR_FEMPT          BIT_(6)
 
+//=============================================================================
+// CAN
+//
+
+#define CYGHWR_HAL_STM32_CAN1_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, CAN1 )
+#define CYGHWR_HAL_STM32_CAN2_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, CAN2 )
+
+
+//=============================================================================
+// Ethernet MAC
+// Include separate header file for this to avoid this header getting unmanageable.
+
+#include <cyg/hal/var_io_eth.h>
+
+//==========================================================================
+
+#if (defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103RC) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103VC) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103ZC) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103RD) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103VD) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103ZD) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103RE) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103VE) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103ZE))
+// NOTE: From ST document ES0104 (STM32F101xC/D/E and STM32F103xC/D/E)
+// errata section 2.6.9 we cannot use FSMC and I2C1 at the same time.
+// For I2C1 support we are limited to on-chip SRAM/Flash execution and
+// must ensure that FSMC is disabled.
+# if (defined(CYG_HAL_STARTUP_SRAM) || \
+      defined(CYG_HAL_STARTUP_ROM) || \
+      defined(CYG_HAL_STARTUP_JTAG))
+#  define HAL_AARDVARK_CHECK_I2C( _i2cdev_ )                                   \
+     CYG_MACRO_START                                                           \
+     if ((_i2cdev_)->i2c_bus == &hal_stm32_i2c_bus1) {                         \
+         CYGHWR_HAL_STM32_CLOCK_DISABLE( CYGHWR_HAL_STM32_CLOCK( AHB, FSMC) ); \
+     }                                                                         \
+     CYG_MACRO_END
+# else // on this CPU we cannot use I2C1 since FSMC needed for the CYG_HAL_STARTUP type
+#  define HAL_AARDVARK_CHECK_I2C( _i2cdev_ )                                  \
+     CYG_MACRO_START                                                          \
+     if ((_i2cdev_)->i2c_bus == &hal_stm32_i2c_bus1) {                        \
+         CYG_TEST_FAIL_FINISH("Invalid CYG_HAL_STARTUP for I2C1 operations"); \
+     }                                                                        \
+     CYG_MACRO_END
+# endif
+#endif
+
+//==========================================================================
+
+#endif // CYGONCE_HAL_VAR_IO_H
 //-----------------------------------------------------------------------------
 // end of var_io.h
-#endif // CYGONCE_HAL_VAR_IO_H
diff --git a/packages/hal/cortexm/stm32/var/current/include/var_io_eth.h b/packages/hal/cortexm/stm32/var/current/include/var_io_eth.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/var/current/include/var_io_eth.h
@@ -0,0 +1,490 @@
+#ifndef CYGONCE_HAL_VAR_IO_ETH_H
+#define CYGONCE_HAL_VAR_IO_ETH_H
+//=============================================================================
+//
+//      var_io_eth.h
+//
+//      Ethernet-specific variant definitions
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg, jlarmour
+// Date:        2008-07-30
+// Purpose:     STM32 variant ETH specific registers
+// Description:
+// Usage:       Do not include this header file directly. Instead:
+//              #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#ifndef CYGONCE_HAL_VAR_IO_H
+# error Do not include var_io_eth.h directly, use var_io.h
+#endif
+
+
+//=============================================================================
+// Ethernet MAC
+//
+// Connectivity devices only
+
+#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+
+#define CYGHWR_HAL_STM32_ETH_MACCR              0x0000
+#define CYGHWR_HAL_STM32_ETH_MACFFR             0x0004
+#define CYGHWR_HAL_STM32_ETH_MACHTHR            0x0008
+#define CYGHWR_HAL_STM32_ETH_MACHTLR            0x000C
+#define CYGHWR_HAL_STM32_ETH_MACMIIAR           0x0010
+#define CYGHWR_HAL_STM32_ETH_MACMIIDR           0x0014
+#define CYGHWR_HAL_STM32_ETH_MACFCR             0x0018
+#define CYGHWR_HAL_STM32_ETH_MACVLANTR          0x001C
+#define CYGHWR_HAL_STM32_ETH_MACRWUFFR          0x0028
+#define CYGHWR_HAL_STM32_ETH_MACPMTCSR          0x002C
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ETH_MACDBGR            0x0034
+#endif
+#define CYGHWR_HAL_STM32_ETH_MACSR              0x0038
+#define CYGHWR_HAL_STM32_ETH_MACIMR             0x003C
+#define CYGHWR_HAL_STM32_ETH_MACA0HR            0x0040
+#define CYGHWR_HAL_STM32_ETH_MACA0LR            0x0044
+#define CYGHWR_HAL_STM32_ETH_MACA1HR            0x0048
+#define CYGHWR_HAL_STM32_ETH_MACA1LR            0x004C
+#define CYGHWR_HAL_STM32_ETH_MACA2HR            0x0050
+#define CYGHWR_HAL_STM32_ETH_MACA2LR            0x0054
+#define CYGHWR_HAL_STM32_ETH_MACA3HR            0x0058
+#define CYGHWR_HAL_STM32_ETH_MACA3LR            0x005C
+
+#define CYGHWR_HAL_STM32_ETH_MMCCR              0x0100
+#define CYGHWR_HAL_STM32_ETH_MMCRIR             0x0104
+#define CYGHWR_HAL_STM32_ETH_MMCTIR             0x0108
+#define CYGHWR_HAL_STM32_ETH_MMCRIMR            0x010C
+#define CYGHWR_HAL_STM32_ETH_MMCTIMR            0x0110
+#define CYGHWR_HAL_STM32_ETH_MMCTGFSCCR         0x014C
+#define CYGHWR_HAL_STM32_ETH_MMCTGFMSCCR        0x0150
+#define CYGHWR_HAL_STM32_ETH_MMCTGFCR           0x0168
+#define CYGHWR_HAL_STM32_ETH_MMCRFCECR          0x0194
+#define CYGHWR_HAL_STM32_ETH_MMCRFAECR          0x0198
+#define CYGHWR_HAL_STM32_ETH_MMCRGUFCR          0x01C4
+
+#define CYGHWR_HAL_STM32_ETH_PTPTSCR            0x0700
+#define CYGHWR_HAL_STM32_ETH_PTPSSIR            0x0704
+#define CYGHWR_HAL_STM32_ETH_PTPTSHR            0x0708
+#define CYGHWR_HAL_STM32_ETH_PTPTSLR            0x070C
+#define CYGHWR_HAL_STM32_ETH_PTPTSHUR           0x0710
+#define CYGHWR_HAL_STM32_ETH_PTPTSLUR           0x0714
+#define CYGHWR_HAL_STM32_ETH_PTPTSAR            0x0718
+#define CYGHWR_HAL_STM32_ETH_PTPTTHR            0x071C
+#define CYGHWR_HAL_STM32_ETH_PTPTTLR            0x0720
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ETH_PTPTSSR            0x0728
+#endif
+
+#define CYGHWR_HAL_STM32_ETH_DMABMR             0x1000
+#define CYGHWR_HAL_STM32_ETH_DMATPDR            0x1004
+#define CYGHWR_HAL_STM32_ETH_DMARPDR            0x1008
+#define CYGHWR_HAL_STM32_ETH_DMARDLAR           0x100C
+#define CYGHWR_HAL_STM32_ETH_DMATDLAR           0x1010
+#define CYGHWR_HAL_STM32_ETH_DMASR              0x1014
+#define CYGHWR_HAL_STM32_ETH_DMAOMR             0x1018
+#define CYGHWR_HAL_STM32_ETH_DMAIER             0x101C
+#define CYGHWR_HAL_STM32_ETH_DMAMFBOCR          0x1020
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ETH_DMARSWTR           0x1024
+#endif
+#define CYGHWR_HAL_STM32_ETH_DMACHTDR           0x1048
+#define CYGHWR_HAL_STM32_ETH_DMACHRDR           0x104C
+#define CYGHWR_HAL_STM32_ETH_DMACHTBAR          0x1050
+#define CYGHWR_HAL_STM32_ETH_DMACHRBAR          0x1054
+
+// MACCR
+
+#define CYGHWR_HAL_STM32_ETH_MACCR_RE           BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_MACCR_TE           BIT_(3)
+#define CYGHWR_HAL_STM32_ETH_MACCR_DC           BIT_(4)
+#define CYGHWR_HAL_STM32_ETH_MACCR_BL(__x)      VALUE_(6, __x)
+#define CYGHWR_HAL_STM32_ETH_MACCR_APCS         BIT_(7)
+#define CYGHWR_HAL_STM32_ETH_MACCR_RD           BIT_(9)
+#define CYGHWR_HAL_STM32_ETH_MACCR_IPCO         BIT_(10)
+#define CYGHWR_HAL_STM32_ETH_MACCR_DM           BIT_(11)
+#define CYGHWR_HAL_STM32_ETH_MACCR_LM           BIT_(12)
+#define CYGHWR_HAL_STM32_ETH_MACCR_ROD          BIT_(13)
+#define CYGHWR_HAL_STM32_ETH_MACCR_FES          BIT_(14)
+#define CYGHWR_HAL_STM32_ETH_MACCR_CSD          BIT_(16)
+#define CYGHWR_HAL_STM32_ETH_MACCR_IFG(__x)     VALUE_(17, (96-(__x))/8 )
+#define CYGHWR_HAL_STM32_ETH_MACCR_JD           BIT_(22)
+#define CYGHWR_HAL_STM32_ETH_MACCR_WD           BIT_(23)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ETH_MACCR_CSTF         BIT_(25)
+#endif
+
+// MACFFR
+
+#define CYGHWR_HAL_STM32_ETH_MACFFR_PM          BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_HU          BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_HM          BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_DAIF        BIT_(3)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_PAM         BIT_(4)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_BFD         BIT_(5)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_BLOCK   VALUE_(6,0)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_NOPAUSE VALUE_(6,1)
+#endif
+#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_ALL     VALUE_(6,2)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_FILTER  VALUE_(6,3)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_SAIF        BIT_(8)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_SAF         BIT_(9)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_HPF         BIT_(10)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_RA          BIT_(31)
+
+// MACHT* omitted
+
+// MACMIIAR
+
+#define CYGHWR_HAL_STM32_ETH_MACMIIAR_MB        BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_MACMIIAR_MW        BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(__x)   VALUE_(2,__x)
+#define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MASK   MASK_(2,4)
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ_CHECK(_mhz) ((_mhz) >= 20 && (_mhz) <= 72)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ_CHECK(_mhz) ((_mhz) >= 20 && (_mhz) <= 120)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ_CHECK(_mhz) ((_mhz) >= 20 && (_mhz) <= 168)
+#endif
+// This macro is shared between F1/F2/F4 families for now (despite
+// irrelevance for >72Mhz speed, but that's checked above) but it's
+// foreseeable that this could change for future products.
+# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ(_mhz)  (          \
+  ((_mhz) >= 150) ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(4) :       \
+  ((_mhz) >= 100) ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(1) :       \
+  ((_mhz) >= 60)  ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(0) :       \
+  ((_mhz) >= 35)  ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(3) :       \
+  /*((_mhz) >= 20)  ?*/ CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(2))
+
+#define CYGHWR_HAL_STM32_ETH_MACMIIAR_MR(__x)   VALUE_(6,__x)
+#define CYGHWR_HAL_STM32_ETH_MACMIIAR_PA(__x)   VALUE_(11,__x)
+
+// MACFCR omitted
+// MACVLANTR omitted
+// MACRWUFFR omitted
+// MACPMTCSR omitted
+// MACDBGR (F2/F4 only) omitted
+
+// MACSR
+
+#define CYGHWR_HAL_STM32_ETH_MACSR_PMTS         BIT_(3)
+#define CYGHWR_HAL_STM32_ETH_MACSR_MMCS         BIT_(4)
+#define CYGHWR_HAL_STM32_ETH_MACSR_MMCRS        BIT_(5)
+#define CYGHWR_HAL_STM32_ETH_MACSR_MMCTS        BIT_(6)
+#define CYGHWR_HAL_STM32_ETH_MACSR_TSTS         BIT_(9)
+
+// MACIMR
+
+#define CYGHWR_HAL_STM32_ETH_MACIMR_PMTIM       BIT_(3)
+#define CYGHWR_HAL_STM32_ETH_MACIMR_TSTIM       BIT_(9)
+
+// MMCR
+
+#define CYGHWR_HAL_STM32_ETH_MMCCR_CR           BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_MMCCR_CSR          BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_MMCCR_ROR          BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_MMCCR_MCF          BIT_(3)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ETH_MMCCR_MCP          BIT_(4)
+#define CYGHWR_HAL_STM32_ETH_MMCCR_MCFHP        BIT_(5)
+#endif
+
+// MMCRIR & MMCRIMR
+
+#define CYGHWR_HAL_STM32_ETH_MMCRIR_RFCES       BIT_(5)
+#define CYGHWR_HAL_STM32_ETH_MMCRIR_RFAES       BIT_(6)
+#define CYGHWR_HAL_STM32_ETH_MMCRIR_RGUFS       BIT_(17)
+
+// MMCTIR & MMCTIMR
+
+#define CYGHWR_HAL_STM32_ETH_MMCTIR_TGFSCS      BIT_(14)
+#define CYGHWR_HAL_STM32_ETH_MMCTIR_TGFMSCS     BIT_(15)
+#define CYGHWR_HAL_STM32_ETH_MMCTIR_TGFS        BIT_(21)
+
+// PTP* omitted
+
+// DMABMR
+
+#define CYGHWR_HAL_STM32_ETH_DMABMR_SR          BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_DA          BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_DSL(__x)    VALUE_(2,__x)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_PBL(__x)    VALUE_(8,__x)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_RTPR(__x)   VALUE_(14,(__x)-1)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_FB          BIT_(16)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_RDP(__x)    VALUE_(17,__x)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_USP         BIT_(23)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_FPM         BIT_(24)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_AAB         BIT_(25)
+
+//DMASR
+
+#define CYGHWR_HAL_STM32_ETH_DMASR_TS           BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_DMASR_TPSS         BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_DMASR_TBUS         BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_DMASR_TJTS         BIT_(3)
+#define CYGHWR_HAL_STM32_ETH_DMASR_ROS          BIT_(4)
+#define CYGHWR_HAL_STM32_ETH_DMASR_TUS          BIT_(5)
+#define CYGHWR_HAL_STM32_ETH_DMASR_RS           BIT_(6)
+#define CYGHWR_HAL_STM32_ETH_DMASR_RBUS         BIT_(7)
+#define CYGHWR_HAL_STM32_ETH_DMASR_RPSS         BIT_(8)
+#define CYGHWR_HAL_STM32_ETH_DMASR_RWTS         BIT_(9)
+#define CYGHWR_HAL_STM32_ETH_DMASR_ETS          BIT_(10)
+#define CYGHWR_HAL_STM32_ETH_DMASR_FBES         BIT_(13)
+#define CYGHWR_HAL_STM32_ETH_DMASR_ERS          BIT_(14)
+#define CYGHWR_HAL_STM32_ETH_DMASR_AIS          BIT_(15)
+#define CYGHWR_HAL_STM32_ETH_DMASR_NIS          BIT_(16)
+#define CYGHWR_HAL_STM32_ETH_DMASR_RPS          MASK_(17,3)
+#define CYGHWR_HAL_STM32_ETH_DMASR_TPS          MASK_(20,3)
+#define CYGHWR_HAL_STM32_ETH_DMASR_EBS          MASK_(23,3)
+#define CYGHWR_HAL_STM32_ETH_DMASR_MMCS         BIT_(27)
+#define CYGHWR_HAL_STM32_ETH_DMASR_PMTS         BIT_(28)
+#define CYGHWR_HAL_STM32_ETH_DMASR_TSTS         BIT_(29)
+
+// DMAOMR
+
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_SR          BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_OSF         BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_RTC(__x)    VALUE_(3,__x)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_FUGF        BIT_(6)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_FEF         BIT_(7)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_ST          BIT_(13)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_TTC(__x)    VALUE_(14,__x)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_FTF         BIT_(20)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_TSF         BIT_(21)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_DFRF        BIT_(24)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_RSF         BIT_(25)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_DTCEFD      BIT_(26)
+
+// DMAIER
+
+#define CYGHWR_HAL_STM32_ETH_DMAIER_TIE         BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_TPSIE       BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_TBUIE       BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_TJTIE       BIT_(3)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_ROIE        BIT_(4)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_TUIE        BIT_(5)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_RIE         BIT_(6)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_RBUIE       BIT_(7)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_RPSIE       BIT_(8)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_RWTIE       BIT_(9)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_ETIE        BIT_(10)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_FBEIE       BIT_(13)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_ERIE        BIT_(14)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_AISE        BIT_(15)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_NISE        BIT_(16)
+
+// DMAFBOCR omitted
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ETH_DMARSWTR_RSWTC_MASK   MASK_(0,8)
+#define CYGHWR_HAL_STM32_ETH_DMARSWTR_RSWTC(__x)   ((__x)& CYGHWR_HAL_STM32_ETH_DMARSWTR_RSWTC_MASK)
+#endif
+
+// Transmit descriptor fields
+
+/*
+-----------------------------------------------------------------------
+TDES0|OWN(31)|CTRL[30:26]|Res[25:24]|CTRL[23:20]|Res[19:17]|Stat[16:0]|
+-----------------------------------------------------------------------
+TDES1|Res[31:29]| Buffer2 Len[28:16] | Res[15:13] | Buffer1 Len[12:0] |
+-----------------------------------------------------------------------
+TDES2|               Buffer1 Address [31:0]                           |
+-----------------------------------------------------------------------
+TDES3|               Buffer2 Address [31:0]                           |
+-----------------------------------------------------------------------
+*/
+
+// TDES0 register: DMA Tx descriptor status
+
+#define CYGHWR_HAL_STM32_ETH_TDES0_DB           BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_TDES0_UF           BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_TDES0_ED           BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_TDES0_CC           MASK_(3,4)
+#define CYGHWR_HAL_STM32_ETH_TDES0_VF           BIT_(7)
+#define CYGHWR_HAL_STM32_ETH_TDES0_EC           BIT_(8)
+#define CYGHWR_HAL_STM32_ETH_TDES0_LCO          BIT_(9)
+#define CYGHWR_HAL_STM32_ETH_TDES0_NC           BIT_(10)
+#define CYGHWR_HAL_STM32_ETH_TDES0_LCA          BIT_(11)
+#define CYGHWR_HAL_STM32_ETH_TDES0_IPE          BIT_(12)
+#define CYGHWR_HAL_STM32_ETH_TDES0_FF           BIT_(13)
+#define CYGHWR_HAL_STM32_ETH_TDES0_JT           BIT_(14)
+#define CYGHWR_HAL_STM32_ETH_TDES0_ES           BIT_(15)
+#define CYGHWR_HAL_STM32_ETH_TDES0_IHE          BIT_(16)
+#define CYGHWR_HAL_STM32_ETH_TDES0_TTSS         BIT_(17)
+#define CYGHWR_HAL_STM32_ETH_TDES0_TCH          BIT_(20)
+#define CYGHWR_HAL_STM32_ETH_TDES0_TER          BIT_(21)
+#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_DISA     VALUE_(22,0)
+#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_H        VALUE_(22,1)
+#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_HP       VALUE_(22,2)
+#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_HPP      VALUE_(22,3)
+#define CYGHWR_HAL_STM32_ETH_TDES0_TTSE         BIT_(25)
+#define CYGHWR_HAL_STM32_ETH_TDES0_DP           BIT_(26)
+#define CYGHWR_HAL_STM32_ETH_TDES0_DC           BIT_(27)
+#define CYGHWR_HAL_STM32_ETH_TDES0_FS           BIT_(28)
+#define CYGHWR_HAL_STM32_ETH_TDES0_LS           BIT_(29)
+#define CYGHWR_HAL_STM32_ETH_TDES0_IC           BIT_(30)
+#define CYGHWR_HAL_STM32_ETH_TDES0_OWN          BIT_(31)
+
+#define CYGHWR_HAL_STM32_ETH_TDES1_TBS1(__x)    (VALUE_(0,__x)&0x00001FFF)
+#define CYGHWR_HAL_STM32_ETH_TDES1_TBS2(__x)    (VALUE_(16,__x)&0x1FFF0000)
+
+// Receive descriptor fields
+
+/*
+-----------------------------------------------------------------------
+RDES0| OWN(31) |                Status [30:0]                         |
+-----------------------------------------------------------------------
+RDES1|DIC(31)|Res[30:29]|Not Used|CTRL[15:14]|Res(13)|Buffer Len[12:0]|
+-----------------------------------------------------------------------
+RDES2|                Buffer1 Address [31:0]                          |
+-----------------------------------------------------------------------
+RDES3|                      Not Used                                  |
+-----------------------------------------------------------------------
+*/
+
+// RDES0 register: DMA Rx descriptor status
+
+#define CYGHWR_HAL_STM32_ETH_RDES0_PCE          BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_RDES0_CE           BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_RDES0_DE           BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_RDES0_RE           BIT_(3)
+#define CYGHWR_HAL_STM32_ETH_RDES0_RWT          BIT_(4)
+#define CYGHWR_HAL_STM32_ETH_RDES0_FT           BIT_(5)
+#define CYGHWR_HAL_STM32_ETH_RDES0_LCO          BIT_(6)
+#define CYGHWR_HAL_STM32_ETH_RDES0_IPHCE        BIT_(7)
+#define CYGHWR_HAL_STM32_ETH_RDES0_LS           BIT_(8)
+#define CYGHWR_HAL_STM32_ETH_RDES0_FS           BIT_(9)
+#define CYGHWR_HAL_STM32_ETH_RDES0_VLAN         BIT_(10)
+#define CYGHWR_HAL_STM32_ETH_RDES0_OE           BIT_(11)
+#define CYGHWR_HAL_STM32_ETH_RDES0_LE           BIT_(12)
+#define CYGHWR_HAL_STM32_ETH_RDES0_SAF          BIT_(13)
+#define CYGHWR_HAL_STM32_ETH_RDES0_DESCE        BIT_(14)
+#define CYGHWR_HAL_STM32_ETH_RDES0_ES           BIT_(15)
+#define CYGHWR_HAL_STM32_ETH_RDES0_FL(__x)      (((__x)>>16)&0x3FFF)
+#define CYGHWR_HAL_STM32_ETH_RDES0_AFM          BIT_(30)
+#define CYGHWR_HAL_STM32_ETH_RDES0_OWN          BIT_(31)
+
+// RDES1 register : DMA Rx descriptor control and buffer length
+
+#define CYGHWR_HAL_STM32_ETH_RDES1_RBS1(__x)    VALUE_(0,__x)
+#define CYGHWR_HAL_STM32_ETH_RDES1_RCH          BIT_(14)
+#define CYGHWR_HAL_STM32_ETH_RDES1_RER          BIT_(15)
+#define CYGHWR_HAL_STM32_ETH_RDES1_RBS2(__x)    VALUE_(16,__x)
+
+
+// GPIO pins
+
+// NOTE: The platform specific (re-)mapping of pins is provided in the relevant
+// target specific "plf_io.h" header file. These definitions just cover the
+// fixed mappings.
+
+// MCO1 clock to PHY
+#define CYGHWR_HAL_STM32_ETH_MCO                CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  8,  0, PUSHPULL,  NONE,     AT_LEAST(50) )
+
+// MII interface
+#define CYGHWR_HAL_STM32_ETH_MII_MDC            CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C,  1, 11, PUSHPULL,  NONE,     AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_TXD2           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C,  2, 11, PUSHPULL,  NONE,     AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_MDIO           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  2, 11, PUSHPULL,  NONE,     AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_TX_CLK         CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C,  3, 11, OPENDRAIN, FLOATING )
+#define CYGHWR_HAL_STM32_ETH_MII_RX_CLK         CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A,  1, 11, OPENDRAIN, FLOATING )
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+// MII interface
+#define CYGHWR_HAL_STM32_ETH_MII_TX_CRS         CYGHWR_HAL_STM32_PIN_IN( A,  0, FLOATING )
+#define CYGHWR_HAL_STM32_ETH_MII_COL            CYGHWR_HAL_STM32_PIN_IN( A,  3, FLOATING )
+#define CYGHWR_HAL_STM32_ETH_MII_RX_ER          CYGHWR_HAL_STM32_PIN_IN( B, 10, FLOATING )
+
+#define CYGHWR_HAL_STM32_ETH_MII_TX_EN          CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 11, 11, PUSHPULL, NONE, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_TXD0           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 12, 11, PUSHPULL, NONE, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_TXD1           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 13, 11, PUSHPULL, NONE, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_PPS_OUT        CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  5, 11, PUSHPULL, NONE, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_TXD3           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  8, 11, PUSHPULL, NONE, AT_LEAST(50) )
+
+// RMII interface
+#define CYGHWR_HAL_STM32_ETH_RMII_MDC           CYGHWR_HAL_STM32_ETH_MII_MDC
+#define CYGHWR_HAL_STM32_ETH_RMII_REF_CLK       CYGHWR_HAL_STM32_ETH_MII_RX_CLK
+#define CYGHWR_HAL_STM32_ETH_RMII_MDIO          CYGHWR_HAL_STM32_ETH_MII_MDIO
+#define CYGHWR_HAL_STM32_ETH_RMII_TX_EN         CYGHWR_HAL_STM32_ETH_MII_TX_EN
+#define CYGHWR_HAL_STM32_ETH_RMII_TXD0          CYGHWR_HAL_STM32_ETH_MII_TXD0
+#define CYGHWR_HAL_STM32_ETH_RMII_TXD1          CYGHWR_HAL_STM32_ETH_MII_TXD1
+#define CYGHWR_HAL_STM32_ETH_RMII_PPS_OUT       CYGHWR_HAL_STM32_ETH_MII_PPS_OUT
+
+// Clock controls
+
+#define CYGHWR_HAL_STM32_ETH_MAC_CLOCK          CYGHWR_HAL_STM32_CLOCK( AHB, ETHMAC )
+#define CYGHWR_HAL_STM32_ETH_TX_CLOCK           CYGHWR_HAL_STM32_CLOCK( AHB, ETHMACTX )
+#define CYGHWR_HAL_STM32_ETH_RX_CLOCK           CYGHWR_HAL_STM32_CLOCK( AHB, ETHMACRX )
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+// MII interface
+#define CYGHWR_HAL_STM32_ETH_MII_RX_DV          CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A,  7, 11, OPENDRAIN, NONE )
+#define CYGHWR_HAL_STM32_ETH_MII_RXD0           CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C,  4, 11, OPENDRAIN, NONE )
+#define CYGHWR_HAL_STM32_ETH_MII_RXD1           CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C,  5, 11, OPENDRAIN, NONE )
+
+// RMII interface
+#define CYGHWR_HAL_STM32_ETH_RMII_MDC           CYGHWR_HAL_STM32_ETH_MII_MDC
+#define CYGHWR_HAL_STM32_ETH_RMII_REF_CLK       CYGHWR_HAL_STM32_ETH_MII_RX_CLK
+#define CYGHWR_HAL_STM32_ETH_RMII_MDIO          CYGHWR_HAL_STM32_ETH_MII_MDIO
+#define CYGHWR_HAL_STM32_ETH_RMII_CRS_DV        CYGHWR_HAL_STM32_ETH_MII_RX_DV
+#define CYGHWR_HAL_STM32_ETH_RMII_RXD0          CYGHWR_HAL_STM32_ETH_MII_RXD0
+#define CYGHWR_HAL_STM32_ETH_RMII_RXD1          CYGHWR_HAL_STM32_ETH_MII_RXD1
+#define CYGHWR_HAL_STM32_ETH_RMII_TX_EN         CYGHWR_HAL_STM32_ETH_MII_TX_EN
+#define CYGHWR_HAL_STM32_ETH_RMII_TXD0          CYGHWR_HAL_STM32_ETH_MII_TXD0
+#define CYGHWR_HAL_STM32_ETH_RMII_TXD1          CYGHWR_HAL_STM32_ETH_MII_TXD1
+#define CYGHWR_HAL_STM32_ETH_RMII_PPS_OUT       CYGHWR_HAL_STM32_ETH_MII_PPS_OUT
+
+// Clock controls
+
+#define CYGHWR_HAL_STM32_ETH_MAC_CLOCK          CYGHWR_HAL_STM32_CLOCK( AHB1, ETHMAC )
+#define CYGHWR_HAL_STM32_ETH_TX_CLOCK           CYGHWR_HAL_STM32_CLOCK( AHB1, ETHMACTX )
+#define CYGHWR_HAL_STM32_ETH_RX_CLOCK           CYGHWR_HAL_STM32_CLOCK( AHB1, ETHMACRX )
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#endif // CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+
+#endif // CYGONCE_HAL_VAR_IO_ETH_H
+//-----------------------------------------------------------------------------
+// end of var_io_eth.h
diff --git a/packages/hal/cortexm/stm32/var/current/include/var_io_pins.h b/packages/hal/cortexm/stm32/var/current/include/var_io_pins.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/var/current/include/var_io_pins.h
@@ -0,0 +1,502 @@
+#ifndef CYGONCE_HAL_VAR_IO_PINS_H
+#define CYGONCE_HAL_VAR_IO_PINS_H
+//=============================================================================
+//
+//      var_io_pins.h
+//
+//      Pin configuration and GPIO definitions
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg, jlarmour
+// Date:        2011-11-29
+// Purpose:     STM32 variant GPIO and pin configuration specific registers
+// Description: 
+// Usage:       Do not include this header file directly. Instead:
+//              #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#ifndef CYGONCE_HAL_VAR_IO_H
+# error Do not include var_io_pins.h directly, use var_io.h
+#endif
+
+//=============================================================================
+// GPIO ports - common manifests
+
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_NA (0) // Convenience define for ease of pin definitions (for F1 actually marks MODE as INPUT)
+
+//=============================================================================
+// GPIO ports - F1 family
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_GPIO_CRL               0x00
+#define CYGHWR_HAL_STM32_GPIO_CRH               0x04
+#define CYGHWR_HAL_STM32_GPIO_IDR               0x08
+#define CYGHWR_HAL_STM32_GPIO_ODR               0x0C
+#define CYGHWR_HAL_STM32_GPIO_BSRR              0x10
+#define CYGHWR_HAL_STM32_GPIO_BRR               0x14
+#define CYGHWR_HAL_STM32_GPIO_LCKR              0x18
+
+#define CYGHWR_HAL_STM32_GPIO_MODE_IN           VALUE_(0,0)     // Input mode
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ    VALUE_(0,1)     // Output mode, max 10MHz
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ     VALUE_(0,2)     // Output mode, max 2MHz
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ    VALUE_(0,3)     // Output mode, max 50MHz
+
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_LOW (CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ)
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_MED (CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ)
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_FAST (CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ)
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_HIGH (CYGHWR_HAL_STM32_GPIO_MODE_OUT_FAST) // F1 limited to 50MHz
+
+// The following allows compatible specification of speed with other parts
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_AT_LEAST(__mhz)  ( ((__mhz) <= 2) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ :   \
+                                                        ((__mhz) <= 10) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ : \
+                                                        ((__mhz) <= 50) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ : \
+                                                          CYGHWR_HAL_STM32_GPIO_MODE_OUT_HIGH )
+
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_AT_MOST(__mhz)  ( ((__mhz) < 10) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ :   \
+                                                       ((__mhz) < 50) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ :  \
+                                                       ((__mhz) < 100) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ : \
+                                                         CYGHWR_HAL_STM32_GPIO_MODE_OUT_HIGH )
+
+#define CYGHWR_HAL_STM32_GPIO_CNF_AIN           VALUE_(2,0)     // Analog input
+#define CYGHWR_HAL_STM32_GPIO_CNF_FIN           VALUE_(2,1)     // Floating input
+#define CYGHWR_HAL_STM32_GPIO_CNF_PULL          VALUE_(2,2)     // Input with pull up/down
+#define CYGHWR_HAL_STM32_GPIO_CNF_RESV          VALUE_(2,3)     // Reserved
+
+#define CYGHWR_HAL_STM32_GPIO_CNF_GPOPP         VALUE_(2,0)     // GP output push/pull
+#define CYGHWR_HAL_STM32_GPIO_CNF_GPOOD         VALUE_(2,1)     // GP output open drain
+#define CYGHWR_HAL_STM32_GPIO_CNF_AOPP          VALUE_(2,2)     // Alt output push/pull
+#define CYGHWR_HAL_STM32_GPIO_CNF_AOOD          VALUE_(2,3)     // Alt output open drain
+
+
+// Alternative, more readable, config names
+// Inputs
+#define CYGHWR_HAL_STM32_GPIO_CNF_ANALOG        CYGHWR_HAL_STM32_GPIO_CNF_AIN
+#define CYGHWR_HAL_STM32_GPIO_CNF_FLOATING      CYGHWR_HAL_STM32_GPIO_CNF_FIN
+#define CYGHWR_HAL_STM32_GPIO_CNF_PULLDOWN      (CYGHWR_HAL_STM32_GPIO_CNF_PULL)
+#define CYGHWR_HAL_STM32_GPIO_CNF_PULLUP        (CYGHWR_HAL_STM32_GPIO_CNF_PULL|CYGHWR_HAL_STM32_GPIO_PULLUP)
+// Outputs
+#define CYGHWR_HAL_STM32_GPIO_CNF_OUT_OPENDRAIN CYGHWR_HAL_STM32_GPIO_CNF_GPOOD
+#define CYGHWR_HAL_STM32_GPIO_CNF_OUT_PUSHPULL  CYGHWR_HAL_STM32_GPIO_CNF_GPOPP
+#define CYGHWR_HAL_STM32_GPIO_CNF_ALT_OPENDRAIN CYGHWR_HAL_STM32_GPIO_CNF_AOOD
+#define CYGHWR_HAL_STM32_GPIO_CNF_ALT_PUSHPULL  CYGHWR_HAL_STM32_GPIO_CNF_AOPP
+
+
+// This macro packs the port number, bit number, mode and
+// configuration for a GPIO pin into a single word. The packing puts
+// the mode and config in the ls 5 bits, the bit number in 16:20 and
+// the offset of the GPIO port from GPIOA in bits 8:15. The port, mode
+// and config are only specified using the last component of the names
+// to keep definitions short.
+
+#define CYGHWR_HAL_STM32_GPIO(__port, __bit, __mode, __cnf )            \
+            ((CYGHWR_HAL_STM32_GPIO##__port - CYGHWR_HAL_STM32_GPIOA) | \
+             (__bit<<16) |                                              \
+             (CYGHWR_HAL_STM32_GPIO_MODE_##__mode) |                    \
+             (CYGHWR_HAL_STM32_GPIO_CNF_##__cnf))
+
+// We treat the CNF and MODE fields as a single field to simplify the hardware register access. The CNFMODE fields are split across
+// two registers (CRL/CRH) so the passed __pin needs to be in the range 0..7
+#define CYGHWR_HAL_STM32_GPIO_CNFMODE_VAL(__pin, __cnfmode) ((__cnfmode) << ((__pin)<<2))
+#define CYGHWR_HAL_STM32_GPIO_CNFMODE_SET(__pin, __cnfmode, __reg) ((__reg) &= ~MASK_((__pin<<2),4), \
+                                                              (__reg) |= CYGHWR_HAL_STM32_GPIO_CNFMODE_VAL(__pin, __cnfmode))
+
+// Macros to extract encoded values
+#define CYGHWR_HAL_STM32_GPIO_PORT(__pin)       (CYGHWR_HAL_STM32_GPIOA+((__pin)&0x0000FF00))
+#define CYGHWR_HAL_STM32_GPIO_BIT(__pin)        (((__pin)>>16)&0x1F)
+#define CYGHWR_HAL_STM32_GPIO_CFG(__pin)        ((__pin)&0xF)
+#define CYGHWR_HAL_STM32_GPIO_PULLUP            BIT_(4)
+
+//=============================================================================
+// Alternate I/O configuration registers.
+
+#define CYGHWR_HAL_STM32_AFIO_EVCR              0x00
+#define CYGHWR_HAL_STM32_AFIO_MAPR              0x04
+#define CYGHWR_HAL_STM32_AFIO_EXTICR1           0x08
+#define CYGHWR_HAL_STM32_AFIO_EXTICR2           0x0C
+#define CYGHWR_HAL_STM32_AFIO_EXTICR3           0x10
+#define CYGHWR_HAL_STM32_AFIO_EXTICR4           0x14
+
+// The following macro allows the four EXTICR registers to be indexed
+// as CYGHWR_HAL_STM32_AFIO_EXTICR(1) to CYGHWR_HAL_STM32_AFIO_EXTICR(4)
+#define CYGHWR_HAL_STM32_AFIO_EXTICR(__x)       (4*((__x)-1)+0x08)
+
+#define CYGHWR_HAL_STM32_AFIO_EVCR_PIN(__x)     VALUE_(0,(__x))
+#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTA        VALUE_(4,0) 
+#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTB        VALUE_(4,1) 
+#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTC        VALUE_(4,2) 
+#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTD        VALUE_(4,3) 
+#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTE        VALUE_(4,4)
+#define CYGHWR_HAL_STM32_AFIO_EVCR_EVOE         BIT_(7) 
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_SPI1_RMP     BIT_(0)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_I2C1_RMP     BIT_(1)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_URT1_RMP     BIT_(2)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_URT2_RMP     BIT_(3)
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_NO_RMP  VALUE_(4,0)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_P1_RMP  VALUE_(4,1)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_FL_RMP  VALUE_(4,3)
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_NO_RMP  VALUE_(6,0)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_P1_RMP  VALUE_(6,1)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_FL_RMP  VALUE_(6,3)
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_NO_RMP  VALUE_(8,0)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_P1_RMP  VALUE_(8,1)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_P2_RMP  VALUE_(8,2)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_FL_RMP  VALUE_(8,3)
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_NO_RMP  VALUE_(10,0)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_P2_RMP  VALUE_(10,2)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_FL_RMP  VALUE_(10,3)
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM4_RMP     BIT_(12)
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_NO_RMP   VALUE_(13,0)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_FL1_RMP  VALUE_(13,2)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_FL2_RMP  VALUE_(13,3)
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_PD01_RMP     BIT_(15)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM5CH4_RMP  BIT_(16)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC1EINJ_RMP BIT_(17)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC1EREG_RMP BIT_(18)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC2EINJ_RMP BIT_(19)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC2EREG_RMP BIT_(20)
+
+#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+#define CYGHWR_HAL_STM32_AFIO_MAPR_ETH_RMP      BIT_(21)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN2_RMP     BIT_(22)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_ETH_RMII     BIT_(23)
+#endif
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_FULL     VALUE_(24,0)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_NORST    VALUE_(24,1)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPEN   VALUE_(24,2)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPDIS  VALUE_(24,4)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_MASK     VALUE_(24,7)
+
+#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+#define CYGHWR_HAL_STM32_AFIO_MAPR_SPI3_RMP     BIT_(28)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2ITR1_RMP BIT_(29)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_PTP_PPS_RMP  BIT_(30)
+#endif
+
+// The following macros are used to generate the bitfields for setting up
+// external interrupts.  For example, CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTC(12)
+// will generate the bitfield which when ORed into the EXTICR4 register will
+// set up C12 as the external interrupt pin for the EXTI12 interrupt.
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTA(__x) VALUE_(4*((__x)&3),0)
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTB(__x) VALUE_(4*((__x)&3),1)
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTC(__x) VALUE_(4*((__x)&3),2)
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTD(__x) VALUE_(4*((__x)&3),3)
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTE(__x) VALUE_(4*((__x)&3),4)
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTF(__x) VALUE_(4*((__x)&3),5)
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTG(__x) VALUE_(4*((__x)&3),6)
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_MASK(__x)  VALUE_(4*((__x)&3),0xF)
+
+// AFIO clock control
+
+#define CYGHWR_HAL_STM32_AFIO_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, AFIO )
+
+#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+//=============================================================================
+// GPIO ports - F2/F4 family
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+// GPIO Register offsets.
+#define CYGHWR_HAL_STM32_GPIO_MODER                   0x00
+#define CYGHWR_HAL_STM32_GPIO_OTYPER                  0x04
+#define CYGHWR_HAL_STM32_GPIO_OSPEEDR                 0x08
+#define CYGHWR_HAL_STM32_GPIO_PUPDR                   0x0C
+#define CYGHWR_HAL_STM32_GPIO_IDR                     0x10
+#define CYGHWR_HAL_STM32_GPIO_ODR                     0x14
+#define CYGHWR_HAL_STM32_GPIO_BSRR                    0x18
+#define CYGHWR_HAL_STM32_GPIO_LCKR                    0x1C
+#define CYGHWR_HAL_STM32_GPIO_AFRL                    0x20
+#define CYGHWR_HAL_STM32_GPIO_AFRH                    0x24
+
+// A helper macro just to allow access to a particular register
+#define CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, __offset)  ((volatile cyg_uint32 *)( ((char*)__portbaseaddr) + __offset ))
+
+// GPIO port mode register. 
+#define CYGHWR_HAL_STM32_GPIO_MODE_GPIO_IN            (0)
+#define CYGHWR_HAL_STM32_GPIO_MODE_GPIO_OUT           (1)
+#define CYGHWR_HAL_STM32_GPIO_MODE_ALTFN              (2)
+#define CYGHWR_HAL_STM32_GPIO_MODE_ANALOG             (3)
+#define CYGHWR_HAL_STM32_GPIO_MODE_VAL(__pin, __mode) ((__mode) << ((__pin)<<1))
+#define CYGHWR_HAL_STM32_GPIO_MODE_SET(__pin, __mode, __reg) ((__reg) &= ~MASK_((__pin<<1),2), \
+                                                              (__reg) |= CYGHWR_HAL_STM32_GPIO_MODE_VAL(__pin, __mode))
+
+// GPIO port output type register.
+#define CYGHWR_HAL_STM32_GPIO_OTYPE_PUSHPULL          (0)
+#define CYGHWR_HAL_STM32_GPIO_OTYPE_OPENDRAIN         (1)
+#define CYGHWR_HAL_STM32_GPIO_OTYPE_VAL(__pin, __otype)   VALUE_(__pin,__otype)
+#define CYGHWR_HAL_STM32_GPIO_OTYPE_SET(__pin, __otype, __reg)   ((__reg) &= ~BIT_(__pin), \
+                                                                  (__reg) |= CYGHWR_HAL_STM32_GPIO_OTYPE_VAL(__pin, __otype))
+#define CYGHWR_HAL_STM32_GPIO_OTYPE_NA                (0) // Convenience define for ease of pin definitions
+
+// GPIO port output speed register.
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_LOW              (0)  // 2MHz
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_2MHZ             (0)
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_MED              (1)  // 25MHz
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_25MHZ            (1)
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_FAST             (2)  // 50MHz
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_50MHZ            (2)
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_HIGH             (3)  // 100MHZ on 30pF, 80MHz on 15pF
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_BAL(__pin, __speed)  ((__speed) << ((__pin)<<1))
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_SET(__pin, __speed, __reg)  ((__reg) &= ~MASK_((__pin<<1),2), \
+                                                                  (__reg) |= CYGHWR_HAL_STM32_GPIO_OSPEED_BAL(__pin, __speed))
+
+// The following allows compatible specification of speed with other parts
+// which have different speed ranges e.g. F1
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_AT_LEAST(__mhz)  ( ((__mhz) <= 2) ? CYGHWR_HAL_STM32_GPIO_OSPEED_2MHZ :   \
+                                                        ((__mhz) <= 25) ? CYGHWR_HAL_STM32_GPIO_OSPEED_25MHZ : \
+                                                        ((__mhz) <= 50) ? CYGHWR_HAL_STM32_GPIO_OSPEED_50MHZ : \
+                                                        CYGHWR_HAL_STM32_GPIO_OSPEED_HIGH )
+  
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_AT_MOST(__mhz)  ( ((__mhz) < 25) ? CYGHWR_HAL_STM32_GPIO_OSPEED_2MHZ :   \
+                                                       ((__mhz) < 50) ? CYGHWR_HAL_STM32_GPIO_OSPEED_25MHZ :  \
+                                                       ((__mhz) < 100) ? CYGHWR_HAL_STM32_GPIO_OSPEED_50MHZ : \
+                                                       CYGHWR_HAL_STM32_GPIO_OSPEED_HIGH )
+
+// GPIO port pull-up/pull-down register.
+#define CYGHWR_HAL_STM32_GPIO_PUPD_NONE               (0)
+#define CYGHWR_HAL_STM32_GPIO_PUPD_PULLUP             (1)
+#define CYGHWR_HAL_STM32_GPIO_PUPD_PULLDOWN           (2)
+#define CYGHWR_HAL_STM32_GPIO_PUPD_VAL(__pin, __pupd) ((__pupd) << ((__pin)<<1))
+#define CYGHWR_HAL_STM32_GPIO_PUPD_SET(__pin, __pupd, __reg) ((__reg) &= ~MASK_(((__pin)<<1),2), \
+                                                              (__reg) |= CYGHWR_HAL_STM32_GPIO_PUPD_VAL(__pin, __pupd))
+
+// GPIO port input data register.
+#define CYGHWR_HAL_STM32_GPIO_IDR_GET(__portbaseaddr, __pin, __val) \
+  ((__val) = ( *CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_IDR) >> (__pin)) & 1)
+
+// GPIO port output data register.
+// Don't encourage setting it here. Use GPIO_BSRR instead for that.
+#define CYGHWR_HAL_STM32_GPIO_ODR_GET(__portbaseaddr, __pin, __val) \
+  ((__val) = ( *CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_ODR) >> (__pin)) & 1)
+
+// GPIO port bit set/reset register.
+#define CYGHWR_HAL_STM32_GPIO_BSRR_SET(__portbaseaddr, __pin, __val) \
+  ( *CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_BSRR) = (__val)?(1<<(__pin)):(1<<((__pin)+16)))
+
+// GPIO port configuration lock register.
+#define CYGHWR_HAL_STM32_GPIO_LCKR_LCKK               BIT_(16)
+#define CYGHWR_HAL_STM32_GPIO_LCKR_LCK(__pin)         BIT_((__pin))
+
+// GPIO alternate function low register.
+#define CYGHWR_HAL_STM32_GPIO_AFRL0                   MASK_(0,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRL1                   MASK_(4,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRL2                   MASK_(8,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRL3                   MASK_(12,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRL4                   MASK_(16,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRL5                   MASK_(20,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRL6                   MASK_(24,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRL7                   MASK_(28,4)
+// GPIO alternate function high register.
+#define CYGHWR_HAL_STM32_GPIO_AFRH8                   MASK_(0,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRH9                   MASK_(4,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRH10                  MASK_(8,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRH11                  MASK_(12,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRH12                  MASK_(16,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRH13                  MASK_(20,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRH14                  MASK_(24,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRH15                  MASK_(28,4)
+
+// Set alternate function. We try to keep this as a macro as most times the
+// arguments will be constant so can easily be collapsed substantially by the
+// compiler.
+// Note, this is not interrupt-safe, unavoidably. Provide your own protection
+// if that's needed, although in general this will happen at startup time.
+#define CYGHWR_HAL_STM32_GPIO_AFR_SET(__portbaseaddr, __pin, __func)    \
+  CYG_MACRO_START                                                       \
+  cyg_uint32 __cur_afr, __mask;                                         \
+  volatile cyg_uint32 *__reg;                                           \
+  cyg_uint8 __reg_pin = (__pin);                                        \
+  if (__pin < 8) {                                                      \
+    __reg = CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_AFRL); \
+  } else {                                                              \
+    __reg = CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_AFRH); \
+    __reg_pin -= 8;                                                     \
+  }                                                                     \
+  HAL_READ_UINT32( __reg, __cur_afr );                                  \
+  __mask = 0xf << (__reg_pin<<2);                                       \
+  __cur_afr &= ~__mask;                                                 \
+  __mask = (__func) << (__reg_pin<<2);                                  \
+  __cur_afr |= __mask;                                                  \
+  HAL_WRITE_UINT32( __reg, __cur_afr );                                 \
+  CYG_MACRO_END
+
+
+// This macro packs the port number, bit number, mode and
+// configuration for a GPIO pin into a single word. The packing puts
+// the GPIO bank at bits 16:19, the pin at bits 12:15, the mode (i.e. function)
+// at bits 10:11, for ALTFN mode the specific mapping at bits 6:9, pushpull(0)
+// or open drain(1) at bit 5, pull-up(1) pull-down (2) or neither(0) at
+// bits 3:4, and speed at bits 0:2 (low, med, fast, high).
+// To keep definitions short, we simplify most of the arguments so they
+// can be passed in with only their last components.
+
+// FIXME: This should be renamed to something like CYGHWR_HAL_STM32_PIN(... when
+// bringing F1 into line with this way of declaring pins.
+
+#define CYGHWR_HAL_STM32_GPIO(__port, __bit, __mode, __af, __ppod, __pupd, __speed) \
+  ( ((CYGHWR_HAL_STM32_GPIO##__port - CYGHWR_HAL_STM32_GPIOA) << 6 ) |	\
+    (__bit << 12) |							\
+    (CYGHWR_HAL_STM32_GPIO_MODE_##__mode << 10) |			\
+    (__af << 6) |                                                       \
+    (CYGHWR_HAL_STM32_GPIO_OTYPE_##__ppod << 5) |			\
+    (CYGHWR_HAL_STM32_GPIO_PUPD_##__pupd << 3) |			\
+    (CYGHWR_HAL_STM32_GPIO_OSPEED_##__speed) )
+
+// Macros to extract encoded values
+#define CYGHWR_HAL_STM32_GPIO_PORT(__pin)       (CYGHWR_HAL_STM32_GPIOA+(((__pin)&0xF0000)>>6))
+#define CYGHWR_HAL_STM32_GPIO_BIT(__pin)        (((__pin)>>12)&0xF)
+#define CYGHWR_HAL_STM32_GPIO_MODE(__pin)       (((__pin)>>10)&0x3)
+#define CYGHWR_HAL_STM32_GPIO_AF(__pin)         (((__pin)>>6)&0xF)
+#define CYGHWR_HAL_STM32_GPIO_OPENDRAIN(__pin)  (((__pin)>>5)&0x1)
+#define CYGHWR_HAL_STM32_GPIO_PULLUPDOWN(__pin) (((__pin)>>3)&0x3)
+#define CYGHWR_HAL_STM32_GPIO_SPEED(__pin)       ((__pin)&0x7)
+
+#endif  //if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+//=============================================================================
+
+#define CYGHWR_HAL_STM32_GPIO_NONE      (0xFFFFFFFF)
+
+// Functions and macros to configure GPIO ports.
+
+__externC void hal_stm32_gpio_set( cyg_uint32 pin );
+__externC void hal_stm32_gpio_out( cyg_uint32 pin, int val );
+__externC void hal_stm32_gpio_in ( cyg_uint32 pin, int *val );
+
+#define CYGHWR_HAL_STM32_GPIO_SET(__pin ) hal_stm32_gpio_set( __pin )
+#define CYGHWR_HAL_STM32_GPIO_OUT(__pin, __val ) hal_stm32_gpio_out( __pin, __val )
+#define CYGHWR_HAL_STM32_GPIO_IN(__pin,  __val ) hal_stm32_gpio_in( __pin, __val )
+
+//-----------------------------------------------------------------------------
+
+// For the following pin definition macros where __speed is a parameter the
+// actual rates available depend on the target family. The generic LOW, MED,
+// FAST and HIGH manifests can be used instead of explicit values, or more
+// usefully the AT_LEAST(__mhz) and AT_MOST(__mhz) macros can be used to specify
+// an acceptable limit instead.
+
+// The CYGHWR_HAL_STM32_PIN_OUT() macro defines a GPIO output pin. The __ppod
+// parameter can be one of PUSHPULL or OPENDRAIN. The __pupd parameter can be
+// one of NONE, PULLUP or PULLDOWN. For F1 devices the __pupd parameter is
+// not-relevant and is ignored.
+// e.g.
+//   CYGHWR_HAL_STM32_PIN_OUT(B,8,OPENDRAIN,NONE,FAST);
+//   CYGHWR_HAL_STM32_PIN_OUT(B,9,OPENDRAIN,NONE.AT_LEAST(50));
+
+// The CYGHWR_HAL_STM32_PIN_ALTFN_OUT() macro defines an alternative function
+// output pin. For F1 family devices the __af field is not-relevant and is
+// ignored. The __ppod should be PUSHPULL or OPENDRAIN. The __pupd parameter can
+// be one of NONE, PULLUP or PULLDOWN. For F1 devices the __pupd parameter is
+// not-relevant and is ignored.
+// e.g.
+//   CYGHWR_HAL_STM32_PIN_ALTFN_OUT(B,6,4,OPENDRAIN,NONE,MED);
+//   CYGHWR_HAL_STM32_PIN_ALTFN_OUT(B,10,4,OPENDRAIN,NONE,AT_LEAST(10));
+
+// The CYGHWR_HAL_STM32_PIN_IN() macro is used to define GPIO input pins. The
+// __pupd should be one of NONE. FLOATING, PULLUP or PULLDOWN.
+// e.g.
+//   CYGHWR_HAL_STM32_PIN_IN(B,4,PULLUP);
+
+// The CYGHWR_HAL_STM32_PIN_ALTFN_IN() macro is used to define alternate
+// function input pins. The __ppod parameter can be one of PUSHPULL,
+// OPENDRAIN or NA. The __pupd should be one of NONE. FLOATING, PULLUP or
+// PULLDOWN. For F1 family devices the __af and _ppod fields are not relevant
+// and are ignored, and in reality this macro peforms the same function as
+// CYGHWR_HAL_STM32_PIN_IN() for F1 family devices since extra AFIO
+// configuration is needed.
+// e.g.
+//   CYGHWR_HAL_STM32_PIN_ALTFN_IN(B,4,6,OPENDRAIN,PULLUP);
+
+// The CYGHWR_HAL_STM32_PIN_ANALOG() macro defines an analog mode pin. For F1
+// family devices this is for input only, e.g. ADC.
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+#define CYGHWR_HAL_STM32_GPIO_CNF_NONE (CYGHWR_HAL_STM32_GPIO_CNF_FLOATING) // Should not be needed for F1 family but ensure HIPERFORMANCE compatible name NONE exists
+
+#define CYGHWR_HAL_STM32_PIN_OUT(__port,__pin,__ppod,__pupd,__speed) \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,OUT_##__speed,OUT_##__ppod)
+
+#define CYGHWR_HAL_STM32_PIN_ALTFN_OUT(__port,__pin,__af,__ppod,__pupd,__speed) \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,OUT_##__speed,ALT_##__ppod)
+
+#define CYGHWR_HAL_STM32_PIN_IN(__port,__pin,__pupd)     \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,IN,__pupd)
+
+#define CYGHWR_HAL_STM32_PIN_ALTFN_IN(__port,__pin,__af,__ppod,__pupd)  \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,IN,__pupd) // NOTE: Identical to CYGHWR_HAL_STM32_PIN_IN() at the moment
+
+#define CYGHWR_HAL_STM32_PIN_ANALOG(__port,__pin) \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,IN,ANALOG)
+
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_GPIO_PUPD_FLOATING (CYGHWR_HAL_STM32_GPIO_PUPD_NONE) // Should not be needed for HIPERFORMANCE family but ensure F1 compatible name FLOATING exists
+
+#define CYGHWR_HAL_STM32_PIN_OUT(__port,__pin,__ppod,__pupd,__speed) \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,GPIO_OUT,0,__ppod,__pupd,__speed)
+
+#define CYGHWR_HAL_STM32_PIN_ALTFN_OUT(__port,__pin,__af,__ppod,__pupd,__speed) \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,ALTFN,__af,__ppod,__pupd,__speed)
+
+#define CYGHWR_HAL_STM32_PIN_IN(__port,__pin,__pupd) \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,GPIO_IN,0,NA,__pupd,NA)
+
+#define CYGHWR_HAL_STM32_PIN_ALTFN_IN(__port,__pin,__af,__ppod,__pupd)  \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,ALTFN,__af,__ppod,__pupd,NA)
+
+#define CYGHWR_HAL_STM32_PIN_ANALOG(__port,__pin) \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,ANALOG,0,NA,NONE,NA)
+
+#else
+#error "Unknown STM32 family for GPIO PIN macros"
+#endif
+
+//-----------------------------------------------------------------------------
+// end of var_io_pins.h
+#endif // CYGONCE_HAL_VAR_IO_PINS_H
diff --git a/packages/hal/cortexm/stm32/var/current/include/var_io_usart.h b/packages/hal/cortexm/stm32/var/current/include/var_io_usart.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/var/current/include/var_io_usart.h
@@ -0,0 +1,264 @@
+#ifndef CYGONCE_HAL_VAR_IO_USART_H
+#define CYGONCE_HAL_VAR_IO_USART_H
+//=============================================================================
+//
+//      var_io_usart.h
+//
+//      USART-specific variant definitions
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg, jlarmour
+// Date:        2008-07-30
+// Purpose:     STM32 variant USART specific registers
+// Description: 
+// Usage:       Do not include this header file directly. Instead:
+//              #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#ifndef CYGONCE_HAL_VAR_IO_H
+# error Do not include var_io_usart.h directly, use var_io.h
+#endif
+
+//=============================================================================
+// UARTs
+
+#define CYGHWR_HAL_STM32_UART_SR                0x00
+#define CYGHWR_HAL_STM32_UART_DR                0x04
+#define CYGHWR_HAL_STM32_UART_BRR               0x08
+#define CYGHWR_HAL_STM32_UART_CR1               0x0C
+#define CYGHWR_HAL_STM32_UART_CR2               0x10
+#define CYGHWR_HAL_STM32_UART_CR3               0x14
+#define CYGHWR_HAL_STM32_UART_GTPR              0x18
+
+// SR Bits
+
+#define CYGHWR_HAL_STM32_UART_SR_PE             BIT_(0)
+#define CYGHWR_HAL_STM32_UART_SR_FE             BIT_(1)
+#define CYGHWR_HAL_STM32_UART_SR_NE             BIT_(2)
+#define CYGHWR_HAL_STM32_UART_SR_NF             BIT_(2)
+#define CYGHWR_HAL_STM32_UART_SR_ORE            BIT_(3)
+#define CYGHWR_HAL_STM32_UART_SR_IDLE           BIT_(4)
+#define CYGHWR_HAL_STM32_UART_SR_RXNE           BIT_(5)
+#define CYGHWR_HAL_STM32_UART_SR_TC             BIT_(6)
+#define CYGHWR_HAL_STM32_UART_SR_TXE            BIT_(7)
+#define CYGHWR_HAL_STM32_UART_SR_LBD            BIT_(8)
+#define CYGHWR_HAL_STM32_UART_SR_CTS            BIT_(9)
+
+// BRR bits
+
+#define CYGHWR_HAL_STM32_UART_BRR_DIVF(__f)      VALUE_(0,__f)
+#define CYGHWR_HAL_STM32_UART_BRR_DIVM(__m)      VALUE_(4,__m)
+
+// CR1 bits
+
+#define CYGHWR_HAL_STM32_UART_CR1_SBK           BIT_(0)
+#define CYGHWR_HAL_STM32_UART_CR1_RWU           BIT_(1)
+#define CYGHWR_HAL_STM32_UART_CR1_RE            BIT_(2)
+#define CYGHWR_HAL_STM32_UART_CR1_TE            BIT_(3)
+#define CYGHWR_HAL_STM32_UART_CR1_IDLEIE        BIT_(4)
+#define CYGHWR_HAL_STM32_UART_CR1_RXNEIE        BIT_(5)
+#define CYGHWR_HAL_STM32_UART_CR1_TCIE          BIT_(6)
+#define CYGHWR_HAL_STM32_UART_CR1_TXEIE         BIT_(7)
+#define CYGHWR_HAL_STM32_UART_CR1_PEIE          BIT_(8)
+#define CYGHWR_HAL_STM32_UART_CR1_PS_EVEN       0
+#define CYGHWR_HAL_STM32_UART_CR1_PS_ODD        BIT_(9)
+#define CYGHWR_HAL_STM32_UART_CR1_PCE           BIT_(10)
+#define CYGHWR_HAL_STM32_UART_CR1_WAKE          BIT_(11)
+#define CYGHWR_HAL_STM32_UART_CR1_M_8           0
+#define CYGHWR_HAL_STM32_UART_CR1_M_9           BIT_(12)
+#define CYGHWR_HAL_STM32_UART_CR1_UE            BIT_(13)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_UART_CR1_OVER8         BIT_(15)
+#endif
+
+// CR2 bits
+
+#define CYGHWR_HAL_STM32_UART_CR2_ADD(__a)      VALUE_(0,__a)
+#define CYGHWR_HAL_STM32_UART_CR2_LBDL          BIT_(5)
+#define CYGHWR_HAL_STM32_UART_CR2_LBDIE         BIT_(6)
+#define CYGHWR_HAL_STM32_UART_CR2_LBCL          BIT_(8)
+#define CYGHWR_HAL_STM32_UART_CR2_CPHA          BIT_(9)
+#define CYGHWR_HAL_STM32_UART_CR2_CPOL          BIT_(10)
+#define CYGHWR_HAL_STM32_UART_CR2_CLKEN         BIT_(11)
+#define CYGHWR_HAL_STM32_UART_CR2_STOP_1        VALUE_(12,0)
+#define CYGHWR_HAL_STM32_UART_CR2_STOP_0_5      VALUE_(12,1)
+#define CYGHWR_HAL_STM32_UART_CR2_STOP_2        VALUE_(12,2)
+#define CYGHWR_HAL_STM32_UART_CR2_STOP_1_5      VALUE_(12,3)
+#define CYGHWR_HAL_STM32_UART_CR2_LINEN         BIT_(14)
+
+// CR3 bits
+
+#define CYGHWR_HAL_STM32_UART_CR3_EIE           BIT_(0)
+#define CYGHWR_HAL_STM32_UART_CR3_IREN          BIT_(1)
+#define CYGHWR_HAL_STM32_UART_CR3_IRLP          BIT_(2)
+#define CYGHWR_HAL_STM32_UART_CR3_HDSEL         BIT_(3)
+#define CYGHWR_HAL_STM32_UART_CR3_NACK          BIT_(4)
+#define CYGHWR_HAL_STM32_UART_CR3_SCEN          BIT_(5)
+#define CYGHWR_HAL_STM32_UART_CR3_DMAR          BIT_(6)
+#define CYGHWR_HAL_STM32_UART_CR3_DMAT          BIT_(7)
+#define CYGHWR_HAL_STM32_UART_CR3_RTSE          BIT_(8)
+#define CYGHWR_HAL_STM32_UART_CR3_CTSE          BIT_(9)
+#define CYGHWR_HAL_STM32_UART_CR3_CTSIE         BIT_(10)
+
+// GTPR fields
+
+#define CYGHWR_HAL_STM32_UART_GTPR_PSC(__p)     VALUE_(0,__p)
+#define CYGHWR_HAL_STM32_UART_GTPR_GT(__g)      VALUE_(8,__g)
+
+// UART GPIO pins
+
+// NOTE: For those UARTS providing a RTS pin the driver uses HW CTS control but
+// manually controls the RTS as a GPIO.
+
+#ifndef CYGHWR_HAL_STM32_UART0_REMAP
+#define CYGHWR_HAL_STM32_UART1_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A, 10,  7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART1_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  9,  7, PUSHPULL, NONE,    50MHZ )
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART1_REMAP_CONFIG     0
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+#else // CYGHWR_HAL_STM32_UART0_REMAP
+#define CYGHWR_HAL_STM32_UART1_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B,  7,  7, NA  ,     FLOATING )
+#define CYGHWR_HAL_STM32_UART1_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  6,  7, PUSHPULL, NONE,    50MHZ )
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART1_REMAP_CONFIG     CYGHWR_HAL_STM32_AFIO_MAPR_URT1_RMP
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+#endif // else CYGHWR_HAL_STM32_UART0_REMAP
+
+#define CYGHWR_HAL_STM32_UART1_CTS              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A, 11,  7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART1_RTS              CYGHWR_HAL_STM32_PIN_OUT( A, 12, PUSHPULL, NONE, 50MHZ )
+
+#define CYGHWR_HAL_STM32_UART1_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB2, UART1 )
+
+#ifndef CYGHWR_HAL_STM32_UART1_REMAP
+#define CYGHWR_HAL_STM32_UART2_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A,  3, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART2_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  2, 7, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART2_CTS              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A,  0, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART2_RTS              CYGHWR_HAL_STM32_PIN_OUT( A, 1, PUSHPULL, NONE, 50MHZ )
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART2_REMAP_CONFIG     0
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+#else
+#define CYGHWR_HAL_STM32_UART2_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  D,  6, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART2_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( D,  5, 7, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART2_CTS              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  D,  3, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART2_RTS              CYGHWR_HAL_STM32_PIN_OUT( D,  4, PUSHPULL, NONE, 50MHZ )
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART2_REMAP_CONFIG     CYGHWR_HAL_STM32_AFIO_MAPR_URT2_RMP
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+#endif
+
+#define CYGHWR_HAL_STM32_UART2_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB1, UART2 )
+
+#if defined(CYGHWR_HAL_STM32_UART2_REMAP_PARTIAL)
+
+#define CYGHWR_HAL_STM32_UART3_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C, 11, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART3_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, 7, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART3_CTS              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B, 13, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART3_RTS              CYGHWR_HAL_STM32_PIN_OUT( B, 14, PUSHPULL, NONE, 50MHZ )
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART3_REMAP_CONFIG     CYGHWR_HAL_STM32_AFIO_MAPR_URT3_P1_RMP
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+
+#elif defined(CYGHWR_HAL_STM32_UART2_REMAP_FULL)
+
+#define CYGHWR_HAL_STM32_UART3_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  D,  9, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART3_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( D,  8, 7, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART3_CTS              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  D, 11, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART3_RTS              CYGHWR_HAL_STM32_PIN_OUT( D, 12, PUSHPULL, NONE, 50MHZ )
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART3_REMAP_CONFIG     CYGHWR_HAL_STM32_AFIO_MAPR_URT3_FL_RMP
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+
+#else
+
+#define CYGHWR_HAL_STM32_UART3_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B, 11, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART3_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 10, 7, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART3_CTS              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B, 13, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART3_RTS              CYGHWR_HAL_STM32_PIN_OUT( B, 14, PUSHPULL, NONE, 50MHZ )
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART3_REMAP_CONFIG     CYGHWR_HAL_STM32_AFIO_MAPR_URT3_NO_RMP
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+
+#endif
+
+#define CYGHWR_HAL_STM32_UART3_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB1, UART3 )
+
+#define CYGHWR_HAL_STM32_UART4_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C, 11, 8, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART4_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, 8, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART4_CTS              CYGHWR_HAL_STM32_GPIO_NONE
+#define CYGHWR_HAL_STM32_UART4_RTS              CYGHWR_HAL_STM32_GPIO_NONE
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART4_REMAP_CONFIG     0
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+
+#define CYGHWR_HAL_STM32_UART4_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB1, UART4 )
+
+#define CYGHWR_HAL_STM32_UART5_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  D,  2, 8, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART5_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 12, 8, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART5_CTS              CYGHWR_HAL_STM32_GPIO_NONE
+#define CYGHWR_HAL_STM32_UART5_RTS              CYGHWR_HAL_STM32_GPIO_NONE
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART5_REMAP_CONFIG     0
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+
+#define CYGHWR_HAL_STM32_UART5_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB1, UART5 )
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_UART6_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C,  7, 8, NA,       NONE )
+#define CYGHWR_HAL_STM32_UART6_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C,  6, 8, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART6_CTS              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  G, 15, 8, NA,       NONE )
+#define CYGHWR_HAL_STM32_UART6_RTS              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G,  8, 8, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART6_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB2, UART6 )
+
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE
+
+#ifndef __ASSEMBLER__
+
+__externC void hal_stm32_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud );
+
+#endif
+
+#endif // CYGONCE_HAL_VAR_IO_USART_H
+//-----------------------------------------------------------------------------
+// end of var_io_usart.h
diff --git a/packages/hal/cortexm/stm32/var/current/src/hal_diag.c b/packages/hal/cortexm/stm32/var/current/src/hal_diag.c
--- a/packages/hal/cortexm/stm32/var/current/src/hal_diag.c
+++ b/packages/hal/cortexm/stm32/var/current/src/hal_diag.c
@@ -72,26 +72,56 @@ typedef struct {
     int                 isr_vector;
     cyg_uint32          rxpin;
     cyg_uint32          txpin;
+    cyg_uint32          clkena;
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+    cyg_uint32          remap;
+#endif
     cyg_uint32          baud_rate;
     int                 irq_state;
     
 } channel_data_t;
 
+// If remap isn't supported (e.g. F2/F4 parts) just #define to nothing. The struct initialiser will still work.
+#ifndef CYGHWR_HAL_STM32_UART1_REMAP_CONFIG
+#define CYGHWR_HAL_STM32_UART1_REMAP_CONFIG
+#endif
+#ifndef CYGHWR_HAL_STM32_UART2_REMAP_CONFIG
+#define CYGHWR_HAL_STM32_UART2_REMAP_CONFIG
+#endif
+#ifndef CYGHWR_HAL_STM32_UART3_REMAP_CONFIG
+#define CYGHWR_HAL_STM32_UART3_REMAP_CONFIG
+#endif
+#ifndef CYGHWR_HAL_STM32_UART4_REMAP_CONFIG
+#define CYGHWR_HAL_STM32_UART4_REMAP_CONFIG
+#endif
+#ifndef CYGHWR_HAL_STM32_UART5_REMAP_CONFIG
+#define CYGHWR_HAL_STM32_UART5_REMAP_CONFIG
+#endif
+
 static channel_data_t stm32_ser_channels[] = {
 #if CYGINT_HAL_STM32_UART0>0
-    { 0, CYGHWR_HAL_STM32_UART1, 1000, CYGNUM_HAL_INTERRUPT_UART1, CYGHWR_HAL_STM32_UART1_RX, CYGHWR_HAL_STM32_UART1_TX },
+    { 0, CYGHWR_HAL_STM32_UART1, 1000, CYGNUM_HAL_INTERRUPT_UART1, CYGHWR_HAL_STM32_UART1_RX, CYGHWR_HAL_STM32_UART1_TX,
+      CYGHWR_HAL_STM32_UART1_CLOCK, CYGHWR_HAL_STM32_UART1_REMAP_CONFIG },
 #endif
 #if CYGINT_HAL_STM32_UART1>0
-    { 1, CYGHWR_HAL_STM32_UART2, 1000, CYGNUM_HAL_INTERRUPT_UART2, CYGHWR_HAL_STM32_UART2_RX, CYGHWR_HAL_STM32_UART2_TX },
+    { 1, CYGHWR_HAL_STM32_UART2, 1000, CYGNUM_HAL_INTERRUPT_UART2, CYGHWR_HAL_STM32_UART2_RX, CYGHWR_HAL_STM32_UART2_TX,
+      CYGHWR_HAL_STM32_UART2_CLOCK, CYGHWR_HAL_STM32_UART2_REMAP_CONFIG },
 #endif
 #if CYGINT_HAL_STM32_UART2>0
-    { 2, CYGHWR_HAL_STM32_UART3, 1000, CYGNUM_HAL_INTERRUPT_UART3, CYGHWR_HAL_STM32_UART3_RX, CYGHWR_HAL_STM32_UART3_TX },
+    { 2, CYGHWR_HAL_STM32_UART3, 1000, CYGNUM_HAL_INTERRUPT_UART3, CYGHWR_HAL_STM32_UART3_RX, CYGHWR_HAL_STM32_UART3_TX,
+      CYGHWR_HAL_STM32_UART3_CLOCK, CYGHWR_HAL_STM32_UART3_REMAP_CONFIG },
 #endif
 #if CYGINT_HAL_STM32_UART3>0
-    { 3, CYGHWR_HAL_STM32_UART4, 1000, CYGNUM_HAL_INTERRUPT_UART4, CYGHWR_HAL_STM32_UART4_RX, CYGHWR_HAL_STM32_UART4_TX },
+    { 3, CYGHWR_HAL_STM32_UART4, 1000, CYGNUM_HAL_INTERRUPT_UART4, CYGHWR_HAL_STM32_UART4_RX, CYGHWR_HAL_STM32_UART4_TX,
+      CYGHWR_HAL_STM32_UART4_CLOCK, CYGHWR_HAL_STM32_UART4_REMAP_CONFIG },
 #endif
 #if CYGINT_HAL_STM32_UART4>0
-    { 4, CYGHWR_HAL_STM32_UART5, 1000, CYGNUM_HAL_INTERRUPT_UART5, CYGHWR_HAL_STM32_UART5_RX, CYGHWR_HAL_STM32_UART5_TX },
+    { 4, CYGHWR_HAL_STM32_UART5, 1000, CYGNUM_HAL_INTERRUPT_UART5, CYGHWR_HAL_STM32_UART5_RX, CYGHWR_HAL_STM32_UART5_TX,
+      CYGHWR_HAL_STM32_UART5_CLOCK, CYGHWR_HAL_STM32_UART5_REMAP_CONFIG },
+#endif
+#if CYGINT_HAL_STM32_UART5>0
+    { 5, CYGHWR_HAL_STM32_UART6, 1000, CYGNUM_HAL_INTERRUPT_UART6, CYGHWR_HAL_STM32_UART6_RX, CYGHWR_HAL_STM32_UART6_TX,
+      CYGHWR_HAL_STM32_UART6_CLOCK },  // UART6 only supported on F2/F4 so no remap config needed.
 #endif
 };
 
@@ -108,6 +138,19 @@ hal_stm32_serial_init_channel(void* __ch
 
     CYGHWR_HAL_STM32_GPIO_SET( chan->rxpin );
     CYGHWR_HAL_STM32_GPIO_SET( chan->txpin );
+    CYGHWR_HAL_STM32_CLOCK_ENABLE( chan->clkena );
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+    if( chan->remap != 0 )
+    {
+        CYG_ADDRESS afio = CYGHWR_HAL_STM32_AFIO;
+        cyg_uint32 mapr;
+        CYGHWR_HAL_STM32_CLOCK_ENABLE( CYGHWR_HAL_STM32_AFIO_CLOCK );
+        HAL_READ_UINT32( afio+CYGHWR_HAL_STM32_AFIO_MAPR, mapr );
+        mapr |= chan->remap;
+        HAL_WRITE_UINT32( afio+CYGHWR_HAL_STM32_AFIO_MAPR, mapr );
+    }
+#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
 
     cr2 = CYGHWR_HAL_STM32_UART_CR2_STOP_1;
     HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR2, cr2 );
diff --git a/packages/hal/cortexm/stm32/var/current/src/stm32_dma.c b/packages/hal/cortexm/stm32/var/current/src/stm32_dma.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/stm32/var/current/src/stm32_dma.c
@@ -0,0 +1,308 @@
+/*=============================================================================
+//
+//      stm32_dma.c
+//
+//      STM32 DMA support
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Contributors: 
+// Date:         2009-10-11
+// Purpose:      STM32 DMA support
+// Description:  This file provides the implementation for the STM32's
+//               on-chip DMA controllers.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal_cortexm_stm32.h>
+
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/var_dma.h>
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_ass.h>
+
+//=============================================================================
+
+#if 0
+#define dma_diag( __fmt, ... ) diag_printf("DMA: %20s[%3d]: " __fmt, __FUNCTION__, __LINE__, ## __VA_ARGS__ );
+#define dma_dump_buf(__addr, __size ) diag_dump_buf( __addr, __size )
+#else
+#define dma_diag( __fmt, ... )
+#define dma_dump_buf(__addr, __size )
+#endif
+
+//=============================================================================
+
+static const struct
+{
+    CYG_ADDRWORD        base;
+    cyg_uint32          clock;
+} hal_stm32_dma_controller[] =
+{
+    { 0, 0 },
+    { CYGHWR_HAL_STM32_DMA1, CYGHWR_HAL_STM32_DMA1_CLOCK },
+    { CYGHWR_HAL_STM32_DMA2, CYGHWR_HAL_STM32_DMA2_CLOCK },
+};
+
+//-----------------------------------------------------------------------------
+
+static cyg_uint32 hal_stm32_dma_isr( cyg_vector_t vector, CYG_ADDRWORD data )
+{
+    hal_stm32_dma_stream *stream = (hal_stm32_dma_stream *)data;
+    cyg_uint32 ret = CYG_ISR_HANDLED;    
+    cyg_uint32 isr;
+
+    HAL_READ_UINT32( stream->ctlr+CYGHWR_HAL_STM32_DMA_ISR_REG(stream->stream), isr );
+
+    dma_diag("ctlr %08x stream %d chan %d isr %08x\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc), isr );
+
+    if( isr & CYGHWR_HAL_STM32_DMA_ISR_TCIF(stream->stream) )
+    {
+        // Clear all stream interrupt bits
+        HAL_WRITE_UINT32( stream->ctlr+CYGHWR_HAL_STM32_DMA_IFCR_REG(stream->stream),
+                          CYGHWR_HAL_STM32_DMA_IFCR_MASK(stream->stream) );
+        
+        if( (stream->ccr & CYGHWR_HAL_STM32_DMA_CCR_CIRC) == 0)
+        {
+            // Disable the stream
+            HAL_WRITE_UINT32( stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), 0 );
+        }
+
+        // Update the count
+        HAL_READ_UINT32( stream->ctlr+CYGHWR_HAL_STM32_DMA_CNDTR(stream->stream), stream->count );
+
+        ret = CYG_ISR_CALL_DSR;
+    }
+
+    return ret;
+}
+
+//-----------------------------------------------------------------------------
+
+static void hal_stm32_dma_dsr( cyg_vector_t vector, cyg_ucount32 count, CYG_ADDRWORD data )
+{
+    hal_stm32_dma_stream *stream = (hal_stm32_dma_stream *)data;
+
+    dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) );
+    
+    stream->callback( stream, stream->count, stream->data );
+
+    stream->active = false;    
+}
+
+//-----------------------------------------------------------------------------
+
+void hal_stm32_dma_init( hal_stm32_dma_stream *stream, int pri )
+{
+    stream->ctlr = hal_stm32_dma_controller[CYGHWR_HAL_STM32_DMA_CONTROLLER(stream->desc)].base;
+    stream->stream = CYGHWR_HAL_STM32_DMA_STREAM(stream->desc);
+
+    dma_diag("ctlr %08x stream %d chan %d pri %d\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc), pri );
+             
+    cyg_drv_interrupt_create( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc),
+                              pri,
+                              (CYG_ADDRWORD)stream,
+                              hal_stm32_dma_isr,
+                              hal_stm32_dma_dsr,
+                              &stream->handle,
+                              &stream->interrupt );
+    cyg_drv_interrupt_attach( stream->handle );
+    cyg_drv_interrupt_unmask( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc) );
+
+    // Enable DMA controller clock
+    CYGHWR_HAL_STM32_CLOCK_ENABLE( hal_stm32_dma_controller[CYGHWR_HAL_STM32_DMA_CONTROLLER(stream->desc)].clock );
+
+
+    // Clear CCR, disable channel and put into known state
+    HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), 0 );
+
+    
+    // Initialize a private copy of the CCR, we don't write this to
+    // the hardware until we are ready to start the transfer.
+
+    stream->ccr = CYGHWR_HAL_STM32_DMA_CCR_EN;
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+    // Select channel number in F2/F4 variants. The F1 variants simply
+    // have the various device DMA request lines wire-ORed together.
+    stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_CHSEL(CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc));
+#endif
+    
+    // Set stream direction
+    if( CYGHWR_HAL_STM32_DMA_MODE(stream->desc) == CYGHWR_HAL_STM32_DMA_MODE_M2P )
+        stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_MEM2P;
+
+    // Set memory increment mode
+    stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_MINC;
+           
+    // Transfer end interrupt enable
+    stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_TCIE;
+
+    // Use top 2 bits of priority to define DMA stream priority
+    stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_PL((pri>>6)&3);
+    
+    dma_diag("ccr %08x\n", stream->ccr);
+}
+
+//-----------------------------------------------------------------------------
+
+void hal_stm32_dma_delete( hal_stm32_dma_stream *stream )
+{
+    dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) );
+
+    // Clear CCR, disables stream
+    HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), 0 );
+
+    // Mask, detach and delete interrupt object
+    cyg_drv_interrupt_mask( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc) );
+    cyg_drv_interrupt_detach( stream->handle );
+    cyg_drv_interrupt_delete( stream->handle );
+}
+
+//-----------------------------------------------------------------------------
+
+void hal_stm32_dma_disable( hal_stm32_dma_stream *stream )
+{
+    dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) );
+
+    // Clear CCR, disables stream
+    HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), 0 );
+}
+
+//-----------------------------------------------------------------------------
+
+void hal_stm32_dma_poll( hal_stm32_dma_stream *stream )
+{
+//    dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream,
+//             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) );
+    
+    if( stream->active )
+        if( hal_stm32_dma_isr( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc), (CYG_ADDRWORD)stream ) & CYG_ISR_CALL_DSR )
+            hal_stm32_dma_dsr( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc), 1, (CYG_ADDRWORD)stream );
+}
+
+//-----------------------------------------------------------------------------
+
+void hal_stm32_dma_configure( hal_stm32_dma_stream *stream, int tfr_size, cyg_bool no_minc, cyg_bool polled  )
+{
+    dma_diag("ctlr %08x stream %d chan %d tfr_size %d no_minc %d polled %d\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc), tfr_size, no_minc, polled );
+    
+    if( tfr_size == 8 )
+        stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_PSIZE8 | CYGHWR_HAL_STM32_DMA_CCR_MSIZE8;
+    else if( tfr_size == 16 )
+        stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_PSIZE16 | CYGHWR_HAL_STM32_DMA_CCR_MSIZE16;
+    else 
+        stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_PSIZE32 | CYGHWR_HAL_STM32_DMA_CCR_MSIZE32;
+
+    // Clear MINC bit if not wanted
+    if( no_minc )
+        stream->ccr &= ~CYGHWR_HAL_STM32_DMA_CCR_MINC;
+    else
+        stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_MINC;
+
+    // Clear interrupt enables if polled mode, otherwise enable them
+    if( polled )
+        stream->ccr &= ~(CYGHWR_HAL_STM32_DMA_CCR_TCIE | CYGHWR_HAL_STM32_DMA_CCR_TEIE);
+    else
+        stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_TCIE | CYGHWR_HAL_STM32_DMA_CCR_TEIE;
+}
+
+//-----------------------------------------------------------------------------
+
+void hal_stm32_dma_configure_circular( hal_stm32_dma_stream *stream, cyg_bool enable)
+{
+    if (enable) {
+        stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_CIRC;
+    } else {
+        stream->ccr &= ~CYGHWR_HAL_STM32_DMA_CCR_CIRC;
+    }
+}
+
+//-----------------------------------------------------------------------------
+
+void hal_stm32_dma_start( hal_stm32_dma_stream *stream, void *memory, CYG_ADDRESS peripheral, cyg_uint32 size )
+{
+    dma_diag("ctlr %08x stream %d chan %d mem %08x peri %08x size %d\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc), memory, peripheral, size );
+
+    HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CMAR(stream->stream), (cyg_uint32)memory );
+
+    HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CPAR(stream->stream), peripheral );
+
+    HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CNDTR(stream->stream), size );
+
+    HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), stream->ccr );
+
+    stream->active = true;
+}
+
+//=============================================================================
+
+void hal_stm32_dma_show( hal_stm32_dma_stream *stream )
+{
+    cyg_uint32 dma = stream->ctlr;
+    cyg_uint32 chan = stream->stream;
+    cyg_uint32 reg;
+    
+    dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) );
+    dma_diag("vector %d stream->ccr %08x\n", CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc), stream->ccr );
+
+    HAL_READ_UINT32( dma+CYGHWR_HAL_STM32_DMA_ISR_REG(chan), reg );
+    dma_diag("DMA   ISR:   %08x\n", reg );
+    
+    HAL_READ_UINT32( dma+CYGHWR_HAL_STM32_DMA_CCR(chan), reg );   dma_diag("DMA %d CCR:   %08x\n", chan, reg );
+    HAL_READ_UINT32( dma+CYGHWR_HAL_STM32_DMA_CNDTR(chan), reg ); dma_diag("DMA %d CNDTR: %08x\n", chan, reg );
+    HAL_READ_UINT32( dma+CYGHWR_HAL_STM32_DMA_CPAR(chan), reg );  dma_diag("DMA %d CPAR:  %08x\n", chan, reg );
+    HAL_READ_UINT32( dma+CYGHWR_HAL_STM32_DMA_CMAR(chan), reg );  dma_diag("DMA %d CMAR:  %08x\n", chan, reg );
+    
+}
+
+
+//=============================================================================
+/* EOF stm32_dma.c */
diff --git a/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c b/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c
--- a/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c
+++ b/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008, 2009 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2009, 2011, 2014 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -40,6 +40,7 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):    nickg
+// Contributors: jld
 // Date:         2008-07-30
 // Description:  
 //
@@ -63,6 +64,11 @@
 #include <cyg/hal/hal_intr.h>           // HAL header
 #include <cyg/hal/hal_if.h>             // HAL header
 
+#ifdef CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER
+#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
+#include <cyg/profile/profile.h>        // __profile_hit()
+#endif
+
 //==========================================================================
 // Clock Initialization values
 
@@ -121,6 +127,9 @@ cyg_uint32 hal_stm32_hclk;
 cyg_uint32 hal_stm32_pclk1;
 cyg_uint32 hal_stm32_pclk2;
 cyg_uint32 hal_cortexm_systick_clock;
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+cyg_uint32 hal_stm32_qclk;
+#endif
 
 void hal_start_clocks( void );
 cyg_uint32 hal_exti_isr( cyg_uint32 vector, CYG_ADDRWORD data );
@@ -129,11 +138,6 @@ cyg_uint32 hal_exti_isr( cyg_uint32 vect
 
 void hal_variant_init( void )
 {
-    CYG_ADDRESS rcc = CYGHWR_HAL_STM32_RCC;
-
-    // Enable all devices in RCC
-    HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_APB2ENR, 0xFFFFFFFF );
-    HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_APB1ENR, 0xFFFFFFFF );
 
 #if 1 //!defined(CYG_HAL_STARTUP_RAM)
     hal_start_clocks();
@@ -161,15 +165,11 @@ void hal_start_clocks( void )
     
     // Reset RCC
 
-    HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, 0x00000001 );
+    cr = CYGHWR_HAL_STM32_RCC_CR_HSION;
+    HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, cr );
     
     // Start up HSE clock
     
-    HAL_READ_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, cr );
-    cr &= CYGHWR_HAL_STM32_RCC_CR_HSEON|CYGHWR_HAL_STM32_RCC_CR_HSEBYP;
-    HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, cr );
-
-    HAL_READ_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, cr );
     cr |= CYGHWR_HAL_STM32_RCC_CR_HSEON;
     HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, cr );
     
@@ -182,25 +182,78 @@ void hal_start_clocks( void )
 
     // Configure clocks
     
-    hal_stm32_sysclk = CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK;
+    // Temporarily divide by 4 until we've dealt with potential large
+    // multiplications overflow.
+    hal_stm32_sysclk = CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK >> 2;
     
     cfgr = 0;
 
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
 #if defined(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE_HSE)
     cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_HSE;
-#elif defined(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE_HSE_HALF)
-    cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_HSE |
-            CYGHWR_HAL_STM32_RCC_CFGR_PLLXTPRE;
+#endif
+
+    // Just a little sanity check.
+#if defined(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE_HSI) && (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV != 2)
+# error PLL PREDIV must be 2
+#endif
+
+    // Ordering could be important if divisions below cause truncation, so multiply first.
+    hal_stm32_sysclk *= CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL;
+
+#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+    HAL_WRITE_UINT32( rcc + CYGHWR_HAL_STM32_RCC_CFGR2,
+                      CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV1(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV-1) );
+    hal_stm32_sysclk /= CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV;
+#else
+    // Non-connectivity parts can only use PLLXTPRE
+    if ( CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 2 )
+    {
+        cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PLLXTPRE; // irrelevant if HSI used, so just set anyway.
     hal_stm32_sysclk /= 2;
-#elif defined(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE_HSI_HALF)
-    hal_stm32_sysclk /= 2;
+    }
 #endif
+    hal_stm32_sysclk <<= 2; // return to correct range now we've dealt with risk of overflow.
     
     cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PLLMUL(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL);
     cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_HPRE;
     cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PPRE1;
     cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PPRE2;
 
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE_HSE)
+    cfgr |= CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLSRC_HSE;
+#endif
+
+    cfgr |= CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLM(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV);
+    cfgr |= CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLN(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL);
+    // Ordering could be important if divisions below cause truncation, so multiply first.
+    hal_stm32_sysclk *= CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL;
+    hal_stm32_sysclk /= CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV;
+
+    hal_stm32_sysclk <<= 2; // return to correct range now we've dealt with risk of overflow.
+
+    cfgr |= CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP(CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV);
+    cfgr |= CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLQ(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV);
+
+    // qclk divides down VCO output, so calc it first before updating sysclk for PLLP
+    hal_stm32_qclk = hal_stm32_sysclk / CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV;
+
+    hal_stm32_sysclk /= CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV;
+
+    HAL_WRITE_UINT32( rcc + CYGHWR_HAL_STM32_RCC_PLLCFGR, cfgr );
+
+    cfgr  = CYGHWR_HAL_STM32_RCC_CFGR_HPRE;
+    cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PPRE1;
+    cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PPRE2;
+
+    // RTCPRE divides down HSE, which is the input clock. Must be 1MHz.
+    cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_RTCPRE( CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK/1000000 );
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
     HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CFGR, cfgr );
 
     // Enable the PLL and wait for it to lock
@@ -214,6 +267,7 @@ void hal_start_clocks( void )
     } while( !(cr & CYGHWR_HAL_STM32_RCC_CR_PLLRDY) );
 
     // Now switch to use PLL as SYSCLK
+    // TODO: make this configurable between HSI, HSE and PLL
     
     cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_SW_PLL;
 
@@ -226,11 +280,14 @@ void hal_start_clocks( void )
 
     // Calculate clocks from configuration
 
-    hal_stm32_sysclk *= CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL;
     hal_stm32_hclk = hal_stm32_sysclk / CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV;
     hal_stm32_pclk1 = hal_stm32_hclk / CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV;
     hal_stm32_pclk2 = hal_stm32_hclk / CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV;
+#ifdef CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE_INTERNAL
+    hal_cortexm_systick_clock = hal_stm32_hclk;
+#else
     hal_cortexm_systick_clock = hal_stm32_hclk / 8;
+#endif
 }
 
 //==========================================================================
@@ -271,6 +328,9 @@ cyg_uint32 hal_exti_isr( cyg_uint32 vect
 
 __externC void hal_stm32_gpio_set( cyg_uint32 pin )
 {
+  // FIXME: Power on GPIO ports selectively here, rather than
+  // platform having to power them all on for boot.
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
     cyg_uint32 port = CYGHWR_HAL_STM32_GPIO_PORT(pin);
     int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin);
     cyg_uint32 cm = CYGHWR_HAL_STM32_GPIO_CFG(pin);
@@ -281,8 +341,7 @@ cyg_uint32 hal_exti_isr( cyg_uint32 vect
     
     if( bit > 7 ) port += 4, bit -= 8;
     HAL_READ_UINT32( port, cr );
-    cr &= ~(0xF<<(bit*4));
-    cr |= cm<<(bit*4);
+    CYGHWR_HAL_STM32_GPIO_CNFMODE_SET(bit,cm,cr);
     HAL_WRITE_UINT32( port, cr );
 
     // If this is a pullup/down input, set the ODR bit to switch on
@@ -299,26 +358,99 @@ cyg_uint32 hal_exti_isr( cyg_uint32 vect
             odr &= ~(1<<bit);
         HAL_WRITE_UINT32( port+CYGHWR_HAL_STM32_GPIO_ODR, odr );
     }
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+    CYG_ADDRESS port = CYGHWR_HAL_STM32_GPIO_PORT(pin);
+    int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin);
+    cyg_uint32 mode = CYGHWR_HAL_STM32_GPIO_MODE(pin);
+    cyg_uint32 af = CYGHWR_HAL_STM32_GPIO_AF(pin);
+    cyg_uint32 od = CYGHWR_HAL_STM32_GPIO_OPENDRAIN(pin);
+    cyg_uint32 pupd = CYGHWR_HAL_STM32_GPIO_PULLUPDOWN(pin);
+    cyg_uint32 speed = CYGHWR_HAL_STM32_GPIO_SPEED(pin);
+    cyg_uint32 reg;
+
+    if( pin == CYGHWR_HAL_STM32_GPIO_NONE )
+        return;
+
+    
+    HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_OTYPER, reg );
+    CYGHWR_HAL_STM32_GPIO_OTYPE_SET( bit, od, reg );
+    HAL_WRITE_UINT32( port+CYGHWR_HAL_STM32_GPIO_OTYPER, reg );
+
+    HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_OSPEEDR, reg );
+    CYGHWR_HAL_STM32_GPIO_OSPEED_SET( bit, speed, reg );
+    HAL_WRITE_UINT32( port+CYGHWR_HAL_STM32_GPIO_OSPEEDR, reg );
+
+    HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_PUPDR, reg );
+    CYGHWR_HAL_STM32_GPIO_PUPD_SET( bit, pupd, reg );
+    HAL_WRITE_UINT32( port+CYGHWR_HAL_STM32_GPIO_PUPDR, reg );
+
+    if ( CYGHWR_HAL_STM32_GPIO_MODE_ALTFN == mode )
+    {
+        CYGHWR_HAL_STM32_GPIO_AFR_SET( port, bit, af );
+    }
+
+    HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_MODER, reg );
+    CYGHWR_HAL_STM32_GPIO_MODE_SET( bit, mode, reg );
+    HAL_WRITE_UINT32( port+CYGHWR_HAL_STM32_GPIO_MODER, reg );
+#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
 }
     
 __externC void hal_stm32_gpio_out( cyg_uint32 pin, int val )
 {
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
     cyg_uint32 port = CYGHWR_HAL_STM32_GPIO_PORT(pin);
     int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin);
     
     port += CYGHWR_HAL_STM32_GPIO_BSRR;
     if( (val&1) == 0 ) port += 4;
     HAL_WRITE_UINT32( port, 1<<bit );
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+    CYG_ADDRESS port = CYGHWR_HAL_STM32_GPIO_PORT(pin);
+    int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin);
+
+    CYGHWR_HAL_STM32_GPIO_BSRR_SET( port, bit, val );
+#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
 }
     
 __externC void hal_stm32_gpio_in ( cyg_uint32 pin, int *val )
 {
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
     cyg_uint32 port = CYGHWR_HAL_STM32_GPIO_PORT(pin);
     int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin);
     cyg_uint32 pd;
     
     HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_IDR, pd );
     *val = (pd>>bit)&1;
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+    CYG_ADDRESS port = CYGHWR_HAL_STM32_GPIO_PORT(pin);
+    int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin);
+
+    CYGHWR_HAL_STM32_GPIO_IDR_GET( port, bit, *val );
+#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+}
+
+//==========================================================================
+// Clock support.
+//
+// These functions provide support for enabling and disabling clock
+// control bits.
+
+__externC void hal_stm32_clock_enable( cyg_uint32 desc )
+{
+    cyg_uint32 r;
+    cyg_uint32 reg = CYGHWR_HAL_STM32_RCC+CYGHWR_HAL_STM32_CLOCK_REG(desc);
+    HAL_READ_UINT32( reg, r );
+    r |= BIT_(CYGHWR_HAL_STM32_CLOCK_PIN(desc));
+    HAL_WRITE_UINT32( reg, r );
+}
+
+__externC void hal_stm32_clock_disable( cyg_uint32 desc )
+{
+    cyg_uint32 r;
+    cyg_uint32 reg = CYGHWR_HAL_STM32_RCC+CYGHWR_HAL_STM32_CLOCK_REG(desc);
+    HAL_READ_UINT32( reg, r );
+    r &= ~BIT_(CYGHWR_HAL_STM32_CLOCK_PIN(desc));
+    HAL_WRITE_UINT32( reg, r );
 }
 
 //==========================================================================
@@ -334,7 +466,6 @@ void hal_stm32_bd_protect( int protect )
         cr &= ~CYGHWR_HAL_STM32_PWR_CR_DBP;
     else
         cr |= CYGHWR_HAL_STM32_PWR_CR_DBP;        
-
     HAL_WRITE_UINT32( pwr+CYGHWR_HAL_STM32_PWR_CR, cr );
 }
 
@@ -350,8 +481,14 @@ void hal_stm32_uart_setbaud( cyg_uint32 
     cyg_uint32 int_div, frac_div;
     cyg_uint32 brr;
     
-    if( base == CYGHWR_HAL_STM32_UART1 )
+    if( base == CYGHWR_HAL_STM32_UART1 ||
+#ifdef CYGHWR_HAL_STM32_UART6
+        base == CYGHWR_HAL_STM32_UART6 ||
+#endif
+        0)
+    {
         apbclk = hal_stm32_pclk2;
+    }
 
     int_div = (25 * apbclk ) / (4 * baud );
     brr = ( int_div / 100 ) << 4;
@@ -387,4 +524,51 @@ cyg_uint32 hal_stm32_timer_clock( CYG_AD
 }
 
 //==========================================================================
+// Profiling timer
+//
+// Implementation of profiling support using general-purpose timer TIM2.
+
+#ifdef CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER
+// Use TIM2 for profiling
+#define STM32_TIMER_PROFILE CYGHWR_HAL_STM32_TIM2
+#define STM32_CLOCK_PROFILE CYGHWR_HAL_STM32_TIM2_CLOCK
+#define HAL_INTERRUPT_PROFILE CYGNUM_HAL_INTERRUPT_TIM2
+
+// Profiling timer ISR
+static cyg_uint32 profile_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
+{
+    extern HAL_SavedRegisters *hal_saved_interrupt_state;
+
+    HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_SR, 0); // clear interrupt pending flag
+    HAL_INTERRUPT_ACKNOWLEDGE(HAL_INTERRUPT_PROFILE);
+    __profile_hit(hal_saved_interrupt_state->u.interrupt.pc);
+    return CYG_ISR_HANDLED;
+}
+
+// Profiling timer setup
+int hal_enable_profile_timer(int resolution)
+{
+    CYG_ASSERT(resolution < 0x10000, "Invalid profile timer resolution"); // 16 bits only
+
+    // Enable clock
+    CYGHWR_HAL_STM32_CLOCK_ENABLE(STM32_CLOCK_PROFILE);
+
+    // Attach ISR
+    HAL_INTERRUPT_ATTACH(HAL_INTERRUPT_PROFILE, &profile_isr, 0x1111, 0);
+    HAL_INTERRUPT_UNMASK(HAL_INTERRUPT_PROFILE);
+
+    // Setup timer
+    HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_PSC,
+        (hal_stm32_timer_clock(STM32_TIMER_PROFILE) / 1000000) - 1); // prescale to microseconds
+    HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_CR2, 0);
+    HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_DIER, CYGHWR_HAL_STM32_TIM_DIER_UIE);
+    HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_ARR, resolution);
+    HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_CR1, CYGHWR_HAL_STM32_TIM_CR1_CEN);
+
+    return resolution;
+}
+
+#endif // CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER
+
+//==========================================================================
 // EOF stm32_misc.c
diff --git a/packages/hal/cortexm/stm32/var/current/tests/timers.c b/packages/hal/cortexm/stm32/var/current/tests/timers.c
--- a/packages/hal/cortexm/stm32/var/current/tests/timers.c
+++ b/packages/hal/cortexm/stm32/var/current/tests/timers.c
@@ -120,7 +120,11 @@ struct timer timers[] =
     { 5, CYGHWR_HAL_STM32_TIM5, CYGNUM_HAL_INTERRUPT_TIM5,    0x60,    1453 },
     { 6, CYGHWR_HAL_STM32_TIM6, CYGNUM_HAL_INTERRUPT_TIM6,    0x70,    1931 },
     { 7, CYGHWR_HAL_STM32_TIM7, CYGNUM_HAL_INTERRUPT_TIM7,    0x80,    2011 },
+#ifdef CYGNUM_HAL_INTERRUPT_TIM8_UP
     { 8, CYGHWR_HAL_STM32_TIM8, CYGNUM_HAL_INTERRUPT_TIM8_UP, 0x90,    2345 },    
+#elif defined(CYGNUM_HAL_INTERRUPT_TIM8_UP_TIM13)
+    { 8, CYGHWR_HAL_STM32_TIM8, CYGNUM_HAL_INTERRUPT_TIM8_UP_TIM13, 0x90,    2345 },
+#endif
 #endif
     { 0, 0, 0, 0 }
 };
diff --git a/packages/hal/frv/arch/current/ChangeLog b/packages/hal/frv/arch/current/ChangeLog
--- a/packages/hal/frv/arch/current/ChangeLog
+++ b/packages/hal/frv/arch/current/ChangeLog
@@ -1,3 +1,7 @@
+2011-01-02  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/hal_frv.cdl: Eliminate some warnings. [ Bugzilla 1001083 ]
+
 2004-09-03  Mark Salter  <msalter@redhat.com>
 2004-09-03  David Woodhouse  <dwmw2@redhat.com>
 
diff --git a/packages/hal/frv/arch/current/cdl/hal_frv.cdl b/packages/hal/frv/arch/current/cdl/hal_frv.cdl
--- a/packages/hal/frv/arch/current/cdl/hal_frv.cdl
+++ b/packages/hal/frv/arch/current/cdl/hal_frv.cdl
@@ -64,7 +64,7 @@ cdl_package CYGPKG_HAL_FRV {
     # special rule used to build any include files, etc, used by assembly code
     make -priority 1 {
         frv.inc : <PACKAGE>/src/hal_mk_defs.c
-        $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,frv.tmp -o hal_mk_defs.tmp -S $<
+        $(CC) $(ACTUAL_CFLAGS) $(INCLUDE_PATH) -Wp,-MD,frv.tmp -o hal_mk_defs.tmp -S $<
         fgrep .equ hal_mk_defs.tmp | sed s/#// | sed s/\\.equ/#define/ > $@
         @echo $@ ": \\" > $(notdir $@).deps
         @tail -n +2 frv.tmp >> $(notdir $@).deps
@@ -83,7 +83,7 @@ cdl_package CYGPKG_HAL_FRV {
 
     make {
         <PREFIX>/lib/target.ld: <PACKAGE>/src/frv.ld
-        $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
+        $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -o $@ $<
         @echo $@ ": \\" > $(notdir $@).deps
         @tail -n +2 target.tmp >> $(notdir $@).deps
         @echo >> $(notdir $@).deps
diff --git a/packages/hal/i386/arch/current/ChangeLog b/packages/hal/i386/arch/current/ChangeLog
--- a/packages/hal/i386/arch/current/ChangeLog
+++ b/packages/hal/i386/arch/current/ChangeLog
@@ -1,3 +1,7 @@
+2011-01-02  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/hal_i386.cdl: Eliminate some warnings. [ Bugzilla 1001083 ]
+
 2005-09-19  David Vrabel  <dvrabel@arcom.com>
 
 	* src/redboot_linux_exec.c: No need to include pcmb_serial.h.
diff --git a/packages/hal/i386/arch/current/cdl/hal_i386.cdl b/packages/hal/i386/arch/current/cdl/hal_i386.cdl
--- a/packages/hal/i386/arch/current/cdl/hal_i386.cdl
+++ b/packages/hal/i386/arch/current/cdl/hal_i386.cdl
@@ -75,7 +75,7 @@ cdl_package CYGPKG_HAL_I386 {
 
     make {
         <PREFIX>/lib/target.ld: <PACKAGE>/src/i386.ld
-        $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
+        $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -o $@ $<
         @echo $@ ": \\" > $(notdir $@).deps
         @tail -n +2 target.tmp >> $(notdir $@).deps
         @echo >> $(notdir $@).deps
diff --git a/packages/hal/i386/pc/current/ChangeLog b/packages/hal/i386/pc/current/ChangeLog
--- a/packages/hal/i386/pc/current/ChangeLog
+++ b/packages/hal/i386/pc/current/ChangeLog
@@ -1,3 +1,8 @@
+2011-08-25  John Dallaway  <john@dallaway.org.uk>
+
+	* misc/grub.cfg: Add example GRUB2 configuration file. Patch from
+	Stephen Polkowski. [ Bugzilla 1001254 ]
+
 2009-01-31  Bart Veer <bartv@ecoscentric.com>
 
 	* cdl/hal_i386_pc.cdl: update compiler flags for gcc 4.x
@@ -505,7 +510,7 @@ 2000-02-15  Nick Garnett  <nickg@cygnus.
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2011 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/hal/i386/pc/current/misc/grub.cfg b/packages/hal/i386/pc/current/misc/grub.cfg
new file mode 100644
--- /dev/null
+++ b/packages/hal/i386/pc/current/misc/grub.cfg
@@ -0,0 +1,13 @@
+# Example GRUB 2 (version 1.98) Configuration File
+
+# Timeout for menu
+set timeout=10
+
+# Set default boot entry as Entry 0
+set default=0
+
+# Entry 0 - redboot
+menuentry "redboot from hd0,1" {
+    set root=(hd0,1)
+    multiboot /boot/redboot.elf
+}
diff --git a/packages/hal/i386/pcmb/current/ChangeLog b/packages/hal/i386/pcmb/current/ChangeLog
--- a/packages/hal/i386/pcmb/current/ChangeLog
+++ b/packages/hal/i386/pcmb/current/ChangeLog
@@ -1,3 +1,8 @@
+2011-03-17  Horst Schirmeier  <horst@schirmeier.com>
+
+	* include/pcmb.inc: To allow the BIOS timer interrupt handler to
+	switch off the drive, we need to make sure interrupts are enabled.
+
 2006-06-02  Nick Garnett  <nickg@ecoscentric.com>
 
 	* include/pcmb_io.h (HAL_PCI_TRANSLATE_INTERRUPT): Fixed PCI
diff --git a/packages/hal/i386/pcmb/current/include/pcmb.inc b/packages/hal/i386/pcmb/current/include/pcmb.inc
--- a/packages/hal/i386/pcmb/current/include/pcmb.inc
+++ b/packages/hal/i386/pcmb/current/include/pcmb.inc
@@ -214,9 +214,12 @@
 _endload:
 1:
 
-	/* Lets be nice and wait for the diskette drive motor to go off
-         * before continuing. */
+	/* Let's be nice and wait for the diskette drive motor to go off
+	 * before continuing.  To allow the BIOS timer interrupt handler
+	 * to switch off the drive, we need to make sure interrupts are
+	 * enabled. */
 	
+	sti
 	movw	$0x40, %ax
 	movw	%ax, %es
 	movl	$0x40, %ebx
diff --git a/packages/hal/misc/freescale/edma/current/ChangeLog b/packages/hal/misc/freescale/edma/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/misc/freescale/edma/current/ChangeLog
@@ -0,0 +1,67 @@
+2014-02-13  Ilija Kocho <ilijak@siva.com.mk>
+
+	* misc/freescale/edma/current/doc/edma.sgml
+	* misc/freescale/edma/current/doc/freescale_begin.sgml
+	* misc/freescale/edma/current/doc/freescale_end.sgml
+	New: Add Freescale eDMA to eCos reference manual.
+
+2013-08-26  Ilija Kocho <ilijak@siva.com.mk>
+
+	* include/freescale_edma.h: Fix FREESCALE_EDMA_NBYTES_MLOFFYES_NBYTES_M bug
+	[ Bugzilla 1001896 ]
+
+2013-05-04  Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/hal_freescale_edma.cdl: Remove requirement for WRITETHRU cache mode
+	that raised conflict when cache was disabled. Bug reported by Mike Jones.
+	[ Bugzilla 1001838 ]
+
+2013-04-01  Ilija Kocho <ilijak@siva.com.mk>
+
+	* src/hal_freescale_edma.c:	Add clock gating enable.
+
+2013-02-06  Stefan Singer <stefan.singer@freescale.com>
+		    Ilija Kocho <ilijak@siva.com.mk>
+
+	* include/freescale_edma.h src/hal_freescale_edma.c:	
+	enhanced endianness support for devices with big and little endian
+	added support for MPC5xxx in addition to Kinetis
+	(see Bugzilla 1001752).
+	
+2012-05-04  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_freescale_edma.cdl
+	* include/freescale_edma.h
+	* src/hal/freescale_edma.c
+	Add support for 32 channel eDMA [Bugzilla 1001579]
+
+2012-01-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+    * cdl/hal_freescale_edma.cdl
+	* include/freescale_edma.h
+	* src/hal/freescale_edma.c
+	New package -- Freescale eDMA DMA controller support [Bugzilla 1001450]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/packages/hal/misc/freescale/edma/current/cdl/hal_freescale_edma.cdl b/packages/hal/misc/freescale/edma/current/cdl/hal_freescale_edma.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/misc/freescale/edma/current/cdl/hal_freescale_edma.cdl
@@ -0,0 +1,146 @@
+##==========================================================================
+##
+##      hal_freescale_edma.cdl
+##
+##      Cortex-M Freescale Kinetis eDMA
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-12-11
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_FREESCALE_EDMA {
+    display "Freescale eDMA controller"
+    hardware
+
+    include_dir cyg/hal
+    compile hal_freescale_edma.c
+    
+    active_if CYGINT_HAL_DMA
+
+    cdl_option CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM {
+        display "Number of DMA channels"
+        flavor data
+        legal_values { 16 32 }
+        default_value 16
+    }
+
+    cdl_option CYGOPT_HAL_FREESCALE_EDMA_ERCA {
+        display "Round robin channel arbitration"
+        flavor bool
+        default_value 0
+    }
+
+    cdl_option CYGOPT_HAL_FREESCALE_EDMA_EMLM {
+        display "Enable minor loop mapping"
+        flavor bool
+        default_value 1
+    }
+
+    cdl_option CYGOPT_HAL_FREESCALE_EDMA_CLM {
+        display "Continuous link mode"
+        flavor bool
+        active_if CYGOPT_HAL_FREESCALE_EDMA_EMLM
+        default_value 0
+    }
+
+    cdl_option CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE {
+        display "Number of channels in DMA group"
+        flavor data
+        calculated  16
+    }
+
+    cdl_component CYGHWR_HAL_FREESCALE_EDMA_GROPS {
+        display "Groups"
+        flavor none
+        no_define
+        active_if { CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM >
+            CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE }
+
+        cdl_option CYGNUM_HAL_FREESCALE_EDMA_GROUP_NUM {
+            display "Number of DMA groups"
+            flavor data
+            calculated  { CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE ?
+                CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM /
+                CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE : 0}
+        }
+
+        cdl_option CYGNUM_HAL_FREESCALE_EDMA_GR0_PRIO {
+            display "Group 0 priority"
+            flavor data
+            legal_values 0 1
+            default_value 0
+        }
+
+        cdl_option CYGNUM_HAL_FREESCALE_EDMA_GR1_PRIO {
+            display "Group 1 priority"
+            flavor data
+            legal_values 0 1
+            calculated { CYGNUM_HAL_FREESCALE_EDMA_GR0_PRIO ? 0 : 1 }
+        }
+
+        cdl_option CYGOPT_HAL_FREESCALE_EDMA_ERGA {
+            display "Round robin group arbitration"
+            active_if { CYGNUM_HAL_FREESCALE_EDMA_GROUP_NUM > 1 }
+            flavor bool
+            default_value 0
+        }
+    }
+
+    cdl_option CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM {
+        display "Channels per DMAMUX"
+        flavor data
+        calculated 16
+    }
+
+    cdl_component CYGNUM_HAL_FREESCALE_DMAMUX_NUM {
+        display "Number of DMAMUX units"
+        flavor data
+        active_if { CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM >
+            CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM
+        }
+        calculated { CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM ?
+           ( CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM /
+            CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM ) : 0
+        }
+    }
+}
+
+# EOF hal_freescale_dma.cdl
diff --git a/packages/hal/misc/freescale/edma/current/doc/edma.sgml b/packages/hal/misc/freescale/edma/current/doc/edma.sgml
new file mode 100644
--- /dev/null
+++ b/packages/hal/misc/freescale/edma/current/doc/edma.sgml
@@ -0,0 +1,179 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     edma.sgml                                                -->
+<!--                                                                 -->
+<!--     EDMA          documentation.                             -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2014 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2014/02/12                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<!-- <part id="hal-freescale-edma"><title>Freescale eDMA Family Support</title> -->
+
+<refentry id="hal-freescale-edma">
+  <refmeta>
+    <refentrytitle>Freescale eDMA </refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname><literal>CYGPKG_HAL_FREESCALE_EDMA</literal></refname>
+    <refpurpose>eCos Support for Freescale eDMA Direct Memory Access controller</refpurpose>
+  </refnamediv>
+  
+  <refsect1 id="hal-freescale-edma-description"><title>Description</title>
+    <para>
+    <emphasis>eDMA</emphasis> is enhanced Direct Memory Access controller found on various Freescale
+    microcontroller families. It is combined with different architectures such as Power Architecture,
+    Coldfire/M68K, ARM, Cortex-M, etc.
+    </para>
+    <para>
+    The eDMA  HAL library provides generic support for module configuration and initialization as well as for executing of DMA transfers.
+    Most common usage of eDMA is as an enhancement of other device. eDMA acts as a cross-bar master and executes fast data
+    transfers on behalf of slave devices.
+    DMA can also perform memory to memory transfers on direct request by the application.
+    In following text the devices and applications 
+    that use DMA shall be referenced as <emphasis>[DMA] users</emphasis>.
+    </para>
+  </refsect1>
+  <refsect1 id="edma-config"><title>Configuration</title>
+    <para>The eDMA package <literal>CYGPKG_HAL_FREESCALE_EDMA</literal> is activated by implementing <literal>CYGINT_HAL_DMA</literal> interface.
+    The CDL provides configuration of DMA multiplexer, channel priorities and interrupt priorities.
+    For the systems with more than 16 channels also there is a provision for configuration of group priorities.
+    Please refer to CDL and eDMA reference manual for details of module operation.
+    </para>
+    <refsect2 id="edma-api"><title>eDMA API</title>
+      <refsect3 id="hal-freescale-edma-init-chanset">
+      <title>hal_freescale_edma_init_chanset</title>
+      <programlisting>
+      void hal_freescale_edma_init_chanset(cyghwr_hal_freescale_dma_set_t *inidat_p);
+      </programlisting>
+      <para>
+      Initialise <parameter>inidat_p</parameter> channel set. A channel set consists of
+      one or more DMA channels.
+      </para>
+      <para>
+      The initialisation parameters are provided by following structure:
+      <programlisting>
+      // DMA Channel set
+      typedef struct cyghwr_hal_freescale_dma_set_s {
+        cyghwr_hal_freescale_edma_t* edma_p;                // eDMA controller [register set]
+        const cyghwr_hal_freescale_dma_chan_set_t *chan_p;  // Channel configuration data
+        cyg_uint8 chan_n;                                   // Number of channels
+      } cyghwr_hal_freescale_dma_set_t;     
+      </programlisting>
+      
+      where:
+      
+      <structfield>chan_p</structfield> points to an array of
+      <structfield>chan_n</structfield> channels.
+      </para>
+      <para>
+      Channel configuration is provided by following structure.
+      <programlisting>
+      // DMA Channel data
+      typedef struct cyghwr_hal_freescale_dma_chan_set_s {
+        cyg_uint8 dma_src;      // Data source
+        cyg_uint8 dma_chan_i;   // Channel index
+        cyg_uint8 dma_prio;     // DMA channel priority
+        cyg_uint8 isr_prio;     // Interrupt priority
+        cyg_uint8 isr_num;      // Interrupt vector
+        cyg_uint8 isr_ena;      // Interruot enable
+      } cyghwr_hal_freescale_dma_chan_set_t;
+      </programlisting>
+      
+      The DMA channel priority <structfield>dma_chan_i</structfield> must be unique for every channel.
+      In order to satisfy this requirement the channel that previously had the given priority shall
+      be assigned with the previous prioruty of the target channel.
+      As a special (and most common case) <literal>FREESCALE_EDMA_DCHPRI_ASIS</literal> shall keep the
+      priority unchanged.
+      </para>
+      </refsect3>
+      
+      <refsect3 id="hal-freescale-edma-transfer-init">
+      <title>hal_freescale_edma_transfer_init</title>
+      <programlisting>
+      void hal_freescale_edma_transfer_init(cyghwr_hal_freescale_dma_set_t *inidat_p,
+                                            cyg_uint8 chan_i,
+                                            const cyghwr_hal_freescale_edma_tcd_t *tcd_cfg_p
+                                            );
+      </programlisting>
+      <para>
+      Initialise transfer. trannsfer on <parameter>chan_i</parameter> channel of
+      <parameter>edma_p</parameter> shall be initialised. with transfer control descriptor
+      <parameter>tcd_cfg_p</parameter>.
+      </para>
+      </refsect3>
+    
+      <refsect3 id="hal-freescale-edma-transfer-diag">
+      <title>hal_freescale_edma_transfer_diag</title>
+      <programlisting>
+      void hal_freescale_edma_transfer_diag(cyghwr_hal_freescale_edma_t
+                                      *edma_p, cyg_uint8 chan_i, cyg_bool recurse);
+      </programlisting>
+      <para>
+      Show contents of a transfer control descriptor set.
+      </para>
+      </refsect3>
+      
+      <refsect3 id="hal-freescale-edma-oper">
+      <title>eDMA operations</title>
+      <para>
+      Following inline functions and macros initiate or stop respective DMA operations.
+      </para>
+      <programlisting>
+      void hal_freescale_edma_erq_enable(cyghwr_hal_freescale_edma_t *edma_p,
+                                         cyg_uint8 chan_i);
+      void hal_freescale_edma_erq_disable(cyghwr_hal_freescale_edma_t *edma_p,
+                                          cyg_uint8 chan_i);
+      void hal_freescale_edma_erq_cleardone(cyghwr_hal_freescale_edma_t *edma_p,
+                                          cyg_uint8 chan_i);
+      void hal_freescale_edma_irq_enable(cyghwr_hal_freescale_edma_t *edma_p,
+                                          cyg_uint8 chan_i);
+      void hal_freescale_edma_irq_disable(cyghwr_hal_freescale_edma_t *edma_p,
+                                          cyg_uint8 chan_i);
+      void hal_freescale_edma_irq_clear(cyghwr_hal_freescale_edma_t *edma_p,
+                                          cyg_uint8 chan_i);
+      void hal_freescale_edma_transfer_clear(cyghwr_hal_freescale_edma_t *edma_p,
+                                          cyg_uint8 chan_i);
+      void hal_freescale_edma_transfer_start(cyghwr_hal_freescale_edma_t *edma_p,
+                                          cyg_uint8 chan_i);
+      
+      #define HAL_DMA_TRANSFER_STOP(__edma,__chan)  \
+              hal_freescale_edma_erq_disable(__edma, __chan)
+      #define HAL_DMA_TRANSFER_START(__edma,__chan) \
+              hal_freescale_edma_erq_enable(__edma, __chan)
+      #define HAL_DMA_TRANSFER_CLEAR(__edma,__chan) \
+              hal_freescale_edma_cleardone(__edma, __chan)
+      </programlisting>
+      </refsect3>
+    </refsect2>
+    </refsect1>
+    
+  </refentry>
+  
+  <!--</part>-->
diff --git a/packages/hal/misc/freescale/edma/current/doc/freescale_begin.sgml b/packages/hal/misc/freescale/edma/current/doc/freescale_begin.sgml
new file mode 100644
--- /dev/null
+++ b/packages/hal/misc/freescale/edma/current/doc/freescale_begin.sgml
@@ -0,0 +1,37 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     freescale_begin.sgml                                          -->
+<!--                                                                 -->
+<!--     Freescale documentation.                                      -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2014 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2014/02/19                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<part id="hal-misc-freescale"><title>Freescale Peripheral Collection Support</title>
diff --git a/packages/hal/misc/freescale/edma/current/doc/freescale_end.sgml b/packages/hal/misc/freescale/edma/current/doc/freescale_end.sgml
new file mode 100644
--- /dev/null
+++ b/packages/hal/misc/freescale/edma/current/doc/freescale_end.sgml
@@ -0,0 +1,37 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     freescale_end.sgml                                             -->
+<!--                                                                 -->
+<!--     Freescale documentation.                                      -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2014 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2014/02/19                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+</part>
diff --git a/packages/hal/misc/freescale/edma/current/include/freescale_edma.h b/packages/hal/misc/freescale/edma/current/include/freescale_edma.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/misc/freescale/edma/current/include/freescale_edma.h
@@ -0,0 +1,542 @@
+#ifndef CYGONCE_FREESCALE_EDMA_H
+#define CYGONCE_FREESCALE_EDMA_H
+//===========================================================================
+//
+//      freescale_edma.h
+//
+//      Freescale eDMA specific registers
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2011-11-04
+// Purpose:       Freescale eDMA specific registers
+// Description:
+// Usage:         #include <cyg/hal/freescale_edma.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+#include <pkgconf/hal.h>
+#if defined CYGHWR_HAL_EDMA_TCD_SECTION || defined CYGHWR_HAL_EDMA_MEM_SECTION
+# include <cyg/infra/cyg_type.h>
+#endif
+
+// ----------------------------------------------------------------------------
+// DMAMUX DMA Multiplexer
+
+// DMAMUX - Peripheral register structure
+typedef volatile struct cyghwr_hal_freescale_dmamux_s {
+    cyg_uint8 chcfg[CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM];   // Channel Configuration Register
+} cyghwr_hal_freescale_dmamux_t;
+
+// DMAMUX - Peripheral instance base addresses - defined in HAL (typically var_io_devs.h)
+// CYGHWR_IO_FREESCALE_DMAMUX0_P defined in HAL
+// CYGHWR_IO_FREESCALE_DMAMUX1_P defined in HAL
+
+
+// ----------------------------------------------------------------------------
+// DMAMUX Register Masks
+
+// CHCFG Bit Fields
+#define FREESCALE_DMAMUX_CHCFG_SOURCE_M      0x3F
+#define FREESCALE_DMAMUX_CHCFG_SOURCE(__val) \
+            (__val & FREESCALE_DMAMUX_CHCFG_SOURCE_M)
+#define FREESCALE_DMAMUX_CHCFG_TRIG_M        0x40
+#define FREESCALE_DMAMUX_CHCFG_TRIG_S        6
+#define FREESCALE_DMAMUX_CHCFG_ENBL_M        0x80
+#define FREESCALE_DMAMUX_CHCFG_ENBL_S        7
+#define FREESCALE_DMAMUX_CHCFG_ASIS          FREESCALE_DMAMUX_CHCFG_ENBL_M
+
+// DMAMUX DMA request sources
+// Provided by HAL (typically var_io_devs.h)
+#define FREESCALE_DMAMUX_SRC(__src) (_src)
+
+//---------------------------------------------------------------------------
+// eDMA
+
+// Transfer control descriptor
+typedef volatile struct cyghwr_hal_freescale_edma_tcd_s
+                           cyghwr_hal_freescale_edma_tcd_t;
+#define CYGBLD_FREESCALE_EDMA_TCD_ALIGN CYGBLD_ATTRIB_ALIGN(32)
+struct cyghwr_hal_freescale_edma_tcd_s {
+    volatile void* saddr;             //  Source Address
+
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+    cyg_uint16 attr;         //  Transfer Attributes
+    cyg_uint16 soff;         //  Signed Source Address Offset
+#else // AKA Little endian
+    cyg_uint16 soff;         //  Signed Source Address Offset
+    cyg_uint16 attr;         //  Transfer Attributes
+#endif
+
+    union {
+        cyg_uint32 mlno;     //  Minor Byte Count (Minor Loop Dis)
+        //  Signed Minor Loop Off:
+        cyg_uint32 mloffyes; //    MinoL Eena and Off Dis
+        cyg_uint32 mloffno;  //    Minor Loop and Off Ena
+    } nbytes;
+    cyg_uint32 slast;         //  Last Source Address Adjustment
+    volatile void *daddr;              //  Destination Address
+
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+
+    union {                   //  Current Minor Loop Link:
+        cyg_uint16 elinkyes;  //  Major Loop Count (Ch Lnkng Ena)
+        cyg_uint16 elinkno;   //  Major Loop Count (Ch Lnkng Dis)
+    } citer;
+    cyg_uint16 doff;          //  Signed Destination Address Offset
+#else // AKA Little endian
+    cyg_uint16 doff;          //  Signed Destination Address Offset
+    union {                   //  Current Minor Loop Link:
+        cyg_uint16 elinkyes;  //  Major Loop Count (Ch Lnkng Ena)
+        cyg_uint16 elinkno;   //  Major Loop Count (Ch Lnkng Dis)
+    } citer;
+#endif
+
+    union {
+        cyg_uint32 dlast;     //  Last Dst Addr Adj/Scat Gath Addr
+        cyghwr_hal_freescale_edma_tcd_t *sga;  //  Last Dst Addr Adj/Scat Gath Addr
+    } dlast_sga;
+
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+    union {                   //  Beginning Minor Loop Link:
+        cyg_uint16 elinkno;   //  Major Loop Cnt (Ch Lnkng Dis)
+        cyg_uint16 elinkyes;  //  Major Loop Cnt (Ch Lnkng Ena)
+    } biter;
+    cyg_uint16 csr;           //  Control and Status
+#else // AKA Little endian
+    cyg_uint16 csr;           //  Control and Status
+    union {                   //  Beginning Minor Loop Link:
+        cyg_uint16 elinkno;   //  Major Loop Cnt (Ch Lnkng Dis)
+        cyg_uint16 elinkyes;  //  Major Loop Cnt (Ch Lnkng Ena)
+    } biter;
+#endif
+};
+
+// DMA - Peripheral register structure
+typedef volatile struct cyghwr_hal_freescale_edma_s {
+    cyg_uint32 cr;                   // Control Register			// 0x0000
+    cyg_uint32 es;                   // Error Status Register			// 0x0004
+    cyg_uint32 reserved_0;							// 0x0008
+    cyg_uint32 erq;                  // Enable Request Register			// 0x000C
+    cyg_uint32 reserved_1;							// 0x0010
+    cyg_uint32 eei;                  // Enable Error Interrupt Register		// 0x0014
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+    cyg_uint8  serq;                 // Set Enable Request Register		// 0x0018
+    cyg_uint8  cerq;                 // Clear Enable Request Register		// 0x0019
+    cyg_uint8  seei;                 // Set Enable Error Interrupt Register	// 0x001A  
+    cyg_uint8  ceei;                 // Clear Enable Error Interrupt Register	// 0x001B
+    cyg_uint8  cint;                 // Clear Interrupt Request Register	// 0x001C
+    cyg_uint8  cerr;                 // Clear Error Register			// 0x001D
+    cyg_uint8  ssrt;                 // Set START Bit Register			// 0x001E
+    cyg_uint8  cdne;                 // Clear DONE Status Bit Register		// 0x001F
+#else // AKA Little endian
+    cyg_uint8  ceei;                 // Clear Enable Error Interrupt Register	
+    cyg_uint8  seei;                 // Set Enable Error Interrupt Register	
+    cyg_uint8  cerq;                 // Clear Enable Request Register		
+    cyg_uint8  serq;                 // Set Enable Request Register		
+    cyg_uint8  cdne;                 // Clear DONE Status Bit Register		
+    cyg_uint8  ssrt;                 // Set START Bit Register			
+    cyg_uint8  cerr;                 // Clear Error Register			
+    cyg_uint8  cint;                 // Clear Interrupt Request Register	
+#endif    
+    cyg_uint32 reserved_2;							// 0x0020
+    cyg_uint32 irq;                  // Interrupt Request Register		// 0x0024
+    cyg_uint32 reserved_3;							// 0x0028
+    cyg_uint32 err;                  // Error Register				// 0x002C
+    cyg_uint32 reserved_4;							// 0x0030
+    cyg_uint32 hrs;                  // Hardware Request Status Register	// 0x0034
+    cyg_uint8  reserved_5[0x8100 - (0x8034 + 4)];
+    cyg_uint8  dchpri[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM]; // Priorities
+    cyg_uint8  reserved_6[0x9000 - 0x8100 - CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM];
+    cyghwr_hal_freescale_edma_tcd_t
+          tcd[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM]; // Transfer control descriptors
+} cyghwr_hal_freescale_edma_t;
+
+// CYGHWR_IO_FREESCALE_EDMA0_P is defined by HAL
+// #define CYGHWR_IO_FREESCALE_EDMA0_P
+
+// ----------------------------------------------------------------------------
+//  DMA Register Bits
+
+// CR Bit Fields
+#define FREESCALE_EDMA_CR_EDBG_M                        0x2
+#define FREESCALE_EDMA_CR_EDBG_S                        1
+#define FREESCALE_EDMA_CR_ERCA_M                        0x4
+#define FREESCALE_EDMA_CR_ERCA_S                        2
+#define FREESCALE_EDMA_CR_ERGA_M                        0x8
+#define FREESCALE_EDMA_CR_ERGA_S                        3
+#define FREESCALE_EDMA_CR_HOE_M                         0x10
+#define FREESCALE_EDMA_CR_HOE_S                         4
+#define FREESCALE_EDMA_CR_HALT_M                        0x20
+#define FREESCALE_EDMA_CR_HALT_S                        5
+#define FREESCALE_EDMA_CR_CLM_M                         0x40
+#define FREESCALE_EDMA_CR_CLM_S                         6
+#define FREESCALE_EDMA_CR_EMLM_M                        0x80
+#define FREESCALE_EDMA_CR_EMLM_S                        7
+#define FREESCALE_EDMA_CR_ECX_M                         0x10000
+#define FREESCALE_EDMA_CR_ECX_S                         16
+#define FREESCALE_EDMA_CR_CX_M                          0x20000
+#define FREESCALE_EDMA_CR_CX_S                          17
+
+#define FREESCALE_EDMA_GR_PRI(_gr_, _pr_) VALUE_((8 + 2 * _gr_), (_pr_ & 0x3))
+
+// ES Bit Fields
+#define FREESCALE_EDMA_ES_DBE_M                         0x1
+#define FREESCALE_EDMA_ES_DBE_S                         0
+#define FREESCALE_EDMA_ES_SBE_M                         0x2
+#define FREESCALE_EDMA_ES_SBE_S                         1
+#define FREESCALE_EDMA_ES_SGE_M                         0x4
+#define FREESCALE_EDMA_ES_SGE_S                         2
+#define FREESCALE_EDMA_ES_NCE_M                         0x8
+#define FREESCALE_EDMA_ES_NCE_S                         3
+#define FREESCALE_EDMA_ES_DOE_M                         0x10
+#define FREESCALE_EDMA_ES_DOE_S                         4
+#define FREESCALE_EDMA_ES_DAE_M                         0x20
+#define FREESCALE_EDMA_ES_DAE_S                         5
+#define FREESCALE_EDMA_ES_SOE_M                         0x40
+#define FREESCALE_EDMA_ES_SOE_S                         6
+#define FREESCALE_EDMA_ES_SAE_M                         0x80
+#define FREESCALE_EDMA_ES_SAE_S                         7
+#define FREESCALE_EDMA_ES_ERRCHN_M                      0xF00
+#define FREESCALE_EDMA_ES_ERRCHN_S                      8
+#define FREESCALE_EDMA_ES_ERRCHN(__val)                 \
+            VALUE_(FREESCALE_EDMA_ES_ERRCHN_S, __val)
+#define FREESCALE_EDMA_ES_CPE_M                         0x4000
+#define FREESCALE_EDMA_ES_CPE_S                         14
+#define FREESCALE_EDMA_ES_GPE_M                         0x8000
+#define FREESCALE_EDMA_ES_GPE_S                         15
+#define FREESCALE_EDMA_ES_ECX_M                         0x10000
+#define FREESCALE_EDMA_ES_ECX_S                         16
+#define FREESCALE_EDMA_ES_VLD_M                         0x80000000
+#define FREESCALE_EDMA_ES_VLD_S                         31
+// ERQ Bit Fields
+#define FREESCALE_EDMA_ERQ(__rq)                        BIT(__rq)
+// EEI Bit Fields
+#define FREESCALE_EDMA_EEI(__rq)                        BIT(__rq)
+#define FREESCALE_EDMA_CHAN_M                           0x1F
+// CEEI Bit Fields
+#define FREESCALE_EDMA_CEEI_CEEI(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_CEEI_CAEE_M                      0x40
+#define FREESCALE_EDMA_CEEI_CAEE_S                      6
+#define FREESCALE_EDMA_CEEI_NOP_M                       0x80
+#define FREESCALE_EDMA_CEEI_NOP_S                       7
+// SEEI Bit Fields
+#define FREESCALE_EDMA_SEEI_SEEI(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_SEEI_SAEE_M                      0x40
+#define FREESCALE_EDMA_SEEI_SAEE_S                      6
+#define FREESCALE_EDMA_SEEI_NOP_M                       0x80
+#define FREESCALE_EDMA_SEEI_NOP_S                       7
+// CERQ Bit Fields
+#define FREESCALE_EDMA_CERQ_CERQ(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_CERQ_CAER_M                      0x40
+#define FREESCALE_EDMA_CERQ_CAER_S                      6
+#define FREESCALE_EDMA_CERQ_NOP_M                       0x80
+#define FREESCALE_EDMA_CERQ_NOP_S                       7
+// SERQ Bit Fields
+#define FREESCALE_EDMA_SERQ_SERQ(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_SERQ_SAER_M                      0x40
+#define FREESCALE_EDMA_SERQ_SAER_S                      6
+#define FREESCALE_EDMA_SERQ_NOP_M                       0x80
+#define FREESCALE_EDMA_SERQ_NOP_S                       7
+// CDNE Bit Fields
+#define FREESCALE_EDMA_CDNE_CDNE(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_CDNE_CADN_M                      0x40
+#define FREESCALE_EDMA_CDNE_CADN_S                      6
+#define FREESCALE_EDMA_CDNE_NOP_M                       0x80
+#define FREESCALE_EDMA_CDNE_NOP_S                       7
+// SSRT Bit Fields
+#define FREESCALE_EDMA_SSRT_SSRT(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_SSRT_SAST_M                      0x40
+#define FREESCALE_EDMA_SSRT_SAST_S                      6
+#define FREESCALE_EDMA_SSRT_NOP_M                       0x80
+#define FREESCALE_EDMA_SSRT_NOP_S                       7
+// CERR Bit Fields
+#define FREESCALE_EDMA_CERR_CERR(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_CERR_CAEI_M                      0x40
+#define FREESCALE_EDMA_CERR_CAEI_S                      6
+#define FREESCALE_EDMA_CERR_NOP_M                       0x80
+#define FREESCALE_EDMA_CERR_NOP_S                       7
+// CINT Bit Fields
+#define FREESCALE_EDMA_CINT_CINT(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_CINT_CAIR_M                      0x40
+#define FREESCALE_EDMA_CINT_CAIR_S                      6
+#define FREESCALE_EDMA_CINT_NOP_M                       0x80
+#define FREESCALE_EDMA_CINT_NOP_S                       7
+// INT Bit Fields
+#define FREESCALE_EDMA_INT(__ch)                        BIT(__ch)
+// ERR Bit Fields
+#define FREESCALE_EDMA_ERR(__ch)                        BIT(__ch)
+// HRS Bit Fields
+#define FREESCALE_EDMA_HRS(__ch)                        BIT(__ch)
+// DCHPRI Bit Fields
+
+#define FREESCALE_EDMA_DCHPRI_CHPRI_M                   0xF
+
+#define FREESCALE_EDMA_DCHPRI_CHPRI(__val)              \
+        (__val & FREESCALE_EDMA_DCHPRI_CHPRI_M)
+#define FREESCALE_EDMA_DCHPRI_DPA_M                     0x40
+#define FREESCALE_EDMA_DCHPRI_DPA_S                     6
+#define FREESCALE_EDMA_DCHPRI_ECP_M                     0x80
+#define FREESCALE_EDMA_DCHPRI_ECP_S                     7
+#define FREESCALE_EDMA_DCHPRI_ASIS                      0x20
+// SOFF Bit Fields
+#define FREESCALE_EDMA_SOFF_SOFF_M                      0xFFFF
+#define FREESCALE_EDMA_SOFF_SOFF(__val)                 \
+        (__val & FREESCALE_EDMA_SOFF_SOFF_M)
+// ATTR Bit Fields
+#define FREESCALE_EDMA_ATTR_DSIZE_M                     0x7
+#define FREESCALE_EDMA_ATTR_DSIZE(__val)                \
+        (__val & FREESCALE_EDMA_ATTR_DSIZE_M)
+#define FREESCALE_EDMA_ATTR_DMOD_M                      0xF8
+#define FREESCALE_EDMA_ATTR_DMOD_S                      3
+#define FREESCALE_EDMA_ATTR_DMOD(__val)                 \
+        VALUE_(FREESCALE_EDMA_ATTR_DMOD_S, __val)
+#define FREESCALE_EDMA_ATTR_SSIZE_M                     0x700
+#define FREESCALE_EDMA_ATTR_SSIZE_S                     8
+#define FREESCALE_EDMA_ATTR_SSIZE(__val)                \
+        VALUE_(FREESCALE_EDMA_ATTR_SSIZE_S, __val)
+#define FREESCALE_EDMA_ATTR_SMOD_M                      0xF800
+#define FREESCALE_EDMA_ATTR_SMOD_S                      11
+#define FREESCALE_EDMA_ATTR_SMOD(__val)                 \
+        VALUE_(FREESCALE_EDMA_ATTR_SMOD_S, __val)
+#define FREESCALE_EDMA_ATTR_SIZE_8       0
+#define FREESCALE_EDMA_ATTR_SIZE_16      1
+#define FREESCALE_EDMA_ATTR_SIZE_32      2
+#define FREESCALE_EDMA_ATTR_SIZE_16B     4
+// NBYTES_MLOFFNO Bit Fields
+#define FREESCALE_EDMA_NBYTES_MLOFFNO_NBYTES_M          0x3FFFFFFF
+#define FREESCALE_EDMA_NBYTES_MLOFFNO_NBYTES(__val)     \
+        (__val & FREESCALE_EDMA_NBYTES_MLOFFNO_NBYTES_M)
+#define FREESCALE_EDMA_NBYTES_MLOFFNO_DMLOE_M           0x40000000
+#define FREESCALE_EDMA_NBYTES_MLOFFNO_DMLOE_S           30
+#define FREESCALE_EDMA_NBYTES_MLOFFNO_SMLOE_M           0x80000000
+#define FREESCALE_EDMA_NBYTES_MLOFFNO_SMLOE_S           31
+// NBYTES_MLOFFYES Bit Fields
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_NBYTES_M         0x3FF
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_NBYTES(__val)    \
+        (__val & FREESCALE_EDMA_NBYTES_MLOFFYES_NBYTES_M)
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF_M          0x3FFFFC00
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF_S          10
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF(__val)     \
+        VALUE_(FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF_S, __val)
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_DMLOE_M          0x40000000
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_DMLOE_S          30
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_SMLOE_M          0x80000000
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_SMLOE_S          31
+// DOFF Bit Fields
+#define FREESCALE_EDMA_DOFF_DOFF_M                      0xFFFF
+#define FREESCALE_EDMA_DOFF_DOFF(__val) (__val & FREESCALE_EDMA_DOFF_DOFF_M)
+// CITER_ELINKYES Bit Fields
+#define FREESCALE_EDMA_CITER_ELINKYES_CITER_M           0x1FF
+#define FREESCALE_EDMA_CITER_ELINKYES_CITER(__val)      \
+            (__val & FREESCALE_EDMA_CITER_ELINKYES_CITER_M)
+#define FREESCALE_EDMA_CITER_ELINKYES_LINKCH_M          0x1E00
+#define FREESCALE_EDMA_CITER_ELINKYES_LINKCH_S          9
+#define FREESCALE_EDMA_CITER_ELINKYES_LINKCH(__val)     \
+            VALUE_(FREESCALE_EDMA_CITER_ELINKYES_LINKCH_S, __val)
+#define FREESCALE_EDMA_CITER_ELINKYES_ELINK_M           0x8000
+#define FREESCALE_EDMA_CITER_ELINKYES_ELINK_S           15
+// CITER_ELINKNO Bit Fields
+#define FREESCALE_EDMA_CITER_ELINKNO_CITER_M            0x7FFF
+#define FREESCALE_EDMA_CITER_ELINKNO_CITER(__val)       \
+            (__val & FREESCALE_EDMA_CITER_ELINKNO_CITER_M)
+#define FREESCALE_EDMA_CITER_ELINKNO_ELINK_M            0x8000
+#define FREESCALE_EDMA_CITER_ELINKNO_ELINK_S            15
+// CSR Bit Fields
+#define FREESCALE_EDMA_CSR_START_M                      0x1
+#define FREESCALE_EDMA_CSR_START_S                      0
+#define FREESCALE_EDMA_CSR_INTMAJOR_M                   0x2
+#define FREESCALE_EDMA_CSR_INTMAJOR_S                   1
+#define FREESCALE_EDMA_CSR_INTHALF_M                    0x4
+#define FREESCALE_EDMA_CSR_INTHALF_S                    2
+#define FREESCALE_EDMA_CSR_DREQ_M                       0x8
+#define FREESCALE_EDMA_CSR_DREQ_S                       3
+#define FREESCALE_EDMA_CSR_ESG_M                        0x10
+#define FREESCALE_EDMA_CSR_ESG_S                        4
+#define FREESCALE_EDMA_CSR_MAJORELINK_M                 0x20
+#define FREESCALE_EDMA_CSR_MAJORELINK_S                 5
+#define FREESCALE_EDMA_CSR_ACTIVE_M                     0x40
+#define FREESCALE_EDMA_CSR_ACTIVE_S                     6
+#define FREESCALE_EDMA_CSR_DONE_M                       0x80
+#define FREESCALE_EDMA_CSR_DONE_S                       7
+#define FREESCALE_EDMA_CSR_MAJORLINKCH_M                0xF00
+#define FREESCALE_EDMA_CSR_MAJORLINKCH_S                8
+#define FREESCALE_EDMA_CSR_MAJORLINKCH(__val)           \
+            VALUE_(FREESCALE_EDMA_CSR_MAJORLINKCH_S, __val)
+#define FREESCALE_EDMA_CSR_BWC_M                        0xC000
+#define FREESCALE_EDMA_CSR_BWC_S                        14
+#define FREESCALE_EDMA_CSR_BWC(__val)                   \
+        VALUE_(FREESCALE_EDMA_CSR_BWC_S, __val)
+#define FREESCALE_EDMA_CSR_BWC_0      0
+#define FREESCALE_EDMA_CSR_BWC_MEDIUM FREESCALE_EDMA_CSR_BWC(2)
+#define FREESCALE_EDMA_CSR_BWC_NICE   FREESCALE_EDMA_CSR_BWC(3)
+
+// BITER_ELINKNO Bit Fields
+#define FREESCALE_EDMA_BITER_ELINKNO_BITER_M            0x7FFF
+#define FREESCALE_EDMA_BITER_ELINKNO_BITER(__val)       \
+            (__val FREESCALE_EDMA_BITER_ELINKNO_BITER_M)
+#define FREESCALE_EDMA_BITER_ELINKNO_ELINK_M            0x8000
+#define FREESCALE_EDMA_BITER_ELINKNO_ELINK_S            15
+// BITER_ELINKYES Bit Fields
+#define FREESCALE_EDMA_BITER_ELINKYES_BITER_M           0x1FF
+#define FREESCALE_EDMA_BITER_ELINKYES_BITER(__val)      \
+            (__val & FREESCALE_EDMA_BITER_ELINKYES_BITER_M)
+#define FREESCALE_EDMA_BITER_ELINKYES_LINKCH_M          0x1E00
+#define FREESCALE_EDMA_BITER_ELINKYES_LINKCH_S          9
+#define FREESCALE_EDMA_BITER_ELINKYES_LINKCH(__val)     \
+            VALUE_(FREESCALE_EDMA_BITER_ELINKYES_LINKCH_S, __val)
+#define FREESCALE_EDMA_BITER_ELINKYES_ELINK_M           0x8000
+#define FREESCALE_EDMA_BITER_ELINKYES_ELINK_S           15
+
+// EDMA buffer descriptor memory section
+#ifdef CYGHWR_HAL_EDMA_TCD_SECTION
+# define EDMA_RAM_TCD_SECTION CYGBLD_ATTRIB_SECTION(CYGHWR_HAL_EDMA_TCD_SECTION)
+#else
+# define EDMA_RAM_MEM_SECTION
+#endif // CYGHWR_HAL_EDMA_MEM_SECTION
+
+// EDMA buffer memory section
+#ifdef CYGHWR_HAL_EDMA_BUF_SECTION
+# define EDMA_RAM_BUF_SECTION CYGBLD_ATTRIB_SECTION(CYGHWR_HAL_EDMA_BUF_SECTION)
+#else
+# define EDMA_RAM_BUF_SECTION
+#endif // CYGHWR_HAL_EDMA_BUF_SECTION
+
+//-----------------------------------------------------------------------------
+
+// DMA Channel data
+typedef struct cyghwr_hal_freescale_dma_chan_set_s {
+    cyg_uint8 dma_src;      // Data source
+    cyg_uint8 dma_chan_i;   // Channel index
+    cyg_uint8 dma_prio;     // DMA channel priority
+    cyg_uint8 isr_prio;     // Interrupt priority
+    cyg_uint8 isr_num;      // Interrupt vector
+    cyg_uint8 isr_ena;      // Interruot enable
+} cyghwr_hal_freescale_dma_chan_set_t;
+
+// DMA Channel set
+typedef struct cyghwr_hal_freescale_dma_set_s {
+    cyghwr_hal_freescale_edma_t* edma_p;
+    const cyghwr_hal_freescale_dma_chan_set_t *chan_p;
+    cyg_uint8 chan_n;
+} cyghwr_hal_freescale_dma_set_t;
+
+
+__externC void
+hal_freescale_edma_init_chanset(cyghwr_hal_freescale_dma_set_t *inidat_p);
+
+__externC void
+hal_freescale_edma_diag(const cyghwr_hal_freescale_dma_set_t *inidat_p, cyg_uint32 mask);
+
+__externC void
+hal_freescale_edma_transfer_init(cyghwr_hal_freescale_edma_t *edma_p,
+                                 cyg_uint8 chan_i,
+                                 const cyghwr_hal_freescale_edma_tcd_t *tcd_cfg_p);
+__externC void
+hal_freescale_edma_tcd_diag(cyghwr_hal_freescale_edma_tcd_t *tcd_p, cyg_int32 chan_i, const char *prefix);
+
+__externC void
+hal_freescale_edma_transfer_diag (cyghwr_hal_freescale_edma_t *edma_p,
+                                  cyg_uint8 chan_i, cyg_bool recurse);
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_erq_enable(cyghwr_hal_freescale_edma_t *edma_p,
+                              cyg_uint8 chan_i)
+{
+    edma_p->serq = chan_i;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_erq_disable(cyghwr_hal_freescale_edma_t *edma_p,
+                               cyg_uint8 chan_i)
+{
+    edma_p->cerq = chan_i;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_cleardone(cyghwr_hal_freescale_edma_t *edma_p,
+                              cyg_uint8 chan_i)
+{
+    edma_p->cdne = chan_i;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_irq_enable(cyghwr_hal_freescale_edma_t *edma_p,
+                              cyg_uint8 chan_i)
+{
+    edma_p->seei = chan_i;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_irq_disable(cyghwr_hal_freescale_edma_t *edma_p,
+                               cyg_uint8 chan_i)
+{
+    edma_p->ceei = chan_i;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_irq_clear(cyghwr_hal_freescale_edma_t *edma_p,
+                               cyg_uint8 chan_i)
+{
+    edma_p->cint = chan_i;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_transfer_clear(cyghwr_hal_freescale_edma_t *edma_p,
+                                  cyg_uint8 chan_i)
+{
+    edma_p->tcd[chan_i].csr &= ~FREESCALE_EDMA_CSR_DONE_M;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_transfer_start(cyghwr_hal_freescale_edma_t *edma_p,
+                                  cyg_uint8 chan_i)
+{
+    edma_p->ssrt = chan_i;
+}
+
+#define HAL_DMA_TRANSFER_STOP(__edma,__chan)   \
+        hal_freescale_edma_erq_disable(__edma, __chan)
+#define HAL_DMA_TRANSFER_START(__edma,__chan)  \
+        hal_freescale_edma_erq_enable(__edma, __chan)
+#define HAL_DMA_TRANSFER_CLEAR(__edma,__chan)  \
+        hal_freescale_edma_cleardone(__edma, __chan)
+
+// end of var_io_dma.h
+#endif // CYGONCE_FREESCALE_EDMA_H
diff --git a/packages/hal/misc/freescale/edma/current/src/hal_freescale_edma.c b/packages/hal/misc/freescale/edma/current/src/hal_freescale_edma.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/misc/freescale/edma/current/src/hal_freescale_edma.c
@@ -0,0 +1,359 @@
+//===========================================================================
+//
+//      hal_freescale_edma.c
+//
+//      Freescale eDMA support library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2011-11-04
+// Purpose:       Freescale eDMA specific functions
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_freescale_edma.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+#include <cyg/hal/freescale_edma.h>     // Freescale eDMA defs
+
+// Channel priority register indexing
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+
+#define EDMA_CHAN_PRIORITY_I(__chan_i) (__chan_i)
+
+#else  // AKA Big endian
+// Indices for cyghwr_hal_freescale_edma_t::dchpri[]
+enum {
+    FREESCALE_DMA_PRI_CH3,  FREESCALE_DMA_PRI_CH2,
+    FREESCALE_DMA_PRI_CH1,  FREESCALE_DMA_PRI_CH0,
+    FREESCALE_DMA_PRI_CH7,  FREESCALE_DMA_PRI_CH6,
+    FREESCALE_DMA_PRI_CH5,  FREESCALE_DMA_PRI_CH4,
+    FREESCALE_DMA_PRI_CH11, FREESCALE_DMA_PRI_CH10,
+    FREESCALE_DMA_PRI_CH9,  FREESCALE_DMA_PRI_CH8,
+    FREESCALE_DMA_PRI_CH15, FREESCALE_DMA_PRI_CH14,
+    FREESCALE_DMA_PRI_CH13, FREESCALE_DMA_PRI_CH12
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16
+    ,
+    FREESCALE_DMA_PRI_CH19, FREESCALE_DMA_PRI_CH18,
+    FREESCALE_DMA_PRI_CH17, FREESCALE_DMA_PRI_CH16,
+    FREESCALE_DMA_PRI_CH23, FREESCALE_DMA_PRI_CH22,
+    FREESCALE_DMA_PRI_CH21, FREESCALE_DMA_PRI_CH20,
+    FREESCALE_DMA_PRI_CH27, FREESCALE_DMA_PRI_CH26,
+    FREESCALE_DMA_PRI_CH25, FREESCALE_DMA_PRI_CH24,
+    FREESCALE_DMA_PRI_CH31, FREESCALE_DMA_PRI_CH30,
+    FREESCALE_DMA_PRI_CH29, FREESCALE_DMA_PRI_CH28
+#endif
+};
+
+const cyg_uint8 const PRICHAN_I[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM] =
+{
+    FREESCALE_DMA_PRI_CH0,  FREESCALE_DMA_PRI_CH1,
+    FREESCALE_DMA_PRI_CH2,  FREESCALE_DMA_PRI_CH3,
+    FREESCALE_DMA_PRI_CH4,  FREESCALE_DMA_PRI_CH5,
+    FREESCALE_DMA_PRI_CH6,  FREESCALE_DMA_PRI_CH7,
+    FREESCALE_DMA_PRI_CH8,  FREESCALE_DMA_PRI_CH9,
+    FREESCALE_DMA_PRI_CH10, FREESCALE_DMA_PRI_CH11,
+    FREESCALE_DMA_PRI_CH12, FREESCALE_DMA_PRI_CH13,
+    FREESCALE_DMA_PRI_CH14, FREESCALE_DMA_PRI_CH15
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE
+    ,
+    FREESCALE_DMA_PRI_CH16, FREESCALE_DMA_PRI_CH17,
+    FREESCALE_DMA_PRI_CH18, FREESCALE_DMA_PRI_CH19,
+    FREESCALE_DMA_PRI_CH20, FREESCALE_DMA_PRI_CH21,
+    FREESCALE_DMA_PRI_CH22, FREESCALE_DMA_PRI_CH23,
+    FREESCALE_DMA_PRI_CH24, FREESCALE_DMA_PRI_CH25,
+    FREESCALE_DMA_PRI_CH26, FREESCALE_DMA_PRI_CH27,
+    FREESCALE_DMA_PRI_CH28, FREESCALE_DMA_PRI_CH29,
+    FREESCALE_DMA_PRI_CH30, FREESCALE_DMA_PRI_CH31
+#endif
+};
+
+#define EDMA_CHAN_PRIORITY_I(__chan_i) (PRICHAN_I[__chan_i])
+
+#endif
+
+// Find an eDMA channel with given priority
+static volatile cyg_uint8*
+hal_freescale_edma_find_chan_with_pri(cyghwr_hal_freescale_edma_t *edma_p,
+                                 cyg_uint32 pri, cyg_uint32 group_i)
+{
+    volatile cyg_uint8 *chan_p;
+
+    for(chan_p = &edma_p->dchpri[group_i * CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE];
+        chan_p < &edma_p->dchpri[group_i * CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE +
+                                 CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE];
+        chan_p++)
+    {
+        if((*chan_p & FREESCALE_EDMA_DCHPRI_CHPRI_M) == pri) break;
+    }
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE
+    if(0 == group_i){
+        if(chan_p >= &edma_p->dchpri[CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE])
+            chan_p = NULL;
+    }
+#endif
+    if(chan_p >= &edma_p->dchpri[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM])
+        chan_p = NULL;
+
+    return chan_p;
+}
+
+// Initialize an eDMA channel
+// If DMA prority change is required than old priority is assigned to the channel
+// that before this call had requested priority.
+void
+hal_freescale_edma_init_1chan(
+                           cyghwr_hal_freescale_edma_t *edma_p,
+                           const cyghwr_hal_freescale_dma_chan_set_t *chan_p)
+{
+    cyg_uint8 oldprio;
+    cyghwr_hal_freescale_dmamux_t *dmamux_p;
+    volatile cyg_uint8 *prev_ch_reqprio_p; // Previous chan with req. prio.
+    volatile cyg_uint8 *chcfg_p;
+    cyg_uint32         group_i;
+
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE
+    dmamux_p = chan_p->dma_chan_i < CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM ?
+                                         CYGHWR_IO_FREESCALE_DMAMUX0_P :
+                                         CYGHWR_IO_FREESCALE_DMAMUX1_P;
+#else
+    dmamux_p = CYGHWR_IO_FREESCALE_DMAMUX0_P;
+#endif
+    chcfg_p = &dmamux_p->chcfg[chan_p->dma_chan_i % CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM];
+    edma_p->cerq = chan_p->dma_chan_i;
+
+    if(chan_p->dma_src & FREESCALE_DMAMUX_CHCFG_SOURCE_M) {
+        *chcfg_p = chan_p->dma_src;
+    } else if(!(chan_p->dma_src & FREESCALE_DMAMUX_CHCFG_ASIS)) {
+        *chcfg_p = 0;
+    }
+
+    if((chan_p->dma_prio != FREESCALE_EDMA_DCHPRI_ASIS) &&
+       (edma_p->dchpri[EDMA_CHAN_PRIORITY_I(chan_p->dma_chan_i)] != chan_p->dma_prio))
+    {
+        group_i = chan_p->dma_chan_i >= CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE ? 1 : 0;
+        if((prev_ch_reqprio_p =
+            hal_freescale_edma_find_chan_with_pri(edma_p, chan_p->dma_prio, group_i)))
+        {
+            oldprio = edma_p->dchpri[EDMA_CHAN_PRIORITY_I(chan_p->dma_chan_i)];
+            edma_p->dchpri[EDMA_CHAN_PRIORITY_I(chan_p->dma_chan_i)] = chan_p->dma_prio;
+            *prev_ch_reqprio_p = oldprio;
+        }
+    }
+}
+
+// Init DMA controller
+
+const cyg_uint32 FREESCALE_EDMA_CR_INI = 0
+#ifdef CYGOPT_HAL_FREESCALE_EDMA_EMLM
+       | FREESCALE_EDMA_CR_EMLM_M
+#endif
+#ifdef CYGOPT_HAL_FREESCALE_EDMA_CLM
+       | FREESCALE_EDMA_CR_CLM_M
+#endif
+#ifdef CYGOPT_HAL_FREESCALE_EDMA_ERCA
+       | FREESCALE_EDMA_CR_ERCA_M
+#endif
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16
+#ifdef CYGOPT_HAL_FREESCALE_EDMA_ERGA
+       | FREESCALE_EDMA_CR_ERGA_M
+#endif
+       | FREESCALE_EDMA_GR_PRI(0, CYGNUM_HAL_FREESCALE_EDMA_GR0_PRIO)
+       | FREESCALE_EDMA_GR_PRI(1, CYGNUM_HAL_FREESCALE_EDMA_GR1_PRIO)
+#endif
+      ;
+
+void
+hal_freescale_edma_init(cyghwr_hal_freescale_edma_t *edma_p)
+{
+    cyg_uint32 regval;
+    
+    CYGHWR_IO_CLOCK_ENABLE(CYGHWR_IO_FREESCALE_EDMA0_CLK);
+    CYGHWR_IO_CLOCK_ENABLE(CYGHWR_IO_FREESCALE_DMAMUX0_CLK);
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16
+    CYGHWR_IO_CLOCK_ENABLE(CYGHWR_IO_FREESCALE_DMAMUX1_CLK);
+#endif
+    regval = edma_p->cr;
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16
+    regval &= ~(FREESCALE_EDMA_GR_PRI(0, 3) | FREESCALE_EDMA_GR_PRI(1, 3));
+#endif
+    regval |= FREESCALE_EDMA_CR_INI;
+    edma_p->cr = regval;
+}
+
+// Initialize a set of DMA channels
+void
+hal_freescale_edma_init_chanset(cyghwr_hal_freescale_dma_set_t *inidat_p)
+{
+    cyghwr_hal_freescale_edma_t *edma_p;
+    const cyghwr_hal_freescale_dma_chan_set_t *chan_p;
+
+    edma_p = inidat_p->edma_p = CYGHWR_HAL_FREESCALE_EDMA0_P;
+
+    hal_freescale_edma_init(edma_p);
+
+    for(chan_p = inidat_p->chan_p;
+        chan_p < inidat_p->chan_p + inidat_p->chan_n;
+        chan_p++)
+    {
+        hal_freescale_edma_init_1chan(edma_p, chan_p);
+    }
+    edma_p->es = 0;
+}
+
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 32
+# define DMA_CHANMASK_FORMAT "0x%08x"
+#else
+# define DMA_CHANMASK_FORMAT "0x%04x"
+#endif
+
+#define EDMA_DIAG_PRINTF_FORMAT(__mf) "CR=0x%08x ES=0x%08x ERQ=" __mf \
+        " INT=" __mf " ERR=" __mf " HRS=" __mf "\n"
+
+// Display DMA configuration
+void
+hal_freescale_edma_diag(const cyghwr_hal_freescale_dma_set_t *inidat_p, cyg_uint32 mask)
+{
+    cyghwr_hal_freescale_edma_t *edma_p;
+    cyghwr_hal_freescale_dmamux_t *dmamux_p;
+    const cyghwr_hal_freescale_dma_chan_set_t *chan_p;
+    cyg_uint8 chan_i;
+    cyg_uint32 chan_p_i;
+
+    edma_p = inidat_p->edma_p;
+    diag_printf(EDMA_DIAG_PRINTF_FORMAT(DMA_CHANMASK_FORMAT),
+                edma_p->cr, edma_p->es,
+                edma_p->erq, edma_p->irq, edma_p->err, edma_p->hrs);
+
+    for(chan_i = 0; chan_i < CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM; chan_i++){
+        if(mask & 0x1){
+            chan_p = inidat_p->chan_p;
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE
+            dmamux_p = chan_i < CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM ?
+                                    CYGHWR_IO_FREESCALE_DMAMUX0_P :
+                                    CYGHWR_IO_FREESCALE_DMAMUX1_P;
+#else
+            dmamux_p = CYGHWR_IO_FREESCALE_DMAMUX0_P;
+#endif
+            diag_printf("Chan %2d: CHCFG=0x%02x (%2d) DCHPRI=0x%02x dmamux[%c]=%p", chan_i,
+                        dmamux_p->chcfg[chan_i % 16],
+                        FREESCALE_DMAMUX_CHCFG_SOURCE(dmamux_p->chcfg[chan_i % 16]),
+                        edma_p->dchpri[EDMA_CHAN_PRIORITY_I(chan_i)],
+                        CYGHWR_IO_FREESCALE_DMAMUX0_P == dmamux_p ? '0' : (
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE
+                        CYGHWR_IO_FREESCALE_DMAMUX1_P == dmamux_p ? '1' :
+#endif
+                        '?'), dmamux_p);
+            for(chan_p_i = 0; chan_p_i < inidat_p->chan_n; chan_p_i++){
+                if(chan_p->dma_chan_i == chan_i){
+                    diag_printf(" ISR_NUM=%2d[0x%02x] ISR_PRI=%3d[0x%02x]",
+                                chan_p->isr_num, chan_p->isr_num,
+                                chan_p->isr_prio, chan_p->isr_prio);
+                }
+                chan_p++;
+            }
+            diag_printf("\n");
+        }
+        mask >>= 1;
+    }
+}
+
+// Initialize eDMA channel TCD
+void
+hal_freescale_edma_transfer_init(cyghwr_hal_freescale_edma_t *edma_p,
+                                 cyg_uint8 chan_i,
+                                 const cyghwr_hal_freescale_edma_tcd_t *tcd_cfg_p)
+{
+    HAL_DMA_TRANSFER_CLEAR(edma_p, chan_i);
+    edma_p->tcd[chan_i] = *tcd_cfg_p;
+}
+
+// Show eDMA TCD
+void hal_freescale_edma_tcd_diag(cyghwr_hal_freescale_edma_tcd_t *tcd_p, cyg_int32 chan_i, const char *prefix)
+{
+    if(chan_i < 0) {
+        diag_printf("TCD %p chan %s:\n", tcd_p, prefix);
+        prefix = "";
+    } else {
+        diag_printf("%sTCD %p chan %d:\n", "", tcd_p, chan_i);
+    }
+
+        diag_printf("%s    saddr=%p soff=0x%04x, attr=0x%04x\n", prefix,
+                    tcd_p->saddr, tcd_p->soff, tcd_p->attr);
+        diag_printf("%s    daddr=%p doff=0x%04x\n", prefix,
+                    tcd_p->daddr, tcd_p->doff);
+        diag_printf("%s    nbytes=%d [0x%08x], slast=%d [0x%08x]\n", prefix,
+                    tcd_p->nbytes.mlno, tcd_p->nbytes.mlno,
+                    tcd_p->slast, tcd_p->slast);
+        diag_printf("%s    %s=%d [%p]\n", prefix,
+                    (tcd_p->csr & FREESCALE_EDMA_CSR_ESG_M) ? "sga" : "dlast",
+                    tcd_p->dlast_sga.dlast, tcd_p->dlast_sga.sga);
+        diag_printf("%s    biter = %d, citer = %d\n", prefix,
+                    tcd_p->biter.elinkno, tcd_p->citer.elinkno);
+        diag_printf("%s    CSR=0x%04x\n", prefix, tcd_p->csr);
+}
+
+// Show eDMA TCD set
+void hal_freescale_edma_transfer_diag(cyghwr_hal_freescale_edma_t
+                                      *edma_p, cyg_uint8 chan_i, cyg_bool recurse)
+{
+    cyghwr_hal_freescale_edma_tcd_t *tcd_p;
+    const char *prefix = "";
+
+    for(tcd_p = &edma_p->tcd[chan_i]; tcd_p; tcd_p = tcd_p->dlast_sga.sga){
+        hal_freescale_edma_tcd_diag(tcd_p, chan_i, prefix);
+        if(!(recurse && (tcd_p->csr & FREESCALE_EDMA_CSR_ESG_M)))
+            break;
+        prefix = "  ";
+    }
+}
+
+// end of freescale_dma.h
diff --git a/packages/hal/misc/ram/micron/cellularram/current/ChangeLog b/packages/hal/misc/ram/micron/cellularram/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/hal/misc/ram/micron/cellularram/current/ChangeLog
@@ -0,0 +1,36 @@
+2013-04-28  Ilija Kocho  <ilijak@siva.com.mk>
+
+	*cdl/ram_micron_cellularram.cdl: RAM size format changed to decimal.
+	[ Bugzilla 1001837 ]
+
+2012-01-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/ram_micron_cellularram.cdl
+	* include/ram_micron_cellularram.h
+	* src/ram_micron_cellularram.c:
+	New package -- Micron CellularRam [Bugzilla 1001450]
+
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/packages/hal/misc/ram/micron/cellularram/current/cdl/ram_micron_cellularram.cdl b/packages/hal/misc/ram/micron/cellularram/current/cdl/ram_micron_cellularram.cdl
new file mode 100644
--- /dev/null
+++ b/packages/hal/misc/ram/micron/cellularram/current/cdl/ram_micron_cellularram.cdl
@@ -0,0 +1,277 @@
+# ====================================================================
+#
+#      ram_micron_cellularram.cdl
+#
+#      RAM memory - Hardware support for Micron Cellularram
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 2011 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later
+## version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with eCos; if not, write to the Free Software Foundation, Inc.,
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+##
+## As a special exception, if other files instantiate templates or use
+## macros or inline functions from this file, or you compile this file
+## and link it with other works to produce a work based on this file,
+## this file does not by itself cause the resulting work to be covered by
+## the GNU General Public License. However the source code for this file
+## must still be made available in accordance with section (3) of the GNU
+## General Public License v2.
+##
+## This exception does not invalidate any other reasons why a work based
+## on this file might be covered by the GNU General Public License.
+## -------------------------------------------
+## ####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      ilijak
+# Contributors:
+# Date:           2011-10-05
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_RAM_MICRON_CELLULARRAM {
+    display       "Micron CellularRam 1.5 support"
+
+    parent        CYGPKG_HAL_EXTRN_MEMORY
+    active_if	  CYGPKG_HAL_EXTRN_MEMORY
+
+    include_dir   cyg/devs
+    compile       -library=libextras.a ram_micron_cellularram.c
+
+    description   "
+        RAM memory device support for Micron CellularRam 1.5
+        Micron CellularRam supports Asynchronous and Sybchronous/Burst bus
+        modes."
+
+    define_proc {
+        puts $::cdl_header "#include <pkgconf/system.h>";
+    }
+
+    cdl_interface CYGINT_DEVS_RAM0_MICRON_CELLULAR {
+    }
+
+    cdl_component CYGHWR_DEVS_RAM0_MICRON_CELLULAR {
+        display "Micron Cellular Ram 1.5 chip 0"
+        flavor bool
+        default_value CYGINT_DEVS_RAM0_MICRON_CELLULAR
+        no_define
+
+        active_if CYGINT_DEVS_RAM0_MICRON_CELLULAR
+
+        cdl_option CYGHWR_RAM0_MICRON_CELLULAR_SIZE {
+            display "RAM size \[Bytes\]"
+            flavor data
+            default_value 16 * 1024 * 1024
+        }
+        cdl_component CYGHWR_RAM0_MICRON_BCR_SETTO {
+            display "Bus Configuration Register"
+            flavor data
+
+            calculated {
+                0x0 +
+                ((CYGHWR_RAM0_MICRON_BCR_ASYNC == "ASYNC" ? 1 : 0) << 15) +
+                ((CYGHWR_RAM0_MICRON_BCR_IL == "VARIABLE" ? 0 : 1) << 14) +
+                ((CYGHWR_RAM0_MICRON_BCR_LC & 0x7) << 11)                 +
+                ((CYGHWR_RAM0_MICRON_BCR_WP == "HIGH"     ? 1 : 0) << 10) +
+                ((CYGHWR_RAM0_MICRON_BCR_WC == "1"        ? 1 : 0) << 8)  +
+
+                ((CYGHWR_RAM0_MICRON_BCR_DS == "FULL" ? 0 :
+                  CYGHWR_RAM0_MICRON_BCR_DS == "1/2"  ? 1 : 2) << 4)      +
+
+                ((CYGHWR_RAM0_MICRON_BCR_BW == "NOWRAP"   ? 1 : 0) << 3)  +
+
+                (CYGHWR_RAM0_MICRON_BCR_BL ==  4   ? 1 :
+                 CYGHWR_RAM0_MICRON_BCR_BL ==  8   ? 2 :
+                 CYGHWR_RAM0_MICRON_BCR_BL ==  16  ? 3 :
+                 CYGHWR_RAM0_MICRON_BCR_BL ==  32  ? 4 : 7)
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_ASYNC {
+                display "Asynchronous/Synchronous mode"
+                flavor data
+                no_define
+                default_value { "SYNC" }
+                legal_values { "SYNC" "ASYNC" }
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_IL {
+                display "Initial latency"
+                flavor data
+                no_define
+                default_value { "FIXED" }
+                legal_values { "VARIABLE" "FIXED" }
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_LC {
+                display "Latency code"
+                flavor data
+                no_define
+                default_value 2
+                legal_values { 2 3 4 5 6 8 }
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_WP {
+                display "Active WAIT polarity"
+                flavor data
+                no_define
+                default_value { "LOW" }
+                legal_values { "HIGH" "LOW" }
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_WC {
+                display "WAIT configuration"
+                flavor data
+                no_define
+                default_value 1
+                legal_values { 0 1 }
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_DS {
+                display "Drive strength"
+                flavor data
+                no_define
+                default_value { "FULL" }
+                legal_values { "FULL" "1/2" "1/4" }
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_BW {
+                display "Burst wrap"
+                flavor data
+                no_define
+                default_value { "NOWRAP" }
+                legal_values { "WRAP" "NOWRAP" }
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_BL {
+                display "Burst length"
+                flavor data
+                no_define
+                default_value { "PERMANENT" }
+                legal_values { 4 8 16 32 "PERMANENT" }
+            }
+        }
+    }
+
+    cdl_interface CYGINT_DEVS_RAM1_MICRON_CELLULAR {
+    }
+
+    cdl_component CYGHWR_DEVS_RAM1_MICRON_CELLULAR {
+        display "Micron Cellular Ram 1.5 chip 1"
+        flavor bool
+        default_value CYGINT_DEVS_RAM1_MICRON_CELLULAR
+        no_define
+
+        active_if CYGINT_DEVS_RAM1_MICRON_CELLULAR
+
+        cdl_option CYGHWR_RAM1_MICRON_CELLULAR_SIZE {
+            display "RAM size \[Bytes\]"
+            flavor data
+            default_value 0x00100000
+        }
+        cdl_component CYGHWR_RAM1_MICRON_BCR_SETTO {
+            display "Bus Configuration Register"
+            flavor data
+
+            calculated {
+                0x0 +
+                ((CYGHWR_RAM1_MICRON_BCR_ASYNC == "ASYNC" ? 1 : 0) << 15) +
+                ((CYGHWR_RAM1_MICRON_BCR_IL == "VARIABLE" ? 0 : 1) << 14) +
+                ((CYGHWR_RAM1_MICRON_BCR_LC & 0x7) << 11)                 +
+                ((CYGHWR_RAM1_MICRON_BCR_WP == "HIGH"     ? 1 : 0) << 10) +
+                ((CYGHWR_RAM1_MICRON_BCR_WC == "1"        ? 1 : 0) << 8)  +
+
+                ((CYGHWR_RAM1_MICRON_BCR_DS == "FULL" ? 0 :
+                  CYGHWR_RAM1_MICRON_BCR_DS == "1/2"  ? 1 : 2) << 4)      +
+
+                ((CYGHWR_RAM1_MICRON_BCR_BW == "NOWRAP"   ? 1 : 0) << 3)  +
+
+                (CYGHWR_RAM1_MICRON_BCR_BL ==  4   ? 1 :
+                 CYGHWR_RAM1_MICRON_BCR_BL ==  8   ? 2 :
+                 CYGHWR_RAM1_MICRON_BCR_BL ==  16  ? 3 :
+                 CYGHWR_RAM1_MICRON_BCR_BL ==  32  ? 4 : 7)
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_ASYNC {
+                display "Asynchronous/Synchronous mode"
+                flavor data
+                no_define
+                default_value { "SYNC" }
+                legal_values { "SYNC" "ASYNC" }
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_IL {
+                display "Initial latency"
+                flavor data
+                no_define
+                default_value { "FIXED" }
+                legal_values { "VARIABLE" "FIXED" }
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_LC {
+                display "Latency code"
+                flavor data
+                no_define
+                default_value 2
+                legal_values { 2 3 4 5 6 8 }
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_WP {
+                display "Active WAIT polarity"
+                flavor data
+                no_define
+                default_value { "LOW" }
+                legal_values { "HIGH" "LOW" }
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_WC {
+                display "WAIT configuration"
+                flavor data
+                no_define
+                default_value 1
+                legal_values { 0 1 }
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_DS {
+                display "Drive strength"
+                flavor data
+                no_define
+                default_value { "FULL" }
+                legal_values { "FULL" "1/2" "1/4" }
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_BW {
+                display "Burst wrap"
+                flavor data
+                no_define
+                default_value { "NOWRAP" }
+                legal_values { "WRAP" "NOWRAP" }
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_BL {
+                display "Burst length"
+                flavor data
+                no_define
+                default_value { "PERMANENT" }
+                legal_values { 4 8 16 32 "PERMANENT" }
+            }
+        }
+    }
+}
diff --git a/packages/hal/misc/ram/micron/cellularram/current/include/ram_micron_cellularram.h b/packages/hal/misc/ram/micron/cellularram/current/include/ram_micron_cellularram.h
new file mode 100644
--- /dev/null
+++ b/packages/hal/misc/ram/micron/cellularram/current/include/ram_micron_cellularram.h
@@ -0,0 +1,74 @@
+#ifndef CYGONCE_DEVS_RAM_MICRON_CELLULAR_H
+#define CYGONCE_DEVS_RAM_MICRON_CELLULAR_H
+//==========================================================================
+//
+//      ram_micron_cellularram.h
+//
+//      Micron CellularRam 1.5
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ilijak
+// Contributors:
+// Date:         2011-10-05
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/devs_ram_micron_cellularram.h>
+
+#define CYGHWR_DEVS_RAM_MICRON_RCR  0
+#define CYGHWR_DEVS_RAM_MICRON_BCR  1
+#define CYGHWR_DEVS_RAM_MICRON_DIDR 2
+
+#ifndef __ASSEMBLER__
+
+__externC cyg_uint16 ram_micron_reg_get(cyg_uint16 mem_reg_i,
+                                        volatile cyg_uint16 *ram_base_p,
+                                        cyg_uint32 ram_size);
+
+__externC void ram_micron_reg_set(cyg_uint16 mem_reg_i, cyg_uint16 setting,
+                                  volatile cyg_uint16 *ram_base_p,
+                                  cyg_uint32 ram_size);
+#endif
+
+#endif  // CYGONCE_DEVS_RAM_MICRON_CELLULAR_H
+// ------------------------------------------------------------------------
+// EOF ram_micron_cellularram.h
diff --git a/packages/hal/misc/ram/micron/cellularram/current/src/ram_micron_cellularram.c b/packages/hal/misc/ram/micron/cellularram/current/src/ram_micron_cellularram.c
new file mode 100644
--- /dev/null
+++ b/packages/hal/misc/ram/micron/cellularram/current/src/ram_micron_cellularram.c
@@ -0,0 +1,86 @@
+//==========================================================================
+//
+//      ram_micron_cellularram.c
+//
+//      Micron CellularRam 1.5 support functions.
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2011-02-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_arch.h>           // HAL header
+
+#include <cyg/devs/ram_micron_cellularram.h>
+
+cyg_uint16 ram_micron_reg_get(cyg_uint16 mem_reg_i,
+                              volatile cyg_uint16 *mem_base_p,
+                              cyg_uint32 ram_size)
+{
+    mem_base_p +=  (ram_size/2) - 1;
+    cyg_uint16 reg_val __attribute__((unused));
+
+    reg_val = *mem_base_p;
+    reg_val = *mem_base_p;
+    *mem_base_p = mem_reg_i;
+    mem_reg_i = *mem_base_p;
+    reg_val = mem_base_p[-16];
+    return mem_reg_i;
+}
+
+void ram_micron_reg_set(cyg_uint16 mem_reg_i, cyg_uint16 setting,
+                       volatile cyg_uint16 *mem_base_p, cyg_uint32 ram_size)
+{
+    mem_base_p += (ram_size/2) - 1;
+    cyg_uint16 reg_val __attribute__((unused));
+
+    reg_val = *mem_base_p;
+    reg_val = *mem_base_p;
+    *mem_base_p = mem_reg_i;
+    *mem_base_p = setting;
+    reg_val = mem_base_p[-16];
+}
+
+//==========================================================================
+// EOF ram_micron_cellularram.c
diff --git a/packages/hal/openrisc/arch/current/ChangeLog b/packages/hal/openrisc/arch/current/ChangeLog
--- a/packages/hal/openrisc/arch/current/ChangeLog
+++ b/packages/hal/openrisc/arch/current/ChangeLog
@@ -1,3 +1,8 @@
+2011-01-02  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/hal_openrisc.cdl: Eliminate some warnings. [ Bugzilla
+	1001083 ]
+
 2004-04-22  Jani Monoses <jani@iv.ro>
 
 	 * cdl/hal_openrisc.cdl :
diff --git a/packages/hal/openrisc/arch/current/cdl/hal_openrisc.cdl b/packages/hal/openrisc/arch/current/cdl/hal_openrisc.cdl
--- a/packages/hal/openrisc/arch/current/cdl/hal_openrisc.cdl
+++ b/packages/hal/openrisc/arch/current/cdl/hal_openrisc.cdl
@@ -89,7 +89,7 @@ cdl_package CYGPKG_HAL_OPENRISC {
 
     make {
         <PREFIX>/lib/target.ld: <PACKAGE>/src/openrisc.ld
-        $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
+        $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -o $@ $<
         @echo $@ ": \\" > $(notdir $@).deps
         @tail -n +2 target.tmp >> $(notdir $@).deps
         @echo >> $(notdir $@).deps
diff --git a/packages/hal/powerpc/arch/current/ChangeLog b/packages/hal/powerpc/arch/current/ChangeLog
--- a/packages/hal/powerpc/arch/current/ChangeLog
+++ b/packages/hal/powerpc/arch/current/ChangeLog
@@ -1,3 +1,14 @@
+2014-03-20  John Dallaway  <john@dallaway.org.uk>
+
+	* src/mcount.S: Add mcount functions for call-graph profiling.
+	* cdl/hal_powerpc.cdl: Add option to build mcount functions.
+	[ Bugzilla 1001961 ]
+
+2011-01-02  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/hal_powerpc.cdl: Eliminate some warnings. [ Bugzilla
+	1001083 ]
+
 2009-08-07  Nick Garnett  <nickg@ecoscentric.com>
 
 	* cdl/hal_powerpc.cdl: Add CYGHWR_HAL_POWERPC_BOOK_E_FIXED_VECTORS
@@ -1941,7 +1952,7 @@ Mon Aug 17 16:23:46 1998  Jesper Skov  <
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2006, 2007, 2008 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2006, 2007, 2008, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/hal/powerpc/arch/current/cdl/hal_powerpc.cdl b/packages/hal/powerpc/arch/current/cdl/hal_powerpc.cdl
--- a/packages/hal/powerpc/arch/current/cdl/hal_powerpc.cdl
+++ b/packages/hal/powerpc/arch/current/cdl/hal_powerpc.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2007 Free Software Foundation, Inc.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2007, 2014 Free Software Foundation, Inc.
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -41,7 +41,7 @@
 #
 # Author(s):      jskov
 # Original data:  bartv
-# Contributors:
+# Contributors:   jld
 # Date:           1999-11-02
 #
 #####DESCRIPTIONEND####
@@ -66,6 +66,8 @@ cdl_package CYGPKG_HAL_POWERPC {
         requires 1 == CYGINT_HAL_POWERPC_VARIANT
     }
 
+    implements    CYGINT_PROFILE_HAL_MCOUNT
+
     compile       hal_misc.c context.S ppc_stub.c hal_intr.c
 
     # The "-o file" is a workaround for CR100958 - without it the
@@ -73,7 +75,7 @@ cdl_package CYGPKG_HAL_POWERPC {
     # n.b. grep does not behave itself under win32
     make -priority 1 {
         <PREFIX>/include/cyg/hal/ppc_offsets.inc : <PACKAGE>/src/hal_mk_defs.c
-        $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,ppc_offsets.tmp -o hal_mk_defs.tmp -S $<
+        $(CC) $(ACTUAL_CFLAGS) $(INCLUDE_PATH) -Wp,-MD,ppc_offsets.tmp -o hal_mk_defs.tmp -S $<
         fgrep .equ hal_mk_defs.tmp | sed s/#// > $@
         @echo $@ ": \\" > $(notdir $@).deps
         @tail -n +2 ppc_offsets.tmp >> $(notdir $@).deps
@@ -92,7 +94,7 @@ cdl_package CYGPKG_HAL_POWERPC {
 
     make {
         <PREFIX>/lib/target.ld: <PACKAGE>/src/powerpc.ld
-        $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
+        $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -o $@ $<
         @echo $@ ": \\" > $(notdir $@).deps
         @tail -n +2 target.tmp >> $(notdir $@).deps
         @echo >> $(notdir $@).deps
@@ -253,6 +255,18 @@ cdl_package CYGPKG_HAL_POWERPC {
         }
     }
 
+    cdl_option CYGBLD_HAL_POWERPC_MCOUNT {
+        display           "Support call-graph profiling"
+        flavor            bool
+        no_define
+        active_if         CYGPKG_PROFILE_GPROF
+        calculated        CYGPKG_PROFILE_CALLGRAPH
+        compile           mcount.S
+        description       "
+            Calculate whether mcount functions should be built
+            to support call-graph profiling."
+    }
+
     cdl_option CYGBLD_LINKER_SCRIPT {
         display "Linker script"
         flavor data
diff --git a/packages/hal/powerpc/arch/current/src/mcount.S b/packages/hal/powerpc/arch/current/src/mcount.S
new file mode 100644
--- /dev/null
+++ b/packages/hal/powerpc/arch/current/src/mcount.S
@@ -0,0 +1,124 @@
+/*==========================================================================
+//
+//      mcount.S
+//
+//      PowerPC mcount implementation
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2014 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):       jld
+// Contributor(s):  
+// Date:            2014-03-20
+// Description:     This file provides mcount functions used for
+//                  call-graph profiling.
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#include <cyg/hal/arch.inc>
+
+/*
+// GCC inserts mcount code at the start of every function when compiling
+// with "-pg". For GCC targeting PowerPC, the following code is inserted:
+//
+//   mflr r0
+//   stw r0, 4(r1)
+//   bl _mcount
+//
+// We provide an implementation of _mcount() to call the eCos
+// __profile_mcount() function.
+*/
+
+        .section ".text.mcount"
+        .globl _mcount
+_mcount:
+        // create stack frame
+        stwu r1, -48(r1)
+
+        // caller assumes r3-r10 will be preserved and we use r14
+        stw r3, 8(r1)
+        stw r4, 12(r1)
+        stw r5, 16(r1)
+        stw r6, 20(r1)
+        stw r7, 24(r1)
+        stw r8, 28(r1)
+        stw r9, 32(r1)
+        stw r10, 36(r1)
+        stw r14, 40(r1)
+
+        // set up parameters for __profile_mcount() and preserve
+        // lr across our __profile_mcount() call
+        lwz r3, 52(r1)
+        subi r3, r3, 2
+        mflr r4
+        stw r4, 44(r1)
+
+        // disable interrupts
+        lwi r0, ~CYGARC_REG_MSR_INTBITS
+        mfmsr r14
+        and r0, r0, r14
+        mtmsr r0
+
+        // call eCos __profile_mcount()
+        // r14 is preserved across the call per EABI standard
+        bl __profile_mcount
+
+        // restore interrupts
+        mtmsr r14
+
+        // restore registers
+        lwz r3, 8(r1)
+        lwz r4, 12(r1)
+        lwz r5, 16(r1)
+        lwz r6, 20(r1)
+        lwz r7, 24(r1)
+        lwz r8, 28(r1)
+        lwz r9, 32(r1)
+        lwz r10, 36(r1)
+        lwz r14, 40(r1)
+
+        // unwind stack frame and return
+        lwz r0, 44(r1)
+        mtctr r0
+        lwz r0, 52(r1)
+        mtlr r0
+        addi r1, r1, 48
+        bctr
+
+//==========================================================================
+// end of mcount.S
diff --git a/packages/hal/powerpc/moab/current/ChangeLog b/packages/hal/powerpc/moab/current/ChangeLog
--- a/packages/hal/powerpc/moab/current/ChangeLog
+++ b/packages/hal/powerpc/moab/current/ChangeLog
@@ -1,3 +1,15 @@
+2011-07-22  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* misc/moab1.1_redboot_BOOT.ecm:
+	* misc/moab1.1_redboot_RAMF.ecm:
+	* misc/moab1.1_redboot_ROMRAM.ecm:
+	* misc/redboot_BOOT.ecm:
+	* misc/redboot_RAM.ecm:
+	* misc/redboot_RAM+FLASH.ecm:
+	* misc/redboot_ROMRAM.ecm:
+	Update due renaming CYGHWR_DEVS_ETH_PHY_DP83847 to
+	CYGHWR_DEVS_ETH_PHY_DP8384X. [ Bugzilla 1001235 ]
+
 2009-01-31  Bart Veer <bartv@ecoscentric.com>
 
 	* cdl/hal_powerpc_moab.cdl: update compiler flags for gcc 4.x
diff --git a/packages/hal/powerpc/moab/current/misc/moab1.1_redboot_BOOT.ecm b/packages/hal/powerpc/moab/current/misc/moab1.1_redboot_BOOT.ecm
--- a/packages/hal/powerpc/moab/current/misc/moab1.1_redboot_BOOT.ecm
+++ b/packages/hal/powerpc/moab/current/misc/moab1.1_redboot_BOOT.ecm
@@ -50,7 +50,7 @@ cdl_option CYGSEM_IO_ETH_DRIVERS_WARN {
     user_value 0
 };
 
-cdl_option CYGHWR_DEVS_ETH_PHY_DP83847 {
+cdl_option CYGHWR_DEVS_ETH_PHY_DP8384X {
     inferred_value 1
 };
 
diff --git a/packages/hal/powerpc/moab/current/misc/moab1.1_redboot_RAMF.ecm b/packages/hal/powerpc/moab/current/misc/moab1.1_redboot_RAMF.ecm
--- a/packages/hal/powerpc/moab/current/misc/moab1.1_redboot_RAMF.ecm
+++ b/packages/hal/powerpc/moab/current/misc/moab1.1_redboot_RAMF.ecm
@@ -41,7 +41,7 @@ cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS 
     inferred_value 0
 };
 
-cdl_option CYGHWR_DEVS_ETH_PHY_DP83847 {
+cdl_option CYGHWR_DEVS_ETH_PHY_DP8384X {
     inferred_value 1
 };
 
diff --git a/packages/hal/powerpc/moab/current/misc/moab1.1_redboot_ROMRAM.ecm b/packages/hal/powerpc/moab/current/misc/moab1.1_redboot_ROMRAM.ecm
--- a/packages/hal/powerpc/moab/current/misc/moab1.1_redboot_ROMRAM.ecm
+++ b/packages/hal/powerpc/moab/current/misc/moab1.1_redboot_ROMRAM.ecm
@@ -50,7 +50,7 @@ cdl_option CYGSEM_IO_ETH_DRIVERS_WARN {
     user_value 0
 };
 
-cdl_option CYGHWR_DEVS_ETH_PHY_DP83847 {
+cdl_option CYGHWR_DEVS_ETH_PHY_DP8384X {
     inferred_value 1
 };
 
diff --git a/packages/hal/powerpc/moab/current/misc/redboot_BOOT.ecm b/packages/hal/powerpc/moab/current/misc/redboot_BOOT.ecm
--- a/packages/hal/powerpc/moab/current/misc/redboot_BOOT.ecm
+++ b/packages/hal/powerpc/moab/current/misc/redboot_BOOT.ecm
@@ -50,7 +50,7 @@ cdl_option CYGSEM_IO_ETH_DRIVERS_WARN {
     user_value 0
 };
 
-cdl_option CYGHWR_DEVS_ETH_PHY_DP83847 {
+cdl_option CYGHWR_DEVS_ETH_PHY_DP8384X {
     inferred_value 1
 };
 
diff --git a/packages/hal/powerpc/moab/current/misc/redboot_RAM+FLASH.ecm b/packages/hal/powerpc/moab/current/misc/redboot_RAM+FLASH.ecm
--- a/packages/hal/powerpc/moab/current/misc/redboot_RAM+FLASH.ecm
+++ b/packages/hal/powerpc/moab/current/misc/redboot_RAM+FLASH.ecm
@@ -41,7 +41,7 @@ cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS 
     inferred_value 0
 };
 
-cdl_option CYGHWR_DEVS_ETH_PHY_DP83847 {
+cdl_option CYGHWR_DEVS_ETH_PHY_DP8384X {
     inferred_value 1
 };
 
diff --git a/packages/hal/powerpc/moab/current/misc/redboot_RAM.ecm b/packages/hal/powerpc/moab/current/misc/redboot_RAM.ecm
--- a/packages/hal/powerpc/moab/current/misc/redboot_RAM.ecm
+++ b/packages/hal/powerpc/moab/current/misc/redboot_RAM.ecm
@@ -39,7 +39,7 @@ cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS 
     inferred_value 0
 };
 
-cdl_option CYGHWR_DEVS_ETH_PHY_DP83847 {
+cdl_option CYGHWR_DEVS_ETH_PHY_DP8384X {
     inferred_value 1
 };
 
diff --git a/packages/hal/powerpc/moab/current/misc/redboot_ROMRAM.ecm b/packages/hal/powerpc/moab/current/misc/redboot_ROMRAM.ecm
--- a/packages/hal/powerpc/moab/current/misc/redboot_ROMRAM.ecm
+++ b/packages/hal/powerpc/moab/current/misc/redboot_ROMRAM.ecm
@@ -47,7 +47,7 @@ cdl_option CYGSEM_IO_ETH_DRIVERS_WARN {
     user_value 0
 };
 
-cdl_option CYGHWR_DEVS_ETH_PHY_DP83847 {
+cdl_option CYGHWR_DEVS_ETH_PHY_DP8384X {
     inferred_value 1
 };
 
diff --git a/packages/hal/sh/arch/current/ChangeLog b/packages/hal/sh/arch/current/ChangeLog
--- a/packages/hal/sh/arch/current/ChangeLog
+++ b/packages/hal/sh/arch/current/ChangeLog
@@ -1,3 +1,7 @@
+2011-01-02  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/hal_sh.cdl: Eliminate some warnings. [ Bugzilla 1001083 ]
+
 2009-02-04  John Dallaway  <john@dallaway.org.uk>
 
 	* src/sh.ld: Process *(.gcc_except_table.*) as for i386
diff --git a/packages/hal/sh/arch/current/cdl/hal_sh.cdl b/packages/hal/sh/arch/current/cdl/hal_sh.cdl
--- a/packages/hal/sh/arch/current/cdl/hal_sh.cdl
+++ b/packages/hal/sh/arch/current/cdl/hal_sh.cdl
@@ -67,7 +67,7 @@ cdl_package CYGPKG_HAL_SH {
     # n.b. grep does not behave itself under win32
     make -priority 1 {
         <PREFIX>/include/cyg/hal/sh_offsets.inc : <PACKAGE>/src/hal_mk_defs.c
-        $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh_offsets.tmp -o hal_mk_defs.tmp -S $<
+        $(CC) $(ACTUAL_CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh_offsets.tmp -o hal_mk_defs.tmp -S $<
         fgrep .equ hal_mk_defs.tmp | sed s/#// > $@
         @echo $@ ": \\" > $(notdir $@).deps
         @tail -n +2 sh_offsets.tmp >> $(notdir $@).deps
@@ -86,7 +86,7 @@ cdl_package CYGPKG_HAL_SH {
 
     make {
         <PREFIX>/lib/target.ld: <PACKAGE>/src/sh.ld
-        $(CC) -E -P -Wp,-MD,target.tmp -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
+        $(CC) -E -P -Wp,-MD,target.tmp -xc $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -o $@ $<
         @echo $@ ": \\" > $(notdir $@).deps
         @tail -n +2 target.tmp >> $(notdir $@).deps
         @echo >> $(notdir $@).deps
diff --git a/packages/hal/sh/sh2/current/ChangeLog b/packages/hal/sh/sh2/current/ChangeLog
--- a/packages/hal/sh/sh2/current/ChangeLog
+++ b/packages/hal/sh/sh2/current/ChangeLog
@@ -1,3 +1,8 @@
+2011-01-02  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/hal_sh_sh2.cdl: Eliminate some warnings. [ Bugzilla
+	1001083 ]
+
 2004-04-22  Jani Monoses <jani@iv.ro>
 
 	 * cdl/hal_sh_sh2.cdl :
diff --git a/packages/hal/sh/sh2/current/cdl/hal_sh_sh2.cdl b/packages/hal/sh/sh2/current/cdl/hal_sh_sh2.cdl
--- a/packages/hal/sh/sh2/current/cdl/hal_sh_sh2.cdl
+++ b/packages/hal/sh/sh2/current/cdl/hal_sh_sh2.cdl
@@ -74,7 +74,7 @@ cdl_package CYGPKG_HAL_SH_SH2 {
     # n.b. grep does not behave itself under win32
     make -priority 1 {
         <PREFIX>/include/cyg/hal/sh2_offsets.inc : <PACKAGE>/src/var_mk_defs.c
-        $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh2_offsets.tmp -o var_mk_defs.tmp -S $<
+        $(CC) $(ACTUAL_CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh2_offsets.tmp -o var_mk_defs.tmp -S $<
         fgrep .equ var_mk_defs.tmp | sed s/#// > $@
         @echo $@ ": \\" > $(notdir $@).deps
         @tail -n +2 sh2_offsets.tmp >> $(notdir $@).deps
diff --git a/packages/hal/sh/sh3/current/ChangeLog b/packages/hal/sh/sh3/current/ChangeLog
--- a/packages/hal/sh/sh3/current/ChangeLog
+++ b/packages/hal/sh/sh3/current/ChangeLog
@@ -1,3 +1,8 @@
+2011-01-02  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/hal_sh_sh3.cdl: Eliminate some warnings. [ Bugzilla
+	1001083 ]
+
 2004-04-22  Jani Monoses <jani@iv.ro>
 
 	 * cdl/hal_sh_sh3.cdl :
diff --git a/packages/hal/sh/sh3/current/cdl/hal_sh_sh3.cdl b/packages/hal/sh/sh3/current/cdl/hal_sh_sh3.cdl
--- a/packages/hal/sh/sh3/current/cdl/hal_sh_sh3.cdl
+++ b/packages/hal/sh/sh3/current/cdl/hal_sh_sh3.cdl
@@ -72,7 +72,7 @@ cdl_package CYGPKG_HAL_SH_SH3 {
     # n.b. grep does not behave itself under win32
     make -priority 1 {
         <PREFIX>/include/cyg/hal/sh3_offsets.inc : <PACKAGE>/src/var_mk_defs.c
-        $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh3_offsets.tmp -o var_mk_defs.tmp -S $<
+        $(CC) $(ACTUAL_CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh3_offsets.tmp -o var_mk_defs.tmp -S $<
         fgrep .equ var_mk_defs.tmp | sed s/#// > $@
         @echo $@ ": \\" > $(notdir $@).deps
         @tail -n +2 sh3_offsets.tmp >> $(notdir $@).deps
diff --git a/packages/hal/sh/sh4/current/ChangeLog b/packages/hal/sh/sh4/current/ChangeLog
--- a/packages/hal/sh/sh4/current/ChangeLog
+++ b/packages/hal/sh/sh4/current/ChangeLog
@@ -1,3 +1,8 @@
+2011-01-02  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/hal_sh_sh4.cdl: Eliminate some warnings. [ Bugzilla
+	1001083 ]
+
 2005-05-13  Hajime Ishitani <pigmon@mail.snd.co.jp>
 
 	* include/mod_regs_cpg.h :
diff --git a/packages/hal/sh/sh4/current/cdl/hal_sh_sh4.cdl b/packages/hal/sh/sh4/current/cdl/hal_sh_sh4.cdl
--- a/packages/hal/sh/sh4/current/cdl/hal_sh_sh4.cdl
+++ b/packages/hal/sh/sh4/current/cdl/hal_sh_sh4.cdl
@@ -75,7 +75,7 @@ cdl_package CYGPKG_HAL_SH_SH4 {
     # n.b. grep does not behave itself under win32
     make -priority 1 {
         <PREFIX>/include/cyg/hal/sh4_offsets.inc : <PACKAGE>/src/var_mk_defs.c
-        $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh4_offsets.tmp -o var_mk_defs.tmp -S $<
+        $(CC) $(ACTUAL_CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh4_offsets.tmp -o var_mk_defs.tmp -S $<
         fgrep .equ var_mk_defs.tmp | sed s/#// > $@
         @echo $@ ": \\" > $(notdir $@).deps
         @tail -n +2 sh4_offsets.tmp >> $(notdir $@).deps
diff --git a/packages/hal/sparc/arch/current/ChangeLog b/packages/hal/sparc/arch/current/ChangeLog
--- a/packages/hal/sparc/arch/current/ChangeLog
+++ b/packages/hal/sparc/arch/current/ChangeLog
@@ -1,3 +1,7 @@
+2011-01-02  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/hal_sparc.cdl: Eliminate some warnings. [ Bugzilla 1001083 ]
+
 2004-04-22  Jani Monoses <jani@iv.ro>
 
 	 * cdl/hal_sparc.cdl :
diff --git a/packages/hal/sparc/arch/current/cdl/hal_sparc.cdl b/packages/hal/sparc/arch/current/cdl/hal_sparc.cdl
--- a/packages/hal/sparc/arch/current/cdl/hal_sparc.cdl
+++ b/packages/hal/sparc/arch/current/cdl/hal_sparc.cdl
@@ -73,7 +73,7 @@ cdl_package CYGPKG_HAL_SPARC {
 
     make {
         <PREFIX>/lib/target.ld: <PACKAGE>/src/sparc.ld
-        $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
+        $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -o $@ $<
         @echo $@ ": \\" > $(notdir $@).deps
         @tail -n +2 target.tmp >> $(notdir $@).deps
         @echo >> $(notdir $@).deps
diff --git a/packages/hal/sparclite/arch/current/ChangeLog b/packages/hal/sparclite/arch/current/ChangeLog
--- a/packages/hal/sparclite/arch/current/ChangeLog
+++ b/packages/hal/sparclite/arch/current/ChangeLog
@@ -1,3 +1,8 @@
+2011-01-02  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/hal_sparclite.cdl: Eliminate some warnings. [ Bugzilla
+	1001083 ]
+
 2004-04-22  Jani Monoses <jani@iv.ro>
 
 	 * cdl/hal_sparclite.cdl :
diff --git a/packages/hal/sparclite/arch/current/cdl/hal_sparclite.cdl b/packages/hal/sparclite/arch/current/cdl/hal_sparclite.cdl
--- a/packages/hal/sparclite/arch/current/cdl/hal_sparclite.cdl
+++ b/packages/hal/sparclite/arch/current/cdl/hal_sparclite.cdl
@@ -73,7 +73,7 @@ cdl_package CYGPKG_HAL_SPARCLITE {
 
     make {
         <PREFIX>/lib/target.ld: <PACKAGE>/src/sparclite.ld
-        $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
+        $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -o $@ $<
         @echo $@ ": \\" > $(notdir $@).deps
         @tail -n +2 target.tmp >> $(notdir $@).deps
         @echo >> $(notdir $@).deps
diff --git a/packages/hal/synth/arch/current/ChangeLog b/packages/hal/synth/arch/current/ChangeLog
--- a/packages/hal/synth/arch/current/ChangeLog
+++ b/packages/hal/synth/arch/current/ChangeLog
@@ -1,3 +1,7 @@
+2011-08-13  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/hal_synth.cdl (CYGPKG_HAL_SYNTH_TESTS): Fix a typo in make rule.
+
 2009-08-13  Bart Veer  <bartv@ecoscentric.com>
 
 	* src/synth.ld (SECTION_eh_frame): allow for a .eh_frame_hdr
diff --git a/packages/hal/synth/arch/current/cdl/hal_synth.cdl b/packages/hal/synth/arch/current/cdl/hal_synth.cdl
--- a/packages/hal/synth/arch/current/cdl/hal_synth.cdl
+++ b/packages/hal/synth/arch/current/cdl/hal_synth.cdl
@@ -155,7 +155,7 @@ cdl_package CYGPKG_HAL_SYNTH {
         make {
             <PREFIX>/tests/ftok: <PACKAGE>/tests/ftok.c
             @mkdir -p "$(dir $@)"
-            @$(HOST_CC) -DHOST -g -O2 -o $@ $< || cc -DHOST -g -O2 -o $@ $< || -DHOST gcc -g -O2 -o $@ $<
+            @$(HOST_CC) -DHOST -g -O2 -o $@ $< || cc -DHOST -g -O2 -o $@ $< || gcc -DHOST -g -O2 -o $@ $<
         }
     }
 }
diff --git a/packages/hal/synth/i386linux/current/ChangeLog b/packages/hal/synth/i386linux/current/ChangeLog
--- a/packages/hal/synth/i386linux/current/ChangeLog
+++ b/packages/hal/synth/i386linux/current/ChangeLog
@@ -1,3 +1,8 @@
+2011-06-05  John Dallaway  <john@dallaway.org.uk>
+
+	* src/syscall-i386-linux-1.0.S: Fix .size and .type expressions to
+	avoid build error with binutils 2.21.x. Patch from Tom Schouten.
+
 2009-08-11  Bart Veer  <bartv@ecoscentric.com>
 
 	* src/tls.c: new module for TLS (thread local storage) support as
@@ -427,7 +432,7 @@ Mon Nov  9 15:18:11 GMT 1998   Chris Pro
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2011 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/hal/synth/i386linux/current/src/syscall-i386-linux-1.0.S b/packages/hal/synth/i386linux/current/src/syscall-i386-linux-1.0.S
--- a/packages/hal/synth/i386linux/current/src/syscall-i386-linux-1.0.S
+++ b/packages/hal/synth/i386linux/current/src/syscall-i386-linux-1.0.S
@@ -444,8 +444,8 @@ cyg_hal_sys_restore_rt:
         movl    $SYS_rt_sigreturn, %eax
         int     $0x80
 1:              
-        .type __restore_rt,@function
-        .size __restore_rt,1b - __restore_rt
+        .type cyg_hal_sys_restore_rt,@function
+        .size cyg_hal_sys_restore_rt,1b - cyg_hal_sys_restore_rt
                 
         .align 8
         .global cyg_hal_sys_restore
@@ -454,5 +454,5 @@ cyg_hal_sys_restore:
         movl    $SYS_sigreturn, %eax
         int     $0x80
 1:              
-        .type __restore,@function
-        .size __restore,1b - __restore
+        .type cyg_hal_sys_restore,@function
+        .size cyg_hal_sys_restore,1b - cyg_hal_sys_restore
diff --git a/packages/infra/current/ChangeLog b/packages/infra/current/ChangeLog
--- a/packages/infra/current/ChangeLog
+++ b/packages/infra/current/ChangeLog
@@ -1,3 +1,30 @@
+2013-02-20  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/cyg_type.h: Add CYGBLD_ATTRIB_NO_INLINE (suggested by Jifl)
+	[ Bugzilla 1001768 ]
+
+2013-02-09  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/cyg_type.h: Add CYGBLD_FORCE_INLINE macro to be used
+	to enforce function inlining when compiling with no optimization.
+	[ Bugzilla Bug 1001759 ]
+
+2012-03-06  Grant Edwards  <grant.b.edwards@gmail.com>
+
+	* include/cyg_type.h: Add CYGBLD_ATTRIB_UNUSED macro to be used to
+	eliminate compiler warnings about unused or set-but-not-referenced
+	varibles. Part of: [ Bugzilla 1001504 ]
+	
+2012-03-06  
+	
+	* src/diag.cxx: Fix compiler warnings about variables that are set
+	but never read. [ Bugzilla 1001503 ]
+
+2010-09-13  Chris Holgate  <chris@zynaptic.com>
+
+	* include/diag.h:
+	* src/diag.cxx: Add diag_vsnprintf().
+
 2009-10-06  Uwe Kindler  <uwe_kindler@web.de>
 
 	* include/cyg_type.h: Changed definition of macro
diff --git a/packages/infra/current/include/cyg_type.h b/packages/infra/current/include/cyg_type.h
--- a/packages/infra/current/include/cyg_type.h
+++ b/packages/infra/current/include/cyg_type.h
@@ -452,6 +452,11 @@ typedef cyg_haladdrword CYG_ADDRWORD;
 # define CYGBLD_ATTRIB_STRFTIME_FORMAT(__format__, __args__) \
         __attribute__((format (strftime, __format__, __args__)))
 
+// Tell compiler not to warn us about an unused variable -- generally
+// because it will be used when sources are build under certain
+// circumstances (e.g. with debugging or asserts enabled.
+# define CYGBLD_ATTRIB_UNUSED  __attribute__((unused))
+
 // Tell the compiler not to throw away a variable or function. Only known
 // available on 3.3.2 or above. Old version's didn't throw them away,
 // but using the unused attribute should stop warnings.
@@ -462,8 +467,21 @@ typedef cyg_haladdrword CYG_ADDRWORD;
 #   define CYGBLD_ATTRIB_USED __attribute__((unused))
 #  endif
 # endif 
+
+// Enforce inlining of a C function. GCC does not inline any C
+// function when not optimizing, unless you specify "always_inline" attribute.
+// Other attributes suppress generation of standalone function.
+# if !defined(CYGBLD_FORCE_INLINE)
+#  define CYGBLD_FORCE_INLINE __externC inline __attribute((gnu_inline)) __attribute((always_inline))
+# endif
+
+// Suppress function inlining
+#define CYGBLD_ATTRIB_NO_INLINE __attribute__((noinline))
+
 #else // non-GNU
 
+# define CYGBLD_ATTRIB_UNUSED  /* nothing */
+
 # define CYGBLD_ATTRIB_CONSTRUCTOR
 
 # define CYGBLD_ATTRIB_NORET
@@ -491,6 +509,9 @@ typedef cyg_haladdrword CYG_ADDRWORD;
 
 # define CYGBLD_ATTRIB_STRFTIME_FORMAT(__format__, __args__)
 
+#define CYGBLD_FORCE_INLINE
+
+#define CYGBLD_ATTRIB_NO_INLINE
 
 #endif
 
diff --git a/packages/infra/current/include/diag.h b/packages/infra/current/include/diag.h
--- a/packages/infra/current/include/diag.h
+++ b/packages/infra/current/include/diag.h
@@ -100,6 +100,8 @@ externC int  diag_snprintf(char *buf, si
      CYGBLD_ATTRIB_PRINTF_FORMAT(3,4);
 externC int  diag_vsprintf(char *buf, const char *fmt, va_list ap)
      CYGBLD_ATTRIB_PRINTF_FORMAT(2,0);
+externC int  diag_vsnprintf(char *buf, size_t len, const char *fmt, va_list ap)
+     CYGBLD_ATTRIB_PRINTF_FORMAT(3,0);
 externC int  diag_vprintf(const char *fmt, va_list ap)
      CYGBLD_ATTRIB_PRINTF_FORMAT(1,0);
 
diff --git a/packages/infra/current/src/diag.cxx b/packages/infra/current/src/diag.cxx
--- a/packages/infra/current/src/diag.cxx
+++ b/packages/infra/current/src/diag.cxx
@@ -522,7 +522,6 @@ static void
 int
 diag_sprintf(char *buf, const char *fmt, ...)
 {        
-    int ret;
     va_list ap;
     struct _sputc_info info;
 
@@ -530,15 +529,14 @@ diag_sprintf(char *buf, const char *fmt,
     info.ptr = buf;
     info.max = 1024;  // Unlimited
     info.len = 0;
-    ret = _vprintf(_sputc, (void **)&info, fmt, ap);
+    _vprintf(_sputc, (void **)&info, fmt, ap);
     va_end(ap);
-    return (info.len);
+    return info.len;
 }
 
 int
 diag_snprintf(char *buf, size_t len, const char *fmt, ...)
 {        
-    int ret;
     va_list ap;
     struct _sputc_info info;
 
@@ -546,7 +544,7 @@ diag_snprintf(char *buf, size_t len, con
     info.ptr = buf;
     info.len = 0;
     info.max = len-1;
-    ret = _vprintf(_sputc, (void **)&info, fmt, ap);
+    _vprintf(_sputc, (void **)&info, fmt, ap);
     va_end(ap);
     return (info.len);
 }
@@ -554,13 +552,24 @@ diag_snprintf(char *buf, size_t len, con
 int 
 diag_vsprintf(char *buf, const char *fmt, va_list ap)
 {
-    int ret;
     struct _sputc_info info;
 
     info.ptr = buf;
     info.max = 1024;  // Unlimited
     info.len = 0;
-    ret = _vprintf(_sputc, (void **)&info, fmt, ap);
+    _vprintf(_sputc, (void **)&info, fmt, ap);
+    return (info.len);
+}
+
+int 
+diag_vsnprintf(char *buf, size_t len, const char *fmt, va_list ap)
+{
+    struct _sputc_info info;
+
+    info.ptr = buf;
+    info.max = len-1;  
+    info.len = 0;
+    _vprintf(_sputc, (void **)&info, fmt, ap);
     return (info.len);
 }
 
diff --git a/packages/io/adc/current/ChangeLog b/packages/io/adc/current/ChangeLog
--- a/packages/io/adc/current/ChangeLog
+++ b/packages/io/adc/current/ChangeLog
@@ -1,3 +1,13 @@
+2010-06-06 ccoutand <ccoutand@stmi.com>
+	* doc/adc.sgml
+	Updated documentation, add new ADC data flush and 
+	correct Copy/Paste in enable_io
+
+2010-05-25 ccoutand <ccoutand@stmi.com>
+	* src/adc.c: 
+	Add new key to ADC driver to flush data buffer:
+	CYG_IO_SET_CONFIG_ADC_DATA_FLUSH
+
 2009-03-02  Simon Kallweit  <simon.kallweit@intefo.ch>
 
 	* cdl/io_adc.cdl:
diff --git a/packages/io/adc/current/doc/adc.sgml b/packages/io/adc/current/doc/adc.sgml
--- a/packages/io/adc/current/doc/adc.sgml
+++ b/packages/io/adc/current/doc/adc.sgml
@@ -257,7 +257,27 @@ int disable_io( cyg_io_handle_t handle )
 int enable_io( cyg_io_handle_t handle )
 {
     return cyg_io_set_config( handle,
-                              CYG_IO_SET_CONFIG_ADC_DISABLE,
+                              CYG_IO_SET_CONFIG_ADC_ENABLE,
+                              NULL,
+                              NULL);
+}
+</programlisting>
+
+</refsect2>
+
+<refsect2 id="adc-details-flush"><title>Flushing a Channel</title>
+
+<para>
+In some particular cases, user might require to flush the ADC data buffer. Flushing
+may be perfomed via a <function>set_config</function>
+function:
+</para>
+
+<programlisting width=72>
+int flush_io( cyg_io_handle_t handle )
+{
+    return cyg_io_set_config( handle,
+                              CYG_IO_SET_CONFIG_ADC_DATA_FLUSH,
                               NULL,
                               NULL);
 }
@@ -267,7 +287,6 @@ int enable_io( cyg_io_handle_t handle )
 
 </refsect1>
 
-
 <refsect1 id="adc-config"><title>Configuration</title>
 
 <para>
diff --git a/packages/io/adc/current/src/adc.c b/packages/io/adc/current/src/adc.c
--- a/packages/io/adc/current/src/adc.c
+++ b/packages/io/adc/current/src/adc.c
@@ -298,6 +298,13 @@ static Cyg_ErrNo adc_set_config(cyg_io_h
         chan->device->funs->disable( chan );
         break;        
 
+    case CYG_IO_SET_CONFIG_ADC_DATA_FLUSH:
+        cyg_drv_isr_lock();
+        chan->put = 0;
+        chan->get = 0;
+        cyg_drv_isr_unlock();
+        break;      
+
     case CYG_IO_SET_CONFIG_READ_BLOCKING:
         if (*len < sizeof(cyg_uint32))
             return -EINVAL;
diff --git a/packages/io/can/current/ChangeLog b/packages/io/can/current/ChangeLog
--- a/packages/io/can/current/ChangeLog
+++ b/packages/io/can/current/ChangeLog
@@ -1,3 +1,34 @@
+2013-06-24  Uwe Kindler <uwe_kindler@web.de>
+
+	* include/canio.h: Added structure cyg_can_err_count_info for reading
+	CAN hardware error counter values from CAN hardware.
+	* doc/can.sgml: Documented new CAN config key
+	CYG_IO_GET_CONFIG_ERR_COUNTERS.
+
+2013-05-06  Uwe Kindler <uwe_kindler@web.de>
+
+	* doc/can.sgml: Documented return code -ENOSPC for cyg_io_set_config()
+	for config keys CYG_IO_SET_CONFIG_CAN_RANGE_FILTER and
+	CYG_IO_SET_CONFIG_CAN_MASK_FILTER
+
+2012-01-22  Bernard Fouché <bernard.fouche@kuantic.com>
+
+	* cdl/io_can.cdl: support for add/remove compiler flags
+	* doc/can.sgml, doc/can_driver_doc.html: updated doc reflecting API
+	changes (range/mask filtering, listen-only mode, return values for
+	xmt_msg/rcv_event, new flags).
+	* include/can.h: given in a match the types of function pointers for
+	can_callbacks_t according to the changes made in can.c.
+	* include/canio.h: flags field in event enlarged to 32 bits to fit
+	new events 'CYGNUM_CAN_EVENT_ERR_ACTIVE' and
+	'CYGNUM_CAN_EVENT_OVERRUN_RX_HW'. Made a 'flag' typedef.
+	cyg_can_event fields reordered so flags size change keeps events the
+	same size.  Defined new filtering capabilities (range/mask). New
+	convenience macro CYGNUM_CAN_EVENT_ALL. New listen-only mode.
+	* src/can.c: can_rcv_event() and can_xmt_msg() now returns cyg_bool
+	(were 'void'). flags using cyg_can_event_flags_t type.
+	[ Bugzilla 1001453 ]
+
 2010-01-13  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
 
 	* include/can.h: EOF footer: s/SERIAL/CAN/.
diff --git a/packages/io/can/current/cdl/io_can.cdl b/packages/io/can/current/cdl/io_can.cdl
--- a/packages/io/can/current/cdl/io_can.cdl
+++ b/packages/io/can/current/cdl/io_can.cdl
@@ -257,7 +257,40 @@ cdl_package CYGPKG_IO_CAN {
                 The initial timeout value in clock ticks for cyg_io_write() calls."
         }
     }
-    
+
+    cdl_component CYGPKG_IO_CAN_OPTIONS {
+        display "CAN device driver build options"
+        flavor  none
+        description   "
+            Package specific build options including control over
+            compiler flags used only in building this package,
+            and details of which tests are built."
+
+
+        cdl_option CYGPKG_IO_CAN_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the CAN device drivers. These flags are used
+                in addition to the set of global flags."
+        }
+
+        cdl_option CYGPKG_IO_CAN_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the CAN device drivers. These flags are
+                removed from the set of global flags if present."
+        }
+
+    }
+
     cdl_option CYGBLD_IO_CAN_EXTRA_TESTS {
         display "Build extra CAN tests"
         default_value 0
diff --git a/packages/io/can/current/doc/can.sgml b/packages/io/can/current/doc/can.sgml
--- a/packages/io/can/current/doc/can.sgml
+++ b/packages/io/can/current/doc/can.sgml
@@ -124,7 +124,7 @@ device independent CAN I/O API for acces
 network. This API handles issues such as locking between threads. The
 package does not contain any hardware-specific code. Instead it will
 call into a CAN device driver to handle the hardware device
-access. This package also defines the inderface that such hardware
+access. This package also defines the interface that such hardware
 drivers should provide.
     </para>
   </listitem>
@@ -173,13 +173,14 @@ All functions return a value of the type
 If an error condition is detected, this value will be negative and the 
 absolute value indicates the actual error, as specified in 
 <filename>cyg/error/codes.h</filename>. The only other legal return values 
-will be <varname>ENOERR</varname>, <varname>-EINTR</varname> and 
-<varname>-EAGAIN</varname>. All other function arguments are pointers 
-(references). This allows the drivers to pass information efficiently, 
-both into and out of the driver. The most striking example of this is the 
-<parameter>len</parameter> value passed to the read and write functions. 
-This parameter contains the desired length of data on input to the 
-function and the actual transferred length on return.
+will be <varname>ENOERR</varname>, <varname>-EINTR</varname>,
+<varname>-EINVAL</varname> and <varname>-EAGAIN</varname>.  All other
+function arguments are pointers (references). This allows the drivers
+to pass information efficiently, both into and out of the driver. The
+most striking example of this is the <parameter>len</parameter> value
+passed to the read and write functions.  This parameter contains the
+desired length of data on input to the function and the actual
+transferred length on return.
 </PARA>
     
 <PROGRAMLISTING>
@@ -226,6 +227,12 @@ of data to receive is contained in <para
 actual size obtained will be returned in the same place. 
 </PARA>
 
+<PARA>
+You may notice that the data sent (messages) is different from the
+data received (events). An event includes flags that describe the
+event, and eventually a received message and a timestamp.
+</PARA>
+
 <PROGRAMLISTING>
 // Read configuration of a CAN device
 Cyg_ErrNo <FUNCTION><!-- <index></index> -->cyg_io_get_config</FUNCTION>( 
@@ -353,7 +360,7 @@ the caller must try again.
 </PARA>
     
 <PARA>
-If a message was sucessfully sent, the function returns <varname>ENOERR</varname>.
+If a message was successfully sent, the function returns <varname>ENOERR</varname>.
 </PARA>
 </SECTION>
     
@@ -455,7 +462,7 @@ cyg_io_read(handle, buf, len)
 </PROGRAMLISTING>
 
 <PARA>
-To receive a message the application calls <function>cyg_can_recv()</function>.
+To receive a message the application calls <function>cyg_io_read()</function>.
 This function receives one single event from a device. The desired size 
 of data to receive is contained in <parameter>*len</parameter> and the
 actual size obtained will be returned in the same place. A pointer to 
@@ -478,7 +485,7 @@ try again.
 </PARA>
     
 <PARA>
-It is possible to configure the write call to be non-blocking with timeout. 
+It is possible to configure the read call to be non-blocking with timeout.
 None-blocking mode with timeout requires the configuration option 
 <varname>CYGOPT_IO_CAN_SUPPORT_NONBLOCKING</varname> and 
 <varname>CYGOPT_IO_CAN_SUPPORT_TIMEOUTS</varname> to be enabled, 
@@ -492,7 +499,7 @@ is returned and the caller must try agai
 </PARA>
     
 <PARA>
-If a event was sucessfully received, the function returns <varname>ENOERR</varname>.    
+If an event was successfully received, the function returns <varname>ENOERR</varname>.
 </PARA>
 </SECTION><!-- cyg_io_read -->
 
@@ -511,8 +518,8 @@ independent type for handling CAN events
 typedef struct cyg_can_event_st
 {
     cyg_uint32      timestamp;
+    cyg_can_event_flags_t flags;
     cyg_can_message msg;
-    cyg_uint16      flags;
 } cyg_can_event;
 </PROGRAMLISTING>
 
@@ -529,6 +536,14 @@ contain a timestamp value for an event t
           </para></listitem>
    </varlistentry>
    <varlistentry>
+       <term><type>cyg_can_event_flags_t</type> <varname>flags</varname></term>
+           <listitem><para>
+Event flags. The <varname>flags</varname> field contains bits that
+indicate which kind of events occured. More than one flag can be raised
+in a single event.
+          </para></listitem>
+   </varlistentry>
+   <varlistentry>
        <term><type>cyg_can_message</type> <varname>msg</varname></term>
            <listitem><para>
 CAN message. The msg field contains a CAN message if an RX or TX event
@@ -538,59 +553,52 @@ the <structfield>msg</structfield> may c
 specific data.
           </para></listitem>
    </varlistentry>
-   <varlistentry>
-       <term><type>cyg_uint16</type> <varname>flags</varname></term>
-           <listitem><para>
-Event flags. The <varname>flags</varname> field contains 16 bits that 
-indicate which kind of events occured. 
-          </para></listitem>
-   </varlistentry>
 </variablelist>
     
 <PARA>
 The following events are supported and after receiving an event the 
-application should check the flag field against these values:
+application should check the <varname>flags</varname> field against these values:
 </PARA>
     
 <PROGRAMLISTING>
-typedef enum
-{
-  CYGNUM_CAN_EVENT_RX               = 0x0001, // message received
-  CYGNUM_CAN_EVENT_TX               = 0x0002, // message transmitted
-  CYGNUM_CAN_EVENT_WARNING_RX       = 0x0004, // (TEC) reached warning level (>96)
-  CYGNUM_CAN_EVENT_WARNING_TX       = 0x0008, // (REC) reached warning level (>96)
-  CYGNUM_CAN_EVENT_ERR_PASSIVE      = 0x0010, // CAN "error passive" occured
-  CYGNUM_CAN_EVENT_BUS_OFF          = 0x0020, // CAN "bus off" error occured
-  CYGNUM_CAN_EVENT_OVERRUN_RX       = 0x0040, // overrun in RX queue or hardware 
-  CYGNUM_CAN_EVENT_OVERRUN_TX       = 0x0080, // overrun in TX queue occured
-  CYGNUM_CAN_EVENT_CAN_ERR          = 0x0100, // a CAN bit or frame error occured
-  CYGNUM_CAN_EVENT_LEAVING_STANDBY  = 0x0200, // CAN hardware leaves standby
-  CYGNUM_CAN_EVENT_ENTERING_STANDBY = 0x0400, // CAN hardware enters standby
-  CYGNUM_CAN_EVENT_ARBITRATION_LOST = 0x0800, // arbitration lost
-  CYGNUM_CAN_EVENT_FILTER_ERR       = 0x1000, // CAN message filter / acceptance filter error
-  CYGNUM_CAN_EVENT_PHY_FAULT        = 0x2000, // General failure of physical layer 
-  CYGNUM_CAN_EVENT_PHY_H            = 0x4000, // Fault on CAN-H (Low Speed CAN)
-  CYGNUM_CAN_EVENT_PHY_L            = 0x8000, // Fault on CAN-L (Low Speed CAN)
-} cyg_can_event_flags;
+CYGNUM_CAN_EVENT_RX               0x00000001 // message received
+CYGNUM_CAN_EVENT_TX               0x00000002 // mesage transmitted
+CYGNUM_CAN_EVENT_WARNING_RX       0x00000004 // tx error counter (TEC) reached warning level (>96)
+CYGNUM_CAN_EVENT_WARNING_TX       0x00000008 // rx error counter (REC) reached warning level (>96)
+CYGNUM_CAN_EVENT_ERR_PASSIVE      0x00000010 // CAN "error passive" occured
+CYGNUM_CAN_EVENT_BUS_OFF          0x00000020 // CAN "bus off" error occured
+CYGNUM_CAN_EVENT_OVERRUN_RX       0x00000040 // overrun in RX queue occured
+CYGNUM_CAN_EVENT_OVERRUN_TX       0x00000080 // overrun in TX queue occured
+CYGNUM_CAN_EVENT_CAN_ERR          0x00000100 // a CAN bit or frame error occured
+CYGNUM_CAN_EVENT_LEAVING_STANDBY  0x00000200 // CAN hardware leaves standby / power down mode or is waked up
+CYGNUM_CAN_EVENT_ENTERING_STANDBY 0x00000400 // CAN hardware enters standby / power down mode
+CYGNUM_CAN_EVENT_ARBITRATION_LOST 0x00000800 // arbitration lost
+CYGNUM_CAN_EVENT_FILTER_ERR       0x00001000 // CAN message filter / acceptance filter error
+CYGNUM_CAN_EVENT_PHY_FAULT        0x00002000 // General failure of physical layer detected
+CYGNUM_CAN_EVENT_PHY_H            0x00004000 // Fault on CAN-H detected (Low Speed CAN)
+CYGNUM_CAN_EVENT_PHY_L            0x00008000 // Fault on CAN-L detected (Low Speed CAN)
+CYGNUM_CAN_EVENT_ERR_ACTIVE       0x00010000 // CAN controller now "error active"
+CYGNUM_CAN_EVENT_OVERRUN_RX_HW    0x00020000 // CAN controller reports a RX overrun
 </PROGRAMLISTING>
 
 <PARA>
 Often the flags field will contain only one single set flag. But it is 
-possible that a number of flags is set and so the flag field should always 
-be checked by a receiver. I.e. if the <varname>CYGNUM_CAN_EVENT_RX</varname> 
-is set then also the <varname>CYGNUM_CAN_EVENT_OVERRUN_RX</varname> 
-may be set if the received message caused an RX overrun.
+possible that a number of flags is set and so the flag field should
+always be checked by a receiver.  Most of the flags are independent
+from each other and the receiver has to handle each of them separately.
 </PARA>
     
 <PARA>
-The internal receive buffers of the CAN device driver are circular buffers. 
-That means that even if the buffers are completely filled new messages 
-will be received. In this case the newest message will always overwrite 
-the oldest message in receive buffer. If this happens the 
-<varname>CYGNUM_CAN_EVENT_OVERRUN_RX</varname> flag will be set for this 
-new message that caused overwriting of the old one. The 
-<varname>CYGNUM_CAN_EVENT_OVERRUN_RX</varname> flag will be set also if 
-a overrun occures in hardware message buffers of the CAN device.
+The internal receive buffers of the CAN device driver are circular
+buffers.  That means that even if the buffers are completely filled
+new messages will be received. In this case the newest message will
+always overwrite the oldest message in the receive buffer. If this
+happens the
+<varname>CYGNUM_CAN_EVENT_OVERRUN_RX</varname> flag will be set for
+this new message that caused overwriting of the old one. However if an
+overrun occurs in the hardware message buffers of the CAN controller,
+the flag <varname>CYGNUM_CAN_EVENT_OVERRUN_RX_HW</varname> is raised
+instead.
 </PARA>
     
 <PARA>
@@ -656,6 +664,7 @@ CYG_IO_GET_CONFIG_CAN_MSGBUF_INFO
 CYG_IO_GET_CONFIG_CAN_TIMEOUT
 CYG_IO_GET_CONFIG_CAN_HDI
 CYG_IO_GET_CONFIG_CAN_STATE
+CYG_IO_GET_CONFIG_CAN_ERR_COUNTERS
 </PROGRAMLISTING>
 </SECTION><!-- can-cyg-io-get-config -->
   
@@ -692,6 +701,8 @@ CYG_IO_SET_CONFIG_CAN_MSGBUF
 CYG_IO_SET_CONFIG_CAN_MODE
 CYG_IO_SET_CONFIG_CAN_ABORT
 CYG_IO_SET_CONFIG_CAN_CALLBACK
+CYG_IO_SET_CONFIG_CAN_RANGE_FILTER
+CYG_IO_SET_CONFIG_CAN_MASK_FILTER
 </PROGRAMLISTING>
 </SECTION><!-- can-cyg-io-set-config -->
 </SECTION><!-- io-can-api-details -->
@@ -875,8 +886,8 @@ The following flags are available in the
      
 <PROGRAMLISTING>    
 |   7   |   6   |   5   |   4   |   3   |   2   |   1   |   0   |
-+-------+-------+-------+-------+-------+-------+-------+-------+
-|  res  |  res  |  res  |timest.|SW-Filt|FullCAN|   Frametype   |
++-------+-------+-------+-------+--------+-------+-------+-------+
+|ListenO|Mask F |Range F|timest.|autobaud|FullCAN|   Frametype   |
 </PROGRAMLISTING>
 
 <variablelist>
@@ -900,17 +911,38 @@ the CAN controller supports more than on
     </para></listitem>
   </varlistentry>
   <varlistentry>
-    <term><parameter>SW-Filter</parameter></term>
+    <term><parameter>autobaud</parameter></term>
     <listitem><para>
-If Bit 3 - <varname>CYGNUM_CAN_HDI_FILT_SW</varname> - is set to one then 
-the CAN driver supports some kind of software message filtering.
+If Bit 3 - <varname>CYGNUM_CAN_HDI_AUTBAUD</varname> - is set to one then
+the CAN driver supports an autobaud feature.
     </para></listitem>
   </varlistentry>
   <varlistentry>
     <term><parameter>Timestamp</parameter></term>
     <listitem><para>
 If Bit 4 - <varname>CYGNUM_CAN_HDI_TIMESTAMP</varname> - is set to one then 
-the CAN hardware supports timestamps for CAN messages
+the CAN hardware supports timestamps for CAN messages.
+    </para></listitem>
+  </varlistentry>
+  <varlistentry>
+    <term><parameter>Identifier Range filtering</parameter></term>
+    <listitem><para>
+If Bit 5 - <varname>CYGNUM_CAN_HDI_RANGE_FILTERING</varname> - is set to one
+then the CAN hardware supports message filtering based on identifier ranges.
+    </para></listitem>
+  </varlistentry>
+  <varlistentry>
+    <term><parameter>Identifier Mask filtering</parameter></term>
+    <listitem><para>
+If Bit 6 - <varname>CYGNUM_CAN_HDI_MASK_FILTERING</varname> - is set to one
+then the CAN hardware supports message filtering based on identifier masks.
+    </para></listitem>
+  </varlistentry>
+  <varlistentry>
+    <term><parameter>Listen Only mode</parameter></term>
+    <listitem><para>
+If Bit 7 - <varname>CYGNUM_CAN_HDI_LISTEN_ONLY</varname> - is set to one
+then the CAN hardware supports a 'listen-only' mode.
     </para></listitem>
   </varlistentry>
 </variablelist>
@@ -921,8 +953,8 @@ the CAN hardware supports timestamps for
 <PROGRAMLISTING>    
 typedef struct cyg_can_msgbox_info_st
 {
-    cyg_uint8 count; // number of message buffers available for this device
-    cyg_uint8 free;  // number of free message buffers
+    cyg_uint16 count; // number of message buffers available for this device
+    cyg_uint16 free;  // number of free message buffers
 } cyg_can_msgbuf_info;
 </PROGRAMLISTING>
    
@@ -937,13 +969,13 @@ free message buffers.
 
 <variablelist>
    <varlistentry>
-       <term><type>cyg_uint8</type> <varname>count</varname></term>
+       <term><type>cyg_uint16</type> <varname>count</varname></term>
            <listitem><para>
 Counts the number of message buffers supported by the device.
           </para></listitem>
    </varlistentry>
    <varlistentry>
-       <term><type>cyg_uint8</type> <varname>free</varname></term>
+       <term><type>cyg_uint16</type> <varname>free</varname></term>
            <listitem><para>
 Contains the number of free message buffers. The free message buffers are 
 available for setting up remote buffers (<varname>CYG_IO_SET_CONFIG_CAN_REMOTE_BUF</varname>) 
@@ -978,6 +1010,26 @@ present state of the CAN controller. Pos
 </PARA>   
 </SECTION> <!-- can-read-hw-state -->
 
+<SECTION>
+<TITLE>Reading CAN hardware error counters</TITLE>
+
+<PROGRAMLISTING>
+typedef struct cyg_can_err_count_info_st
+{
+    cyg_uint8 rx_err_count;
+    cyg_uint8 tx_err_count;
+} cyg_can_err_count_info;
+</PROGRAMLISTING>
+
+<PARA>
+Each CAN node maintains two error counters: the Transmit Error Counter (TEC)
+and the Receive Error Counter (REC). There are several rules governing how
+these counters are incremented and/or decremented.
+<varname>CYG_IO_GET_CONFIG_CAN_ERR_COUNTERS</varname> retrieves the present
+value of both error counters (TEC and REC).
+</PARA>
+</SECTION> <!-- can-read-err-counters -->
+
 
 <SECTION>
 <TITLE>Changing mode of CAN hardware</TITLE>
@@ -993,7 +1045,10 @@ typedef enum
 {
   CYGNUM_CAN_MODE_STOP,   // set controller into stop mode
   CYGNUM_CAN_MODE_START,  // set controller into operational mode
-  CYGNUM_CAN_MODE_STANDBY // set controller into standby / sleep mode
+  CYGNUM_CAN_MODE_STANDBY,// set controller into standby / sleep mode
+  CYGNUM_CAN_MODE_CONFIG, // safe mode to add/delete message buffers
+  CYGNUM_CAN_MODE_LISTEN_ONLY_ENTER, // set controller into listen only mode.
+  CYGNUM_CAN_MODE_LISTEN_ONLY_EXIT   // set controller out of listen only mode.
 } cyg_can_mode;
 </PROGRAMLISTING>
  
@@ -1016,13 +1071,35 @@ Set controller into operational mode
 Set controller into standby / sleep mode.
           </para></listitem>
    </varlistentry>
+   <varlistentry>
+       <term><type>CYGNUM_CAN_MODE_CONFIG</type></term>
+           <listitem><para>
+Set controller into a mode allowing modifying message buffers.
+          </para></listitem>
+   </varlistentry>
+   <varlistentry>
+       <term><type>CYGNUM_CAN_MODE_LISTEN_ONLY_ENTER</type></term>
+           <listitem><para> Make controller enter listen-only mode (if
+supported by hardware). In such a mode the CAN controller won't
+acknowledge the messages it sees on the bus. This mode can help to
+perform autobaud at application level if the underlying hardware does
+not support it directly. Depending on your CAN transceiver, such a
+mode may also be implemented by the transceiver.
+          </para></listitem>
+   </varlistentry>
+   <varlistentry>
+       <term><type>CYGNUM_CAN_MODE_LISTEN_ONLY_EXIT</type></term>
+           <listitem><para> Make controller exit of listen-only
+mode. The controller will acknowledge all messages it sees on the bus.
+          </para></listitem>
+   </varlistentry>
 </variablelist>
 
 <PARA>
 Before the hardware configuration of the device is changed, that means
 if baud rate is changed or the message buffer and filter configuration
-is changed, the CAN hardware should be set into stop mode and if
-configuration is finished, then device should be set back into
+is changed, the CAN hardware should be set into stop or config mode
+and if configuration is finished, then device should be set back into
 operational mode.  Before the device is set into standby mode, the
 output buffers should be flushed or drained because transmission of a
 CAN message may wake up the CAN hardware. If a received message wakes
@@ -1032,6 +1109,12 @@ inserted into receive message buffer or
 the <varname>CYGNUM_CAN_EVENT_LEAVING_STANDBY</varname> flag will be
 set for the message that caused wake up of CAN hardware.
 </PARA>
+
+<PARA>
+You must also check with the CAN controller data sheet if an incoming
+message waking up the controller is fully received and processed by
+the controller, or if such a wake up message is lost.
+</PARA>
 </SECTION> <!-- can-mode-cfg -->
    
 <SECTION>
@@ -1072,7 +1155,7 @@ CYG_IO_SET_CONFIG_WRITE_BLOCKING
 enable switching between blocking and nonblocking calls separatly for
 read and write calls.  If blocking calls are configured then the
 read/write functions return only if a message was stored into TX
-buffer or a event was received from RX buffer. If non-blocking calls
+buffer or an event was received from RX buffer. If non-blocking calls
 are enabled and there is no space in TX buffer or RX buffer is empty
 then the function returns immediately
 with <varname>-EAGAIN</varname>.
@@ -1103,7 +1186,7 @@ CYG_IO_GET_CONFIG_WRITE_BLOCKING
 <TITLE>Message buffer management</TITLE>
 
 <PARA>
-Full CAN controllers often support more the one message buffer. These
+Full CAN controllers often support more than one message buffer. These
 message buffers are often configurable for transmission or reception
 of certain CAN messages or as a remote buffers.  If a CAN hardware
 supports more than one message buffer then it is possible to configure
@@ -1177,7 +1260,7 @@ CYGNUM_CAN_MSGBUF_REMOTE_BUF_WRITE // st
    <varlistentry>
        <term><type>CYGNUM_CAN_MSGBUF_RESET_ALL</type></term>
            <listitem><para>
-Clears alle message buffers - no message will be received and all remote buffers are deleted.
+Clears all message buffers - no message will be received and all remote buffers are deleted.
           </para></listitem>
    </varlistentry>
    <varlistentry>
@@ -1437,7 +1520,7 @@ if (ENOERR != cyg_io_set_config(hDrvFlex
 }
 
 // prepare the message filter
-rx_filter.cfg_id = CYGNUM_CAN_MSGBUF_RX_FILTER_ADD
+rx_filter.cfg_id = CYGNUM_CAN_MSGBUF_RX_FILTER_ADD;
 rx_filter.msg.id  = 0x800;
 rx_filter.msg.ext = CYGNUM_CAN_ID_EXT;
 
@@ -1497,6 +1580,160 @@ if (ENOERR != cyg_io_set_config(hDrvFlex
 </PROGRAMLISTING> 
 </SECTION> <!-- can-msgfilt-deact -->
 
+<SECTION id="can-id-range-filter">
+<TITLE>Message filtering using identifier ranges</TITLE>
+
+<PARA>
+If the low level driver supports it, you can filter messages using
+identifier ranges. Such filtering is interesting if it is directly
+supported by the CAN controller hardware. Instead of waiting for a
+particular message identifier, the application can define one or more
+ranges of identifiers. If a received message has an identifier value
+(and type) matching a defined identifier range, then the message
+passes the filter and is made available to the application.
+</PARA>
+
+<PARA>
+To add such a filter, use this configuration ID:
+</PARA>
+
+<PROGRAMLISTING>
+CYG_IO_SET_CONFIG_CAN_RANGE_FILTER
+</PROGRAMLISTING>
+
+<PARA>
+The buffer argument given to <function>cyg_io_set_config()</function>
+must point to an area holding the following structure:
+</PARA>
+
+<PROGRAMLISTING>
+typedef struct cyg_can_filter_range_cfg_st
+{
+    cyg_can_id_type        ext;            // type of identifier concerned
+    cyg_uint32             lower_id_bound; // lower bound identifier (included)
+    cyg_uint32             upper_id_bound; // upper bound identifier (included)
+} cyg_can_filter_range_cfg;
+</PROGRAMLISTING>
+
+<variablelist>
+   <varlistentry>
+       <term><type>cyg_can_id_type</type> <varname>ext</varname></term>
+           <listitem><para> Extended ID. If this field
+is <varname>CYGNUM_CAN_ID_EXT</varname> then the next two fields contains
+29 bit extended ID. If <varname>ext</varname>
+contains <varname>CYGNUM_CAN_ID_STD</varname> then the next two fields
+represent 11 bits identifiers.
+          </para></listitem>
+   </varlistentry>
+   <varlistentry>
+       <term><type>cyg_uint32</type> <varname>lower_id_bound</varname></term>
+           <listitem><para>
+Combined with <varname>upper_id_bound</varname> an identifier range is
+defined. All messages having an identifier of the type defined by
+<varname>ext</varname> and included in the range <varname>lower_id_bound</varname>
+to <varname>upper_id_bound</varname> will pass the filter. The identifiers
+<varname>lower_id_bound</varname> and <varname>upper_id_bound</varname> are
+included in the defined range.
+          </para></listitem>
+   </varlistentry>
+   <varlistentry>
+       <term><type>cyg_uint32</type> <varname>upper_id_bound</varname></term>
+           <listitem><para>
+Upper identifier value of the defined range.
+          </para></listitem>
+   </varlistentry>
+</variablelist>
+
+<PARA>
+If no free buffers or filters are available, <varname>-ENOSPC</varname> is
+returned.
+</PARA>
+
+</SECTION> <!-- can-id-range-filter -->
+
+<SECTION id="can-id-mask-filter">
+<TITLE>Message filtering using identifier masks</TITLE>
+
+<PARA>
+If the low level driver supports it, you can filter messages using
+identifier masks. Such filtering is interesting if it is directly
+supported by the CAN controller hardware. Instead of waiting for a
+particular message identifier, the application can define one or more
+pair of identifier and mask. If a received message has an identifier
+value (and type) that, for each bit set of the mask, matches the
+corresponding bit in the provided identifier, then the message passes
+the filter and is made available to the application.
+</PARA>
+
+<PARA>
+To add such a filter, use this configuration ID:
+</PARA>
+
+<PROGRAMLISTING>
+CYG_IO_SET_CONFIG_CAN_MASK_FILTER
+</PROGRAMLISTING>
+
+<PARA>
+The buffer argument given to <function>cyg_io_set_config()</function>
+must point to an area holding the following structure:
+</PARA>
+
+<PROGRAMLISTING>
+typedef struct cyg_can_filter_mask_cfg_st
+{
+    cyg_can_id_type        ext;            // type of identifier concerned
+    cyg_uint32             id;             // identifier to use for filtering
+    cyg_uint32             mask;           // mask to apply for filtering
+} cyg_can_filter_mask_cfg;
+</PROGRAMLISTING>
+
+<variablelist>
+   <varlistentry>
+       <term><type>cyg_can_id_type</type> <varname>ext</varname></term>
+           <listitem><para>
+Extended ID. If this field is <varname>CYGNUM_CAN_ID_EXT</varname> then the
+<structname>id</structname> field contains a 29 bit extended ID. If it
+contains <varname>CYGNUM_CAN_ID_STD</varname> then the ID is 11 bits.
+          </para></listitem>
+   </varlistentry>
+   <varlistentry>
+       <term><type>cyg_uint32</type> <varname>id</varname></term>
+           <listitem><para>
+Message ID. This is the ID to be matched with an incoming message, after
+having considered the <varname>mask</varname> field.
+          </para></listitem>
+   </varlistentry>
+   <varlistentry>
+       <term><type>cyg_uint32</type> <varname>mask</varname></term>
+           <listitem><para>
+Mask value. A message will pass the filter if, for each bit set in
+<varname>mask</varname>, the received message ID has its corresponding
+bit equals to the corresponding bit in the <varname>id</varname> field.
+          </para></listitem>
+   </varlistentry>
+</variablelist>
+
+<PARA>
+For instance let's suppose that the <varname>id</varname> field is
+0x05 (bits 0 and 2 are set) and the <varname>mask</varname> field is
+0x07 (bits 0, 1 and 2 are set). If an incoming message has an ID of
+0x01: bit 0 matches since bit 0 is set in the mask and both the
+incoming message and the <varname>id</varname> field have a similar
+value for bit 0. The message ID has its bit 1 set to 0, as
+the <varname>id</varname> field and the mask tells the controller to
+check this bit: it passes too. However the message ID has its bit 2
+unset, while bit 2 of the mask tells the controller to check bit
+2. Bit 2 of the identifier isn't set in the <varname>id</varname>
+field, hence this example message does not pass the filter.
+</PARA>
+
+<PARA>
+If no free buffers or filters are available, <varname>-ENOSPC</varname> is
+returned.
+</PARA>
+
+</SECTION> <!-- can-id-mask-filter -->
+
 <SECTION id="can-event-callback">
 <TITLE>Configuring a callback on events</TITLE>
 
@@ -1527,7 +1764,7 @@ typedef void (*cyg_can_event_cb_t)(cyg_u
 typedef struct cyg_can_callback_cfg_st
 {
     cyg_can_event_cb_t callback_func;   // callback function
-    cyg_uint16  flag_mask;              // flags mask
+    cyg_can_event_flags_t flag_mask;  // flags mask
     CYG_ADDRWORD data;                  // data passed to callback
 } cyg_can_callback_cfg;
 </PROGRAMLISTING>
@@ -1538,7 +1775,7 @@ typedef struct cyg_can_callback_cfg_st
            <listitem><para> 
 Pointer to the callback function. The function will be called from DSR context so
 you should be careful to only call API functions that are safe in DSR
-context.  The First parameter is a combination of event flags for events that have 
+context.  The first parameter is a combination of event flags for events that have
 occurred. Second parameter is a user defined data pointer or value.
           </para></listitem>
    </varlistentry>
@@ -1549,17 +1786,72 @@ Additional user data that will be passed
           </para></listitem>
    </varlistentry>
    <varlistentry>
-       <term><type>cyg_uint16</type> <varname>flag_mask</varname></term>
+       <term><type>cyg_can_event_flags_t</type> <varname>flag_mask</varname></term>
            <listitem><para>
 Should be set with a combination
 of <varname>CYGNUM_CAN_EVENT_*</varname> flags.  If one of these
 events happens, the callback function will be called, with the
 actually event flags passed as a parameter.  To disable the callback
-function from being called set <varname>flag_mask</varname> to 0.
+function from being called set <varname>flag_mask</varname> to 0. To
+set all possible flags use the <varname>CYGNUM_CAN_EVENT_ALL</varname> macro.
           </para></listitem>
    </varlistentry>
 </variablelist>
 
+<PARA>
+Instead of using a thread dedicated to reading CAN events, it is
+possible, if the CAN controller I/O handle was set in non-blocking
+mode for read operations, to have the callback function to read each
+event it is waiting for. However the callback function runs in DSR
+mode, so it must be carefully written to avoid any blocking call.
+</PARA>
+
+<PARA>
+If you plan to have the callback function to perform read operations,
+be aware that <function>cyg_io_read()</function> retrieves events of
+all kinds while the callback function is triggered only on events it
+is expecting, as defined by the <varname>flag_mask</varname>
+field. The side effect is that the callback function, if it is not
+waiting for all events, may see its first parameter (the flag(s)
+describing why the callback function is called) different from an
+event it get from <function>cyg_io_read()</function>.
+</PARA>
+
+<PARA>
+For instance, let's suppose the callback function is expecting
+only <varname>CYGNUM_CAN_EVENT_RX</varname> events while the bus
+activity triggers other kind of events, like
+the <varname>CYGNUM_CAN_EVENT_WARNING_RX</varname> event. It is
+possible to have in the receive queue a first event of
+type <varname>CYGNUM_CAN_EVENT_WARNING_RX</varname> followed by a
+second event of type <varname>CYGNUM_CAN_EVENT_RX</varname>. In that
+case, the callback function is triggered and have its first parameter
+set to <varname>CYGNUM_CAN_EVENT_RX</varname> exactly
+when <varname>CYGNUM_CAN_EVENT_RX</varname> occurs, but if the
+callback function reads the event queue, it will first get
+the <varname>CYGNUM_CAN_EVENT_WARNING_RX</varname> event.
+</PARA>
+
+<PARA>
+If the callback function is set to process all kind of events and
+always call <function>cyg_io_read()</function> to get each event, it
+is possible to have a receive queue size of one event.
+</PARA>
+
+<PARA>
+If the CAN controller does not provide message timestamps of its own,
+or if the provided timestamps do not match your needs, the callback
+function mechanism can be helpful since it is called from the DSR
+processing the hardware related events. The callback function can
+manage timestamps in the way that suits you the best however there is
+a slight delay between an event related to the CAN bus activity occurs
+and the time the callback function runs. If you implement your own
+timestamps this way, pay also attention to what gives you the current
+time. For instance the granularity
+of <function>cyg_current_time()</function> may not be accurate enough,
+according to the clock resolution and your needs of accuracy.
+</PARA>
+
 </SECTION> <!-- can-event-callback -->
 
 </SECTION>  
@@ -1951,24 +2243,30 @@ void (*can_init)(can_channel *chan)
 <PARA>This function is used to initialize the CAN channel.</PARA>
 
 <PROGRAMLISTING>
-void (*xmt_msg)(can_channel *chan, void *pdata)
+cyg_bool (*xmt_msg)(can_channel *chan, void *pdata)
 </PROGRAMLISTING>
 
 <PARA>
 This function would be called from an interrupt handler after a
 transmit interrupt indicating that additional messages may be
 sent. The upper driver will call the <function>putmsg</function>
-function as appropriate to send more data to the device.
+function as appropriate to send more data to the
+device. <function>xmt_msg()</function> returns <literal>true</literal>
+if a message has been provided to the low level
+driver, <literal>false</literal> otherwise.
 </PARA>
 
 <PROGRAMLISTING>
-void (*rcv_event)(can_channel *chan, void *pdata)
+cyg_bool (*rcv_event)(can_channel *chan, void *pdata)
 </PROGRAMLISTING>
 
 <PARA>
-This function is used to tell the driver that a message has arrived
-at the interface or that an event has occurred. This function is typically 
-called from the interrupt handler. 
+This function is used to tell the driver that a message has arrived at
+the interface or that an event has occurred. This function is
+typically called from the interrupt
+handler. <function>rcv_event()</function>
+returns <literal>true</literal> if an event has been provided by the
+low level driver, <literal>false</literal> otherwise.
 </PARA>
 </SECTION><!-- Callbacks -->
 
diff --git a/packages/io/can/current/doc/can_driver_doc.html b/packages/io/can/current/doc/can_driver_doc.html
--- a/packages/io/can/current/doc/can_driver_doc.html
+++ b/packages/io/can/current/doc/can_driver_doc.html
@@ -79,7 +79,7 @@
 		</p>
 		<p>It is possible to configure the read call to be blocking (default) or non-blocking. Non-blocking mode requires both the configuration option <code>CYGOPT_IO_CAN_SUPPORT_NONBLOCKING</code> to be enabled, and the specific device to be set to non-blocking mode for reads (<code>see cyg_io_set_config()</code>). In blocking mode, the call will not return until one single CAN event has been read. In<i> </i>non-blocking mode, if there is no CAN event in buffer, the call returns immediately with <code>-EAGAIN</code> and the caller must try again.</p>
 		<p>It is possible to configure the write call to be non-blocking with timeout. None-blocking mode with timeout requires the configuration option <code>CYGOPT_IO_CAN_SUPPORT_NONBLOCKING </code>and<code> CYGOPT_IO_CAN_SUPPORT_TIMEOUTS </code>to be enabled, requires the eCos kernel package to be included and the specific device to be set to non-blocking mode for reads (see <code>cyg_io_set_config()</code>). In non-blocking mode with timeouts, if there is no CAN event in receive buffer, the driver waits a certain amound of time (the timeout time) for a CAN event to arrive. If there is still no CAN event in buffer after expiration of the timeout time, <code> -EINTR</code> is returned and the caller must try again.</p>
-		<p>If a event was sucessfully received, the function returns <code>ENOERR</code>.</p>
+		<p>If an event was sucessfully received, the function returns <code>ENOERR</code>.</p>
 		<p><code>typedef struct cyg_can_event_st<br>
 				{<br>
 				&nbsp;&nbsp;&nbsp;&nbsp;cyg_uint32&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;timestamp;<br>
@@ -332,7 +332,7 @@
 		<code>CYG_IO_GET_CONFIG_READ_BLOCKING<br>
 			CYG_IO_GET_CONFIG_WRITE_BLOCKING<br>
 			<br>
-		</code>enable switching between blocking and nonblocking calls separatly for read and write calls. If  blocking calls are configured then the read/write functions return only if a message was stored into TX buffer or a event was received from RX buffer. If nonblocking calls are enabled and there is no space in TX buffer or RX buffer is empty then the function returns immediatelly with <code>-EAGAIN</code>. If nonblocking calls are enabled and additionally timeouts are supported by driver, then the read/write functions wait until  timeout value is expired and then return witn <code>-EINTR</code>. If the read/write operation succeeds during the timed wait then the functions return succesfully with<code> ENOERR</code>.
+		</code>enable switching between blocking and nonblocking calls separatly for read and write calls. If  blocking calls are configured then the read/write functions return only if a message was stored into TX buffer or an event was received from RX buffer. If nonblocking calls are enabled and there is no space in TX buffer or RX buffer is empty then the function returns immediatelly with <code>-EAGAIN</code>. If nonblocking calls are enabled and additionally timeouts are supported by driver, then the read/write functions wait until timeout value is expired and then return witn <code>-EINTR</code>. If the read/write operation succeeds during the timed wait then the functions return succesfully with<code> ENOERR</code>.
 
 		<h4>Message buffer configuration</h4>
 		<p><code>typedef struct cyg_can_msgbox_cfg_st<br>
@@ -345,7 +345,7 @@
 		<p><code>CYG_IO_SET_CONFIG_CAN_MSGBUF<br>
 			</code></p>
 		<p>and exchanging  <code>cyg_can_msgbuf_cfg </code>data structures. The <i>cfg_id</i> field contains the configuration ID that tells the driver what to do with a message buffer, the <i>handle</i> field contains a reference to a certain message buffer and the <i>msg</i> field is necessary for configuration of message buffer parameters. The following configuration identifiers are supported:</p>
-		<p><code>CYGNUM_CAN_MSGBUF_RESET_ALL &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;// clears alle message buffers, no message will be received, all remote buffers deleted<br>
+		<p><code>CYGNUM_CAN_MSGBUF_RESET_ALL &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;// clears all message buffers, no message will be received, all remote buffers deleted<br>
 			</code><code>CYGNUM_CAN_MSGBUF_RX_FILTER_ALL &nbsp;&nbsp;&nbsp;// cfg driver for reception of all can messges<br>
 			</code><code>CYGNUM_CAN_MSGBUF_RX_FILTER_ADD &nbsp;&nbsp;&nbsp;// add single message filter<br>
 			</code><code>CYGNUM_CAN_MSGBUF_REMOTE_BUF_ADD &nbsp;&nbsp;// add new remote response buffer<br>
diff --git a/packages/io/can/current/include/can.h b/packages/io/can/current/include/can.h
--- a/packages/io/can/current/include/can.h
+++ b/packages/io/can/current/include/can.h
@@ -109,9 +109,9 @@ typedef struct can_lowlevel_funs can_low
 //
 typedef struct 
 {
-    void (*can_init)(can_channel *chan);              // Initialize the can channel
-    void (*xmt_msg)(can_channel *chan, void *pdata);  // transmit one single message
-    void (*rcv_event)(can_channel *chan, void *pdata);// indicate can event occurance
+    void (*can_init)(can_channel *chan);                   // Initialize the CAN channel
+    cyg_bool (*xmt_msg)(can_channel *chan, void *pdata);   // transmit one single message
+    cyg_bool (*rcv_event)(can_channel *chan, void *pdata); // indicate CAN event occurance
 } can_callbacks_t;
 
 
diff --git a/packages/io/can/current/include/canio.h b/packages/io/can/current/include/canio.h
--- a/packages/io/can/current/include/canio.h
+++ b/packages/io/can/current/include/canio.h
@@ -99,25 +99,46 @@ typedef enum {
 // hardware but normally these events should cover the most common CAN events
 // that may occur. A combination of the event type values is allowed.
 //
-typedef enum 
-{
-    CYGNUM_CAN_EVENT_RX                  = 0x0001, // message received
-    CYGNUM_CAN_EVENT_TX                  = 0x0002, // mesage transmitted
-    CYGNUM_CAN_EVENT_WARNING_RX          = 0x0004, // tx error counter (TEC) reached warning level (>96)
-    CYGNUM_CAN_EVENT_WARNING_TX          = 0x0008, // rx error counter (REC) reached warning level (>96)
-    CYGNUM_CAN_EVENT_ERR_PASSIVE         = 0x0010, // CAN "error passive" occured
-    CYGNUM_CAN_EVENT_BUS_OFF             = 0x0020, // CAN "bus off" error occured
-    CYGNUM_CAN_EVENT_OVERRUN_RX          = 0x0040, // overrun in RX queue or hardware occured
-    CYGNUM_CAN_EVENT_OVERRUN_TX          = 0x0080, // overrun in TX queue occured
-    CYGNUM_CAN_EVENT_CAN_ERR             = 0x0100, // a CAN bit or frame error occured
-    CYGNUM_CAN_EVENT_LEAVING_STANDBY     = 0x0200, // CAN hardware leaves standby / power don mode or is waked up
-    CYGNUM_CAN_EVENT_ENTERING_STANDBY    = 0x0400, // CAN hardware enters standby / power down mode
-    CYGNUM_CAN_EVENT_ARBITRATION_LOST    = 0x0800, // arbitration lost
-    CYGNUM_CAN_EVENT_FILTER_ERR          = 0x1000, // CAN message filter / acceptance filter error
-    CYGNUM_CAN_EVENT_PHY_FAULT           = 0x2000, // General failure of physical layer detected (if supported by hardware)
-    CYGNUM_CAN_EVENT_PHY_H               = 0x4000, // Fault on CAN-H detected (Low Speed CAN)
-    CYGNUM_CAN_EVENT_PHY_L               = 0x8000, // Fault on CAN-L detected (Low Speed CAN)
-} cyg_can_event_flags;
+#define CYGNUM_CAN_EVENT_RX                  0x00000001 // message received
+#define CYGNUM_CAN_EVENT_TX                  0x00000002 // mesage transmitted
+#define CYGNUM_CAN_EVENT_WARNING_RX          0x00000004 // tx error counter (TEC) reached warning level (>96)
+#define CYGNUM_CAN_EVENT_WARNING_TX          0x00000008 // rx error counter (REC) reached warning level (>96)
+#define CYGNUM_CAN_EVENT_ERR_PASSIVE         0x00000010 // CAN "error passive" occured
+#define CYGNUM_CAN_EVENT_BUS_OFF             0x00000020 // CAN "bus off" error occured
+#define CYGNUM_CAN_EVENT_OVERRUN_RX          0x00000040 // overrun in RX queue occured
+#define CYGNUM_CAN_EVENT_OVERRUN_TX          0x00000080 // overrun in TX queue occured
+#define CYGNUM_CAN_EVENT_CAN_ERR             0x00000100 // a CAN bit or frame error occured
+#define CYGNUM_CAN_EVENT_LEAVING_STANDBY     0x00000200 // CAN hardware leaves standby/power down mode or is waked up
+#define CYGNUM_CAN_EVENT_ENTERING_STANDBY    0x00000400 // CAN hardware enters standby/power down mode
+#define CYGNUM_CAN_EVENT_ARBITRATION_LOST    0x00000800 // arbitration lost
+#define CYGNUM_CAN_EVENT_FILTER_ERR          0x00001000 // CAN message filter / acceptance filter error
+#define CYGNUM_CAN_EVENT_PHY_FAULT           0x00002000 // General failure of physical layer detected (if supported by hardware)
+#define CYGNUM_CAN_EVENT_PHY_H               0x00004000 // Fault on CAN-H detected (Low Speed CAN)
+#define CYGNUM_CAN_EVENT_PHY_L               0x00008000 // Fault on CAN-L detected (Low Speed CAN)
+#define CYGNUM_CAN_EVENT_ERR_ACTIVE          0x00010000 // CAN controller now "error active"
+#define CYGNUM_CAN_EVENT_OVERRUN_RX_HW       0x00020000 // CAN controller reports a RX overrun
+
+typedef cyg_int32 cyg_can_event_flags_t;
+
+#define CYGNUM_CAN_EVENT_ALL                       \
+  CYGNUM_CAN_EVENT_RX                              \
+  |CYGNUM_CAN_EVENT_TX                             \
+  |CYGNUM_CAN_EVENT_WARNING_RX                     \
+  |CYGNUM_CAN_EVENT_WARNING_TX                     \
+  |CYGNUM_CAN_EVENT_ERR_PASSIVE                    \
+  |CYGNUM_CAN_EVENT_BUS_OFF                        \
+  |CYGNUM_CAN_EVENT_OVERRUN_RX                     \
+  |CYGNUM_CAN_EVENT_OVERRUN_TX                     \
+  |CYGNUM_CAN_EVENT_CAN_ERR                        \
+  |CYGNUM_CAN_EVENT_LEAVING_STANDBY                \
+  |CYGNUM_CAN_EVENT_ENTERING_STANDBY               \
+  |CYGNUM_CAN_EVENT_ARBITRATION_LOST               \
+  |CYGNUM_CAN_EVENT_FILTER_ERR                     \
+  |CYGNUM_CAN_EVENT_PHY_FAULT                      \
+  |CYGNUM_CAN_EVENT_PHY_H                          \
+  |CYGNUM_CAN_EVENT_PHY_L                          \
+  |CYGNUM_CAN_EVENT_ERR_ACTIVE                     \
+  |CYGNUM_CAN_EVENT_OVERRUN_RX_HW
 
 //
 // State of CAN controller
@@ -144,7 +165,9 @@ typedef enum e_cyg_can_mode
     CYGNUM_CAN_MODE_STOP,   // set controller into stop mode
     CYGNUM_CAN_MODE_START,  // set controller into operational mode
     CYGNUM_CAN_MODE_STANDBY,// set controller into standby / sleep mode
-    CYGNUM_CAN_MODE_CONFIG  // set controller and driver into a state where it is safe to add/delete message buffers
+    CYGNUM_CAN_MODE_CONFIG, // safe mode to add/delete message buffers
+    CYGNUM_CAN_MODE_LISTEN_ONLY_ENTER, // set controller into listen only mode.
+    CYGNUM_CAN_MODE_LISTEN_ONLY_EXIT   // set controller out of listen only mode.
 } cyg_can_mode;
 
 //
@@ -211,8 +234,8 @@ typedef struct st_cyg_can_message
 typedef struct cyg_can_event_st
 {
     cyg_uint32      timestamp;
+    cyg_can_event_flags_t flags;
     cyg_can_message msg;
-    cyg_uint16      flags;     
 } cyg_can_event;
 
 //
@@ -260,6 +283,16 @@ typedef struct cyg_can_timeout_info_st
 
 
 //
+// For reading error counter values from CAN controller
+//
+typedef struct cyg_can_err_count_info_st
+{
+    cyg_uint8 rx_err_count;
+    cyg_uint8 tx_err_count;
+} cyg_can_err_count_info;
+
+
+//
 // this data type defines a handle to a message buffer or message box
 // of the CAN hardware device
 //
@@ -277,6 +310,26 @@ typedef struct cyg_can_msgbox_cfg_st
 } cyg_can_msgbuf_cfg;
 
 //
+// structure for configuration of identifier range filtering
+//
+typedef struct cyg_can_filter_range_cfg_st
+{
+    cyg_can_id_type        ext;            // type of identifier concerned
+    cyg_uint32             lower_id_bound; // lower bound identifier (included)
+    cyg_uint32             upper_id_bound; // upper bound identifier (included)
+} cyg_can_filter_range_cfg;
+
+//
+// structure for configuration of identifier/mask filtering
+//
+typedef struct cyg_can_filter_mask_cfg_st
+{
+    cyg_can_id_type        ext;            // type of identifier concerned
+    cyg_uint32             id;             // identifier to use for filtering
+    cyg_uint32             mask;           // mask to apply for filtering
+} cyg_can_filter_mask_cfg;
+
+//
 // this data type defines a CAN message filter. It consits
 // of a handle to a message box or message buffer and a CAN message.
 // For the filtering only the id and the ext field of the CAN message are
@@ -306,7 +359,7 @@ typedef cyg_can_msgbuf_cfg cyg_can_remot
 // Support flags:
 // |   7   |   6   |   5   |   4   |   3    |   2   |   1   |   0    |
 // +-------+-------+-------+-------+--------+-------+-------+--------+
-// | res   |  res  |  res  |timest.|autobaud|FullCAN|   Frametype    |
+// |ListenO|Mask F |Range F|timest.|autobaud|FullCAN|   Frametype    |
 //
 typedef struct cyg_can_hdi_st
 {
@@ -324,7 +377,9 @@ typedef struct cyg_can_hdi_st
 #define CYGNUM_CAN_HDI_FULLCAN                 0x04 // controller supports more than one receive and transmit buffer
 #define CYGNUM_CAN_HDI_AUTBAUD                 0x08 // driver supports automatic baudrate detection
 #define CYGNUM_CAN_HDI_TIMESTAMP               0x10 // driver supports timestamps
-
+#define CYGNUM_CAN_HDI_RANGE_FILTERING         0x20 // driver supports identifier range filtering
+#define CYGNUM_CAN_HDI_MASK_FILTERING          0x40 // driver supports identifier mask filtering
+#define CYGNUM_CAN_HDI_LISTEN_ONLY             0x80 // driver supports 'listen-only' mode.
 
 //
 // Callback configuration structure.
@@ -339,7 +394,7 @@ typedef void (*cyg_can_event_cb_t)(cyg_u
 typedef struct cyg_can_callback_cfg_st
 {
     cyg_can_event_cb_t callback_func;              // callback function
-    cyg_uint16  flag_mask;                         // flags mask
+    cyg_can_event_flags_t flag_mask;               // flags mask
     CYG_ADDRWORD data;                             // data passed to callback
 } cyg_can_callback_cfg;
 
diff --git a/packages/io/can/current/src/can.c b/packages/io/can/current/src/can.c
--- a/packages/io/can/current/src/can.c
+++ b/packages/io/can/current/src/can.c
@@ -89,8 +89,8 @@ static Cyg_ErrNo can_set_config(cyg_io_h
 // Callback functions into upper layer driver
 //
 static void can_init(can_channel *chan);    
-static void can_rcv_event(can_channel *chan, void *pdata);
-static void can_xmt_msg(can_channel *chan, void *pdata);
+static cyg_bool can_rcv_event(can_channel *chan, void *pdata);
+static cyg_bool can_xmt_msg(can_channel *chan, void *pdata);
 
 //
 // Device I/O table
@@ -710,13 +710,14 @@ static cyg_bool can_select(cyg_io_handle
 //===========================================================================
 // Callback for received events
 //===========================================================================
-static void can_rcv_event(can_channel *chan, void *pdata)
+static cyg_bool can_rcv_event(can_channel *chan, void *pdata)
 {
     can_cbuf_t       *cbuf   = &chan->in_cbuf;
     CYG_CAN_EVENT_T  *prxbuf = (CYG_CAN_EVENT_T *)cbuf->pdata;
 #ifdef CYGOPT_IO_CAN_SUPPORT_CALLBACK
-    cyg_uint16        flags;
+    cyg_can_event_flags_t flags;
 #endif
+    cyg_bool          res    = false;
     
     //
     // cbuf is a ring buffer - if the buffer is full, then we overwrite the
@@ -730,6 +731,7 @@ static void can_rcv_event(can_channel *c
     prxbuf[cbuf->put].flags = 0; // clear flags because it is a new event
     if (chan->funs->getevent(chan, &prxbuf[cbuf->put], pdata))
     {
+        res = true;
         if (cbuf->data_cnt < cbuf->len)
         {
             cbuf->data_cnt++;
@@ -769,18 +771,21 @@ static void can_rcv_event(can_channel *c
     }
     
     cyg_drv_dsr_unlock();
+
+    return res;
 }
 
 
 //===========================================================================
 // Callback function for transmit events
 //===========================================================================
-static void can_xmt_msg(can_channel *chan, void *pdata)
+static cyg_bool can_xmt_msg(can_channel *chan, void *pdata)
 {
     can_cbuf_t        *cbuf    = &chan->out_cbuf;
     can_lowlevel_funs *funs    = chan->funs;  
     CYG_CAN_MSG_T     *ptxbuf  = (CYG_CAN_MSG_T *)cbuf->pdata;
     CYG_CAN_MSG_T     *pbuf_txmsg;
+    cyg_bool           res     = false;
 
     //
     // transmit messages as long as there are messages in the buffer 
@@ -793,6 +798,7 @@ static void can_xmt_msg(can_channel *cha
         {
             cbuf->get = (cbuf->get + 1) % cbuf->len;
             cbuf->data_cnt--;
+            res = true;
         }
         else
         {
@@ -809,7 +815,7 @@ static void can_xmt_msg(can_channel *cha
                     cyg_drv_cond_broadcast(&cbuf->wait);
                 }
             }
-            return;
+            return res;
         }
     } // while (cbuf->data_cnt > 0)
     funs->stop_xmit(chan);  // Done with transmit
@@ -819,6 +825,8 @@ static void can_xmt_msg(can_channel *cha
         cbuf->waiting = false;
         cyg_drv_cond_broadcast(&cbuf->wait);
     }            
+
+    return res;
 }
 
 
diff --git a/packages/io/common/current/ChangeLog b/packages/io/common/current/ChangeLog
--- a/packages/io/common/current/ChangeLog
+++ b/packages/io/common/current/ChangeLog
@@ -1,3 +1,28 @@
+2013-06-24  Uwe Kindler  <uwe.kindler@web.de>
+
+	* include/config_keys.h: Add config key
+	CYG_IO_GET_CONFIG_CAN_ERR_COUNTERS to read TX and RX error counters
+	from CAN hardware.
+
+2012-01-22  Bernard Fouché  <bernard.fouche@kuantic.com>
+
+	* include/config_keys.h: Add two new keys to configure CAN driver:
+	CYG_IO_SET_CONFIG_CAN_{RANGE,MASK}_FILTER. [ Bugzilla 1001453 ]
+
+2011-08-16  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* doc/io.sgml (Callbacks): Fixed prototypes of several functions,
+	reported by Stano Menuna. [ Bugzilla 1001293 ]
+
+2010-06-06 ccoutand <ccoutand@stmi.com>
+	*doc/io.sgml
+	Updated DEVIO_TABLE definition, missing select argument
+
+2010-05-25 ccoutand <ccoutand@stmi.com>
+	* include/config_keys.h: 
+	Add new key to ADC driver to flush data buffer:
+	CYG_IO_SET_CONFIG_ADC_DATA_FLUSH
+
 2008-08-08  Nick Garnett  <nickg@ecoscentric.com>
 
 	* include/config_keys.h: Add keys for ADC devices.
diff --git a/packages/io/common/current/doc/io.sgml b/packages/io/common/current/doc/io.sgml
--- a/packages/io/common/current/doc/io.sgml
+++ b/packages/io/common/current/doc/io.sgml
@@ -1091,7 +1091,7 @@ routines. This table is defined by the m
 
 
 <PROGRAMLISTING>
-DEVIO_TABLE(l, write, read, get_config, set_config)
+DEVIO_TABLE(l, write, read, select, get_config, set_config)
 </PROGRAMLISTING>
 
 <variablelist>
@@ -1111,6 +1111,11 @@ DEVIO_TABLE(l, write, read, get_config, 
     <function>cyg_io_read()</function>. </para></listitem>
   </varlistentry>
   <varlistentry>
+    <term>select</term>
+    <listitem><para>The function called as a result of
+    <function>cyg_io_select()</function>. </para></listitem>
+  </varlistentry>
+  <varlistentry>
     <term>get_config</term>
     <listitem><para>The function called as a result of
     <function>cyg_io_get_config()</function>.</para></listitem>
@@ -1433,11 +1438,11 @@ CYGINT_IO_SERIAL_BLOCK_TRANSFER&quot;). 
 functions are available as well:</PARA>
 
 <PROGRAMLISTING>
-bool (*data_xmt_req)(serial_channel *chan,
+xmt_req_reply_t (*data_xmt_req)(serial_channel *chan,
                      int space,
                      int* chars_avail,
                      unsigned char** chars)
-void (*data_xmt_done)(serial_channel *chan)
+void (*data_xmt_done)(serial_channel *chan, int chars_sent)
 </PROGRAMLISTING>
 
 <PARA>
@@ -1460,11 +1465,11 @@ driver must call <function>data_xmt_done
 
 
 <PROGRAMLISTING>
-bool (*data_rcv_req)(serial_channel *chan,
+rcv_req_reply_t (*data_rcv_req)(serial_channel *chan,
                      int avail,
                      int* space_avail,
                      unsigned char** space)
-void (*data_rcv_done)(serial_channel *chan)
+void (*data_rcv_done)(serial_channel *chan, int chars_rcvd)
 </PROGRAMLISTING>
 
 <PARA>Instead of calling <function>rcv_char()</function> with a single
diff --git a/packages/io/common/current/include/config_keys.h b/packages/io/common/current/include/config_keys.h
--- a/packages/io/common/current/include/config_keys.h
+++ b/packages/io/common/current/include/config_keys.h
@@ -140,6 +140,7 @@
 #define CYG_IO_GET_CONFIG_CAN_TIMEOUT               0x0804
 #define CYG_IO_GET_CONFIG_CAN_HDI                   0x0805
 #define CYG_IO_GET_CONFIG_CAN_STATE                 0x0806
+#define CYG_IO_GET_CONFIG_CAN_ERR_COUNTERS          0x0807
 
 #define CYG_IO_SET_CONFIG_CAN_INFO                  0x0881
 #define CYG_IO_SET_CONFIG_CAN_OUTPUT_DRAIN          0x0882
@@ -150,6 +151,8 @@
 #define CYG_IO_SET_CONFIG_CAN_MODE                  0x0887
 #define CYG_IO_SET_CONFIG_CAN_ABORT                 0x0888
 #define CYG_IO_SET_CONFIG_CAN_CALLBACK              0x0889
+#define CYG_IO_SET_CONFIG_CAN_RANGE_FILTER          0x088A
+#define CYG_IO_SET_CONFIG_CAN_MASK_FILTER           0x088B
 
 // ======== 0x900 ADC ========================================================
 // Get/Set configuration 'key' values for ADC I/O
@@ -159,6 +162,7 @@
 #define CYG_IO_SET_CONFIG_ADC_RATE                  0x0981
 #define CYG_IO_SET_CONFIG_ADC_ENABLE                0x0982
 #define CYG_IO_SET_CONFIG_ADC_DISABLE               0x0983
+#define CYG_IO_SET_CONFIG_ADC_DATA_FLUSH            0x0984
 
 // ======== 0x1000 Generic ===================================================
 // Get/Set configuration 'key' values that can apply to more than one
diff --git a/packages/io/eth/current/src/lwip/README b/packages/io/eth/current/src/lwip/README
deleted file mode 100644
--- a/packages/io/eth/current/src/lwip/README
+++ /dev/null
@@ -1,10 +0,0 @@
-An EPK of lwip is available from http://humans.iv.ro/jani which has the most
-up-to-date package (at least until it all gets integrated).
-
-It has just been tested on another ARM similar to the EB40 with CS89000
-and it works there too (that board has 128K of RAM).
-
-Alternatively, lw.diff is the diff against the lwip-0.5.3 tree. It contains
-eCos support + an eCos project sample based on unixsim. Look at
-lwip-0.5.3/proj/ecos to see how to use it. Modify the Makefile to suit
-your needs and to reflect your eCos project dir.
diff --git a/packages/io/fileio/current/ChangeLog b/packages/io/fileio/current/ChangeLog
--- a/packages/io/fileio/current/ChangeLog
+++ b/packages/io/fileio/current/ChangeLog
@@ -1,3 +1,18 @@
+2012-03-04  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* tests/fnmatch.c: Add missed CYG_TEST_INIT().
+
+2011-05-23  Manuel Borchers  <manuel@matronix.de>
+
+	* src/dir.cxx (rewinddir): Fix tracing of rewinddir().
+	* src/fio.h: Add new function entry macro (FILEIO_ENTRY_VOID).
+	[ Bugzilla 1001243 ]
+
+2010-02-08  Jay Foster <jay@systech.com>
+
+	* tests/pselect.c: Corrected return value of pthread_kill()
+	to match POSIX standard.
+
 2008-11-18  Rutger Hofman <rutger@cs.vu.nl>
 
 	* src/file.cxx: add a chmod() call, implemented by calling
diff --git a/packages/io/fileio/current/src/dir.cxx b/packages/io/fileio/current/src/dir.cxx
--- a/packages/io/fileio/current/src/dir.cxx
+++ b/packages/io/fileio/current/src/dir.cxx
@@ -214,7 +214,7 @@ extern int readdir_r( DIR *dirp, struct 
 
 extern void rewinddir( DIR *dirp )
 {
-    FILEIO_ENTRY();
+    FILEIO_ENTRY_VOID();
 
     int fd = (int)dirp;
 
diff --git a/packages/io/fileio/current/src/fio.h b/packages/io/fileio/current/src/fio.h
--- a/packages/io/fileio/current/src/fio.h
+++ b/packages/io/fileio/current/src/fio.h
@@ -139,6 +139,11 @@ typedef int sigset_t;
     CYG_REPORT_FUNCTYPE( "returning %d" );      \
     CYG_FILEIO_FUNCTION_START();                \
 
+#define FILEIO_ENTRY_VOID()                     \
+    CYG_REPORT_FUNCTION();                      \
+    CYG_FILEIO_FUNCTION_START();                \
+
+
 // Do a fileio package defined return. This requires the error code
 // to be placed in errno, and if it is non-zero, -1 returned as the
 // result of the function. This also gives us a place to put any
diff --git a/packages/io/fileio/current/tests/fnmatch.c b/packages/io/fileio/current/tests/fnmatch.c
--- a/packages/io/fileio/current/tests/fnmatch.c
+++ b/packages/io/fileio/current/tests/fnmatch.c
@@ -119,6 +119,8 @@ int main( int argc, char **argv )
     { 0,           FNM_PERIOD|FNM_PATHNAME, "/.abc", "/.abc" }
   };
   
+  CYG_TEST_INIT();
+
   for (i=0; i < CYG_NELEM(test_case); i++) {
     if (test_case[i].result != 
         fnmatch(test_case[i].pattern,
diff --git a/packages/io/fileio/current/tests/pselect.c b/packages/io/fileio/current/tests/pselect.c
--- a/packages/io/fileio/current/tests/pselect.c
+++ b/packages/io/fileio/current/tests/pselect.c
@@ -273,7 +273,8 @@ void *pthread_entry2( void *arg)
         nanosleep( &zzz, NULL );
 
         err = pthread_kill( thread1, SIGUSR1 );
-        if( err < 0 ) SHOW_RESULT( pthread_kill, err );
+        if( err != 0 )
+            diag_printf("INFO: pthread_kill() returned %d %s\n", err, strerror(err));
 
         sigusr1_sent++;
 
diff --git a/packages/io/flash/current/ChangeLog b/packages/io/flash/current/ChangeLog
--- a/packages/io/flash/current/ChangeLog
+++ b/packages/io/flash/current/ChangeLog
@@ -1,3 +1,19 @@
+2011-12-21  John Dallaway  <john@dallaway.org.uk>
+
+	* doc/flash.sgml: Fix block_info field name. Issue reported by Keith
+	Smith. [ Bugzilla 1001431 ]
+
+2011-05-13  John Dallaway  <john@dallaway.org.uk>
+
+	* doc/flash.sgml: Fix cyg_flash_get_into_addr() function name. Issue
+	reported by Christophe Coutand. [ Bugzilla 1001233 ]
+
+2010-05-15  Christophe Coutand <ccoutand@stmi.com>
+
+	* src/flashiodev.c (flashiodev_lookup): Fix wrong code execution if
+	CYGFUN_IO_FLASH_BLOCK_FROM_FIS is enabled and
+	CYGFUN_IO_FLASH_BLOCK_FROM_DEVOFFSET is disabled.
+
 2010-03-25  Daniel Helgason  <dhelgason@shaw.ca>
 
 	* cdl/io_flash.cdl: Fix "requires" constraint on
@@ -706,7 +722,7 @@ 2000-07-29  Gary Thomas  <gthomas@redhat
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2005, 2006, 2008, 2009, 2010 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2005, 2006, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/io/flash/current/doc/flash.sgml b/packages/io/flash/current/doc/flash.sgml
--- a/packages/io/flash/current/doc/flash.sgml
+++ b/packages/io/flash/current/doc/flash.sgml
@@ -11,7 +11,7 @@
 <!-- =============================================================== -->
 <!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
 <!-- =============================================================== -->
-<!-- Copyright (C) 2004, 2005, 2006, 2007, 2009 Free Software Foundation, Inc. -->
+<!-- Copyright (C) 2004, 2005, 2006, 2007, 2009, 2011 Free Software Foundation, Inc. -->
 <!-- This material may be distributed only subject to the terms      -->
 <!-- and conditions set forth in the Open Publication License, v1.0  -->
 <!-- or later (the latest version is presently available at          -->
@@ -154,7 +154,7 @@ typedef struct {
     cyg_flashaddr_t              start;          // First address
     cyg_flashaddr_t              end;            // Last address
     cyg_uint32                   num_block_infos;// Number of entries
-    const cyg_flash_block_info_t *blocks_info;   // Info about one block size
+    const cyg_flash_block_info_t *block_info;    // Info about one block size
 } cyg_flash_info_t;
 </PROGRAMLISTING>
 
@@ -165,7 +165,7 @@ flash devices, starting from 0. If the d
 structure pointed to by <PARAMETER>info</PARAMETER> is filled in and
 <LITERAL>CYG_FLASH_ERR_OK</LITERAL> is returned, otherwise
 <LITERAL>CYG_FLASH_ERR_INVALID</LITERAL>.
-<FUNCTION>cyg_flash_get_info()</FUNCTION> is similar, but returns the
+<FUNCTION>cyg_flash_get_info_addr()</FUNCTION> is similar, but returns the
 information about the flash device at the given address.
 <FUNCTION>cyg_flash_block_size()</FUNCTION> returns the size of the
 block at the given address.  <FUNCTION>cyg_flash_verify_addr()
diff --git a/packages/io/flash/current/src/flashiodev.c b/packages/io/flash/current/src/flashiodev.c
--- a/packages/io/flash/current/src/flashiodev.c
+++ b/packages/io/flash/current/src/flashiodev.c
@@ -247,7 +247,10 @@ flashiodev_lookup(struct cyg_devtab_entr
         start = flash_base;
         end = flash_base + size - 1;
         valid = true;
-    } else
+    }
+# ifdef CYGFUN_IO_FLASH_BLOCK_FROM_DEVOFFSET
+    else
+# endif
 #endif // ifdef CYGFUN_IO_FLASH_BLOCK_FROM_FIS
 #ifdef CYGFUN_IO_FLASH_BLOCK_FROM_DEVOFFSET
     // Next, support device numbers with offsets encoded in path name
diff --git a/packages/io/i2c/current/ChangeLog b/packages/io/i2c/current/ChangeLog
--- a/packages/io/i2c/current/ChangeLog
+++ b/packages/io/i2c/current/ChangeLog
@@ -1,3 +1,8 @@
+2013-04-10  Ilija Kocho <ilijak@siva.com.mk
+
+	* include/i2c.h: Add CYGBLD_I2C_DEVICE_CONST. This will allow driver
+	to modify cyg_i2c_device streucture. [ Bugzilla 1001816 ]
+
 2009-02-09  Bart Veer  <bartv@ecoscentric.com>
 
 	* cdl/i2c.cdl, src/i2c.cxx, doc/i2c.sgml: I2C buses now initialize
diff --git a/packages/io/i2c/current/include/i2c.h b/packages/io/i2c/current/include/i2c.h
--- a/packages/io/i2c/current/include/i2c.h
+++ b/packages/io/i2c/current/include/i2c.h
@@ -82,6 +82,10 @@ typedef struct cyg_i2c_device {
 // The information needed for interacting over a particular I2C bus.
 // Most hardware will only have one bus, but multiple buses are
 // supported. Thread synchronization happens on a per-bus level.
+#ifndef CYGBLD_I2C_DEVICE_CONST
+#define CYGBLD_I2C_DEVICE_CONST const
+#endif
+
 typedef struct cyg_i2c_bus {
     cyg_drv_mutex_t         i2c_lock;
 #ifdef CYGDBG_USE_ASSERTS
@@ -89,8 +93,8 @@ typedef struct cyg_i2c_bus {
 #endif
     // The hardware-specific functions that do the real work
     void                    (*i2c_init_fn)(struct cyg_i2c_bus*);
-    cyg_uint32              (*i2c_tx_fn)(const cyg_i2c_device*, cyg_bool, const cyg_uint8*, cyg_uint32, cyg_bool);
-    cyg_uint32              (*i2c_rx_fn)(const cyg_i2c_device*, cyg_bool, cyg_uint8*, cyg_uint32, cyg_bool, cyg_bool);
+    cyg_uint32              (*i2c_tx_fn)(CYGBLD_I2C_DEVICE_CONST cyg_i2c_device*, cyg_bool, const cyg_uint8*, cyg_uint32, cyg_bool);
+    cyg_uint32              (*i2c_rx_fn)(CYGBLD_I2C_DEVICE_CONST cyg_i2c_device*, cyg_bool, cyg_uint8*, cyg_uint32, cyg_bool, cyg_bool);
     void                    (*i2c_stop_fn)(const cyg_i2c_device*);
     // A spare field for use by the driver
     void*                   i2c_extra;
diff --git a/packages/io/serial/current/ChangeLog b/packages/io/serial/current/ChangeLog
--- a/packages/io/serial/current/ChangeLog
+++ b/packages/io/serial/current/ChangeLog
@@ -1,3 +1,21 @@
+2012-03-13  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* tests/serial1.c: Fix compiler warning about variable that is set but
+	not used.
+	* tests/tty1.c: Ditto.
+
+2011-03-28  Ilija Kocho  <ilijak@siva.com.mk>
+	    Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* src/common/termiostty.c: Add a possibility to define a few
+	additional DEVTAB entries.
+	* src/common/tty.c: Same.
+
+2010-06-02	Jay Foster	<jay@systech.com>
+
+	* src/common/termios.c : Fix tcflush() and tcdrain().  They were
+	effectively no-op functions.
+
 2008-09-02  Steven Clugston  <steven.clugston@ncl.ac.uk>
 
 	* tests/ser_test_protocol.inl : Add mpc555 generic platform
diff --git a/packages/io/serial/current/src/common/termios.c b/packages/io/serial/current/src/common/termios.c
--- a/packages/io/serial/current/src/common/termios.c
+++ b/packages/io/serial/current/src/common/termios.c
@@ -263,7 +263,7 @@ tcdrain( int fildes )
 
     ret = fp->f_ops->fo_getinfo( fp,
                                  CYG_IO_GET_CONFIG_SERIAL_OUTPUT_DRAIN,
-                                 NULL, 0 );
+                                 NULL, 1 );
     cyg_fp_free( fp );
 
     if ( ret > 0 ) {
@@ -302,17 +302,17 @@ tcflush( int fildes, int queue_sel )
     case TCIOFLUSH:
         ret = fp->f_ops->fo_getinfo( fp,
                                      CYG_IO_GET_CONFIG_SERIAL_OUTPUT_FLUSH,
-                                     NULL, 0 );
+                                     NULL, 1 );
         // fallthrough
     case TCIFLUSH:
         ret = fp->f_ops->fo_getinfo( fp,
                                      CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH,
-                                     NULL, 0 );
+                                     NULL, 1 );
         break;
     case TCOFLUSH:
         ret = fp->f_ops->fo_getinfo( fp,
                                      CYG_IO_GET_CONFIG_SERIAL_OUTPUT_FLUSH,
-                                     NULL, 0 );
+                                     NULL, 1 );
         break;
     default:
         ret = EINVAL;
diff --git a/packages/io/serial/current/src/common/termiostty.c b/packages/io/serial/current/src/common/termiostty.c
--- a/packages/io/serial/current/src/common/termiostty.c
+++ b/packages/io/serial/current/src/common/termiostty.c
@@ -166,6 +166,11 @@ DEVTAB_ENTRY(termios_io3,
              &termios_private_info3);
 #endif
 
+// More DEVTAB entries can be added using an inclusion
+#ifdef CYGDAT_IO_SERIAL_TERMIOS_ADD_INL
+# include CYGDAT_IO_SERIAL_TERMIOS_ADD_INL
+#endif
+
 static const cc_t c_cc_init[ NCCS ] = { 
     0x04,     /* EOF == ^D */
     0,        /* EOL */
diff --git a/packages/io/serial/current/src/common/tty.c b/packages/io/serial/current/src/common/tty.c
--- a/packages/io/serial/current/src/common/tty.c
+++ b/packages/io/serial/current/src/common/tty.c
@@ -137,6 +137,11 @@ DEVTAB_ENTRY(tty_io3,
              &tty_private_info3);
 #endif
 
+// More DEVTAB entries can be added using an inclusion
+#ifdef CYGDAT_IO_SERIAL_TTY_ADD_INL
+# include CYGDAT_IO_SERIAL_TTY_ADD_INL
+#endif
+
 static bool 
 tty_init(struct cyg_devtab_entry *tab)
 {
diff --git a/packages/io/serial/current/tests/serial1.c b/packages/io/serial/current/tests/serial1.c
--- a/packages/io/serial/current/tests/serial1.c
+++ b/packages/io/serial/current/tests/serial1.c
@@ -75,7 +75,6 @@ void
 serial_api_test(int dummy)
 {
     cyg_io_handle_t handle;
-    int res;
     cyg_uint32 len;
     unsigned char buffer[16];
 
@@ -88,8 +87,8 @@ serial_api_test(int dummy)
     test_open_ser(&handle);
 
     // read & write
-    res = cyg_io_read(handle, &buffer[0], &len);
-    res = cyg_io_write(handle, &buffer[0], &len);
+    cyg_io_read(handle, &buffer[0], &len);
+    cyg_io_write(handle, &buffer[0], &len);
 
     // cyg_io_get_config
     cyg_io_get_config(handle, 
diff --git a/packages/io/serial/current/tests/tty1.c b/packages/io/serial/current/tests/tty1.c
--- a/packages/io/serial/current/tests/tty1.c
+++ b/packages/io/serial/current/tests/tty1.c
@@ -74,7 +74,6 @@ cyg_handle_t thread_handle;
 void
 tty_api_test(cyg_io_handle_t* handle)
 {
-    int res;
     cyg_uint32 len;
     unsigned char buffer[16];
 
@@ -85,8 +84,8 @@ tty_api_test(cyg_io_handle_t* handle)
     CYG_TEST_FAIL_FINISH("Not reached");
 
     // read & write
-    res = cyg_io_read(handle, &buffer[0], &len);
-    res = cyg_io_write(handle, &buffer[0], &len);
+    cyg_io_read(handle, &buffer[0], &len);
+    cyg_io_write(handle, &buffer[0], &len);
 
     // cyg_io_get_config
     // TTY layer
diff --git a/packages/io/usb/msd/slave/current/ChangeLog b/packages/io/usb/msd/slave/current/ChangeLog
new file mode 100644
--- /dev/null
+++ b/packages/io/usb/msd/slave/current/ChangeLog
@@ -0,0 +1,44 @@
+2010-11-13  John Dallaway  <john@dallaway.org.uk>
+
+     * cdl/usbs_msd.cdl: Reference per-package documentation.
+
+2010-11-13  Christophe Coutand  <ccoutand@stmi.com>
+
+     * doc/usbs_msd.sgml: Added package documentation
+
+2010-11-12  Christophe Coutand  <ccoutand@stmi.com>
+
+     *include/usbs_msd_opcode.h
+     *include/usbs_msd_io.h
+     *include/usbs_msd.h
+     *include/usbs_msd.inl
+     *include/usbs_msd_scsi.h
+     *tests/usbs_test_ramdisk.c
+     *src/usbs_msd_handler.c
+     *src/usbs_msd_scsi.c
+     *src/usbs_msd.c
+     *cdl/usbs_msd.cdl: Initial contribution. [ Bugzilla 1000987 ]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/packages/io/usb/msd/slave/current/cdl/usbs_msd.cdl b/packages/io/usb/msd/slave/current/cdl/usbs_msd.cdl
new file mode 100644
--- /dev/null
+++ b/packages/io/usb/msd/slave/current/cdl/usbs_msd.cdl
@@ -0,0 +1,364 @@
+# ====================================================================
+#
+#      usbs_msd.cdl
+#
+#      USB slave-side mass storage package.
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      USB Slave Mass Storage, ccoutand <ccoutand@stmi.com>
+#    
+# Contributors:   jld
+# Date:           2010-06-04
+#
+#####DESCRIPTIONEND####
+# ====================================================================
+
+cdl_package CYGPKG_IO_USB_SLAVE_MSD {
+
+    display     "USB slave mass storage support"
+    include_dir "cyg/io/usb"
+    parent      CYGPKG_IO_USB_SLAVE
+    doc         ref/io-usb-slave-msd.html
+
+    requires    { CYGPKG_KERNEL }
+    requires    { CYGPKG_IO_DISK }
+    requires    { CYGHWR_IO_USB_SLAVE_OUT_ENDPOINTS >= 1 }
+    requires    { CYGHWR_IO_USB_SLAVE_IN_ENDPOINTS >= 1 }
+
+    compile     usbs_msd.c usbs_msd_handler.c usbs_msd_scsi.c
+
+    implements  CYGINT_IO_USB_SLAVE_CLIENTS
+
+    define_proc {
+      puts $::cdl_system_header "#define CYGDAT_IO_USB_SLAVE_MSD_INL <cyg/io/usb/usbs_msd.inl>"
+    }    
+
+    description "
+        The USB slave mass storage device (MSD) package supports 
+        the development of USB peripherals which act has mass storage
+        device to the host machine. The actual storage must be implemented
+        on top of the disk package."
+
+    # 
+    # Mass Storage Device 0
+    #
+    cdl_component CYGPKG_IO_USB_SLAVE_MSD0 {
+       display        "USB slave mass storage support for device 0"
+       flavor         bool
+       default_value  1
+       description "
+           This option implement the USB MSD device 0."
+
+       cdl_option CYGDAT_IO_USB_SLAVE_MSD0_SUB_CLASS_TYPE {
+           display         "Mass-storage Device USB Sub Class"
+           flavor          data
+           default_value   { "SCSI" }
+           legal_values    { "SCSI" "RBC" }
+           description     "
+               Specify the transport protocols and command code systems
+               transported by the interface. Currently only the SCSI
+               transparent command set is implemented."
+       }
+
+       cdl_option CYGDAT_IO_USB_SLAVE_MSD0_EP0 {
+           display       "Name of EP0 structure"
+           flavor        data               
+           default_value { "usbs_at91_ep0" }
+           description   "
+               The name of the variable that contains the endpoint 0
+               structure.  This should be set to the EP0 structure for
+               the desired USB device driver such as usbs_at91_ep0,
+               usbs_sa11x0_ep0, etc"
+       }
+
+       cdl_option CYGNUM_IO_USB_SLAVE_MSD0_EP0_MAX_PACKET_SIZE {
+           display       "The size of EP0"
+           flavor        data
+           default_value 8
+           legal_values  { 8 16 64 } 
+           description   "
+               The size of the EP0 hardware buffer on the specific USB
+               chip used."
+       } 
+
+
+       cdl_component CYGPKG_IO_USB_SLAVE_MSD0_STATIC_EP {
+           display         "Use static I/O endpoint structures"
+           flavor          bool
+           default_value   1
+           description     "
+               Enables the use of static I/O endpoint structures. Some
+               USB slave device drivers implement dynamic endpoint
+               configuration and therefore require this component to be
+               disabled."
+
+           cdl_option  CYGDAT_IO_USB_SLAVE_MSD0_TX_EP {
+               display         "The Tx (USB IN) endpoint structure"
+               flavor         data               
+               default_value  { "usbs_at91_ep1" }
+               description    "
+                   The endpoint structure that corresponds to the selected
+                   Tx endpoint number. This is dependent on the USBS device
+                   driver selected, and could be usbs_at91_ep1,
+                   usbs_sa11x0_ep1, etc"
+           }
+       
+           cdl_option CYGDAT_IO_USB_SLAVE_MSD0_RX_EP {
+               display         "The Rx (USB OUT) endpoint structure"
+               flavor         data               
+               default_value  { "usbs_at91_ep2" }
+               description    "
+                   The endpoint structure that corresponds to the selected
+                   Rx endpoint number. This is dependent on the USBS device
+                   driver selected, and could be usbs_at91_ep2,
+                   usbs_sa11x0_ep2, etc"
+          }
+       }
+
+       cdl_option CYGNUM_IO_USB_SLAVE_MSD0_TX_EP_NUM {
+           display       "Tx (USB IN) endpoint number"
+           flavor        data
+           default_value 1
+           description   "
+               The endpoint that should be used for the device-side
+               transmitter, which is the USB IN direction."
+       }
+       
+       cdl_option CYGNUM_IO_USB_SLAVE_MSD0_TX_EP_MAX_PACKET_SIZE {
+           display       "Tx (USB IN) endpoint sze"
+           flavor        data
+           default_value 64
+           legal_values  { 32 64 128 256 512 } 
+           description   "
+               The size of the Tx EP hardware buffer on the specific USB
+               chip used."
+       }        
+
+       cdl_option CYGNUM_IO_USB_SLAVE_MSD0_RX_EP_NUM {
+           display         "Rx (USB OUT) endpoint number"
+           flavor          data
+           default_value   2
+           description     "
+               The endpoint that should be used for the device-side
+               receiver, which is the USB OUT direction."
+       } 
+
+       cdl_option CYGNUM_IO_USB_SLAVE_MSD0_RX_EP_MAX_PACKET_SIZE {
+           display       "Rx (USB OUT) endpoint size"
+           flavor        data
+           default_value 64
+           legal_values  { 32 64 128 256 512} 
+           description   "
+               The size of the Rx EP hardware buffer on the specific USB
+               chip used."
+       }  
+       
+       cdl_option CYGNUM_IO_USB_SLAVE_MSD0_VENDOR_ID {
+           display       "USB Forum Vendor ID"
+           flavor        data
+           default_value 0xFFFF
+           legal_values  1 to 0xFFFF
+           description   "
+               Each USB vendor has an Vendor ID allocated to it by the
+               USB-IF organization.  Any arbitrary value can be selected
+               for testing provided that it doesn't conflict with devices
+               on the development host, but a device should NEVER be
+               released publicly without a valid Vendor ID"
+       }
+
+       cdl_option CYGNUM_IO_USB_SLAVE_MSD0_PRODUCT_ID {
+           display       "USB product ID"
+           flavor        data
+           default_value 1
+           legal_values  1 to 0xFFFF
+           description   "
+               You are free to select an arbitrary 16-bit Product ID for
+               a device. The combination of Vendor ID and Product ID
+               uniquely identified a USB device."
+       }
+
+       cdl_option CYGDAT_IO_USB_SLAVE_MSD0_MFG_STR {
+          display       "The Device Vendor's Name (Manufacturer String)"
+           flavor        data
+           default_value { "\"eCos\"" }
+           description "
+                   The standard USB enumeration allows for a
+                   manufacturer's name which is normally reported to the
+                   user when the device is first plugged into the host."
+       }
+
+       cdl_option CYGDAT_IO_USB_SLAVE_MSD0_PRODUCT_STR {
+           display       "The Device Product Name"
+           flavor        data
+           default_value { "\"eCos USB Mass Storage Device\"" }
+           description "
+                   The standard USB enumeration allows for a product name
+                   which is normally reported to the user when the device
+                   is first plugged into the host."
+       }
+
+       cdl_option CYGDAT_IO_USB_SLAVE_MSD0_SERIAL_STR {
+           display       "The Device Product Serial Number"
+           flavor        data
+           default_value { "\"123456789AB\"" }
+           description "
+                   The standard USB enumeration allows for a serial number."
+       }
+       
+        cdl_option CYGDAT_IO_USB_SLAVE_MSD0_LUN0_NAME {
+           display       "LUN0 entry name"
+           flavor        data
+           default_value { "\"/dev/ramdisk0/1\"" }
+           description "
+               Specify the logical unit 0 devtab entry name. The default value
+               correspond to the partition 1 of the RAM disk created in the
+               USBS mass storage example application."
+       }               
+       
+       cdl_option CYGOPT_IO_USB_SLAVE_MSD0_BUSPOWERED {
+           display       "The Device is bus powered"
+           default_value 0
+           flavor        bool
+           description   "
+               Tells the host whether the Device is a bus powered
+               device or a self powered device."
+       }
+
+       cdl_option CYGNUM_IO_USB_SLAVE_MSD0_CURRENTDRAW {
+           display       "Maximum current (in mA) drawn from USB bus"
+           flavor        data
+           default_value 100
+           legal_values  1 to 500
+           requires      { (CYGNUM_IO_USB_SLAVE_MSD_CURRENTDRAW > 100) 
+                         implies CYGOPT_IO_USB_SLAVE_MSD_BUSPOWERED }
+           description   "
+               The maximum current drawn by the Device from the USB bus.
+               It should report the peak value. A self powered device
+               can draw up to 100mA, a bus powered device can draw up to
+               500mA. (If it is sometimes below 100mA and sometimes over,
+               then a transition could be done at runtime between self and
+               bus powered modes, but that would be complicated and the
+               device would have to return from configured to addressed
+               state. For details, see the USB specification.)"
+       }
+
+    }
+
+    cdl_option  CYGBLD_IO_USB_SLAVE_MSD_DEBUG {
+        display       "Enable debug output from the driver"
+        default_value 0
+        flavor        bool
+        description   "
+            The driver may produce debug output which can be
+            useful to work out why it is not working as expected."
+    }
+    
+    cdl_option  CYGBLD_IO_USB_SLAVE_MSD_TRACE {
+        display       "Enable trace output from the driver"
+        default_value 0
+        flavor        bool
+        description   "
+            Allow tracing of every USB transaction for debugging 
+            purpose."
+    }    
+
+    cdl_option CYGSEM_IO_USB_SLAVE_MSD_STALL_ENABLE {
+        display       "Enable application to stall endpoints"
+        default_value 0
+        flavor        bool
+        description   "
+            A mass storage device must stall one or both bulk endpoints in 
+            several situations. However, not all USB device drivers seems
+            to implement this functionality correctly. Hence this option is
+            disable be default. Testing shows that both Linux and Windows can
+            handle mass storage with stall disable."
+    }   
+
+    cdl_component CYGPKG_IO_USB_SLAVE_MSD_OPTIONS {
+    display     "Build options"
+    flavor      none
+
+    description "
+        Package-specific build options including control over compiler
+        flags used only in building this package."
+
+        cdl_option CYGPKG_IO_USB_SLAVE_MSD_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building this package. These flags are used in addition
+                to the set of global flags."
+        }
+ 
+        cdl_option CYGPKG_IO_USB_SLAVE_MSD_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building this package. These flags are removed from
+                the set of global flags if present."
+        }
+        
+        cdl_component CYGBLD_IO_USB_SLAVE_MSD_EXAMPLES {
+            display "Build example programs"
+            no_define     
+            description "
+                Enabling this option will cause the example program
+                to be built using the normal test case infrastructure."
+            
+             cdl_option CYGPKG_IO_USB_SLAVE_MSD_TESTS {
+                 display "USBS MSD example/test program"
+                 no_define
+                 flavor data
+                 calculated { "tests/usbs_test_ramdisk" }
+                 description "
+                     usbs_test_ramdisk creates a tiny FAT12 file-system
+                     on top of a 'ram disk' device. The USB MSD service is
+                     started and the disk should appear at the host side as
+                     a regular mass storage device. If the FAT file-system 
+                     package is included, some files will be created prior to
+                     the USB MSD device to be started."
+             }
+        }
+
+    }
+}
diff --git a/packages/io/usb/msd/slave/current/doc/usbs_msd.sgml b/packages/io/usb/msd/slave/current/doc/usbs_msd.sgml
new file mode 100644
--- /dev/null
+++ b/packages/io/usb/msd/slave/current/doc/usbs_msd.sgml
@@ -0,0 +1,275 @@
+<!-- DOCTYPE reference  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                         -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     usbs_msd.sgml                                               -->
+<!--                                                                 -->
+<!--     USB slave-side Mass Storage Support package.                -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2010 Free Software Foundation, Inc.               -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   ccoutand                                           -->
+<!-- Contact(s):                                                     -->
+<!-- Date:        2010/11/13                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<part id="io-usb-slave-msd">
+  <!-- reference id="io-usb-slave-msd" -->
+  <title>eCos Support for USB Mass Storage Peripherals</title>
+  
+  <!-- {{{ Intro                          -->
+  
+  <refentry id="usbs-msd-intro">
+    <refmeta>
+      <refentrytitle>Introduction</refentrytitle>
+    </refmeta>
+    <refnamediv>
+      <refname>Introduction</refname>
+      <refpurpose>
+        eCos support for USB Mass Storage Peripherals
+      </refpurpose>
+    </refnamediv>
+    
+    <refsect1><title>Introduction</title>
+      <para>
+        Currently, the eCos USB-Mass Storage Device (MSD) slave package  
+        provides support only for the SCSI transparent command set. The 
+        package flexibility allows future extension for other sub-class, 
+        .i.e. RBC, UFI etc..
+        The package requires the actual storage media to use the eCos disk
+        interface. Disk sector size is assumed 512 bytes.
+      </para>
+      <para>
+        The USB-MSD package is not tied to any specific
+        hardware. It requires the presence of USB hardware on the
+        target and a suitable device driver to make endpoints
+        available for this code to use. The configuration system
+        cannot load the eCos package automatically for specific
+        targets, in the way that a USB device driver or an ethernet
+        driver can be loaded automatically. Instead, the package has
+        to be added explicitly. When using the command line tools this
+        will involve an operation like the following:
+      </para>
+      <screen width=72 format=linespecific>
+        $ ecosconfig add usbs_msd
+      </screen>
+      <para>
+        Typically, this will automatically cause the USB device driver
+        to become active. The USB-Mass Storage Device driver runs as a 
+        thread, therefore requires the kernel package to be active. To
+        start the MSD interface, user must call the <literal>usbs_msd_start()</literal> 
+        function. No other user intervention is required. 
+        The MSD driver will interact directly with the storage media. 
+        Care should be taken not to mount/use the filesystem present on 
+        the media while used as a mass storage. This could potentially 
+        damage the filesystem.
+      </para>
+    </refsect1>
+  </refentry>
+  
+  <!-- }}} -->
+  <!-- {{{ Config                          -->
+  
+  <refentry id="usbs-msd-config">
+    <refmeta>
+      <refentrytitle>Configuration</refentrytitle>
+    </refmeta>
+    <refnamediv>
+      <refname>Configuration</refname>
+      <refpurpose>Configuration USB Mass Storage Peripherals</refpurpose>
+    </refnamediv>
+    
+    <refsect1><title>Configuration</title>
+      <para>
+        The USB Mass Storage Device interface uses the bulk transfer mode. It needs 
+        three endpoints for the communication with the host to be complete. 
+        The control endpoint (commonly EP0), the transmission and reception 
+        endpoints. The default CDL file contains configuration for 
+        the USB-Mass Storage Device 0. While it is uncommon to have several USB 
+        ports on a device, it is not impossible, hence user can update the package and 
+        create a second device .e.g. MSD1.
+      </para>
+
+      <refsect2><title>Endpoints</title>     
+      <para>
+        Each endpoint shall be configured according to the underlying hardware.
+        The endpoints configuration includes, the structure name, endpoint number 
+        and buffer size according to the USB chip specification.
+
+        The control endpoint is selected with
+        <literal>CYGDAT_IO_USB_SLAVE_MSD0_EP0</literal>. 
+        The default values is set to <literal>"usbs_at91_ep0"</literal>. This is the control
+        endpoint for the Atmel AT91 USB device driver. 
+
+         The TX and RX endpoints can be assigned statically or dynamically (assuming the USB
+         device driver supports it). In case of static configuration, the bulk IN and bulk OUT
+         endpoints are configured with <literal>CYGDAT_IO_USB_SLAVE_MSD0_TX_EP</literal> 
+         and <literal>CYGDAT_IO_USB_SLAVE_MSD0_RX_EP</literal> respectively.
+
+        In addition, the  TX and RX enpoints number must be provided by the user. 
+        They are configured with  <literal>CYGNUM_IO_USB_SLAVE_MSD0_TX_EP_NUM</literal> 
+        and <literal>CYGNUM_IO_USB_SLAVE_MSD0_RX_EP_NUM</literal>
+
+        In case of dynamic endpoints configuration, only the endpoint number is mandatory.
+      </para>
+
+      <para>
+        The last endpoints configuration parameters are the entpoints buffer size. They are set with:
+      <programlisting>
+      CYGNUM_IO_USB_SLAVE_MSD0_EP0_MAX_PACKET_SIZE
+      CYGNUM_IO_USB_SLAVE_MSD0_TX_EP_MAX_PACKET_SIZE
+      CYGNUM_IO_USB_SLAVE_MSD0_RX_EP_MAX_PACKET_SIZE
+      </programlisting>
+        A mass storage device must stall one or both bulk endpoints in 
+        several situations. However, not all eCos USB device drivers seems
+        to implement this functionality correctly. Hence, this option is
+        disable by default. Testing shows that both Linux and Windows can
+        handle mass storage device with stall disable as long as all data transfer phase
+        are handled correctly. Enpoint stall can be enable with
+        <literal>CYGSEM_IO_USB_SLAVE_MSD_STALL_ENABLE</literal>.
+      </para>
+      </refsect2>
+      <refsect2><title>Enumeration</title>  
+      <para>
+        The USB MSD device will make its vendor:product ID known to
+        the host. This should be configured
+        with <literal>CYGNUM_IO_USB_SLAVE_MSD0_VENDOR_ID</literal> and
+        <literal>CYGNUM_IO_USB_SLAVE_MSD0_PRODUCT_ID</literal> NOTE:
+        The default configurations are not valid for commercial products, but
+        should work for testing.
+      </para>
+       <para>
+        The USB enumeration also contains text strings to describe the
+        device. The manufacturer string can be set with
+        <literal>CYGDAT_IO_USB_SLAVE_MSD0_MFG_STR</literal>. The product name
+        can be set with <literal>CYGDAT_IO_USB_SLAVE_MSD0_MFG_STR</literal>,
+        finally, the serial number can be set
+        with <literal>CYGDAT_IO_USB_SLAVE_MSD0_SERIAL_STR</literal>.
+      </para>
+      </refsect2>
+      <refsect2><title>Storage</title>  
+      <para>
+        To access the storage media, the USB MSD package requires the storage
+        media to use the eCos disk interface. The disk sector size is assumed 
+        to be 512 bytes. Multiple logical units are supported by the package 
+        (2 by default).
+        More logical units can be supported by changing the
+        <literal>USBS_MSD_CBW_MAX_LUN</literal> definition according 
+        to the user needs. Two logical units can be either 2 partitions on the same
+        disk or 2 partitions on 2 different physical disks. 
+        The first logical unit can be set with 
+        <literal>CYGDAT_IO_USB_SLAVE_MSD0_LUN0_NAME</literal>. The default value 
+        is assigned to <literal>"/dev/ramdisk0/1"</literal>, the first partition of the ramdisk
+         used by the test application.
+      </para>
+      </refsect2>      
+    </refsect1>
+  </refentry>
+  
+  <!-- }}} -->
+  <!-- {{{ Host Config                          -->
+  
+  <refentry id="usbs-msd-host-config">
+    <refmeta>
+      <refentrytitle>Host Configuration</refentrytitle>
+    </refmeta>
+    <refnamediv>
+      <refname>Host Configuration</refname>
+      <refpurpose>Host Configuration for USB Mass Storage like Peripherals
+      </refpurpose>
+    </refnamediv>
+    
+    <refsect1>
+      <title>Host Configuration</title>
+      <para>
+        With modern host operating system, no specific configuration of the 
+        host shall be required to bring up the eCos USB-Mass Storage Device.
+      </para>
+      <refsect2><title>SCSI command set</title>  
+      <para>
+       The USB-Mass Storage device will respond to a set of SCSI commands:
+      <programlisting>
+      INQUIRY
+      READ_CAPACITY
+      READ_10
+      WRITE_10
+      REQUEST_SENSE
+      TEST_UNIT_READY
+      </programlisting>
+      and partially to the commands:
+      <programlisting>
+      SENSE_6
+      VERIFY_10
+      REVENT_ALLOW_MEDIUM_REMOVAL
+      </programlisting>
+      </para>   
+      </refsect2>       
+    </refsect1>
+  </refentry>
+  
+  <!-- }}} -->
+  <!-- {{{ Using                         -->
+  
+  <refentry id="usbs-msd-using">
+   <refmeta>
+      <refentrytitle>Example</refentrytitle>
+    </refmeta>
+    <refnamediv>
+      <refname>Example</refname>
+      <refpurpose>Example for USB Mass Storage like Peripherals
+      </refpurpose>
+    </refnamediv>  
+    <refsect1>
+      <title>RAM disk</title>
+      <para>
+        The "ram disk" is a test application supplied to verify / debug the USB-Mass Storage
+        package. The minimal functionality of this test case is to create a tiny "ram disk"
+        device large of around 32 sectors of 512 bytes each. The disk devtab entry
+        is <literal>"/dev/ramdisk0"</literal>. A FAT12 filesystem is created on top of it 
+        as the first partition of the disk. The partition is therefore accessible from 
+        <literal>"/dev/ramdisk0/1"</literal>. The default behavior of the application is to 
+        start the USB MSD thread. Once plugged into the host machine, an empty drive 
+        called eCos-3.0 shall appear in the host explorer.
+        To test further, the FAT filesystem package can be included while compiling the test
+        application. If included, before the MSD driver is started, the application will 
+        create 2 files (fee and foo) and 1 directory (bar) in the filesystem. Both files and
+        directory shall appear in the host explorer.
+      </para>   
+      <refsect2><title>Configuration</title>  
+      <para>
+        The test application was primarly tested with the AT91 architecture. The control 
+        endpoint is set to <literal>"usbs_at91_ep0"</literal> and the buffer size
+        to 8 bytes.
+        The TX endpoint is set to <literal>"usbs_at91_ep1"</literal> and the buffer size
+        to 64 bytes (with Tx (USB IN) endpoint number set to 1).
+        The RX endpoint is set to <literal>"usbs_at91_ep2"</literal> and the buffer size
+        to 64 bytes (with Rx (USB OUT) endpoint number set to 2).                 
+      </para>   
+      </refsect2>  
+   </refsect1>         
+  </refentry> 
+       
+  <!-- }}} -->
+</part>
+<!-- /reference -->
diff --git a/packages/io/usb/msd/slave/current/include/usbs_msd.h b/packages/io/usb/msd/slave/current/include/usbs_msd.h
new file mode 100644
--- /dev/null
+++ b/packages/io/usb/msd/slave/current/include/usbs_msd.h
@@ -0,0 +1,282 @@
+#ifndef CYGONCE_USBS_MSD_H
+#define CYGONCE_USBS_MSD_H
+//==========================================================================
+//
+//      include/usbs_msd.h
+//
+//      Description of the USB slave-side MSD
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008, 2010 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors:
+// Date:         2010-06-03
+// Purpose:
+// Description:  USB slave-side MSD support
+//
+//
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/io/usb/usbs.h>
+
+// ----------------------------------------------------------------------------
+// The Mass Storage class requests
+//
+#define USBS_MSD_CLASS_REQ_ADSC          0x00
+#define USBS_MSD_CLASS_REQ_GET_REQUEST   0xFC
+#define USBS_MSD_CLASS_REQ_PUT_REQUEST   0xFD
+#define USBS_MSD_CLASS_REQ_GET_MAX_LUN   0xFE
+#define USBS_MSD_CLASS_REQ_BOMSR         0xFF
+
+// ----------------------------------------------------------------------------
+// Subclass values
+//
+#define USBS_MSD_SUB_CLASS_RBC           0x01 // Reduced Block Commands, typically for flash device
+#define USBS_MSD_SUB_CLASS_SFF8020I      0x02 // For CDROM devices
+#define USBS_MSD_SUB_CLASS_QIC_157       0x03 // QIC-157, Tape devices
+#define USBS_MSD_SUB_CLASS_UFI           0x04 // For Floppy Drive Device
+#define USBS_MSD_SUB_CLASS_SFF8070I      0x05 // For Floppy Drive Device
+#define USBS_MSD_SUB_CLASS_SCSI          0x06 // SCSI transparent
+
+#define USBS_MSD_DATA_IFACE_CLASS        0x8  // mass-storage
+
+// ----------------------------------------------------------------------------
+// Command Wrapper values
+//
+#define USBS_MSD_CSW_STATUS_PASSED       0x0
+#define USBS_MSD_CSW_STATUS_FAILED       0x1
+
+#define USBS_MSD_CBW_SIGNATURE           0x43425355
+#define USBS_MSD_CSW_SIGNATURE           0x53425355
+
+#define USBS_MSD_CBW_HOST2DEVICE         0x00
+#define USBS_MSD_CBW_DEVICE2HOST         0x80
+
+#define USBS_MSD_DEVICE_CLASS            0
+#define USBS_MSD_NUM_IFACE               1
+#define USBS_MSD_NUM_ENDP                2
+
+// ----------------------------------------------------------------------------
+// Helper macros
+//
+#define LO_BYTE_16(word16)          ((cyg_uint8) ((word16) & 0xFF))
+#define HI_BYTE_16(word16)          ((cyg_uint8) (((word16) >> 8) & 0xFF))
+
+#define BYTE0_32(word32)            ((cyg_uint8) ((word32) & 0xFF))
+#define BYTE1_32(word32)            ((cyg_uint8) (((word32) >>  8) & 0xFF))
+#define BYTE2_32(word32)            ((cyg_uint8) (((word32) >> 16) & 0xFF))
+#define BYTE3_32(word32)            ((cyg_uint8) (((word32) >> 24) & 0xFF))
+
+#define USB_CONFIGURATION_DESCRIPTOR_TOTAL_LENGTH(interfaces, endpoints) \
+            (USB_CONFIGURATION_DESCRIPTOR_LENGTH +            \
+            ((interfaces) * USB_INTERFACE_DESCRIPTOR_LENGTH) +  \
+            ((endpoints)  * USB_ENDPOINT_DESCRIPTOR_LENGTH))
+
+// ----------------------------------------------------------------------------
+// Interface values
+//
+#define USBS_MSD_INTERFACE_PROTO          0x50 // Bulk mode
+
+#define USBS_MSD_CBW_MAX_LUN               2
+#define USBS_MSD_CBW_MIN_SCSI_CMD_LEN      1
+#define USBS_MSD_CBW_MAX_SCSI_CMD_LEN     16
+
+#define USBS_MSD_DISK_SECTOR_SIZE        512
+
+// ----------------------------------------------------------------------------
+// Mass Storage task constant
+//
+#define USBS_MSD_THREAD_STACK_SIZE       2048
+#define USBS_MSD_THREAD_STACK_PRIORITY   15
+
+// command block wrapper
+typedef struct usbs_msd_cbw {
+    cyg_uint32 signature;
+    cyg_uint32 tag;
+    cyg_uint32 data_transfert_len;
+    cyg_uint8 flags;
+    cyg_uint8 lun;
+    struct cb {
+      cyg_uint8 len;
+      cyg_uint8 data[16];
+    } cb;
+} __attribute__((packed)) usbs_msd_cbw;
+
+// command status wrapper
+typedef struct usbs_msd_csw {
+    cyg_uint32 signature;
+    cyg_uint32 tag;
+    cyg_uint32 data_residue;
+    cyg_uint8  status;
+} __attribute__((packed)) usbs_msd_csw;
+
+// command block wrapper state
+typedef enum {
+    CYG_USBS_MSD_WAIT,
+    CYG_USBS_MSD_DATA_IN,
+    CYG_USBS_MSD_DATA_OUT
+} usbs_msd_state_t;
+
+// End-point type
+typedef enum {
+    CYG_USBS_EP0,
+    CYG_USBS_EP_RX,
+    CYG_USBS_EP_TX
+} usbs_msd_ep_t;
+
+// End-point status / control
+typedef struct usbs_msd_ep_sc_t {
+    cyg_sem_t   ready;
+    cyg_int32   result;
+} usbs_msd_ep_sc_t;
+
+// Storage devices
+typedef struct usbs_msd_lun {
+    cyg_io_handle_t handle[USBS_MSD_CBW_MAX_LUN];
+    const char    * name[USBS_MSD_CBW_MAX_LUN];
+    cyg_uint8       max_lun;
+} usbs_msd_lun;
+
+typedef struct usbs_msd usbs_msd;
+
+// Sub Class Handler
+typedef cyg_int32 (*handler_cmd_fn)( usbs_msd * );
+typedef bool (*handler_init_fn)(void **);
+
+// End-point functions
+typedef cyg_int32 (*send_fn)   ( usbs_msd *, const void * , cyg_int32 );
+typedef cyg_int32 (*receive_fn)( usbs_msd *, const void * , cyg_int32 );
+typedef cyg_int32 (*stall_fn)  ( usbs_msd* msd, usbs_msd_ep_t ep );
+
+// Mass-storage device structure
+struct usbs_msd {
+    // Specify end-points to be used
+    usbs_control_endpoint* ctrl_ep;
+    usbs_tx_endpoint*   tx_ep;
+    usbs_rx_endpoint*   rx_ep;
+
+    cyg_uint8           tx_ep_num;
+    cyg_uint8           rx_ep_num;
+
+    cyg_bool            static_ep;
+
+    // Enumeration data for this device
+    usbs_enumeration_data* enum_data;
+
+    // Enumeration string
+    const char*         mfg_str;
+    const char*         product_str;
+    const char*         serial_str;
+    char*               enum_mfg_str;
+    char*               enum_product_str;
+    char*               enum_serial_str;
+
+    // End-point internal status/control
+    usbs_msd_ep_sc_t    rx;
+    usbs_msd_ep_sc_t    tx;
+
+    // Lock for the state
+    cyg_mutex_t         lock;
+
+    // Condition variable for state changes
+    cyg_cond_t          state_cond;
+
+    // State of the USB interface
+    cyg_uint32          usb_state;
+
+    // Data transport-phase buffer
+    cyg_uint8           buffer[USBS_MSD_DISK_SECTOR_SIZE];
+
+    // State of the MSD
+    usbs_msd_state_t    state;
+
+    void (*app_state_change_fn)(struct usbs_control_endpoint*,
+                                               void*, usbs_state_change, int);
+
+    // Pointer to handler data
+    void*               handler_data;
+
+    // Commands Handler
+    handler_cmd_fn      handler_cmd;
+
+    // Initialize Command Handler
+    handler_init_fn     handler_init;
+
+    send_fn             send;
+    receive_fn          receive;
+    stall_fn            stall;
+
+    // Mass-Storage Service
+    char                serv_stack[USBS_MSD_THREAD_STACK_SIZE];
+    cyg_handle_t        serv_handle;
+    cyg_thread          serv_thread;
+    char*               serv_name;
+
+    // Storage Device
+    usbs_msd_lun*       lun;
+
+    // Command Block Wrapper
+    usbs_msd_cbw        cbw;
+
+    // Command Status Wrapper
+    usbs_msd_csw        csw;
+};
+
+// ----------------------------------------------------------------------------
+// A C interface to the MSD USB code.
+// This is the interface for internal code
+
+// Block the calling thread until the host configures the USB device.
+void usbs_msd_wait_until_configured( usbs_msd* );
+
+// Determines if the USB subsystem is configured
+cyg_bool usbs_msd_is_configured( usbs_msd* );
+
+// MSD main thread
+void usbs_msd_handler( cyg_addrword_t );
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif // CYGONCE_USBS_MSD_H
+
diff --git a/packages/io/usb/msd/slave/current/include/usbs_msd.inl b/packages/io/usb/msd/slave/current/include/usbs_msd.inl
new file mode 100644
--- /dev/null
+++ b/packages/io/usb/msd/slave/current/include/usbs_msd.inl
@@ -0,0 +1,241 @@
+//==========================================================================
+//
+//      usbs_msd.inl
+//
+//      Support for slave-side USB mass storage devices
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008, 2010 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand <ccoutand@stmi.com>
+//              
+// Contributors: jld
+// Date:         2010-06-06
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#ifndef CYGONCE_IO_USB_SLAVE_MSD_INL
+#define CYGONCE_IO_USB_SLAVE_MSD_INL
+
+#define MFG_STR_INDEX           '\x01'
+#define PRODUCT_STR_INDEX       '\x02'
+#define SERIAL_STR_INDEX        '\x03'
+
+#define USB_MAX_STR_LEN         256
+
+// Declare Mass Storage Device 0
+#ifdef CYGPKG_IO_USB_SLAVE_MSD0
+
+#ifdef CYGDAT_IO_USB_SLAVE_MSD0_SUB_CLASS_TYPE_SCSI
+#define USBS_MSD0_DATA_IFACE_SUB_CLASS USBS_MSD_SUB_CLASS_SCSI
+#else
+# error "Only SCSI Sub Class is implemented"
+#endif
+
+// ----- USB external definition
+extern usbs_control_endpoint    CYGDAT_IO_USB_SLAVE_MSD0_EP0;
+#if defined(CYGPKG_IO_USB_SLAVE_MSD0_STATIC_EP)
+extern usbs_tx_endpoint         CYGDAT_IO_USB_SLAVE_MSD0_TX_EP;
+extern usbs_rx_endpoint         CYGDAT_IO_USB_SLAVE_MSD0_RX_EP;
+#endif
+
+
+// ----- Configuration Descriptor -----
+
+static const usb_configuration_descriptor usbs_msd0_configuration = {
+    length            : sizeof(usb_configuration_descriptor),
+    type              : USB_CONFIGURATION_DESCRIPTOR_TYPE,
+    total_length_lo   :    
+        USB_CONFIGURATION_DESCRIPTOR_TOTAL_LENGTH_LO(USBS_MSD_NUM_IFACE, 
+                                                     USBS_MSD_NUM_ENDP),
+    total_length_hi   :    
+        USB_CONFIGURATION_DESCRIPTOR_TOTAL_LENGTH_HI(USBS_MSD_NUM_IFACE, 
+                                                     USBS_MSD_NUM_ENDP),
+    number_interfaces : USBS_MSD_NUM_IFACE,
+    configuration_id  : 1,
+    configuration_str : 0,
+#ifdef CYGOPT_IO_USB_SLAVE_MSD0_BUSPOWERED
+    attributes        : (USB_CONFIGURATION_DESCRIPTOR_ATTR_REQUIRED),
+#else
+    attributes        : (USB_CONFIGURATION_DESCRIPTOR_ATTR_REQUIRED |
+                         USB_CONFIGURATION_DESCRIPTOR_ATTR_SELF_POWERED),
+#endif
+    max_power         : ((CYGNUM_IO_USB_SLAVE_MSD0_CURRENTDRAW+1) >> 1)
+};
+
+// ----- Interface Descriptor -----
+
+static const usb_interface_descriptor usbs_msd0_interface[] = {
+    {
+        length:             sizeof(usb_interface_descriptor),
+        type:               USB_INTERFACE_DESCRIPTOR_TYPE,
+        interface_id:       0,
+        alternate_setting:  0,
+        number_endpoints:   2,
+        interface_class:    USBS_MSD_DATA_IFACE_CLASS,
+        interface_subclass: USBS_MSD0_DATA_IFACE_SUB_CLASS,
+        interface_protocol: USBS_MSD_INTERFACE_PROTO,
+        interface_str:      0x00
+    }
+};
+
+// ----- Endpoint Descriptors -----
+
+static const usb_endpoint_descriptor usbs_msd0_endpoints[] =
+{ 
+    // Tx (Bulk IN) Endpoint Descriptor
+    {
+        sizeof(usb_endpoint_descriptor),
+        USB_ENDPOINT_DESCRIPTOR_TYPE,
+        USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN  | \
+                CYGNUM_IO_USB_SLAVE_MSD0_TX_EP_NUM,
+        USB_ENDPOINT_DESCRIPTOR_ATTR_BULK,
+        LO_BYTE_16(CYGNUM_IO_USB_SLAVE_MSD0_TX_EP_MAX_PACKET_SIZE),
+        HI_BYTE_16(CYGNUM_IO_USB_SLAVE_MSD0_TX_EP_MAX_PACKET_SIZE),
+        0
+    },
+
+    // Rx (Bulk OUT) Endpoint Descriptor
+    {
+        sizeof(usb_endpoint_descriptor),
+        USB_ENDPOINT_DESCRIPTOR_TYPE,
+        USB_ENDPOINT_DESCRIPTOR_ENDPOINT_OUT | \
+               CYGNUM_IO_USB_SLAVE_MSD0_RX_EP_NUM,
+        USB_ENDPOINT_DESCRIPTOR_ATTR_BULK,
+        LO_BYTE_16(CYGNUM_IO_USB_SLAVE_MSD0_RX_EP_MAX_PACKET_SIZE),
+        HI_BYTE_16(CYGNUM_IO_USB_SLAVE_MSD0_RX_EP_MAX_PACKET_SIZE),
+        0
+    }
+};
+
+// ----- String Descriptors -----
+
+static char usbs_msd0_mfg_str_descr[USB_MAX_STR_LEN],
+            usbs_msd0_product_str_descr[USB_MAX_STR_LEN],
+            usbs_msd0_serial_str_descr[USB_MAX_STR_LEN];
+
+static const char* usbs_msd0_strings[] = {
+    "\x04\x03\x09\x04",
+    usbs_msd0_mfg_str_descr,
+    usbs_msd0_product_str_descr,
+    usbs_msd0_serial_str_descr
+};     
+
+// ----- Enumeration Data w/ Device Descriptor -----
+
+static usbs_enumeration_data usbs_msd0_enum_data = {
+    {
+        length:                 sizeof(usb_device_descriptor),
+        type:                   USB_DEVICE_DESCRIPTOR_TYPE,
+        usb_spec_lo:            0x00, 
+        usb_spec_hi:            0x02,
+        device_class:           USBS_MSD_DEVICE_CLASS,
+        device_subclass:        0,
+        device_protocol:        0,
+        max_packet_size:        CYGNUM_IO_USB_SLAVE_MSD0_EP0_MAX_PACKET_SIZE,
+        vendor_lo:              LO_BYTE_16(CYGNUM_IO_USB_SLAVE_MSD0_VENDOR_ID),
+        vendor_hi:              HI_BYTE_16(CYGNUM_IO_USB_SLAVE_MSD0_VENDOR_ID),
+        product_lo:             LO_BYTE_16(CYGNUM_IO_USB_SLAVE_MSD0_PRODUCT_ID),
+        product_hi:             HI_BYTE_16(CYGNUM_IO_USB_SLAVE_MSD0_PRODUCT_ID),
+        device_lo:              0x00,
+        device_hi:              0x00,
+        manufacturer_str:       MFG_STR_INDEX,
+        product_str:            PRODUCT_STR_INDEX,
+        serial_number_str:      SERIAL_STR_INDEX, // must be > 0 for mass-storage
+        number_configurations:  1
+    },
+
+    total_number_interfaces:    USBS_MSD_NUM_IFACE,
+    total_number_endpoints:     USBS_MSD_NUM_ENDP,
+    total_number_strings:       3,
+    configurations:             &usbs_msd0_configuration,
+    interfaces:                 usbs_msd0_interface,
+    endpoints:                  usbs_msd0_endpoints,
+    strings:                    (const unsigned char **) usbs_msd0_strings
+};
+
+// Logical Unit
+usbs_msd_lun msd0_lun = {
+#ifdef CYGDAT_IO_USB_SLAVE_MSD0_LUN0_NAME
+  .name[0] = CYGDAT_IO_USB_SLAVE_MSD0_LUN0_NAME,
+#else
+  .name[0] = NULL,
+#endif  
+#ifdef CYGDAT_IO_USB_SLAVE_MSD0_LUN1_NAME
+  .name[1] = CYGDAT_IO_USB_SLAVE_MSD0_LUN1_NAME
+#else
+  .name[1] = NULL
+#endif 
+};
+
+
+// USBS Mass Storage Device 0
+usbs_msd msd0 = {
+#ifdef CYGDAT_IO_USB_SLAVE_MSD0_SUB_CLASS_TYPE_SCSI
+ .handler_cmd      = usbs_msd_scsi_handle_cmd,
+ .handler_init     = usbs_msd_scsi_init,
+#else
+ .handler_cmd      = NULL,
+ .handler_init     = NULL,
+#endif
+ .ctrl_ep          = &CYGDAT_IO_USB_SLAVE_MSD0_EP0,
+#if defined(CYGPKG_IO_USB_SLAVE_MSD0_STATIC_EP)
+ .tx_ep            = &CYGDAT_IO_USB_SLAVE_MSD0_TX_EP,
+ .rx_ep            = &CYGDAT_IO_USB_SLAVE_MSD0_RX_EP,
+ .static_ep        = true,
+#else
+ .static_ep        = false,
+#endif
+ .tx_ep_num        = CYGNUM_IO_USB_SLAVE_MSD0_TX_EP_NUM,
+ .rx_ep_num        = CYGNUM_IO_USB_SLAVE_MSD0_RX_EP_NUM,
+ .lun              = &msd0_lun,
+ .handler_data     = NULL,
+ .serv_name        = "msd0_service",
+ .enum_data        = &usbs_msd0_enum_data,
+ .enum_mfg_str     = &usbs_msd0_mfg_str_descr[0],
+ .enum_product_str = &usbs_msd0_product_str_descr[0],
+ .enum_serial_str  = &usbs_msd0_serial_str_descr[0],
+ .mfg_str          = CYGDAT_IO_USB_SLAVE_MSD0_MFG_STR,
+ .product_str      = CYGDAT_IO_USB_SLAVE_MSD0_PRODUCT_STR,
+ .serial_str       = CYGDAT_IO_USB_SLAVE_MSD0_SERIAL_STR
+};
+
+#endif // CYGPKG_IO_USB_SLAVE_MSD0
+
+#endif // CYGONCE_IO_USB_SLAVE_MSD_INL
diff --git a/packages/io/usb/msd/slave/current/include/usbs_msd_io.h b/packages/io/usb/msd/slave/current/include/usbs_msd_io.h
new file mode 100644
--- /dev/null
+++ b/packages/io/usb/msd/slave/current/include/usbs_msd_io.h
@@ -0,0 +1,66 @@
+#ifndef CYGONCE_USBS_MSD_IO_H
+#define CYGONCE_USBS_MSD_IO_H
+//==========================================================================
+//
+//      include/usbs_msd_io.h
+//
+//      Application API for the USB slave-side MSD device
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2010 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand <ccoutand@stmi.com>
+// Contributors:
+// Date:         2010-06-04
+// Purpose:
+// Description:  USB slave-side MSD support
+//
+//
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Starts the USB subsystem
+bool usbs_msd_start(void);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif // CYGONCE_USBS_MSD_IO_H
+
diff --git a/packages/io/usb/msd/slave/current/include/usbs_msd_opcode.h b/packages/io/usb/msd/slave/current/include/usbs_msd_opcode.h
new file mode 100644
--- /dev/null
+++ b/packages/io/usb/msd/slave/current/include/usbs_msd_opcode.h
@@ -0,0 +1,114 @@
+#ifndef CYGONCE_USBS_MSD_OPCODE_H
+#define CYGONCE_USBS_MSD_OPCODE_H
+//==========================================================================
+//
+//      include/usbs_msd_opcode.h
+//
+//      SCSI support for the USB slave-side MSD device
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2010 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand <ccoutand@stmi.com>
+// Contributors:
+// Date:         2010-06-02
+// Purpose:
+// Description:  USB slave-side MSD support
+//
+//
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// SCSI commands from SBC-2 or SBC-3
+#define USBS_SCSI_FORMAT_UNIT            0x04
+#define USBS_SCSI_INQUIRY                0x12
+#define USBS_SCSI_MODE_SELECT_6          0x15
+#define USBS_SCSI_MODE_SELECT_10         0x55
+#define USBS_SCSI_SENSE_6                0x1A
+#define USBS_SCSI_SENSE_10               0x5A
+#define USBS_SCSI_READ_6                 0x08
+#define USBS_SCSI_READ_10                0x28
+#define USBS_SCSI_READ_12                0xA8
+#define USBS_SCSI_READ_CAPACITY          0x25
+#define USBS_SCSI_READ_FORMAT_CAPACITIES 0x23
+#define USBS_SCSI_READ_TOC               0x43
+#define USBS_SCSI_REPORT_LUNS            0xA0
+#define USBS_SCSI_REQUEST_SENSE          0x03
+#define USBS_SCSI_SEND_DIAGNOSTIC        0x1D
+#define USBS_SCSI_START_STOP_UNIT        0x1B
+#define USBS_SCSI_SYNC_CACHE_10          0x35
+#define USBS_SCSI_TEST_UNIT_READY        0x00
+#define USBS_SCSI_VERIFY_10              0x2F
+#define USBS_SCSI_WRITE_6                0x0A
+#define USBS_SCSI_WRITE_10               0x2A
+#define USBS_SCSI_WRITE_12               0xAA
+#define USBS_SCSI_PREVENT_ALLOW_REMOVAL  0x1E
+
+// Sense result
+#define USBS_MSD_SCSI_SENSE_NOT_READY                            0x2
+#define USBS_MSD_SCSI_SENSE_MEDIUM_ERROR                         0x3
+#define USBS_MSD_SCSI_SENSE_ILLEGAL_REQUEST                      0x5
+#define USBS_MSD_SCSI_SENSE_UNIT_ATTENTION                       0x6
+#define USBS_MSD_SCSI_SENSE_ASC_LOGICAL_BLOCK_ADDR_OUT_OF_RANGE  0x21
+#define USBS_MSD_SCSI_SENSE_ASCQ_LOGICAL_BLOCK_ADDR_OUT_OF_RANGE 0x0
+#define USBS_MSD_SCSI_SENSE_ASC_INVALID_OPCODE                   0x20
+#define USBS_MSD_SCSI_SENSE_ASCQ_INVALID_OPCODE                  0x0
+#define USBS_MSD_SCSI_SENSE_ASC_MEDIUM_NOT_PRESENT               0x3a
+#define USBS_MSD_SCSI_SENSE_ASCQ_MEDIUM_NOT_PRESENT              0x00
+#define USBS_MSD_SCSI_SENSE_ASC_PERIPHERAL_DEVICE_WRITE_FAULT    0x03
+#define USBS_MSD_SCSI_SENSE_ASCQ_PERIPHERAL_DEVICE_WRITE_FAULT   0x00
+#define USBS_MSD_SCSI_SENSE_ASC_UNRECOVERED_READ_ERROR           0x11
+#define USBS_MSD_SCSI_SENSE_ASCQ_UNRECOVERED_READ_ERROR          0x00
+#define USBS_MSD_SCSI_SENSE_ASC_WRITE_ERROR                      0x0C
+#define USBS_MSD_SCSI_SENSE_ASCQ_WRITE_ERROR                     0x00
+#define USBS_MSD_SCSI_SENSE_ASC_WRITE_PROTECTED                  0x27
+#define USBS_MSD_SCSI_SENSE_ASCQ_WRITE_PROTECTED                 0x00
+#define USBS_MSD_SCSI_SENSE_ASC_INVALID_FIELD_IN_CBD             0x24
+
+// Mode Page
+#define USBS_MSD_SCSI_MODE_PAGE_CODE_ALL     0x3F
+#define USBS_MSD_SCSI_MODE_PAGE_CODE_IEC     0x1C
+#define USBS_MSD_SCSI_MODE_PAGE_CODE_CACHING 0x08
+#define USBS_MSD_SCSI_MODE_PAGE_CODE_FDM     0x05
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif // CYGONCE_USBS_MSD_OPCODE_H
diff --git a/packages/io/usb/msd/slave/current/include/usbs_msd_scsi.h b/packages/io/usb/msd/slave/current/include/usbs_msd_scsi.h
new file mode 100644
--- /dev/null
+++ b/packages/io/usb/msd/slave/current/include/usbs_msd_scsi.h
@@ -0,0 +1,143 @@
+#ifndef CYGONCE_USBS_MSD_SCSI_H
+#define CYGONCE_USBS_MSD_SCSI_H
+//==========================================================================
+//
+//      include/usbs_msd_scsi.h
+//
+//      SCSI support for the USB slave-side MSD device
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2010 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors:
+// Date:         2010-06-02
+// Purpose:
+// Description:  USB slave-side MSD support
+//
+//
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// The standard INQUIRY data shall contain at least 36 bytes
+// This is the reduced structure for Mass Storage Devices
+typedef struct
+{
+   cyg_uint8 peripheral;         // Device Type
+   cyg_uint8 rmb;                // Removable Media Bit
+   cyg_uint8 version;            // Version Field
+   cyg_uint8 resp_data_format;   // Response Data Format
+   cyg_uint8 additional_len;     // Additional Length
+   cyg_uint8 sccstp;             // SCC Supported (include embedded storage array)
+   cyg_uint8 bque;               // Basic Queuing
+   cyg_uint8 cmdque;             // Command Queuing
+   cyg_uint8 vendor_id[8];
+   cyg_uint8 product_id[16];
+   cyg_uint8 product_rev[4];
+} msd_scsi_inq_resp;
+
+#define USBS_SCSI_DIRECT_ACCESS_BLOCK_DEVICE 0x00
+#define USBS_SCSI_REMOVABLE_DEVICE           0x80
+
+// Fixed-format Sense Data ( defined as a 18 bytes array )
+typedef struct
+{
+   cyg_uint8 byte[18];
+} msd_scsi_req_sense_resp;
+
+// Set Valid information field
+#define USBS_MSD_SCSI_SET_SENSE_VALID( ptr_sense, _valid_ ) \
+{ \
+  if( _valid_ ) \
+    ptr_sense[0] |= 0x80; \
+  else \
+    ptr_sense[0] &= ~0x80; \
+};
+
+// Set Response Code field
+#define USBS_MSD_SCSI_SET_SENSE_RESP_CODE( ptr_sense, _code_ ) \
+{ \
+    cyg_uint8 byte = ptr_sense[0] & 0x80; \
+    ptr_sense[0] = ((_code_ & 0x7F) | byte); \
+};
+
+// Set Sense Key field
+#define USBS_MSD_SCSI_SET_SENSE_KEY( ptr_sense, _key_ ) \
+{ \
+    cyg_uint8 byte = ptr_sense[0] & 0xF0; \
+    ptr_sense[0] = ((_key_ & 0x0F) | byte); \
+};
+
+// Set Additional Sense Length field
+#define USBS_MSD_SCSI_SET_SENSE_ASL( ptr_sense, _asl_ ) \
+{ \
+    ptr_sense[7] = _asl_; \
+};
+
+// Set Additional Sense Code field
+#define USBS_MSD_SCSI_SET_SENSE_ASC( ptr_sense, _asc_ ) \
+{ \
+    ptr_sense[12] = _asc_; \
+};
+
+// Set Additional Sense Code Qualifier field
+#define USBS_MSD_SCSI_SET_SENSE_ASCQ( ptr_sense, _ascq_ ) \
+{ \
+    ptr_sense[13] = _ascq_; \
+};
+
+// Init Sense Data structure
+#define USBS_MSD_SCSI_INIT_SENSE_DATA( _array_ ) \
+{ \
+   cyg_int32 i; \
+   for(i = 0; i < sizeof(msd_scsi_req_sense_resp); i++) \
+   _array_[i] = 0; \
+   USBS_MSD_SCSI_SET_SENSE_VALID( _array_, 1); \
+   USBS_MSD_SCSI_SET_SENSE_RESP_CODE( _array_, 0x70 ); \
+   USBS_MSD_SCSI_SET_SENSE_ASC( _array_, 0x0a ); \
+};
+
+cyg_int32 usbs_msd_scsi_handle_cmd( usbs_msd * );
+bool usbs_msd_scsi_init( void ** ctxt );
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif // CYGONCE_USBS_MSD_SCSI_H
diff --git a/packages/io/usb/msd/slave/current/src/usbs_msd.c b/packages/io/usb/msd/slave/current/src/usbs_msd.c
new file mode 100644
--- /dev/null
+++ b/packages/io/usb/msd/slave/current/src/usbs_msd.c
@@ -0,0 +1,471 @@
+//==========================================================================
+//
+//      usbs_msd.c
+//
+//      Support for slave-side USB mass storage devices.
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008, 2010 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+//
+// Contributors: jld
+// Date:         2010-05-27
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+#include <pkgconf/system.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/cyg_trac.h>
+#include <cyg/infra/diag.h>
+#include <cyg/io/devtab.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/kernel/kapi.h>
+
+#include <pkgconf/io_usb_slave_msd.h>
+#include <cyg/io/usb/usbs_msd.h>
+
+#ifdef CYGDAT_IO_USB_SLAVE_MSD0_SUB_CLASS_TYPE_SCSI
+#include <cyg/io/usb/usbs_msd_scsi.h>
+#endif
+
+#include <string.h>
+
+#if defined(CYGBLD_IO_USB_SLAVE_MSD_DEBUG)
+#define DBG diag_printf
+#else
+#define DBG (1) ? (void)0 : diag_printf
+#endif
+
+#include CYGDAT_IO_USB_SLAVE_MSD_INL // Declaration of the Mass Storage devices
+
+// --------------------------------------------------------------------------
+// Create a USB String Descriptor from a C string.
+//
+void
+usbs_msd_create_str_descriptor(char descr[], const char *str)
+{
+    cyg_uint32 i, n = strlen(str);
+
+    if (n > (USB_MAX_STR_LEN/2 - 2))
+        n = USB_MAX_STR_LEN/2 - 2;
+
+    descr[0] = (cyg_uint8) (2*n + 2);
+    descr[1] = USB_DEVREQ_DESCRIPTOR_TYPE_STRING;
+
+    for (i=0; i<n; i++) {
+        descr[i*2+2] = str[i];
+        descr[i*2+3] = '\x00';
+    }
+}
+
+// --------------------------------------------------------------------------
+// Mass Storage Device Class Handler
+//
+static usbs_control_return
+usbs_msd_class_handler(usbs_control_endpoint* ep0, void* callback_data)
+{
+  usbs_control_return result = USBS_CONTROL_RETURN_UNKNOWN;
+  usb_devreq *req = (usb_devreq *) ep0->control_buffer;
+  usbs_msd   *msd = (usbs_msd *) callback_data;
+  static cyg_uint8 rsp_buf[32];
+
+  DBG("USB MSD Class Handler: ");
+
+  switch (req->request) {
+
+    case USBS_MSD_CLASS_REQ_GET_MAX_LUN :
+      DBG("USB MSD Request: Get MAX LUN %d\n", \
+                                 msd->lun->max_lun);
+      rsp_buf[0]  = msd->lun->max_lun - 1;
+      ep0->buffer = rsp_buf;
+      ep0->buffer_size = 1;
+      result = USBS_CONTROL_RETURN_HANDLED;
+      break;
+
+    case USBS_MSD_CLASS_REQ_BOMSR :
+      DBG("USB MSD Request: Reset\n");
+      // FIXME : Handle Reset
+      ep0->buffer_size = 0;
+      result = USBS_CONTROL_RETURN_HANDLED;
+      break;
+
+    default :
+      DBG("*** USB MSD Request: 0x%02X not implemented !***\n",
+          (unsigned) req->request);
+  }
+
+  return result;
+}
+
+
+// --------------------------------------------------------------------------
+// Callback for a USB state change
+//
+void
+usbs_msd_state_change_handler(usbs_control_endpoint* ep, void* callback_data,
+                                 usbs_state_change change, int prev_state)
+{
+  usbs_msd *msd = (usbs_msd *) callback_data;
+
+#if defined(CYGBLD_IO_USB_SLAVE_MSD_DEBUG)
+  const char *STATE_CHG_STR[] = { "Detached", "Attached", "Powered", "Reset",
+                                  "Addressed", "Configured", "Deconfigured",
+                                  "Suspended", "Resumed" };
+
+  if (change > 0 && change < 10) {
+    DBG("### %d:%s ###\n", change, STATE_CHG_STR[(int) change-1]);
+  }
+  else {
+    DBG("### %d ###\n", change);
+  }
+#endif
+
+  // Called from DSR, cond broadcast should be ok without mutex lock
+  msd->usb_state = msd->ctrl_ep->state;
+
+  cyg_cond_broadcast( &msd->state_cond );
+
+  if (msd->app_state_change_fn)
+    (*msd->app_state_change_fn)(ep, callback_data, change, prev_state);
+
+}
+
+
+// --------------------------------------------------------------------------
+// Block the calling thread until the USB is configured.
+ //
+void
+usbs_msd_wait_until_configured( usbs_msd* msd )
+{
+  cyg_mutex_lock( &msd->lock );
+  while ( msd->usb_state != USBS_STATE_CONFIGURED )
+    cyg_cond_wait( &msd->state_cond );
+
+  // Dynamic end-points configuration
+  if ( msd->static_ep == false )
+  {
+    msd->tx_ep = usbs_get_tx_endpoint( msd->ctrl_ep, msd->tx_ep_num );
+    msd->rx_ep = usbs_get_rx_endpoint( msd->ctrl_ep, msd->rx_ep_num );
+    DBG("tx_ep = %p\n", msd->tx_ep);
+    DBG("rx_ep = %p\n", msd->rx_ep);
+  }
+
+  cyg_mutex_unlock( &msd->lock );
+}
+
+
+// --------------------------------------------------------------------------
+// Determine if the device is currently configured.
+//
+cyg_bool
+usbs_msd_is_configured( usbs_msd* msd )
+{
+  return msd->usb_state == USBS_STATE_CONFIGURED;
+}
+
+
+// --------------------------------------------------------------------------
+// Callback for when a transmit / stall is complete
+//
+static void
+usbs_msd_tx_complete( void *p, cyg_int32 result )
+{
+  usbs_msd* msd  = (usbs_msd*) p;
+  msd->tx.result = result;
+  cyg_semaphore_post( &msd->tx.ready );
+}
+
+
+// --------------------------------------------------------------------------
+// Callback for when a receive / stall is complete
+//
+static void
+usbs_msd_rx_complete( void *p, cyg_int32 result )
+{
+  usbs_msd* msd  = (usbs_msd*) p;
+  msd->rx.result = result;
+  cyg_semaphore_post( &msd->rx.ready );
+}
+
+
+// --------------------------------------------------------------------------
+// Start an asynchronous transmit of a buffer.
+//
+static void
+usbs_msd_start_tx(usbs_msd* msd, const void* buf, cyg_int32 n)
+{
+  usbs_start_tx_buffer( msd->tx_ep, (unsigned char*) buf, n,
+                       usbs_msd_tx_complete, msd );
+}
+
+
+// --------------------------------------------------------------------------
+// Block the caller until the transmit / stall is complete
+//
+static int
+usbs_msd_wait_for_tx(usbs_msd* msd)
+{
+  cyg_semaphore_wait( &msd->tx.ready );
+  return msd->tx.result;
+}
+
+
+// --------------------------------------------------------------------------
+// Perform a synchronous transmit and wait for it to complete.
+//
+static cyg_int32
+usbs_msd_tx(usbs_msd* msd, const void* buf, cyg_int32 n)
+{
+  usbs_msd_start_tx( msd, buf, n );
+  return usbs_msd_wait_for_tx( msd );
+}
+
+
+// --------------------------------------------------------------------------
+// Start an asynchronous receive of a buffer.
+//
+static void
+usbs_msd_start_rx(usbs_msd* msd, void* buf, cyg_int32 n)
+{
+  usbs_start_rx_buffer( msd->rx_ep, (unsigned char*) buf, n,
+                       usbs_msd_rx_complete, msd );
+}
+
+
+// --------------------------------------------------------------------------
+// Block the caller until the receive / stall is complete
+//
+static cyg_int32
+usbs_msd_wait_for_rx(usbs_msd* msd)
+{
+  cyg_semaphore_wait( &msd->rx.ready );
+  return msd->rx.result;
+}
+
+
+// --------------------------------------------------------------------------
+// Perform a synchronous receive and wait for it to complete
+//
+static cyg_int32
+usbs_msd_rx(usbs_msd* msd, void* buf, cyg_int32 n)
+{
+  usbs_msd_start_rx( msd, buf, n );
+  return usbs_msd_wait_for_rx( msd );
+}
+
+
+// --------------------------------------------------------------------------
+// Halt end-point
+//
+static void
+usbs_msd_set_ep_halted( usbs_msd* msd , usbs_msd_ep_t ep, cyg_bool state )
+{
+  if( ep == CYG_USBS_EP_RX )
+    usbs_set_rx_endpoint_halted( msd->rx_ep , state );
+  else if( ep == CYG_USBS_EP_TX )
+    usbs_set_tx_endpoint_halted( msd->tx_ep , state );
+}
+
+
+// --------------------------------------------------------------------------
+// Perform a synchronous end-point halt and wait for host to restart it
+//
+static cyg_int32
+usbs_msd_ep_stall(usbs_msd* msd, usbs_msd_ep_t ep )
+{
+  cyg_sem_t *ready;
+  cyg_int32 *result;
+
+#if !defined(CYGSEM_IO_USB_SLAVE_MSD_STALL_ENABLE)
+   return 1;
+#endif
+
+  if( ep == CYG_USBS_EP_RX )
+  {
+    ready    = &msd->rx.ready;
+    result   = &msd->rx.result;
+  }
+  else if( ep == CYG_USBS_EP_TX )
+  {
+    ready    = &msd->tx.ready;
+    result   = &msd->tx.result;
+  }
+  else
+    return 0;
+
+  // Halt End-point
+  usbs_msd_set_ep_halted( msd, ep , 1 );
+
+  // Wait
+  if( ep == CYG_USBS_EP_RX )
+    usbs_start_rx_endpoint_wait( msd->rx_ep, usbs_msd_rx_complete, msd );
+  else if( ep == CYG_USBS_EP_TX )
+    usbs_start_tx_endpoint_wait( msd->tx_ep, usbs_msd_tx_complete, msd );
+
+  cyg_semaphore_wait( ready );
+
+  return ( *result );
+
+}
+
+
+// --------------------------------------------------------------------------
+// Initialize a Mass Storage Device structure
+//
+static bool
+usbs_msd_init( usbs_msd* msd )
+{
+  cyg_io_handle_t handle;
+  cyg_uint8 i = 0;
+
+  if( msd->ctrl_ep == NULL )
+    return false;
+
+  // Lookup storage devices
+  msd->lun->max_lun = 0;
+  for (i = 0; i < USBS_MSD_CBW_MAX_LUN; i++)
+  {
+    if ( msd->lun->name[i] != NULL )
+    {
+      DBG("USB Slave MSD: Lookup %s \n", msd->lun->name[i] );
+      if( cyg_io_lookup( msd->lun->name[i] , &handle ) != ENOERR )
+        return false;
+      msd->lun->handle[i] = handle;
+      msd->lun->max_lun++;
+    }
+  }
+
+  msd->tx.result =  0;
+  msd->rx.result =  0;
+
+  // Initialize TX and RX semaphore
+  cyg_semaphore_init( &msd->tx.ready, 0 );
+  cyg_semaphore_init( &msd->rx.ready, 0 );
+
+  cyg_mutex_init( &msd->lock );
+
+  cyg_cond_init( &msd->state_cond, &msd->lock );
+
+  // Make USB string descriptors
+  usbs_msd_create_str_descriptor( \
+                     msd->enum_mfg_str,\
+                     msd->mfg_str );
+  usbs_msd_create_str_descriptor( \
+                     msd->enum_product_str,\
+                     msd->product_str );
+  usbs_msd_create_str_descriptor( \
+                     msd->enum_serial_str,\
+                     msd->serial_str );
+
+  // Set up enumeration & USB call-backs
+  msd->usb_state = msd->ctrl_ep->state;
+
+  msd->ctrl_ep->enumeration_data = msd->enum_data;
+
+  if ( msd->ctrl_ep->state_change_fn )
+    msd->app_state_change_fn = msd->ctrl_ep->state_change_fn;
+
+  msd->ctrl_ep->state_change_fn    = usbs_msd_state_change_handler;
+  msd->ctrl_ep->state_change_data  = (void*) msd;
+  msd->ctrl_ep->class_control_fn   = usbs_msd_class_handler;
+  msd->ctrl_ep->class_control_data = (void*) msd;
+
+  if ( msd->handler_init )
+     msd->handler_init( &msd->handler_data );
+
+  msd->send    = usbs_msd_tx;
+  msd->receive = usbs_msd_rx;
+  msd->stall   = usbs_msd_ep_stall;
+
+  // Setup initial state
+  msd->state = CYG_USBS_MSD_WAIT;
+
+  return true;
+}
+
+
+// --------------------------------------------------------------------------
+// Initialize a Mass Storage Device structure
+//
+static void
+usbs_msd_start_service(usbs_msd* msd)
+{
+
+  cyg_thread_create( USBS_MSD_THREAD_STACK_PRIORITY , &usbs_msd_handler, \
+                     (cyg_addrword_t) msd, msd->serv_name, msd->serv_stack,  \
+                     USBS_MSD_THREAD_STACK_SIZE, &msd->serv_handle, \
+                     &msd->serv_thread);
+
+  cyg_thread_resume( msd->serv_handle );
+
+}
+
+
+// --------------------------------------------------------------------------
+// Start the USB subsystem
+//
+bool
+usbs_msd_start(void)
+{
+
+#ifdef CYGPKG_IO_USB_SLAVE_MSD0
+
+  DBG("USB Slave Mass-Storage 0 starts\n");
+
+  if ( usbs_msd_init( &msd0 ) == false )
+  {
+    DBG("USB Slave Mass-Storage 0 startup failed\n");
+    return false;
+  }
+
+  // ----- Start USB subsystem -----
+  //
+  usbs_start( msd0.ctrl_ep );
+
+  usbs_msd_start_service( &msd0 );
+
+#endif
+
+  return true;
+}
+
+
+
+
diff --git a/packages/io/usb/msd/slave/current/src/usbs_msd_handler.c b/packages/io/usb/msd/slave/current/src/usbs_msd_handler.c
new file mode 100644
--- /dev/null
+++ b/packages/io/usb/msd/slave/current/src/usbs_msd_handler.c
@@ -0,0 +1,266 @@
+//==========================================================================
+//
+//      usbs_msd_handler.c
+//
+//      Support for slave-side USB mass storage devices.
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+//
+// Date:         2010-06-02
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/cyg_trac.h>
+#include <cyg/infra/diag.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_endian.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/kernel/kapi.h>
+
+#include <pkgconf/io_usb_slave_msd.h>
+#include <cyg/io/usb/usbs_msd.h>
+
+#include <stdio.h> // for memcpy
+
+#if defined(CYGBLD_IO_USB_SLAVE_MSD_DEBUG)
+#define DBG diag_printf
+#else
+#define DBG (1) ? (void)0 : diag_printf
+#endif
+
+#if defined(CYGBLD_IO_USB_SLAVE_MSD_TRACE)
+#define TRACE diag_printf
+#else
+#define TRACE (1) ? (void)0 : diag_printf
+#endif
+
+#define CONSTRUCT_CSW( _csw_, _tag_ ) \
+{ \
+   _csw_.tag = _tag_; \
+   _csw_.signature = USBS_MSD_CSW_SIGNATURE; \
+};
+
+
+// Validate a command block wrapper
+// CBW is sent from host in little endian format, hence it
+// must be converted to the CPU endianness
+//
+static inline bool
+usbs_msd_validate_cbw(usbs_msd_cbw *cbw, cyg_int32 len)
+{
+
+  // Convert to CPU endianness
+  cbw->signature = CYG_LE32_TO_CPU( cbw->signature );
+  cbw->tag       = CYG_LE32_TO_CPU( cbw->tag );
+  cbw->data_transfert_len = CYG_LE32_TO_CPU( cbw->data_transfert_len );
+
+  if( len != sizeof( usbs_msd_cbw ) ||
+     cbw->signature != USBS_MSD_CBW_SIGNATURE )
+  {
+    DBG("USB Slave MSD: CBW signature %x, len %d\n\r", \
+      cbw->signature, len);
+    return false;
+  }
+  else
+    return true;
+}
+
+
+// Validate a command block wrapper content
+//
+static inline bool
+usbs_msd_validate_cbw_data(usbs_msd_cbw *cbw)
+{
+  if( ( cbw->lun < USBS_MSD_CBW_MAX_LUN ) && \
+      ( cbw->cb.len <= USBS_MSD_CBW_MAX_SCSI_CMD_LEN ) && \
+      ( cbw->cb.len >= USBS_MSD_CBW_MIN_SCSI_CMD_LEN ) && \
+      ( ( cbw->flags == USBS_MSD_CBW_HOST2DEVICE ) || \
+        ( cbw->flags == USBS_MSD_CBW_DEVICE2HOST ) ) )
+  {
+    return true;
+  }
+  else
+  {
+    DBG("USB Slave MSD: CBW Invalid data, LUN %d, len %d, flag %x\n\r", \
+        cbw->lun, cbw->cb.len, cbw->flags);
+  }
+  return false;
+}
+
+
+// Send Command Status Wrapper
+//
+static inline cyg_int32
+usbs_msd_send_csw( usbs_msd* msd )
+{
+  // Convert to host endianness
+  msd->csw.signature = CYG_CPU_TO_LE32( msd->csw.signature );
+  msd->csw.tag       = CYG_CPU_TO_LE32( msd->csw.tag );
+  msd->csw.data_residue = CYG_CPU_TO_LE32( msd->csw.data_residue );
+
+  return msd->send( msd, &msd->csw, sizeof( usbs_msd_csw ));
+}
+
+
+// Receive Command Status Wrapper
+//
+static cyg_int32
+usbs_msd_wait_for_cbw( usbs_msd *msd )
+{
+  cyg_uint8 cbw[sizeof( usbs_msd_cbw ) + 1];
+  cyg_int32 n;
+
+  TRACE("USB Slave MSD: Wait for CBW\n\r");
+  n = msd->receive( msd, cbw, sizeof( cbw ) );
+
+  TRACE("USB Slave MSD: CBW received, len %d\n\r", n);
+
+  if ( n < 0)
+    return n;
+
+  memcpy(&msd->cbw, cbw, sizeof( usbs_msd_cbw ));
+
+  if ( ( true == usbs_msd_validate_cbw( &msd->cbw, n ) ) && \
+          ( true == usbs_msd_validate_cbw_data( &msd->cbw ) ) )
+  {
+    CONSTRUCT_CSW( msd->csw , msd->cbw.tag );
+
+    if( msd->cbw.flags == USBS_MSD_CBW_DEVICE2HOST )
+    {
+      msd->state = CYG_USBS_MSD_DATA_OUT;
+    }
+    else if ( msd->cbw.flags == USBS_MSD_CBW_HOST2DEVICE )
+    {
+      msd->state = CYG_USBS_MSD_DATA_IN;
+    }
+  }
+
+  return n;
+}
+
+// USB slave side Mass-Storage Handler
+//
+void
+usbs_msd_handler( cyg_addrword_t data )
+{
+  usbs_msd* msd = (usbs_msd*) data;
+  cyg_int32 transfered = 0;
+  cyg_int32 received   = 0;
+
+  while(1)
+  {
+
+    // Wait for device to be configured
+    DBG("USB Slave MSD: Wait for device configuration\n\r");
+    usbs_msd_wait_until_configured( msd );
+    cyg_thread_delay( (cyg_tick_count_t) 10 );
+
+    while(1)
+    {
+
+      switch( msd->state )
+      {
+         case CYG_USBS_MSD_WAIT:
+            // FIXME, check for return values
+            // For the time being, -EPIPE and -EAGAIN triggers the
+            // driver to wait for the device to be configured again.
+            received = usbs_msd_wait_for_cbw( msd );
+            if ( received < 0 )
+              break;
+            // Fall through
+
+         case CYG_USBS_MSD_DATA_IN:
+         case CYG_USBS_MSD_DATA_OUT:
+            // Handle data transfer IN and OUT
+            transfered = msd->handler_cmd( msd );
+
+            // Data transfer failed because of -EPIPE or -EAGAIN. For
+            // the time being just wait for the device to be re-configured
+            if(transfered < 0)
+            {
+              DBG("USB Slave MSD: Data transfer error\n\r");
+              msd->state = CYG_USBS_MSD_WAIT;
+              break;
+            }
+
+            // Compute the data residue value to be recorded in the
+            // Command Status Wrapper
+            msd->csw.data_residue = msd->cbw.data_transfert_len - transfered;
+
+            // Check if all data has been transfered / received to / from
+            // the host
+            if( msd->csw.data_residue != 0 )
+            {
+              DBG("USB Slave MSD: Transfer not complete %d / %d\n\r", \
+                        msd->cbw.data_transfert_len, transfered);
+
+              // Stall endpoint, this is a waiting call until the host has
+              // cleared the stall. AT91 USB driver does not seem to handle
+              // it!
+              msd->stall( msd, CYG_USBS_EP_TX );
+#if defined(CYGSEM_IO_USB_SLAVE_MSD_STALL_ENABLE)
+              TRACE("USB Slave MSD: Stall completed\n\r");
+#endif
+            }
+
+            // Complete the transaction by sending the command status
+            usbs_msd_send_csw( msd );
+
+            TRACE("USB Slave MSD: CSW sent\n\r");
+
+            // Wait for next command
+            msd->state = CYG_USBS_MSD_WAIT;
+            break;
+
+         default:
+            DBG("USB Slave MSD: Invalid state\n\r");
+            break;
+      }
+
+      if( ( transfered < 0 ) || ( received < 0 ) )
+        break;
+
+    }
+  }
+}
+
+
diff --git a/packages/io/usb/msd/slave/current/src/usbs_msd_scsi.c b/packages/io/usb/msd/slave/current/src/usbs_msd_scsi.c
new file mode 100644
--- /dev/null
+++ b/packages/io/usb/msd/slave/current/src/usbs_msd_scsi.c
@@ -0,0 +1,510 @@
+//==========================================================================
+//
+//      usbs_msd_scsi.c
+//
+//      Support for slave-side USB mass storage SCSI devices.
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand <ccoutand@stmi.com>
+//
+// Date:         2010-06-02
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/cyg_trac.h>
+#include <cyg/kernel/kapi.h>
+#include <cyg/infra/diag.h>
+
+#include <pkgconf/io_usb_slave_msd.h>
+#include <cyg/io/usb/usbs_msd.h>
+
+#include <cyg/io/usb/usbs_msd_opcode.h>
+#include <cyg/io/usb/usbs_msd_scsi.h>
+
+#include <cyg/io/disk.h>
+
+#include <stdio.h> // for memcpy
+
+#if defined(CYGBLD_IO_USB_SLAVE_MSD_DEBUG)
+#define DBG diag_printf
+#else
+#define DBG (1) ? (void)0 : diag_printf
+#endif
+
+#if defined(CYGBLD_IO_USB_SLAVE_MSD_TRACE)
+#define TRACE diag_printf
+#else
+#define TRACE (1) ? (void)0 : diag_printf
+#endif
+
+
+const msd_scsi_inq_resp inq_resp = {
+   USBS_SCSI_DIRECT_ACCESS_BLOCK_DEVICE, // Direct Access Block device
+   USBS_SCSI_REMOVABLE_DEVICE,           // Device is removable
+   0x04,                                 // Comply with SPC-2
+   0x02,                                 // Standard format
+   0x20,                                 // Response is 0x20 + 4 bytes
+   0x00,
+   0x00,
+   0x00,
+   {'e','C','o','s',' ',' ',' ',' '},
+   {'M','a','s','s',' ','S','t','o','r','a','g','e',' ',' ',' ',' '},
+   {'0','.','0','1'},
+};
+
+
+// Handle Mode Sense Command
+//
+static inline void
+usbs_msd_scsi_update_sense(msd_scsi_req_sense_resp *sense, \
+                                cyg_uint8 asc, cyg_uint8 ascq, cyg_uint8 key )
+{
+   USBS_MSD_SCSI_SET_SENSE_ASC( sense->byte , asc );
+   USBS_MSD_SCSI_SET_SENSE_ASCQ( sense->byte , ascq );
+   USBS_MSD_SCSI_SET_SENSE_KEY( sense->byte , key );
+}
+
+
+// Handle Inquiry Request Command
+//
+static inline cyg_int32
+usbs_msd_scsi_handle_inquiry( usbs_msd * msd )
+{
+   cyg_int32 tx_bytes = sizeof(msd_scsi_inq_resp);
+
+   TRACE("USB Slave MSD: SCSI inquiry\n\r");
+
+   // Copy over to message buffer
+   memcpy( msd->buffer, (cyg_uint8 *) &inq_resp, tx_bytes );
+
+   tx_bytes = msd->send( msd, msd->buffer, tx_bytes );
+
+   msd->csw.status = USBS_MSD_CSW_STATUS_PASSED;
+
+   return tx_bytes;
+}
+
+
+// Handle Read Capacity Command
+//
+static inline cyg_int32
+usbs_msd_scsi_handle_capacity( usbs_msd * msd )
+{
+   cyg_disk_info_t disk_info;
+   cyg_int32 tx_bytes = sizeof(cyg_uint32) << 1;
+   cyg_uint32 len     = sizeof(cyg_disk_info_t);
+   cyg_uint32 key     = CYG_IO_GET_CONFIG_DISK_INFO;
+   cyg_io_handle_t lun = msd->lun->handle[msd->cbw.lun];
+
+   TRACE("USB Slave MSD: SCSI capacity\n\r");
+
+   // Get the configuration of a device
+   cyg_io_get_config( lun, key, &disk_info, &len );
+
+   msd->buffer[0] = BYTE3_32( disk_info.blocks_num );
+   msd->buffer[1] = BYTE2_32( disk_info.blocks_num );
+   msd->buffer[2] = BYTE1_32( disk_info.blocks_num );
+   msd->buffer[3] = BYTE0_32( disk_info.blocks_num );
+
+   msd->buffer[4] = BYTE3_32( disk_info.block_size );
+   msd->buffer[5] = BYTE2_32( disk_info.block_size );
+   msd->buffer[6] = BYTE1_32( disk_info.block_size );
+   msd->buffer[7] = BYTE0_32( disk_info.block_size );
+
+   tx_bytes = msd->send( msd, msd->buffer, tx_bytes );
+
+   msd->csw.status = USBS_MSD_CSW_STATUS_PASSED;
+
+   return tx_bytes;
+}
+
+
+// Handle Read Command
+//
+static inline cyg_int32
+usbs_msd_scsi_handle_read( usbs_msd * msd, msd_scsi_req_sense_resp *sense )
+{
+   Cyg_ErrNo ret;
+   cyg_uint32 transfert_len = 0, pos = 0, len = 1;
+   cyg_int32 ret_len = 0;
+   cyg_int32 tx_byte = 0;
+   cyg_io_handle_t lun = msd->lun->handle[msd->cbw.lun];
+
+   TRACE("USB Slave MSD: SCSI read\n\r");
+
+   pos = ( msd->cbw.cb.data[2] << 24 ) | \
+         ( msd->cbw.cb.data[3] << 16 ) | \
+         ( msd->cbw.cb.data[4] <<  8 ) | \
+           msd->cbw.cb.data[5];
+
+   transfert_len = ( msd->cbw.cb.data[7] << 8 ) | msd->cbw.cb.data[8];
+
+   // Read data from a block device
+   while ( transfert_len > 0 ) {
+     if( ( ret = cyg_io_bread( lun, msd->buffer, &len, pos)) != ENOERR )
+       break;
+     tx_byte = msd->send( msd, msd->buffer, (USBS_MSD_DISK_SECTOR_SIZE) );
+     TRACE("USB Slave MSD: Read %d block, %d bytes\n\r", transfert_len, tx_byte);
+     ret_len += tx_byte;
+     // Substract 1 sector
+     transfert_len -= 1;
+     pos += 1;
+   }
+
+   if ( ret == ENOERR )
+   {
+      msd->csw.status = USBS_MSD_CSW_STATUS_PASSED;
+   }
+   else
+   {
+     msd->csw.status = USBS_MSD_CSW_STATUS_FAILED;
+     usbs_msd_scsi_update_sense( sense, \
+             USBS_MSD_SCSI_SENSE_ASC_UNRECOVERED_READ_ERROR, \
+             USBS_MSD_SCSI_SENSE_ASCQ_UNRECOVERED_READ_ERROR, \
+             USBS_MSD_SCSI_SENSE_MEDIUM_ERROR );
+   }
+
+   return ret_len;
+}
+
+
+// Handle Write Command
+//
+static inline cyg_int32
+usbs_msd_scsi_handle_write( usbs_msd * msd , msd_scsi_req_sense_resp *sense )
+{
+   Cyg_ErrNo ret;
+   cyg_uint32 transfert_len = 0, pos = 0, len = 1;
+   cyg_int32 ret_len = 0;
+   cyg_int32 rx_byte = 0;
+   cyg_io_handle_t lun = msd->lun->handle[msd->cbw.lun];
+
+   DBG("USB Slave MSD: SCSI Write\n\r");
+
+   pos = ( msd->cbw.cb.data[2] << 24 ) | \
+             ( msd->cbw.cb.data[3] << 16 ) | \
+             ( msd->cbw.cb.data[4] <<  8 ) | \
+               msd->cbw.cb.data[5];
+
+   transfert_len = ( msd->cbw.cb.data[7] << 8 ) | msd->cbw.cb.data[8];
+
+   // Read data from a block device
+   while ( transfert_len > 0 ) {
+     rx_byte = msd->receive( msd, msd->buffer, (USBS_MSD_DISK_SECTOR_SIZE) );
+     if( ( ret = cyg_io_bwrite( lun, msd->buffer, &len, pos)) != ENOERR )
+       break;
+     TRACE("USB Slave MSD: Write %d block, %d bytes\n\r", transfert_len, rx_byte);
+     ret_len += ( rx_byte );
+     // Substract 1 sector
+     transfert_len -= 1;
+     pos += 1;
+   }
+
+   if ( ret == ENOERR )
+   {
+     msd->csw.status = USBS_MSD_CSW_STATUS_PASSED;
+   }
+   else
+   {
+     msd->csw.status = USBS_MSD_CSW_STATUS_FAILED;
+     usbs_msd_scsi_update_sense( sense, \
+             USBS_MSD_SCSI_SENSE_ASC_WRITE_ERROR, \
+             USBS_MSD_SCSI_SENSE_ASCQ_WRITE_ERROR, \
+             USBS_MSD_SCSI_SENSE_MEDIUM_ERROR );
+   }
+
+   return ret_len;
+}
+
+
+// Handle Request Sense Command
+//
+static inline cyg_int32
+usbs_msd_scsi_handle_req_sense( usbs_msd * msd,  \
+                                      msd_scsi_req_sense_resp *sense )
+{
+   cyg_uint8 i = 0;
+   cyg_int32 tx_bytes = sizeof(msd_scsi_req_sense_resp);
+
+   TRACE("USB Slave MSD: SCSI request sense\n\r");
+
+   // Copy over to message buffer
+   for(i = 0 ; i < tx_bytes ; i++)
+       msd->buffer[i] = sense->byte[i];
+
+   tx_bytes = msd->send( msd, msd->buffer, tx_bytes );
+
+   msd->csw.status = USBS_MSD_CSW_STATUS_PASSED;
+
+   return tx_bytes;
+}
+
+
+// Handle Mode Sense Command
+//
+static inline cyg_int32
+usbs_msd_scsi_handle_sense( usbs_msd * msd,  \
+                           msd_scsi_req_sense_resp *sense )
+{
+   cyg_int32 tx_bytes = 0x0;
+   DBG("USB Slave MSD: SCSI sense\n\r");
+
+   msd->buffer[0] = 0x03; // Number of byte in the following message
+   msd->buffer[1] = 0x00; // Media type
+   msd->buffer[2] = 0x00; // Not Write protected, no cache-control-bit support
+   msd->buffer[3] = 0x00; // No Mode parameter
+
+   // FIXME : handle different option correctly. For the time being,
+   // just respond with minimum data
+   if( ( msd->cbw.cb.data[2] & 0x3F ) == \
+        USBS_MSD_SCSI_MODE_PAGE_CODE_ALL )
+   {
+     DBG("USB Slave MSD: SCSI sense all\n\r");
+
+     tx_bytes = msd->send( msd, msd->buffer, 4 );
+
+     msd->csw.status = USBS_MSD_CSW_STATUS_PASSED;
+   }
+   else
+   {
+     DBG("USB Slave MSD: SCSI sense page: %x\n\r", \
+             msd->cbw.cb.data[2]);
+
+     tx_bytes = msd->send( msd, msd->buffer, 4 );
+
+     msd->csw.status = USBS_MSD_CSW_STATUS_FAILED;
+   }
+
+   return tx_bytes;
+}
+
+
+// Handle Test Unit Ready Command
+//
+static inline cyg_int32
+usbs_msd_scsi_handle_test_unit_ready( usbs_msd * msd , \
+                                         msd_scsi_req_sense_resp *sense )
+{
+   cyg_disk_info_t disk_info;
+   Cyg_ErrNo ret;
+   cyg_uint32 len = sizeof(cyg_disk_info_t);
+   cyg_uint32 key = CYG_IO_GET_CONFIG_DISK_INFO;
+   cyg_io_handle_t lun = msd->lun->handle[msd->cbw.lun];
+
+   TRACE("USB Slave MSD: SCSI test unit ready\n\r");
+
+   // Get the configuration of a device
+   ret = cyg_io_get_config( lun, key, &disk_info, &len);
+
+   msd->csw.status = USBS_MSD_CSW_STATUS_PASSED;
+
+   USBS_MSD_SCSI_INIT_SENSE_DATA( sense->byte );
+
+   // check if disk is connected / mounted here
+   if( disk_info.connected == false )
+   {
+      DBG("USB Slave MSD: Disk not mounted \n\r");
+      usbs_msd_scsi_update_sense( sense, \
+             USBS_MSD_SCSI_SENSE_ASC_MEDIUM_NOT_PRESENT, \
+             USBS_MSD_SCSI_SENSE_ASCQ_MEDIUM_NOT_PRESENT, \
+             USBS_MSD_SCSI_SENSE_UNIT_ATTENTION);
+
+      msd->csw.status = USBS_MSD_CSW_STATUS_FAILED;
+   }
+
+   // No data to transfer
+   return 0;
+}
+
+
+// Windows host operating system uses this command. Usually if
+// a command is not supported, the CSW should return failure.
+// Since no data is sent in the data transfer phase, the TX
+// endpoint shall be stalled. Since some USB driver in eCos
+// do not support endpoint stall, is it required to respond
+// with some data, otherwise the driver would freeze. In the
+// following case, we fill the data structure but report
+// failure in the CSW.
+#if !defined(CYGSEM_IO_USB_SLAVE_MSD_STALL_ENABLE)
+// Handle Read Format Capacities
+//
+static inline cyg_int32
+usbs_msd_scsi_read_format_capacities( usbs_msd * msd )
+{
+   cyg_int32 i = 0;
+   DBG("USB Slave MSD: SCSI read format capacities\n\r");
+
+   for(i = 0 ; i < msd->cbw.data_transfert_len; i++)
+   {
+     msd->buffer[i] = 0;
+   }
+
+   i = msd->send( msd, msd->buffer, i );
+
+   msd->csw.status = USBS_MSD_CSW_STATUS_FAILED;
+
+   return i;
+}
+#endif
+
+
+// Handle Verify
+//
+static inline cyg_int32
+usbs_msd_scsi_handle_verify( usbs_msd * msd )
+{
+   DBG("USB Slave MSD: SCSI test unit verify\n\r");
+
+   // FIXME: Should do something here?
+   // Return success, command is optional
+   msd->csw.status = USBS_MSD_CSW_STATUS_PASSED;
+
+   // No data to transfer
+   return 0;
+}
+
+
+// Handle Medium Removal
+//
+static inline cyg_int32
+usbs_msd_scsi_handle_removal( usbs_msd * msd )
+{
+   DBG("USB Slave MSD: SCSI Prevent / Allow device removal, LUN %d, flag %d %d\n\r",
+          ( msd->cbw.cb.data[1] & 0xf0 >> 4 ) , ( msd->cbw.cb.data[4] & 0x01 ),
+            msd->cbw.data_transfert_len );
+
+   // Support for this command is not mandatory.
+   // No specific handling of this command is implemented.
+   // Maybe mount / umount the disc?
+   msd->csw.status = USBS_MSD_CSW_STATUS_PASSED;
+
+   // No data to transfer
+   return 0;
+}
+
+
+// Handle SCSI command
+//
+cyg_int32
+usbs_msd_scsi_handle_cmd( usbs_msd * msd )
+{
+   bool ret;
+   cyg_uint8 cmd = msd->cbw.cb.data[0];
+   msd_scsi_req_sense_resp *sense = (msd_scsi_req_sense_resp *) msd->handler_data;
+
+   switch( cmd )
+   {
+     case USBS_SCSI_INQUIRY:
+        ret = usbs_msd_scsi_handle_inquiry( msd );
+        break;
+
+     case USBS_SCSI_READ_CAPACITY:
+        ret = usbs_msd_scsi_handle_capacity( msd );
+        break;
+
+     case USBS_SCSI_READ_10:
+        ret = usbs_msd_scsi_handle_read(msd , sense );
+        break;
+
+     case USBS_SCSI_WRITE_10:
+        ret = usbs_msd_scsi_handle_write( msd , sense );
+        break;
+
+     case USBS_SCSI_REQUEST_SENSE:
+        ret = usbs_msd_scsi_handle_req_sense( msd , sense );
+        break;
+
+     case USBS_SCSI_SENSE_6:
+        ret = usbs_msd_scsi_handle_sense( msd , sense);
+        break;
+
+     case USBS_SCSI_TEST_UNIT_READY:
+        ret = usbs_msd_scsi_handle_test_unit_ready( msd , sense );
+        break;
+
+     case USBS_SCSI_VERIFY_10:
+        ret = usbs_msd_scsi_handle_verify( msd );
+        break;
+
+#if !defined(CYGSEM_IO_USB_SLAVE_MSD_STALL_ENABLE)
+     case USBS_SCSI_READ_FORMAT_CAPACITIES:
+        ret = usbs_msd_scsi_read_format_capacities( msd );
+        break;
+#endif
+
+     case USBS_SCSI_PREVENT_ALLOW_REMOVAL:
+        ret = usbs_msd_scsi_handle_removal( msd );
+        break;
+
+     default:
+        // Use for all commands not implemented, not
+        // supported
+        DBG("USB Slave MSD: SCSI illegal request %x \n\r", cmd );
+        USBS_MSD_SCSI_INIT_SENSE_DATA( sense->byte );
+        usbs_msd_scsi_update_sense( sense, \
+                USBS_MSD_SCSI_SENSE_ASC_INVALID_OPCODE, \
+                USBS_MSD_SCSI_SENSE_ASCQ_INVALID_OPCODE, \
+                USBS_MSD_SCSI_SENSE_ILLEGAL_REQUEST);
+        msd->csw.status = USBS_MSD_CSW_STATUS_FAILED;
+        ret = 0;
+        break;
+
+   }
+
+   return ret;
+
+}
+
+// SCSI initialization
+//
+bool
+usbs_msd_scsi_init( void ** ctxt )
+{
+  static msd_scsi_req_sense_resp sense;
+
+  DBG("USB Slave MSD: SCSI init %p\n", &sense);
+
+  USBS_MSD_SCSI_INIT_SENSE_DATA( sense.byte );
+
+  *ctxt = &sense;
+
+  return true;
+}
diff --git a/packages/io/usb/msd/slave/current/tests/usbs_test_ramdisk.c b/packages/io/usb/msd/slave/current/tests/usbs_test_ramdisk.c
new file mode 100644
--- /dev/null
+++ b/packages/io/usb/msd/slave/current/tests/usbs_test_ramdisk.c
@@ -0,0 +1,738 @@
+//==========================================================================
+//
+//      usb_test_ramdisk.c
+//
+//      Example application for the USB MSD layer in eCos.
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors:
+// Date:         2010-06-27
+// Description:  USB Slave Mass Storage example application.
+//
+//####DESCRIPTIONEND####
+//===========================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+
+#if defined(CYGPKG_FS_FAT)
+#include <pkgconf/io_fileio.h>
+#include <pkgconf/fs_fat.h>
+#endif
+
+#include <pkgconf/io_usb_slave_msd.h>
+#include <pkgconf/kernel.h>
+#include <cyg/kernel/kapi.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/infra/diag.h>
+#include <cyg/io/usb/usbs_msd_io.h>
+#include <cyg/io/io.h>
+#include <cyg/io/devtab.h>
+#include <cyg/io/disk.h>
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#if defined(CYGPKG_FS_FAT)
+#include <cyg/infra/cyg_trac.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/testcase.h>
+#include <unistd.h>
+#include <dirent.h>
+#include <errno.h>
+#include <cyg/fileio/fileio.h>
+#include <cyg/fs/fatfs.h>
+#endif
+
+#if defined(CYGBLD_IO_USB_SLAVE_MSD_DEBUG)
+#define DBG diag_printf
+#else
+#define DBG (1) ? (void)0 : diag_printf
+#endif
+
+// ----------------------------------------------------------------------------
+// FAT12 file-system FBR, FAT and ROOT directory entries are hardcoded
+// and later copied over to the RAM disk
+//
+
+#define USBS_MSD_RAMDISK_BLOCKLEN   512
+#define USBS_MSD_RAMDISK_NUM_BLOCK   32
+
+// Allocate space for the RAM disk
+static char ram_disk[ USBS_MSD_RAMDISK_BLOCKLEN * USBS_MSD_RAMDISK_NUM_BLOCK ] __attribute__((aligned(4)));
+
+// FAT12 Boot Record
+const char fat12_br[] = {
+   0xEB, 0x3C, 0x90,                               // Field for Bootable Media
+   0x4D, 0x53, 0x57, 0x49, 0x4E, 0x34, 0x2E, 0x31, // MSWIN4.1
+   0x00, 0x02,                                     // 512 bytes sector
+   0x01,                                           // 1 sector per cluster
+   0x01, 0x00,                                     // 1 reserved sector (including MBR)
+   0x02,                                           // 2 FATs
+   0x40, 0x00,                                     // 64 entries
+   USBS_MSD_RAMDISK_NUM_BLOCK, 0x00,               // Number of sectors is less than 32K: 32 sectors
+   0xF0,                                           // Removable media
+   0x01, 0x00,                                     // 1sector per FAT
+   0x00, 0x00,                                     // Sector per track (not used in LBA)
+   0x00, 0x00,                                     // Number of Heads (not used in LBA)
+   0x00, 0x00, 0x00, 0x00,                         // Hidden sector
+   0x00, 0x00, 0x00, 0x00,                         // Number of sectors is more than 32K
+   0x00,                                           // Logical drive number
+   0x00,                                           // Reserved
+   0x29,                                           // Extended boot signature
+   0x04, 0x03, 0x02, 0x01,                         // Serial Number
+   0x65, 0x43, 0x6F, 0x73, 0x20, 0x64, 0x69, 0x73, // VOLUME: eCos disk
+   0x6B, 0x20, 0x20,
+   0x46, 0x41, 0x54, 0x31, 0x32, 0x20, 0x20, 0x20  // FAT12
+};
+
+// MBR and Volume sector signature
+const char mbr_signature[] = {
+   0x55, 0xAA
+};
+
+// Partition table
+const char partition_tbl[] = {
+   // First (FAT12)
+   0x80, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+   0x01, 0x00, 0x00, 0x00, (USBS_MSD_RAMDISK_NUM_BLOCK-1), 0x00, 0x00, 0x00,
+   // Second
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   // Third
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   // Fourth
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+// Root directory (eCos-3.0)
+const char root_dir[] = {
+   0x65, 0x43, 0x6F, 0x73, 0x2d, 0x33, 0x2e, 0x30,
+   0x20, 0x20, 0x20, 0x28, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x91, 0x9e,
+   0x65, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+// File-system Allocation Table
+const char fat[] = {
+  0xF0, 0xff, 0xff
+};
+
+// Initialize FAT12
+static void
+init_fat12_disk( char *start_addr )
+{
+  char * dst = start_addr;
+
+  // Copy partition table
+  dst = start_addr + 446;
+  memcpy(dst, partition_tbl, 64);
+
+  // Copy signature
+  dst = start_addr + (USBS_MSD_RAMDISK_BLOCKLEN - 2 );
+  memcpy(dst, mbr_signature, 2);
+
+  // Copy FBR
+  dst = start_addr + USBS_MSD_RAMDISK_BLOCKLEN;
+  memcpy(dst, fat12_br, 62);
+
+  // Copy signature
+  dst = start_addr + (( USBS_MSD_RAMDISK_BLOCKLEN * 2 ) - 2 );
+  memcpy(dst, mbr_signature, 2);
+
+  // Copy FAT0
+  dst = start_addr + ( USBS_MSD_RAMDISK_BLOCKLEN * 2);
+  memcpy(dst, fat, 3);
+
+  // Copy FAT1
+  dst = start_addr + ( USBS_MSD_RAMDISK_BLOCKLEN * 3);
+  memcpy(dst, fat, 3);
+
+  // Copy Root directory
+  dst = start_addr + ( USBS_MSD_RAMDISK_BLOCKLEN * 4);
+  memcpy(dst, root_dir, 32);
+
+}
+
+
+// ----------------------------------------------------------------------------
+// Create a tiny "RAM disk" device
+//
+//
+
+#define RAM_DISK_NAME "/dev/ramdisk0/"
+
+typedef struct {
+    volatile cyg_uint8 *base;
+    cyg_uint16 size;
+} ram_disk_info_t;
+
+static cyg_bool ram_disk_init(struct cyg_devtab_entry *tab);
+
+static Cyg_ErrNo ram_disk_bread(disk_channel *chan,
+                              void         *buf,
+                              cyg_uint32    len,
+                              cyg_uint32    block_num);
+
+
+static Cyg_ErrNo ram_disk_bwrite(disk_channel *chan,
+                               const void   *buf,
+                               cyg_uint32    len,
+                               cyg_uint32    block_num);
+
+static Cyg_ErrNo ram_disk_get_config(disk_channel *chan,
+                               cyg_uint32    key,
+                               const void   *xbuf,
+                               cyg_uint32   *len);
+
+static Cyg_ErrNo ram_disk_set_config(disk_channel *chan,
+                               cyg_uint32    key,
+                               const void   *xbuf,
+                               cyg_uint32   *len);
+
+static Cyg_ErrNo ram_disk_lookup(struct cyg_devtab_entry **tab,
+                                struct cyg_devtab_entry  *sub_tab,
+                                const char               *name);
+
+DISK_FUNS(ram_disk_funs,
+          ram_disk_bread,
+          ram_disk_bwrite,
+          ram_disk_get_config,
+          ram_disk_set_config
+);
+
+DISK_CONTROLLER(ram_disk_controller, ram_disk_controller);
+
+#define RAM_DISK_INSTANCE(_number_,_base_,_mbr_supp_,_name_)    \
+static ram_disk_info_t ram_disk_info##_number_ = {              \
+    base: (volatile cyg_uint8 *)_base_,                         \
+};                                                              \
+DISK_CHANNEL(ram_disk_channel##_number_,                        \
+             ram_disk_funs,                                     \
+             ram_disk_info##_number_,                           \
+             ram_disk_controller,                               \
+             _mbr_supp_,                                        \
+             1                                                  \
+);                                                              \
+BLOCK_DEVTAB_ENTRY(ram_disk_io##_number_,                       \
+             _name_,                                            \
+             0,                                                 \
+             &cyg_io_disk_devio,                                \
+             ram_disk_init,                                     \
+             ram_disk_lookup,                                   \
+             &ram_disk_channel##_number_                        \
+);
+
+RAM_DISK_INSTANCE(0, 0, true, RAM_DISK_NAME);
+
+
+// ----------------------------------------------------------------------------
+static void
+read_data(volatile cyg_uint8  *base,
+          void                *buf,
+          cyg_uint32           len)
+{
+    cyg_uint8 *dst = (cyg_uint8 *)buf;
+    cyg_uint8 *src = (cyg_uint8 *)base;
+    cyg_uint32 i = 0;
+
+    for (i = 0; i < len; i += 1)
+    {
+        *dst = *src;
+        dst = dst + 1; src = src + 1;
+    }
+
+}
+
+static void
+write_data(volatile cyg_uint8  *base,
+           const void          *buf,
+           cyg_uint16           len)
+{
+    cyg_uint8 *dst = (cyg_uint8 *)base;
+    cyg_uint8 *src = (cyg_uint8 *)buf;
+    cyg_uint32 i = 0;
+
+    for (i = 0; i < len; i += 1)
+    {
+        *dst = *src;
+         dst = dst + 1; src = src + 1;
+    }
+}
+
+// ----------------------------------------------------------------------------
+static cyg_bool
+ram_disk_init(struct cyg_devtab_entry *tab)
+{
+    disk_channel           *chan = (disk_channel *) tab->priv;
+    ram_disk_info_t         *info = (ram_disk_info_t *) chan->dev_priv;
+    cyg_disk_identify_t     ident;
+
+    if (chan->init)
+        return true;
+
+    info->base = (volatile cyg_uint8 *) &ram_disk[0];
+    info->size = USBS_MSD_RAMDISK_BLOCKLEN * USBS_MSD_RAMDISK_NUM_BLOCK;
+
+    DBG("RAM DISK ( %p ) init\n", info->base);
+
+    init_fat12_disk( &ram_disk[0] );
+
+    ident.cylinders_num   =  0;
+    ident.heads_num       =  0;
+    ident.lba_sectors_num = USBS_MSD_RAMDISK_NUM_BLOCK-2;
+    ident.phys_block_size = USBS_MSD_RAMDISK_BLOCKLEN;
+    ident.max_transfer    = USBS_MSD_RAMDISK_BLOCKLEN;
+
+    if (!(chan->callbacks->disk_init)(tab))
+        return false;
+
+    if (ENOERR != (chan->callbacks->disk_connected)(tab, &ident))
+        return false;
+
+    return true;
+}
+
+static Cyg_ErrNo
+ram_disk_lookup(struct cyg_devtab_entry **tab,
+               struct cyg_devtab_entry  *sub_tab,
+               const char *name)
+{
+    disk_channel *chan = (disk_channel *) (*tab)->priv;
+    return (chan->callbacks->disk_lookup)(tab, sub_tab, name);
+}
+
+static Cyg_ErrNo
+ram_disk_bread(disk_channel *chan,
+             void         *buf,
+             cyg_uint32    len,
+             cyg_uint32    block_num)
+{
+    ram_disk_info_t *info = (ram_disk_info_t *)chan->dev_priv;
+    volatile cyg_uint8 *src = info->base + USBS_MSD_RAMDISK_BLOCKLEN * block_num;
+    cyg_uint32 len_byte = len * USBS_MSD_RAMDISK_BLOCKLEN;
+
+    if ( len_byte == 0 )
+      return EINVAL;
+
+    read_data(src, buf, len_byte);
+
+    return ENOERR;
+}
+
+static Cyg_ErrNo
+ram_disk_bwrite(disk_channel *chan,
+              const void   *buf,
+              cyg_uint32    len,
+              cyg_uint32    block_num)
+{
+    ram_disk_info_t *info = (ram_disk_info_t *)chan->dev_priv;
+    volatile cyg_uint8 *dst = info->base + USBS_MSD_RAMDISK_BLOCKLEN * block_num;
+    cyg_uint32 len_byte = len * USBS_MSD_RAMDISK_BLOCKLEN;
+
+    if ( len_byte == 0 )
+      return EINVAL;
+
+    write_data(dst, buf, len_byte);
+
+    return ENOERR;
+}
+
+static Cyg_ErrNo
+ram_disk_get_config(disk_channel *chan,
+                   cyg_uint32    key,
+                   const void   *xbuf,
+                   cyg_uint32   *len)
+{
+    return -EINVAL;
+}
+
+static Cyg_ErrNo
+ram_disk_set_config(disk_channel *chan,
+                   cyg_uint32    key,
+                   const void   *xbuf,
+                   cyg_uint32   *len)
+{
+    return -EINVAL;
+}
+
+
+// ----------------------------------------------------------------------------
+// In case FAT file-system package is included, this application will try
+// to play with the file-system before it is mounted as a mass storage device.
+// The following code is a copy of the fatfs1.c from the fs/test directory
+//
+#if defined(CYGPKG_FS_FAT)
+
+#define SHOW_RESULT( _fn, _res ) \
+  DBG("<FAIL>: " #_fn "() returned %d %s\n", _res, _res<0?strerror(errno):"");
+
+#define IOSIZE  100
+
+//==========================================================================
+
+void checkcwd( const char *cwd )
+{
+    static char cwdbuf[PATH_MAX];
+    char *ret;
+
+    ret = getcwd( cwdbuf, sizeof(cwdbuf));
+    if( ret == NULL ) SHOW_RESULT( getcwd, (int)ret );
+
+    if( strcmp( cwdbuf, cwd ) != 0 )
+    {
+        DBG( "cwdbuf %s cwd %s\n",cwdbuf, cwd );
+        CYG_TEST_FAIL( "Current directory mismatch");
+    }
+}
+
+//==========================================================================
+
+static void listdir( char *name, int statp, int numexpected, int *numgot )
+{
+    int err;
+    DIR *dirp;
+    int num=0;
+
+    DBG("<INFO>: reading directory %s\n",name);
+
+    dirp = opendir( name );
+    if( dirp == NULL ) SHOW_RESULT( opendir, -1 );
+
+    for(;;)
+    {
+        struct dirent *entry = readdir( dirp );
+
+        if( entry == NULL )
+            break;
+        num++;
+        DBG("<INFO>: entry %14s",entry->d_name);
+#ifdef CYGPKG_FS_FAT_RET_DIRENT_DTYPE
+        DBG(" d_type %2x", entry->d_type);
+#endif
+        if( statp )
+        {
+            char fullname[PATH_MAX];
+            struct stat sbuf;
+
+            if( name[0] )
+            {
+                strcpy(fullname, name );
+                if( !(name[0] == '/' && name[1] == 0 ) )
+                    strcat(fullname, "/" );
+            }
+            else fullname[0] = 0;
+
+            strcat(fullname, entry->d_name );
+
+            err = stat( fullname, &sbuf );
+            if( err < 0 )
+            {
+                if( errno == ENOSYS )
+                    DBG(" <no status available>");
+                else SHOW_RESULT( stat, err );
+            }
+            else
+            {
+                DBG(" [mode %08x ino %08x nlink %d size %ld]",
+                            sbuf.st_mode,sbuf.st_ino,sbuf.st_nlink,(long)sbuf.st_size);
+            }
+#ifdef CYGPKG_FS_FAT_RET_DIRENT_DTYPE
+            if ((entry->d_type & S_IFMT) != (sbuf.st_mode & S_IFMT))
+              CYG_TEST_FAIL("File mode's don't match between dirent and stat");
+#endif
+        }
+
+        DBG("\n");
+    }
+
+    err = closedir( dirp );
+    if( err < 0 ) SHOW_RESULT( stat, err );
+    if (numexpected >= 0 && num != numexpected)
+        CYG_TEST_FAIL("Wrong number of dir entries\n");
+    if ( numgot != NULL )
+        *numgot = num;
+}
+
+//==========================================================================
+
+static void createfile( char *name, size_t size )
+{
+    char buf[IOSIZE];
+    int fd;
+    ssize_t wrote;
+    int i;
+    int err;
+
+    DBG("<INFO>: create file %s size %zd \n",name,size);
+
+    err = access( name, F_OK );
+    if( err < 0 && errno != EACCES ) SHOW_RESULT( access, err );
+
+    for( i = 0; i < IOSIZE; i++ ) buf[i] = i%256;
+
+    fd = open( name, O_WRONLY|O_CREAT );
+    if( fd < 0 ) SHOW_RESULT( open, fd );
+
+    while( size > 0 )
+    {
+        ssize_t len = size;
+        if ( len > IOSIZE ) len = IOSIZE;
+
+        wrote = write( fd, buf, len );
+        if( wrote != len ) SHOW_RESULT( write, (int)wrote );
+
+        size -= wrote;
+    }
+
+    err = close( fd );
+    if( err < 0 ) SHOW_RESULT( close, err );
+}
+
+//==========================================================================
+
+static void checkfile( char *name )
+{
+    char buf[IOSIZE];
+    int fd;
+    ssize_t done;
+    int i;
+    int err;
+    off_t pos = 0;
+
+    DBG("<INFO>: check file %s\n",name);
+
+    err = access( name, F_OK );
+    if( err != 0 ) SHOW_RESULT( access, err );
+
+    fd = open( name, O_RDONLY );
+    if( fd < 0 ) SHOW_RESULT( open, fd );
+
+    for(;;)
+    {
+        done = read( fd, buf, IOSIZE );
+        if( done < 0 ) SHOW_RESULT( read, (int)done );
+
+        if( done == 0 ) break;
+
+        for( i = 0; i < done; i++ )
+            if( buf[i] != i%256 )
+            {
+                DBG("buf[%ld+%d](%02x) != %02x\n",pos,i,buf[i],i%256);
+                CYG_TEST_FAIL("Data read not equal to data written\n");
+            }
+
+        pos += done;
+    }
+
+    err = close( fd );
+    if( err < 0 ) SHOW_RESULT( close, err );
+}
+
+//==========================================================================
+
+static void copyfile( char *name2, char *name1 )
+{
+
+    int err;
+    char buf[IOSIZE];
+    int fd1, fd2;
+    ssize_t done, wrote;
+
+    DBG("<INFO>: copy file %s -> %s\n",name2,name1);
+
+    err = access( name1, F_OK );
+    if( err < 0 && errno != EACCES ) SHOW_RESULT( access, err );
+
+    err = access( name2, F_OK );
+    if( err != 0 ) SHOW_RESULT( access, err );
+
+    fd1 = open( name1, O_WRONLY|O_CREAT );
+    if( fd1 < 0 ) SHOW_RESULT( open, fd1 );
+
+    fd2 = open( name2, O_RDONLY );
+    if( fd2 < 0 ) SHOW_RESULT( open, fd2 );
+
+    for(;;)
+    {
+        done = read( fd2, buf, IOSIZE );
+        if( done < 0 ) SHOW_RESULT( read, (int)done );
+
+        if( done == 0 ) break;
+
+        wrote = write( fd1, buf, done );
+        if( wrote != done ) SHOW_RESULT( write, (int) wrote );
+
+        if( wrote != done ) break;
+    }
+
+    err = close( fd1 );
+    if( err < 0 ) SHOW_RESULT( close, err );
+
+    err = close( fd2 );
+    if( err < 0 ) SHOW_RESULT( close, err );
+
+}
+
+//==========================================================================
+
+static void comparefiles( char *name2, char *name1 )
+{
+    int err;
+    char buf1[IOSIZE];
+    char buf2[IOSIZE];
+    int fd1, fd2;
+    ssize_t done1, done2;
+    int i;
+
+    DBG("<INFO>: compare files %s == %s\n",name2,name1);
+
+    err = access( name1, F_OK );
+    if( err != 0 ) SHOW_RESULT( access, err );
+
+    err = access( name1, F_OK );
+    if( err != 0 ) SHOW_RESULT( access, err );
+
+    fd1 = open( name1, O_RDONLY );
+    if( fd1 < 0 ) SHOW_RESULT( open, fd1 );
+
+    fd2 = open( name2, O_RDONLY );
+    if( fd2 < 0 ) SHOW_RESULT( open, fd2 );
+
+    for(;;)
+    {
+        done1 = read( fd1, buf1, IOSIZE );
+        if( done1 < 0 ) SHOW_RESULT( read, (int)done1 );
+
+        done2 = read( fd2, buf2, IOSIZE );
+        if( done2 < 0 ) SHOW_RESULT( read, (int)done2 );
+
+        if( done1 != done2 )
+            DBG("Files different sizes\n");
+
+        if( done1 == 0 ) break;
+
+        for( i = 0; i < done1; i++ )
+            if( buf1[i] != buf2[i] )
+            {
+                DBG("buf1[%d](%02x) != buf1[%d](%02x)\n",i,buf1[i],i,buf2[i]);
+                CYG_TEST_FAIL("Data in files not equal\n");
+            }
+    }
+
+    err = close( fd1 );
+    if( err < 0 ) SHOW_RESULT( close, err );
+
+    err = close( fd2 );
+    if( err < 0 ) SHOW_RESULT( close, err );
+
+}
+
+#endif
+
+
+
+// ----------------------------------------------------------------------------
+// Entry point of the test application. If the FAT file-system package is
+// included, the file-system is mounted and tested before the USB Mass Storage
+// service is started.
+//
+// Once the mass storage device is mounted on the host computer, 2 files
+// (foo and fee) and one directory (bar) should appear in the device
+//
+
+int cyg_start(void)
+{
+#if defined(CYGPKG_FS_FAT)
+  int err;
+  int existingdirents=-1;
+#endif
+
+  DBG("Start USB MSD application\n\r");
+
+#if defined(CYGPKG_FS_FAT)
+
+  // Mount RAM disk partition 1
+  err = mount( "/dev/ramdisk0/1", "/", "fatfs" );
+
+  if( err < 0 )
+     SHOW_RESULT( mount, err );
+
+  err = chdir( "/" );
+  if( err < 0 )
+     SHOW_RESULT( chdir, err );
+
+  checkcwd( "/" );
+
+  // Display list of all files/directories from root
+  listdir( "/", true, -1, &existingdirents );
+
+  // Play around with the file-system, create / copy /
+  // compare files
+  createfile( "/foo", 1000 );
+  checkfile( "foo" );
+  copyfile( "foo", "fee" );
+  checkfile( "fee" );
+  comparefiles( "foo", "/fee" );
+  DBG("<INFO>: mkdir bar\n");
+
+  // Create new directory
+  err = mkdir( "/bar", 0 );
+  if( err < 0 )
+     SHOW_RESULT( mkdir, err );
+
+  // Display list of all files/directories from root
+  listdir( "/" , true, existingdirents+3, NULL );
+
+  // Umount file-system
+  err = umount( "/" );
+
+  if( err < 0 )
+     SHOW_RESULT( umount, err );
+
+#endif
+
+  // Start Mass Storage Service
+  usbs_msd_start();
+
+  // Start scheduler
+  cyg_scheduler_start();
+
+}
diff --git a/packages/io/usb/serial/slave/current/ChangeLog b/packages/io/usb/serial/slave/current/ChangeLog
--- a/packages/io/usb/serial/slave/current/ChangeLog
+++ b/packages/io/usb/serial/slave/current/ChangeLog
@@ -1,3 +1,14 @@
+2010-10-27  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/usb_serial.cdl: Place static endpoint struct options in a CDL
+	component.
+	* src/usbs_serial.c: Use usbs_get_[tr]x_endpoint() when static
+	endpoint structs are disabled. [ Bugzilla 1001024 ]
+	* tests/usbserial_echo.c, tests/usb2serial.c: Eliminate inclusion of
+	the AT91 USB slave driver header file.
+	* doc/usbs_serial.sgml: Mention the new static endpoint struct CDL
+	component.
+
 2009-11-13  John Dallaway  <john@dallaway.org.uk>
 
 	* cdl/usb_serial.cdl: Specify test executable names for compatibility
@@ -38,7 +49,7 @@ 2008-07-12  Frank Pagliughi <fpagliughi@
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008, 2009 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.                        
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/io/usb/serial/slave/current/cdl/usbs_serial.cdl b/packages/io/usb/serial/slave/current/cdl/usbs_serial.cdl
--- a/packages/io/usb/serial/slave/current/cdl/usbs_serial.cdl
+++ b/packages/io/usb/serial/slave/current/cdl/usbs_serial.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 2008, 2009 Free Software Foundation, Inc.                        
+## Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.                        
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -40,7 +40,7 @@
 ######DESCRIPTIONBEGIN####
 #
 # Author(s):      Frank M. Pagliughi (fmp), SoRo Systems, Inc.
-# Contributors:
+# Contributors:   jld
 # Date:           2008-06-04
 #
 #####DESCRIPTIONEND####
@@ -105,17 +105,6 @@ cdl_package CYGPKG_IO_USB_SLAVE_SERIAL {
             The endpoint that should be used for the device-side
             transmitter, which is the USB IN direction."
     }
-    cdl_option CYGDAT_IO_USB_SLAVE_SERIAL_TX_EP {
-        display         "The Tx (USB IN) endpoint structure"
-         flavor         data               
-         default_value  { "usbs_at91_ep1" }
-         description    "
-             The endpoint structure that corresponds to the selected
-             Tx endpoint number. This is dependent on the USBS device
-             driver selected, and could be usbs_at91_ep1,
-             usbs_sa11x0_ep1, etc"
-
-    }
     cdl_option CYGNUM_IO_USB_SLAVE_SERIAL_RX_EP_NUM {
         display         "Rx (USB OUT) endpoint number"
         flavor          data
@@ -124,16 +113,39 @@ cdl_package CYGPKG_IO_USB_SLAVE_SERIAL {
             The endpoint that should be used for the device-side
             receiver, which is the USB OUT direction."
     } 
-    cdl_option CYGDAT_IO_USB_SLAVE_SERIAL_RX_EP {
-        display         "The Rx (USB OUT) endpoint structure"
-         flavor         data               
-         default_value  { "usbs_at91_ep2" }
-         description    "
-             The endpoint structure that corresponds to the selected
-             Rx endpoint number. This is dependent on the USBS device
-             driver selected, and could be usbs_at91_ep2,
-             usbs_sa11x0_ep2, etc"
+
+    cdl_component CYGPKG_IO_USB_SLAVE_SERIAL_STATIC_EP {
+        display         "Use static I/O endpoint structures"
+        flavor          bool
+        default_value   1
+        description     "
+            Enables the use of static I/O endpoint structures. Some
+            USB slave device drivers implement dynamic endpoint
+            configuration and therefore require this component to be
+            disabled."
+
+        cdl_option CYGDAT_IO_USB_SLAVE_SERIAL_TX_EP {
+            display         "The Tx (USB IN) endpoint structure"
+            flavor         data               
+            default_value  { "usbs_at91_ep1" }
+            description    "
+                The endpoint structure that corresponds to the selected
+                Tx endpoint number. This is dependent on the USBS device
+                driver selected, and could be usbs_at91_ep1,
+                usbs_sa11x0_ep1, etc"
+        }
+        cdl_option CYGDAT_IO_USB_SLAVE_SERIAL_RX_EP {
+            display         "The Rx (USB OUT) endpoint structure"
+            flavor         data               
+            default_value  { "usbs_at91_ep2" }
+            description    "
+                The endpoint structure that corresponds to the selected
+                Rx endpoint number. This is dependent on the USBS device
+                driver selected, and could be usbs_at91_ep2,
+                usbs_sa11x0_ep2, etc"
+        }
     }
+    
     cdl_option CYGNUM_IO_USB_SLAVE_SERIAL_INTR_EP_NUM {
         display         "Interrupt IN endpoint number"
         flavor          data
diff --git a/packages/io/usb/serial/slave/current/doc/usbs_serial.sgml b/packages/io/usb/serial/slave/current/doc/usbs_serial.sgml
--- a/packages/io/usb/serial/slave/current/doc/usbs_serial.sgml
+++ b/packages/io/usb/serial/slave/current/doc/usbs_serial.sgml
@@ -11,7 +11,7 @@
 <!-- =============================================================== -->
 <!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
 <!-- =============================================================== -->
-<!-- Copyright (C) 2008 Free Software Foundation, Inc.               -->
+<!-- Copyright (C) 2008, 2010 Free Software Foundation, Inc.         -->
 <!-- This material may be distributed only subject to the terms      -->
 <!-- and conditions set forth in the Open Publication License, v1.0  -->
 <!-- or later (the latest version is presently available at          -->
@@ -26,6 +26,7 @@
 <!--                                                                 -->
 <!-- Author(s):   Andrew Lunn, Frank Pagliughi                       -->
 <!-- Contact(s):  asl                                                -->
+<!-- Contributor: jld                                                -->
 <!-- Date:        2008/06/18                                         -->
 <!-- Version:     0.01                                               -->
 <!--                                                                 -->
@@ -111,7 +112,9 @@
       <para>
         The <literal>CYGDAT_IO_USB_SLAVE_SERIAL_EP0</literal> must be
         configured with the control end point of the USB
-        device. <literal>CYGDAT_IO_USB_SLAVE_SERIAL_TX_EP</literal>
+        device. When using static endpoint configuration,
+        <literal>CYGPKG_IO_USB_SLAVE_SERIAL_STATIC_EP</literal> must be
+        enabled, <literal>CYGDAT_IO_USB_SLAVE_SERIAL_TX_EP</literal>
         must be configured with the endpoint to be used for
         transmission and  
         <literal>CYGDAT_IO_USB_SLAVE_SERIAL_RX_EP</literal> must be
diff --git a/packages/io/usb/serial/slave/current/src/usbs_serial.c b/packages/io/usb/serial/slave/current/src/usbs_serial.c
--- a/packages/io/usb/serial/slave/current/src/usbs_serial.c
+++ b/packages/io/usb/serial/slave/current/src/usbs_serial.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2010 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -40,6 +40,7 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):    Frank M. Pagliughi (fmp), SoRo Systems, Inc.
+// Contributors: jld
 // Date:         2008-06-02
 //
 //####DESCRIPTIONEND####
@@ -67,16 +68,19 @@
 #define EP0_MAX_PACKET_SIZE     CYGNUM_IO_USB_SLAVE_SERIAL_EP0_MAX_PACKET_SIZE
 
 extern usbs_control_endpoint    CYGDAT_IO_USB_SLAVE_SERIAL_EP0;
+
+#if defined(CYGPKG_IO_USB_SLAVE_SERIAL_STATIC_EP)
 extern usbs_tx_endpoint         CYGDAT_IO_USB_SLAVE_SERIAL_TX_EP;
 extern usbs_rx_endpoint         CYGDAT_IO_USB_SLAVE_SERIAL_RX_EP;
+#define TX_EP                   (&CYGDAT_IO_USB_SLAVE_SERIAL_TX_EP)
+#define RX_EP                   (&CYGDAT_IO_USB_SLAVE_SERIAL_RX_EP)
+#define INTR_EP                 (&CYGDAT_IO_USB_SLAVE_SERIAL_INTR_EP)
+#endif
 
 #define TX_EP_NUM               CYGNUM_IO_USB_SLAVE_SERIAL_TX_EP_NUM
 #define RX_EP_NUM               CYGNUM_IO_USB_SLAVE_SERIAL_RX_EP_NUM
 #define INTR_EP_NUM             CYGNUM_IO_USB_SLAVE_SERIAL_INTR_EP_NUM
 #define EP0                     (&CYGDAT_IO_USB_SLAVE_SERIAL_EP0)
-#define TX_EP                   (&CYGDAT_IO_USB_SLAVE_SERIAL_TX_EP)
-#define RX_EP                   (&CYGDAT_IO_USB_SLAVE_SERIAL_RX_EP)
-#define INTR_EP                 (&CYGDAT_IO_USB_SLAVE_SERIAL_INTR_EP)
 
 
 #define VENDOR_ID               CYGNUM_IO_USB_SLAVE_SERIAL_VENDOR_ID
@@ -279,8 +283,6 @@ cyg_cond_t  usbs_serial_state_cond;
 int usbs_serial_state;
 
 usbs_serial usbs_ser0 = {
-    tx_ep:      TX_EP,
-    rx_ep:      RX_EP,
     tx_result:  0,    
     rx_result:  0,    
 };
@@ -402,6 +404,12 @@ usbs_serial_wait_until_configured(void)
   cyg_mutex_lock(&usbs_serial_lock);
   while (usbs_serial_state != USBS_STATE_CONFIGURED)
     cyg_cond_wait(&usbs_serial_state_cond);
+
+#if !defined(CYGPKG_IO_USB_SLAVE_SERIAL_STATIC_EP)
+  usbs_ser0.tx_ep = usbs_get_tx_endpoint(usbs_serial_ep0, TX_EP_NUM);
+  usbs_ser0.rx_ep = usbs_get_rx_endpoint(usbs_serial_ep0, RX_EP_NUM);
+#endif
+
   cyg_mutex_unlock(&usbs_serial_lock);
 }
 
@@ -517,7 +525,11 @@ usbs_serial_init(usbs_serial* ser, usbs_
 void
 usbs_serial_start(void)
 {
+#if defined(CYGPKG_IO_USB_SLAVE_SERIAL_STATIC_EP)
   usbs_serial_init(&usbs_ser0, TX_EP, RX_EP);
+#else  
+  usbs_serial_init(&usbs_ser0, NULL, NULL);
+#endif
   
   cyg_mutex_init(&usbs_serial_lock);
   cyg_cond_init(&usbs_serial_state_cond, &usbs_serial_lock);
diff --git a/packages/io/usb/serial/slave/current/tests/usb2serial.c b/packages/io/usb/serial/slave/current/tests/usb2serial.c
--- a/packages/io/usb/serial/slave/current/tests/usb2serial.c
+++ b/packages/io/usb/serial/slave/current/tests/usb2serial.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2010 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -53,8 +53,6 @@
 #include <pkgconf/kernel.h>
 #include <cyg/io/serialio.h>
 
-// Replace this with any other USB driver desired.
-#include <cyg/io/usb/usbs_at91.h>
 #include <cyg/io/usb/usbs_serial.h>
 #include <pkgconf/io_usb_slave_serial.h>
 
diff --git a/packages/io/usb/serial/slave/current/tests/usbserial_echo.c b/packages/io/usb/serial/slave/current/tests/usbserial_echo.c
--- a/packages/io/usb/serial/slave/current/tests/usbserial_echo.c
+++ b/packages/io/usb/serial/slave/current/tests/usbserial_echo.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2010 Free Software Foundation, Inc.                        
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -51,7 +51,6 @@
 #include <cyg/hal/hal_arch.h>
 #include <cyg/infra/diag.h>
 #include <pkgconf/kernel.h>
-#include <cyg/io/usb/usbs_at91.h>
 #include <cyg/io/usb/usbs_serial.h>
 
 #include <stdio.h>
diff --git a/packages/io/usb/slave/current/ChangeLog b/packages/io/usb/slave/current/ChangeLog
--- a/packages/io/usb/slave/current/ChangeLog
+++ b/packages/io/usb/slave/current/ChangeLog
@@ -1,3 +1,13 @@
+2010-10-26  John Dallaway  <john@dallaway.org.uk>
+
+	* src/usbs.c, include/usbs.h: Extend usbs_control_endpoint struct and
+	provide usbs_get_*_endpoint() functions to facilitate dynamic data
+	endpoint configuration. Contributed by Chris Holgate.
+	[ Bugzilla 1001024]
+	* doc/usbs.sgml: Document the above changes.
+	* cdl/usbs.cdl: Fix erroneous CYGPKG_IO_USB_SLAVE_TESTS display
+	string.
+
 2008-08-28  Bart Veer  <bartv@ecoscentric.com>
 
 	* host/configure: regenerate after update of Tcl macro
@@ -186,7 +196,7 @@ 2000-11-21  Bart Veer  <bartv@redhat.com
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2010 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/io/usb/slave/current/cdl/usbs.cdl b/packages/io/usb/slave/current/cdl/usbs.cdl
--- a/packages/io/usb/slave/current/cdl/usbs.cdl
+++ b/packages/io/usb/slave/current/cdl/usbs.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2010 Free Software Foundation, Inc.
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -123,7 +123,7 @@ cdl_package CYGPKG_IO_USB_SLAVE {
     }
     
     cdl_option CYGPKG_IO_USB_SLAVE_TESTS {
-	display   "Kernel tests"
+	display   "USB slave tests"
 	flavor    data
 	no_define
 	default_value { "" }
diff --git a/packages/io/usb/slave/current/doc/usbs.sgml b/packages/io/usb/slave/current/doc/usbs.sgml
--- a/packages/io/usb/slave/current/doc/usbs.sgml
+++ b/packages/io/usb/slave/current/doc/usbs.sgml
@@ -11,7 +11,7 @@
 <!-- =============================================================== -->
 <!-- ####ECOSDOCCOPYRIGHTBEGIN####                                       -->
 <!-- ===============================================================     -->
-<!-- Copyright (C) 2001, 2002 Free Software Foundation, Inc.             -->
+<!-- Copyright (C) 2001, 2002, 2010 Free Software Foundation, Inc.       -->
 <!-- This material may be distributed only subject to the terms          -->
 <!-- and conditions set forth in the Open Publication License, v1.0      -->
 <!-- or later (the latest version is presently available at              -->
@@ -26,6 +26,7 @@
 <!--                                                                 -->
 <!-- Author(s):   bartv                                              -->
 <!-- Contact(s):  bartv                                              -->
+<!-- Contributor: jld                                                -->
 <!-- Date:        2001/01/03                                         -->
 <!-- Version:     0.01                                               -->
 <!--                                                                 -->
@@ -1952,6 +1953,28 @@ be identified in the data structure as w
 </para>
 </refsect2>
 
+<refsect2><title>Dynamic Data Endpoint Support</title>
+<programlisting width=72>
+typedef struct usbs_control_endpoint {
+    struct usbs_rx_endpoint* (*get_rxep_fn)(struct usbs_control_endpoint*, cyg_uint8);
+    struct usbs_tx_endpoint* (*get_txep_fn)(struct usbs_control_endpoint*, cyg_uint8);
+    &hellip;
+} usbs_control_endpoint;
+</programlisting>
+<para>
+USB slave hardware may support multiple USB configurations via
+configurable data endpoints. If the device driver can support such
+operation, it will provide a pair of functions via the
+<structfield>get_rxep_fn</structfield> and
+<structfield>get_txep_fn</structfield> fields which enable retrieval
+of the receive and transmit data endpoint structures using the logical
+endpoint IDs specified in a USB class descriptor. Access to these
+functions from higher-level code is provided by the
+<function>usbs_get_rx_endpoint</function> and
+<function>usbs_get_tx_endpoint</function> functions.
+</para>
+</refsect2>
+
 </refsect1>
 
 </refentry>
diff --git a/packages/io/usb/slave/current/include/usbs.h b/packages/io/usb/slave/current/include/usbs.h
--- a/packages/io/usb/slave/current/include/usbs.h
+++ b/packages/io/usb/slave/current/include/usbs.h
@@ -10,7 +10,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2010 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -171,6 +171,10 @@ typedef enum {
     USBS_CONTROL_RETURN_STALL   = 2
 } usbs_control_return;
 
+// Forward type definitions - see below for structure detail.
+struct usbs_rx_endpoint;
+struct usbs_tx_endpoint;
+
 typedef struct usbs_control_endpoint {
     // The state is maintained by the USB code and should not be
     // modified by anything higher up.
@@ -274,6 +278,27 @@ typedef struct usbs_control_endpoint {
     void*               fill_data;
     int                 fill_index;
     usbs_control_return (*complete_fn)(struct usbs_control_endpoint*, int);
+
+    // The following two functions provide a common API for accessing
+    // USB data endpoints.  This avoids class drivers needing to know 
+    // about the physical configuration of endpoints for each underlying
+    // USB slave device driver.  The functions are used to map the 
+    // logical endpoint ID (as specified in the USB class descriptors) to 
+    // the appropriate endpoint data structure (as used by the eCos USB 
+    // slave API calls).  Individual USB slave drivers are free to implement
+    // this mapping in the most appropriate manner for the underlying
+    // hardware.  This may be via CDL compile time options or preferably 
+    // by scanning the supplied class driver descriptors at runtime.
+    // The latter method allows eCos to support multiple USB configurations
+    // in a single USB device.  For this reason, these functions will only
+    // yield a valid endpoint mapping while the USB device is in its
+    // configured state.  In all other states they will return a null
+    // pointer.  These functions should also return a null pointer if the 
+    // requested endpoint ID is not valid for the currently selected 
+    // configuration.
+    struct usbs_rx_endpoint* (*get_rxep_fn)(struct usbs_control_endpoint*, cyg_uint8);
+    struct usbs_tx_endpoint* (*get_txep_fn)(struct usbs_control_endpoint*, cyg_uint8);
+    
 } usbs_control_endpoint;
 
 // Data endpoints are a little bit simpler, but not much. From the
@@ -341,6 +366,10 @@ extern void     usbs_set_rx_endpoint_hal
 extern void     usbs_set_tx_endpoint_halted(usbs_tx_endpoint*, cyg_bool);
 extern void     usbs_start_rx_endpoint_wait(usbs_rx_endpoint*, void (*)(void*, int), void*);
 extern void     usbs_start_tx_endpoint_wait(usbs_tx_endpoint*, void (*)(void*, int), void*);
+
+// Utility function to access USB data endpoints by logical endpoint ID.
+extern usbs_rx_endpoint* usbs_get_rx_endpoint(usbs_control_endpoint*, cyg_uint8);
+extern usbs_tx_endpoint* usbs_get_tx_endpoint(usbs_control_endpoint*, cyg_uint8);
     
 // Functions that can go into devtab entries. These should not be
 // called directly, they are intended only for use by USB device
diff --git a/packages/io/usb/slave/current/src/usbs.c b/packages/io/usb/slave/current/src/usbs.c
--- a/packages/io/usb/slave/current/src/usbs.c
+++ b/packages/io/usb/slave/current/src/usbs.c
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2010 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -195,6 +195,28 @@ usbs_devtab_set_config(cyg_io_handle_t h
 // USB-specific functions that are useful for applications/packages which
 // do not want to use the devtab interface. These may get called in DSR
 // context.
+ 
+usbs_rx_endpoint* 
+usbs_get_rx_endpoint(usbs_control_endpoint* control_endpoint, 
+                                       cyg_uint8 endpoint_id)
+{
+    CYG_CHECK_DATA_PTR(control_endpoint, "A valid control endpoint must be supplied");
+    CYG_CHECK_FUNC_PTR(control_endpoint->get_rxep_fn, "Dynamic endpoint access not supported");
+    if (control_endpoint->state != USBS_STATE_CONFIGURED) 
+        return NULL;
+    return (*control_endpoint->get_rxep_fn)(control_endpoint, endpoint_id);
+}
+
+usbs_tx_endpoint* 
+usbs_get_tx_endpoint(usbs_control_endpoint* control_endpoint, 
+                                       cyg_uint8 endpoint_id)
+{
+    CYG_CHECK_DATA_PTR(control_endpoint, "A valid control endpoint must be supplied");
+    CYG_CHECK_FUNC_PTR(control_endpoint->get_txep_fn, "Dynamic endpoint access not supported");
+    if (control_endpoint->state != USBS_STATE_CONFIGURED) 
+        return NULL;
+    return (*control_endpoint->get_txep_fn)(control_endpoint, endpoint_id);
+}
 
 void
 usbs_start_rx(usbs_rx_endpoint* endpoint)
diff --git a/packages/isoinfra/current/ChangeLog b/packages/isoinfra/current/ChangeLog
--- a/packages/isoinfra/current/ChangeLog
+++ b/packages/isoinfra/current/ChangeLog
@@ -1,3 +1,13 @@
+2014-05-15  Andy Jackson  <andy@xylanta.com>
+
+	* include/sys/select.h: Make select FD_COPY and FD_ZERO macros single
+	statements. [ Bugzilla 1001986 ]
+
+2012-03-09  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* include/time.h: Add suseconds_t and useconds_t here for now.
+	* include/sys/time.h: Use suseconds_t when defining struct timeval.
+
 2009-06-03  Ross Younger  <wry@ecoscentric.com>
 
 	* include/sys/stat.h: Include cyg_type.h for __externC
@@ -433,7 +443,7 @@ 2000-05-02  Jonathan Larmour  <jlarmour@
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/isoinfra/current/include/sys/select.h b/packages/isoinfra/current/include/sys/select.h
--- a/packages/isoinfra/current/include/sys/select.h
+++ b/packages/isoinfra/current/include/sys/select.h
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2014 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -102,19 +102,17 @@ typedef	struct fd_set {
 #define	FD_CLR(__n, __p)   ((__p)->fds_bits[(__n)/__NFDBITS] &= ~(1 << ((__n) % __NFDBITS)))
 #define	FD_ISSET(__n, __p) ((__p)->fds_bits[(__n)/__NFDBITS] & (1 << ((__n) % __NFDBITS)))
 
-#define	FD_COPY(__f, __t)                                       \
-{                                                               \
+#define	FD_COPY(__f, __t) CYG_MACRO_START                       \
     unsigned int _i;                                            \
     for( _i = 0; _i < __howmany(FD_SETSIZE, __NFDBITS) ; _i++ ) \
         (__t)->fds_bits[_i] = (__f)->fds_bits[_i];              \
-}
+CYG_MACRO_END
 
-#define	FD_ZERO(__p)                                            \
-{                                                               \
+#define	FD_ZERO(__p) CYG_MACRO_START                            \
     unsigned int _i;                                            \
     for( _i = 0; _i < __howmany(FD_SETSIZE, __NFDBITS) ; _i++ ) \
         (__p)->fds_bits[_i] = 0;                                \
-}
+CYG_MACRO_END
 
 #   endif /* CYGONCE_ISO_SYS_SELECT_FD_SETS */
 
diff --git a/packages/isoinfra/current/include/sys/time.h b/packages/isoinfra/current/include/sys/time.h
--- a/packages/isoinfra/current/include/sys/time.h
+++ b/packages/isoinfra/current/include/sys/time.h
@@ -78,8 +78,8 @@
  * and used in other calls such as select(2).
  */
 struct timeval {
-	time_t	tv_sec;		/* seconds */
-	time_t	tv_usec;	/* and microseconds */
+       time_t      tv_sec;      /* seconds */
+       suseconds_t tv_usec;     /* and microseconds */
 };
 
 #endif
diff --git a/packages/isoinfra/current/include/time.h b/packages/isoinfra/current/include/time.h
--- a/packages/isoinfra/current/include/time.h
+++ b/packages/isoinfra/current/include/time.h
@@ -77,7 +77,16 @@
  * Epoch (00:00:00 GMT, 1970-01-01), but don't rely on this - always use
  * the type opaquely
  */
-typedef int time_t;
+typedef long time_t;
+
+/* Additional POSIX-derived types. Not the ideal place as these should
+ * also be defined in <sys/types.h>, along with time_t but that will
+ * require major upheaval to resolve these sorts of minor strict
+ * compliance issues properly.
+ */
+typedef long suseconds_t;
+typedef long useconds_t;
+
 # define __time_t_defined
 
 #endif
diff --git a/packages/kernel/current/ChangeLog b/packages/kernel/current/ChangeLog
--- a/packages/kernel/current/ChangeLog
+++ b/packages/kernel/current/ChangeLog
@@ -1,3 +1,72 @@
+2014-03-13  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* tests/tm_basic.c: Increase resolution of time measurement for platforms
+	featuring HAL_CLOCK_READ_NS. [Bugzilla 1001958]
+
+2013-06-13  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* tests/kintr0.c, tests/kcache1.c: Fix compiler warnings.
+
+2013-04-26  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* tests/fpint_thread_switch.c: Fix missing semicolon.
+	Bug spotted and patch provided by John Dallaway. [ Bugzilla 1001835 ]
+
+2013-02-10  Ilija Kocho  <ilijak@siva.com.mk>
+            Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/kernel.cdl:
+	* tests/fpinttestf.c, tests/fpinttestf1.c, tests/fpinttestf2.c,
+	* tests/fpint_thread_switch.c: Add single precision floating point tests.
+	[ Bugzilla 1001607 ]
+
+2012-10-04  Ilija Kocho <ilijak@siva.com.mk>
+
+	* tests/kcache2.c: Include CYGHWR_MEMORY_LAYOUT_H in order to
+	effectively test memory size. Bug reported and fix suggested by
+	Bernd Edlinger.                              [Bugzilla 1001650]
+
+2012-05-27  Ilija Kocho <ilijak@siva.com.mk>
+
+	* tests/kcache2.c: Allow comilation for targets with less then
+	128KiB RAM by conditionally reducing of MAXSIZE to (1<<16)
+
+
+2012-03-19  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+            Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* tests/except1.cxx (cause_exception): Fix compiler warning about
+	variable that is set but not used. Enter CYGBLD_ATTRIB_UNUSED.
+	* tests/kexcept1.c (cause_exception): Ditto.
+	* tests/kmbox1.c (entry1): Fix compiler warning about variable that
+	is set but not used. Use by a conditional CYGMTH_MBOX_PUT_CAN_WAIT.
+	* tests/mbox1.cxx (entry1): Ditto.
+	* tests/tm_basic.cxx (run_thread_tests, run_mbox_tests,
+	run_flag_tests): Remove unused variables.
+
+2012-03-06  Grant Edwards <grant.b.edwards@gmail.com>
+	
+	* src/intr/intr.cxx (attach): Fix compiler warning about unused
+	variable. [ Bugzilla 1001505 ]
+
+2011-07-09  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* tests/bin_sem2.cxx (PHILOSOPHERS):
+	* tests/fptest.cx (TEST_NA):
+	* tests/kmutex3.c (NTHREADS):
+	* tests/kmutex4.c (NTHREADS):
+	* tests/mutex3.cxx (NTHREADS):
+	* tests/thread_gdb.c (NTHREADS):
+	* tests/timeslice.c (NTHREADS_MAX):
+	* tests/timeslice2.c (NTHREADS_MAX):
+	* tests/tm_basic.cxx (NTEST_THREADS): Given a chance to compile and
+	run more tests for low memory footprint targets. [ Bugzilla 1001253 ]
+
+2010-11-22  Andrew Lunn  <andrew.lunn@ascom.ch>
+
+	* tests/intr0.cxx (intr0_main): Fix a compiler warning by changing
+	a CHECK() statement.
+
 2010-03-29  Lars Povlsen  <lpovlsen@vitesse.com>
 
 	* src/common/thread.cxx: Add volatile to idle_thread_loops for use with
diff --git a/packages/kernel/current/cdl/kernel.cdl b/packages/kernel/current/cdl/kernel.cdl
--- a/packages/kernel/current/cdl/kernel.cdl
+++ b/packages/kernel/current/cdl/kernel.cdl
@@ -151,14 +151,14 @@ cdl_package CYGPKG_KERNEL {
 
     # ---------------------------------------------------------------------
     # SMP support
-    
+
     cdl_component CYGPKG_KERNEL_SMP_SUPPORT {
 	display       "SMP support"
 	flavor        bool
 	requires      CYGPKG_HAL_SMP_SUPPORT
 	default_value 0
     }
-    
+
     # ---------------------------------------------------------------------
     cdl_component CYGPKG_KERNEL_COUNTERS {
         display       "Counters and clocks"
@@ -317,19 +317,32 @@ cdl_package CYGPKG_KERNEL {
                 the set of global flags if present."
         }
 
-        cdl_option CYGPKG_KERNEL_TESTS {
+        cdl_component CYGPKG_KERNEL_TESTS {
             display "Kernel tests"
             flavor  data
             no_define
-            calculated { 
-                "tests/bin_sem0 tests/bin_sem1 tests/bin_sem2 tests/bin_sem3 tests/clock0 tests/clock1 tests/clockcnv tests/clocktruth tests/cnt_sem0 tests/cnt_sem1 tests/except1 tests/flag0 tests/flag1 tests/intr0 tests/kill tests/mbox1 tests/mqueue1 tests/mutex0 tests/mutex1 tests/mutex2 tests/mutex3 tests/release tests/sched1 tests/sync2 tests/sync3 tests/thread0 tests/thread1 tests/thread2" 
-                . ((CYGFUN_KERNEL_API_C) ? " tests/kclock0 tests/kclock1 tests/kexcept1 tests/kflag0 tests/kflag1 tests/kintr0 tests/klock tests/kmbox1 tests/kmutex0 tests/kmutex1 tests/kmutex3 tests/kmutex4 tests/ksched1 tests/ksem0 tests/ksem1 tests/kthread0 tests/kthread1 tests/stress_threads tests/thread_gdb tests/timeslice tests/timeslice2 tests/tm_basic tests/fptest tests/kalarm0" : "")
+            calculated {
+                "tests/bin_sem0 tests/bin_sem1 tests/bin_sem2 tests/bin_sem3 tests/clock0 tests/clock1 tests/clockcnv tests/clocktruth tests/cnt_sem0 tests/cnt_sem1 tests/except1 tests/flag0 tests/flag1 tests/intr0 tests/kill tests/mbox1 tests/mqueue1 tests/mutex0 tests/mutex1 tests/mutex2 tests/mutex3 tests/release tests/sched1 tests/sync2 tests/sync3 tests/thread0 tests/thread1 tests/thread2"
+                . ((CYGFUN_KERNEL_API_C) ? " tests/kclock0 tests/kclock1 tests/kexcept1 tests/kflag0 tests/kflag1 tests/kintr0 tests/klock tests/kmbox1 tests/kmutex0 tests/kmutex1 tests/kmutex3 tests/kmutex4 tests/ksched1 tests/ksem0 tests/ksem1 tests/kthread0 tests/kthread1 tests/stress_threads tests/thread_gdb tests/timeslice tests/timeslice2 tests/tm_basic tests/kalarm0" : "")
                 . ((!CYGPKG_INFRA_DEBUG && !CYGPKG_KERNEL_INSTRUMENT && CYGFUN_KERNEL_API_C) ? " tests/dhrystone" : "")
                 . ((CYGPKG_KERNEL_SMP_SUPPORT && CYGFUN_KERNEL_API_C) ? " tests/smp" : "")
                 . ((!CYGINT_HAL_TESTS_NO_CACHES && CYGFUN_KERNEL_API_C) ? " tests/kcache1 tests/kcache2" : "")
+                . ((CYGFUN_KERNEL_API_C) ? (" tests/fpint_thread_switch" . (CYGTST_KERNEL_SKIP_MULTI_THREAD_FP_TEST ? " tests/fpinttestf1" :
+                   " tests/fptest tests/fpinttestf tests/fpinttestf2")) : "")
             }
             description   "
                 This option specifies the set of tests for the eCos kernel."
+
+            cdl_option CYGTST_KERNEL_SKIP_MULTI_THREAD_FP_TEST {
+                display       "Suppress multi thread floating point test"
+                flavor        bool
+                default_value 0
+                description "Hardware floating point configurations that do not
+                    preserve FPU context are supposed to fail multi thread FPU
+                    integrity tests. Setting this option to 1 shall suppress
+                    building of such tests and shall build single thread fpu
+                    integrity test instead."
+            }
         }
     }
 }
diff --git a/packages/kernel/current/src/intr/intr.cxx b/packages/kernel/current/src/intr/intr.cxx
--- a/packages/kernel/current/src/intr/intr.cxx
+++ b/packages/kernel/current/src/intr/intr.cxx
@@ -467,7 +467,7 @@ Cyg_Interrupt::attach(void)
 
     if( chain_list[index] == NULL )
     {
-        int in_use;
+        int in_use CYGBLD_ATTRIB_UNUSED;
         // First Interrupt on this chain, just assign it and register
         // the chain_isr with the HAL.
         
@@ -499,8 +499,7 @@ Cyg_Interrupt::attach(void)
 #else
     
     {
-        int in_use;
-
+        int in_use CYGBLD_ATTRIB_UNUSED;
 
         HAL_INTERRUPT_IN_USE( vector, in_use );
         CYG_ASSERT( 0 == in_use, "Interrupt vector not free.");
diff --git a/packages/kernel/current/tests/bin_sem2.cxx b/packages/kernel/current/tests/bin_sem2.cxx
--- a/packages/kernel/current/tests/bin_sem2.cxx
+++ b/packages/kernel/current/tests/bin_sem2.cxx
@@ -58,10 +58,19 @@
 #include <cyg/infra/testcase.h>
 
 #include <cyg/kernel/sched.inl>
+#include CYGHWR_MEMORY_LAYOUT_H
 
 static cyg_ucount16 PHILO_LOOPS = 1000;
 
-#define PHILOSOPHERS 15
+#if (CYGMEM_REGION_ram_SIZE <= 32768)
+# define PHILOSOPHERS 5
+#elif (CYGMEM_REGION_ram_SIZE <= 49152)
+# define PHILOSOPHERS 9
+#elif (CYGMEM_REGION_ram_SIZE <= 65536)
+# define PHILOSOPHERS 11
+#else
+# define PHILOSOPHERS 15
+#endif
 #define NTHREADS PHILOSOPHERS
 #include "testaux.hxx"
 
diff --git a/packages/kernel/current/tests/except1.cxx b/packages/kernel/current/tests/except1.cxx
--- a/packages/kernel/current/tests/except1.cxx
+++ b/packages/kernel/current/tests/except1.cxx
@@ -122,7 +122,7 @@ cause_fpe(int num)
 
 void cause_exception(void)
 {
-    int x;
+    int x CYGBLD_ATTRIB_UNUSED;
     unsigned int p=0;
 
     // First try for an address exception (unaligned access exception
diff --git a/packages/kernel/current/tests/fpint_thread_switch.cxx b/packages/kernel/current/tests/fpint_thread_switch.cxx
new file mode 100644
--- /dev/null
+++ b/packages/kernel/current/tests/fpint_thread_switch.cxx
@@ -0,0 +1,512 @@
+//==========================================================================
+//
+//        fpint_thread_switch.cxx
+//
+//        Thread switch delay measurement
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ilijak
+// Original code: gthomas (tm_basic.cxx from kernel tests)
+// Date:          2012-12-18
+// Description:   Switch delay measurement between threads that do/don't use
+//                floating point operations.
+//####DESCRIPTIONEND####
+
+#include <pkgconf/kernel.h>
+#include <pkgconf/hal.h>
+
+#include <cyg/kernel/sched.hxx>
+#include <cyg/kernel/thread.hxx>
+#include <cyg/kernel/thread.inl>
+#include <cyg/kernel/mutex.hxx>
+#include <cyg/kernel/sema.hxx>
+#include <cyg/kernel/flag.hxx>
+#include <cyg/kernel/sched.inl>
+#include <cyg/kernel/clock.hxx>
+#include <cyg/kernel/clock.inl>
+#include <cyg/kernel/kapi.h>
+
+#include <cyg/infra/testcase.h>
+#include <cyg/infra/diag.h>
+
+#include <cyg/kernel/test/stackmon.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+
+#ifndef HAL_CLOCK_READ_NS
+#define HAL_CLOCK_READ_NS(__pvalue) \
+CYG_MACRO_START                     \
+    HAL_CLOCK_READ(__pvalue);       \
+    *__pvalue *= 1000;              \
+CYG_MACRO_END
+#endif
+
+//==========================================================================
+// Random number generator. Ripped out of the C fptest.c.
+
+static int CYGBLD_ATTRIB_NO_INLINE rand( unsigned int *seed )
+{
+// This is the code supplied in Knuth Vol 2 section 3.6 p.185 bottom
+
+#define RAND_MAX 0x7fffffff
+#define MM 2147483647    // a Mersenne prime
+#define AA 48271         // this does well in the spectral test
+#define QQ 44488         // (long)(MM/AA)
+#define RR 3399          // MM % AA; it is important that RR<QQ
+
+    *seed = AA*(*seed % QQ) - RR*(unsigned int)(*seed/QQ);
+    if (*seed < 0)
+        *seed += MM;
+
+    return (int)( *seed & RAND_MAX );
+}
+
+// Define this to see the statistics with the first sample datum removed.
+// This can expose the effects of caches on the speed of operations.
+#undef STATS_WITHOUT_FIRST_SAMPLE
+#define STATS_WITHOUT_FIRST_SAMPLE 1
+
+#if defined(CYGFUN_KERNEL_API_C) &&             \
+    defined(CYGSEM_KERNEL_SCHED_MLQUEUE) &&     \
+    defined(CYGVAR_KERNEL_COUNTERS_CLOCK) &&    \
+    !defined(CYGDBG_INFRA_DIAG_USE_DEVICE) &&   \
+    (CYGNUM_KERNEL_SCHED_PRIORITIES > 12)
+
+#define NTHREADS 4
+#include "testaux.hxx"
+
+// Structure used to keep track of times
+typedef struct fun_times {
+    cyg_uint32 start;
+    cyg_uint32 end;
+} fun_times;
+
+#define STACK_SIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
+
+#define NTEST_THREADS    2
+
+#define NSAMPLES         2
+
+#define NTHREAD_SWITCHES 128
+#define NTHREAD_SWITCHES_TS 16
+
+#define NSAMPLES_SIM 2
+#define NTHREAD_SWITCHES_SIM 4
+#define NTHREAD_SWITCHES_TS_SIM 4
+
+static int nsamples;
+static int ntest_threads;
+static int nthread_switches;
+static int nthread_switches_ts;
+
+static char stacks[NTEST_THREADS][STACK_SIZE] CYGBLD_ATTRIB_ALIGN_MAX;
+static cyg_thread test_threads[NTEST_THREADS];
+static cyg_handle_t threads[NTEST_THREADS];
+static cyg_sem_t test_sem[NTEST_THREADS];
+static int overhead;
+static cyg_sem_t synchro;
+
+static fun_times test2_ft[4][NTHREAD_SWITCHES];
+
+
+static long rtc_resolution[] = CYGNUM_KERNEL_COUNTERS_RTC_RESOLUTION;
+static long ns_per_system_clock;
+
+void run_thread_switch_test(int);
+
+#ifndef min
+#define min(X,Y) ((X) < (Y) ? (X) : (Y))
+#endif
+
+
+
+// Wait until a clock tick [real time clock] has passed.  This should keep it
+// from happening again during a measurement, thus minimizing any fluctuations
+void
+wait_for_tick(void)
+{
+    cyg_tick_count_t tv0, tv1;
+    tv0 = cyg_current_time();
+    while (true) {
+        tv1 = cyg_current_time();
+        if (tv1 != tv0) break;
+    }
+}
+
+// Display a number of ticks as nanoseconds
+void
+show_ticks_in_ns(cyg_uint32 ticks)
+{
+    long long ns;
+    ns = (ns_per_system_clock * (long long)ticks) / CYGNUM_KERNEL_COUNTERS_RTC_PERIOD;
+    diag_printf("%8d", (int)(ns));
+}
+
+
+void
+show_times_hdr(void)
+{
+    diag_printf("\n");
+    diag_printf("                                 Confidence\n");
+    diag_printf("     Ave     Min     Max Max-Min  Ave  Min  Samp  Function\n");
+    diag_printf("  ======  ======  ======  ====== ==== ===== ===== ========\n");
+}
+
+void
+show_times_detail(fun_times ft[], int nsamples, char *title, bool ignore_first)
+{
+    int i, delta, min, max, con_ave, con_min, ave_dev;
+    int start_sample, total_samples;
+    cyg_int32 total, ave;
+
+    if (ignore_first) {
+        start_sample = 1;
+        total_samples = nsamples-1;
+    } else {
+        start_sample = 0;
+        total_samples = nsamples;
+    }
+    total = 0;
+    min = 0x7FFFFFFF;
+    max = 0;
+    for (i = start_sample;  i < nsamples;  i++) {
+        if (ft[i].end < ft[i].start) {
+            // Clock wrapped around (timer tick)
+            delta = (ft[i].end+CYGNUM_KERNEL_COUNTERS_RTC_PERIOD*1000) - ft[i].start;
+        } else {
+            delta = ft[i].end - ft[i].start;
+        }
+        delta -= overhead;
+        if (delta < 0) delta = 0;
+        total += delta;
+        if (delta < min) min = delta;
+        if (delta > max) max = delta;
+    }
+    ave = total / total_samples;
+    total = 0;
+    ave_dev = 0;
+    for (i = start_sample;  i < nsamples;  i++) {
+        if (ft[i].end < ft[i].start) {
+            // Clock wrapped around (timer tick)
+            delta = (ft[i].end+CYGNUM_KERNEL_COUNTERS_RTC_PERIOD*1000) - ft[i].start;
+        } else {
+            delta = ft[i].end - ft[i].start;
+        }
+        delta -= overhead;
+        if (delta < 0) delta = 0;
+        delta = delta - ave;
+        if (delta < 0) delta = -delta;
+        ave_dev += delta;
+    }
+    ave_dev /= total_samples;
+    con_ave = 0;
+    con_min = 0;
+    for (i = start_sample;  i < nsamples;  i++) {
+        if (ft[i].end < ft[i].start) {
+            // Clock wrapped around (timer tick)
+            delta = (ft[i].end+CYGNUM_KERNEL_COUNTERS_RTC_PERIOD*1000) - ft[i].start;
+        } else {
+            delta = ft[i].end - ft[i].start;
+        }
+        delta -= overhead;
+        if (delta < 0) delta = 0;
+        if ((delta <= (ave+ave_dev)) && (delta >= (ave-ave_dev))) con_ave++;
+        if ((delta <= (min+ave_dev)) && (delta >= (min-ave_dev))) con_min++;
+    }
+    con_ave = (con_ave * 100) / total_samples;
+    con_min = (con_min * 100) / total_samples;
+    show_ticks_in_ns(ave);
+    show_ticks_in_ns(min);
+    show_ticks_in_ns(max);
+    show_ticks_in_ns(max-min);
+    diag_printf("  %3d%% %3d%%", con_ave, con_min);
+    diag_printf("  %4d", total_samples);
+    diag_printf(" %s\n", title);
+}
+
+void
+show_times(fun_times ft[], int nsamples, char *title)
+{
+#ifndef STATS_WITHOUT_FIRST_SAMPLE
+    show_times_detail(ft, nsamples, title, false);
+#else// STATS_WITHOUT_FIRST_SAMPLE
+    show_times_detail(ft, nsamples, title, true);
+#endif
+}
+
+void
+show_test_parameters(void)
+{
+    diag_printf("\nTesting parameters:\n");
+    diag_printf("   Thread switches:            %5d\n", nthread_switches);
+    diag_printf("   Time unit:         nanoseconds [ns]\n");
+}
+
+void
+end_of_test_group(void)
+{
+    diag_printf("\n");
+}
+
+// Compute a name for a thread
+char *
+thread_name(char *basename, int indx) {
+    return "<<NULL>>";  // Not currently used
+}
+
+// test0 - null test, never executed
+void
+test0(cyg_uint32 indx)
+{
+#ifndef CYGPKG_KERNEL_SMP_SUPPORT
+    // In SMP, somw of these threads will execute
+    diag_printf("test0.%d executed?\n", indx);
+#endif
+    cyg_thread_exit();
+}
+
+// test1 - empty test, simply exit.  Last thread signals parent.
+void
+test1(cyg_uint32 indx)
+{
+    if (indx == (cyg_uint32)(ntest_threads-1)) {
+        cyg_semaphore_post(&synchro);  // Signal that last thread is dying
+    }
+    cyg_thread_exit();
+}
+
+char title[128];
+char* thread_title[2];
+
+volatile int ires __attribute__((unused));
+
+// This thread does not use floating point
+void
+thread_int(cyg_uint32 indx_fp)
+{
+    int i;
+    int fp_i, indx;
+    unsigned int seed;
+    int iop1, iop2;
+
+    fp_i = indx_fp & 0x3;
+    indx = (indx_fp & 0x4) >> 2;
+    thread_title[indx] = "int";
+
+    // Just for symmetry with thread_fp.
+    seed = indx_fp;
+    iop1 = rand(&seed);
+    iop2 = rand(&seed);
+    ires = iop1 + iop2;
+    cyg_semaphore_wait(&test_sem[indx]);
+
+    for (i = 0;  i < nthread_switches;  i++) {
+        ires = iop1 + iop2;
+        if (indx == 0) {
+            HAL_CLOCK_READ_NS(&test2_ft[fp_i][i].start);
+        } else {
+            HAL_CLOCK_READ_NS(&test2_ft[fp_i][i].end);
+        }
+        cyg_thread_yield();
+    }
+    if (indx) {
+        cyg_semaphore_post(&synchro);
+    }
+    cyg_thread_exit();
+}
+
+volatile float fres __attribute__((unused));
+
+// This thread does use floating point
+void
+thread_fp(cyg_uint32 indx_fp)
+{
+    int i;
+    int fp_i, indx;
+    unsigned int seed;
+    float fop1, fop2;
+
+    fp_i = indx_fp & 0x3;
+    indx = (indx_fp & 0x4) >> 2;
+    thread_title[indx] = "fpu";
+
+    // In LAZY mode we need some FP usage to enforce
+    // FPU context saving.
+    seed = indx_fp;
+    fop1 = (float)rand(&seed) / (float)0x7fffffff;
+    fop2 = (float)rand(&seed) / (float)0x7fffffff;
+    fres = fop1 + fop2;
+    cyg_semaphore_wait(&test_sem[indx]);
+
+    for (i = 0;  i < nthread_switches;  i++) {
+        fres = fop1 + fop2;
+        if (indx == 0) {
+            HAL_CLOCK_READ_NS(&test2_ft[fp_i][i].start);
+        } else {
+            HAL_CLOCK_READ_NS(&test2_ft[fp_i][i].end);
+        }
+        cyg_thread_yield();
+    }
+    if (indx) {
+        cyg_semaphore_post(&synchro);
+    }
+    cyg_thread_exit();
+}
+
+void
+run_tests(CYG_ADDRESS id)
+{
+    int tst_i;
+
+    ns_per_system_clock = 1000000/rtc_resolution[1];
+
+    diag_printf("Thread switch test\n");
+    show_test_parameters();
+    // Set my priority lower than any I plan to create
+    cyg_thread_set_priority(cyg_thread_self(), 3);
+
+    // Set up the end-of-threads synchronizer
+    cyg_semaphore_init(&synchro, 0);
+    show_times_hdr();
+#if CYGNUM_TESTS_RUN_COUNT < 0
+    while (1)
+#else
+    int i;
+    for (i = 0;  i < CYGNUM_TESTS_RUN_COUNT;  i++)
+#endif
+        for(tst_i = 0; tst_i < 4; tst_i ++){
+            run_thread_switch_test(tst_i);
+        }
+    CYG_TEST_PASS_FINISH("Thread switching OK");
+}
+
+
+void
+run_thread_switch_test(int fp_i)
+{
+    int i;
+    cyg_thread_entry_t* thr_ent[2];
+
+    for (i = 0;  i < 2;  i++) {
+        cyg_semaphore_init(&test_sem[i], 0);
+    }
+    // Set up for thread context switch
+    thr_ent[0] = !(fp_i & 0x2) ? thread_int : thread_fp;
+    thr_ent[1] = !(fp_i & 0x1) ? thread_int : thread_fp;
+
+    for (i = 0;  i < 2;  i++) {
+        cyg_thread_create(10,         // Priority - just a number
+                thr_ent[i],           // entry
+                (i << 2) | fp_i,      // index
+                thread_name("thread", i),     // Name
+                &stacks[i][0],   // Stack
+                STACK_SIZE,      // Size
+                &threads[i],     // Handle
+                &test_threads[i] // Thread data structure
+            );
+    }
+    for (i = 0;  i < 2;  i++) {
+        cyg_thread_resume(threads[i]);
+    }
+    cyg_thread_delay(2);
+    wait_for_tick(); // Wait until the next clock tick to minimize aberations
+    for (i = 0;  i < 2;  i++) {
+        cyg_semaphore_post(&test_sem[i]);
+    }
+    cyg_semaphore_wait(&synchro);
+    __builtin_strcpy(title, "Thread switch: ");
+    __builtin_strcat(title, thread_title[0]);
+    __builtin_strcat(title,"-");
+    __builtin_strcat(title, thread_title[1]);
+    show_times(test2_ft[fp_i], nthread_switches, title);
+    // Clean up
+    for (i = 0;  i < 2;  i++) {
+        cyg_thread_delete(threads[i]);
+    }
+}
+
+void thread_switch_main( void )
+{
+    CYG_TEST_INIT();
+
+    if (cyg_test_is_simulator) {
+        nsamples = NSAMPLES_SIM;
+        nthread_switches = NTHREAD_SWITCHES_SIM;
+        nthread_switches_ts = NTHREAD_SWITCHES_TS_SIM;
+    } else {
+        nsamples = NSAMPLES;
+        nthread_switches = NTHREAD_SWITCHES;
+        nthread_switches_ts = NTHREAD_SWITCHES_TS;
+    }
+
+    new_thread(run_tests, 0);
+
+    Cyg_Scheduler::scheduler.start();
+
+}
+
+#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
+externC void
+cyg_hal_invoke_constructors();
+#endif
+
+externC void
+cyg_start( void )
+{
+#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
+    cyg_hal_invoke_constructors();
+#endif
+    thread_switch_main();
+}
+
+#else // CYGFUN_KERNEL_API_C
+
+externC void
+cyg_start( void )
+{
+    CYG_TEST_INIT();
+    CYG_TEST_INFO("Timing tests require:\n"
+                "CYGFUN_KERNEL_API_C && \n"
+                "CYGSEM_KERNEL_SCHED_MLQUEUE &&\n"
+                "CYGVAR_KERNEL_COUNTERS_CLOCK &&\n"
+                "!CYGDBG_INFRA_DIAG_USE_DEVICE &&\n"
+                "(CYGNUM_KERNEL_SCHED_PRIORITIES > 12)\n");
+    CYG_TEST_NA("Timing tests requirements");
+}
+#endif // CYGFUN_KERNEL_API_C, etc.
+
+// EOF fpint_thread_switch.cxx
diff --git a/packages/kernel/current/tests/fpinttestf.c b/packages/kernel/current/tests/fpinttestf.c
new file mode 100644
--- /dev/null
+++ b/packages/kernel/current/tests/fpinttestf.c
@@ -0,0 +1,588 @@
+//==========================================================================
+//
+//        fpinttestf.c
+//
+//        Basic FPU integrity test
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ilijak
+// Original code: nickg@calivar.com
+// Contributors:
+// Date:          2012-12-18
+// Description:   Simple FPU test with a mix of threads that do and do not use
+//                floating point.
+//                This is a modification of the original FPU test, and presents
+//                both "integer" and "float" threads in order to enforce LAZY
+//                context switching. Single precision floating point is used.
+//                This is not very sophisticated as far
+//                as checking FPU performance or accuracy. It is more
+//                concerned with checking that several threads doing FP
+//                operations do not interfere with eachother's use of the
+//                FPU.
+//                Note: NONE context switching scheme should NOT pass this test with
+//                      multiple FP threads. Look for fpinttestf1.c instead.
+//
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#include <pkgconf/kernel.h>
+#include <pkgconf/hal.h>
+
+#include <cyg/hal/hal_arch.h>
+
+#include <cyg/kernel/kapi.h>
+
+#include <cyg/infra/testcase.h>
+#include <cyg/infra/diag.h>
+
+#include <cyg/kernel/test/stackmon.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//==========================================================================
+
+#ifndef FP_THREADS_N
+#define FP_THREADS_N 3
+#define FP_TEST_NAME "FP test"
+#endif
+
+#if defined(CYGFUN_KERNEL_API_C) &&                                    \
+    defined(CYGSEM_KERNEL_SCHED_MLQUEUE) &&                            \
+    (CYGNUM_KERNEL_SCHED_PRIORITIES > 12) &&                           \
+    (CYGMEM_REGION_ram_SIZE >= (49152-4096)) &&                        \
+    (!defined(CYGTST_KERNEL_SKIP_MULTI_THREAD_FP_TEST) || (FP_THREADS_N == 1))
+
+//==========================================================================
+// Base priority for all threads.
+
+#define BASE_PRI        5
+
+//==========================================================================
+// Runtime
+//
+// This is the number of ticks that the program will run for. 3000
+// ticks is equal to 30 seconds in the default configuration. For
+// simulators we reduce the run time to 3 simulated seconds.
+
+#define RUN_TICKS       3000
+#define RUN_TICKS_SIM   300
+
+//==========================================================================
+// Thread parameters
+
+#define STACK_SIZE CYGNUM_HAL_STACK_SIZE_MINIMUM
+#define THREADS_N 8
+static cyg_uint8 stacks[THREADS_N][STACK_SIZE] CYGBLD_ATTRIB_ALIGN_MAX;
+static cyg_handle_t thread[THREADS_N];
+static cyg_thread thread_struct[THREADS_N];
+static unsigned long iter_n[THREADS_N];
+
+//==========================================================================
+// Alarm parameters.
+
+static cyg_alarm alarm_struct;
+static cyg_handle_t alarm;
+
+static cyg_count8 cur_thread = 0;
+static cyg_count32 alarm_ticks = 0;
+static cyg_count32 run_ticks = RUN_TICKS;
+
+//==========================================================================
+
+static int errors = 0;
+
+//==========================================================================
+// Random number generator. Ripped out of the C library.
+
+static int CYGBLD_ATTRIB_NO_INLINE rand( unsigned int *seed )
+{
+// This is the code supplied in Knuth Vol 2 section 3.6 p.185 bottom
+
+#define RAND_MAX 0x7fffffff
+#define MM 2147483647    // a Mersenne prime
+#define AA 48271         // this does well in the spectral test
+#define QQ 44488         // (long)(MM/AA)
+#define RR 3399          // MM % AA; it is important that RR<QQ
+
+    *seed = AA*(*seed % QQ) - RR*(unsigned int)(*seed/QQ);
+    if (*seed < 0)
+        *seed += MM;
+
+    return (int)( *seed & RAND_MAX );
+}
+
+
+//==========================================================================
+// Test calculation.
+//
+// Generates an array of random FP values and then repeatedly applies
+// a calculation to them and checks that the same result is reached
+// each time. The calculation, in the macro CALC, is intended to make
+// maximum use of the FPU registers. However, the i386 compiler
+// doesn't let this expression get very complex before it starts
+// spilling values out to memory.
+
+static void do_test( float *values,
+                     int count,
+                     int loops,
+                     int test,
+                     const char *name)
+{
+    unsigned int i, j;
+    // volatiles necessary to force
+    // values to 32 bits for comparison
+    volatile float sum = 1.0;
+    volatile float last_sum;
+    unsigned int seed;
+
+    cyg_uint32 iter = 0;
+    int thread_i = name[__builtin_strlen(name)-1]-'1';
+
+#define V(__i) (values[(__i)%count])
+#define CALC ((V(i-1)*V(i+1))*(V(i-2)*V(i+2))*(V(i-3)*sum))
+
+    seed = ((unsigned int)&i)*count;
+
+    // Set up an array of values...
+    for( i = 0; i < count; i++ )
+        values[i] = (float)rand( &seed )/(float)0x7fffffff;
+
+    // Now calculate something from them...
+    for( i = 0; i < count; i++ )
+        sum += CALC;
+
+    last_sum = sum;
+
+    // Now recalculate the sum in a loop and look for errors
+    for( j = 0; j < loops ; j++ )
+    {
+        iter++;
+        if(thread_i < 3)
+            iter_n[thread_i]++;
+        sum = 1.0;
+        for( i = 0; i < count; i++ )
+            sum += CALC;
+
+        if( sum != last_sum )
+        {
+            union float_int_union {
+                float d;
+                cyg_uint32 i;
+            } diu_sum, diu_lastsum;
+
+            diu_sum.d = sum;
+            diu_lastsum.d = last_sum;
+
+            errors++;
+            if (sizeof(float) != sizeof(cyg_uint32)) {
+                diag_printf("Warning: sizeof(float) != sizeof(cyg_uint32), therefore next line may\n"
+                            "have invalid sum/last_sum values\n");
+            }
+            diag_printf("%s: Sum mismatch! %d sum=[%08x] last_sum=[%08x]\n",
+                        name,j, diu_sum.i, diu_lastsum.i );
+
+        }
+#if 0
+        if( ((j*count)%1000000) == 0 )
+            diag_printf("INFO:<%s: %2d calculations done>\n",name,j*count);
+#endif
+    }
+#if 0
+    if(thread_i < 3)
+        diag_printf("INFO:<%s [%d]: %2d calculations done>\n",name,thread_i,j*count);
+#endif
+    if(thread_i < 3)
+        iter_n[thread_i] = iter;
+}
+
+
+//==========================================================================
+// Test calculation.
+//
+// Generates an array of random integer values and then repeatedly applies
+// a calculation to them and checks that the same result is reached
+// each time.
+
+static void do_int_test( int *values,
+                     int count,
+                     int loops,
+                     int test,
+                     const char *name)
+{
+    unsigned int i, j;
+    // volatiles necessary to force
+    // values to 32 bits for comparison
+    volatile int sum = 1;
+    volatile int last_sum;
+    unsigned int seed;
+#if 0
+    cyg_uint32 ctrlreg;
+#endif
+    cyg_uint32 iter = 0;
+    int thread_i = name[__builtin_strlen(name)-1]-'1';
+
+#define VI(__i) (values[(__i)%count])
+#define CALCI ((VI(i-1)*VI(i+1))*(VI(i-2)*VI(i+2))*(VI(i-3)*sum))
+
+    seed = ((unsigned int)&i)*count;
+
+    // Set up an array of values...
+    for( i = 0; i < count; i++ )
+        values[i] = rand( &seed );
+
+    // Now calculate something from them...
+    for( i = 0; i < count; i++ )
+        sum += CALC;
+
+    last_sum = sum;
+
+    // Now recalculate the sum in a loop and look for errors
+    for( j = 0; j < loops ; j++ )
+    {
+        iter++;
+        if(thread_i < 8)
+            iter_n[thread_i]++;
+        sum = 1;
+        for( i = 0; i < count; i++ )
+            sum += CALC;
+
+        if( sum != last_sum )
+        {
+            errors++;
+            diag_printf("%s: Sum mismatch! %d sum=[%08x] last_sum=[%08x]\n",
+                        name,j, sum, last_sum );
+        }
+#if 0
+        CYGARC_MRS(ctrlreg, control);
+        if(ctrlreg & 0x04){
+            diag_printf("%s: control = 0x%08x\n", name, ctrlreg);
+        }
+#endif
+#if 0
+        if( ((j*count)%1000000) == 0 )
+            diag_printf("INFO:<%s: %2d calculations done>\n",name,j*count);
+#endif
+    }
+}
+
+//==========================================================================
+// Alarm handler
+//
+// This is called every tick. It lowers the priority of the currently
+// running thread and raises the priority of the next. Thus we
+// implement a form of timelslicing between the threads at one tick
+// granularity.
+
+static void alarm_fn(cyg_handle_t alarm, cyg_addrword_t data)
+{
+    alarm_ticks++;
+    unsigned long iter_sum;
+
+    if( alarm_ticks >= run_ticks )
+    {
+        if( errors )
+            CYG_TEST_FAIL("Errors detected");
+        else
+            CYG_TEST_PASS("OK");
+
+        iter_sum = + iter_n[0] + iter_n[1] + iter_n[2] + iter_n[3]+ iter_n[4] + iter_n[5]+ iter_n[6] + iter_n[7];
+        diag_printf("Iterations = %lu+%lu+%lu+%lu+%lu+%lu+%lu+%lu",
+                iter_n[0], iter_n[1], iter_n[2], iter_n[3], iter_n[4], iter_n[5], iter_n[6], iter_n[7]);
+        diag_printf("=%lu\n", iter_sum);
+        CYG_TEST_FINISH("FP Test done");
+    }
+    else
+    {
+        cyg_thread_set_priority( thread[cur_thread], BASE_PRI );
+
+        cur_thread = (cur_thread+1)%8;
+
+        cyg_thread_set_priority( thread[cur_thread], BASE_PRI-1 );
+    }
+}
+
+
+//==========================================================================
+// Floating point threads
+//
+#define FP1_COUNT 1000
+
+static float fpt1_values[FP1_COUNT];
+
+void fptest1( CYG_ADDRWORD id )
+{
+    while(1)
+        do_test( fpt1_values, FP1_COUNT, 2000000000, id, "fptest1" );
+}
+
+//==========================================================================
+#if (CYGMEM_REGION_ram_SIZE / 8 / 2) < 10000
+#define FP2_COUNT (CYGMEM_REGION_ram_SIZE / 8 / 2)
+#else
+#define FP2_COUNT 10000
+#endif
+
+static float fpt2_values[FP2_COUNT];
+
+void fptest2( CYG_ADDRWORD id )
+{
+    while(1)
+        do_test( fpt2_values, FP2_COUNT, 2000000000, id, "fptest2" );
+}
+
+//==========================================================================
+
+#define FP3_COUNT 100
+
+static float fpt3_values[FP3_COUNT];
+
+void fptest3( CYG_ADDRWORD id )
+{
+    while(1)
+        do_test( fpt3_values, FP3_COUNT, 2000000000, id, "fptest3" );
+}
+
+//==========================================================================
+// Integral threads
+//
+
+#define INT1_COUNT 1000
+
+static int int1_values[INT1_COUNT];
+
+void inttest4( CYG_ADDRWORD id )
+{
+    while(1)
+        do_int_test( int1_values, INT1_COUNT, 2000000000, id, "inttest4" );
+}
+
+#define INT2_COUNT 1000
+
+static int int2_values[INT2_COUNT];
+
+void inttest5( CYG_ADDRWORD id )
+{
+    while(1)
+        do_int_test( int2_values, INT2_COUNT, 2000000000, id, "inttest5" );
+}
+
+#define INT3_COUNT 1000
+
+static int int3_values[INT3_COUNT];
+
+void inttest6( CYG_ADDRWORD id )
+{
+    while(1)
+        do_int_test( int3_values, INT3_COUNT, 2000000000, id, "inttest6" );
+}
+
+
+#define INT4_COUNT 1000
+
+static int int4_values[INT4_COUNT];
+
+void inttest7( CYG_ADDRWORD id )
+{
+    while(1)
+        do_int_test( int4_values, INT4_COUNT, 2000000000, id, "inttest7" );
+}
+
+#define INT5_COUNT 1000
+
+static int int5_values[INT5_COUNT];
+
+void inttest8( CYG_ADDRWORD id )
+{
+    while(1)
+        do_int_test( int5_values, INT5_COUNT, 2000000000, id, "inttest8" );
+}
+
+//======================================================================================
+// Main
+
+void fptest_main( void )
+{
+    CYG_TEST_INIT();
+
+    if( cyg_test_is_simulator )
+    {
+        run_ticks = RUN_TICKS_SIM;
+    }
+    CYG_TEST_INFO("Run fptest in cyg_start");
+    do_test( fpt3_values, FP3_COUNT, 1000, 0, "start" );
+    CYG_TEST_INFO( "cyg_start run done");
+
+    cyg_thread_create( BASE_PRI-1,
+                       fptest1,
+                       0,
+                       "fptest1",
+                       &stacks[0][0],
+                       STACK_SIZE,
+                       &thread[0],
+                       &thread_struct[0]);
+#if FP_THREADS_N > 0
+    cyg_thread_resume( thread[0] );
+#endif
+    cyg_thread_create( BASE_PRI,
+                       fptest2,
+                       1,
+                       "fptest2",
+                       &stacks[1][0],
+                       STACK_SIZE,
+                       &thread[1],
+                       &thread_struct[1]);
+
+#if FP_THREADS_N > 1
+    cyg_thread_resume( thread[1] );
+#endif
+    cyg_thread_create( BASE_PRI,
+                       fptest3,
+                       2,
+                       "fptest3",
+                       &stacks[2][0],
+                       STACK_SIZE,
+                       &thread[2],
+                       &thread_struct[2]);
+
+#if FP_THREADS_N > 2
+    cyg_thread_resume( thread[2] );
+#endif
+
+    cyg_thread_create( BASE_PRI,
+                       inttest4,
+                       3,
+                       "inttest4",
+                       &stacks[3][0],
+                       STACK_SIZE,
+                       &thread[3],
+                       &thread_struct[3]);
+
+    cyg_thread_resume( thread[3] );
+
+    cyg_thread_create( BASE_PRI,
+                       inttest5,
+                       4,
+                       "inttest5",
+                       &stacks[4][0],
+                       STACK_SIZE,
+                       &thread[4],
+                       &thread_struct[4]);
+
+    cyg_thread_resume( thread[4] );
+
+    cyg_thread_create( BASE_PRI,
+                       inttest6,
+                       5,
+                       "inttest6",
+                       &stacks[5][0],
+                       STACK_SIZE,
+                       &thread[5],
+                       &thread_struct[5]);
+
+    cyg_thread_resume( thread[5] );
+
+    cyg_thread_create( BASE_PRI,
+                       inttest7,
+                       6,
+                       "inttest7",
+                       &stacks[6][0],
+                       STACK_SIZE,
+                       &thread[6],
+                       &thread_struct[6]);
+
+    cyg_thread_resume( thread[6] );
+
+    cyg_thread_create( BASE_PRI,
+                       inttest8,
+                       7,
+                       "inttest8",
+                       &stacks[7][0],
+                       STACK_SIZE,
+                       &thread[7],
+                       &thread_struct[7]);
+
+    cyg_thread_resume( thread[7] );
+
+    cyg_alarm_create( cyg_real_time_clock(),
+                      alarm_fn,
+                      0,
+                      &alarm,
+                      &alarm_struct );
+
+    cyg_alarm_initialize( alarm, cyg_current_time()+1, 1 );
+
+    cyg_scheduler_start();
+
+}
+
+//==========================================================================
+
+#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
+externC void
+cyg_hal_invoke_constructors();
+#endif
+
+externC void
+cyg_start( void )
+{
+#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
+    cyg_hal_invoke_constructors();
+#endif
+    fptest_main();
+}
+
+//==========================================================================
+
+#else // CYGFUN_KERNEL_API_C...
+
+externC void
+cyg_start( void )
+{
+    CYG_TEST_INIT();
+    CYG_TEST_INFO(FP_TEST_NAME " requires:\n"
+                "CYGFUN_KERNEL_API_C && \n"
+                "CYGSEM_KERNEL_SCHED_MLQUEUE && \n"
+                "(CYGNUM_KERNEL_SCHED_PRIORITIES > 12) &&\n"
+                "(CYGMEM_REGION_ram_SIZE >= (49152-4096)) &&\n"
+                "(!defined(CYGHWR_HAL_CORTEXM_FPU_SWITCH_NONE) || (FP_THREADS_N == 1))"
+                );
+    CYG_TEST_NA("FP test requirements");
+}
+
+#endif // CYGFUN_KERNEL_API_C, etc.
+
+//==========================================================================
+// EOF fpinttestf.c
diff --git a/packages/kernel/current/tests/fpinttestf1.c b/packages/kernel/current/tests/fpinttestf1.c
new file mode 100644
--- /dev/null
+++ b/packages/kernel/current/tests/fpinttestf1.c
@@ -0,0 +1,58 @@
+//==========================================================================
+//
+//        fpinttestf1.cxx
+//
+//        Basic FPU integrity test for NONE context switching scheme
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012, 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ilijak
+// Contributors:
+// Date:          2012-12-18
+// Description:   Simple FPU test with a mix of threads that do and do not use
+//                floating point.
+//                This is a special case of fpinttestf.c with single FP thread.
+//
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#define FP_THREADS_N 1
+#define FP_TEST_NAME "FP test for switching scheme NONE"
+
+#include "fpinttestf.c"
+
+//==========================================================================
+// EOF fpinttestf1.c
diff --git a/packages/kernel/current/tests/fpinttestf2.c b/packages/kernel/current/tests/fpinttestf2.c
new file mode 100644
--- /dev/null
+++ b/packages/kernel/current/tests/fpinttestf2.c
@@ -0,0 +1,400 @@
+//==========================================================================
+//
+//        fpinttestf2.c
+//
+//        Basic FPU integrity test
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ilijak
+// Original code: nickg@calivar.com
+// Contributors:
+// Date:          2012-12-18
+// Description:   Simple FPU test with a mix of threads that do and do not use
+//                floating point.
+//                This is a modification of the original FPU test, and presents
+//                both "integer" and "float" threads in order to enforce LAZY
+//                context switching. Single precision floating point is used.
+//                This is not very sophisticated as far
+//                as checking FPU performance or accuracy. It is more
+//                concerned with checking that several threads doing FP
+//                operations do not interfere with eachother's use of the
+//                FPU.
+//
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#include <pkgconf/kernel.h>
+#include <pkgconf/hal.h>
+
+#include <cyg/hal/hal_arch.h>
+
+#include <cyg/kernel/kapi.h>
+
+#include <cyg/infra/testcase.h>
+#include <cyg/infra/diag.h>
+
+#include <cyg/kernel/test/stackmon.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//==========================================================================
+
+#if defined(CYGFUN_KERNEL_API_C) &&               \
+    defined(CYGSEM_KERNEL_SCHED_MLQUEUE) &&       \
+    (CYGNUM_KERNEL_SCHED_PRIORITIES > 12) &&      \
+    (CYGMEM_REGION_ram_SIZE >= (49152-4096)) &&   \
+    (!defined(CYGHWR_HAL_CORTEXM_FPU_SWITCH_NONE))
+
+
+//==========================================================================
+// Base priority for all threads.
+
+#define BASE_PRI        5
+
+//==========================================================================
+// Runtime
+//
+// This is the number of ticks that the program will run for. 3000
+// ticks is equal to 30 seconds in the default configuration. For
+// simulators we reduce the run time to 3 simulated seconds.
+
+#define RUN_TICKS       3000
+#define RUN_TICKS_SIM   300
+
+//==========================================================================
+// Thread parameters
+
+#define STACK_SIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
+#define THREADS_N 2
+static cyg_uint8 stacks[THREADS_N][STACK_SIZE] CYGBLD_ATTRIB_ALIGN_MAX;
+static cyg_handle_t thread[THREADS_N];
+static cyg_thread thread_struct[THREADS_N];
+static unsigned long iter_n[THREADS_N];
+
+//==========================================================================
+// Alarm parameters.
+
+static cyg_alarm alarm_struct;
+static cyg_handle_t alarm;
+
+volatile static cyg_count32 alarm_ticks = 0;
+static cyg_count32 run_ticks = RUN_TICKS;
+
+//==========================================================================
+
+static int errors = 0;
+
+//==========================================================================
+// Random number generator. Ripped out of the C library.
+
+static int CYGBLD_ATTRIB_NO_INLINE rand( unsigned int *seed )
+{
+// This is the code supplied in Knuth Vol 2 section 3.6 p.185 bottom
+
+#define RAND_MAX 0x7fffffff
+#define MM 2147483647    // a Mersenne prime
+#define AA 48271         // this does well in the spectral test
+#define QQ 44488         // (long)(MM/AA)
+#define RR 3399          // MM % AA; it is important that RR<QQ
+
+    *seed = AA*(*seed % QQ) - RR*(unsigned int)(*seed/QQ);
+    if (*seed < 0)
+        *seed += MM;
+
+    return (int)( *seed & RAND_MAX );
+}
+
+
+//==========================================================================
+// Test calculation.
+// Generates an array of random FP values and then thread repeatedly
+// alternates following cases:
+//    - Floatin point calculation occur before it yields;
+//    - No floating point instructions occur before it yields;
+// In addition the re-calculation is called either directly or by means of
+// proxy in order to enforce context stacking in different stack locations
+// Floating point calculation checks whether the same result is reached
+// on every repetition.
+// 
+
+
+#define V(__i) (values[(__i)%count])
+#define CALC ((V(i-1)*V(i+1))*(V(i-2)*V(i+2))*(V(i-3)*sum))
+
+volatile unsigned int fint;
+
+void  CYGBLD_ATTRIB_NO_INLINE
+recalc (float *values, float last_sum, cyg_uint32 iter, int thread_i,
+                    int count, const char *name, unsigned int loop_i)
+{
+    volatile float sum = 1.0;
+    unsigned int i;
+    
+    iter++;
+    if(thread_i < 3)
+        iter_n[thread_i]++;
+    sum = 1.0;
+    for( i = 0; i < count; i++ )
+        sum += CALC;
+    
+    if( sum != last_sum )
+    {
+        union float_int_union {
+            float d;
+            cyg_uint32 i;
+        } diu_sum, diu_lastsum;
+        
+        diu_sum.d = sum;
+        diu_lastsum.d = last_sum;
+        
+        errors++;
+        if (sizeof(float) != sizeof(cyg_uint32)) {
+            diag_printf("Warning: sizeof(float) != sizeof(cyg_uint32), therefore next line may\n"
+                        "have invalid sum/last_sum values\n");
+        }
+        diag_printf("%s: Sum mismatch! %d sum=[%08x] last_sum=[%08x]\n",
+                    name, loop_i, diu_sum.i, diu_lastsum.i );
+        
+    }
+}
+
+void CYGBLD_ATTRIB_NO_INLINE
+recalc_proxy (float *values, float last_sum, cyg_uint32 iter, int thread_i,
+                                        int count, const char *name, unsigned int loop_i)
+{
+    int ticks;
+    
+    ticks = alarm_ticks;
+    while(ticks == alarm_ticks)
+        CYG_EMPTY_STATEMENT;
+    cyg_thread_yield();
+    ticks = alarm_ticks;
+    while(ticks == alarm_ticks);
+        CYG_EMPTY_STATEMENT;
+    cyg_thread_yield();
+    recalc(values, last_sum, iter, thread_i, count, name, loop_i);
+    cyg_thread_yield();
+    ticks = alarm_ticks;
+    while(ticks == alarm_ticks);    
+        CYG_EMPTY_STATEMENT;
+}
+
+
+static void do_test1( float *values,
+                     int count,
+                     int loops,
+                     int test,
+                     const char *name)
+{
+    unsigned int i, j;
+    // volatiles necessary to force
+    // values to 32 bits for comparison
+    volatile float sum = 1.0;
+    volatile float last_sum;
+    unsigned int seed;
+
+    cyg_uint32 iter = 0;
+    int thread_i = name[__builtin_strlen(name)-1]-'1';
+
+    seed = ((unsigned int)&i)*count;
+
+    // Set up an array of values...
+    for( i = 0; i < count; i++ )
+        values[i] = (float)rand( &seed )/(float)0x7fffffff;
+
+    // Now calculate something from them...
+    for( i = 0; i < count; i++ )
+        sum += CALC;
+
+    last_sum = sum;
+
+    // Now recalculate the sum in a loop and look for errors
+    for( j = 0; j < loops ; j++ )
+    {
+        if(j % 2) {
+            recalc_proxy(values, last_sum, iter, thread_i, count, name, j);
+        } else {
+            recalc(values, last_sum, iter, thread_i, count, name, j);
+        }
+    }
+#if 0
+    if(thread_i < 3)
+        diag_printf("INFO:<%s [%d]: %2d calculations done>\n",name,thread_i,j*count);
+#endif
+    if(thread_i < 3)
+        iter_n[thread_i] = iter;
+}
+
+
+//==========================================================================
+// Alarm handler
+//
+// This is called every tick. It lowers the priority of the currently
+// running thread and raises the priority of the next. Thus we
+// implement a form of timelslicing between the threads at one tick
+// granularity.
+
+static void alarm_fn(cyg_handle_t alarm, cyg_addrword_t data)
+{
+    alarm_ticks++;
+    unsigned long iter_sum;
+
+    if( alarm_ticks >= run_ticks )
+    {
+        if( errors )
+            CYG_TEST_FAIL("Errors detected");
+        else
+            CYG_TEST_PASS("OK");
+
+        iter_sum = + iter_n[0] + iter_n[1];
+        diag_printf("Iterations = %lu+%lu",
+                iter_n[0], iter_n[1]);
+        diag_printf("=%lu\n", iter_sum);
+        CYG_TEST_FINISH("FP Test done");
+    }
+}
+
+
+//==========================================================================
+// Floating point threads
+//
+#define FP1_COUNT 10
+
+static float fpt1_values[FP1_COUNT];
+
+void fptest1( CYG_ADDRWORD id )
+{
+    while(1)
+        do_test1( fpt1_values, FP1_COUNT, 2000000000, id, "fptest1" );
+}
+
+//==========================================================================
+#define FP2_COUNT 11
+
+static float fpt2_values[FP2_COUNT];
+
+void fptest2( CYG_ADDRWORD id )
+{
+    while(1)
+        do_test1( fpt2_values, FP2_COUNT, 2000000000, id, "fptest2" );
+}
+
+//======================================================================================
+// Main
+
+
+void fptest_main( void )
+{
+    CYG_TEST_INIT();
+
+    if( cyg_test_is_simulator )
+    {
+        run_ticks = RUN_TICKS_SIM;
+    }
+    CYG_TEST_INFO("Run fptest in cyg_start");
+    CYG_TEST_INFO( "cyg_start run done");
+
+    cyg_thread_create( BASE_PRI,
+                       fptest1,
+                       0,
+                       "thread1",
+                       &stacks[0][0],
+                       STACK_SIZE,
+                       &thread[0],
+                       &thread_struct[0]);
+    cyg_thread_resume( thread[0] );
+
+    cyg_thread_create( BASE_PRI,
+                       fptest2,
+                       1,
+                       "thread2",
+                       &stacks[1][0],
+                       STACK_SIZE,
+                       &thread[1],
+                       &thread_struct[1]);
+
+    cyg_thread_resume( thread[1] );
+
+    cyg_alarm_create( cyg_real_time_clock(),
+                      alarm_fn,
+                      0,
+                      &alarm,
+                      &alarm_struct );
+
+    cyg_alarm_initialize( alarm, cyg_current_time()+1, 1 );
+
+    cyg_scheduler_start();
+
+}
+
+//==========================================================================
+
+#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
+externC void
+cyg_hal_invoke_constructors();
+#endif
+
+externC void
+cyg_start( void )
+{
+#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
+    cyg_hal_invoke_constructors();
+#endif
+    fptest_main();
+}
+
+//==========================================================================
+
+#else // CYGFUN_KERNEL_API_C...
+
+externC void
+cyg_start( void )
+{
+    CYG_TEST_INIT();
+    CYG_TEST_INFO("FP test 2 requires:\n"
+                "CYGFUN_KERNEL_API_C && \n"
+                "CYGSEM_KERNEL_SCHED_MLQUEUE && \n"
+                "(CYGNUM_KERNEL_SCHED_PRIORITIES > 12) &&\n"
+                "(CYGMEM_REGION_ram_SIZE >= (49152-4096))\n"
+                "(!defined(CYGHWR_HAL_CORTEXM_FPU_SWITCH_NONE))\n"
+                );
+    CYG_TEST_NA("FP test requirements");
+}
+
+#endif // CYGFUN_KERNEL_API_C, etc.
+
+//==========================================================================
+// EOF fpinttestf2.c
diff --git a/packages/kernel/current/tests/fptest.c b/packages/kernel/current/tests/fptest.c
--- a/packages/kernel/current/tests/fptest.c
+++ b/packages/kernel/current/tests/fptest.c
@@ -68,7 +68,8 @@
 
 #if defined(CYGFUN_KERNEL_API_C) &&             \
     defined(CYGSEM_KERNEL_SCHED_MLQUEUE) &&     \
-    (CYGNUM_KERNEL_SCHED_PRIORITIES > 12)
+    (CYGNUM_KERNEL_SCHED_PRIORITIES > 12) &&    \
+    (CYGMEM_REGION_ram_SIZE >= (49152-4096))
 
 //==========================================================================
 // Base priority for all threads.
@@ -358,7 +359,8 @@ cyg_start( void )
     CYG_TEST_INFO("FP test requires:\n"
                 "CYGFUN_KERNEL_API_C && \n"
                 "CYGSEM_KERNEL_SCHED_MLQUEUE && \n"
-                "(CYGNUM_KERNEL_SCHED_PRIORITIES > 12)\n");
+                "(CYGNUM_KERNEL_SCHED_PRIORITIES > 12) &&\n"
+                "(CYGMEM_REGION_ram_SIZE >= (49152-4096))\n");
     CYG_TEST_NA("FP test requirements");
 }
 
diff --git a/packages/kernel/current/tests/intr0.cxx b/packages/kernel/current/tests/intr0.cxx
--- a/packages/kernel/current/tests/intr0.cxx
+++ b/packages/kernel/current/tests/intr0.cxx
@@ -197,8 +197,8 @@ void intr0_main( void )
     new_vsr = NULL;
     Cyg_Interrupt::get_vsr( v, &new_vsr );
     CHECK( old_vsr == new_vsr );
-        
-    CHECK( NULL != vsr0 );
+
+    CHECK( NULL != new_vsr);
 
     cyg_vector v1;
 #ifdef CYGPKG_HAL_MIPS_TX39    
diff --git a/packages/kernel/current/tests/kcache1.c b/packages/kernel/current/tests/kcache1.c
--- a/packages/kernel/current/tests/kcache1.c
+++ b/packages/kernel/current/tests/kcache1.c
@@ -109,7 +109,7 @@ static void time0(register cyg_uint32 st
     register cyg_uint32 j,k;
     cyg_tick_count_t count0, count1;
     cyg_ucount32 t;
-    register char c;
+    register char c CYGBLD_ATTRIB_UNUSED;
 
     count0 = cyg_current_time();
 
@@ -147,7 +147,7 @@ static void time0II(register cyg_uint32 
     register cyg_uint32 j,k;
     cyg_tick_count_t count0, count1;
     cyg_ucount32 t;
-    register char c;
+    register char c CYGBLD_ATTRIB_UNUSED;
 
     count0 = cyg_current_time();
 
@@ -189,7 +189,7 @@ static void time0DI(register cyg_uint32 
     volatile cyg_tick_count_t count0;
     cyg_tick_count_t count1;
     cyg_ucount32 t;
-    register char c;
+    register char c CYGBLD_ATTRIB_UNUSED;
     register CYG_INTERRUPT_STATE oldints;
 
     count0 = cyg_current_time();
diff --git a/packages/kernel/current/tests/kcache2.c b/packages/kernel/current/tests/kcache2.c
--- a/packages/kernel/current/tests/kcache2.c
+++ b/packages/kernel/current/tests/kcache2.c
@@ -57,6 +57,7 @@
 
 #include <cyg/infra/diag.h>
 #include <cyg/hal/hal_cache.h>
+#include CYGHWR_MEMORY_LAYOUT_H
 
 // -------------------------------------------------------------------------
 
@@ -83,7 +84,11 @@ static cyg_handle_t thread[NTHREADS];
 static cyg_thread thread_obj[NTHREADS];
 static char stack[NTHREADS][STACKSIZE];
 
-#define MAXSIZE 1<<18
+#if (CYGMEM_REGION_ram_SIZE <= (128*1024))
+# define MAXSIZE (1<<16)
+#else
+# define MAXSIZE (1<<18)
+#endif
 
 volatile char m[MAXSIZE];
 
diff --git a/packages/kernel/current/tests/kexcept1.c b/packages/kernel/current/tests/kexcept1.c
--- a/packages/kernel/current/tests/kexcept1.c
+++ b/packages/kernel/current/tests/kexcept1.c
@@ -131,7 +131,7 @@ cause_fpe(int num)
 
 void cause_exception(void)
 {
-    int x;
+    int x CYGBLD_ATTRIB_UNUSED;
     unsigned int p=0;
 
     // First try for an address exception (unaligned access exception
diff --git a/packages/kernel/current/tests/kintr0.c b/packages/kernel/current/tests/kintr0.c
--- a/packages/kernel/current/tests/kintr0.c
+++ b/packages/kernel/current/tests/kintr0.c
@@ -142,10 +142,12 @@ static bool flash( void )
 
 static cyg_VSR_t vsr0;
 
-static void vsr0()
+static void vsr0(void)
 {
 }
 
+static void (*vsr0_p)(void) = vsr0;
+
 void kintr0_main( void )
 {
     cyg_vector_t v = (CYGNUM_HAL_VSR_MIN + 11) % CYGNUM_HAL_VSR_COUNT;
@@ -221,7 +223,7 @@ void kintr0_main( void )
     cyg_interrupt_get_vsr( v, &new_vsr );
     CHECK( old_vsr == new_vsr );
         
-    CHECK( NULL != vsr0 );
+    CHECK( NULL != *vsr0_p );
 
     cyg_interrupt_mask(v1);
     cyg_interrupt_unmask(v1);
diff --git a/packages/kernel/current/tests/kmbox1.c b/packages/kernel/current/tests/kmbox1.c
--- a/packages/kernel/current/tests/kmbox1.c
+++ b/packages/kernel/current/tests/kmbox1.c
@@ -151,8 +151,10 @@ static void entry0( cyg_addrword_t data 
 
 static void entry1( cyg_addrword_t data )
 {
+#ifdef CYGMTH_MBOX_PUT_CAN_WAIT
     cyg_count8 i;
     i = (cyg_count8)cyg_mbox_get(m1);
+#endif
     CYG_TEST_CHECK(1==q++, "bad synchronization");
     cyg_mbox_PUT(m0, (void *)3);                  // wake t0
 
diff --git a/packages/kernel/current/tests/kmutex3.c b/packages/kernel/current/tests/kmutex3.c
--- a/packages/kernel/current/tests/kmutex3.c
+++ b/packages/kernel/current/tests/kmutex3.c
@@ -79,6 +79,7 @@ cyg_hal_invoke_constructors();
 #include <cyg/infra/cyg_ass.h>
 #include <cyg/infra/cyg_trac.h>
 #include <cyg/infra/diag.h>             // diag_printf
+#include CYGHWR_MEMORY_LAYOUT_H
 
 
 // ------------------------------------------------------------------------
@@ -133,8 +134,11 @@ cyg_hal_invoke_constructors();
 //
 // Translated into KAPI also.
 
-#define NTHREADS 7
-
+#if (CYGMEM_REGION_ram_SIZE <= 32768)
+# define NTHREADS 5
+#else
+# define NTHREADS 7
+#endif
 #define STACKSIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
 
 static  cyg_handle_t thread[NTHREADS] = { 0 };
diff --git a/packages/kernel/current/tests/kmutex4.c b/packages/kernel/current/tests/kmutex4.c
--- a/packages/kernel/current/tests/kmutex4.c
+++ b/packages/kernel/current/tests/kmutex4.c
@@ -78,6 +78,7 @@ cyg_hal_invoke_constructors();
 #include <cyg/infra/cyg_ass.h>
 #include <cyg/infra/cyg_trac.h>
 #include <cyg/infra/diag.h>             // diag_printf
+#include CYGHWR_MEMORY_LAYOUT_H
 
 // ------------------------------------------------------------------------
 
@@ -116,7 +117,11 @@ static char * protnames[] = {
 //
 // Translated into KAPI also.
 
-#define NTHREADS 7
+#if (CYGMEM_REGION_ram_SIZE <= 32768)
+# define NTHREADS 5
+#else
+# define NTHREADS 7
+#endif
 
 #define STACKSIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
 
diff --git a/packages/kernel/current/tests/mbox1.cxx b/packages/kernel/current/tests/mbox1.cxx
--- a/packages/kernel/current/tests/mbox1.cxx
+++ b/packages/kernel/current/tests/mbox1.cxx
@@ -151,11 +151,15 @@ static void entry0( CYG_ADDRWORD data )
 
 static void entry1( CYG_ADDRWORD data )
 {
+#ifdef CYGMTH_MBOX_PUT_CAN_WAIT
     cyg_count8 i;
+#endif
 
     Cyg_Thread::self()->set_priority(5);
     
+#ifdef CYGMTH_MBOX_PUT_CAN_WAIT
     i = (cyg_count8)m1.get();
+#endif
     CYG_TEST_CHECK(1==q++, "bad synchronization");
     m0.PUT((void *)3);                  // wake t0
 
diff --git a/packages/kernel/current/tests/mutex3.cxx b/packages/kernel/current/tests/mutex3.cxx
--- a/packages/kernel/current/tests/mutex3.cxx
+++ b/packages/kernel/current/tests/mutex3.cxx
@@ -59,6 +59,7 @@
 #include <cyg/kernel/thread.inl>
 
 #include <cyg/infra/diag.h>             // diag_printf
+#include CYGHWR_MEMORY_LAYOUT_H
 
 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
 externC void
@@ -128,7 +129,11 @@ cyg_hal_invoke_constructors();
 // Stolen from testaux.hxx and copied in here because I want to be able to
 // reset the world also.
 
-#define NTHREADS 7
+#if (CYGMEM_REGION_ram_SIZE <= 32768)
+# define NTHREADS 5
+#else
+# define NTHREADS 7
+#endif
 
 inline void *operator new(size_t size, void *ptr) { return ptr; };
 
diff --git a/packages/kernel/current/tests/thread_gdb.c b/packages/kernel/current/tests/thread_gdb.c
--- a/packages/kernel/current/tests/thread_gdb.c
+++ b/packages/kernel/current/tests/thread_gdb.c
@@ -56,10 +56,17 @@
     (CYGNUM_KERNEL_SCHED_PRIORITIES > 26)
 
 #include <cyg/hal/hal_arch.h>           // for CYGNUM_HAL_STACK_SIZE_TYPICAL
+#include CYGHWR_MEMORY_LAYOUT_H
 
 // -------------------------------------------------------------------------
 
-#define THREADS                 10
+#if (CYGMEM_REGION_ram_SIZE <= 32768)
+# define THREADS 5
+#elif (CYGMEM_REGION_ram_SIZE <= 49152)
+# define THREADS 8
+#else
+# define THREADS 10
+#endif
 
 #ifdef CYGNUM_HAL_STACK_SIZE_TYPICAL
 #define STACKSIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
diff --git a/packages/kernel/current/tests/timeslice.c b/packages/kernel/current/tests/timeslice.c
--- a/packages/kernel/current/tests/timeslice.c
+++ b/packages/kernel/current/tests/timeslice.c
@@ -58,6 +58,7 @@
 
 #include <cyg/infra/testcase.h>
 #include <cyg/infra/diag.h>
+#include CYGHWR_MEMORY_LAYOUT_H
 
 //==========================================================================
 
@@ -72,7 +73,11 @@
 
 #define STACK_SIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
 
+#if (CYGMEM_REGION_ram_SIZE <= 32768)
+#define NTHREADS_MAX (CYGNUM_KERNEL_CPU_MAX*4)
+#else
 #define NTHREADS_MAX (CYGNUM_KERNEL_CPU_MAX*6)
+#endif
 
 static int ncpus = CYGNUM_KERNEL_CPU_MAX;
 
diff --git a/packages/kernel/current/tests/timeslice2.c b/packages/kernel/current/tests/timeslice2.c
--- a/packages/kernel/current/tests/timeslice2.c
+++ b/packages/kernel/current/tests/timeslice2.c
@@ -58,6 +58,7 @@
 
 #include <cyg/infra/testcase.h>
 #include <cyg/infra/diag.h>
+#include CYGHWR_MEMORY_LAYOUT_H
 
 //==========================================================================
 
@@ -72,7 +73,11 @@
 
 #define STACK_SIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
 
+#if (CYGMEM_REGION_ram_SIZE <= 32768)
+#define NTHREADS_MAX (CYGNUM_KERNEL_CPU_MAX*3)
+#else
 #define NTHREADS_MAX (CYGNUM_KERNEL_CPU_MAX*6)
+#endif
 
 static int ncpus = CYGNUM_KERNEL_CPU_MAX;
 
diff --git a/packages/kernel/current/tests/tm_basic.cxx b/packages/kernel/current/tests/tm_basic.cxx
--- a/packages/kernel/current/tests/tm_basic.cxx
+++ b/packages/kernel/current/tests/tm_basic.cxx
@@ -88,7 +88,8 @@ typedef struct fun_times {
 
 #ifdef CYGMEM_REGION_ram_SIZE
 #define CYG_THREAD_OVERHEAD  (STACK_SIZE+sizeof(cyg_thread)+(sizeof(fun_times)*2))
-#define NTEST_THREADS        ((CYGMEM_REGION_ram_SIZE/16)/CYG_THREAD_OVERHEAD)
+#define NTEST_THREADS_AVAIL  ((CYGMEM_REGION_ram_SIZE/16)/CYG_THREAD_OVERHEAD)
+#define NTEST_THREADS        (2>(NTEST_THREADS_AVAIL)?2:(NTEST_THREADS_AVAIL))
 #define CYG_MUTEX_OVERHEAD   (sizeof(cyg_mutex_t)+sizeof(fun_times))
 #define NMUTEXES             ((CYGMEM_REGION_ram_SIZE/16)/CYG_MUTEX_OVERHEAD)
 #define CYG_MBOX_OVERHEAD    (sizeof(cyg_mbox)+sizeof(fun_times))
@@ -224,15 +225,26 @@ wait_for_tick(void)
     }
 }
 
+#ifdef HAL_CLOCK_READ_NS
+#define READ_CLOCK(__x) HAL_CLOCK_READ_NS(__x)
+#define NSTICK (1)
+#else
+#define READ_CLOCK(__x) HAL_CLOCK_READ(__x)
+#define NSTICK (1000)
+#endif
 // Display a number of ticks as microseconds
-// Note: for improved calculation significance, values are kept in ticks*1000
+// Note: for improved calculation significance, values are kept in ticks*NSTICK
 void
 show_ticks_in_us(cyg_uint32 ticks)
 {
     long long ns;
     ns = (ns_per_system_clock * (long long)ticks) / CYGNUM_KERNEL_COUNTERS_RTC_PERIOD;
+#ifdef HAL_CLOCK_READ_NS
+    diag_printf("%4d.%03d", (int)(ns/1000), (int)(ns%1000));
+#else
     ns += 5;  // for rounding to .01us
     diag_printf("%5d.%02d", (int)(ns/1000), (int)((ns%1000)/10));
+#endif
 }
 
 //
@@ -324,7 +336,7 @@ show_times_detail(fun_times ft[], int ns
         }
         delta -= overhead;
         if (delta < 0) delta = 0;
-        delta *= 1000;
+        delta *= NSTICK;
         total += delta;
         if (delta < min) min = delta;
         if (delta > max) max = delta;
@@ -341,7 +353,7 @@ show_times_detail(fun_times ft[], int ns
         }
         delta -= overhead;
         if (delta < 0) delta = 0;
-        delta *= 1000;
+        delta *= NSTICK;
         delta = delta - ave;
         if (delta < 0) delta = -delta;
         ave_dev += delta;
@@ -358,7 +370,7 @@ show_times_detail(fun_times ft[], int ns
         }
         delta -= overhead;
         if (delta < 0) delta = 0;
-        delta *= 1000;
+        delta *= NSTICK;
         if ((delta <= (ave+ave_dev)) && (delta >= (ave-ave_dev))) con_ave++;
         if ((delta <= (min+ave_dev)) && (delta >= (min-ave_dev))) con_min++;
     }
@@ -444,9 +456,9 @@ test2(cyg_uint32 indx)
     int i;
     for (i = 0;  i < nthread_switches;  i++) {
         if (indx == 0) {
-            HAL_CLOCK_READ(&test2_ft[i].start);
+            READ_CLOCK(&test2_ft[i].start);
         } else {
-            HAL_CLOCK_READ(&test2_ft[i].end);
+            READ_CLOCK(&test2_ft[i].end);
         }
         cyg_thread_yield();
     }
@@ -465,7 +477,7 @@ mutex_test(cyg_uint32 indx)
     for (i = 0;  i < nmutexes;  i++) {
         cyg_semaphore_wait(&synchro);
         wait_for_tick(); // Wait until the next clock tick to minimize aberations
-        HAL_CLOCK_READ(&mutex_ft[i].start);
+        READ_CLOCK(&mutex_ft[i].start);
         cyg_mutex_unlock(&test_mutexes[0]);
         cyg_mutex_lock(&test_mutexes[0]);
         cyg_semaphore_post(&synchro);
@@ -480,7 +492,7 @@ mbox_test(cyg_uint32 indx)
     void *item;
     do {
         item = cyg_mbox_get(test_mbox_handles[0]);
-        HAL_CLOCK_READ(&mbox_ft[(int)item].end);
+        READ_CLOCK(&mbox_ft[(int)item].end);
         cyg_semaphore_post(&synchro);
     } while ((int)item != (nmboxes-1));
     cyg_thread_exit();
@@ -493,7 +505,7 @@ semaphore_test(cyg_uint32 indx)
     int i;
     for (i = 0;  i < nsemaphores;  i++) {
         cyg_semaphore_wait(&test_semaphores[0]);
-        HAL_CLOCK_READ(&semaphore_ft[i].end);
+        READ_CLOCK(&semaphore_ft[i].end);
         cyg_semaphore_post(&synchro);
     }
     cyg_thread_exit();
@@ -506,14 +518,13 @@ void
 run_thread_tests(void)
 {
     int i;
-    cyg_priority_t prio;
 
     // Set my priority higher than any I plan to create
     cyg_thread_set_priority(cyg_thread_self(), 2);
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_create(10,              // Priority - just a number
                           test0,           // entry
                           i,               // index
@@ -523,63 +534,63 @@ run_thread_tests(void)
                           &threads[i],     // Handle
                           &test_threads[i] // Thread data structure
             );
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Create thread");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_yield();
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Yield thread [all suspended]");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_suspend(threads[i]);
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Suspend [suspended] thread");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_resume(threads[i]);
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Resume thread");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_set_priority(threads[i], 11);
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Set priority");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
-        prio = cyg_thread_get_priority(threads[i]);
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].start);
+        cyg_thread_get_priority(threads[i]);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Get priority");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_kill(threads[i]);
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Kill [suspended] thread");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_yield();
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Yield [no other] thread");
 
@@ -601,42 +612,42 @@ run_thread_tests(void)
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_resume(threads[i]);
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Resume [suspended low prio] thread");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_resume(threads[i]);
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Resume [runnable low prio] thread");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_suspend(threads[i]);
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Suspend [runnable] thread");
 
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_yield();
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Yield [only low prio] thread");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_suspend(threads[i]);
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Suspend [runnable->not runnable]");
     for (i = 0;  i < ntest_threads;  i++) {
@@ -645,17 +656,17 @@ run_thread_tests(void)
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_kill(threads[i]);
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Kill [runnable] thread");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_delete(threads[i]);
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Destroy [dead] thread");
 
@@ -675,9 +686,9 @@ run_thread_tests(void)
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_delete(threads[i]);
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Destroy [runnable] thread");
 
@@ -702,9 +713,9 @@ run_thread_tests(void)
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ntest_threads;  i++) {
-        HAL_CLOCK_READ(&thread_ft[i].start);
+        READ_CLOCK(&thread_ft[i].start);
         cyg_thread_resume(threads[i]);
-        HAL_CLOCK_READ(&thread_ft[i].end);
+        READ_CLOCK(&thread_ft[i].end);
     }
     show_times(thread_ft, ntest_threads, "Resume [high priority] thread");
     cyg_semaphore_wait(&synchro);  // Wait for all threads to finish
@@ -754,41 +765,41 @@ run_mutex_tests(void)
     // Mutex primitives
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmutexes;  i++) {
-        HAL_CLOCK_READ(&mutex_ft[i].start);
+        READ_CLOCK(&mutex_ft[i].start);
         cyg_mutex_init(&test_mutexes[i]);
-        HAL_CLOCK_READ(&mutex_ft[i].end);
+        READ_CLOCK(&mutex_ft[i].end);
     }
     show_times(mutex_ft, nmutexes, "Init mutex");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmutexes;  i++) {
-        HAL_CLOCK_READ(&mutex_ft[i].start);
+        READ_CLOCK(&mutex_ft[i].start);
         cyg_mutex_lock(&test_mutexes[i]);
-        HAL_CLOCK_READ(&mutex_ft[i].end);
+        READ_CLOCK(&mutex_ft[i].end);
     }
     show_times(mutex_ft, nmutexes, "Lock [unlocked] mutex");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmutexes;  i++) {
-        HAL_CLOCK_READ(&mutex_ft[i].start);
+        READ_CLOCK(&mutex_ft[i].start);
         cyg_mutex_unlock(&test_mutexes[i]);
-        HAL_CLOCK_READ(&mutex_ft[i].end);
+        READ_CLOCK(&mutex_ft[i].end);
     }
     show_times(mutex_ft, nmutexes, "Unlock [locked] mutex");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmutexes;  i++) {
-        HAL_CLOCK_READ(&mutex_ft[i].start);
+        READ_CLOCK(&mutex_ft[i].start);
         cyg_mutex_trylock(&test_mutexes[i]);
-        HAL_CLOCK_READ(&mutex_ft[i].end);
+        READ_CLOCK(&mutex_ft[i].end);
     }
     show_times(mutex_ft, nmutexes, "Trylock [unlocked] mutex");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmutexes;  i++) {
-        HAL_CLOCK_READ(&mutex_ft[i].start);
+        READ_CLOCK(&mutex_ft[i].start);
         cyg_mutex_trylock(&test_mutexes[i]);
-        HAL_CLOCK_READ(&mutex_ft[i].end);
+        READ_CLOCK(&mutex_ft[i].end);
     }
     show_times(mutex_ft, nmutexes, "Trylock [locked] mutex");
 
@@ -799,9 +810,9 @@ run_mutex_tests(void)
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmutexes;  i++) {
-        HAL_CLOCK_READ(&mutex_ft[i].start);
+        READ_CLOCK(&mutex_ft[i].start);
         cyg_mutex_destroy(&test_mutexes[i]);
-        HAL_CLOCK_READ(&mutex_ft[i].end);
+        READ_CLOCK(&mutex_ft[i].end);
     }
     show_times(mutex_ft, nmutexes, "Destroy mutex");
     run_mutex_circuit_test();
@@ -832,7 +843,7 @@ run_mutex_circuit_test(void)
     for (i = 0;  i < nmutexes;  i++) {
         cyg_semaphore_post(&synchro);
         cyg_mutex_lock(&test_mutexes[0]);
-        HAL_CLOCK_READ(&mutex_ft[i].end);
+        READ_CLOCK(&mutex_ft[i].end);
         cyg_mutex_unlock(&test_mutexes[0]);
         cyg_semaphore_wait(&synchro);
     }
@@ -843,136 +854,135 @@ run_mutex_circuit_test(void)
 void
 run_mbox_tests(void)
 {
-    int i, cnt;
-    void *item;
+    int i;
     // Mailbox primitives
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
+        READ_CLOCK(&mbox_ft[i].start);
         cyg_mbox_create(&test_mbox_handles[i], &test_mboxes[i]);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Create mbox");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
-        cnt = cyg_mbox_peek(test_mbox_handles[i]);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].start);
+        cyg_mbox_peek(test_mbox_handles[i]);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Peek [empty] mbox");
 
 #ifdef CYGMFN_KERNEL_SYNCH_MBOXT_PUT_CAN_WAIT
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
+        READ_CLOCK(&mbox_ft[i].start);
         cyg_mbox_put(test_mbox_handles[i], (void *)i);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Put [first] mbox");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
-        cnt = cyg_mbox_peek(test_mbox_handles[i]);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].start);
+        cyg_mbox_peek(test_mbox_handles[i]);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Peek [1 msg] mbox");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
+        READ_CLOCK(&mbox_ft[i].start);
         cyg_mbox_put(test_mbox_handles[i], (void *)i);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Put [second] mbox");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
-        cnt = cyg_mbox_peek(test_mbox_handles[i]);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].start);
+        cyg_mbox_peek(test_mbox_handles[i]);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Peek [2 msgs] mbox");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
-        item = cyg_mbox_get(test_mbox_handles[i]);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].start);
+        cyg_mbox_get(test_mbox_handles[i]);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Get [first] mbox");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
-        item = cyg_mbox_get(test_mbox_handles[i]);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].start);
+        cyg_mbox_get(test_mbox_handles[i]);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Get [second] mbox");
 #endif // ifdef CYGMFN_KERNEL_SYNCH_MBOXT_PUT_CAN_WAIT
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
+        READ_CLOCK(&mbox_ft[i].start);
         cyg_mbox_tryput(test_mbox_handles[i], (void *)i);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Tryput [first] mbox");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
-        item = cyg_mbox_peek_item(test_mbox_handles[i]);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].start);
+        cyg_mbox_peek_item(test_mbox_handles[i]);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Peek item [non-empty] mbox");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
-        item = cyg_mbox_tryget(test_mbox_handles[i]);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].start);
+        cyg_mbox_tryget(test_mbox_handles[i]);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Tryget [non-empty] mbox");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
-        item = cyg_mbox_peek_item(test_mbox_handles[i]);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].start);
+        cyg_mbox_peek_item(test_mbox_handles[i]);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Peek item [empty] mbox");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
-        item = cyg_mbox_tryget(test_mbox_handles[i]);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].start);
+        cyg_mbox_tryget(test_mbox_handles[i]);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Tryget [empty] mbox");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
+        READ_CLOCK(&mbox_ft[i].start);
         cyg_mbox_waiting_to_get(test_mbox_handles[i]);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Waiting to get mbox");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
+        READ_CLOCK(&mbox_ft[i].start);
         cyg_mbox_waiting_to_put(test_mbox_handles[i]);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Waiting to put mbox");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nmboxes;  i++) {
-        HAL_CLOCK_READ(&mbox_ft[i].start);
+        READ_CLOCK(&mbox_ft[i].start);
         cyg_mbox_delete(test_mbox_handles[i]);
-        HAL_CLOCK_READ(&mbox_ft[i].end);
+        READ_CLOCK(&mbox_ft[i].end);
     }
     show_times(mbox_ft, nmboxes, "Delete mbox");
 
@@ -1002,7 +1012,7 @@ run_mbox_circuit_test(void)
     cyg_thread_resume(mbox_test_thread_handle);
     for (i = 0;  i < nmboxes;  i++) {
         wait_for_tick(); // Wait until the next clock tick to minimize aberations
-        HAL_CLOCK_READ(&mbox_ft[i].start);
+        READ_CLOCK(&mbox_ft[i].start);
         cyg_mbox_put(test_mbox_handles[0], (void *)i);
         cyg_semaphore_wait(&synchro);
     }
@@ -1019,58 +1029,58 @@ run_semaphore_tests(void)
     // Semaphore primitives
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nsemaphores;  i++) {
-        HAL_CLOCK_READ(&semaphore_ft[i].start);
+        READ_CLOCK(&semaphore_ft[i].start);
         cyg_semaphore_init(&test_semaphores[i], 0);
-        HAL_CLOCK_READ(&semaphore_ft[i].end);
+        READ_CLOCK(&semaphore_ft[i].end);
     }
     show_times(semaphore_ft, nsemaphores, "Init semaphore");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nsemaphores;  i++) {
-        HAL_CLOCK_READ(&semaphore_ft[i].start);
+        READ_CLOCK(&semaphore_ft[i].start);
         cyg_semaphore_post(&test_semaphores[i]);
-        HAL_CLOCK_READ(&semaphore_ft[i].end);
+        READ_CLOCK(&semaphore_ft[i].end);
     }
     show_times(semaphore_ft, nsemaphores, "Post [0] semaphore");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nsemaphores;  i++) {
-        HAL_CLOCK_READ(&semaphore_ft[i].start);
+        READ_CLOCK(&semaphore_ft[i].start);
         cyg_semaphore_wait(&test_semaphores[i]);
-        HAL_CLOCK_READ(&semaphore_ft[i].end);
+        READ_CLOCK(&semaphore_ft[i].end);
     }
     show_times(semaphore_ft, nsemaphores, "Wait [1] semaphore");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nsemaphores;  i++) {
-        HAL_CLOCK_READ(&semaphore_ft[i].start);
+        READ_CLOCK(&semaphore_ft[i].start);
         cyg_semaphore_trywait(&test_semaphores[i]);
-        HAL_CLOCK_READ(&semaphore_ft[i].end);
+        READ_CLOCK(&semaphore_ft[i].end);
     }
     show_times(semaphore_ft, nsemaphores, "Trywait [0] semaphore");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nsemaphores;  i++) {
         cyg_semaphore_post(&test_semaphores[i]);
-        HAL_CLOCK_READ(&semaphore_ft[i].start);
+        READ_CLOCK(&semaphore_ft[i].start);
         cyg_semaphore_trywait(&test_semaphores[i]);
-        HAL_CLOCK_READ(&semaphore_ft[i].end);
+        READ_CLOCK(&semaphore_ft[i].end);
     }
     show_times(semaphore_ft, nsemaphores, "Trywait [1] semaphore");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nsemaphores;  i++) {
-        HAL_CLOCK_READ(&semaphore_ft[i].start);
+        READ_CLOCK(&semaphore_ft[i].start);
         cyg_semaphore_peek(&test_semaphores[i], &sem_val);
-        HAL_CLOCK_READ(&semaphore_ft[i].end);
+        READ_CLOCK(&semaphore_ft[i].end);
     }
     show_times(semaphore_ft, nsemaphores, "Peek semaphore");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nsemaphores;  i++) {
-        HAL_CLOCK_READ(&semaphore_ft[i].start);
+        READ_CLOCK(&semaphore_ft[i].start);
         cyg_semaphore_destroy(&test_semaphores[i]);
-        HAL_CLOCK_READ(&semaphore_ft[i].end);
+        READ_CLOCK(&semaphore_ft[i].end);
     }
     show_times(semaphore_ft, nsemaphores, "Destroy semaphore");
 
@@ -1099,7 +1109,7 @@ run_semaphore_circuit_test(void)
     cyg_thread_resume(semaphore_test_thread_handle);
     for (i = 0;  i < nsemaphores;  i++) {
         wait_for_tick(); // Wait until the next clock tick to minimize aberations
-        HAL_CLOCK_READ(&semaphore_ft[i].start);
+        READ_CLOCK(&semaphore_ft[i].start);
         cyg_semaphore_post(&test_semaphores[0]);
         cyg_semaphore_wait(&synchro);
     }
@@ -1115,41 +1125,41 @@ run_counter_tests(void)
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ncounters;  i++) {
-        HAL_CLOCK_READ(&counter_ft[i].start);
+        READ_CLOCK(&counter_ft[i].start);
         cyg_counter_create(&counters[i], &test_counters[i]);
-        HAL_CLOCK_READ(&counter_ft[i].end);
+        READ_CLOCK(&counter_ft[i].end);
     }
     show_times(counter_ft, ncounters, "Create counter");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ncounters;  i++) {
-        HAL_CLOCK_READ(&counter_ft[i].start);
+        READ_CLOCK(&counter_ft[i].start);
         val = cyg_counter_current_value(counters[i]);
-        HAL_CLOCK_READ(&counter_ft[i].end);
+        READ_CLOCK(&counter_ft[i].end);
     }
     show_times(counter_ft, ncounters, "Get counter value");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ncounters;  i++) {
-        HAL_CLOCK_READ(&counter_ft[i].start);
+        READ_CLOCK(&counter_ft[i].start);
         cyg_counter_set_value(counters[i], val);
-        HAL_CLOCK_READ(&counter_ft[i].end);
+        READ_CLOCK(&counter_ft[i].end);
     }
     show_times(counter_ft, ncounters, "Set counter value");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ncounters;  i++) {
-        HAL_CLOCK_READ(&counter_ft[i].start);
+        READ_CLOCK(&counter_ft[i].start);
         cyg_counter_tick(counters[i]);
-        HAL_CLOCK_READ(&counter_ft[i].end);
+        READ_CLOCK(&counter_ft[i].end);
     }
     show_times(counter_ft, ncounters, "Tick counter");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < ncounters;  i++) {
-        HAL_CLOCK_READ(&counter_ft[i].start);
+        READ_CLOCK(&counter_ft[i].start);
         cyg_counter_delete(counters[i]);
-        HAL_CLOCK_READ(&counter_ft[i].end);
+        READ_CLOCK(&counter_ft[i].end);
     }
     show_times(counter_ft, ncounters, "Delete counter");
     end_of_test_group();
@@ -1159,21 +1169,20 @@ void
 run_flag_tests(void)
 {
     int i;
-    cyg_flag_value_t val;
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nflags;  i++) {
-        HAL_CLOCK_READ(&flag_ft[i].start);
+        READ_CLOCK(&flag_ft[i].start);
         cyg_flag_init(&test_flags[i]);
-        HAL_CLOCK_READ(&flag_ft[i].end);
+        READ_CLOCK(&flag_ft[i].end);
     }
     show_times(flag_ft, nflags, "Init flag");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nflags;  i++) {
-        HAL_CLOCK_READ(&flag_ft[i].start);
+        READ_CLOCK(&flag_ft[i].start);
         cyg_flag_destroy(&test_flags[i]);
-        HAL_CLOCK_READ(&flag_ft[i].end);
+        READ_CLOCK(&flag_ft[i].end);
     }
     show_times(flag_ft, nflags, "Destroy flag");
 
@@ -1184,62 +1193,62 @@ run_flag_tests(void)
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nflags;  i++) {
-        HAL_CLOCK_READ(&flag_ft[i].start);
+        READ_CLOCK(&flag_ft[i].start);
         cyg_flag_maskbits(&test_flags[i], 0);
-        HAL_CLOCK_READ(&flag_ft[i].end);
+        READ_CLOCK(&flag_ft[i].end);
     }
     show_times(flag_ft, nflags, "Mask bits in flag");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nflags;  i++) {
-        HAL_CLOCK_READ(&flag_ft[i].start);
+        READ_CLOCK(&flag_ft[i].start);
         cyg_flag_setbits(&test_flags[i], 0x11);
-        HAL_CLOCK_READ(&flag_ft[i].end);
+        READ_CLOCK(&flag_ft[i].end);
     }
     show_times(flag_ft, nflags, "Set bits in flag [no waiters]");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nflags;  i++) {
         cyg_flag_setbits(&test_flags[i], 0x11);
-        HAL_CLOCK_READ(&flag_ft[i].start);
+        READ_CLOCK(&flag_ft[i].start);
         cyg_flag_wait(&test_flags[i], 0x11, CYG_FLAG_WAITMODE_AND);
-        HAL_CLOCK_READ(&flag_ft[i].end);
+        READ_CLOCK(&flag_ft[i].end);
     }
     show_times(flag_ft, nflags, "Wait for flag [AND]");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nflags;  i++) {
         cyg_flag_setbits(&test_flags[i], 0x11);
-        HAL_CLOCK_READ(&flag_ft[i].start);
+        READ_CLOCK(&flag_ft[i].start);
         cyg_flag_wait(&test_flags[i], 0x11, CYG_FLAG_WAITMODE_OR);
-        HAL_CLOCK_READ(&flag_ft[i].end);
+        READ_CLOCK(&flag_ft[i].end);
     }
     show_times(flag_ft, nflags, "Wait for flag [OR]");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nflags;  i++) {
         cyg_flag_setbits(&test_flags[i], 0x11);
-        HAL_CLOCK_READ(&flag_ft[i].start);
+        READ_CLOCK(&flag_ft[i].start);
         cyg_flag_wait(&test_flags[i], 0x11, CYG_FLAG_WAITMODE_AND|CYG_FLAG_WAITMODE_CLR);
-        HAL_CLOCK_READ(&flag_ft[i].end);
+        READ_CLOCK(&flag_ft[i].end);
     }
     show_times(flag_ft, nflags, "Wait for flag [AND/CLR]");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nflags;  i++) {
         cyg_flag_setbits(&test_flags[i], 0x11);
-        HAL_CLOCK_READ(&flag_ft[i].start);
+        READ_CLOCK(&flag_ft[i].start);
         cyg_flag_wait(&test_flags[i], 0x11, CYG_FLAG_WAITMODE_OR|CYG_FLAG_WAITMODE_CLR);
-        HAL_CLOCK_READ(&flag_ft[i].end);
+        READ_CLOCK(&flag_ft[i].end);
     }
     show_times(flag_ft, nflags, "Wait for flag [OR/CLR]");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nflags;  i++) {
         cyg_flag_setbits(&test_flags[i], 0x11);
-        HAL_CLOCK_READ(&flag_ft[i].start);
-        val = cyg_flag_peek(&test_flags[i]);
-        HAL_CLOCK_READ(&flag_ft[i].end);
+        READ_CLOCK(&flag_ft[i].start);
+        cyg_flag_peek(&test_flags[i]);
+        READ_CLOCK(&flag_ft[i].end);
     }
     show_times(flag_ft, nflags, "Peek on flag");
 
@@ -1264,7 +1273,7 @@ alarm_cb2(cyg_handle_t alarm, cyg_addrwo
 {
     if (alarm_cnt == nscheds) return;
     sched_ft[alarm_cnt].start = 0;
-    HAL_CLOCK_READ(&sched_ft[alarm_cnt++].end);
+    READ_CLOCK(&sched_ft[alarm_cnt++].end);
     if (alarm_cnt == nscheds) {
         cyg_semaphore_post(&synchro);
     }
@@ -1296,7 +1305,7 @@ alarm_test2(cyg_uint32 id)
 {
     cyg_handle_t me = cyg_thread_self();
     while (true) {
-        HAL_CLOCK_READ(&sched_ft[alarm_cnt++].end);
+        READ_CLOCK(&sched_ft[alarm_cnt++].end);
         cyg_thread_suspend(me);
     }
 }
@@ -1313,44 +1322,44 @@ run_alarm_tests(void)
         cyg_counter_create(&counters[i], &test_counters[i]);
     }
     for (i = 0;  i < nalarms;  i++) {
-        HAL_CLOCK_READ(&alarm_ft[i].start);
+        READ_CLOCK(&alarm_ft[i].start);
         cyg_alarm_create(counters[0], alarm_cb, 0, &alarms[i], &test_alarms[i]);
-        HAL_CLOCK_READ(&alarm_ft[i].end);
+        READ_CLOCK(&alarm_ft[i].end);
     }
     show_times(alarm_ft, nalarms, "Create alarm");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     init_val = 0;  step_val = 0;
     for (i = 0;  i < nalarms;  i++) {
-        HAL_CLOCK_READ(&alarm_ft[i].start);
+        READ_CLOCK(&alarm_ft[i].start);
         cyg_alarm_initialize(alarms[i], init_val, step_val);
-        HAL_CLOCK_READ(&alarm_ft[i].end);
+        READ_CLOCK(&alarm_ft[i].end);
     }
     show_times(alarm_ft, nalarms, "Initialize alarm");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     init_val = 0;  step_val = 0;
     for (i = 0;  i < nalarms;  i++) {
-        HAL_CLOCK_READ(&alarm_ft[i].start);
+        READ_CLOCK(&alarm_ft[i].start);
         cyg_alarm_disable(alarms[i]);
-        HAL_CLOCK_READ(&alarm_ft[i].end);
+        READ_CLOCK(&alarm_ft[i].end);
     }
     show_times(alarm_ft, nalarms, "Disable alarm");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     init_val = 0;  step_val = 0;
     for (i = 0;  i < nalarms;  i++) {
-        HAL_CLOCK_READ(&alarm_ft[i].start);
+        READ_CLOCK(&alarm_ft[i].start);
         cyg_alarm_enable(alarms[i]);
-        HAL_CLOCK_READ(&alarm_ft[i].end);
+        READ_CLOCK(&alarm_ft[i].end);
     }
     show_times(alarm_ft, nalarms, "Enable alarm");
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nalarms;  i++) {
-        HAL_CLOCK_READ(&alarm_ft[i].start);
+        READ_CLOCK(&alarm_ft[i].start);
         cyg_alarm_delete(alarms[i]);
-        HAL_CLOCK_READ(&alarm_ft[i].end);
+        READ_CLOCK(&alarm_ft[i].end);
     }
     show_times(alarm_ft, nalarms, "Delete alarm");
 
@@ -1361,9 +1370,9 @@ run_alarm_tests(void)
     cyg_alarm_initialize(alarms[0], init_val, step_val);
     cyg_alarm_enable(alarms[0]);
     for (i = 0;  i < ncounters;  i++) {
-        HAL_CLOCK_READ(&counter_ft[i].start);
+        READ_CLOCK(&counter_ft[i].start);
         cyg_counter_tick(counters[0]);
-        HAL_CLOCK_READ(&counter_ft[i].end);
+        READ_CLOCK(&counter_ft[i].end);
     }
     show_times(counter_ft, ncounters, "Tick counter [1 alarm]");
 
@@ -1376,9 +1385,9 @@ run_alarm_tests(void)
         cyg_alarm_enable(alarms[i]);
     }
     for (i = 0;  i < ncounters;  i++) {
-        HAL_CLOCK_READ(&counter_ft[i].start);
+        READ_CLOCK(&counter_ft[i].start);
         cyg_counter_tick(counters[0]);
-        HAL_CLOCK_READ(&counter_ft[i].end);
+        READ_CLOCK(&counter_ft[i].end);
     }
     show_times(counter_ft, ncounters, "Tick counter [many alarms]");
 
@@ -1389,9 +1398,9 @@ run_alarm_tests(void)
     cyg_alarm_initialize(alarms[0], init_val, step_val);
     cyg_alarm_enable(alarms[0]);
     for (i = 0;  i < ncounters;  i++) {
-        HAL_CLOCK_READ(&counter_ft[i].start);
+        READ_CLOCK(&counter_ft[i].start);
         cyg_counter_tick(counters[0]);
-        HAL_CLOCK_READ(&counter_ft[i].end);
+        READ_CLOCK(&counter_ft[i].end);
     }
     show_times(counter_ft, ncounters, "Tick & fire counter [1 alarm]");
 
@@ -1404,9 +1413,9 @@ run_alarm_tests(void)
         cyg_alarm_enable(alarms[i]);
     }
     for (i = 0;  i < nalarms;  i++) {
-        HAL_CLOCK_READ(&alarm_ft[i].start);
+        READ_CLOCK(&alarm_ft[i].start);
         cyg_counter_tick(counters[0]);
-        HAL_CLOCK_READ(&alarm_ft[i].end);
+        READ_CLOCK(&alarm_ft[i].end);
     }
     for (i = 0;  i < nalarms;  i++) {
         cyg_alarm_delete(alarms[i]);
@@ -1422,9 +1431,9 @@ run_alarm_tests(void)
         cyg_alarm_enable(alarms[i]);
     }
     for (i = 0;  i < nalarms;  i++) {
-        HAL_CLOCK_READ(&alarm_ft[i].start);
+        READ_CLOCK(&alarm_ft[i].start);
         cyg_counter_tick(counters[0]);
-        HAL_CLOCK_READ(&alarm_ft[i].end);
+        READ_CLOCK(&alarm_ft[i].end);
     }
     for (i = 0;  i < nalarms;  i++) {
         cyg_alarm_delete(alarms[i]);
@@ -1539,9 +1548,9 @@ run_sched_tests(void)
 
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nscheds;  i++) {
-        HAL_CLOCK_READ(&sched_ft[i].start);
+        READ_CLOCK(&sched_ft[i].start);
         cyg_scheduler_lock();
-        HAL_CLOCK_READ(&sched_ft[i].end);
+        READ_CLOCK(&sched_ft[i].end);
         cyg_scheduler_unlock();
     }
     show_times(sched_ft, nscheds, "Scheduler lock");
@@ -1549,9 +1558,9 @@ run_sched_tests(void)
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nscheds;  i++) {
         cyg_scheduler_lock();
-        HAL_CLOCK_READ(&sched_ft[i].start);
+        READ_CLOCK(&sched_ft[i].start);
         cyg_scheduler_unlock();
-        HAL_CLOCK_READ(&sched_ft[i].end);
+        READ_CLOCK(&sched_ft[i].end);
     }
     show_times(sched_ft, nscheds, "Scheduler unlock [0 threads]");
 
@@ -1571,9 +1580,9 @@ run_sched_tests(void)
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nscheds;  i++) {
         cyg_scheduler_lock();
-        HAL_CLOCK_READ(&sched_ft[i].start);
+        READ_CLOCK(&sched_ft[i].start);
         cyg_scheduler_unlock();
-        HAL_CLOCK_READ(&sched_ft[i].end);
+        READ_CLOCK(&sched_ft[i].end);
     }
     show_times(sched_ft, nscheds, "Scheduler unlock [1 suspended]");
     for (i = 0;  i < 1;  i++) {
@@ -1596,9 +1605,9 @@ run_sched_tests(void)
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nscheds;  i++) {
         cyg_scheduler_lock();
-        HAL_CLOCK_READ(&sched_ft[i].start);
+        READ_CLOCK(&sched_ft[i].start);
         cyg_scheduler_unlock();
-        HAL_CLOCK_READ(&sched_ft[i].end);
+        READ_CLOCK(&sched_ft[i].end);
     }
     show_times(sched_ft, nscheds, "Scheduler unlock [many suspended]");
     for (i = 0;  i < ntest_threads;  i++) {
@@ -1622,9 +1631,9 @@ run_sched_tests(void)
     wait_for_tick(); // Wait until the next clock tick to minimize aberations
     for (i = 0;  i < nscheds;  i++) {
         cyg_scheduler_lock();
-        HAL_CLOCK_READ(&sched_ft[i].start);
+        READ_CLOCK(&sched_ft[i].start);
         cyg_scheduler_unlock();
-        HAL_CLOCK_READ(&sched_ft[i].end);
+        READ_CLOCK(&sched_ft[i].end);
     }
     show_times(sched_ft, nscheds, "Scheduler unlock [many low prio]");
     for (i = 0;  i < ntest_threads;  i++) {
@@ -1668,7 +1677,7 @@ static void
 
     wait_for_tick();
     for (i = 0;  i < nsamples;  i++) {
-        HAL_CLOCK_READ(&tv[i]);
+        READ_CLOCK(&tv[i]);
     }
     tv0 = 0;
     for (i = 1;  i < nsamples;  i++) {
@@ -1687,17 +1696,17 @@ static void
             tick1 = cyg_current_time();
             if (tick0 != tick1) break;
         }
-        HAL_CLOCK_READ(&tv[i]);
+        READ_CLOCK(&tv[i]);
     }
     tv1 = 0;
     for (i = 0;  i < nsamples;  i++) {
-        tv1 += tv[i] * 1000;
+        tv1 += tv[i] * NSTICK;
     }
     tv1 = tv1 / nsamples;
     tv1 -= overhead;  // Adjust out the cost of getting the timer value
     diag_printf("Clock interrupt took");
     show_ticks_in_us(tv1);
-    diag_printf(" microseconds (%d raw clock ticks)\n", tv1/1000);
+    diag_printf(" microseconds (%d raw clock ticks)\n", tv1/NSTICK);
     enable_clock_latency_measurement();
 
     ticks = cyg_current_time();
@@ -1728,10 +1737,10 @@ static void
 #if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && defined(HAL_CLOCK_LATENCY)
     // Display latency figures in same format as all other numbers
     disable_clock_latency_measurement();
-    clock_ave = (total_clock_latency*1000) / total_clock_interrupts;
+    clock_ave = (total_clock_latency*NSTICK) / total_clock_interrupts;
     show_ticks_in_us(clock_ave);
-    show_ticks_in_us(min_clock_latency*1000);
-    show_ticks_in_us(max_clock_latency*1000);
+    show_ticks_in_us(min_clock_latency*NSTICK);
+    show_ticks_in_us(max_clock_latency*NSTICK);
     show_ticks_in_us(0);
     diag_printf("            Clock/interrupt latency\n\n");
     enable_clock_latency_measurement();    
@@ -1739,10 +1748,10 @@ static void
 
 #if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_DSR_LATENCY) && defined(HAL_CLOCK_LATENCY)
     disable_clock_latency_measurement();    
-    clock_ave = (total_clock_dsr_latency*1000) / total_clock_dsr_calls;
+    clock_ave = (total_clock_dsr_latency*NSTICK) / total_clock_dsr_calls;
     show_ticks_in_us(clock_ave);
-    show_ticks_in_us(min_clock_dsr_latency*1000);
-    show_ticks_in_us(max_clock_dsr_latency*1000);
+    show_ticks_in_us(min_clock_dsr_latency*NSTICK);
+    show_ticks_in_us(max_clock_dsr_latency*NSTICK);
     show_ticks_in_us(0);
     diag_printf("            Clock DSR latency\n\n");
     enable_clock_latency_measurement();
diff --git a/packages/language/c/libc/i18n/current/ChangeLog b/packages/language/c/libc/i18n/current/ChangeLog
--- a/packages/language/c/libc/i18n/current/ChangeLog
+++ b/packages/language/c/libc/i18n/current/ChangeLog
@@ -1,3 +1,9 @@
+2012-03-19  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+            Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* tests/i18nmb.c (main): Fix compiler warnings about variables are
+	set but not used. Enter CYGBLD_ATTRIB_UNUSED.
+
 2009-01-26  Jonathan Larmour  <jifl@eCosCentric.com>
 
 	* tests/ctype.c: Allow to run if CYGPKG_LIBC_STARTUP isn't there.
diff --git a/packages/language/c/libc/i18n/current/tests/i18nmb.c b/packages/language/c/libc/i18n/current/tests/i18nmb.c
--- a/packages/language/c/libc/i18n/current/tests/i18nmb.c
+++ b/packages/language/c/libc/i18n/current/tests/i18nmb.c
@@ -221,12 +221,10 @@ main( int argc, char *argv[] )
   wchar_t wcbuff[100];
   char buff[100];
   
-  char *ptr, *locale;
-  int result, i, j, k;
+  char *ptr, *locale CYGBLD_ATTRIB_UNUSED;
+  int result, i, j, k CYGBLD_ATTRIB_UNUSED;
   wchar_t *wcptr;
 
-  k=0; locale=NULL; // silence warnings
-  
   CYG_TEST_INIT();
   
   CYG_TEST_INFO( "Starting tests from testcase " __FILE__ " for C library "
diff --git a/packages/language/c/libc/startup/current/ChangeLog b/packages/language/c/libc/startup/current/ChangeLog
--- a/packages/language/c/libc/startup/current/ChangeLog
+++ b/packages/language/c/libc/startup/current/ChangeLog
@@ -1,3 +1,9 @@
+2012-03-06  Grant Edwards <grant.b.edwards@gmail.com>
+	
+	* src/abort.cxx (abort):
+	* src/exit.cxx (exit): Fix compiler warnings about unused 'rc'
+	variables. [ Bugzilla 1001506 ]
+	
 2007-10-05  Jonathan Larmour  <jifl@eCosCentric.com>
 
 	* src/main.cxx (main): Suspend main thread, rather than exit.
diff --git a/packages/language/c/libc/startup/current/src/abort.cxx b/packages/language/c/libc/startup/current/src/abort.cxx
--- a/packages/language/c/libc/startup/current/src/abort.cxx
+++ b/packages/language/c/libc/startup/current/src/abort.cxx
@@ -75,7 +75,7 @@ abort( void )
     CYG_REPORT_FUNCNAME( "abort" );
     
 #if CYGINT_ISO_SIGNAL_IMPL > 0
-    int rc;
+    int rc CYGBLD_ATTRIB_UNUSED;
     
     rc = raise(SIGABRT);
     
diff --git a/packages/language/c/libc/startup/current/src/exit.cxx b/packages/language/c/libc/startup/current/src/exit.cxx
--- a/packages/language/c/libc/startup/current/src/exit.cxx
+++ b/packages/language/c/libc/startup/current/src/exit.cxx
@@ -87,7 +87,7 @@ exit( int status )
 
 #ifdef CYGSEM_LIBC_EXIT_CALLS_FFLUSH
 
-    int rc;
+    int rc CYGBLD_ATTRIB_UNUSED;
 
     CYG_TRACE0( true, "Calling fflush( NULL )" );
     rc = fflush( NULL );
diff --git a/packages/language/c/libc/stdio/current/ChangeLog b/packages/language/c/libc/stdio/current/ChangeLog
--- a/packages/language/c/libc/stdio/current/ChangeLog
+++ b/packages/language/c/libc/stdio/current/ChangeLog
@@ -1,6 +1,18 @@
+2014-07-03  John Dallaway  <john@dallaway.org.uk>
+
+	* src/common/sprintf.cxx (__sprintf_chk): Implement alias for use
+	with libsupc++ in fortified linux distributions. [ Bugzilla 1001139 ]
+
+2012-02-19  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* src/common/vsnprintf.c: If string truncated (C99 case), apply the
+	null termination in correct place.
+	* tests/sprintf2.c: Fix checks for return values if C99 implementation
+	snprintf() used.
+
 2009-08-20  Uwe Kindler  <uwe_kindler@web.de>
 
-	* cdl/stdio.cdl Added option CYGIMP_LIBC_STDIO_C99_SNPRINTF
+	* cdl/stdio.cdl: Added option CYGIMP_LIBC_STDIO_C99_SNPRINTF
 	for activation of C99 compliant snprintf() return value.
 	* src/output/vfnprintf.cxx: Added optional C99 compliant return
 	value calculation.
@@ -573,7 +585,7 @@ 2000-05-02  Jonathan Larmour  <jlarmour@
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2006, 2009 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2006, 2009, 2014 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/language/c/libc/stdio/current/src/common/sprintf.cxx b/packages/language/c/libc/stdio/current/src/common/sprintf.cxx
--- a/packages/language/c/libc/stdio/current/src/common/sprintf.cxx
+++ b/packages/language/c/libc/stdio/current/src/common/sprintf.cxx
@@ -8,7 +8,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2014 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -40,7 +40,7 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):    jlarmour
-// Contributors: 
+// Contributors: jld
 // Date:         2000-04-20
 // Purpose:     
 // Description: 
@@ -78,4 +78,8 @@ sprintf( char *s, const char *format, ..
     return rc;
 } // sprintf()
 
+externC int
+__sprintf_chk( char *s, const char *format, ... ) __THROW
+    CYGBLD_ATTRIB_ALIAS( sprintf );
+
 // EOF sprintf.cxx
diff --git a/packages/language/c/libc/stdio/current/src/common/vsnprintf.cxx b/packages/language/c/libc/stdio/current/src/common/vsnprintf.cxx
--- a/packages/language/c/libc/stdio/current/src/common/vsnprintf.cxx
+++ b/packages/language/c/libc/stdio/current/src/common/vsnprintf.cxx
@@ -113,6 +113,13 @@ vsnprintf( char *s, size_t size, const c
      */
     if ( (ret >= 0) && ((size_t)ret < size) )
         s[ret] = '\0';
+#ifdef CYGIMP_LIBC_STDIO_C99_SNPRINTF
+    /* C99 case. If no error, and string truncated, apply null termination
+     * in correct place
+     */
+    if ( (ret >= 0) && ((size_t)ret >= size) && (size > 0) )
+        s[size-1] = '\0';
+#endif
     return ret;
 } // vsnprintf()
 
diff --git a/packages/language/c/libc/stdio/current/tests/sprintf2.c b/packages/language/c/libc/stdio/current/tests/sprintf2.c
--- a/packages/language/c/libc/stdio/current/tests/sprintf2.c
+++ b/packages/language/c/libc/stdio/current/tests/sprintf2.c
@@ -136,14 +136,22 @@ test( CYG_ADDRWORD data )
     ret = snprintf(y, 19, "print up to here >< and not this bit" );
     my_strcpy(z, "print up to here >");
     CYG_TEST_PASS_FAIL(my_strcmp(y,z) == 0, "simple snprintf test #1");
+#ifdef CYGIMP_LIBC_STDIO_C99_SNPRINTF
+    CYG_TEST_PASS_FAIL(ret > my_strlen(z),
+#else
     CYG_TEST_PASS_FAIL(ret == my_strlen(z),
+#endif
                        "simple snprintf test #1 return code" );
     
     // Check 4
     ret = snprintf(y, 31, "print a bit of this number: %05d nyer", 1234);
     my_strcpy(z, "print a bit of this number: 01");
     CYG_TEST_PASS_FAIL(my_strcmp(y,z) == 0, "simple snprintf test #2");
+#ifdef CYGIMP_LIBC_STDIO_C99_SNPRINTF
+    CYG_TEST_PASS_FAIL(ret > my_strlen(z),
+#else
     CYG_TEST_PASS_FAIL(ret == my_strlen(z),
+#endif
                        "simple snprintf test #2 return code" );
     
 #ifdef CYGSEM_LIBC_STDIO_PRINTF_FLOATING_POINT
@@ -168,7 +176,11 @@ test( CYG_ADDRWORD data )
     CYG_TEST_PASS_FAIL(my_strcmp(y,z) == 0,
                        "snprintf double test #1");
 
+#ifdef CYGIMP_LIBC_STDIO_C99_SNPRINTF
+    CYG_TEST_PASS_FAIL(ret > my_strlen(z),
+#else
     CYG_TEST_PASS_FAIL(ret == my_strlen(z),
+#endif
                        "snprintf double test #1 return code");
 
 #endif // ifdef CYGSEM_LIBC_STDIO_PRINTF_FLOATING_POINT
diff --git a/packages/language/c/libc/string/current/ChangeLog b/packages/language/c/libc/string/current/ChangeLog
--- a/packages/language/c/libc/string/current/ChangeLog
+++ b/packages/language/c/libc/string/current/ChangeLog
@@ -1,3 +1,8 @@
+2013-06-13  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* tests/memchr.c: Fix compiler warnings for discrediting const pointer.
+	[ Bugzilla 1001865 ]
+
 2010-05-10  Ross Younger  <wry@ecoscentric.com>
 
 	* include/string.h: Declare strnlen.
diff --git a/packages/language/c/libc/string/current/tests/memchr.c b/packages/language/c/libc/string/current/tests/memchr.c
--- a/packages/language/c/libc/string/current/tests/memchr.c
+++ b/packages/language/c/libc/string/current/tests/memchr.c
@@ -75,7 +75,8 @@ void cyg_user_start(void)
 #endif
 {
     char x[] = "Your feeble skills are no match for the power of "
-               "the dark side!";
+          "the dark side!";
+    char x0[] = "";
     void *ret;
 
     CYG_TEST_INIT();
@@ -104,7 +105,7 @@ void cyg_user_start(void)
     CYG_TEST_PASS_FAIL( ret == NULL, "Boundary test 2" );
 
     // Check 6 (boundary condition)
-    ret = memchr( (void *)"", (int)'\0', 0 );
+    ret = memchr(x0, (int)'\0', 0 );
     CYG_TEST_PASS_FAIL( ret == NULL, "Boundary test 3" );
 
 //    CYG_TEST_NA("Testing is not applicable to this configuration");
diff --git a/packages/language/c/libm/current/ChangeLog b/packages/language/c/libm/current/ChangeLog
--- a/packages/language/c/libm/current/ChangeLog
+++ b/packages/language/c/libm/current/ChangeLog
@@ -1,3 +1,129 @@
+2013-08-25  Ilija Kocho <ilijak@siva.com.mk>
+
+	* src/complex/cabs.c, src/complex/casinf.c, src/complex/ccosh.c, src/complex/cimagf.c,
+	* src/complex/cprojf.c, src/complex/ctan.c, src/complex/cabsf.c, src/complex/casinh.c,
+	* src/complex/ccoshf.c, src/complex/clog.c, src/complex/creal.c, src/complex/ctanf.c,
+	* src/complex/cacos.c, src/complex/casinhf.c, src/complex/cephes_subr.c,
+	* src/complex/clogf.c, src/complex/crealf.c, src/complex/ctanh.c, src/complex/cacosf.c,
+	* src/complex/catan.c, src/complex/cephes_subrf.c, src/complex/src/complex.tex,
+	* src/complex/csin.c, src/complex/ctanhf.c, src/complex/cacosh.c, src/complex/catanf.c,
+	* src/complex/cephes_subrf.h src/complex/conj.c, src/complex/csinf.c,
+	* src/complex/cacoshf.c, src/complex/catanh.c, src/complex/cephes_subr.h
+	* src/complex/conjf.c, src/complex/csinh.c, src/complex/carg.c, src/complex/catanhf.c,
+	* src/complex/cexp.c, src/complex/cpow.c, src/complex/csinhf.c, src/complex/cargf.c,
+	* src/complex/ccos.c, src/complex/cexpf.c, src/complex/cpowf.c, src/complex/csqrt.c,
+	* src/complex/casin.c, src/complex/ccosf.c, src/complex/cimag.c, src/complex/cproj.c,
+	* src/complex/csqrtf.c,
+	* include/src/complex.h:
+
+	Add: Complex number header and library (single and double precision floating point),
+	port from Newlib. [ Bugzilla 1001539 ]
+
+2013-08-25  Visar Zejnullahu <visar.siva.mk>
+            Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/compat.cdl, cdl/libm.cdl, include/complex.h, include/math.h,
+	* src/float/ieee754-api/wf_acos.c, src/float/ieee754-api/wf_acosh.c,
+	* src/float/ieee754-api/wf_asin.c, src/float/ieee754-api/wf_atan2.c,
+	* src/float/ieee754-api/wf_atanh.c, src/float/ieee754-api/wf_cosh.c,
+	* src/float/ieee754-api/wf_exp.c, src/float/ieee754-api/wf_fmod.c,
+	* src/float/ieee754-api/wf_gamma.c, src/float/ieee754-api/wf_gamma_r.c,
+	* src/float/ieee754-api/wf_hypot.c, src/float/ieee754-api/wf_j0.c,
+	* src/float/ieee754-api/wf_j1.c, src/float/ieee754-api/wf_jn.c,
+	* src/float/ieee754-api/wf_lgamma.c, src/float/ieee754-api/wf_lgamma_r.c,
+	* src/float/ieee754-api/wf_log10.c, src/float/ieee754-api/wf_log.c,
+	* src/float/ieee754-api/wf_pow.c, src/float/ieee754-api/wf_remainder.c,
+	* src/float/ieee754-api/wf_scalb.c, src/float/ieee754-api/wf_sinh.c,
+	* src/float/ieee754-api/wf_sqrt.c, 
+	* src/float/ieee754-core/ef_acos.c, src/float/ieee754-core/ef_acosh.c,
+	* src/float/ieee754-core/ef_asin.c, src/float/ieee754-core/ef_atan2.c,
+	* src/float/ieee754-core/ef_atanh.c, src/float/ieee754-core/ef_cosh.c,
+	* src/float/ieee754-core/ef_exp.c, src/float/ieee754-core/ef_fmod.c,
+	* src/float/ieee754-core/ef_gamma.c, src/float/ieee754-core/ef_gamma_r.c,
+	* src/float/ieee754-core/ef_hypot.c, src/float/ieee754-core/ef_j0.c,
+	* src/float/ieee754-core/ef_j1.c, src/float/ieee754-core/ef_jn.c,
+	* src/float/ieee754-core/ef_lgamma.c, src/float/ieee754-core/ef_lgamma_r.c,
+	* src/float/ieee754-core/ef_log10.c, src/float/ieee754-core/ef_log.c,
+	* src/float/ieee754-core/ef_pow.c, src/float/ieee754-core/ef_remainder.c,
+	* src/float/ieee754-core/ef_rem_pio2.c, src/float/ieee754-core/ef_scalb.c,
+	* src/float/ieee754-core/ef_sinh.c, src/float/ieee754-core/ef_sqrt.c,
+	* src/float/internal/kf_cos.c, src/float/internal/kf_rem_pio2.c,
+	* src/float/internal/kf_sin.c, src/float/internal/kf_tan.c,
+	* src/float/portable-api/sf_asinh.c, src/float/portable-api/sf_atan.c,
+	* src/float/portable-api/sf_cbrt.c, src/float/portable-api/sf_ceil.c,
+	* src/float/portable-api/sf_copysign.c, src/float/portable-api/sf_cos.c,
+	* src/float/portable-api/sf_erf.c, src/float/portable-api/sf_expm1.c,
+	* src/float/portable-api/sf_fabs.c, src/float/portable-api/sf_finite.c,
+	* src/float/portable-api/sf_floor.c, src/float/portable-api/sf_frexp.c,
+	* src/float/portable-api/sf_ilogb.c, src/float/portable-api/sf_isnan.c,
+	* src/float/portable-api/sf_ldexp.c, src/float/portable-api/sf_log1p.c,
+	* src/float/portable-api/sf_logb.c, src/float/portable-api/sf_modf.c,
+	* src/float/portable-api/sf_nextafter.c, src/float/portable-api/sf_rint.c,
+	* src/float/portable-api/sf_scalbn.c, src/float/portable-api/sf_significand.c,
+	* src/float/portable-api/sf_sin.c, src/float/portable-api/sf_tan.c,
+	* src/float/portable-api/sf_tanh.c,
+	* src/mathincl/fdlibm.h,
+	* tests/vector_support.h,
+	* tests/vectors/acosf.c, tests/vectors/atan2.h,
+	* tests/vectors/copysignf.h, tests/vectors/expf.h,
+	* tests/vectors/fmodf.c, tests/vectors/ilogbf.h,
+	* tests/vectors/log10f.c, tests/vectors/modff.h, tests/vectors/scalbf.h,
+	* tests/vectors/sqrtf.h, tests/vectors/acosf.h, tests/vectors/atanf.c,
+	* tests/vectors/cosf.c, tests/vectors/exp.h, tests/vectors/fmodf.h,
+	* tests/vectors/isnanf.c, tests/vectors/log10f.h, tests/vectors/modf.h,
+	* tests/vectors/scalbnf.c, tests/vectors/sqrt.h, tests/vectors/acos.h,
+	* tests/vectors/atanf.h, tests/vectors/cosf.h, tests/vectors/expm1f.c,
+	* tests/vectors/fmod.h, tests/vectors/isnanf.h, tests/vectors/log10.h,
+	* tests/vectors/nextafterf.c, tests/vectors/scalbnf.h, tests/vectors/tanf.c,
+	* tests/vectors/acoshf.c, tests/vectors/atan.h, tests/vectors/cos.h,
+	* tests/vectors/expm1f.h, tests/vectors/frexpf.c, tests/vectors/j0f.c,
+	* tests/vectors/log1pf.c, tests/vectors/nextafterf.h,
+	* tests/vectors/significandf.c, tests/vectors/tanf.h,
+	* tests/vectors/acoshf.h, tests/vectors/atanhf.c, tests/vectors/coshf.c,
+	* tests/vectors/fabsf.c, tests/vectors/frexpf.h, tests/vectors/j0f.h,
+	* tests/vectors/log1pf.h, tests/vectors/powf.c, tests/vectors/significandf.h,
+	* tests/vectors/tan.h, tests/vectors/asinf.c, tests/vectors/atanhf.h,
+	* tests/vectors/coshf.h, tests/vectors/fabsf.h,
+	* tests/vectors/frexpf_visar.h, tests/vectors/j1f.c,
+	* tests/vectors/logbf.c, tests/vectors/powf.h,
+	* tests/vectors/sinf.c, tests/vectors/tanhf.c,
+	* tests/vectors/asinf.h, tests/vectors/cbrtf.c, tests/vectors/cosh.h,
+	* tests/vectors/fabs.h, tests/vectors/frexp.h, tests/vectors/j1f.h,
+	* tests/vectors/logbf.h, tests/vectors/pow.h, tests/vectors/sinf.h,
+	* tests/vectors/tanhf.h, tests/vectors/asin.h, tests/vectors/cbrtf.h,
+	* tests/vectors/erfcf.c, tests/vectors/finitef.c,
+	* tests/vectors/gammaf.c, tests/vectors/jnf.c, tests/vectors/logf.c,
+	* tests/vectors/remainderf.c, tests/vectors/sin.h,
+	* tests/vectors/tanh.h, tests/vectors/asinhf.c, tests/vectors/ceilf.c,
+	* tests/vectors/erfcf.h, tests/vectors/finitef.h,
+	* tests/vectors/gammaf.h, tests/vectors/jnf.h,
+	* tests/vectors/logf.h, tests/vectors/remainderf.h,
+	* tests/vectors/sinhf.c, tests/vectors/vector_support_float.h,
+	* tests/vectors/asinhf.h, tests/vectors/ceilf.h, tests/vectors/erff.c,
+	* tests/vectors/floorf.c, tests/vectors/hypotf.c, tests/vectors/ldexpf.c,
+	* tests/vectors/log.h, tests/vectors/rintf.c, tests/vectors/sinhf.h,
+	* tests/vectors/vector_support.h, tests/vectors/atan2f.c,
+	* tests/vectors/ceil.h, tests/vectors/erff.h, tests/vectors/floorf.h,
+	* tests/vectors/hypotf.h, tests/vectors/ldexpf.h,
+	* tests/vectors/modf.c, tests/vectors/rintf.h, tests/vectors/sinh.h,
+	* tests/vectors/atan2f.h, tests/vectors/copysignf.c, tests/vectors/expf.c,
+	* tests/vectors/floor.h, tests/vectors/ilogbf.c, tests/vectors/ldexp.h,
+	* tests/vectors/modff.c, tests/vectors/scalbf.c, tests/vectors/sqrtf.c:
+
+	Add: Single precision floating point library, port from Newlib.
+	[ Bugzilla 1001539 ]
+
+2010-11-11  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/libm.cdl (CYGPKG_LIBM_CFLAGS_ADD): Add a set of parentheses
+	around 'if-then-else' expression, simplified evaluated expression.
+
+2010-05-15  Jonathan Larmour  <jifl@jifvik.org>
+
+	* cdl/libm.cdl (CYGPKG_LIBM_CFLAGS_ADD): Compile with
+	-fno-strict-aliasing to avoid miscompilation. Workaround for a more
+	fundamental problem with CYG_LIBM_HI/LO.
+
 2008-11-20  Jonathan Larmour  <jifl@eCosCentric.com>
 
 	* cdl/libm.cdl: Rename X_TLOSS CDL option to match normal convention.
@@ -813,7 +939,7 @@ Fri Jun  5 07:07:03 1998  Jonathan Larmo
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2007, 2008, 2010, 2013 Free Software Foundation, Inc.
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/language/c/libm/current/cdl/compat.cdl b/packages/language/c/libm/current/cdl/compat.cdl
--- a/packages/language/c/libm/current/cdl/compat.cdl
+++ b/packages/language/c/libm/current/cdl/compat.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2013 Free Software Foundation, Inc.
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -41,7 +41,7 @@
 #
 # Author(s):      jskov
 # Original data:  jlarmour
-# Contributors:
+# Contributors:   ilijak
 # Date:           1999-07-07
 #
 #####DESCRIPTIONEND####
@@ -52,7 +52,7 @@ cdl_interface CYGINT_LIBM_COMPAT {
     requires 1 == CYGINT_LIBM_COMPAT
 }
 
-cdl_option CYGSEM_LIBM_COMPAT_IEEE_ONLY {
+cdl_component CYGSEM_LIBM_COMPAT_IEEE_ONLY {
     display       "IEEE-only"
     default_value 0
     implements    CYGINT_LIBM_COMPAT
@@ -66,6 +66,19 @@ cdl_option CYGSEM_LIBM_COMPAT_IEEE_ONLY 
         modes. If not defined, the math library can be
         set at run-time to any of the supported
         compatibility modes."
+
+    cdl_option CYGSEM_LIBM_IEEE_API_INLINE {
+        display    "Inline IEEE754 API wrappers"
+        default_value 0
+
+        description "
+            IEEE754 API functions are just wrappers for
+            core functions. This introduces indirection which can can be
+            avoided by inlining. This will also prevent GCC from rendering
+            these functions as builtin. The HAL can override for a set of functions
+            by providing a list of builtin functions."
+    }
+
 }
 
 cdl_component CYGNUM_LIBM_COMPATIBILITY {
@@ -83,7 +96,7 @@ cdl_component CYGNUM_LIBM_COMPATIBILITY 
         you choose which mode should be the default."
 
     cdl_option CYGNUM_LIBM_COMPAT_DEFAULT {
-      	display       "Numeric representation"
+	display       "Numeric representation"
 	flavor        data
 	calculated   { \
             CYGNUM_LIBM_COMPATIBILITY == "POSIX" ? "CYGNUM_LIBM_COMPAT_POSIX" :\
@@ -97,6 +110,16 @@ cdl_component CYGNUM_LIBM_COMPATIBILITY 
 	    mode for numeric representation in terms of the values used
 	    to set that mode at run-time."
     }
+
+    cdl_option CYGOPT_LIBM_COMPAT_POSIX_IEEE {
+        display       "POSIX return NaN for out-of-domain argument."
+        active_if   { CYGNUM_LIBM_COMPATIBILITY == "POSIX" }
+        default_value 0
+        description   "Later POSIX specification states that functions
+            may return either NaN (like IEEE), or implementation defined
+            value when argument is out of domain. For backward compatibility
+            default value is set to 0."
+    }
 }
 
 cdl_option CYGFUN_LIBM_SVID3_scalb {
diff --git a/packages/language/c/libm/current/cdl/libm.cdl b/packages/language/c/libm/current/cdl/libm.cdl
--- a/packages/language/c/libm/current/cdl/libm.cdl
+++ b/packages/language/c/libm/current/cdl/libm.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2010, 2012, 2013 Free Software Foundation, Inc.
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -41,7 +41,7 @@
 #
 # Author(s):      bartv
 # Original data:  jlarmour
-# Contributors:
+# Contributors:   visar, ilijak
 # Date:           1999-06-13
 #
 #####DESCRIPTIONEND####
@@ -56,38 +56,85 @@ cdl_package CYGPKG_LIBM {
         containing many useful functions for mathematical
         calculations."
 
-    compile       misc/matherr.c misc/standard.c misc/compatmode.cxx          \
-                  misc/infconst.c                                             \
-                                                                              \
-                  double/ieee754-core/e_acos.c double/ieee754-core/e_asin.c   \
-                  double/ieee754-core/e_atan2.c double/ieee754-core/e_cosh.c  \
-                  double/ieee754-core/e_exp.c double/ieee754-core/e_fmod.c    \
-                  double/ieee754-core/e_log.c double/ieee754-core/e_log10.c   \
-                  double/ieee754-core/e_pow.c                                 \
-                  double/ieee754-core/e_rem_pio2.c                            \
-                  double/ieee754-core/e_scalb.c double/ieee754-core/e_sinh.c  \
-                  double/ieee754-core/e_sqrt.c                                \
-                                                                              \
-                  double/ieee754-api/w_acos.c double/ieee754-api/w_asin.c     \
-                  double/ieee754-api/w_atan2.c double/ieee754-api/w_cosh.c    \
-                  double/ieee754-api/w_exp.c double/ieee754-api/w_fmod.c      \
-                  double/ieee754-api/w_log.c double/ieee754-api/w_log10.c     \
-                  double/ieee754-api/w_pow.c double/ieee754-api/w_scalb.c     \
-                  double/ieee754-api/w_sinh.c double/ieee754-api/w_sqrt.c     \
-                                                                              \
-                  double/internal/k_cos.c double/internal/k_rem_pio2.c        \
-                  double/internal/k_sin.c double/internal/k_tan.c             \
-                                                                              \
-                  double/portable-api/s_atan.c double/portable-api/s_ceil.c   \
-                  double/portable-api/s_copysign.c                            \
-                  double/portable-api/s_cos.c double/portable-api/s_expm1.c   \
-                  double/portable-api/s_fabs.c double/portable-api/s_finite.c \
-                  double/portable-api/s_floor.c double/portable-api/s_frexp.c \
-                  double/portable-api/s_isnan.c double/portable-api/s_ldexp.c \
-                  double/portable-api/s_rint.c double/portable-api/s_scalbn.c \
-                  double/portable-api/s_sin.c double/portable-api/s_tan.c     \
-                  double/portable-api/s_modf.c double/portable-api/s_tanh.c
-
+        compile   misc/matherr.c misc/standard.c misc/standard_float.c                  \
+                  misc/compatmode.cxx misc/infconst.c                                   \
+                                                                                        \
+                  double/ieee754-core/e_acos.c double/ieee754-core/e_asin.c             \
+                  double/ieee754-core/e_atan2.c double/ieee754-core/e_cosh.c            \
+                  double/ieee754-core/e_exp.c double/ieee754-core/e_fmod.c              \
+                  double/ieee754-core/e_log.c double/ieee754-core/e_log10.c             \
+                  double/ieee754-core/e_pow.c                                           \
+                  double/ieee754-core/e_rem_pio2.c                                      \
+                  double/ieee754-core/e_scalb.c double/ieee754-core/e_sinh.c            \
+                  double/ieee754-core/e_sqrt.c double/ieee754-core/e_hypot.c            \
+                                                                                        \
+                  double/ieee754-api/w_acos.c double/ieee754-api/w_asin.c               \
+                  double/ieee754-api/w_atan2.c double/ieee754-api/w_cosh.c              \
+                  double/ieee754-api/w_exp.c double/ieee754-api/w_fmod.c                \
+                  double/ieee754-api/w_log.c double/ieee754-api/w_log10.c               \
+                  double/ieee754-api/w_pow.c double/ieee754-api/w_scalb.c               \
+                  double/ieee754-api/w_sinh.c double/ieee754-api/w_sqrt.c               \
+                  double/ieee754-api/w_hypot.c                                          \
+                  double/ieee754-core/e_gamma.c double/ieee754-api/w_gamma.c            \
+                  double/ieee754-core/e_gamma_r.c double/ieee754-api/w_gamma_r.c        \
+                  double/ieee754-core/e_lgamma.c double/ieee754-api/w_lgamma.c          \
+                  double/ieee754-core/e_lgamma_r.c double/ieee754-api/w_lgamma_r.c      \
+                                                                                        \
+                  double/internal/k_cos.c double/internal/k_rem_pio2.c                  \
+                  double/internal/k_sin.c double/internal/k_tan.c                       \
+                                                                                        \
+                  float/internal/kf_cos.c float/internal/kf_sin.c                       \
+                  float/internal/kf_rem_pio2.c float/internal/kf_tan.c                  \
+                                                                                        \
+                  double/portable-api/s_atan.c double/portable-api/s_ceil.c             \
+                  double/portable-api/s_copysign.c                                      \
+                  double/portable-api/s_cos.c double/portable-api/s_expm1.c             \
+                  double/portable-api/s_fabs.c double/portable-api/s_finite.c           \
+                  double/portable-api/s_floor.c double/portable-api/s_frexp.c           \
+                  double/portable-api/s_isnan.c double/portable-api/s_ldexp.c           \
+                  double/portable-api/s_rint.c double/portable-api/s_scalbn.c           \
+                  double/portable-api/s_sin.c double/portable-api/s_tan.c               \
+                  double/portable-api/s_modf.c double/portable-api/s_tanh.c             \
+                                                                                        \
+                  float/ieee754-core/ef_rem_pio2.c                                      \
+                  float/ieee754-core/ef_sqrt.c   float/ieee754-api/wf_sqrt.c            \
+                  float/ieee754-core/ef_pow.c    float/ieee754-api/wf_pow.c             \
+                  float/ieee754-core/ef_exp.c    float/ieee754-api/wf_exp.c             \
+                  float/ieee754-core/ef_asin.c   float/ieee754-api/wf_asin.c            \
+                  float/ieee754-core/ef_log.c   float/ieee754-api/wf_log.c              \
+                  float/ieee754-core/ef_log10.c   float/ieee754-api/wf_log10.c          \
+                  float/ieee754-core/ef_hypot.c float/ieee754-api/wf_hypot.c            \
+                  float/ieee754-core/ef_fmod.c   float/ieee754-api/wf_fmod.c            \
+                  float/ieee754-core/ef_remainder.c   float/ieee754-api/wf_remainder.c  \
+                  float/ieee754-core/ef_scalb.c   float/ieee754-api/wf_scalb.c          \
+                  float/ieee754-core/ef_acos.c   float/ieee754-api/wf_acos.c            \
+                  float/ieee754-core/ef_atan2.c  float/ieee754-api/wf_atan2.c           \
+                  float/ieee754-core/ef_acosh.c   float/ieee754-api/wf_acosh.c          \
+                  float/ieee754-core/ef_atanh.c   float/ieee754-api/wf_atanh.c          \
+                  float/ieee754-core/ef_cosh.c   float/ieee754-api/wf_cosh.c            \
+                  float/ieee754-core/ef_j0.c   float/ieee754-api/wf_j0.c                \
+                  float/ieee754-core/ef_j1.c   float/ieee754-api/wf_j1.c                \
+                  float/ieee754-core/ef_jn.c   float/ieee754-api/wf_jn.c                \
+                  float/ieee754-core/ef_sinh.c   float/ieee754-api/wf_sinh.c            \
+                  float/portable-api/sf_asinh.c float/portable-api/sf_ilogb.c           \
+                  float/portable-api/sf_copysign.c                                      \
+                  float/portable-api/sf_sin.c                                           \
+                  float/portable-api/sf_finite.c float/portable-api/sf_erf.c            \
+                  float/portable-api/sf_isnan.c float/portable-api/sf_floor.c           \
+                  float/portable-api/sf_modf.c                                          \
+                  float/portable-api/sf_atan.c                                          \
+                  float/portable-api/sf_ldexp.c                                         \
+                  float/portable-api/sf_nextafter.c                                     \
+                  float/portable-api/sf_tan.c float/portable-api/sf_cbrt.c              \
+                  float/portable-api/sf_expm1.c                                         \
+                  float/portable-api/sf_frexp.c                                         \
+                  float/portable-api/sf_log1p.c  float/portable-api/sf_rint.c           \
+                  float/portable-api/sf_tanh.c float/portable-api/sf_ceil.c             \
+                  float/portable-api/sf_fabs.c                                          \
+                  float/portable-api/sf_logb.c                                          \
+                  float/portable-api/sf_scalbn.c                                        \
+                  float/portable-api/sf_cos.c                                           \
+                  float/portable-api/sf_significand.c
 
     # COMPATIBILITY-MODE RELATED CONFIGURATION OPTIONS
     cdl_component CYGPKG_LIBM_COMPATIBILITY {
@@ -216,6 +263,43 @@ cdl_package CYGPKG_LIBM {
         puts $::cdl_header "/****** proc output end ******/"
     }
 
+    cdl_component CYGPKG_COMPLEX {
+        display       "Complex"
+        flavor        bool
+        default_value 1
+
+        description "
+            Complex library provides support for some basic operations
+            on complex numbers as well as mathematical functions in
+            complex domain."
+
+            compile   complex/cabs.c complex/cabsf.c     \
+            complex/carg.c complex/cargf.c               \
+                                                         \
+            complex/creal.c complex/crealf.c             \
+            complex/cimag.c complex/cimagf.c             \
+            complex/conj.c complex/conjf.c               \
+                                                         \
+            complex/cacos.c complex/cacosf.c             \
+            complex/cacosh.c complex/cacoshf.c           \
+            complex/casin.c complex/casinf.c             \
+            complex/casinh.c complex/casinhf.c           \
+            complex/catan.c complex/catanf.c             \
+            complex/catanh.c complex/catanhf.c           \
+            complex/ccos.c complex/ccosf.c               \
+            complex/ccosh.c complex/ccoshf.c             \
+            complex/cephes_subr.c complex/cephes_subrf.c \
+            complex/cexp.c complex/cexpf.c               \
+            complex/clog.c complex/clogf.c               \
+            complex/cpow.c complex/cpowf.c               \
+            complex/cproj.c complex/cprojf.c             \
+            complex/csin.c complex/csinf.c               \
+            complex/csinh.c complex/csinhf.c             \
+            complex/csqrt.c complex/csqrtf.c             \
+            complex/ctan.c complex/ctanf.c               \
+            complex/ctanh.c complex/ctanhf.c
+    }
+
     cdl_component CYGPKG_LIBM_OPTIONS {
         display "Math library build options"
         flavor  none
@@ -229,7 +313,8 @@ cdl_package CYGPKG_LIBM {
             display "Additional compiler flags"
             flavor  data
             no_define
-            default_value { ((0 == CYGPKG_HAL_I386) && (0 == CYGPKG_HAL_SYNTH_I386)) ? "" : "-ffloat-store" }
+            default_value { "-fno-strict-aliasing" . \
+                                ((!CYGPKG_HAL_I386 && !CYGPKG_HAL_SYNTH_I386) ? "" : " -ffloat-store") }
             description   "
                 This option modifies the set of compiler flags for
                 building the math library. These flags are used in addition
@@ -251,9 +336,30 @@ cdl_package CYGPKG_LIBM {
             display "Math library tests"
             flavor  data
             no_define
-            calculated { "tests/vectors/acos tests/vectors/asin tests/vectors/atan tests/vectors/atan2 tests/vectors/ceil tests/vectors/cos tests/vectors/cosh tests/vectors/exp tests/vectors/fabs tests/vectors/floor tests/vectors/fmod tests/vectors/frexp tests/vectors/ldexp tests/vectors/log tests/vectors/log10 tests/vectors/modf tests/vectors/pow tests/vectors/sin tests/vectors/sinh tests/vectors/sqrt tests/vectors/tan tests/vectors/tanh" }
+            calculated { "tests/vectors/acos tests/vectors/asin             \
+                tests/vectors/cos tests/vectors/cosh                        \
+                tests/vectors/sin tests/vectors/sinh                        \
+                tests/vectors/atan tests/vectors/atan2                      \
+                tests/vectors/tan tests/vectors/tanh                        \
+                tests/vectors/sqrt tests/vectors/pow                        \
+                tests/vectors/ceil tests/vectors/floor                      \
+                tests/vectors/fabs tests/vectors/fmod                       \
+                tests/vectors/frexp tests/vectors/ldexp                     \
+                tests/vectors/exp tests/vectors/log tests/vectors/log10     \
+                                                                            \
+                tests/vectors/acosf tests/vectors/asinf                     \
+                tests/vectors/cosf tests/vectors/coshf                      \
+                tests/vectors/sinf tests/vectors/sinhf                      \
+                tests/vectors/atanf tests/vectors/atan2f                    \
+                tests/vectors/tanf tests/vectors/tanhf                      \
+                tests/vectors/hypotf tests/vectors/sqrtf tests/vectors/powf \
+                tests/vectors/floorf tests/vectors/ceilf                    \
+                tests/vectors/fabsf tests/vectors/fmodf                     \
+                tests/vectors/frexpf tests/vectors/ldexpf                   \
+                tests/vectors/expf tests/vectors/logf tests/vectors/log10f "
+            }
             description   "
-                This option specifies the set of tests for the math library."
+               this option specifies the set of tests for the math library."
         }
     }
 }
diff --git a/packages/language/c/libm/current/include/complex.h b/packages/language/c/libm/current/include/complex.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/include/complex.h
@@ -0,0 +1,202 @@
+#ifndef	CYGONCE_COMPLEX_H
+#define	CYGONCE_COMPLEX_H
+
+//===========================================================================
+//
+//      complex.h
+//
+//      Standard complex number functions conforming to ANSI and other standards
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Based on:    see below
+// Contributors:
+// Date:        2013-06-05
+// Purpose:
+// Description: Standard complex number mathematical functions.
+//
+// Usage:       #include <complex.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// This file was derived from a file with following copyright
+
+/* $NetBSD: complex.h,v 1.3 2010/09/15 16:11:30 christos Exp $ */
+
+/*
+ * Written by Matthias Drochner.
+ * Public domain.
+ */
+
+#ifndef _COMPLEX_H
+#define _COMPLEX_H
+#endif
+
+#define complex _Complex
+#define _Complex_I (1.0fi)
+#define I _Complex_I
+
+// 7.3.5 Trigonometric functions
+// 7.3.5.1 The cacos functions
+double complex cacos(double complex);
+float complex cacosf(float complex);
+
+// 7.3.5.2 The casin functions
+double complex casin(double complex);
+float complex casinf(float complex);
+
+// 7.3.5.1 The catan functions
+double complex catan(double complex);
+float complex catanf(float complex);
+
+// 7.3.5.1 The ccos functions
+double complex ccos(double complex);
+float complex ccosf(float complex);
+
+// 7.3.5.1 The csin functions
+double complex csin(double complex);
+float complex csinf(float complex);
+
+// 7.3.5.1 The ctan functions
+double complex ctan(double complex);
+float complex ctanf(float complex);
+
+// 7.3.6 Hyperbolic functions
+// 7.3.6.1 The cacosh functions
+double complex cacosh(double complex);
+float complex cacoshf(float complex);
+
+// 7.3.6.2 The casinh functions
+double complex casinh(double complex);
+float complex casinhf(float complex);
+
+// 7.3.6.3 The catanh functions
+double complex catanh(double complex);
+float complex catanhf(float complex);
+
+// 7.3.6.4 The ccosh functions
+double complex ccosh(double complex);
+float complex ccoshf(float complex);
+
+// 7.3.6.5 The csinh functions
+double complex csinh(double complex);
+float complex csinhf(float complex);
+
+// 7.3.6.6 The ctanh functions
+double complex ctanh(double complex);
+float complex ctanhf(float complex);
+
+// 7.3.7 Exponential and logarithmic functions
+// 7.3.7.1 The cexp functions
+double complex cexp(double complex);
+float complex cexpf(float complex);
+
+// 7.3.7.2 The clog functions
+double complex clog(double complex);
+float complex clogf(float complex);
+
+// 7.3.9 Manipulation functions
+// 7.3.9.2 The cimag functions
+double cimag(double complex);
+float cimagf(float complex);
+//long double cimagl(long double complex);
+
+// 7.3.9.3 The conj functions
+double complex conj(double complex);
+float complex conjf(float complex);
+//long double complex conjl(long double complex);
+
+// 7.3.9.4 The cproj functions
+double complex cproj(double complex);
+float complex cprojf(float complex);
+//long double complex cprojl(long double complex);
+
+// 7.3.9.5 The creal functions
+double creal(double complex);
+float crealf(float complex);
+//long double creall(long double complex);
+
+// 7.3.9.1 The carg functions
+#ifdef CYGSEM_LIBM_IEEE_API_INLINE
+CYGBLD_FORCE_INLINE double
+carg(double complex z)
+{
+	return atan2( cimag(z) , creal(z) );
+}
+
+CYGBLD_FORCE_INLINE float
+cargf(float complex z)
+{
+	return atan2f( cimagf(z) , crealf(z) );
+}
+#else
+double carg(double complex);
+float cargf(float complex);
+#endif
+
+// 7.3.8 Power and absolute-value functions
+// 7.3.8.1 The cabs functions
+#ifdef CYGSEM_LIBM_IEEE_API_INLINE
+CYGBLD_FORCE_INLINE double
+cabs(double complex z)
+{
+	return hypot( creal(z) , cimag(z) );
+}
+
+CYGBLD_FORCE_INLINE float
+cabsf(float complex z)
+{
+	return hypotf( crealf(z) , cimagf(z) );
+}
+#else
+double cabs(double complex) ;
+float cabsf(float complex) ;
+#endif
+
+// 7.3.8.2 The cpow functions
+double complex cpow(double complex, double complex);
+float complex cpowf(float complex, float complex);
+
+// 7.3.8.3 The csqrt functions
+double complex csqrt(double complex);
+float complex csqrtf(float complex);
+
+#endif //CYGONCE_COMPLEX_H
+
+// End of complex.h
diff --git a/packages/language/c/libm/current/include/math.h b/packages/language/c/libm/current/include/math.h
--- a/packages/language/c/libm/current/include/math.h
+++ b/packages/language/c/libm/current/include/math.h
@@ -10,7 +10,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2012, 2013 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -42,9 +42,9 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):   jlarmour
-// Contributors:  jlarmour
+// Contributors:  jlarmour, visar, ilijak
 // Date:        1998-02-13
-// Purpose:     
+// Purpose:
 // Description: Standard mathematical functions. These can be
 //              configured to conform to ANSI section 7.5. There are also
 //              a number of extensions conforming to IEEE-754 and behaviours
@@ -57,33 +57,150 @@
 
 // CONFIGURATION
 
+#include <pkgconf/system.h> // System configuration header
 #include <pkgconf/libm.h>   // Configuration header
 
 // Include the Math library?
-#ifdef CYGPKG_LIBM     
+#ifdef CYGPKG_LIBM
+
+#ifdef CYGBLD_HAL_LIBM_H
+# include CYGBLD_HAL_LIBM_H
+#endif
+
+// Inline IEEE754 API macros
+#define CYGBLD_LIBM_INLINE CYGBLD_FORCE_INLINE
+
+#ifdef CYGSEM_LIBM_IEEE_API_INLINE
+
+#define CYGDCL_LIBM_IEEE_API_INLINE_F(_fun)        \
+externC double __ieee754_##_fun(double);           \
+CYGBLD_LIBM_INLINE double _fun(double x)           \
+{                                                  \
+    return __ieee754_##_fun(x);                    \
+}                                                  \
+externC float __ieee754_##_fun##f(float);          \
+CYGBLD_LIBM_INLINE float _fun##f(float x)          \
+{                                                  \
+    return __ieee754_##_fun##f(x);                 \
+}
+
+#define CYGDCL_LIBM_IEEE_API_INLINE_FF(_fun)       \
+externC double __ieee754_##_fun(double, double);   \
+CYGBLD_LIBM_INLINE double _fun(double x, double y) \
+{                                                  \
+    return __ieee754_##_fun(x, y);                 \
+}                                                  \
+externC float __ieee754_##_fun##f(float, float);   \
+CYGBLD_LIBM_INLINE float _fun##f(float x, float y) \
+{                                                  \
+    return __ieee754_##_fun##f(x, y);              \
+}
+
+#define CYGDCL_LIBM_IEEE_API_INLINE_IF(_fun)       \
+externC double __ieee754_##_fun(int, double);      \
+CYGBLD_LIBM_INLINE double _fun(int x, double y)    \
+{                                                  \
+    return __ieee754_##_fun(x, y);                 \
+}                                                  \
+externC float __ieee754_##_fun##f(int, float);     \
+CYGBLD_LIBM_INLINE float _fun##f(int x, float y)   \
+{                                                  \
+    return __ieee754_##_fun##f(x, y);              \
+}
+
+#define CYGDCL_LIBM_IEEE_API_INLINE_FIP(_fun)      \
+externC double __ieee754_##_fun(double, int *);    \
+CYGBLD_LIBM_INLINE double _fun(double x, int *y)   \
+{                                                  \
+    return __ieee754_##_fun(x, y);                 \
+}                                                  \
+externC float __ieee754_##_fun##f(float, int*);    \
+CYGBLD_LIBM_INLINE float _fun##f(float x, int *y)  \
+{                                                  \
+    return __ieee754_##_fun##f(x, y);              \
+}
+
+#else
+
+#define CYGDCL_LIBM_IEEE_API_INLINE_F(_fun) \
+externC inline double _fun(double);         \
+externC float inline _fun##f(float);
+
+#define CYGDCL_LIBM_IEEE_API_INLINE_FF(_fun) \
+externC inline double _fun(double, double);  \
+externC inline float _fun##f(float, float);
+
+#define CYGDCL_LIBM_IEEE_API_INLINE_IF(_fun) \
+externC inline double _fun(int, double);     \
+externC inline float _fun##f(int, float);
+
+#define CYGDCL_LIBM_IEEE_API_INLINE_FIP(_fun) \
+externC inline double _fun(double, int *);    \
+externC inline float _fun##f(float, int *);
+
+#endif
 
 // INCLUDES
 
 #include <cyg/infra/cyg_type.h>    // Common type definitions and support
 #include <float.h>                 // Properties of FP representation on this
                                    // platform
-#include <sys/ieeefp.h>            // Cyg_libm_ieee_double_shape_type
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_[double|float]_shape_type
 
 // CONSTANT DEFINITIONS
 
+// Useful constants.
+
+#define MAXFLOAT    3.40282347e+38F
+
+#define M_E         2.7182818284590452354
+#define M_LOG2E     1.4426950408889634074
+#define M_LOG10E    0.43429448190325182765
+#define M_LN2       _M_LN2
+#define M_LN10      2.30258509299404568402
+#define M_PI        3.14159265358979323846
+#define M_TWOPI     (M_PI * 2.0)
+#define M_PI_2      1.57079632679489661923
+#define M_PI_4      0.78539816339744830962
+#define M_3PI_4     2.3561944901923448370E0
+#define M_SQRTPI    1.77245385090551602792981
+#define M_1_PI      0.31830988618379067154
+#define M_2_PI      0.63661977236758134308
+#define M_2_SQRTPI  1.12837916709551257390
+#define M_SQRT2     1.41421356237309504880
+#define M_SQRT1_2   0.70710678118654752440
+#define M_LN2LO     1.9082149292705877000E-10
+#define M_LN2HI     6.9314718036912381649E-1
+#define M_SQRT3     1.73205080756887719000
+#define M_IVLN10    0.43429448190325182765   /* 1 / log(10) */
+#define M_LOG2_E    _M_LN2
+#define M_INVLN2    1.4426950408889633870E0  /* 1 / log(2) */
 
 // HUGE_VAL is a positive double (not necessarily representable as a float)
 // representing infinity as specified in ANSI 7.5. cyg_libm_infinity is
 // defined further down
+#if 1
 #define HUGE_VAL        (cyg_libm_infinity.value)
+#define HUGE_VALF       (cyg_libm_float_infinity.value)
 
+#else
+ /* gcc >= 3.3 implicitly defines builtins for HUGE_VALx values.  */
+
+# ifndef HUGE_VAL
+#  define HUGE_VAL (__builtin_huge_val())
+# endif
+
+# ifndef HUGE_VALF
+#  define HUGE_VALF (__builtin_huge_valf())
+# endif
+
+#endif /* !gcc >= 3.3  */
 
 #ifndef CYGSYM_LIBM_NO_XOPEN_SVID_NAMESPACE_POLLUTION
 // HUGE is defined in System V Interface Definition 3 (SVID3) as the largest
 // finite single precision number
 #define HUGE            FLT_MAX    // from float.h
 
-
 // Values used in the type field of struct exception below
 
 #define DOMAIN          1
@@ -93,6 +210,9 @@
 #define TLOSS           5
 #define PLOSS           6
 
+#ifndef FP_ILOGBNAN
+# define FP_ILOGBNAN INT_MAX
+#endif
 
 // TYPE DEFINITIONS
 
@@ -106,12 +226,20 @@ struct exception {
     double retval;  // Value to be returned - can be altered by matherr()
 };
 
+struct exceptionf {
+    int type;       // One of DOMAIN, SING, OVERFLOW, UNDERFLOW, TLOSS, PLOSS
+    char *name;     // Name of the function generating the exception
+    float arg1;     // First argument to the function
+    float arg2;     // Second argument to the function
+    float retval;   // Value to be returned - can be altered by matherr()
+};
+
 #endif // ifndef CYGSYM_LIBM_NO_XOPEN_SVID_NAMESPACE_POLLUTION
 
-
 // GLOBALS
 
 externC const Cyg_libm_ieee_double_shape_type cyg_libm_infinity;
+externC const Cyg_libm_ieee_float_shape_type cyg_libm_float_infinity;
 
 //===========================================================================
 // FUNCTION PROTOTYPES
@@ -178,84 +306,108 @@ externC int signgam;
 
 // Trigonometric functions - ANSI 7.5.2
 
-externC double
-acos( double );            // arc cosine i.e. inverse cos
+// arc cosine i.e. inverse cos
+CYGDCL_LIBM_IEEE_API_INLINE_F(acos)
 
-externC double
-asin( double );            // arc sine i.e. inverse sin
+// arc sine i.e. inverse sin
+CYGDCL_LIBM_IEEE_API_INLINE_F(asin)
 
 externC double
 atan( double );            // arc tan i.e. inverse tan
 
-externC double
-atan2( double, double );   // arc tan of (first arg/second arg) using signs
-                           // of args to determine quadrant
+externC float
+atanf ( float );
+
+// arc tan of (first arg/second arg) using signs
+// of args to determine quadrant
+CYGDCL_LIBM_IEEE_API_INLINE_FF(atan2)
 
 externC double
 cos( double );             // cosine
 
+externC float
+cosf( float );
+
 externC double
 sin( double );             // sine
 
+externC float
+sinf( float );
+
 externC double
 tan( double );             // tangent
 
+externC float
+tanf ( float );
+
 // Hyperbolic functions - ANSI 7.5.3
 
-externC double
-cosh( double );            // hyperbolic cosine
+// hyperbolic cosine
+CYGDCL_LIBM_IEEE_API_INLINE_F(cosh)
 
-externC double
-sinh( double );            // hyperbolic sine
+// hyperbolic sine
+CYGDCL_LIBM_IEEE_API_INLINE_F(sinh)
 
 externC double
 tanh( double );            // hyperbolic tangent
 
+externC float
+tanhf ( float );
+
 // Exponential and Logarithmic Functions - ANSI 7.5.4
 
-externC double
-exp( double );             // exponent
+CYGDCL_LIBM_IEEE_API_INLINE_F(exp)
 
 externC double
 frexp( double, int * );    // break number into normalized fraction (returned)
                            // and integral power of 2 (second arg)
-
-externC double
-ldexp( double, int );      // multiples number by integral power of 2 
+externC float
+frexpf( float, int * );
 
 externC double
-log( double );             // natural logarithm
+ldexp( double, int );      // multiples number by integral power of 2
+
+externC float
+ldexpf( float, int );
 
-externC double
-log10( double );           // base ten logarithm
+// natural logarithm
+CYGDCL_LIBM_IEEE_API_INLINE_F(log)
+
+// base ten logarithm
+CYGDCL_LIBM_IEEE_API_INLINE_F(log10)
 
 externC double
 modf( double, double * );  // break number into integral and fractional
                            // parts, each of which has same sign as arg.
-                           // It returns signed fractional part, and
-                           // puts integral part in second arg
+externC float              // It returns signed fractional part, and
+modff ( float, float *);   // puts integral part in second arg
 
 // Power Functions - ANSI 7.5.5
 
-externC double
-pow( double, double );     // (1st arg) to the power of (2nd arg)
+// (1st arg) to the power of (2nd arg)
+CYGDCL_LIBM_IEEE_API_INLINE_FF(pow)
 
-externC double
-sqrt( double );            // square root
+// square root
+CYGDCL_LIBM_IEEE_API_INLINE_F(sqrt)
 
 // Nearest integer, absolute value and remainder functions - ANSI 7.5.6
 
 externC double
 ceil( double );            // smallest integer >= arg
+externC float
+ceilf ( float );
 
 externC double
 fabs( double );            // absolute value
+externC float
+fabsf ( float );
 
 externC double
 floor( double );           // largest integer <= arg
+externC float
+floorf ( float );
 
-externC double
-fmod( double, double );    // remainder of (1st arg)/(2nd arg)
+CYGDCL_LIBM_IEEE_API_INLINE_FF(fmod)
 
 //===========================================================================
 // Other standard functions
@@ -263,93 +415,121 @@ fmod( double, double );    // remainder 
 #ifndef CYGSYM_LIBM_NO_XOPEN_SVID_NAMESPACE_POLLUTION
 externC int
 matherr( struct exception * );    // User-overridable error handling - see
-#endif                            // <pkgconf/libm.h> for a discussion
+                                  // <pkgconf/libm.h> for a discussion
+externC int
+matherrf( struct exceptionf * );
+#endif
 
 // FIXME: from here needs to be documented and mentioned as non-ISO
 // Arc Hyperbolic trigonometric functions
 
-externC double
-acosh( double );                  // Arc hyperbolic cos i.e. inverse cosh
+// Arc hyperbolic cos i.e. inverse cosh
+CYGDCL_LIBM_IEEE_API_INLINE_F(acosh)
 
-externC double
-asinh( double );                  // Arc hyperbolic sin i.e. inverse sinh
+// Arc hyperbolic sin i.e. inverse sinh
+CYGDCL_LIBM_IEEE_API_INLINE_F(asinh)
 
-externC double
-atanh( double );                  // Arc hyperbolic tan i.e. inverse tanh
+// Arc hyperbolic tan i.e. inverse tanh
+CYGDCL_LIBM_IEEE_API_INLINE_F(atanh)
 
 // Error functions
 
 externC double                    // Error function, such that
 erf( double );                    // erf(x) = 2/sqrt(pi) * integral from
                                   // 0 to x of e**(-t**2) dt
+externC float
+erff ( float );
 
 externC double                    // Complementary error function - simply
 erfc( double );                   // 1.0 - erf(x)
 
+externC float
+erfcf ( float );
+
 // Gamma functions
 
-externC double                    // Logarithm of the absolute value of the
-lgamma( double );                 // gamma function of the argument. The
-                                  // integer signgam is used to store the
-                                  // sign of the gamma function of the arg
+// Logarithm of the absolute value of the
+// gamma function of the argument. The
+// integer signgam is used to store the
+// sign of the gamma function of the arg
+CYGDCL_LIBM_IEEE_API_INLINE_F(lgamma)
 
-externC double
-lgamma_r( double, int * );        // Re-entrant version of the above, where
-                                  // the user passes the location of signgam
-                                  // as the second argument
+// Re-entrant version of the above, where
+// the user passes the location of signgam
+// as the second argument
+CYGDCL_LIBM_IEEE_API_INLINE_FIP(lgamma_r)
 
-externC double                    // Identical to lgamma()!
-gamma( double );                  // The reasons for this are historical,
-                                  // and may be changed in future standards
-                                  //
-                                  // To get the real gamma function, you should
-                                  // use: l=lgamma(x); g=signgam*exp(l);
-                                  //
-                                  // Do not just do signgam*exp(lgamma(x))
-                                  // as lgamma() modifies signgam
+// Identical to lgamma()!
+// The reasons for this are historical,
+// and may be changed in future standards
+//
+// To get the real gamma function, you should
+// use: l=lgamma(x); g=signgam*exp(l);
+//
+// Do not just do signgam*exp(lgamma(x))
+// as lgamma() modifies signgam
+CYGDCL_LIBM_IEEE_API_INLINE_F(gamma)
 
 externC double
 gamma_r( double, int * );         // Identical to lgamma_r(). See above.
 
+externC float
+gammaf_r( float, int * );
+
 
 // Bessel functions
 
-externC double                    // Zero-th order Bessel function of the
-j0( double );                     // first kind at the ordinate of the argument
+// Zero-th order Bessel function of the
+// first kind at the ordinate of the argument
+CYGDCL_LIBM_IEEE_API_INLINE_F(j0)
 
-externC double                    // First-order Bessel function of the
-j1( double );                     // first kind at the ordinate of the argument
+// First-order Bessel function of the
+// first kind at the ordinate of the argument
+CYGDCL_LIBM_IEEE_API_INLINE_F(j1)
 
-externC double                    // Bessel function of the first kind of the
-jn( int, double );                // order of the first argument at the
-                                  // ordinate of the second argument
+// Bessel function of the first kind of the
+// order of the first argument at the
+// ordinate of the second argument
+CYGDCL_LIBM_IEEE_API_INLINE_IF(jn)
 
 externC double                    // Zero-th order Bessel function of the
 y0( double );                     // second kind at the ordinate of the
-                                  // argument
+
+externC float
+y0f( float );
 
 externC double                    // First-order Bessel function of the
 y1( double );                     // second kind at the ordinate of the
                                   // argument
+externC float
+y1f( float );
 
 externC double                    // Bessel function of the second kind of the
 yn( int, double );                // order of the first argument at the
                                   // ordinate of the second argument
+externC float
+ynf( int, float );
 
 // scalb*()
 
 externC double                    // scalbn(x,n) returns x*(2**n)
 scalbn( double, int );
 
+externC float
+scalbnf ( float, int);
+
 #ifdef CYGFUN_LIBM_SVID3_scalb
 
-externC double
-scalb( double, double );          // as above except n is a floating point arg
+// as above except n is a floating point arg
+CYGDCL_LIBM_IEEE_API_INLINE_FF(scalb)
 
 #else
 externC double
 scalb( double, int );             // as scalbn()
 
+externC float
+scalbf( float, int );
+
 #endif // ifdef CYGFUN_LIBM_SVID3_scalb
 
 // And the rest
@@ -357,58 +537,90 @@ scalb( double, int );             // as 
 externC double
 cbrt( double );                   // Cube Root
 
-externC double                    // hypotenuse function, defined such that:
-hypot( double, double );          // hypot(x,y)==sqrt(x**2 + y**2)
+externC float
+cbrtf( float );
+
+// hypotenuse function, defined such that:
+// hypotf(x,y)==sqrt(x**2 + y**2)
+
+CYGDCL_LIBM_IEEE_API_INLINE_FF(hypot)
 
 externC int                       // whether the argument is NaN
 isnan( double );
 
 externC int
+isnanf ( float );
+
+externC int                       // wheteher the argument is infinite
+isinf(double);
+
+externC int
+isinff(float);
+
+externC int
 finite( double );                 // whether the argument is finite
 
+externC int
+finitef ( float );
+
 externC double                    // logb returns the binary exponent of its
 logb( double );                   // argument as an integral value
                                   // This is not recommended - use ilogb
-                                  // instead
+externC float                     // instead
+logbf ( float );
 
 externC int                       // As for logb, but has the more correct
 ilogb( double );                  // return value type of int
 
+externC int
+ilogbf ( float );
 
 externC double                    // nextafter(x,y) returns the next
 nextafter( double, double );      // representable floating point number
                                   // adjacent to x in the direction of y
-                                  // i.e. the next greater FP if y>x, the next
-                                  // less FP if y<x, or just x if y==x
+externC float                     // i.e. the next greater FP if y>x, the next
+nextafterf ( float, float );      // less FP if y<x, or just x if y==x
 
-externC double                    // remainder(x,y) returns the remainder
-remainder( double, double );      // when x is divided by y
+// when x is divided by y
+CYGDCL_LIBM_IEEE_API_INLINE_FF(remainder)
 
 externC double                    // IEEE Test Vector
 significand( double );            // significand(x) computes:
                                   //   scalb(x, (double) -ilogb(x))
-                                 
+externC float
+significandf( float );
+
 //===========================================================================
 // Non-standard functions
 
 externC double                    // copysign(x,y) returns a number with
 copysign ( double, double );      // the absolute value of x and the sign of y
 
+externC float
+copysignf ( float, float );
+
 externC double                    // rounds to an integer according to the
 rint( double );                   // current rounding mode
 
+externC float
+rintf ( float );
+
 
 // BSD functions
 
 externC double                    // expm1(x) returns the equivalent of
 expm1( double );                  // (exp(x) - 1) but more accurately when
                                   // x tends to zero
+externC float
+expm1f ( float );
 
 externC double                    // log1p(x) returns the equivalent of
 log1p( double );                  // log(1+x) but more accurately when
                                   // x tends to zero
+externC float
+log1pf ( float );
 
-#endif // ifdef CYGPKG_LIBM     
+#endif // ifdef CYGPKG_LIBM
 
 #endif // CYGONCE_LIBM_MATH_H multiple inclusion protection
 
diff --git a/packages/language/c/libm/current/src/complex/cabs.c b/packages/language/c/libm/current/src/complex/cabs.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cabs.c
@@ -0,0 +1,53 @@
+/* $NetBSD: cabs.c,v 1.1 2007/08/20 16:01:30 drochner Exp $ */
+
+/*
+ * Written by Matthias Drochner <drochner@NetBSD.org>.
+ * Public domain.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<cabs>>, <<cabsf>>---complex absolute-value
+
+INDEX
+        cabs
+INDEX
+        cabsf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double cabs(double complex <[z]>);
+       float cabsf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute compute the complex absolute value 
+        (also called norm, modulus, or magnitude) of <[z]>. 
+
+        <<cabsf>> is identical to <<cabs>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        The cabs functions return the complex absolute value.
+
+PORTABILITY
+        <<cabs>> and <<cabsf>> are ISO C99
+
+QUICKREF
+        <<cabs>> and <<cabsf>> are ISO C99
+
+*/
+
+
+#include <complex.h>
+#include <math.h>
+
+double
+cabs(double complex z)
+{
+
+	return hypot( creal(z), cimag(z) );
+}
diff --git a/packages/language/c/libm/current/src/complex/cabsf.c b/packages/language/c/libm/current/src/complex/cabsf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cabsf.c
@@ -0,0 +1,19 @@
+/* $NetBSD: cabsf.c,v 1.1 2007/08/20 16:01:30 drochner Exp $ */
+
+/*
+ * Written by Matthias Drochner <drochner@NetBSD.org>.
+ * Public domain.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+
+float
+cabsf(float complex z)
+{
+
+	return hypotf( crealf(z), cimagf(z) );
+}
diff --git a/packages/language/c/libm/current/src/complex/cacos.c b/packages/language/c/libm/current/src/complex/cacos.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cacos.c
@@ -0,0 +1,99 @@
+/* $NetBSD: cacos.c,v 1.1 2007/08/20 16:01:30 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<cacos>>, <<cacosf>>---complex arc cosine
+
+INDEX
+        cacos
+INDEX
+        cacosf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex cacos(double complex <[z]>);
+       float complex cacosf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute the complex arc cosine of <[z]>,
+        with branch cuts outside the interval [-1, +1] along the real axis.
+
+        <<cacosf>> is identical to <<cacos>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        @ifnottex
+        These functions return the complex arc cosine value, in the range
+        of a strip mathematically  unbounded  along the imaginary axis
+        and in the interval [0, pi] along the real axis.
+        @end ifnottex
+        @tex
+        These functions return the complex arc cosine value, in the range
+        of a strip mathematically  unbounded  along the imaginary axis
+        and in the interval [<<0>>, $\pi$] along the real axis.
+        @end tex
+
+PORTABILITY
+        <<cacos>> and <<cacosf>> are ISO C99
+
+QUICKREF
+        <<cacos>> and <<cacosf>> are ISO C99
+
+*/
+
+#include <complex.h>
+#include <math.h>
+
+double complex
+cacos(double complex z)
+{
+	double complex w;
+
+	/* FIXME: The original NetBSD code results in an ICE when trying to
+	   build this function on ARM/Thumb using gcc 4.5.1.  For now we use
+	   a hopefully temporary workaround. */
+#if 0
+	w = casin(z);
+	w = (M_PI_2 - creal(w)) - cimag(w) * I;
+#else
+	double complex tmp0, tmp1;
+
+	tmp0 = casin(z);
+	tmp1 = M_PI_2 - creal(tmp0);
+	w = tmp1 - (cimag(tmp0) * I);
+#endif
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/cacosf.c b/packages/language/c/libm/current/src/complex/cacosf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cacosf.c
@@ -0,0 +1,46 @@
+/* $NetBSD: cacosf.c,v 1.1 2007/08/20 16:01:30 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+
+float complex
+cacosf(float complex z)
+{
+	float complex w;
+
+	w = casinf(z);
+	w = ((float)M_PI_2 - crealf(w)) - cimagf(w) * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/cacosh.c b/packages/language/c/libm/current/src/complex/cacosh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cacosh.c
@@ -0,0 +1,93 @@
+/* $NetBSD: cacosh.c,v 1.2 2009/08/03 19:41:32 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<cacosh>>, <<cacoshf>>---complex arc hyperbolic cosine
+
+INDEX
+        cacosh
+INDEX
+        cacoshf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex cacosh(double complex <[z]>);
+       float complex cacoshf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute the complex arc hyperbolic cosine of <[z]>,
+        with a branch cut at values less than 1 along the real axis.
+
+        <<cacoshf>> is identical to <<cacosh>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        @ifnottex
+        These functions return the complex arc hyperbolic cosine value, 
+        in the range of a half-strip of non-negative values along the 
+        real axis and in the interval [-i * pi, +i * pi] along the 
+        imaginary axis.
+        @end ifnottex
+        @tex
+        These functions return the complex arc hyperbolic cosine value, 
+        in the range of a half-strip of non-negative values along the 
+        real axis and in the interval [$-i\pi$, $+i\pi$] along the 
+        imaginary axis.
+        @end tex
+
+PORTABILITY
+        <<cacosh>> and <<cacoshf>> are ISO C99
+
+QUICKREF
+        <<cacosh>> and <<cacoshf>> are ISO C99
+
+*/
+
+
+#include <complex.h>
+
+double complex
+cacosh(double complex z)
+{
+	double complex w;
+
+#if 0 /* does not give the principal value */
+	w = I * cacos(z);
+#else
+	w = clog(z + csqrt(z + 1) * csqrt(z - 1));
+#endif
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/cacoshf.c b/packages/language/c/libm/current/src/complex/cacoshf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cacoshf.c
@@ -0,0 +1,48 @@
+/* $NetBSD: cacoshf.c,v 1.2 2009/08/03 19:41:32 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+
+float complex
+cacoshf(float complex z)
+{
+	float complex w;
+
+#if 0 /* does not give the principal value */
+	w = I * cacosf(z);
+#else
+	w = clogf(z + csqrtf(z + 1) * csqrtf(z - 1));
+#endif
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/carg.c b/packages/language/c/libm/current/src/complex/carg.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/carg.c
@@ -0,0 +1,59 @@
+/* $NetBSD: carg.c,v 1.1 2007/08/20 16:01:31 drochner Exp $ */
+
+/*
+ * Written by Matthias Drochner <drochner@NetBSD.org>.
+ * Public domain.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<carg>>, <<cargf>>---argument (phase angle)
+
+INDEX
+        carg
+INDEX
+        cargf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double carg(double complex <[z]>);
+       float cargf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute the argument (also called phase angle) 
+        of <[z]>, with a branch cut along the negative real axis.
+
+        <<cargf>> is identical to <<carg>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        @ifnottex
+        The carg functions return the value of the argument in the 
+        interval [-pi, +pi]
+        @end ifnottex
+        @tex
+        The carg functions return the value of the argument in the 
+        interval [$-\pi$, $+\pi$]
+        @end tex
+
+PORTABILITY
+        <<carg>> and <<cargf>> are ISO C99
+
+QUICKREF
+        <<carg>> and <<cargf>> are ISO C99
+
+*/
+
+#include <complex.h>
+#include <math.h>
+
+double
+carg(double complex z)
+{
+
+	return atan2( cimag(z) , creal(z) );
+}
diff --git a/packages/language/c/libm/current/src/complex/cargf.c b/packages/language/c/libm/current/src/complex/cargf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cargf.c
@@ -0,0 +1,19 @@
+/* $NetBSD: cargf.c,v 1.1 2007/08/20 16:01:31 drochner Exp $ */
+
+/*
+ * Written by Matthias Drochner <drochner@NetBSD.org>.
+ * Public domain.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+
+float
+cargf(float complex z)
+{
+
+	return atan2f( cimagf(z), crealf(z) );
+}
diff --git a/packages/language/c/libm/current/src/complex/casin.c b/packages/language/c/libm/current/src/complex/casin.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/casin.c
@@ -0,0 +1,165 @@
+/* $NetBSD: casin.c,v 1.1 2007/08/20 16:01:31 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<casin>>, <<casinf>>---complex arc sine
+
+INDEX
+        casin
+INDEX
+        casinf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex casin(double complex <[z]>);
+       float complex casinf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute the complex arc sine of <[z]>,
+        with branch cuts outside the interval [-1, +1] along the real axis.
+
+        <<casinf>> is identical to <<casin>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        @ifnottex
+        These functions return the complex arc sine value, in the range
+        of a strip mathematically  unbounded  along the imaginary axis
+        and in the interval [-pi/2, +pi/2] along the real axis.
+        @end ifnottex
+        @tex
+        These functions return the complex arc sine value, in the range
+        of a strip mathematically  unbounded  along the imaginary axis
+        and in the interval [$-\pi/2$, $+\pi/2$] along the real axis.
+        @end tex
+
+PORTABILITY
+        <<casin>> and <<casinf>> are ISO C99
+
+QUICKREF
+        <<casin>> and <<casinf>> are ISO C99
+
+*/
+
+
+#include <complex.h>
+#include <math.h>
+
+#ifdef __weak_alias
+__weak_alias(casin, _casin)
+#endif
+
+double complex
+casin(double complex z)
+{
+	double complex w;
+	double complex ca, ct, zz, z2;
+	double x, y;
+
+	x = creal(z);
+	y = cimag(z);
+
+#if 0 /* MD: test is incorrect, casin(>1) is defined */
+	if (y == 0.0) {
+		if (fabs(x) > 1.0) {
+			w = M_PI_2 + 0.0 * I;
+#if 0
+			mtherr ("casin", DOMAIN);
+#endif
+		} else {
+			w = asin(x) + 0.0 * I;
+		}
+		return w;
+	}
+#endif
+
+/* Power series expansion */
+/*
+b = cabs(z);
+if( b < 0.125 )
+{
+z2.r = (x - y) * (x + y);
+z2.i = 2.0 * x * y;
+
+cn = 1.0;
+n = 1.0;
+ca.r = x;
+ca.i = y;
+sum.r = x;
+sum.i = y;
+do
+	{
+	ct.r = z2.r * ca.r  -  z2.i * ca.i;
+	ct.i = z2.r * ca.i  +  z2.i * ca.r;
+	ca.r = ct.r;
+	ca.i = ct.i;
+
+	cn *= n;
+	n += 1.0;
+	cn /= n;
+	n += 1.0;
+	b = cn/n;
+
+	ct.r *= b;
+	ct.i *= b;
+	sum.r += ct.r;
+	sum.i += ct.i;
+	b = fabs(ct.r) + fabs(ct.i);
+	}
+while( b > MACHEP );
+w->r = sum.r;
+w->i = sum.i;
+return;
+}
+*/
+
+
+	ca = x + y * I;
+	ct = ca * I;
+	/* sqrt( 1 - z*z) */
+	/* cmul( &ca, &ca, &zz ) */
+	/*x * x  -  y * y */
+	zz = (x - y) * (x + y) + (2.0 * x * y) * I;
+
+	zz = 1.0 - creal(zz) - cimag(zz) * I;
+	z2 = csqrt(zz);
+
+	zz = ct + z2;
+	zz = clog(zz);
+	/* multiply by 1/i = -i */
+	w = zz * (-1.0 * I);
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/casinf.c b/packages/language/c/libm/current/src/complex/casinf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/casinf.c
@@ -0,0 +1,122 @@
+/* $NetBSD: casinf.c,v 1.1 2007/08/20 16:01:31 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+
+#ifdef __weak_alias
+__weak_alias(casinf, _casinf)
+#endif
+
+float complex
+casinf(float complex z)
+{
+	float complex w;
+	float complex ca, ct, zz, z2;
+	float x, y;
+
+	x = crealf(z);
+	y = cimagf(z);
+
+#if 0 /* MD: test is incorrect, casin(>1) is defined */
+	if (y == 0.0f) {
+		if (fabsf(x) > 1.0) {
+			w = M_PI_2 + 0.0f * I;
+#if 0
+			mtherr ("casin", DOMAIN);
+#endif
+		} else {
+			w = asinf(x) + 0.0f * I;
+		}
+		return w;
+	}
+#endif
+
+/* Power series expansion */
+/*
+b = cabsf(z);
+if( b < 0.125 )
+{
+z2.r = (x - y) * (x + y);
+z2.i = 2.0 * x * y;
+
+cn = 1.0;
+n = 1.0;
+ca.r = x;
+ca.i = y;
+sum.r = x;
+sum.i = y;
+do
+	{
+	ct.r = z2.r * ca.r  -  z2.i * ca.i;
+	ct.i = z2.r * ca.i  +  z2.i * ca.r;
+	ca.r = ct.r;
+	ca.i = ct.i;
+
+	cn *= n;
+	n += 1.0;
+	cn /= n;
+	n += 1.0;
+	b = cn/n;
+
+	ct.r *= b;
+	ct.i *= b;
+	sum.r += ct.r;
+	sum.i += ct.i;
+	b = fabsf(ct.r) + fabsf(ct.i);
+	}
+while( b > MACHEP );
+w->r = sum.r;
+w->i = sum.i;
+return;
+}
+*/
+
+
+	ca = x + y * I;
+	ct = ca * I;
+	/* sqrt( 1 - z*z) */
+	/* cmul( &ca, &ca, &zz ) */
+	/*x * x  -  y * y */
+	zz = (x - y) * (x + y) + (2.0f * x * y) * I;
+
+	zz = 1.0f - crealf(zz) - cimagf(zz) * I;
+	z2 = csqrtf(zz);
+
+	zz = ct + z2;
+	zz = clogf(zz);
+	/* multiply by 1/i = -i */
+	w = zz * (-1.0f * I);
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/casinh.c b/packages/language/c/libm/current/src/complex/casinh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/casinh.c
@@ -0,0 +1,97 @@
+/* $NetBSD: casinh.c,v 1.1 2007/08/20 16:01:31 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<casinh>>, <<casinhf>>---complex arc hyperbolic sine
+
+INDEX
+        casinh
+INDEX
+        casinhf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex casinh(double complex <[z]>);
+       float complex casinhf(float complex <[z]>);
+
+
+DESCRIPTION
+        @ifnottex
+        These functions compute the complex arc hyperbolic sine of <[z]>,
+        with branch cuts outside the interval [-i, +i] along the 
+        imaginary axis.        
+        @end ifnottex
+        @tex
+        These functions compute the complex arc hyperbolic sine of <[z]>,
+        with branch cuts outside the interval [$-i$, $+i$] along the 
+        imaginary axis.        
+        @end tex
+
+        <<casinhf>> is identical to <<casinh>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        @ifnottex
+        These functions return the complex arc hyperbolic sine value, 
+        in the range of a strip mathematically unbounded along the 
+        real axis and in the interval [-i*p/2, +i*p/2] along the 
+        imaginary axis.
+        @end ifnottex
+        @tex
+        These functions return the complex arc hyperbolic sine value, 
+        in the range of a strip mathematically unbounded along the 
+        real axis and in the interval [$-i\pi/2$, $+i\pi/2$] along the 
+        imaginary axis.
+        @end tex
+
+PORTABILITY
+        <<casinh>> and <<casinhf>> are ISO C99
+
+QUICKREF
+        <<casinh>> and <<casinhf>> are ISO C99
+
+*/
+
+
+#include <complex.h>
+
+double complex
+casinh(double complex z)
+{
+	double complex w;
+
+	w = -1.0 * I * casin(z * I);
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/casinhf.c b/packages/language/c/libm/current/src/complex/casinhf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/casinhf.c
@@ -0,0 +1,44 @@
+/* $NetBSD: casinhf.c,v 1.1 2007/08/20 16:01:32 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+
+float complex
+casinhf(float complex z)
+{
+	float complex w;
+
+	w = -1.0f * I * casinf(z * I);
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/catan.c b/packages/language/c/libm/current/src/complex/catan.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/catan.c
@@ -0,0 +1,130 @@
+/* $NetBSD: catan.c,v 1.1 2007/08/20 16:01:32 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<catan>>, <<catanf>>---complex arc tangent
+
+INDEX
+        catan
+INDEX
+        catanf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex catan(double complex <[z]>);
+       float complex catanf(float complex <[z]>);
+
+
+DESCRIPTION
+        @ifnottex
+        These functions compute the complex arc tangent of <[z]>,
+        with branch cuts outside the interval [-i, +i] along the 
+        imaginary axis.
+        @end ifnottex
+        @tex
+        These functions compute the complex arc tangent of <[z]>,
+        with branch cuts outside the interval [$-i$, $+i$] along the 
+        imaginary axis.
+        @end tex
+
+        <<catanf>> is identical to <<catan>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        @ifnottex
+        These functions return the complex arc tangent value, in the range
+        of a strip mathematically  unbounded  along the imaginary axis
+        and in the interval [-pi/2, +pi/2] along the real axis.
+        @end ifnottex
+        @tex
+        These functions return the complex arc tangent, in the range
+        of a strip mathematically  unbounded  along the imaginary axis
+        and in the interval [$-\pi/2$, $+\pi/2$] along the real axis.
+        @end tex
+
+PORTABILITY
+        <<catan>> and <<catanf>> are ISO C99
+
+QUICKREF
+        <<catan>> and <<catanf>> are ISO C99
+
+*/
+
+
+#include <complex.h>
+#include <math.h>
+#include "cephes_subr.h"
+
+#ifdef __weak_alias
+__weak_alias(catan, _catan)
+#endif
+
+double complex
+catan(double complex z)
+{
+	double complex w;
+	double a, t, x, x2, y;
+
+	x = creal(z);
+	y = cimag(z);
+
+	if ((x == 0.0) && (y > 1.0))
+		goto ovrf;
+
+	x2 = x * x;
+	a = 1.0 - x2 - (y * y);
+	if (a == 0.0)
+		goto ovrf;
+
+	t = 0.5 * atan2(2.0 * x, a);
+	w = _redupi(t);
+
+	t = y - 1.0;
+	a = x2 + (t * t);
+	if (a == 0.0)
+		goto ovrf;
+
+	t = y + 1.0;
+	a = (x2 + (t * t))/a;
+	w = w + (0.25 * log(a)) * I;
+	return w;
+
+ovrf:
+#if 0
+	mtherr ("catan", OVERFLOW);
+#endif
+	w = HUGE_VAL + HUGE_VAL * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/catanf.c b/packages/language/c/libm/current/src/complex/catanf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/catanf.c
@@ -0,0 +1,79 @@
+/* $NetBSD: catanf.c,v 1.1 2007/08/20 16:01:32 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+#include "cephes_subrf.h"
+
+#ifdef __weak_alias
+__weak_alias(catanf, _catanf)
+#endif
+
+float complex
+catanf(float complex z)
+{
+	float complex w;
+	float a, t, x, x2, y;
+
+	x = crealf(z);
+	y = cimagf(z);
+
+	if ((x == 0.0f) && (y > 1.0f))
+		goto ovrf;
+
+	x2 = x * x;
+	a = 1.0f - x2 - (y * y);
+	if (a == 0.0f)
+		goto ovrf;
+
+	t = 0.5f * atan2f(2.0f * x, a);
+	w = _redupif(t);
+
+	t = y - 1.0f;
+	a = x2 + (t * t);
+	if (a == 0.0f)
+		goto ovrf;
+
+	t = y + 1.0f;
+	a = (x2 + (t * t))/a;
+	w = w + (0.25f * logf(a)) * I;
+	return w;
+
+ovrf:
+#if 0
+	mtherr ("catan", OVERFLOW);
+#endif
+	w = HUGE_VALF + HUGE_VALF * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/catanh.c b/packages/language/c/libm/current/src/complex/catanh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/catanh.c
@@ -0,0 +1,90 @@
+/* $NetBSD: catanh.c,v 1.1 2007/08/20 16:01:32 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<catanh>>, <<catanhf>>---complex arc hyperbolic tangent
+
+INDEX
+        catanh
+INDEX
+        catanhf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex catanh(double complex <[z]>);
+       float complex catanhf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute the complex arc hyperbolic tan of <[z]>,
+        with branch cuts outside the interval [-1, +1] along the
+        real axis.
+
+        <<catanhf>> is identical to <<catanh>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        @ifnottex
+        These functions return the complex arc hyperbolic tangent value,
+        in the range of a strip mathematically unbounded along the
+        real axis and in the interval [-i*p/2, +i*p/2] along the
+        imaginary axis.
+        @end ifnottex
+        @tex
+        These functions return the complex arc hyperbolic tangent value,
+        in the range of a strip mathematically unbounded along the
+        real axis and in the interval [$-i\pi/2$, $+i\pi/2$] along the
+        imaginary axis.
+        @end tex
+
+PORTABILITY
+        <<catanh>> and <<catanhf>> are ISO C99
+
+QUICKREF
+        <<catanh>> and <<catanhf>> are ISO C99
+
+*/
+
+
+#include <complex.h>
+
+double complex
+catanh(double complex z)
+{
+	double complex w;
+
+	w = -1.0 * I * catan(z * I);
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/catanhf.c b/packages/language/c/libm/current/src/complex/catanhf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/catanhf.c
@@ -0,0 +1,44 @@
+/* $NetBSD: catanhf.c,v 1.1 2007/08/20 16:01:32 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+
+float complex
+catanhf(float complex z)
+{
+	float complex w;
+
+	w = -1.0f * I * catanf(z * I);
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/ccos.c b/packages/language/c/libm/current/src/complex/ccos.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/ccos.c
@@ -0,0 +1,81 @@
+/* $NetBSD: ccos.c,v 1.1 2007/08/20 16:01:32 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<ccos>>, <<ccosf>>---complex cosine
+
+INDEX
+        ccos
+INDEX
+        ccosf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex ccos(double complex <[z]>);
+       float complex ccosf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute the complex cosine of <[z]>.
+
+        <<ccosf>> is identical to <<ccos>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        These functions return the complex cosine value.
+
+PORTABILITY
+        <<ccos>> and <<ccosf>> are ISO C99
+
+QUICKREF
+        <<ccos>> and <<ccosf>> are ISO C99
+
+*/
+
+
+#include <complex.h>
+#include <math.h>
+#include "cephes_subr.h"
+
+double complex
+ccos(double complex z)
+{
+	double complex w;
+	double ch, sh;
+
+	_cchsh(cimag(z), &ch, &sh);
+	w = cos(creal(z)) * ch - (sin(creal(z)) * sh) * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/ccosf.c b/packages/language/c/libm/current/src/complex/ccosf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/ccosf.c
@@ -0,0 +1,48 @@
+/* $NetBSD: ccosf.c,v 1.1 2007/08/20 16:01:33 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+#include "cephes_subrf.h"
+
+float complex
+ccosf(float complex z)
+{
+	float complex w;
+	float ch, sh;
+
+	_cchshf(cimagf(z), &ch, &sh);
+	w = cosf(crealf(z)) * ch - (sinf(crealf(z)) * sh) * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/ccosh.c b/packages/language/c/libm/current/src/complex/ccosh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/ccosh.c
@@ -0,0 +1,81 @@
+/* $NetBSD: ccosh.c,v 1.1 2007/08/20 16:01:33 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<ccosh>>, <<ccoshf>>---complex hyperbolic cosine
+
+INDEX
+        ccosh
+INDEX
+        ccoshf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex ccosh(double complex <[z]>);
+       float complex ccoshf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute the complex hyperbolic cosine of <[z]>.
+
+        <<ccoshf>> is identical to <<ccosh>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        These functions return the complex hyperbolic cosine value.
+
+PORTABILITY
+        <<ccosh>> and <<ccoshf>> are ISO C99
+
+QUICKREF
+        <<ccosh>> and <<ccoshf>> are ISO C99
+
+*/
+
+
+#include <complex.h>
+#include <math.h>
+
+double complex
+ccosh(double complex z)
+{
+	double complex w;
+	double x, y;
+
+	x = creal(z);
+	y = cimag(z);
+	w = cosh(x) * cos(y) + (sinh(x) * sin(y)) * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/ccoshf.c b/packages/language/c/libm/current/src/complex/ccoshf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/ccoshf.c
@@ -0,0 +1,48 @@
+/* $NetBSD: ccoshf.c,v 1.1 2007/08/20 16:01:33 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+
+float complex
+ccoshf(float complex z)
+{
+	float complex w;
+	float x, y;
+
+	x = crealf(z);
+	y = cimagf(z);
+	w = coshf(x) * cosf(y) + (sinhf(x) * sinf(y)) * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/cephes_subr.c b/packages/language/c/libm/current/src/complex/cephes_subr.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cephes_subr.c
@@ -0,0 +1,126 @@
+/* $NetBSD: cephes_subr.c,v 1.1 2007/08/20 16:01:33 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+#include "cephes_subr.h"
+
+/* calculate cosh and sinh */
+
+void
+_cchsh(double x, double *c, double *s)
+{
+	double e, ei;
+
+	if (fabs(x) <= 0.5) {
+		*c = cosh(x);
+		*s = sinh(x);
+	} else {
+		e = exp(x);
+		ei = 0.5 / e;
+		e = 0.5 * e;
+		*s = e - ei;
+		*c = e + ei;
+	}
+}
+
+/* Program to subtract nearest integer multiple of PI */
+
+/* extended precision value of PI: */
+static const double DP1 = 3.14159265160560607910E0;
+static const double DP2 = 1.98418714791870343106E-9;
+static const double DP3 = 1.14423774522196636802E-17;
+#define MACHEP 1.1e-16
+
+double
+_redupi(double x)
+{
+	double t;
+	long i;
+
+	t = x / M_PI;
+	if (t >= 0.0)
+		t += 0.5;
+	else
+		t -= 0.5;
+
+	i = t;	/* the multiple */
+	t = i;
+	t = ((x - t * DP1) - t * DP2) - t * DP3;
+	return t;
+}
+
+/* Taylor series expansion for cosh(2y) - cos(2x) */
+
+double
+_ctans(double complex z)
+{
+	double f, x, x2, y, y2, rn, t;
+	double d;
+
+	x = fabs(2.0 * creal(z));
+	y = fabs(2.0 * cimag(z));
+
+	x = _redupi(x);
+
+	x = x * x;
+	y = y * y;
+	x2 = 1.0;
+	y2 = 1.0;
+	f = 1.0;
+	rn = 0.0;
+	d = 0.0;
+	do {
+		rn += 1.0;
+		f *= rn;
+		rn += 1.0;
+		f *= rn;
+		x2 *= x;
+		y2 *= y;
+		t = y2 + x2;
+		t /= f;
+		d += t;
+
+		rn += 1.0;
+		f *= rn;
+		rn += 1.0;
+		f *= rn;
+		x2 *= x;
+		y2 *= y;
+		t = y2 - x2;
+		t /= f;
+		d += t;
+	} while (fabs(t/d) > MACHEP);
+	return d;
+}
diff --git a/packages/language/c/libm/current/src/complex/cephes_subr.h b/packages/language/c/libm/current/src/complex/cephes_subr.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cephes_subr.h
@@ -0,0 +1,5 @@
+/* $NetBSD: cephes_subr.h,v 1.1 2007/08/20 16:01:33 drochner Exp $ */
+
+void _cchsh(double, double *, double *);
+double _redupi(double);
+double _ctans(double complex);
diff --git a/packages/language/c/libm/current/src/complex/cephes_subrf.c b/packages/language/c/libm/current/src/complex/cephes_subrf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cephes_subrf.c
@@ -0,0 +1,125 @@
+/* $NetBSD: cephes_subrf.c,v 1.1 2007/08/20 16:01:34 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+#include "cephes_subrf.h"
+
+/* calculate cosh and sinh */
+
+void
+_cchshf(float x, float *c, float *s)
+{
+	float e, ei;
+
+	if (fabsf(x) <= 0.5f) {
+		*c = coshf(x);
+		*s = sinhf(x);
+	} else {
+		e = expf(x);
+		ei = 0.5f / e;
+		e = 0.5f * e;
+		*s = e - ei;
+		*c = e + ei;
+	}
+}
+
+/* Program to subtract nearest integer multiple of PI */
+
+/* extended precision value of PI: */
+static const double DP1 =  3.140625;
+static const double DP2 =  9.67502593994140625E-4;
+static const double DP3 =  1.509957990978376432E-7;
+#define MACHEPF 3.0e-8
+
+float
+_redupif(float x)
+{
+	float t;
+	long i;
+
+	t = x / (float)M_PI;
+	if (t >= 0.0f)
+		t += 0.5f;
+	else
+		t -= 0.5f;
+
+	i = t;	/* the multiple */
+	t = i;
+	t = ((x - t * DP1) - t * DP2) - t * DP3;
+	return t;
+}
+
+/* Taylor series expansion for cosh(2y) - cos(2x) */
+
+float
+_ctansf(float complex z)
+{
+	float f, x, x2, y, y2, rn, t, d;
+
+	x = fabsf(2.0f * crealf(z));
+	y = fabsf(2.0f * cimagf(z));
+
+	x = _redupif(x);
+
+	x = x * x;
+	y = y * y;
+	x2 = 1.0f;
+	y2 = 1.0f;
+	f = 1.0f;
+	rn = 0.0f;
+	d = 0.0f;
+	do {
+		rn += 1.0f;
+		f *= rn;
+		rn += 1.0f;
+		f *= rn;
+		x2 *= x;
+		y2 *= y;
+		t = y2 + x2;
+		t /= f;
+		d += t;
+
+		rn += 1.0f;
+		f *= rn;
+		rn += 1.0f;
+		f *= rn;
+		x2 *= x;
+		y2 *= y;
+		t = y2 - x2;
+		t /= f;
+		d += t;
+	} while (fabsf(t/d) > MACHEPF);
+	return d;
+}
diff --git a/packages/language/c/libm/current/src/complex/cephes_subrf.h b/packages/language/c/libm/current/src/complex/cephes_subrf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cephes_subrf.h
@@ -0,0 +1,5 @@
+/* $NetBSD: cephes_subrf.h,v 1.1 2007/08/20 16:01:34 drochner Exp $ */
+
+void _cchshf(float, float *, float *);
+float _redupif(float);
+float _ctansf(float complex);
diff --git a/packages/language/c/libm/current/src/complex/cexp.c b/packages/language/c/libm/current/src/complex/cexp.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cexp.c
@@ -0,0 +1,82 @@
+/* $NetBSD: cexp.c,v 1.1 2007/08/20 16:01:34 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<cexp>>, <<cexpf>>---complex base-e exponential
+
+INDEX
+        cexp
+INDEX
+        cexpf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex cexp(double complex <[z]>);
+       float complex cexpf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute  the complex base-<[e]> exponential of <[z]>.
+
+        <<cexpf>> is identical to <<cexp>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        The cexp functions return the complex base-<[e]> exponential value.
+
+PORTABILITY
+        <<cexp>> and <<cexpf>> are ISO C99
+
+QUICKREF
+        <<cexp>> and <<cexpf>> are ISO C99
+
+*/
+
+
+#include <complex.h>
+#include <math.h>
+
+double complex
+cexp(double complex z)
+{
+	double complex w;
+	double r, x, y;
+
+	x = creal(z);
+	y = cimag(z);
+	r = exp(x);
+	w = r * cos(y) + r * sin(y) * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/cexpf.c b/packages/language/c/libm/current/src/complex/cexpf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cexpf.c
@@ -0,0 +1,49 @@
+/* $NetBSD: cexpf.c,v 1.1 2007/08/20 16:01:34 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+
+float complex
+cexpf(float complex z)
+{
+	float complex w;
+	float r, x, y;
+
+	x = crealf(z);
+	y = cimagf(z);
+	r = expf(x);
+	w = r * cosf(y) + r * sinf(y) * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/cimag.c b/packages/language/c/libm/current/src/complex/cimag.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cimag.c
@@ -0,0 +1,61 @@
+//===========================================================================
+//
+//      cimag.c
+//
+//      Complex numbr real part  - double precision.
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ilijak
+// Contributors:
+// Date:         2013-06-06
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+#include <complex.h>
+
+double
+cimag(double complex z)
+{
+    return __builtin_cimag(z);
+}
+
+//  End of cimag.c
diff --git a/packages/language/c/libm/current/src/complex/cimagf.c b/packages/language/c/libm/current/src/complex/cimagf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cimagf.c
@@ -0,0 +1,61 @@
+//===========================================================================
+//
+//      cimagf.c
+//
+//      Complex numbr real part  - single precision.
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ilijak
+// Contributors:
+// Date:         2013-06-06
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+#include <complex.h>
+
+float
+cimagf(float complex z)
+{
+    return __builtin_cimagf(z);
+}
+
+// End of cimagf.c
diff --git a/packages/language/c/libm/current/src/complex/clog.c b/packages/language/c/libm/current/src/complex/clog.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/clog.c
@@ -0,0 +1,91 @@
+/* $NetBSD: clog.c,v 1.1 2007/08/20 16:01:35 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<clog>>, <<clogf>>---complex base-e logarithm
+
+INDEX
+        clog
+INDEX
+        clogf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex clog(double complex <[z]>);
+       float complex clogf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute the complex natural (base-<[e]>) logarithm 
+        of <[z]>, with a branch cut along the negative real axis. 
+
+        <<clogf>> is identical to <<clog>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        @ifnottex
+        The clog functions return the complex natural logarithm value, in 
+        the range of a strip mathematically unbounded along the real axis 
+        and in the interval [-i*pi , +i*pi] along the imaginary axis.
+        @end ifnottex
+        @tex
+        The clog functions return the complex natural logarithm value, in
+        the range of a strip mathematically unbounded along the real axis
+         and in the interval [$-i\pi$, $+i\pi$] along the imaginary axis.
+        @end tex
+
+PORTABILITY
+        <<clog>> and <<clogf>> are ISO C99
+
+QUICKREF
+        <<clog>> and <<clogf>> are ISO C99
+
+*/
+
+#include <complex.h>
+#include <math.h>
+
+double complex
+clog(double complex z)
+{
+	double complex w;
+	double p, rr;
+
+	rr = cabs(z);
+	p = log(rr);
+	rr = atan2(cimag(z), creal(z));
+	w = p + rr * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/clogf.c b/packages/language/c/libm/current/src/complex/clogf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/clogf.c
@@ -0,0 +1,49 @@
+/* $NetBSD: clogf.c,v 1.1 2007/08/20 16:01:35 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+
+float complex
+clogf(float complex z)
+{
+	float complex w;
+	float p, rr;
+
+	rr = cabsf(z);
+	p = logf(rr);
+	rr = atan2f(cimagf(z), crealf(z));
+	w = p + rr * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/complex.tex b/packages/language/c/libm/current/src/complex/complex.tex
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/complex.tex
@@ -0,0 +1,55 @@
+@node Complex
+@chapter Mathematical Complex Functions (@file{complex.h})
+
+This chapter groups the complex mathematical functions.  The
+corresponding definitions and declarations are in @file{complex.h}.  
+Functions and documentations are taken from NetBSD.
+
+@menu 
+* cabs::	Complex absolute value
+* cacos::	Complex arc cosine
+* cacosh::	Complex arc hyperbolic cosine
+* carg::	Argument (also called phase angle)
+* casin::	Complex arc sine
+* casinh::	Complex arc hyperbolic sine
+* catan::	Complex arc tangent
+* catanh::	Complex arc hyperbolic tangent
+* ccos::	Complex cosine
+* ccosh::	Complex hyperbolic cosine
+* cexp::	Complex exponent
+* cimag::	Imaginary part
+* clog::	Complex natural (base e) logarithm
+* conj::	Complex conjugate
+* cpow::	Complex power function
+* cproj::	Compute a projection on the Riemann sphere
+* creal::	Real part
+* csin::	Complex sine
+* csinh::	Complex hyperbolic sine
+* csqrt::	Complex square root
+* ctan::	Complex tangent
+* ctanh::	Complex hyperbolic tangent
+@end menu
+
+
+@page @include   complex/cabs.def
+@page @include   complex/cacos.def
+@page @include   complex/cacosh.def
+@page @include   complex/carg.def
+@page @include   complex/casin.def
+@page @include   complex/casinh.def
+@page @include   complex/catan.def
+@page @include   complex/catanh.def
+@page @include   complex/ccos.def
+@page @include   complex/ccosh.def
+@page @include   complex/cexp.def
+@page @include   complex/cimag.def
+@page @include   complex/clog.def
+@page @include   complex/conj.def
+@page @include   complex/cpow.def
+@page @include   complex/cproj.def
+@page @include   complex/creal.def
+@page @include   complex/csin.def
+@page @include   complex/csinh.def
+@page @include   complex/csqrt.def
+@page @include   complex/ctan.def
+@page @include   complex/ctanh.def
diff --git a/packages/language/c/libm/current/src/complex/conj.c b/packages/language/c/libm/current/src/complex/conj.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/conj.c
@@ -0,0 +1,61 @@
+//===========================================================================
+//
+//      conj.c
+//
+//      Complex cojugate - double precision.
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ilijak
+// Contributors:
+// Date:         2013-06-06
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+#include <complex.h>
+
+double complex
+conj(double complex z)
+{
+    return __builtin_conj(z);
+}
+
+// End of conj.c
diff --git a/packages/language/c/libm/current/src/complex/conjf.c b/packages/language/c/libm/current/src/complex/conjf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/conjf.c
@@ -0,0 +1,61 @@
+//===========================================================================
+//
+//      conjf.c
+//
+//      Complex cojugate - single precision.
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: ilijak
+// Date:         2013-06-06
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+#include <complex.h>
+
+float complex
+conjf(float complex z)
+{
+    return __builtin_conjf(z);
+}
+
+// End of conjf.c
diff --git a/packages/language/c/libm/current/src/complex/cpow.c b/packages/language/c/libm/current/src/complex/cpow.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cpow.c
@@ -0,0 +1,101 @@
+/* $NetBSD: cpow.c,v 1.1 2007/08/20 16:01:35 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<cpow>>, <<cpowf>>---complex power
+
+INDEX
+        cpow
+INDEX
+        cpowf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex cpow(double complex <[x]>, double complex <[y]>);
+       float complex cpowf(float complex <[x]>, float complex <[y]>);
+
+
+DESCRIPTION
+        @ifnottex
+        The cpow functions compute the complex power function x^y 
+        power, with a branch cut for the first parameter along the 
+        negative real axis.
+        @end ifnottex
+        @tex
+        The cpow functions compute the complex power function $x^y$ 
+        power, with a branch cut for the first parameter along the 
+        negative real axis.
+        @end tex
+
+        <<cpowf>> is identical to <<cpow>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        The cpow functions return the complex power function value.
+
+PORTABILITY
+        <<cpow>> and <<cpowf>> are ISO C99
+
+QUICKREF
+        <<cpow>> and <<cpowf>> are ISO C99
+
+*/
+
+
+#include <complex.h>
+#include <math.h>
+
+double complex
+cpow(double complex a, double complex z)
+{
+	double complex w;
+	double x, y, r, theta, absa, arga;
+
+	x = creal(z);
+	y = cimag(z);
+	absa = cabs(a);
+	if (absa == 0.0) {
+		return (0.0 + 0.0 * I);
+	}
+	arga = carg(a);
+	r = pow(absa, x);
+	theta = x * arga;
+	if (y != 0.0) {
+		r = r * exp(-y * arga);
+		theta = theta + y * log(absa);
+	}
+	w = r * cos(theta) + (r * sin(theta)) * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/cpowf.c b/packages/language/c/libm/current/src/complex/cpowf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cpowf.c
@@ -0,0 +1,59 @@
+/* $NetBSD: cpowf.c,v 1.1 2007/08/20 16:01:36 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+
+float complex
+cpowf(float complex a, float complex z)
+{
+	float complex w;
+	float x, y, r, theta, absa, arga;
+
+	x = crealf(z);
+	y = cimagf(z);
+	absa = cabsf(a);
+	if (absa == 0.0f) {
+		return (0.0f + 0.0f * I);
+	}
+	arga = cargf(a);
+	r = powf(absa, x);
+	theta = x * arga;
+	if (y != 0.0f) {
+		r = r * expf(-y * arga);
+		theta = theta + y * logf(absa);
+	}
+	w = r * cosf(theta) + (r * sinf(theta)) * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/cproj.c b/packages/language/c/libm/current/src/complex/cproj.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cproj.c
@@ -0,0 +1,106 @@
+/*	$NetBSD: cproj.c,v 1.3 2010/09/20 17:51:38 christos Exp $	*/
+
+/*-
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<cproj>>, <<cprojf>>--- Riemann sphere projection
+ 
+INDEX
+        cproj
+INDEX
+        cprojf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex cproj(double complex <[z]>);
+       float complex cprojf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute a projection of <[z]> onto the Riemann 
+        sphere: <[z]> projects to <[z]> except that all complex infinities 
+        (even those with one infinite part and one NaN part) project 
+        to positive infinity on the real axis. If <[z]> has an infinite part,
+        then <<cproj>>(<[z]>) is equivalent to
+
+                 INFINITY + I * copysign(0.0, cimag(z))
+
+        <<cprojf>> is identical to <<cproj>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        The cproj functions return the value of the projection onto 
+        the Riemann sphere.
+
+PORTABILITY
+        <<cproj>> and <<cprojf>> are ISO C99
+
+QUICKREF
+        <<cproj>> and <<cprojf>> are ISO C99
+
+*/
+
+//#include <sys/cdefs.h>
+/*__RCSID("$NetBSD: cproj.c,v 1.3 2010/09/20 17:51:38 christos Exp $"); */
+
+#include <complex.h>
+#include <math.h>
+
+#include "../mathincl/fdlibm.h"
+
+/*
+ * cproj(double complex z)
+ *
+ * These functions return the value of the projection (not stereographic!)
+ * onto the Riemann sphere.
+ *
+ * z projects to z, except that all complex infinities (even those with one
+ * infinite part and one NaN part) project to positive infinity on the real axis.
+ * If z has an infinite part, then cproj(z) shall be equivalent to:
+ *
+ * INFINITY + I * copysign(0.0, cimag(z))
+ */
+double complex
+cproj(double complex z)
+{
+	double_complex w = { .z = z };
+
+	if (isinf(creal(z)) || isinf(cimag(z))) {
+#ifdef __INFINITY
+		REAL_PART(w) = __INFINITY;
+#else
+		REAL_PART(w) = HUGE_VAL;
+#endif
+		IMAG_PART(w) = copysign(0.0, cimag(z));
+	}
+
+	return (w.z);
+}
diff --git a/packages/language/c/libm/current/src/complex/cprojf.c b/packages/language/c/libm/current/src/complex/cprojf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/cprojf.c
@@ -0,0 +1,67 @@
+/*	$NetBSD: cprojf.c,v 1.3 2010/09/20 17:51:38 christos Exp $	*/
+
+/*-
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*__RCSID("$NetBSD: cprojf.c,v 1.3 2010/09/20 17:51:38 christos Exp $"); */
+
+#include <complex.h>
+#include <math.h>
+
+#include "../mathincl/fdlibm.h"
+
+/*
+ * cprojf(float complex z)
+ *
+ * These functions return the value of the projection (not stereographic!)
+ * onto the Riemann sphere.
+ *
+ * z projects to z, except that all complex infinities (even those with one
+ * infinite part and one NaN part) project to positive infinity on the real axis.
+ * If z has an infinite part, then cproj(z) shall be equivalent to:
+ *
+ * INFINITY + I * copysign(0.0, cimag(z))
+ */
+
+float complex
+cprojf(float complex z)
+{
+	float_complex w = { .z = z };
+
+	if (isinff(crealf(z)) || isinff(cimagf(z))) {
+#ifdef __INFINITY
+		REAL_PART(w) = __INFINITY;
+#else
+		REAL_PART(w) = HUGE_VALF;
+#endif
+		IMAG_PART(w) = copysignf(0.0, cimagf(z));
+	}
+
+	return (w.z);
+}
diff --git a/packages/language/c/libm/current/src/complex/creal.c b/packages/language/c/libm/current/src/complex/creal.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/creal.c
@@ -0,0 +1,61 @@
+//===========================================================================
+//
+//      creal.c
+//
+//      Complex numbr real part  - double precision.
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ilijak
+// Contributors:
+// Date:         2013-06-06
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+#include <complex.h>
+
+double
+creal(double complex z)
+{
+    return __builtin_creal(z);
+}
+
+//  End of creal.c
diff --git a/packages/language/c/libm/current/src/complex/crealf.c b/packages/language/c/libm/current/src/complex/crealf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/crealf.c
@@ -0,0 +1,61 @@
+//===========================================================================
+//
+//      crealf.c
+//
+//      Complex numbr real part  - single precision.
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ilijak
+// Contributors:
+// Date:         2013-06-06
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+#include <complex.h>
+
+float
+crealf(float complex z)
+{
+    return __builtin_crealf(z);
+}
+
+// End of crealf.c
diff --git a/packages/language/c/libm/current/src/complex/csin.c b/packages/language/c/libm/current/src/complex/csin.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/csin.c
@@ -0,0 +1,81 @@
+/* $NetBSD: csin.c,v 1.1 2007/08/20 16:01:36 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<csin>>, <<csinf>>---complex sine
+
+INDEX
+        csin
+INDEX
+        csinf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex csin(double complex <[z]>);
+       float complex csinf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute the complex sine of <[z]>.
+
+        <<csinf>> is identical to <<csin>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        These functions return the complex sine value.
+
+PORTABILITY
+        <<csin>> and <<csinf>> are ISO C99
+
+QUICKREF
+        <<csin>> and <<csinf>> are ISO C99
+
+*/
+
+
+#include <complex.h>
+#include <math.h>
+#include "cephes_subr.h"
+
+double complex
+csin(double complex z)
+{
+	double complex w;
+	double ch, sh;
+
+	_cchsh(cimag(z), &ch, &sh);
+	w = sin(creal(z)) * ch + (cos(creal(z)) * sh) * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/csinf.c b/packages/language/c/libm/current/src/complex/csinf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/csinf.c
@@ -0,0 +1,48 @@
+/* $NetBSD: csinf.c,v 1.1 2007/08/20 16:01:36 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+#include "cephes_subrf.h"
+
+float complex
+csinf(float complex z)
+{
+	float complex w;
+	float ch, sh;
+
+	_cchshf(cimagf(z), &ch, &sh);
+	w = sinf(crealf(z)) * ch + (cosf(crealf(z)) * sh) * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/csinh.c b/packages/language/c/libm/current/src/complex/csinh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/csinh.c
@@ -0,0 +1,80 @@
+/* $NetBSD: csinh.c,v 1.1 2007/08/20 16:01:36 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<csinh>>, <<csinhf>>---complex hyperbolic sine
+
+INDEX
+        csinh
+INDEX
+        csinhf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex csinh(double complex <[z]>);
+       float complex csinhf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute the complex hyperbolic sine of <[z]>.
+
+        <<ccoshf>> is identical to <<ccosh>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        These functions return the complex hyperbolic sine value.
+
+PORTABILITY
+        <<csinh>> and <<csinhf>> are ISO C99
+
+QUICKREF
+        <<csinh>> and <<csinhf>> are ISO C99
+
+*/
+
+#include <complex.h>
+#include <math.h>
+
+double complex
+csinh(double complex z)
+{
+	double complex w;
+	double x, y;
+
+	x = creal(z);
+	y = cimag(z);
+	w = sinh(x) * cos(y) + (cosh(x) * sin(y)) * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/csinhf.c b/packages/language/c/libm/current/src/complex/csinhf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/csinhf.c
@@ -0,0 +1,48 @@
+/* $NetBSD: csinhf.c,v 1.1 2007/08/20 16:01:37 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+
+float complex
+csinhf(float complex z)
+{
+	float complex w;
+	float x, y;
+
+	x = crealf(z);
+	y = cimagf(z);
+	w = sinhf(x) * cosf(y) + (coshf(x) * sinf(y)) * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/csqrt.c b/packages/language/c/libm/current/src/complex/csqrt.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/csqrt.c
@@ -0,0 +1,137 @@
+/* $NetBSD: csqrt.c,v 1.1 2007/08/20 16:01:37 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<csqrt>>, <<csqrtf>>---complex square root
+
+INDEX
+        csqrt
+INDEX
+        csqrtf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex csqrt(double complex <[z]>);
+       float complex csqrtf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute the complex square root of <[z]>, with 
+        a branch cut along the negative real axis. 
+
+        <<csqrtf>> is identical to <<csqrt>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        The csqrt functions return the complex square root value, in 
+        the range of the right halfplane (including the imaginary axis).
+
+PORTABILITY
+        <<csqrt>> and <<csqrtf>> are ISO C99
+
+QUICKREF
+        <<csqrt>> and <<csqrtf>> are ISO C99
+
+*/
+
+
+#include <complex.h>
+#include <math.h>
+
+double complex
+csqrt(double complex z)
+{
+	double complex w;
+	double x, y, r, t, scale;
+
+	x = creal (z);
+	y = cimag (z);
+
+	if (y == 0.0) {
+		if (x == 0.0) {
+			w = 0.0 + y * I;
+		} else {
+			r = fabs(x);
+			r = sqrt(r);
+			if (x < 0.0) {
+				w = 0.0 + r * I;
+			} else {
+				w = r + y * I;
+			}
+		}
+		return w;
+	}
+	if (x == 0.0) {
+		r = fabs(y);
+		r = sqrt(0.5 * r);
+		if (y > 0)
+			w = r + r * I;
+		else
+			w = r - r * I;
+		return w;
+	}
+	/* Rescale to avoid internal overflow or underflow.  */
+	if ((fabs(x) > 4.0) || (fabs(y) > 4.0)) {
+		x *= 0.25;
+		y *= 0.25;
+		scale = 2.0;
+	} else {
+#if 1
+		x *= 1.8014398509481984e16;  /* 2^54 */
+		y *= 1.8014398509481984e16;
+		scale = 7.450580596923828125e-9; /* 2^-27 */
+#else
+		x *= 4.0;
+		y *= 4.0;
+		scale = 0.5;
+#endif
+	}
+	w = x + y * I;
+	r = cabs(w);
+	if (x > 0) {
+		t = sqrt(0.5 * r + 0.5 * x);
+		r = scale * fabs((0.5 * y) / t );
+		t *= scale;
+	} else {
+		r = sqrt(0.5 * r - 0.5 * x);
+		t = scale * fabs((0.5 * y) / r);
+		r *= scale;
+	}
+	if (y < 0)
+		w = t - r * I;
+	else
+		w = t + r * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/csqrtf.c b/packages/language/c/libm/current/src/complex/csqrtf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/csqrtf.c
@@ -0,0 +1,102 @@
+/* $NetBSD: csqrtf.c,v 1.1 2007/08/20 16:01:37 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+
+float complex
+csqrtf(float complex z)
+{
+	float complex w;
+	float x, y, r, t, scale;
+
+	x = crealf (z);
+	y = cimagf (z);
+
+	if (y == 0.0f) {
+		if (x < 0.0f) {
+			w = 0.0f + sqrtf(-x) * I;
+			return w;
+		} else if (x == 0.0f) {
+			return (0.0f + y * I);
+		} else {
+			w = sqrtf(x) + y * I;
+			return w;
+		}
+	}
+
+	if (x == 0.0f) {
+		r = fabsf(y);
+		r = sqrtf(0.5f * r);
+		if (y > 0)
+			w = r + r * I;
+		else
+			w = r - r * I;
+		return w;
+	}
+
+	/* Rescale to avoid internal overflow or underflow.  */
+	if ((fabsf(x) > 4.0f) || (fabsf(y) > 4.0f)) {
+		x *= 0.25f;
+		y *= 0.25f;
+		scale = 2.0f;
+	} else {
+#if 1
+		x *= 6.7108864e7f; /* 2^26 */
+		y *= 6.7108864e7f;
+		scale = 1.220703125e-4f; /* 2^-13 */
+#else
+		x *= 4.0f;
+		y *= 4.0f;
+		scale = 0.5f;
+#endif
+	}
+	w = x + y * I;
+	r = cabsf(w);
+	if( x > 0 ) {
+		t = sqrtf(0.5f * r + 0.5f * x);
+		r = scale * fabsf((0.5f * y) / t);
+		t *= scale;
+	} else {
+		r = sqrtf(0.5f * r - 0.5f * x);
+		t = scale * fabsf((0.5f * y) / r);
+		r *= scale;
+	}
+
+	if (y < 0)
+		w = t - r * I;
+	else
+		w = t + r * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/ctan.c b/packages/language/c/libm/current/src/complex/ctan.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/ctan.c
@@ -0,0 +1,91 @@
+/* $NetBSD: ctan.c,v 1.1 2007/08/20 16:01:37 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<ctan>>, <<ctanf>>---complex tangent
+
+INDEX
+        ctan
+INDEX
+        ctanf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex ctan(double complex <[z]>);
+       float complex ctanf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute the complex tangent of <[z]>.
+
+        <<ctanf>> is identical to <<ctan>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        These functions return the complex tangent value.
+
+PORTABILITY
+        <<ctan>> and <<ctanf>> are ISO C99
+
+QUICKREF
+        <<ctan>> and <<ctanf>> are ISO C99
+
+*/
+
+
+#include <complex.h>
+#include <math.h>
+#include "cephes_subr.h"
+
+double complex
+ctan(double complex z)
+{
+	double complex w;
+	double d;
+
+	d = cos(2.0 * creal(z)) + cosh(2.0 * cimag(z));
+
+	if (fabs(d) < 0.25)
+		d = _ctans(z);
+
+	if (d == 0.0) {
+		/* mtherr ("ctan", OVERFLOW); */
+		w = HUGE_VAL + HUGE_VAL * I;
+		return w;
+	}
+
+	w = sin(2.0 * creal(z)) / d + (sinh(2.0 * cimag(z)) / d) * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/ctanf.c b/packages/language/c/libm/current/src/complex/ctanf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/ctanf.c
@@ -0,0 +1,58 @@
+/* $NetBSD: ctanf.c,v 1.1 2007/08/20 16:01:38 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+#include "cephes_subrf.h"
+
+float complex
+ctanf(float complex z)
+{
+	float complex w;
+	float d;
+
+	d = cosf(2.0f * crealf(z)) + coshf(2.0f * cimagf(z));
+
+	if (fabsf(d) < 0.25f)
+		d = _ctansf(z);
+
+	if (d == 0.0f) {
+		/* mtherr ("ctan", OVERFLOW); */
+		w = HUGE_VALF + HUGE_VALF * I;
+		return w;
+	}
+
+	w = sinf(2.0f * crealf(z)) / d + (sinhf(2.0f * cimagf(z)) / d) * I;
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/ctanh.c b/packages/language/c/libm/current/src/complex/ctanh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/ctanh.c
@@ -0,0 +1,83 @@
+/* $NetBSD: ctanh.c,v 1.1 2007/08/20 16:01:38 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+/*
+FUNCTION
+        <<ctanh>>, <<ctanf>>---complex hyperbolic tangent
+
+INDEX
+        ctanh
+INDEX
+        ctanhf
+
+ANSI_SYNOPSIS
+       #include <complex.h>
+       double complex ctanh(double complex <[z]>);
+       float complex ctanhf(float complex <[z]>);
+
+
+DESCRIPTION
+        These functions compute the complex hyperbolic tangent of <[z]>.
+
+        <<ctanhf>> is identical to <<ctanh>>, except that it performs
+        its calculations on <<floats complex>>.
+
+RETURNS
+        These functions return the complex hyperbolic tangent value.
+
+PORTABILITY
+        <<ctanh>> and <<ctanhf>> are ISO C99
+
+QUICKREF
+        <<ctanh>> and <<ctanhf>> are ISO C99
+
+*/
+
+
+#include <complex.h>
+#include <math.h>
+
+double complex
+ctanh(double complex z)
+{
+	double complex w;
+	double x, y, d;
+
+	x = creal(z);
+	y = cimag(z);
+	d = cosh(2.0 * x) + cos(2.0 * y);
+	w = sinh(2.0 * x) / d  +  (sin(2.0 * y) / d) * I;
+
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/complex/ctanhf.c b/packages/language/c/libm/current/src/complex/ctanhf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/complex/ctanhf.c
@@ -0,0 +1,50 @@
+/* $NetBSD: ctanhf.c,v 1.1 2007/08/20 16:01:38 drochner Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software written by Stephen L. Moshier.
+ * It is redistributed by the NetBSD Foundation by permission of the author.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * imported and modified include for newlib 2010/10/03 
+ * Marco Atzeri <marco_atzeri@yahoo.it>
+ */
+
+#include <complex.h>
+#include <math.h>
+
+float complex
+ctanhf(float complex z)
+{
+	float complex w;
+	float x, y, d;
+
+	x = crealf(z);
+	y = cimagf(z);
+	d = coshf(2.0f * x) + cosf(2.0f * y);
+	w = sinhf(2.0f * x) / d  +  (sinf(2.0f * y) / d) * I;
+
+	return w;
+}
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_acos.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_acos.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_acos.c
@@ -0,0 +1,103 @@
+//===========================================================================
+//
+//      wf_acos.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrap_acosf(x)
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef _HAVE_STDC
+	float acosf(float x)		/* wrapper acosf */
+#else
+	float acosf(x)			/* wrapper acosf */
+	float x;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_acosf(x);
+#else
+    float z;
+
+    z = __ieee754_acosf(x);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE || isnanf(x)) return z;
+    if(fabsf(x)>(float)1.0) {
+        return __kernel_standard_float(x,x,1); /* acos(|x|>1) */
+    } else
+        return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_acos.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_acosh.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_acosh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_acosh.c
@@ -0,0 +1,103 @@
+//===========================================================================
+//
+//      wf_acosh.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+/*
+ * wrapper acoshf(x)
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float acoshf(float x)		/* wrapper acoshf */
+#else
+	float acoshf(x)			/* wrapper acoshf */
+	float x;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_acoshf(x);
+#else
+    float z;
+    z = __ieee754_acoshf(x);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE || isnanf(x)) return z;
+    if(x<1.0) {
+        return __kernel_standard(x,x,29); /* acosh(x<1) */
+    } else
+        return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_acosh.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_asin.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_asin.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_asin.c
@@ -0,0 +1,104 @@
+//===========================================================================
+//
+//      wf_asin.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+/*
+ * wrapper asinf(x)
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float asinf(float x)		/* wrapper asinf */
+#else
+	float asinf(x)			/* wrapper asinf */
+	float x;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_asinf(x);
+#else
+    float z;
+
+    z = __ieee754_asinf(x);
+    if( cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE || isnanf(x)) return z;
+    if(fabsf(x)>(float)1.0) {
+        return __kernel_standard_float(x,x,2); /* asin(|x|>1) */
+    } else
+        return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_asin.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_atan2.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_atan2.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_atan2.c
@@ -0,0 +1,93 @@
+//===========================================================================
+//
+//      wf_atan2.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+/*
+ * wrapper atan2f(y,x)
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float atan2f(float y, float x)		/* wrapper atan2f */
+#else
+	float atan2f(y,x)			/* wrapper atan2 */
+	float y,x;
+#endif
+{
+	return __ieee754_atan2f(y,x);
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_atan2.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_atanh.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_atanh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_atanh.c
@@ -0,0 +1,105 @@
+//===========================================================================
+//
+//      wf_atanh.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/*
+ * wrapper atanhf(x)
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float atanhf(float x)		/* wrapper atanhf */
+#else
+	float atanhf(x)			/* wrapper atanhf */
+	float x;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_atanhf(x);
+#else
+    float z,y;
+    z = __ieee754_atanhf(x);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE || isnanf(x)) return z;
+    y = fabs(x);
+    if(y>=1.0) {
+        if(y>1.0)
+            return __kernel_standard(x,x,30); /* atanh(|x|>1) */
+        else
+            return __kernel_standard(x,x,31); /* atanh(|x|==1) */
+    } else
+        return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_atanh.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_cosh.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_cosh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_cosh.c
@@ -0,0 +1,102 @@
+//===========================================================================
+//
+//      wf_cosh.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrapper coshf(x)
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float coshf(float x)		/* wrapper coshf */
+#else
+	float coshf(x)			/* wrapper coshf */
+	float x;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_coshf(x);
+#else
+    float z;
+    z = __ieee754_coshf(x);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE || isnanf(x)) return z;
+    if(fabsf(x)>(float)8.9415985107e+01) {
+        return __kernel_standard(x,x,5); /* cosh overflow */
+    } else
+        return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_cosh.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_exp.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_exp.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_exp.c
@@ -0,0 +1,114 @@
+//===========================================================================
+//
+//      wf_exp.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrapper expf(x)
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+o_threshold=  8.8721679688e+01,  /* 0x42b17180 */
+u_threshold= -1.0397208405e+02;  /* 0xc2cff1b5 */
+
+#ifdef __STDC__
+	float expf(float x)		/* wrapper expf */
+#else
+	float expf(x)			/* wrapper expf */
+	float x;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_expf(x);
+#else
+	float z;
+	//struct exception exc;
+	z = __ieee754_expf(x);
+	if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE) return z;
+	if(finitef(x)) {
+	    if(x>o_threshold)
+	        return __kernel_standard(x,x,6); /* exp overflow */
+       else if(x<u_threshold)
+            return __kernel_standard(x,x,7); /* exp underflow */
+	}
+	return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_exp.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_fmod.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_fmod.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_fmod.c
@@ -0,0 +1,102 @@
+//===========================================================================
+//
+//      w_fmod.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrapper fmodf(x,y)
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float fmodf(float x, float y)	/* wrapper fmodf */
+#else
+	float fmodf(x,y)		/* wrapper fmodf */
+	float x,y;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_fmodf(x,y);
+#else
+    float z;
+    z = __ieee754_fmodf(x,y);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE ||isnanf(y)||isnanf(x)) return z;
+    if(y==0.0) {
+        return __kernel_standard(x,y,27); /* fmod(x,0) */
+    } else
+        return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_fmod.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_gamma.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_gamma.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_gamma.c
@@ -0,0 +1,103 @@
+//===========================================================================
+//
+//      wf_gamma.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+#include <math.h>
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float gammaf(float x)
+#else
+	float gammaf(x)
+	float x;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_gammaf_r(x,&signgam);
+#else
+    float y;
+    y = __ieee754_gammaf_r(x,&signgam);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE) return y;
+    if(!finitef(y)&&finitef(x)) {
+        if(floorf(x)==x&&x<=0.0)
+            return __kernel_standard(x,x,41); /* gamma pole */
+        else
+            return __kernel_standard(x,x,40); /* gamma overflow */
+    } else
+        return y;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_gamma.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_gamma_r.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_gamma_r.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_gamma_r.c
@@ -0,0 +1,106 @@
+//===========================================================================
+//
+//      wf_gamma_r.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrapper float gammaf_r(float x, int *signgamp)
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float gammaf_r(float x, int *signgamp) /* wrapper lgammaf_r */
+#else
+	float gammaf_r(x,signgamp)              /* wrapper lgammaf_r */
+	float x; int *signgamp;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_gammaf_r(x,signgamp);
+#else
+    float y;
+    y = __ieee754_gammaf_r(x,signgamp);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE) return y;
+    if(!finitef(y)&&finitef(x)) {
+        if(floorf(x)==x&&x<=0.0)
+            return __kernel_standard(x,x,41); /* gamma pole */
+        else
+            return __kernel_standard(x,x,40); /* gamma overflow */
+    } else
+        return y;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_gamma_r.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_hypot.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_hypot.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_hypot.c
@@ -0,0 +1,102 @@
+//===========================================================================
+//
+//      wf_hypot.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrapper hypotf(x,y)
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float hypotf(float x, float y)	/* wrapper hypotf */
+#else
+	float hypotf(x,y)		/* wrapper hypotf */
+	float x,y;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_hypotf(x,y);
+#else
+    float z;
+    z = __ieee754_hypotf(x,y);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE) return z;
+    if((!finitef(z))&&finitef(x)&&finitef(y))
+        return __kernel_standard(x,y,4); /* hypot overflow */
+    else
+        return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_hypot.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_j0.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_j0.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_j0.c
@@ -0,0 +1,129 @@
+//===========================================================================
+//
+//      w_j0.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrapper j0f(float x), y0f(float x)
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float j0f(float x)		/* wrapper j0f */
+#else
+	float j0f(x)			/* wrapper j0f */
+	float x;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_j0f(x);
+#else
+    float z = __ieee754_j0f(x);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE || isnanf(x)) return z;
+    if(fabsf(x)>(float)X_TLOSS) {
+        return __kernel_standard(x,x,34); /* j0(|x|>X_TLOSS) */
+    } else
+        return z;
+#endif
+}
+
+#ifdef __STDC__
+	float y0f(float x)		/* wrapper y0f */
+#else
+	float y0f(x)			/* wrapper y0f */
+	float x;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_y0f(x);
+#else
+    float z;
+    z = __ieee754_y0f(x);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE || isnanf(x) ) return z;
+    if(x <= 0.0){
+        if(x==0.0)
+            /* d= -one/(x-x); */
+            return __kernel_standard(x,x,8);
+        else
+            /* d = zero/(x-x); */
+            return __kernel_standard(x,x,9);
+    }
+    if(x>X_TLOSS) {
+        return __kernel_standard(x,x,35); /* y0(x>X_TLOSS) */
+    } else
+        return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_j0.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_j1.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_j1.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_j1.c
@@ -0,0 +1,130 @@
+//===========================================================================
+//
+//      wf_j1.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrapper of j1f,y1f
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float j1f(float x)		/* wrapper j1f */
+#else
+	float j1f(x)			/* wrapper j1f */
+	float x;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_j1f(x);
+#else
+    float z;
+    z = __ieee754_j1f(x);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE || isnanf(x) ) return z;
+    if(fabs(x)>X_TLOSS) {
+        return __kernel_standard(x,x,36); /* j1(|x|>X_TLOSS) */
+    } else
+        return z;
+#endif
+}
+
+#ifdef __STDC__
+	float y1f(float x)		/* wrapper y1f */
+#else
+	float y1f(x)			/* wrapper y1f */
+	float x;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_y1f(x);
+#else
+    float z;
+    z = __ieee754_y1f(x);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE || isnanf(x) ) return z;
+    if(x <= 0.0){
+        if(x==0.0)
+            /* d= -one/(x-x); */
+            return __kernel_standard(x,x,10);
+        else
+            /* d = zero/(x-x); */
+            return __kernel_standard(x,x,11);
+    }
+    if(x>X_TLOSS) {
+        return __kernel_standard(x,x,37); /* y1(x>X_TLOSS) */
+    } else
+        return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_j1.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_jn.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_jn.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_jn.c
@@ -0,0 +1,117 @@
+//===========================================================================
+//
+//      wf_jn.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+#include "mathincl/fdlibm.h"
+
+	float jnf(int n, float x)	/* wrapper jnf */
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_jnf(n,x);
+#else
+    float z;
+    z = __ieee754_jnf(n,x);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE || isnanf(x) ) return z;
+    if(fabsf(x)>(float)X_TLOSS) {
+        return __kernel_standard((double)n,x,38); /* jn(|x|>X_TLOSS,n) */
+    } else
+        return z;
+#endif
+}
+
+
+	float ynf(int n, float x)	/* wrapper ynf */
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_ynf(n,x);
+#else
+    float z;
+    z = __ieee754_ynf(n,x);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE || isnanf(x) ) return z;
+    if(x <= 0.0){
+        if(x==0.0)
+        /* d= -one/(x-x); */
+        return __kernel_standard((double)n,x,12);
+    else
+        /* d = zero/(x-x); */
+        return __kernel_standard((double)n,x,13);
+    }
+    if(x>X_TLOSS) {
+        return __kernel_standard((double)n,x,39); /* yn(x>X_TLOSS,n) */
+    } else
+        return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_jn.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_lgamma.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_lgamma.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_lgamma.c
@@ -0,0 +1,103 @@
+//===========================================================================
+//
+//      wf_lgamma.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+#include <math.h>
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float lgammaf(float x)
+#else
+	float lgammaf(x)
+	float x;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_lgammaf_r(x,&signgam);
+#else
+    float y;
+    y = __ieee754_lgammaf_r(x,&signgam);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE) return y;
+    if(!finitef(y)&&finitef(x)) {
+        if(floorf(x)==x&&x<=0.0)
+            return __kernel_standard(x,x,15); /* lgamma pole */
+        else
+            return __kernel_standard(x,x,14); /* lgamma overflow */
+    } else
+        return y;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_lgamma.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_lgamma_r.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_lgamma_r.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_lgamma_r.c
@@ -0,0 +1,105 @@
+//===========================================================================
+//
+//      w_lgamma_r.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrapper float lgammaf_r(float x, int *signgamp)
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float lgammaf_r(float x, int *signgamp) /* wrapper lgammaf_r */
+#else
+	float lgammaf_r(x,signgamp)              /* wrapper lgammaf_r */
+	float x; int *signgamp;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_lgammaf_r(x,signgamp);
+#else
+    float y;
+    y = __ieee754_lgammaf_r(x,signgamp);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE) return y;
+        if(!finitef(y)&&finitef(x)) {
+            if(floorf(x)==x&&x<=0.0)
+                return __kernel_standard(x,x,15); /* lgamma pole */
+            else
+                return __kernel_standard(x,x,14); /* lgamma overflow */
+        } else
+            return y;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_lgamma_r.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_log.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_log.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_log.c
@@ -0,0 +1,102 @@
+//===========================================================================
+//
+//      wf_log.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrapper logf(x)
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float logf(float x)		/* wrapper logf */
+#else
+	float logf(x)			/* wrapper logf */
+	float x;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_logf(x);
+#else
+	float z;
+    z = __ieee754_logf(x);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE || isnan(x) || x > 0.0) return z;
+    if(x==0.0)
+        return __kernel_standard_float(x,x,16); /* log(0) */
+    else
+        return __kernel_standard_float(x,x,17); /* log(x<0) */
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_log.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_log10.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_log10.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_log10.c
@@ -0,0 +1,111 @@
+//===========================================================================
+//
+//      w_log10.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrapper log10f(X)
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float log10f(float x)		/* wrapper log10f */
+#else
+	float log10f(x)			/* wrapper log10f */
+	float x;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_log10f(x);
+#else
+	float z;
+    cyg_uint32 compat_mode = cyg_libm_get_compat_mode();
+
+	z = __ieee754_log10f(x);
+    if(
+#ifdef CYGOPT_LIBM_COMPAT_POSIX_IEEE
+       compat_mode == CYGNUM_LIBM_COMPAT_POSIX ||
+#endif
+       compat_mode == CYGNUM_LIBM_COMPAT_IEEE || isnanf(x)) return z;
+    if(x<=0.0) {
+        if(x==0.0)
+            return __kernel_standard(x,x,18); /* log10(0) */
+        else
+           return __kernel_standard(x,x,19); /* log10(x<0) */
+    } else
+        return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_log10.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_pow.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_pow.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_pow.c
@@ -0,0 +1,119 @@
+//========================================================================
+//
+//      wf_pow.c
+//
+//      Part of the standard mathematical function library
+//
+//========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     jlarmour
+// Contributors: visar, ilijak
+// Date:          1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrapper powf(x,y) return x**y
+ */
+
+#include "mathincl/fdlibm.h"
+
+	float powf(float x, float y)	/* wrapper powf */
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return  __ieee754_powf(x,y);
+#else
+	float z;
+    z=__ieee754_powf(x,y);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE||
+        isnan(y))
+        return z;
+    if(isnan(x)) {
+        if(y==0.0)
+            return __kernel_standard(x,y,42); /* pow(NaN,0.0) */
+        else
+            return z;
+    }
+    if(x==0.0){
+        if(y==0.0)
+            return __kernel_standard(x,y,20); /* pow(0.0,0.0) */
+        if(finitef(y)&&y<0.0)
+            return __kernel_standard(x,y,23); /* pow(0.0,negative) */
+    return z;
+    }
+    if(!finitef(z)) {
+        if(finitef(x)&&finitef(y)) {
+            if(isnan(z))
+                return __kernel_standard(x,y,24);/* pow neg**non-int */
+            else
+                return __kernel_standard(x,y,21); /* pow overflow */
+        }
+    }
+    if(z==0.0&&finitef(x)&&finitef(y))
+        return __kernel_standard(x,y,22); /* pow underflow */
+    return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_pow.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_remainder.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_remainder.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_remainder.c
@@ -0,0 +1,103 @@
+//===========================================================================
+//
+//      wf_remainder.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrapper remainderf(x,p)
+ */
+
+#include "mathincl/fdlibm.h"
+//#include <errno.h>
+
+#ifdef __STDC__
+	float remainderf(float x, float y)	/* wrapper remainder */
+#else
+	float remainderf(x,y)			/* wrapper remainder */
+	float x,y;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_remainderf(x,y);
+#else
+    double z;
+    z = __ieee754_remainderf(x,y);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE || isnanf(y)) return z;
+    if(y==0.0)
+        return __kernel_standard(x,y,28); /* remainder(x,0) */
+    else
+        return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_remainder.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_scalb.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_scalb.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_scalb.c
@@ -0,0 +1,124 @@
+//===========================================================================
+//
+//      wf_scalb.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrapper scalbf(float x, float fn) is provide for
+ * passing various standard test suite. One
+ * should use scalbn() instead.
+ */
+
+// CONFIGURATION
+
+
+#include "mathincl/fdlibm.h"
+#ifndef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+# include <errno.h>
+#endif
+
+#ifdef __STDC__
+#ifdef CYGFUN_LIBM_SVID3_scalb
+	float scalbf(float x, float fn)		/* wrapper scalbf */
+#else
+	float scalbf(float x, int fn)		/* wrapper scalbf */
+#endif
+#else
+	float scalbf(x,fn)			/* wrapper scalbf */
+#ifdef CYGFUN_LIBM_SVID3_scalb
+	float x,fn;
+#else
+	float x; int fn;
+#endif
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_scalbf(x,fn);
+#else
+    double z;
+    z = __ieee754_scalbf(x,fn);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE) return z;
+    if(!(finitef(z)||isnanf(z))&&finitef(x)) {
+        return __kernel_standard(x,(double)fn,32); /* scalb overflow */
+    }
+    if(z==0.0&&z!=x) {
+        return __kernel_standard(x,(double)fn,33); /* scalb underflow */
+    }
+#ifdef CYGFUN_LIBM_SVID3_scalb
+    if(!finitef(fn)) errno = ERANGE;
+#endif
+    return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_scalb.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_sinh.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_sinh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_sinh.c
@@ -0,0 +1,104 @@
+//===========================================================================
+//
+//      wf_sinh.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrapper sinhf(x)
+ */
+
+// CONFIGURATION
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float sinhf(float x)		/* wrapper sinhf */
+#else
+	float sinhf(x)			/* wrapper sinhf */
+	float x;
+#endif
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_sinhf(x);
+#else
+    float z;
+    z = __ieee754_sinhf(x);
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE) return z;
+    if(!finitef(z)&&finitef(x)) {
+        return __kernel_standard(x,x,25); /* sinh overflow */
+    } else
+        return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_sinh.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-api/wf_sqrt.c b/packages/language/c/libm/current/src/float/ieee754-api/wf_sqrt.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-api/wf_sqrt.c
@@ -0,0 +1,98 @@
+//===========================================================================
+//
+//      wf_sqrt.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * wrapper sqrtf(x)
+ */
+
+#include "mathincl/fdlibm.h"
+
+float sqrtf(float x)		/* wrapper sqrtf */
+
+{
+#ifdef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+	return __ieee754_sqrtf(x);
+#else
+	float z;
+	z = __ieee754_sqrtf(x);
+	if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE || isnan(x)) return z;
+        if(x<0.0) {
+            return __kernel_standard(x,x,26); /* sqrt(negative) */
+        } else
+            return z;
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF wf_sqrtf.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_acos.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_acos.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_acos.c
@@ -0,0 +1,151 @@
+//===========================================================================
+//
+//      ef_acos.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_acos.c -- float version of e_acos.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+one =  1.0000000000e+00, /* 0x3F800000 */
+pi =  3.1415925026e+00, /* 0x40490fda */
+pio2_hi =  1.5707962513e+00, /* 0x3fc90fda */
+pio2_lo =  7.5497894159e-08, /* 0x33a22168 */
+pS0 =  1.6666667163e-01, /* 0x3e2aaaab */
+pS1 = -3.2556581497e-01, /* 0xbea6b090 */
+pS2 =  2.0121252537e-01, /* 0x3e4e0aa8 */
+pS3 = -4.0055535734e-02, /* 0xbd241146 */
+pS4 =  7.9153501429e-04, /* 0x3a4f7f04 */
+pS5 =  3.4793309169e-05, /* 0x3811ef08 */
+qS1 = -2.4033949375e+00, /* 0xc019d139 */
+qS2 =  2.0209457874e+00, /* 0x4001572d */
+qS3 = -6.8828397989e-01, /* 0xbf303361 */
+qS4 =  7.7038154006e-02; /* 0x3d9dc62e */
+
+#ifdef __STDC__
+	float __ieee754_acosf(float x)
+#else
+	float __ieee754_acosf(x)
+	float x;
+#endif
+{
+	float z,p,q,r,w,s,c,df;
+	__int32_t hx,ix;
+	hx = CYG_LIBM_WORD(x);
+	ix = hx&0x7fffffff;
+	if(ix==0x3f800000) {		/* |x|==1 */
+	    if(hx>0) return 0.0;	/* acos(1) = 0  */
+	    else return pi+(float)2.0*pio2_lo;	/* acos(-1)= pi */
+	} else if(ix>0x3f800000) {	/* |x| >= 1 */
+	    return (x-x)/(x-x);		/* acos(|x|>1) is NaN */
+	}
+	if(ix<0x3f000000) {	/* |x| < 0.5 */
+	    if(ix<=0x23000000) return pio2_hi+pio2_lo;/*if|x|<2**-57*/
+	    z = x*x;
+	    p = z*(pS0+z*(pS1+z*(pS2+z*(pS3+z*(pS4+z*pS5)))));
+	    q = one+z*(qS1+z*(qS2+z*(qS3+z*qS4)));
+	    r = p/q;
+	    return pio2_hi - (x - (pio2_lo-x*r));
+	} else  if (hx<0) {		/* x < -0.5 */
+	    z = (one+x)*(float)0.5;
+	    p = z*(pS0+z*(pS1+z*(pS2+z*(pS3+z*(pS4+z*pS5)))));
+	    q = one+z*(qS1+z*(qS2+z*(qS3+z*qS4)));
+	    s = __ieee754_sqrtf(z);
+	    r = p/q;
+	    w = r*s-pio2_lo;
+	    return pi - (float)2.0*(s+w);
+	} else {			/* x > 0.5 */
+	    __int32_t idf;
+	    z = (one-x)*(float)0.5;
+	    s = __ieee754_sqrtf(z);
+	    df = s;
+	    idf = CYG_LIBM_WORD(df);
+	    SET_FLOAT_WORD(df,idf&0xfffff000);
+	    c  = (z-df*df)/(s+df);
+	    p = z*(pS0+z*(pS1+z*(pS2+z*(pS3+z*(pS4+z*pS5)))));
+	    q = one+z*(qS1+z*(qS2+z*(qS3+z*qS4)));
+	    r = p/q;
+	    w = r*s+c;
+	    return (float)2.0*(df+w);
+	}
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_acos.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_acosh.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_acosh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_acosh.c
@@ -0,0 +1,120 @@
+//===========================================================================
+//
+//      ef_acosh.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_acosh.c -- float version of e_acosh.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+one	= 1.0,
+ln2	= 6.9314718246e-01;  /* 0x3f317218 */
+
+#ifdef __STDC__
+	float __ieee754_acoshf(float x)
+#else
+	float __ieee754_acoshf(x)
+	float x;
+#endif
+{
+	float t;
+	__int32_t hx;
+	hx = CYG_LIBM_WORD(x);
+	if(hx<0x3f800000) {		/* x < 1 */
+	    return (x-x)/(x-x);
+	} else if(hx >=0x4d800000) {	/* x > 2**28 */
+	    if(!FLT_UWORD_IS_FINITE(hx)) {	/* x is inf of NaN */
+	        return x+x;
+	    } else
+		return __ieee754_logf(x)+ln2;	/* acosh(huge)=log(2x) */
+	} else if (hx==0x3f800000) {
+	    return 0.0;			/* acosh(1) = 0 */
+	} else if (hx > 0x40000000) {	/* 2**28 > x > 2 */
+	    t=x*x;
+	    return __ieee754_logf((float)2.0*x-one/(x+__ieee754_sqrtf(t-one)));
+	} else {			/* 1<x<2 */
+	    t = x-one;
+	    return log1pf(t+__ieee754_sqrtf((float)2.0*t+t*t));
+	}
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF e_acosh.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_asin.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_asin.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_asin.c
@@ -0,0 +1,151 @@
+//===========================================================================
+//
+//      ef_asin.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+one =  1.0000000000e+00, /* 0x3F800000 */
+huge =  1.000e+30,
+pio2_hi = 1.57079637050628662109375f,
+pio2_lo = -4.37113900018624283e-8f,
+pio4_hi = 0.785398185253143310546875f,
+	/* coefficient for R(x^2) */
+pS0 =  1.6666667163e-01, /* 0x3e2aaaab */
+pS1 = -3.2556581497e-01, /* 0xbea6b090 */
+pS2 =  2.0121252537e-01, /* 0x3e4e0aa8 */
+pS3 = -4.0055535734e-02, /* 0xbd241146 */
+pS4 =  7.9153501429e-04, /* 0x3a4f7f04 */
+pS5 =  3.4793309169e-05, /* 0x3811ef08 */
+qS1 = -2.4033949375e+00, /* 0xc019d139 */
+qS2 =  2.0209457874e+00, /* 0x4001572d */
+qS3 = -6.8828397989e-01, /* 0xbf303361 */
+qS4 =  7.7038154006e-02; /* 0x3d9dc62e */
+
+#ifdef __STDC__
+	float __ieee754_asinf(float x)
+#else
+	float __ieee754_asinf(x)
+	float x;
+#endif
+{
+	float t,w,p,q,c,r,s;
+	__int32_t hx,ix;
+	hx = CYG_LIBM_WORD(x);
+	ix = hx&0x7fffffff;
+	if(ix==0x3f800000) {
+		/* asin(1)=+-pi/2 with inexact */
+	    return x*pio2_hi+x*pio2_lo;
+	} else if(ix> 0x3f800000) {	/* |x|>= 1 */
+	    return (x-x)/(x-x);		/* asin(|x|>1) is NaN */
+	} else if (ix<0x3f000000) {	/* |x|<0.5 */
+	    if(ix<0x32000000) {		/* if |x| < 2**-27 */
+		if(huge+x>one) return x;/* return x with inexact if x!=0*/
+          } else {
+		t = x*x;
+		p = t*(pS0+t*(pS1+t*(pS2+t*(pS3+t*(pS4+t*pS5)))));
+		q = one+t*(qS1+t*(qS2+t*(qS3+t*qS4)));
+		w = p/q;
+		return x+x*w;
+          }
+	}
+	/* 1> |x|>= 0.5 */
+	w = one-fabsf(x);
+	t = w*(float)0.5;
+	p = t*(pS0+t*(pS1+t*(pS2+t*(pS3+t*(pS4+t*pS5)))));
+	q = one+t*(qS1+t*(qS2+t*(qS3+t*qS4)));
+	s = __ieee754_sqrtf(t);
+	if(ix>=0x3F79999A) {	/* if |x| > 0.975 */
+	    w = p/q;
+	    t = pio2_hi-((float)2.0*(s+s*w)-pio2_lo);
+	} else {
+	    __int32_t iw;
+	    w  = s;
+	    iw = CYG_LIBM_WORD(w);
+	    SET_FLOAT_WORD(w,iw&0xfffff000);
+	    c  = (t-w*w)/(s+w);
+	    r  = p/q;
+	    p  = (float)2.0*s*r-(pio2_lo-(float)2.0*c);
+	    q  = pio4_hi-(float)2.0*w;
+	    t  = pio4_hi-(p-q);
+	}
+	if(hx>0) return t; else return -t;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_asin.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_atan2.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_atan2.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_atan2.c
@@ -0,0 +1,167 @@
+//===========================================================================
+//
+//      e_atan2.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_atan2.c -- float version of e_atan2.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+tiny  = 1.0e-30,
+zero  = 0.0,
+pi_o_4  = 7.8539818525e-01, /* 0x3f490fdb */
+pi_o_2  = 1.5707963705e+00, /* 0x3fc90fdb */
+pi      = 3.1415927410e+00,  /* 0x40490fdb */
+pi_lo   = -8.7422776573e-08; /* 0xb3bbbd2e */
+
+#ifdef __STDC__
+	float __ieee754_atan2f(float y, float x)
+#else
+	float __ieee754_atan2f(y,x)
+	float  y,x;
+#endif
+{
+	float z;
+	__int32_t k,m,hx,hy,ix,iy;
+
+	hx = CYG_LIBM_WORD(x);
+	ix = hx&0x7fffffff;
+	hy = CYG_LIBM_WORD(y);
+	iy = hy&0x7fffffff;
+	if(FLT_UWORD_IS_NAN(ix)||
+	   FLT_UWORD_IS_NAN(iy))	/* x or y is NaN */
+	   return x+y;
+	if(hx==0x3f800000) return atanf(y);   /* x=1.0 */
+	m = ((hy>>31)&1)|((hx>>30)&2);	/* 2*sign(x)+sign(y) */
+
+    /* when y = 0 */
+	if(FLT_UWORD_IS_ZERO(iy)) {
+	    switch(m) {
+		case 0:
+		case 1: return y;	/* atan(+-0,+anything)=+-0 */
+		case 2: return  pi+tiny;/* atan(+0,-anything) = pi */
+		case 3: return -pi-tiny;/* atan(-0,-anything) =-pi */
+	    }
+	}
+    /* when x = 0 */
+	if(FLT_UWORD_IS_ZERO(ix)) return (hy<0)?  -pi_o_2-tiny: pi_o_2+tiny;
+
+    /* when x is INF */
+	if(FLT_UWORD_IS_INFINITE(ix)) {
+	    if(FLT_UWORD_IS_INFINITE(iy)) {
+		switch(m) {
+		    case 0: return  pi_o_4+tiny;/* atan(+INF,+INF) */
+		    case 1: return -pi_o_4-tiny;/* atan(-INF,+INF) */
+		    case 2: return  (float)3.0*pi_o_4+tiny;/*atan(+INF,-INF)*/
+		    case 3: return (float)-3.0*pi_o_4-tiny;/*atan(-INF,-INF)*/
+		}
+	    } else {
+		switch(m) {
+		    case 0: return  zero  ;	/* atan(+...,+INF) */
+		    case 1: return -zero  ;	/* atan(-...,+INF) */
+		    case 2: return  pi+tiny  ;	/* atan(+...,-INF) */
+		    case 3: return -pi-tiny  ;	/* atan(-...,-INF) */
+		}
+	    }
+	}
+    /* when y is INF */
+	if(FLT_UWORD_IS_INFINITE(iy)) return (hy<0)? -pi_o_2-tiny: pi_o_2+tiny;
+
+    /* compute y/x */
+	k = (iy-ix)>>23;
+	if(k > 60) z=pi_o_2+(float)0.5*pi_lo;	/* |y/x| >  2**60 */
+	else if(hx<0&&k<-60) z=0.0;	/* |y|/x < -2**60 */
+	else z=atanf(fabsf(y/x));	/* safe to do y/x */
+	switch (m) {
+	    case 0: return       z  ;	/* atan(+,+) */
+	    case 1: {
+		      __uint32_t zh;
+		      zh = CYG_LIBM_WORD(z);
+		      SET_FLOAT_WORD(z,zh ^ 0x80000000);
+		    }
+		    return       z  ;	/* atan(-,+) */
+	    case 2: return  pi-(z-pi_lo);/* atan(+,-) */
+	    default: /* case 3 */
+		    return  (z-pi_lo)-pi;/* atan(-,-) */
+	}
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_atan2.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_atanh.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_atanh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_atanh.c
@@ -0,0 +1,121 @@
+//===========================================================================
+//
+//      ef_atanh.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_atanh.c -- float version of e_atanh.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float one = 1.0, huge = 1e30;
+#else
+static float one = 1.0, huge = 1e30;
+#endif
+
+#ifdef __STDC__
+static const float zero = 0.0;
+#else
+static float zero = 0.0;
+#endif
+
+#ifdef __STDC__
+	float __ieee754_atanhf(float x)
+#else
+	float __ieee754_atanhf(x)
+	float x;
+#endif
+{
+	float t;
+	__int32_t hx,ix;
+	hx = CYG_LIBM_WORD(x);
+	ix = hx&0x7fffffff;
+	if (ix>0x3f800000)		/* |x|>1 */
+	    return (x-x)/(x-x);
+	if(ix==0x3f800000)
+	    return x/zero;
+	if(ix<0x31800000&&(huge+x)>zero) return x;	/* x<2**-28 */
+	SET_FLOAT_WORD(x,ix);
+	if(ix<0x3f000000) {		/* x < 0.5 */
+	    t = x+x;
+	    t = (float)0.5*log1pf(t+t*x/(one-x));
+	} else
+	    t = (float)0.5*log1pf((x+x)/(one-x));
+	if(hx>=0) return t; else return -t;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_atanh.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_cosh.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_cosh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_cosh.c
@@ -0,0 +1,134 @@
+//===========================================================================
+//
+//      ef_cosh.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_cosh.c -- float version of e_cosh.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float one = 1.0, half=0.5, huge = 1.0e30;
+#else
+static float one = 1.0, half=0.5, huge = 1.0e30;
+#endif
+
+#ifdef __STDC__
+	float __ieee754_coshf(float x)
+#else
+	float __ieee754_coshf(x)
+	float x;
+#endif
+{
+	float t,w;
+	__int32_t ix;
+
+	ix = CYG_LIBM_WORD(x);
+	ix &= 0x7fffffff;
+
+    /* x is INF or NaN */
+	if(!FLT_UWORD_IS_FINITE(ix)) return x*x;
+
+    /* |x| in [0,0.5*ln2], return 1+expm1(|x|)^2/(2*exp(|x|)) */
+	if(ix<0x3eb17218) {
+	    t = expm1f(fabsf(x));
+	    w = one+t;
+	    if (ix<0x24000000) return w;	/* cosh(tiny) = 1 */
+	    return one+(t*t)/(w+w);
+	}
+
+    /* |x| in [0.5*ln2,22], return (exp(|x|)+1/exp(|x|)/2; */
+	if (ix < 0x41b00000) {
+		t = __ieee754_expf(fabsf(x));
+		return half*t+half/t;
+	}
+
+    /* |x| in [22, log(maxdouble)] return half*exp(|x|) */
+	if (ix <= FLT_UWORD_LOG_MAX)
+	  return half*__ieee754_expf(fabsf(x));
+
+    /* |x| in [log(maxdouble), overflowthresold] */
+	if (ix <= FLT_UWORD_LOG_2MAX) {
+	    w = __ieee754_expf(half*fabsf(x));
+	    t = half*w;
+	    return t*w;
+	}
+
+    /* |x| > overflowthresold, cosh(x) overflow */
+	return huge*huge;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_cosh.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_exp.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_exp.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_exp.c
@@ -0,0 +1,165 @@
+//===========================================================================
+//
+//      ef_exp.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_exp.c -- float version of e_exp.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+one	= 1.0,
+halF[2]	= {0.5,-0.5,},
+huge	= 1.0e+30,
+twom100 = 7.8886090522e-31,      /* 2**-100=0x0d800000 */
+ln2HI[2]   ={ 6.9313812256e-01,		/* 0x3f317180 */
+	     -6.9313812256e-01,},	/* 0xbf317180 */
+ln2LO[2]   ={ 9.0580006145e-06,	/* 0x3717f7d1 */
+	     -9.0580006145e-06,},	/* 0xb717f7d1 */
+invln2 =  1.4426950216e+00,		/* 0x3fb8aa3b */
+P1   =  1.6666667163e-01, /* 0x3e2aaaab */
+P2   = -2.7777778450e-03, /* 0xbb360b61 */
+P3   =  6.6137559770e-05, /* 0x388ab355 */
+P4   = -1.6533901999e-06, /* 0xb5ddea0e */
+P5   =  4.1381369442e-08; /* 0x3331bb4c */
+
+#ifdef __STDC__
+	float __ieee754_expf(float x)	/* default IEEE double exp */
+#else
+	float __ieee754_expf(x)	/* default IEEE double exp */
+	float x;
+#endif
+{
+	float y,hi,lo,c,t;
+	__int32_t k,xsb,sx;
+	__uint32_t hx;
+
+	sx = CYG_LIBM_WORD(x);
+	xsb = (sx>>31)&1;		/* sign bit of x */
+	hx = sx & 0x7fffffff;		/* high word of |x| */
+
+    /* filter out non-finite argument */
+        if(FLT_UWORD_IS_NAN(hx))
+            return x+x;		/* NaN */
+        if(FLT_UWORD_IS_INFINITE(hx))
+	    return (xsb==0)? x:0.0;		/* exp(+-inf)={inf,0} */
+	if(sx > FLT_UWORD_LOG_MAX)
+	    return huge*huge; /* overflow */
+	if(sx < 0 && hx > FLT_UWORD_LOG_MIN)
+	    return twom100*twom100; /* underflow */
+
+    /* argument reduction */
+	if(hx > 0x3eb17218) {		/* if  |x| > 0.5 ln2 */
+	    if(hx < 0x3F851592) {	/* and |x| < 1.5 ln2 */
+		hi = x-ln2HI[xsb]; lo=ln2LO[xsb]; k = 1-xsb-xsb;
+	    } else {
+		k  = invln2*x+halF[xsb];
+		t  = k;
+		hi = x - t*ln2HI[0];	/* t*ln2HI is exact here */
+		lo = t*ln2LO[0];
+	    }
+	    x  = hi - lo;
+	}
+	else if(hx < 0x31800000)  {	/* when |x|<2**-28 */
+	    if(huge+x>one)
+            return one+x;/* trigger inexact */
+        else // VAE
+            k = 0;
+	}
+	else k = 0;
+
+    /* x is now in primary range */
+	t  = x*x;
+	c  = x - t*(P1+t*(P2+t*(P3+t*(P4+t*P5))));
+	if(k==0)	return one-((x*c)/(c-(float)2.0)-x);
+	else		y = one-((lo-(x*c)/((float)2.0-c))-hi);
+	if(k >= -125) {
+	    __uint32_t hy;
+	    hy = CYG_LIBM_WORD(y);
+	    SET_FLOAT_WORD(y,hy+(k<<23));	/* add k to y's exponent */
+	    return y;
+	} else {
+	    __uint32_t hy;
+	    hy = CYG_LIBM_WORD(y);
+	    SET_FLOAT_WORD(y,hy+((k+100)<<23));	/* add k to y's exponent */
+	    return y*twom100;
+	}
+}
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_exp.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_fmod.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_fmod.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_fmod.c
@@ -0,0 +1,180 @@
+//===========================================================================
+//
+//      ef_fmod.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_fmod.c -- float version of e_fmod.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * __ieee754_fmodf(x,y)
+ * Return x mod y in exact arithmetic
+ * Method: shift and subtract
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float one = 1.0, Zero[] = {0.0, -0.0,};
+#else
+static float one = 1.0, Zero[] = {0.0, -0.0,};
+#endif
+
+#ifdef __STDC__
+	float __ieee754_fmodf(float x, float y)
+#else
+	float __ieee754_fmodf(x,y)
+	float x,y ;
+#endif
+{
+	__int32_t n,hx,hy,hz,ix,iy,sx,i;
+
+	hx = CYG_LIBM_WORD(x);
+	hy = CYG_LIBM_WORD(y);
+	sx = hx&0x80000000;		/* sign of x */
+	hx ^=sx;		/* |x| */
+	hy &= 0x7fffffff;	/* |y| */
+
+    /* purge off exception values */
+	if(FLT_UWORD_IS_ZERO(hy)||
+	   !FLT_UWORD_IS_FINITE(hx)||
+	   FLT_UWORD_IS_NAN(hy))
+	    return (x*y)/(x*y);
+	if(hx<hy) return x;			/* |x|<|y| return x */
+	if(hx==hy)
+	    return Zero[(__uint32_t)sx>>31];	/* |x|=|y| return x*0*/
+
+    /* Note: y cannot be zero if we reach here. */
+
+    /* determine ix = ilogb(x) */
+	if(FLT_UWORD_IS_SUBNORMAL(hx)) {	/* subnormal x */
+	    for (ix = -126,i=(hx<<8); i>0; i<<=1) ix -=1;
+	} else ix = (hx>>23)-127;
+
+    /* determine iy = ilogb(y) */
+	if(FLT_UWORD_IS_SUBNORMAL(hy)) {	/* subnormal y */
+	    for (iy = -126,i=(hy<<8); i>=0; i<<=1) iy -=1;
+	} else iy = (hy>>23)-127;
+
+    /* set up {hx,lx}, {hy,ly} and align y to x */
+	if(ix >= -126)
+	    hx = 0x00800000|(0x007fffff&hx);
+	else {		/* subnormal x, shift x to normal */
+	    n = -126-ix;
+	    hx = hx<<n;
+	}
+	if(iy >= -126)
+	    hy = 0x00800000|(0x007fffff&hy);
+	else {		/* subnormal y, shift y to normal */
+	    n = -126-iy;
+	    hy = hy<<n;
+	}
+
+    /* fix point fmod */
+	n = ix - iy;
+	while(n--) {
+	    hz=hx-hy;
+	    if(hz<0){hx = hx+hx;}
+	    else {
+		if(hz==0)		/* return sign(x)*0 */
+		    return Zero[(__uint32_t)sx>>31];
+		hx = hz+hz;
+	    }
+	}
+	hz=hx-hy;
+	if(hz>=0) {hx=hz;}
+
+    /* convert back to floating value and restore the sign */
+	if(hx==0)			/* return sign(x)*0 */
+	    return Zero[(__uint32_t)sx>>31];
+	while(hx<0x00800000) {		/* normalize x */
+	    hx = hx+hx;
+	    iy -= 1;
+	}
+	if(iy>= -126) {		/* normalize output */
+	    hx = ((hx-0x00800000)|((iy+127)<<23));
+	    SET_FLOAT_WORD(x,hx|sx);
+	} else {		/* subnormal output */
+	    /* If denormals are not supported, this code will generate a
+	       zero representation.  */
+	    n = -126 - iy;
+	    hx >>= n;
+	    SET_FLOAT_WORD(x,hx|sx);
+	    x *= one;		/* create necessary signal */
+	}
+	return x;		/* exact output */
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_fmod.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_gamma.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_gamma.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_gamma.c
@@ -0,0 +1,93 @@
+//===========================================================================
+//
+//      ef_gamma.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* @(#)ef_gamma.c 1.3 95/01/18 */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunSoft, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+/* __ieee754_gamma(x)
+ * Return the logarithm of the Gamma function of x.
+ *
+ * Method: call __ieee754_gamma_r
+ */
+
+#include <math.h>
+#include "mathincl/fdlibm.h"
+
+float
+__ieee754_gammaf(float x)
+{
+        return __ieee754_gammaf_r(x,&signgam);
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_gamma.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_gamma_r.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_gamma_r.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_gamma_r.c
@@ -0,0 +1,106 @@
+//===========================================================================
+//
+//      ef_gamma_r.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+/* erf_gamma.c -- float version of er_gamma.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+/* __ieee754_gammaf_r(x, signgamp)
+ * Reentrant version of the logarithm of the Gamma function
+ * with user provide pointer for the sign of Gamma(x).
+ *
+ * Method: See __ieee754_lgammaf_r
+ */
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float __ieee754_gammaf_r(float x, int *signgamp)
+#else
+	float __ieee754_gammaf_r(x,signgamp)
+	float x; int *signgamp;
+#endif
+{
+	return __ieee754_lgammaf_r(x,signgamp);
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_gamma_r.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_hypot.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_hypot.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_hypot.c
@@ -0,0 +1,149 @@
+//===========================================================================
+//
+//      ef_hypot.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_hypot.c -- float version of e_hypot.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float __ieee754_hypotf(float x, float y)
+#else
+	float __ieee754_hypotf(x,y)
+	float x, y;
+#endif
+{
+	float a=x,b=y,t1,t2,y1,y2,w;
+	__int32_t j,k,ha,hb;
+
+	ha = CYG_LIBM_WORD(x);
+	ha &= 0x7fffffffL;
+	hb = CYG_LIBM_WORD(y);
+	hb &= 0x7fffffffL;
+	if(hb > ha) {a=y;b=x;j=ha; ha=hb;hb=j;} else {a=x;b=y;}
+	SET_FLOAT_WORD(a,ha);	/* a <- |a| */
+	SET_FLOAT_WORD(b,hb);	/* b <- |b| */
+	if((ha-hb)>0xf000000L) {return a+b;} /* x/y > 2**30 */
+	k=0;
+	if(ha > 0x58800000L) {	/* a>2**50 */
+	   if(!FLT_UWORD_IS_FINITE(ha)) {	/* Inf or NaN */
+	       w = a+b;			/* for sNaN */
+	       if(FLT_UWORD_IS_INFINITE(ha)) w = a;
+	       if(FLT_UWORD_IS_INFINITE(hb)) w = b;
+	       return w;
+	   }
+	   /* scale a and b by 2**-68 */
+	   ha -= 0x22000000L; hb -= 0x22000000L;	k += 68;
+	   SET_FLOAT_WORD(a,ha);
+	   SET_FLOAT_WORD(b,hb);
+	}
+	if(hb < 0x26800000L) {	/* b < 2**-50 */
+	    if(FLT_UWORD_IS_ZERO(hb)) {
+	        return a;
+	    } else if(FLT_UWORD_IS_SUBNORMAL(hb)) {
+		SET_FLOAT_WORD(t1,0x7e800000L);	/* t1=2^126 */
+		b *= t1;
+		a *= t1;
+		k -= 126;
+	    } else {		/* scale a and b by 2^68 */
+	        ha += 0x22000000;	/* a *= 2^68 */
+		hb += 0x22000000;	/* b *= 2^68 */
+		k -= 68;
+		SET_FLOAT_WORD(a,ha);
+		SET_FLOAT_WORD(b,hb);
+	    }
+	}
+    /* medium size a and b */
+	w = a-b;
+	if (w>b) {
+	    SET_FLOAT_WORD(t1,ha&0xfffff000L);
+	    t2 = a-t1;
+	    w  = __ieee754_sqrtf(t1*t1-(b*(-b)-t2*(a+t1)));
+	} else {
+	    a  = a+a;
+	    SET_FLOAT_WORD(y1,hb&0xfffff000L);
+	    y2 = b - y1;
+	    SET_FLOAT_WORD(t1,ha+0x00800000L);
+	    t2 = a - t1;
+	    w  = __ieee754_sqrtf(t1*y1-(w*(-w)-(t1*y2+t2*b)));
+	}
+	if(k!=0) {
+	    SET_FLOAT_WORD(t1,0x3f800000L+(k<<23));
+	    return t1*w;
+	} else return w;
+}
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_hypot.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_j0.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_j0.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_j0.c
@@ -0,0 +1,506 @@
+//===========================================================================
+//
+//      ef_j0.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_j0.c -- float version of e_j0.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static float pzerof(float), qzerof(float);
+#else
+static float pzerof(), qzerof();
+#endif
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+huge	= 1e30,
+one	= 1.0,
+invsqrtpi=  5.6418961287e-01, /* 0x3f106ebb */
+tpi      =  6.3661974669e-01, /* 0x3f22f983 */
+		/* R0/S0 on [0, 2.00] */
+R02  =  1.5625000000e-02, /* 0x3c800000 */
+R03  = -1.8997929874e-04, /* 0xb947352e */
+R04  =  1.8295404516e-06, /* 0x35f58e88 */
+R05  = -4.6183270541e-09, /* 0xb19eaf3c */
+S01  =  1.5619102865e-02, /* 0x3c7fe744 */
+S02  =  1.1692678527e-04, /* 0x38f53697 */
+S03  =  5.1354652442e-07, /* 0x3509daa6 */
+S04  =  1.1661400734e-09; /* 0x30a045e8 */
+
+#ifdef __STDC__
+static const float zero = 0.0;
+#else
+static float zero = 0.0;
+#endif
+
+#ifdef __STDC__
+	float __ieee754_j0f(float x)
+#else
+	float __ieee754_j0f(x)
+	float x;
+#endif
+{
+	float z, s,c,ss,cc,r,u,v;
+	__int32_t hx,ix;
+
+	hx = CYG_LIBM_WORD(x);
+	ix = hx&0x7fffffff;
+	if(!FLT_UWORD_IS_FINITE(ix)) return one/(x*x);
+	x = fabsf(x);
+	if(ix >= 0x40000000) {	/* |x| >= 2.0 */
+		s = sinf(x);
+		c = cosf(x);
+		ss = s-c;
+		cc = s+c;
+		if(ix<=FLT_UWORD_HALF_MAX) {  /* make sure x+x not overflow */
+		    z = -cosf(x+x);
+		    if ((s*c)<zero) cc = z/ss;
+		    else	    ss = z/cc;
+		}
+	/*
+	 * j0(x) = 1/sqrt(pi) * (P(0,x)*cc - Q(0,x)*ss) / sqrt(x)
+	 * y0(x) = 1/sqrt(pi) * (P(0,x)*ss + Q(0,x)*cc) / sqrt(x)
+	 */
+		if(ix>0x80000000) z = (invsqrtpi*cc)/__ieee754_sqrtf(x);
+		else {
+		    u = pzerof(x); v = qzerof(x);
+		    z = invsqrtpi*(u*cc-v*ss)/__ieee754_sqrtf(x);
+		}
+		return z;
+	}
+	if(ix<0x39000000) {	/* |x| < 2**-13 */
+	    if(huge+x>one) {	/* raise inexact if x != 0 */
+	        if(ix<0x32000000) return one;	/* |x|<2**-27 */
+	        else	      return one - (float)0.25*x*x;
+	    }
+	}
+	z = x*x;
+	r =  z*(R02+z*(R03+z*(R04+z*R05)));
+	s =  one+z*(S01+z*(S02+z*(S03+z*S04)));
+	if(ix < 0x3F800000) {	/* |x| < 1.00 */
+	    return one + z*((float)-0.25+(r/s));
+	} else {
+	    u = (float)0.5*x;
+	    return((one+u)*(one-u)+z*(r/s));
+	}
+}
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+u00  = -7.3804296553e-02, /* 0xbd9726b5 */
+u01  =  1.7666645348e-01, /* 0x3e34e80d */
+u02  = -1.3818567619e-02, /* 0xbc626746 */
+u03  =  3.4745343146e-04, /* 0x39b62a69 */
+u04  = -3.8140706238e-06, /* 0xb67ff53c */
+u05  =  1.9559013964e-08, /* 0x32a802ba */
+u06  = -3.9820518410e-11, /* 0xae2f21eb */
+v01  =  1.2730483897e-02, /* 0x3c509385 */
+v02  =  7.6006865129e-05, /* 0x389f65e0 */
+v03  =  2.5915085189e-07, /* 0x348b216c */
+v04  =  4.4111031494e-10; /* 0x2ff280c2 */
+
+#ifdef __STDC__
+	float __ieee754_y0f(float x)
+#else
+	float __ieee754_y0f(x)
+	float x;
+#endif
+{
+	float z, s,c,ss,cc,u,v;
+	__int32_t hx,ix;
+
+	hx = CYG_LIBM_WORD(x);
+        ix = 0x7fffffff&hx;
+    /* Y0(NaN) is NaN, y0(-inf) is Nan, y0(inf) is 0  */
+	if(!FLT_UWORD_IS_FINITE(ix)) return  one/(x+x*x);
+        if(FLT_UWORD_IS_ZERO(ix)) return -one/zero;
+        if(hx<0) return zero/zero;
+        if(ix >= 0x40000000) {  /* |x| >= 2.0 */
+        /* y0(x) = sqrt(2/(pi*x))*(p0(x)*sin(x0)+q0(x)*cos(x0))
+         * where x0 = x-pi/4
+         *      Better formula:
+         *              cos(x0) = cos(x)cos(pi/4)+sin(x)sin(pi/4)
+         *                      =  1/sqrt(2) * (sin(x) + cos(x))
+         *              sin(x0) = sin(x)cos(3pi/4)-cos(x)sin(3pi/4)
+         *                      =  1/sqrt(2) * (sin(x) - cos(x))
+         * To avoid cancellation, use
+         *              sin(x) +- cos(x) = -cos(2x)/(sin(x) -+ cos(x))
+         * to compute the worse one.
+         */
+                s = sinf(x);
+                c = cosf(x);
+                ss = s-c;
+                cc = s+c;
+	/*
+	 * j0(x) = 1/sqrt(pi) * (P(0,x)*cc - Q(0,x)*ss) / sqrt(x)
+	 * y0(x) = 1/sqrt(pi) * (P(0,x)*ss + Q(0,x)*cc) / sqrt(x)
+	 */
+                if(ix<=FLT_UWORD_HALF_MAX) {  /* make sure x+x not overflow */
+                    z = -cosf(x+x);
+                    if ((s*c)<zero) cc = z/ss;
+                    else            ss = z/cc;
+                }
+                if(ix>0x80000000) z = (invsqrtpi*ss)/__ieee754_sqrtf(x);
+                else {
+                    u = pzerof(x); v = qzerof(x);
+                    z = invsqrtpi*(u*ss+v*cc)/__ieee754_sqrtf(x);
+                }
+                return z;
+	}
+	if(ix<=0x32000000) {	/* x < 2**-27 */
+	    return(u00 + tpi*__ieee754_logf(x));
+	}
+	z = x*x;
+	u = u00+z*(u01+z*(u02+z*(u03+z*(u04+z*(u05+z*u06)))));
+	v = one+z*(v01+z*(v02+z*(v03+z*v04)));
+	return(u/v + tpi*(__ieee754_j0f(x)*__ieee754_logf(x)));
+}
+
+/* The asymptotic expansions of pzero is
+ *	1 - 9/128 s^2 + 11025/98304 s^4 - ...,	where s = 1/x.
+ * For x >= 2, We approximate pzero by
+ *	pzero(x) = 1 + (R/S)
+ * where  R = pR0 + pR1*s^2 + pR2*s^4 + ... + pR5*s^10
+ *	  S = 1 + pS0*s^2 + ... + pS4*s^10
+ * and
+ *	| pzero(x)-1-R/S | <= 2  ** ( -60.26)
+ */
+#ifdef __STDC__
+static const float pR8[6] = { /* for x in [inf, 8]=1/[0,0.125] */
+#else
+static float pR8[6] = { /* for x in [inf, 8]=1/[0,0.125] */
+#endif
+  0.0000000000e+00, /* 0x00000000 */
+ -7.0312500000e-02, /* 0xbd900000 */
+ -8.0816707611e+00, /* 0xc1014e86 */
+ -2.5706311035e+02, /* 0xc3808814 */
+ -2.4852163086e+03, /* 0xc51b5376 */
+ -5.2530439453e+03, /* 0xc5a4285a */
+};
+#ifdef __STDC__
+static const float pS8[5] = {
+#else
+static float pS8[5] = {
+#endif
+  1.1653436279e+02, /* 0x42e91198 */
+  3.8337448730e+03, /* 0x456f9beb */
+  4.0597855469e+04, /* 0x471e95db */
+  1.1675296875e+05, /* 0x47e4087c */
+  4.7627726562e+04, /* 0x473a0bba */
+};
+#ifdef __STDC__
+static const float pR5[6] = { /* for x in [8,4.5454]=1/[0.125,0.22001] */
+#else
+static float pR5[6] = { /* for x in [8,4.5454]=1/[0.125,0.22001] */
+#endif
+ -1.1412546255e-11, /* 0xad48c58a */
+ -7.0312492549e-02, /* 0xbd8fffff */
+ -4.1596107483e+00, /* 0xc0851b88 */
+ -6.7674766541e+01, /* 0xc287597b */
+ -3.3123129272e+02, /* 0xc3a59d9b */
+ -3.4643338013e+02, /* 0xc3ad3779 */
+};
+#ifdef __STDC__
+static const float pS5[5] = {
+#else
+static float pS5[5] = {
+#endif
+  6.0753936768e+01, /* 0x42730408 */
+  1.0512523193e+03, /* 0x44836813 */
+  5.9789707031e+03, /* 0x45bad7c4 */
+  9.6254453125e+03, /* 0x461665c8 */
+  2.4060581055e+03, /* 0x451660ee */
+};
+
+#ifdef __STDC__
+static const float pR3[6] = {/* for x in [4.547,2.8571]=1/[0.2199,0.35001] */
+#else
+static float pR3[6] = {/* for x in [4.547,2.8571]=1/[0.2199,0.35001] */
+#endif
+ -2.5470459075e-09, /* 0xb12f081b */
+ -7.0311963558e-02, /* 0xbd8fffb8 */
+ -2.4090321064e+00, /* 0xc01a2d95 */
+ -2.1965976715e+01, /* 0xc1afba52 */
+ -5.8079170227e+01, /* 0xc2685112 */
+ -3.1447946548e+01, /* 0xc1fb9565 */
+};
+#ifdef __STDC__
+static const float pS3[5] = {
+#else
+static float pS3[5] = {
+#endif
+  3.5856033325e+01, /* 0x420f6c94 */
+  3.6151397705e+02, /* 0x43b4c1ca */
+  1.1936077881e+03, /* 0x44953373 */
+  1.1279968262e+03, /* 0x448cffe6 */
+  1.7358093262e+02, /* 0x432d94b8 */
+};
+
+#ifdef __STDC__
+static const float pR2[6] = {/* for x in [2.8570,2]=1/[0.3499,0.5] */
+#else
+static float pR2[6] = {/* for x in [2.8570,2]=1/[0.3499,0.5] */
+#endif
+ -8.8753431271e-08, /* 0xb3be98b7 */
+ -7.0303097367e-02, /* 0xbd8ffb12 */
+ -1.4507384300e+00, /* 0xbfb9b1cc */
+ -7.6356959343e+00, /* 0xc0f4579f */
+ -1.1193166733e+01, /* 0xc1331736 */
+ -3.2336456776e+00, /* 0xc04ef40d */
+};
+#ifdef __STDC__
+static const float pS2[5] = {
+#else
+static float pS2[5] = {
+#endif
+  2.2220300674e+01, /* 0x41b1c32d */
+  1.3620678711e+02, /* 0x430834f0 */
+  2.7047027588e+02, /* 0x43873c32 */
+  1.5387539673e+02, /* 0x4319e01a */
+  1.4657617569e+01, /* 0x416a859a */
+};
+
+#ifdef __STDC__
+	static float pzerof(float x)
+#else
+	static float pzerof(x)
+	float x;
+#endif
+{
+#ifdef __STDC__
+	const float *p,*q;
+#else
+	float *p,*q;
+#endif
+	float z,r,s;
+	__int32_t ix;
+	ix = CYG_LIBM_WORD(x);
+	ix &= 0x7fffffff;
+	if(ix>=0x41000000)     {p = pR8; q= pS8;}
+	else if(ix>=0x40f71c58){p = pR5; q= pS5;}
+	else if(ix>=0x4036db68){p = pR3; q= pS3;}
+      else {p = pR2; q= pS2;}
+	z = one/(x*x);
+	r = p[0]+z*(p[1]+z*(p[2]+z*(p[3]+z*(p[4]+z*p[5]))));
+	s = one+z*(q[0]+z*(q[1]+z*(q[2]+z*(q[3]+z*q[4]))));
+	return one+ r/s;
+}
+
+
+/* For x >= 8, the asymptotic expansions of qzero is
+ *	-1/8 s + 75/1024 s^3 - ..., where s = 1/x.
+ * We approximate qzero by
+ *	qzero(x) = s*(-1.25 + (R/S))
+ * where  R = qR0 + qR1*s^2 + qR2*s^4 + ... + qR5*s^10
+ *	  S = 1 + qS0*s^2 + ... + qS5*s^12
+ * and
+ *	| qzero(x)/s +1.25-R/S | <= 2  ** ( -61.22)
+ */
+#ifdef __STDC__
+static const float qR8[6] = { /* for x in [inf, 8]=1/[0,0.125] */
+#else
+static float qR8[6] = { /* for x in [inf, 8]=1/[0,0.125] */
+#endif
+  0.0000000000e+00, /* 0x00000000 */
+  7.3242187500e-02, /* 0x3d960000 */
+  1.1768206596e+01, /* 0x413c4a93 */
+  5.5767340088e+02, /* 0x440b6b19 */
+  8.8591972656e+03, /* 0x460a6cca */
+  3.7014625000e+04, /* 0x471096a0 */
+};
+#ifdef __STDC__
+static const float qS8[6] = {
+#else
+static float qS8[6] = {
+#endif
+  1.6377603149e+02, /* 0x4323c6aa */
+  8.0983447266e+03, /* 0x45fd12c2 */
+  1.4253829688e+05, /* 0x480b3293 */
+  8.0330925000e+05, /* 0x49441ed4 */
+  8.4050156250e+05, /* 0x494d3359 */
+ -3.4389928125e+05, /* 0xc8a7eb69 */
+};
+
+#ifdef __STDC__
+static const float qR5[6] = { /* for x in [8,4.5454]=1/[0.125,0.22001] */
+#else
+static float qR5[6] = { /* for x in [8,4.5454]=1/[0.125,0.22001] */
+#endif
+  1.8408595828e-11, /* 0x2da1ec79 */
+  7.3242180049e-02, /* 0x3d95ffff */
+  5.8356351852e+00, /* 0x40babd86 */
+  1.3511157227e+02, /* 0x43071c90 */
+  1.0272437744e+03, /* 0x448067cd */
+  1.9899779053e+03, /* 0x44f8bf4b */
+};
+#ifdef __STDC__
+static const float qS5[6] = {
+#else
+static float qS5[6] = {
+#endif
+  8.2776611328e+01, /* 0x42a58da0 */
+  2.0778142090e+03, /* 0x4501dd07 */
+  1.8847289062e+04, /* 0x46933e94 */
+  5.6751113281e+04, /* 0x475daf1d */
+  3.5976753906e+04, /* 0x470c88c1 */
+ -5.3543427734e+03, /* 0xc5a752be */
+};
+
+#ifdef __STDC__
+static const float qR3[6] = {/* for x in [4.547,2.8571]=1/[0.2199,0.35001] */
+#else
+static float qR3[6] = {/* for x in [4.547,2.8571]=1/[0.2199,0.35001] */
+#endif
+  4.3774099900e-09, /* 0x3196681b */
+  7.3241114616e-02, /* 0x3d95ff70 */
+  3.3442313671e+00, /* 0x405607e3 */
+  4.2621845245e+01, /* 0x422a7cc5 */
+  1.7080809021e+02, /* 0x432acedf */
+  1.6673394775e+02, /* 0x4326bbe4 */
+};
+#ifdef __STDC__
+static const float qS3[6] = {
+#else
+static float qS3[6] = {
+#endif
+  4.8758872986e+01, /* 0x42430916 */
+  7.0968920898e+02, /* 0x44316c1c */
+  3.7041481934e+03, /* 0x4567825f */
+  6.4604252930e+03, /* 0x45c9e367 */
+  2.5163337402e+03, /* 0x451d4557 */
+ -1.4924745178e+02, /* 0xc3153f59 */
+};
+
+#ifdef __STDC__
+static const float qR2[6] = {/* for x in [2.8570,2]=1/[0.3499,0.5] */
+#else
+static float qR2[6] = {/* for x in [2.8570,2]=1/[0.3499,0.5] */
+#endif
+  1.5044444979e-07, /* 0x342189db */
+  7.3223426938e-02, /* 0x3d95f62a */
+  1.9981917143e+00, /* 0x3fffc4bf */
+  1.4495602608e+01, /* 0x4167edfd */
+  3.1666231155e+01, /* 0x41fd5471 */
+  1.6252708435e+01, /* 0x4182058c */
+};
+#ifdef __STDC__
+static const float qS2[6] = {
+#else
+static float qS2[6] = {
+#endif
+  3.0365585327e+01, /* 0x41f2ecb8 */
+  2.6934811401e+02, /* 0x4386ac8f */
+  8.4478375244e+02, /* 0x44533229 */
+  8.8293585205e+02, /* 0x445cbbe5 */
+  2.1266638184e+02, /* 0x4354aa98 */
+ -5.3109550476e+00, /* 0xc0a9f358 */
+};
+
+#ifdef __STDC__
+	static float qzerof(float x)
+#else
+	static float qzerof(x)
+	float x;
+#endif
+{
+#ifdef __STDC__
+	const float *p,*q;
+#else
+	float *p,*q;
+#endif
+	float s,r,z;
+	__int32_t ix;
+	ix = CYG_LIBM_WORD(x);
+	ix &= 0x7fffffff;
+	if(ix>=0x41000000)     {p = qR8; q= qS8;}
+	else if(ix>=0x40f71c58){p = qR5; q= qS5;}
+	else if(ix>=0x4036db68){p = qR3; q= qS3;}
+      else {p = qR2; q= qS2;}
+	z = one/(x*x);
+	r = p[0]+z*(p[1]+z*(p[2]+z*(p[3]+z*(p[4]+z*p[5]))));
+	s = one+z*(q[0]+z*(q[1]+z*(q[2]+z*(q[3]+z*(q[4]+z*q[5])))));
+	return (-(float).125 + r/s)/x;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_j0.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_j1.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_j1.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_j1.c
@@ -0,0 +1,506 @@
+//===========================================================================
+//
+//      ef_j1.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_j1.c -- float version of e_j1.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static float ponef(float), qonef(float);
+#else
+static float ponef(), qonef();
+#endif
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+huge    = 1e30,
+one	= 1.0,
+invsqrtpi=  5.6418961287e-01, /* 0x3f106ebb */
+tpi      =  6.3661974669e-01, /* 0x3f22f983 */
+	/* R0/S0 on [0,2] */
+r00  = -6.2500000000e-02, /* 0xbd800000 */
+r01  =  1.4070566976e-03, /* 0x3ab86cfd */
+r02  = -1.5995563444e-05, /* 0xb7862e36 */
+r03  =  4.9672799207e-08, /* 0x335557d2 */
+s01  =  1.9153760746e-02, /* 0x3c9ce859 */
+s02  =  1.8594678841e-04, /* 0x3942fab6 */
+s03  =  1.1771846857e-06, /* 0x359dffc2 */
+s04  =  5.0463624390e-09, /* 0x31ad6446 */
+s05  =  1.2354227016e-11; /* 0x2d59567e */
+
+#ifdef __STDC__
+static const float zero    = 0.0;
+#else
+static float zero    = 0.0;
+#endif
+
+#ifdef __STDC__
+	float __ieee754_j1f(float x)
+#else
+	float __ieee754_j1f(x)
+	float x;
+#endif
+{
+	float z, s,c,ss,cc,r,u,v,y;
+	__int32_t hx,ix;
+
+	hx = CYG_LIBM_WORD(x);
+	ix = hx&0x7fffffff;
+	if(!FLT_UWORD_IS_FINITE(ix)) return one/x;
+	y = fabsf(x);
+	if(ix >= 0x40000000) {	/* |x| >= 2.0 */
+		s = sinf(y);
+		c = cosf(y);
+		ss = -s-c;
+		cc = s-c;
+		if(ix<=FLT_UWORD_HALF_MAX) {  /* make sure y+y not overflow */
+		    z = cosf(y+y);
+		    if ((s*c)>zero) cc = z/ss;
+		    else	    ss = z/cc;
+		}
+	/*
+	 * j1(x) = 1/sqrt(pi) * (P(1,x)*cc - Q(1,x)*ss) / sqrt(x)
+	 * y1(x) = 1/sqrt(pi) * (P(1,x)*ss + Q(1,x)*cc) / sqrt(x)
+	 */
+		if(ix>0x80000000) z = (invsqrtpi*cc)/__ieee754_sqrtf(y);
+		else {
+		    u = ponef(y); v = qonef(y);
+		    z = invsqrtpi*(u*cc-v*ss)/__ieee754_sqrtf(y);
+		}
+		if(hx<0) return -z;
+		else	 return  z;
+	}
+	if(ix<0x32000000) {	/* |x|<2**-27 */
+	    if(huge+x>one) return (float)0.5*x;/* inexact if x!=0 necessary */
+	}
+	z = x*x;
+	r =  z*(r00+z*(r01+z*(r02+z*r03)));
+	s =  one+z*(s01+z*(s02+z*(s03+z*(s04+z*s05))));
+	r *= x;
+	return(x*(float)0.5+r/s);
+}
+
+#ifdef __STDC__
+static const float U0[5] = {
+#else
+static float U0[5] = {
+#endif
+ -1.9605709612e-01, /* 0xbe48c331 */
+  5.0443872809e-02, /* 0x3d4e9e3c */
+ -1.9125689287e-03, /* 0xbafaaf2a */
+  2.3525259166e-05, /* 0x37c5581c */
+ -9.1909917899e-08, /* 0xb3c56003 */
+};
+#ifdef __STDC__
+static const float V0[5] = {
+#else
+static float V0[5] = {
+#endif
+  1.9916731864e-02, /* 0x3ca3286a */
+  2.0255257550e-04, /* 0x3954644b */
+  1.3560879779e-06, /* 0x35b602d4 */
+  6.2274145840e-09, /* 0x31d5f8eb */
+  1.6655924903e-11, /* 0x2d9281cf */
+};
+
+#ifdef __STDC__
+	float __ieee754_y1f(float x)
+#else
+	float __ieee754_y1f(x)
+	float x;
+#endif
+{
+	float z, s,c,ss,cc,u,v;
+	__int32_t hx,ix;
+
+	hx = CYG_LIBM_WORD(x);
+        ix = 0x7fffffff&hx;
+    /* if Y1(NaN) is NaN, Y1(-inf) is NaN, Y1(inf) is 0 */
+	if(!FLT_UWORD_IS_FINITE(ix)) return one/(x+x*x);
+        if(FLT_UWORD_IS_ZERO(ix)) return -one/zero;
+        if(hx<0) return zero/zero;
+        if(ix >= 0x40000000) {  /* |x| >= 2.0 */
+                s = sinf(x);
+                c = cosf(x);
+                ss = -s-c;
+                cc = s-c;
+                if(ix<=FLT_UWORD_HALF_MAX) {  /* make sure x+x not overflow */
+                    z = cosf(x+x);
+                    if ((s*c)>zero) cc = z/ss;
+                    else            ss = z/cc;
+                }
+        /* y1(x) = sqrt(2/(pi*x))*(p1(x)*sin(x0)+q1(x)*cos(x0))
+         * where x0 = x-3pi/4
+         *      Better formula:
+         *              cos(x0) = cos(x)cos(3pi/4)+sin(x)sin(3pi/4)
+         *                      =  1/sqrt(2) * (sin(x) - cos(x))
+         *              sin(x0) = sin(x)cos(3pi/4)-cos(x)sin(3pi/4)
+         *                      = -1/sqrt(2) * (cos(x) + sin(x))
+         * To avoid cancellation, use
+         *              sin(x) +- cos(x) = -cos(2x)/(sin(x) -+ cos(x))
+         * to compute the worse one.
+         */
+                if(ix>0x48000000) z = (invsqrtpi*ss)/__ieee754_sqrtf(x);
+                else {
+                    u = ponef(x); v = qonef(x);
+                    z = invsqrtpi*(u*ss+v*cc)/__ieee754_sqrtf(x);
+                }
+                return z;
+        }
+        if(ix<=0x24800000) {    /* x < 2**-54 */
+            return(-tpi/x);
+        }
+        z = x*x;
+        u = U0[0]+z*(U0[1]+z*(U0[2]+z*(U0[3]+z*U0[4])));
+        v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4]))));
+        return(x*(u/v) + tpi*(__ieee754_j1f(x)*__ieee754_logf(x)-one/x));
+}
+
+/* For x >= 8, the asymptotic expansions of pone is
+ *	1 + 15/128 s^2 - 4725/2^15 s^4 - ...,	where s = 1/x.
+ * We approximate pone by
+ *	pone(x) = 1 + (R/S)
+ * where  R = pr0 + pr1*s^2 + pr2*s^4 + ... + pr5*s^10
+ *	  S = 1 + ps0*s^2 + ... + ps4*s^10
+ * and
+ *	| pone(x)-1-R/S | <= 2  ** ( -60.06)
+ */
+
+#ifdef __STDC__
+static const float pr8[6] = { /* for x in [inf, 8]=1/[0,0.125] */
+#else
+static float pr8[6] = { /* for x in [inf, 8]=1/[0,0.125] */
+#endif
+  0.0000000000e+00, /* 0x00000000 */
+  1.1718750000e-01, /* 0x3df00000 */
+  1.3239480972e+01, /* 0x4153d4ea */
+  4.1205184937e+02, /* 0x43ce06a3 */
+  3.8747453613e+03, /* 0x45722bed */
+  7.9144794922e+03, /* 0x45f753d6 */
+};
+#ifdef __STDC__
+static const float ps8[5] = {
+#else
+static float ps8[5] = {
+#endif
+  1.1420736694e+02, /* 0x42e46a2c */
+  3.6509309082e+03, /* 0x45642ee5 */
+  3.6956207031e+04, /* 0x47105c35 */
+  9.7602796875e+04, /* 0x47bea166 */
+  3.0804271484e+04, /* 0x46f0a88b */
+};
+
+#ifdef __STDC__
+static const float pr5[6] = { /* for x in [8,4.5454]=1/[0.125,0.22001] */
+#else
+static float pr5[6] = { /* for x in [8,4.5454]=1/[0.125,0.22001] */
+#endif
+  1.3199052094e-11, /* 0x2d68333f */
+  1.1718749255e-01, /* 0x3defffff */
+  6.8027510643e+00, /* 0x40d9b023 */
+  1.0830818176e+02, /* 0x42d89dca */
+  5.1763616943e+02, /* 0x440168b7 */
+  5.2871520996e+02, /* 0x44042dc6 */
+};
+#ifdef __STDC__
+static const float ps5[5] = {
+#else
+static float ps5[5] = {
+#endif
+  5.9280597687e+01, /* 0x426d1f55 */
+  9.9140142822e+02, /* 0x4477d9b1 */
+  5.3532670898e+03, /* 0x45a74a23 */
+  7.8446904297e+03, /* 0x45f52586 */
+  1.5040468750e+03, /* 0x44bc0180 */
+};
+
+#ifdef __STDC__
+static const float pr3[6] = {
+#else
+static float pr3[6] = {/* for x in [4.547,2.8571]=1/[0.2199,0.35001] */
+#endif
+  3.0250391081e-09, /* 0x314fe10d */
+  1.1718686670e-01, /* 0x3defffab */
+  3.9329774380e+00, /* 0x407bb5e7 */
+  3.5119403839e+01, /* 0x420c7a45 */
+  9.1055007935e+01, /* 0x42b61c2a */
+  4.8559066772e+01, /* 0x42423c7c */
+};
+#ifdef __STDC__
+static const float ps3[5] = {
+#else
+static float ps3[5] = {
+#endif
+  3.4791309357e+01, /* 0x420b2a4d */
+  3.3676245117e+02, /* 0x43a86198 */
+  1.0468714600e+03, /* 0x4482dbe3 */
+  8.9081134033e+02, /* 0x445eb3ed */
+  1.0378793335e+02, /* 0x42cf936c */
+};
+
+#ifdef __STDC__
+static const float pr2[6] = {/* for x in [2.8570,2]=1/[0.3499,0.5] */
+#else
+static float pr2[6] = {/* for x in [2.8570,2]=1/[0.3499,0.5] */
+#endif
+  1.0771083225e-07, /* 0x33e74ea8 */
+  1.1717621982e-01, /* 0x3deffa16 */
+  2.3685150146e+00, /* 0x401795c0 */
+  1.2242610931e+01, /* 0x4143e1bc */
+  1.7693971634e+01, /* 0x418d8d41 */
+  5.0735230446e+00, /* 0x40a25a4d */
+};
+#ifdef __STDC__
+static const float ps2[5] = {
+#else
+static float ps2[5] = {
+#endif
+  2.1436485291e+01, /* 0x41ab7dec */
+  1.2529022980e+02, /* 0x42fa9499 */
+  2.3227647400e+02, /* 0x436846c7 */
+  1.1767937469e+02, /* 0x42eb5bd7 */
+  8.3646392822e+00, /* 0x4105d590 */
+};
+
+#ifdef __STDC__
+	static float ponef(float x)
+#else
+	static float ponef(x)
+	float x;
+#endif
+{
+#ifdef __STDC__
+	const float *p,*q;
+#else
+	float *p,*q;
+#endif
+	float z,r,s;
+        __int32_t ix;
+	ix = CYG_LIBM_WORD(x);
+	ix &= 0x7fffffff;
+        if(ix>=0x41000000)     {p = pr8; q= ps8;}
+        else if(ix>=0x40f71c58){p = pr5; q= ps5;}
+        else if(ix>=0x4036db68){p = pr3; q= ps3;}
+        else {p = pr2; q= ps2;}
+        z = one/(x*x);
+        r = p[0]+z*(p[1]+z*(p[2]+z*(p[3]+z*(p[4]+z*p[5]))));
+        s = one+z*(q[0]+z*(q[1]+z*(q[2]+z*(q[3]+z*q[4]))));
+        return one+ r/s;
+}
+
+
+/* For x >= 8, the asymptotic expansions of qone is
+ *	3/8 s - 105/1024 s^3 - ..., where s = 1/x.
+ * We approximate qone by
+ *	qone(x) = s*(0.375 + (R/S))
+ * where  R = qr1*s^2 + qr2*s^4 + ... + qr5*s^10
+ *	  S = 1 + qs1*s^2 + ... + qs6*s^12
+ * and
+ *	| qone(x)/s -0.375-R/S | <= 2  ** ( -61.13)
+ */
+
+#ifdef __STDC__
+static const float qr8[6] = { /* for x in [inf, 8]=1/[0,0.125] */
+#else
+static float qr8[6] = { /* for x in [inf, 8]=1/[0,0.125] */
+#endif
+  0.0000000000e+00, /* 0x00000000 */
+ -1.0253906250e-01, /* 0xbdd20000 */
+ -1.6271753311e+01, /* 0xc1822c8d */
+ -7.5960174561e+02, /* 0xc43de683 */
+ -1.1849806641e+04, /* 0xc639273a */
+ -4.8438511719e+04, /* 0xc73d3683 */
+};
+#ifdef __STDC__
+static const float qs8[6] = {
+#else
+static float qs8[6] = {
+#endif
+  1.6139537048e+02, /* 0x43216537 */
+  7.8253862305e+03, /* 0x45f48b17 */
+  1.3387534375e+05, /* 0x4802bcd6 */
+  7.1965775000e+05, /* 0x492fb29c */
+  6.6660125000e+05, /* 0x4922be94 */
+ -2.9449025000e+05, /* 0xc88fcb48 */
+};
+
+#ifdef __STDC__
+static const float qr5[6] = { /* for x in [8,4.5454]=1/[0.125,0.22001] */
+#else
+static float qr5[6] = { /* for x in [8,4.5454]=1/[0.125,0.22001] */
+#endif
+ -2.0897993405e-11, /* 0xadb7d219 */
+ -1.0253904760e-01, /* 0xbdd1fffe */
+ -8.0564479828e+00, /* 0xc100e736 */
+ -1.8366960144e+02, /* 0xc337ab6b */
+ -1.3731937256e+03, /* 0xc4aba633 */
+ -2.6124443359e+03, /* 0xc523471c */
+};
+#ifdef __STDC__
+static const float qs5[6] = {
+#else
+static float qs5[6] = {
+#endif
+  8.1276550293e+01, /* 0x42a28d98 */
+  1.9917987061e+03, /* 0x44f8f98f */
+  1.7468484375e+04, /* 0x468878f8 */
+  4.9851425781e+04, /* 0x4742bb6d */
+  2.7948074219e+04, /* 0x46da5826 */
+ -4.7191835938e+03, /* 0xc5937978 */
+};
+
+#ifdef __STDC__
+static const float qr3[6] = {
+#else
+static float qr3[6] = {/* for x in [4.547,2.8571]=1/[0.2199,0.35001] */
+#endif
+ -5.0783124372e-09, /* 0xb1ae7d4f */
+ -1.0253783315e-01, /* 0xbdd1ff5b */
+ -4.6101160049e+00, /* 0xc0938612 */
+ -5.7847221375e+01, /* 0xc267638e */
+ -2.2824453735e+02, /* 0xc3643e9a */
+ -2.1921012878e+02, /* 0xc35b35cb */
+};
+#ifdef __STDC__
+static const float qs3[6] = {
+#else
+static float qs3[6] = {
+#endif
+  4.7665153503e+01, /* 0x423ea91e */
+  6.7386511230e+02, /* 0x4428775e */
+  3.3801528320e+03, /* 0x45534272 */
+  5.5477290039e+03, /* 0x45ad5dd5 */
+  1.9031191406e+03, /* 0x44ede3d0 */
+ -1.3520118713e+02, /* 0xc3073381 */
+};
+
+#ifdef __STDC__
+static const float qr2[6] = {/* for x in [2.8570,2]=1/[0.3499,0.5] */
+#else
+static float qr2[6] = {/* for x in [2.8570,2]=1/[0.3499,0.5] */
+#endif
+ -1.7838172539e-07, /* 0xb43f8932 */
+ -1.0251704603e-01, /* 0xbdd1f475 */
+ -2.7522056103e+00, /* 0xc0302423 */
+ -1.9663616180e+01, /* 0xc19d4f16 */
+ -4.2325313568e+01, /* 0xc2294d1f */
+ -2.1371921539e+01, /* 0xc1aaf9b2 */
+};
+#ifdef __STDC__
+static const float qs2[6] = {
+#else
+static float qs2[6] = {
+#endif
+  2.9533363342e+01, /* 0x41ec4454 */
+  2.5298155212e+02, /* 0x437cfb47 */
+  7.5750280762e+02, /* 0x443d602e */
+  7.3939318848e+02, /* 0x4438d92a */
+  1.5594900513e+02, /* 0x431bf2f2 */
+ -4.9594988823e+00, /* 0xc09eb437 */
+};
+
+#ifdef __STDC__
+	static float qonef(float x)
+#else
+	static float qonef(x)
+	float x;
+#endif
+{
+#ifdef __STDC__
+	const float *p,*q;
+#else
+	float *p,*q;
+#endif
+	float  s,r,z;
+	__int32_t ix;
+	ix = CYG_LIBM_WORD(x);
+	ix &= 0x7fffffff;
+	if(ix>=0x40200000)     {p = qr8; q= qs8;}
+	else if(ix>=0x40f71c58){p = qr5; q= qs5;}
+	else if(ix>=0x4036db68){p = qr3; q= qs3;}
+      else {p = qr2; q= qs2;}
+	z = one/(x*x);
+	r = p[0]+z*(p[1]+z*(p[2]+z*(p[3]+z*(p[4]+z*p[5]))));
+	s = one+z*(q[0]+z*(q[1]+z*(q[2]+z*(q[3]+z*(q[4]+z*q[5])))));
+	return ((float).375 + r/s)/x;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_j1.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_jn.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_jn.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_jn.c
@@ -0,0 +1,274 @@
+//===========================================================================
+//
+//      ef_jn.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_jn.c -- float version of e_jn.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+invsqrtpi=  5.6418961287e-01, /* 0x3f106ebb */
+two   =  2.0000000000e+00, /* 0x40000000 */
+one   =  1.0000000000e+00; /* 0x3F800000 */
+
+#ifdef __STDC__
+static const float zero  =  0.0000000000e+00;
+#else
+static float zero  =  0.0000000000e+00;
+#endif
+
+#ifdef __STDC__
+	float __ieee754_jnf(int n, float x)
+#else
+	float __ieee754_jnf(n,x)
+	int n; float x;
+#endif
+{
+	__int32_t i,hx,ix, sgn;
+	float a, b, temp, di;
+	float z, w;
+
+    /* J(-n,x) = (-1)^n * J(n, x), J(n, -x) = (-1)^n * J(n, x)
+     * Thus, J(-n,x) = J(n,-x)
+     */
+	hx = CYG_LIBM_WORD(x);
+	ix = 0x7fffffff&hx;
+    /* if J(n,NaN) is NaN */
+	if(FLT_UWORD_IS_NAN(ix)) return x+x;
+	if(n<0){
+		n = -n;
+		x = -x;
+		hx ^= 0x80000000;
+	}
+	if(n==0) return(__ieee754_j0f(x));
+	if(n==1) return(__ieee754_j1f(x));
+	sgn = (n&1)&(hx>>31);	/* even n -- 0, odd n -- sign(x) */
+	x = fabsf(x);
+	if(FLT_UWORD_IS_ZERO(ix)||FLT_UWORD_IS_INFINITE(ix))
+	    b = zero;
+	else if((float)n<=x) {
+		/* Safe to use J(n+1,x)=2n/x *J(n,x)-J(n-1,x) */
+	    a = __ieee754_j0f(x);
+	    b = __ieee754_j1f(x);
+	    for(i=1;i<n;i++){
+		temp = b;
+		b = b*((float)(i+i)/x) - a; /* avoid underflow */
+		a = temp;
+	    }
+	} else {
+	    if(ix<0x30800000) {	/* x < 2**-29 */
+    /* x is tiny, return the first Taylor expansion of J(n,x)
+     * J(n,x) = 1/n!*(x/2)^n  - ...
+     */
+		if(n>33)	/* underflow */
+		    b = zero;
+		else {
+		    temp = x*(float)0.5; b = temp;
+		    for (a=one,i=2;i<=n;i++) {
+			a *= (float)i;		/* a = n! */
+			b *= temp;		/* b = (x/2)^n */
+		    }
+		    b = b/a;
+		}
+	    } else {
+		/* use backward recurrence */
+		/*			x      x^2      x^2
+		 *  J(n,x)/J(n-1,x) =  ----   ------   ------   .....
+		 *			2n  - 2(n+1) - 2(n+2)
+		 *
+		 *			1      1        1
+		 *  (for large x)   =  ----  ------   ------   .....
+		 *			2n   2(n+1)   2(n+2)
+		 *			-- - ------ - ------ -
+		 *			 x     x         x
+		 *
+		 * Let w = 2n/x and h=2/x, then the above quotient
+		 * is equal to the continued fraction:
+		 *		    1
+		 *	= -----------------------
+		 *		       1
+		 *	   w - -----------------
+		 *			  1
+		 *	        w+h - ---------
+		 *		       w+2h - ...
+		 *
+		 * To determine how many terms needed, let
+		 * Q(0) = w, Q(1) = w(w+h) - 1,
+		 * Q(k) = (w+k*h)*Q(k-1) - Q(k-2),
+		 * When Q(k) > 1e4	good for single
+		 * When Q(k) > 1e9	good for double
+		 * When Q(k) > 1e17	good for quadruple
+		 */
+	    /* determine k */
+		float t,v;
+		float q0,q1,h,tmp; __int32_t k,m;
+		w  = (n+n)/(float)x; h = (float)2.0/(float)x;
+		q0 = w;  z = w+h; q1 = w*z - (float)1.0; k=1;
+		while(q1<(float)1.0e9) {
+			k += 1; z += h;
+			tmp = z*q1 - q0;
+			q0 = q1;
+			q1 = tmp;
+		}
+		m = n+n;
+		for(t=zero, i = 2*(n+k); i>=m; i -= 2) t = one/(i/x-t);
+		a = t;
+		b = one;
+		/*  estimate log((2/x)^n*n!) = n*log(2/x)+n*ln(n)
+		 *  Hence, if n*(log(2n/x)) > ...
+		 *  single 8.8722839355e+01
+		 *  double 7.09782712893383973096e+02
+		 *  long double 1.1356523406294143949491931077970765006170e+04
+		 *  then recurrent value may overflow and the result is
+		 *  likely underflow to zero
+		 */
+		tmp = n;
+		v = two/x;
+		tmp = tmp*__ieee754_logf(fabsf(v*tmp));
+		if(tmp<(float)8.8721679688e+01) {
+		    for(i=n-1,di=(float)(i+i);i>0;i--){
+		        temp = b;
+			b *= di;
+			b  = b/x - a;
+		        a = temp;
+			di -= two;
+		    }
+		} else {
+		    for(i=n-1,di=(float)(i+i);i>0;i--){
+		        temp = b;
+			b *= di;
+			b  = b/x - a;
+		        a = temp;
+			di -= two;
+		    /* scale b to avoid spurious overflow */
+			if(b>(float)1e10) {
+			    a /= b;
+			    t /= b;
+			    b  = one;
+			}
+		    }
+		}
+		b = (t*__ieee754_j0f(x)/b);
+	    }
+	}
+	if(sgn==1) return -b; else return b;
+}
+
+#ifdef __STDC__
+	float __ieee754_ynf(int n, float x)
+#else
+	float __ieee754_ynf(n,x)
+	int n; float x;
+#endif
+{
+	__int32_t i,hx,ix,ib;
+	__int32_t sign;
+	float a, b, temp;
+
+	hx = CYG_LIBM_WORD(x);
+	ix = 0x7fffffff&hx;
+    /* if Y(n,NaN) is NaN */
+	if(FLT_UWORD_IS_NAN(ix)) return x+x;
+	if(FLT_UWORD_IS_ZERO(ix)) return -one/zero;
+	if(hx<0) return zero/zero;
+	sign = 1;
+	if(n<0){
+		n = -n;
+		sign = 1 - ((n&1)<<1);
+	}
+	if(n==0) return(__ieee754_y0f(x));
+	if(n==1) return(sign*__ieee754_y1f(x));
+	if(FLT_UWORD_IS_INFINITE(ix)) return zero;
+
+	a = __ieee754_y0f(x);
+	b = __ieee754_y1f(x);
+	/* quit if b is -inf */
+	ib = CYG_LIBM_WORD(b);
+	for(i=1;i<n&&ib!=0xff800000;i++){
+	    temp = b;
+	    b = ((float)(i+i)/x)*b - a;
+	    ib = CYG_LIBM_WORD(b);
+	    a = temp;
+	}
+	if(sign>0) return b; else return -b;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_jn.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_lgamma.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_lgamma.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_lgamma.c
@@ -0,0 +1,93 @@
+//===========================================================================
+//
+//      ef_lgamma.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* @(#)e_lgamma.c 1.3 95/01/18 */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunSoft, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+/* __ieee754_lgamma(x)
+ * Return the logarithm of the Gamma function of x.
+ *
+ * Method: call __ieee754_lgamma_r
+ */
+
+#include <math.h>
+#include "mathincl/fdlibm.h"
+
+float
+__ieee754_lgammaf(float x)
+{
+        return __ieee754_lgammaf_r(x,&signgam);
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_lgamma.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_lgamma_r.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_lgamma_r.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_lgamma_r.c
@@ -0,0 +1,316 @@
+//===========================================================================
+//
+//      ef_lgamma_r.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+/* erf_lgamma.c -- float version of er_lgamma.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+two23=  8.3886080000e+06, /* 0x4b000000 */
+half=  5.0000000000e-01, /* 0x3f000000 */
+one =  1.0000000000e+00, /* 0x3f800000 */
+pi  =  3.1415927410e+00, /* 0x40490fdb */
+a0  =  7.7215664089e-02, /* 0x3d9e233f */
+a1  =  3.2246702909e-01, /* 0x3ea51a66 */
+a2  =  6.7352302372e-02, /* 0x3d89f001 */
+a3  =  2.0580807701e-02, /* 0x3ca89915 */
+a4  =  7.3855509982e-03, /* 0x3bf2027e */
+a5  =  2.8905137442e-03, /* 0x3b3d6ec6 */
+a6  =  1.1927076848e-03, /* 0x3a9c54a1 */
+a7  =  5.1006977446e-04, /* 0x3a05b634 */
+a8  =  2.2086278477e-04, /* 0x39679767 */
+a9  =  1.0801156895e-04, /* 0x38e28445 */
+a10 =  2.5214456400e-05, /* 0x37d383a2 */
+a11 =  4.4864096708e-05, /* 0x383c2c75 */
+tc  =  1.4616321325e+00, /* 0x3fbb16c3 */
+tf  = -1.2148628384e-01, /* 0xbdf8cdcd */
+/* tt = -(tail of tf) */
+tt  =  6.6971006518e-09, /* 0x31e61c52 */
+t0  =  4.8383611441e-01, /* 0x3ef7b95e */
+t1  = -1.4758771658e-01, /* 0xbe17213c */
+t2  =  6.4624942839e-02, /* 0x3d845a15 */
+t3  = -3.2788541168e-02, /* 0xbd064d47 */
+t4  =  1.7970675603e-02, /* 0x3c93373d */
+t5  = -1.0314224288e-02, /* 0xbc28fcfe */
+t6  =  6.1005386524e-03, /* 0x3bc7e707 */
+t7  = -3.6845202558e-03, /* 0xbb7177fe */
+t8  =  2.2596477065e-03, /* 0x3b141699 */
+t9  = -1.4034647029e-03, /* 0xbab7f476 */
+t10 =  8.8108185446e-04, /* 0x3a66f867 */
+t11 = -5.3859531181e-04, /* 0xba0d3085 */
+t12 =  3.1563205994e-04, /* 0x39a57b6b */
+t13 = -3.1275415677e-04, /* 0xb9a3f927 */
+t14 =  3.3552918467e-04, /* 0x39afe9f7 */
+u0  = -7.7215664089e-02, /* 0xbd9e233f */
+u1  =  6.3282704353e-01, /* 0x3f2200f4 */
+u2  =  1.4549225569e+00, /* 0x3fba3ae7 */
+u3  =  9.7771751881e-01, /* 0x3f7a4bb2 */
+u4  =  2.2896373272e-01, /* 0x3e6a7578 */
+u5  =  1.3381091878e-02, /* 0x3c5b3c5e */
+v1  =  2.4559779167e+00, /* 0x401d2ebe */
+v2  =  2.1284897327e+00, /* 0x4008392d */
+v3  =  7.6928514242e-01, /* 0x3f44efdf */
+v4  =  1.0422264785e-01, /* 0x3dd572af */
+v5  =  3.2170924824e-03, /* 0x3b52d5db */
+s0  = -7.7215664089e-02, /* 0xbd9e233f */
+s1  =  2.1498242021e-01, /* 0x3e5c245a */
+s2  =  3.2577878237e-01, /* 0x3ea6cc7a */
+s3  =  1.4635047317e-01, /* 0x3e15dce6 */
+s4  =  2.6642270386e-02, /* 0x3cda40e4 */
+s5  =  1.8402845599e-03, /* 0x3af135b4 */
+s6  =  3.1947532989e-05, /* 0x3805ff67 */
+r1  =  1.3920053244e+00, /* 0x3fb22d3b */
+r2  =  7.2193557024e-01, /* 0x3f38d0c5 */
+r3  =  1.7193385959e-01, /* 0x3e300f6e */
+r4  =  1.8645919859e-02, /* 0x3c98bf54 */
+r5  =  7.7794247773e-04, /* 0x3a4beed6 */
+r6  =  7.3266842264e-06, /* 0x36f5d7bd */
+w0  =  4.1893854737e-01, /* 0x3ed67f1d */
+w1  =  8.3333335817e-02, /* 0x3daaaaab */
+w2  = -2.7777778450e-03, /* 0xbb360b61 */
+w3  =  7.9365057172e-04, /* 0x3a500cfd */
+w4  = -5.9518753551e-04, /* 0xba1c065c */
+w5  =  8.3633989561e-04, /* 0x3a5b3dd2 */
+w6  = -1.6309292987e-03; /* 0xbad5c4e8 */
+
+#ifdef __STDC__
+static const float zero=  0.0000000000e+00;
+#else
+static float zero=  0.0000000000e+00;
+#endif
+
+#ifdef __STDC__
+	static float sin_pif(float x)
+#else
+	static float sin_pif(x)
+	float x;
+#endif
+{
+	float y,z;
+	__int32_t n,ix;
+
+	ix = CYG_LIBM_WORD(x);
+	ix &= 0x7fffffff;
+
+	if(ix<0x3e800000) return __kernel_sinf(pi*x,zero,0);
+	y = -x;		/* x is assume negative */
+
+    /*
+     * argument reduction, make sure inexact flag not raised if input
+     * is an integer
+     */
+	z = floorf(y);
+	if(z!=y) {				/* inexact anyway */
+	    y  *= (float)0.5;
+	    y   = (float)2.0*(y - floorf(y));	/* y = |x| mod 2.0 */
+	    n   = (__int32_t) (y*(float)4.0);
+	} else {
+            if(ix>=0x4b800000) {
+                y = zero; n = 0;                 /* y must be even */
+            } else {
+                if(ix<0x4b000000) z = y+two23;	/* exact */
+		n = CYG_LIBM_WORD(z);
+		n &= 1;
+                y  = n;
+                n<<= 2;
+            }
+        }
+	switch (n) {
+	    case 0:   y =  __kernel_sinf(pi*y,zero,0); break;
+	    case 1:
+	    case 2:   y =  __kernel_cosf(pi*((float)0.5-y),zero); break;
+	    case 3:
+	    case 4:   y =  __kernel_sinf(pi*(one-y),zero,0); break;
+	    case 5:
+	    case 6:   y = -__kernel_cosf(pi*(y-(float)1.5),zero); break;
+	    default:  y =  __kernel_sinf(pi*(y-(float)2.0),zero,0); break;
+	    }
+	return -y;
+}
+
+
+#ifdef __STDC__
+	float __ieee754_lgammaf_r(float x, int *signgamp)
+#else
+	float __ieee754_lgammaf_r(x,signgamp)
+	float x; int *signgamp;
+#endif
+{
+	float t,y,z,nadj,p,p1,p2,p3,q,r,w;
+	__int32_t i,hx,ix;
+
+	hx = CYG_LIBM_WORD(x);
+
+    /* purge off +-inf, NaN, +-0, and negative arguments */
+	*signgamp = 1;
+	ix = hx&0x7fffffff;
+	if(ix>=0x7f800000) return x*x;
+	if(ix==0) return one/zero;
+	if(ix<0x1c800000) {	/* |x|<2**-70, return -log(|x|) */
+	    if(hx<0) {
+	        *signgamp = -1;
+	        return -__ieee754_logf(-x);
+	    } else return -__ieee754_logf(x);
+	}
+	if(hx<0) {
+	    if(ix>=0x4b000000)	/* |x|>=2**23, must be -integer */
+		return one/zero;
+	    t = sin_pif(x);
+	    if(t==zero) return one/zero; /* -integer */
+	    nadj = __ieee754_logf(pi/fabsf(t*x));
+	    if(t<zero) *signgamp = -1;
+	    x = -x;
+	}
+
+    /* purge off 1 and 2 */
+	if (ix==0x3f800000||ix==0x40000000) r = 0;
+    /* for x < 2.0 */
+	else if(ix<0x40000000) {
+	    if(ix<=0x3f666666) {	/* lgamma(x) = lgamma(x+1)-log(x) */
+		r = -__ieee754_logf(x);
+		if(ix>=0x3f3b4a20) {y = one-x; i= 0;}
+		else if(ix>=0x3e6d3308) {y= x-(tc-one); i=1;}
+		else {y = x; i=2;}
+	    } else {
+		r = zero;
+	        if(ix>=0x3fdda618) {y=(float)2.0-x;i=0;} /* [1.7316,2] */
+	        else if(ix>=0x3F9da620) {y=x-tc;i=1;} /* [1.23,1.73] */
+		else {y=x-one;i=2;}
+	    }
+	    switch(i) {
+	      case 0:
+		z = y*y;
+		p1 = a0+z*(a2+z*(a4+z*(a6+z*(a8+z*a10))));
+		p2 = z*(a1+z*(a3+z*(a5+z*(a7+z*(a9+z*a11)))));
+		p  = y*p1+p2;
+		r  += (p-(float)0.5*y); break;
+	      case 1:
+		z = y*y;
+		w = z*y;
+		p1 = t0+w*(t3+w*(t6+w*(t9 +w*t12)));	/* parallel comp */
+		p2 = t1+w*(t4+w*(t7+w*(t10+w*t13)));
+		p3 = t2+w*(t5+w*(t8+w*(t11+w*t14)));
+		p  = z*p1-(tt-w*(p2+y*p3));
+		r += (tf + p); break;
+	      case 2:
+		p1 = y*(u0+y*(u1+y*(u2+y*(u3+y*(u4+y*u5)))));
+		p2 = one+y*(v1+y*(v2+y*(v3+y*(v4+y*v5))));
+		r += (-(float)0.5*y + p1/p2);
+	    }
+	}
+	else if(ix<0x41000000) {			/* x < 8.0 */
+	    i = (__int32_t)x;
+	    t = zero;
+	    y = x-(float)i;
+	    p = y*(s0+y*(s1+y*(s2+y*(s3+y*(s4+y*(s5+y*s6))))));
+	    q = one+y*(r1+y*(r2+y*(r3+y*(r4+y*(r5+y*r6)))));
+	    r = half*y+p/q;
+	    z = one;	/* lgamma(1+s) = log(s) + lgamma(s) */
+	    switch(i) {
+	    case 7: z *= (y+(float)6.0);	/* FALLTHRU */
+	    case 6: z *= (y+(float)5.0);	/* FALLTHRU */
+	    case 5: z *= (y+(float)4.0);	/* FALLTHRU */
+	    case 4: z *= (y+(float)3.0);	/* FALLTHRU */
+	    case 3: z *= (y+(float)2.0);	/* FALLTHRU */
+		    r += __ieee754_logf(z); break;
+	    }
+    /* 8.0 <= x < 2**58 */
+	} else if (ix < 0x5c800000) {
+	    t = __ieee754_logf(x);
+	    z = one/x;
+	    y = z*z;
+	    w = w0+z*(w1+y*(w2+y*(w3+y*(w4+y*(w5+y*w6)))));
+	    r = (x-half)*(t-one)+w;
+	} else
+    /* 2**58 <= x <= inf */
+	    r =  x*(__ieee754_logf(x)-one);
+	if(hx<0) r = nadj - r;
+	return r;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_lgamma_r.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_log.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_log.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_log.c
@@ -0,0 +1,159 @@
+//===========================================================================
+//
+//      ef_log.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_log.c -- float version of e_log.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+ln2_hi =   6.9313812256e-01,	/* 0x3f317180 */
+ln2_lo =   9.0580006145e-06,	/* 0x3717f7d1 */
+two25 =    3.355443200e+07,	/* 0x4c000000 */
+Lg1 = 6.6666668653e-01,	/* 3F2AAAAB */
+Lg2 = 4.0000000596e-01,	/* 3ECCCCCD */
+Lg3 = 2.8571429849e-01, /* 3E924925 */
+Lg4 = 2.2222198546e-01, /* 3E638E29 */
+Lg5 = 1.8183572590e-01, /* 3E3A3325 */
+Lg6 = 1.5313838422e-01, /* 3E1CD04F */
+Lg7 = 1.4798198640e-01; /* 3E178897 */
+
+#ifdef __STDC__
+static const float zero   =  0.0;
+#else
+static float zero   =  0.0;
+#endif
+
+#ifdef __STDC__
+	float __ieee754_logf(float x)
+#else
+	float __ieee754_logf(x)
+	float x;
+#endif
+{
+	float hfsq,f,s,z,R,w,t1,t2,dk;
+	__int32_t k,ix,i,j;
+
+	ix = CYG_LIBM_WORD(x);
+
+	k=0;
+	if (FLT_UWORD_IS_ZERO(ix&0x7fffffff))
+	    return -two25/zero;		/* log(+-0)=-inf */
+        if (ix<0) return (x-x)/zero;	/* log(-#) = NaN */
+	if (!FLT_UWORD_IS_FINITE(ix)) return x+x;
+	if (FLT_UWORD_IS_SUBNORMAL(ix)) {
+	    k -= 25; x *= two25; /* subnormal number, scale up x */
+	    ix = CYG_LIBM_WORD(x);
+	}
+	k += (ix>>23)-127;
+	ix &= 0x007fffff;
+	i = (ix+(0x95f64<<3))&0x800000;
+	SET_FLOAT_WORD(x,ix|(i^0x3f800000));	/* normalize x or x/2 */
+	k += (i>>23);
+	f = x-(float)1.0;
+	if((0x007fffff&(15+ix))<16) {	/* |f| < 2**-20 */
+           if(f==zero) { if(k==0) return zero;  else {dk=(float)k;
+                                return dk*ln2_hi+dk*ln2_lo;}}
+	    R = f*f*((float)0.5-(float)0.33333333333333333*f);
+	    if(k==0) return f-R; else {dk=(float)k;
+		     return dk*ln2_hi-((R-dk*ln2_lo)-f);}
+	}
+	s = f/((float)2.0+f);
+	dk = (float)k;
+	z = s*s;
+	i = ix-(0x6147a<<3);
+	w = z*z;
+	j = (0x6b851<<3)-ix;
+	t1= w*(Lg2+w*(Lg4+w*Lg6));
+	t2= z*(Lg1+w*(Lg3+w*(Lg5+w*Lg7)));
+	i |= j;
+	R = t2+t1;
+	if(i>0) {
+	    hfsq=(float)0.5*f*f;
+	    if(k==0) return f-(hfsq-s*(hfsq+R)); else
+		     return dk*ln2_hi-((hfsq-(s*(hfsq+R)+dk*ln2_lo))-f);
+	} else {
+	    if(k==0) return f-s*(f-R); else
+		     return dk*ln2_hi-((s*(f-R)-dk*ln2_lo)-f);
+	}
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_log.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_log10.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_log10.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_log10.c
@@ -0,0 +1,129 @@
+//===========================================================================
+//
+//      ef_log10.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_log10.c -- float version of e_log10.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+two25      =  3.3554432000e+07, /* 0x4c000000 */
+ivln10     =  4.3429449201e-01, /* 0x3ede5bd9 */
+log10_2hi  =  3.0102920532e-01, /* 0x3e9a2080 */
+log10_2lo  =  7.9034151668e-07; /* 0x355427db */
+
+#ifdef __STDC__
+static const float zero   =  0.0;
+#else
+static float zero   =  0.0;
+#endif
+
+#ifdef __STDC__
+	float __ieee754_log10f(float x)
+#else
+	float __ieee754_log10f(x)
+	float x;
+#endif
+{
+	float y,z;
+	__int32_t i,k,hx;
+
+	hx = CYG_LIBM_WORD(x);
+
+        k=0;
+        if (FLT_UWORD_IS_ZERO(hx&0x7fffffff))
+            return -two25/zero;             /* log(+-0)=-inf */
+        if (hx<0) return (x-x)/zero;        /* log(-#) = NaN */
+	if (!FLT_UWORD_IS_FINITE(hx)) return x+x;
+        if (FLT_UWORD_IS_SUBNORMAL(hx)) {
+            k -= 25; x *= two25; /* subnormal number, scale up x */
+	    hx = CYG_LIBM_WORD(x);
+        }
+	k += (hx>>23)-127;
+	i  = ((__uint32_t)k&0x80000000)>>31;
+        hx = (hx&0x007fffff)|((0x7f-i)<<23);
+        y  = (float)(k+i);
+	SET_FLOAT_WORD(x,hx);
+	z  = y*log10_2lo + ivln10*__ieee754_logf(x);
+	return  z+y*log10_2hi;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_log10.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_pow.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_pow.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_pow.c
@@ -0,0 +1,325 @@
+//========================================================================
+//
+//      ef_pow.c
+//
+//      Part of the standard mathematical function library
+//
+//========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     jlarmour
+// Contributors:
+// Date:          2001-07-20
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+/* ef_pow.c -- float version of e_pow.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+#include <pkgconf/libm.h>   // Configuration header
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+bp[] = {1.0, 1.5,},
+dp_h[] = { 0.0, 5.84960938e-01,}, /* 0x3f15c000 */
+dp_l[] = { 0.0, 1.56322085e-06,}, /* 0x35d1cfdc */
+zero    =  0.0,
+one	=  1.0,
+two	=  2.0,
+two24	=  16777216.0,	/* 0x4b800000 */
+huge	=  1.0e30,
+tiny    =  1.0e-30,
+	/* poly coefs for (3/2)*(log(x)-2s-2/3*s**3 */
+L1  =  6.0000002384e-01, /* 0x3f19999a */
+L2  =  4.2857143283e-01, /* 0x3edb6db7 */
+L3  =  3.3333334327e-01, /* 0x3eaaaaab */
+L4  =  2.7272811532e-01, /* 0x3e8ba305 */
+L5  =  2.3066075146e-01, /* 0x3e6c3255 */
+L6  =  2.0697501302e-01, /* 0x3e53f142 */
+P1   =  1.6666667163e-01, /* 0x3e2aaaab */
+P2   = -2.7777778450e-03, /* 0xbb360b61 */
+P3   =  6.6137559770e-05, /* 0x388ab355 */
+P4   = -1.6533901999e-06, /* 0xb5ddea0e */
+P5   =  4.1381369442e-08, /* 0x3331bb4c */
+lg2  =  6.9314718246e-01, /* 0x3f317218 */
+lg2_h  =  6.93145752e-01, /* 0x3f317200 */
+lg2_l  =  1.42860654e-06, /* 0x35bfbe8c */
+ovt =  4.2995665694e-08, /* -(128-log2(ovfl+.5ulp)) */
+cp    =  9.6179670095e-01, /* 0x3f76384f =2/(3ln2) */
+cp_h  =  9.6179199219e-01, /* 0x3f763800 =head of cp */
+cp_l  =  4.7017383622e-06, /* 0x369dc3a0 =tail of cp_h */
+ivln2    =  1.4426950216e+00, /* 0x3fb8aa3b =1/ln2 */
+ivln2_h  =  1.4426879883e+00, /* 0x3fb8aa00 =16b 1/ln2*/
+ivln2_l  =  7.0526075433e-06; /* 0x36eca570 =1/ln2 tail*/
+
+/* VAE
+static float
+my_abs_f( float x )
+{
+    Cyg_libm_ieee_float_shape_type t;
+
+    t.value = x;
+
+    t.number.sign = 0;
+
+    return t.value;
+} // my_abs_f()
+*/
+
+#ifdef __STDC__
+	float __ieee754_powf(float x, float y)
+#else
+	float __ieee754_powf(x,y)
+	float x, y;
+#endif
+{
+	float z,ax,z_h,z_l,p_h,p_l;
+	float y1,t1,t2,r,s,t,u,v,w;
+	__int32_t i,j,k,yisint,n;
+	__int32_t hx,hy,ix,iy,is;
+
+	hx = CYG_LIBM_WORD(x);
+	hy = CYG_LIBM_WORD(y);
+	ix = hx&0x7fffffff;  iy = hy&0x7fffffff;
+
+    /* y==zero: x**0 = 1 */
+	if(FLT_UWORD_IS_ZERO(iy)) return one;
+
+    /* x|y==NaN return NaN unless x==1 then return 1 */
+	if(FLT_UWORD_IS_NAN(ix) ||
+	   FLT_UWORD_IS_NAN(iy)) { // VAE
+	    if(ix==0x3f800000) return one;
+	    else return 2143289344u;
+    }
+    /* determine if y is an odd int when x < 0
+     * yisint = 0	... y is not an integer
+     * yisint = 1	... y is an odd int
+     * yisint = 2	... y is an even int
+     */
+	yisint  = 0;
+	if(hx<0) {
+	    if(iy>=0x4b800000) yisint = 2; /* even integer y */
+	    else if(iy>=0x3f800000) {
+		k = (iy>>23)-0x7f;	   /* exponent */
+		j = iy>>(23-k);
+		if((j<<(23-k))==iy) yisint = 2-(j&1);
+	    }
+	}
+
+    /* special value of y */
+	if (FLT_UWORD_IS_INFINITE(iy)) {	/* y is +-inf */
+	    if (ix==0x3f800000)
+		return one;		/* +-1**+-inf = 1 */
+	    else if (ix > 0x3f800000)/* (|x|>1)**+-inf = inf,0 */
+	        return (hy>=0)? y: zero;
+	    else			/* (|x|<1)**-,+inf = inf,0 */
+	        return (hy<0)?-y: zero;
+	}
+	if(iy==0x3f800000) {	/* y is  +-1 */
+	    if(hy<0) return one/x; else return x;
+	}
+	if(hy==0x40000000) return x*x; /* y is  2 */
+	if(hy==0x3f000000) {	/* y is  0.5 */
+	    if(hx>=0)	/* x >= +0 */
+	    return __ieee754_sqrtf(x);
+	}
+
+	ax   = fabsf(x);
+    /* special value of x */
+	if(FLT_UWORD_IS_INFINITE(ix)||FLT_UWORD_IS_ZERO(ix)||ix==0x3f800000){
+	    z = ax;			/*x is +-0,+-inf,+-1*/
+	    if(hy<0) z = one/z;	/* z = (1/|x|) */
+	    if(hx<0) {
+		if(((ix-0x3f800000)|yisint)==0) {
+		    z = (z-z)/(z-z); /* (-1)**non-int is NaN */
+		} else if(yisint==1)
+		    z = -z;		/* (x<0)**odd = -(|x|**odd) */
+	    }
+	    return z;
+	}
+
+    /* (x<0)**(non-int) is NaN */
+	if(((((__uint32_t)hx>>31)-1)|yisint)==0) return (x-x)/(x-x);
+
+    /* |y| is huge */
+	if(iy>0x4d000000) { /* if |y| > 2**27 */
+	/* over/underflow if x is not close to one */
+	    if(ix<0x3f7ffff8) return (hy<0)? huge*huge:tiny*tiny;
+	    if(ix>0x3f800007) return (hy>0)? huge*huge:tiny*tiny;
+	/* now |1-x| is tiny <= 2**-20, suffice to compute
+	   log(x) by x-x^2/2+x^3/3-x^4/4 */
+	    t = ax-1;		/* t has 20 trailing zeros */
+	    w = (t*t)*((float)0.5-t*((float)0.333333333333-t*(float)0.25));
+	    u = ivln2_h*t;	/* ivln2_h has 16 sig. bits */
+	    v = t*ivln2_l-w*ivln2;
+	    t1 = u+v;
+	    is = CYG_LIBM_WORD(t1);
+	    SET_FLOAT_WORD(t1,is&0xfffff000);
+	    t2 = v-(t1-u);
+	} else {
+	    float s2,s_h,s_l,t_h,t_l;
+	    n = 0;
+	/* take care subnormal number */
+	    if(FLT_UWORD_IS_SUBNORMAL(ix))
+		{ax *= two24; n -= 24; ix = CYG_LIBM_WORD(ax); }
+	    n  += ((ix)>>23)-0x7f;
+	    j  = ix&0x007fffff;
+	/* determine interval */
+	    ix = j|0x3f800000;		/* normalize ix */
+	    if(j<=0x1cc471) k=0;	/* |x|<sqrt(3/2) */
+	    else if(j<0x5db3d7) k=1;	/* |x|<sqrt(3)   */
+	    else {k=0;n+=1;ix -= 0x00800000;}
+	    SET_FLOAT_WORD(ax,ix);
+
+	/* compute s = s_h+s_l = (x-1)/(x+1) or (x-1.5)/(x+1.5) */
+	    u = ax-bp[k];		/* bp[0]=1.0, bp[1]=1.5 */
+	    v = one/(ax+bp[k]);
+	    s = u*v;
+	    s_h = s;
+	    is = CYG_LIBM_WORD(s_h);
+	    SET_FLOAT_WORD(s_h,is&0xfffff000);
+	/* t_h=ax+bp[k] High */
+	    SET_FLOAT_WORD(t_h,((ix>>1)|0x20000000)+0x0040000+(k<<21));
+	    t_l = ax - (t_h-bp[k]);
+	    s_l = v*((u-s_h*t_h)-s_h*t_l);
+	/* compute log(ax) */
+	    s2 = s*s;
+	    r = s2*s2*(L1+s2*(L2+s2*(L3+s2*(L4+s2*(L5+s2*L6)))));
+	    r += s_l*(s_h+s);
+	    s2  = s_h*s_h;
+	    t_h = (float)3.0+s2+r;
+	    is = CYG_LIBM_WORD(t_h);
+	    SET_FLOAT_WORD(t_h,is&0xfffff000);
+	    t_l = r-((t_h-(float)3.0)-s2);
+	/* u+v = s*(1+...) */
+	    u = s_h*t_h;
+	    v = s_l*t_h+t_l*s;
+	/* 2/(3log2)*(s+...) */
+	    p_h = u+v;
+	    is = CYG_LIBM_WORD(p_h);
+	    SET_FLOAT_WORD(p_h,is&0xfffff000);
+	    p_l = v-(p_h-u);
+	    z_h = cp_h*p_h;		/* cp_h+cp_l = 2/(3*log2) */
+	    z_l = cp_l*p_h+p_l*cp+dp_l[k];
+	/* log2(ax) = (s+..)*2/(3*log2) = n + dp_h + z_h + z_l */
+	    t = (float)n;
+	    t1 = (((z_h+z_l)+dp_h[k])+t);
+	    is = CYG_LIBM_WORD(t1);
+	    SET_FLOAT_WORD(t1,is&0xfffff000);
+	    t2 = z_l-(((t1-t)-dp_h[k])-z_h);
+	}
+
+	s = one; /* s (sign of result -ve**odd) = -1 else = 1 */
+	if(((((__uint32_t)hx>>31)-1)|(yisint-1))==0)
+	    s = -one;	/* (-ve)**(odd int) */
+
+    /* split up y into y1+y2 and compute (y1+y2)*(t1+t2) */
+	is = CYG_LIBM_WORD(y);
+	SET_FLOAT_WORD(y1,is&0xfffff000);
+	p_l = (y-y1)*t1+y*t2;
+	p_h = y1*t1;
+	z = p_l+p_h;
+	j = CYG_LIBM_WORD(z);
+	i = j&0x7fffffff;
+	if (j>0) {
+	    if (i>FLT_UWORD_EXP_MAX)
+	        return s*huge*huge;			/* overflow */
+	    else if (i==FLT_UWORD_EXP_MAX)
+	        if(p_l+ovt>z-p_h) return s*huge*huge;	/* overflow */
+        } else {
+	    if (i>FLT_UWORD_EXP_MIN)
+	        return s*tiny*tiny;			/* underflow */
+	    else if (i==FLT_UWORD_EXP_MIN)
+	        if(p_l<=z-p_h) return s*tiny*tiny;	/* underflow */
+	}
+    /*
+     * compute 2**(p_h+p_l)
+     */
+	k = (i>>23)-0x7f;
+	n = 0;
+	if(i>0x3f000000) {		/* if |z| > 0.5, set n = [z+0.5] */
+	    n = j+(0x00800000>>(k+1));
+	    k = ((n&0x7fffffff)>>23)-0x7f;	/* new k for n */
+	    SET_FLOAT_WORD(t,n&~(0x007fffff>>k));
+	    n = ((n&0x007fffff)|0x00800000)>>(23-k);
+	    if(j<0) n = -n;
+	    p_h -= t;
+	}
+	t = p_l+p_h;
+	is = CYG_LIBM_WORD(t);
+	SET_FLOAT_WORD(t,is&0xfffff000);
+	u = t*lg2_h;
+	v = (p_l-(t-p_h))*lg2+t*lg2_l;
+	z = u+v;
+	w = v-(z-u);
+	t  = z*z;
+	t1  = z - t*(P1+t*(P2+t*(P3+t*(P4+t*P5))));
+	r  = (z*t1)/(t1-two)-(w+z*w);
+	z  = one-(r-z);
+	j = CYG_LIBM_WORD(z);
+	j += (n<<23);
+	if((j>>23)<=0) z = scalbn(z,(int)n);	/* subnormal output */
+	else SET_FLOAT_WORD(z,j);
+	return s*z;
+}
+
+// EOF ef_pow.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_rem_pio2.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_rem_pio2.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_rem_pio2.c
@@ -0,0 +1,260 @@
+//===========================================================================
+//
+//      ef_rem_pio2.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_rem_pio2.c -- float version of e_rem_pio2.c
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+/* __ieee754_rem_pio2f(x,y)
+ *
+ * return the remainder of x rem pi/2 in y[0]+y[1]
+ * use __kernel_rem_pio2f()
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+/*
+ * Table of constants for 2/pi, 396 Hex digits (476 decimal) of 2/pi
+ */
+#ifdef __STDC__
+static const __int32_t two_over_pi[] = {
+#else
+static __int32_t two_over_pi[] = {
+#endif
+0xA2, 0xF9, 0x83, 0x6E, 0x4E, 0x44, 0x15, 0x29, 0xFC,
+0x27, 0x57, 0xD1, 0xF5, 0x34, 0xDD, 0xC0, 0xDB, 0x62,
+0x95, 0x99, 0x3C, 0x43, 0x90, 0x41, 0xFE, 0x51, 0x63,
+0xAB, 0xDE, 0xBB, 0xC5, 0x61, 0xB7, 0x24, 0x6E, 0x3A,
+0x42, 0x4D, 0xD2, 0xE0, 0x06, 0x49, 0x2E, 0xEA, 0x09,
+0xD1, 0x92, 0x1C, 0xFE, 0x1D, 0xEB, 0x1C, 0xB1, 0x29,
+0xA7, 0x3E, 0xE8, 0x82, 0x35, 0xF5, 0x2E, 0xBB, 0x44,
+0x84, 0xE9, 0x9C, 0x70, 0x26, 0xB4, 0x5F, 0x7E, 0x41,
+0x39, 0x91, 0xD6, 0x39, 0x83, 0x53, 0x39, 0xF4, 0x9C,
+0x84, 0x5F, 0x8B, 0xBD, 0xF9, 0x28, 0x3B, 0x1F, 0xF8,
+0x97, 0xFF, 0xDE, 0x05, 0x98, 0x0F, 0xEF, 0x2F, 0x11,
+0x8B, 0x5A, 0x0A, 0x6D, 0x1F, 0x6D, 0x36, 0x7E, 0xCF,
+0x27, 0xCB, 0x09, 0xB7, 0x4F, 0x46, 0x3F, 0x66, 0x9E,
+0x5F, 0xEA, 0x2D, 0x75, 0x27, 0xBA, 0xC7, 0xEB, 0xE5,
+0xF1, 0x7B, 0x3D, 0x07, 0x39, 0xF7, 0x8A, 0x52, 0x92,
+0xEA, 0x6B, 0xFB, 0x5F, 0xB1, 0x1F, 0x8D, 0x5D, 0x08,
+0x56, 0x03, 0x30, 0x46, 0xFC, 0x7B, 0x6B, 0xAB, 0xF0,
+0xCF, 0xBC, 0x20, 0x9A, 0xF4, 0x36, 0x1D, 0xA9, 0xE3,
+0x91, 0x61, 0x5E, 0xE6, 0x1B, 0x08, 0x65, 0x99, 0x85,
+0x5F, 0x14, 0xA0, 0x68, 0x40, 0x8D, 0xFF, 0xD8, 0x80,
+0x4D, 0x73, 0x27, 0x31, 0x06, 0x06, 0x15, 0x56, 0xCA,
+0x73, 0xA8, 0xC9, 0x60, 0xE2, 0x7B, 0xC0, 0x8C, 0x6B,
+};
+
+/* This array is like the one in e_rem_pio2.c, but the numbers are
+   single precision and the last 8 bits are forced to 0.  */
+#ifdef __STDC__
+static const __int32_t npio2_hw[] = {
+#else
+static __int32_t npio2_hw[] = {
+#endif
+0x3fc90f00, 0x40490f00, 0x4096cb00, 0x40c90f00, 0x40fb5300, 0x4116cb00,
+0x412fed00, 0x41490f00, 0x41623100, 0x417b5300, 0x418a3a00, 0x4196cb00,
+0x41a35c00, 0x41afed00, 0x41bc7e00, 0x41c90f00, 0x41d5a000, 0x41e23100,
+0x41eec200, 0x41fb5300, 0x4203f200, 0x420a3a00, 0x42108300, 0x4216cb00,
+0x421d1400, 0x42235c00, 0x4229a500, 0x422fed00, 0x42363600, 0x423c7e00,
+0x4242c700, 0x42490f00
+};
+
+/*
+ * invpio2:  24 bits of 2/pi
+ * pio2_1:   first  17 bit of pi/2
+ * pio2_1t:  pi/2 - pio2_1
+ * pio2_2:   second 17 bit of pi/2
+ * pio2_2t:  pi/2 - (pio2_1+pio2_2)
+ * pio2_3:   third  17 bit of pi/2
+ * pio2_3t:  pi/2 - (pio2_1+pio2_2+pio2_3)
+ */
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+zero =  0.0000000000e+00, /* 0x00000000 */
+half =  5.0000000000e-01, /* 0x3f000000 */
+two8 =  2.5600000000e+02, /* 0x43800000 */
+invpio2 =  6.3661980629e-01, /* 0x3f22f984 */
+pio2_1  =  1.5707855225e+00, /* 0x3fc90f80 */
+pio2_1t =  1.0804334124e-05, /* 0x37354443 */
+pio2_2  =  1.0804273188e-05, /* 0x37354400 */
+pio2_2t =  6.0770999344e-11, /* 0x2e85a308 */
+pio2_3  =  6.0770943833e-11, /* 0x2e85a300 */
+pio2_3t =  6.1232342629e-17; /* 0x248d3132 */
+
+#ifdef __STDC__
+	__int32_t __ieee754_rem_pio2f(float x, float *y)
+#else
+	__int32_t __ieee754_rem_pio2f(x,y)
+	float x,y[];
+#endif
+{
+	float z,w,t,r,fn;
+	float tx[3];
+	__int32_t i,j,n,ix,hx;
+	int e0,nx;
+
+	hx = CYG_LIBM_WORD(x);
+	ix = hx&0x7fffffff;
+	if(ix<=0x3f490fd8)   /* |x| ~<= pi/4 , no need for reduction */
+	    {y[0] = x; y[1] = 0; return 0;}
+	if(ix<0x4016cbe4) {  /* |x| < 3pi/4, special case with n=+-1 */
+	    if(hx>0) {
+		z = x - pio2_1;
+		if((ix&0xfffffff0)!=0x3fc90fd0) { /* 24+24 bit pi OK */
+		    y[0] = z - pio2_1t;
+		    y[1] = (z-y[0])-pio2_1t;
+		} else {		/* near pi/2, use 24+24+24 bit pi */
+		    z -= pio2_2;
+		    y[0] = z - pio2_2t;
+		    y[1] = (z-y[0])-pio2_2t;
+		}
+		return 1;
+	    } else {	/* negative x */
+		z = x + pio2_1;
+		if((ix&0xfffffff0)!=0x3fc90fd0) { /* 24+24 bit pi OK */
+		    y[0] = z + pio2_1t;
+		    y[1] = (z-y[0])+pio2_1t;
+		} else {		/* near pi/2, use 24+24+24 bit pi */
+		    z += pio2_2;
+		    y[0] = z + pio2_2t;
+		    y[1] = (z-y[0])+pio2_2t;
+		}
+		return -1;
+	    }
+	}
+	if(ix<=0x43490f80) { /* |x| ~<= 2^7*(pi/2), medium size */
+	    t  = fabsf(x);
+	    n  = (__int32_t) (t*invpio2+half);
+	    fn = (float)n;
+	    r  = t-fn*pio2_1;
+	    w  = fn*pio2_1t;	/* 1st round good to 40 bit */
+	    if(n<32&&(ix&0xffffff00)!=npio2_hw[n-1]) {
+		y[0] = r-w;	/* quick check no cancellation */
+	    } else {
+	        __uint32_t high;
+	        j  = ix>>23;
+	        y[0] = r-w;
+		high = CYG_LIBM_WORD(y[0]);
+	        i = j-((high>>23)&0xff);
+	        if(i>8) {  /* 2nd iteration needed, good to 57 */
+		    t  = r;
+		    w  = fn*pio2_2;
+		    r  = t-w;
+		    w  = fn*pio2_2t-((t-r)-w);
+		    y[0] = r-w;
+		    high = CYG_LIBM_WORD(y[0]);
+		    i = j-((high>>23)&0xff);
+		    if(i>25)  {	/* 3rd iteration need, 74 bits acc */
+			t  = r;	/* will cover all possible cases */
+			w  = fn*pio2_3;
+			r  = t-w;
+			w  = fn*pio2_3t-((t-r)-w);
+			y[0] = r-w;
+		    }
+		}
+	    }
+	    y[1] = (r-y[0])-w;
+	    if(hx<0)	{y[0] = -y[0]; y[1] = -y[1]; return -n;}
+	    else	 return n;
+	}
+    /*
+     * all other (large) arguments
+     */
+	if(!FLT_UWORD_IS_FINITE(ix)) {
+	    y[0]=y[1]=x-x; return 0;
+	}
+    /* set z = scalbn(|x|,ilogb(x)-7) */
+	e0	= (int)((ix>>23)-134);	/* e0 = ilogb(z)-7; */
+	SET_FLOAT_WORD(z, ix - ((__int32_t)e0<<23));
+	for(i=0;i<2;i++) {
+		tx[i] = (float)((__int32_t)(z));
+		z     = (z-tx[i])*two8;
+	}
+	tx[2] = z;
+	nx = 3;
+	while(tx[nx-1]==zero) nx--;	/* skip zero term */
+	n  =  __kernel_rem_pio2f(tx,y,e0,nx,2,two_over_pi);
+	if(hx<0) {y[0] = -y[0]; y[1] = -y[1]; return -n;}
+	return n;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_rem_pio2.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_remainder.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_remainder.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_remainder.c
@@ -0,0 +1,135 @@
+//===========================================================================
+//
+//      ef_remainder.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_remainder.c -- float version of e_remainder.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float zero = 0.0;
+#else
+static float zero = 0.0;
+#endif
+
+
+#ifdef __STDC__
+	float __ieee754_remainderf(float x, float p)
+#else
+	float __ieee754_remainderf(x,p)
+	float x,p;
+#endif
+{
+	__int32_t hx,hp;
+	__uint32_t sx;
+	float p_half;
+
+	hx = CYG_LIBM_WORD(x);
+	hp = CYG_LIBM_WORD(p);
+	sx = hx&0x80000000;
+	hp &= 0x7fffffff;
+	hx &= 0x7fffffff;
+
+    /* purge off exception values */
+	if(FLT_UWORD_IS_ZERO(hp)||
+	   !FLT_UWORD_IS_FINITE(hx)||
+	   FLT_UWORD_IS_NAN(hp))
+	    return (x*p)/(x*p);
+
+
+	if (hp<=FLT_UWORD_HALF_MAX) x = __ieee754_fmodf(x,p+p); /* now x < 2p */
+	if ((hx-hp)==0) return zero*x;
+	x  = fabsf(x);
+	p  = fabsf(p);
+	if (hp<0x01000000) {
+	    if(x+x>p) {
+		x-=p;
+		if(x+x>=p) x -= p;
+	    }
+	} else {
+	    p_half = (float)0.5*p;
+	    if(x>p_half) {
+		x-=p;
+		if(x>=p_half) x -= p;
+	    }
+	}
+	hx = CYG_LIBM_WORD(x);
+	SET_FLOAT_WORD(x,hx^sx);
+	return x;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_remainder.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_scalb.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_scalb.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_scalb.c
@@ -0,0 +1,118 @@
+//===========================================================================
+//
+//      ef_scalb.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_scalb.c -- float version of e_scalb.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef CYGFUN_LIBM_SVID3_scalb
+#ifdef __STDC__
+    float __ieee754_scalbf(float x, float fn)
+#else
+    float __ieee754_scalbf(float x, int fn)
+#endif
+#else
+#ifdef __STDC__
+	float __ieee754_scalbf(float x, float fn)
+#else
+	float __ieee754_scalbf(x,fn)
+	float x, fn;
+#endif
+#endif
+{
+#ifdef CYGFUN_LIBM_SVID3_scalb
+	return scalbnf(x,fn);
+#else
+	if (isnan(x)||isnan(fn)) return x*fn;
+	if (!finitef(fn)) {
+	    if(fn>(float)0.0) return x*fn;
+	    else       return x/(-fn);
+	}
+	if (rintf(fn)!=fn) return (fn-fn)/(fn-fn);
+#if INT_MAX > 65000
+	if ( fn > (float)65000.0) return scalbnf(x, 65000);
+	if (-fn > (float)65000.0) return scalbnf(x,-65000);
+#else
+	if ( fn > (float)32000.0) return scalbnf(x, 32000);
+	if (-fn > (float)32000.0) return scalbnf(x,-32000);
+#endif
+	return scalbnf(x,(int)fn);
+#endif
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF e_scalb.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_sinh.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_sinh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_sinh.c
@@ -0,0 +1,130 @@
+//===========================================================================
+//
+//      ef_sinh.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_sinh.c -- float version of e_sinh.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float one = 1.0, shuge = 1.0e37;
+#else
+static float one = 1.0, shuge = 1.0e37;
+#endif
+
+#ifdef __STDC__
+	float __ieee754_sinhf(float x)
+#else
+	float __ieee754_sinhf(x)
+	float x;
+#endif
+{
+	float t,w,h;
+	__int32_t ix,jx;
+
+	jx = CYG_LIBM_WORD(x);
+	ix = jx&0x7fffffff;
+
+    /* x is INF or NaN */
+	if(!FLT_UWORD_IS_FINITE(ix)) return x+x;
+
+	h = 0.5;
+	if (jx<0) h = -h;
+    /* |x| in [0,22], return sign(x)*0.5*(E+E/(E+1))) */
+	if (ix < 0x41b00000) {		/* |x|<22 */
+	    if (ix<0x31800000)		/* |x|<2**-28 */
+		if(shuge+x>one) return x;/* sinh(tiny) = tiny with inexact */
+	    t = expm1f(fabsf(x));
+	    if(ix<0x3f800000) return h*((float)2.0*t-t*t/(t+one));
+	    return h*(t+t/(t+one));
+	}
+
+    /* |x| in [22, log(maxdouble)] return 0.5*exp(|x|) */
+	if (ix<=FLT_UWORD_LOG_MAX)  return h*__ieee754_expf(fabsf(x));
+
+    /* |x| in [log(maxdouble), overflowthresold] */
+	if (ix<=FLT_UWORD_LOG_2MAX) {
+	    w = __ieee754_expf((float)0.5*fabsf(x));
+	    t = h*w;
+	    return t*w;
+	}
+
+    /* |x| > overflowthresold, sinh(x) overflow */
+	return x*shuge;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_sinh.c
diff --git a/packages/language/c/libm/current/src/float/ieee754-core/ef_sqrt.c b/packages/language/c/libm/current/src/float/ieee754-core/ef_sqrt.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/ieee754-core/ef_sqrt.c
@@ -0,0 +1,148 @@
+//===========================================================================
+//
+//      ef_sqrt.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* ef_sqrtf.c -- float version of e_sqrt.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+static	const float	one	= 1.0, tiny=1.0e-30;
+
+float __ieee754_sqrtf(float x)
+{
+	float z;
+	cyg_uint32 r,hx;
+	cyg_int32 ix,s,q,m,t,i;
+
+	ix = CYG_LIBM_WORD(x);
+
+	hx = ix&0x7fffffff;
+
+    /* take care of Inf and NaN */
+	if(!FLT_UWORD_IS_FINITE(hx))
+	    return x*x+x;		/* sqrt(NaN)=NaN, sqrt(+inf)=+inf
+					   sqrt(-inf)=sNaN */
+    /* take care of zero and -ves */
+	if(FLT_UWORD_IS_ZERO(hx)) return x;/* sqrt(+-0) = +-0 */
+	if(ix<0) return (x-x)/(x-x);		/* sqrt(-ve) = sNaN */
+
+    /* normalize x */
+	m = (ix>>23);
+	if(FLT_UWORD_IS_SUBNORMAL(hx)) {		/* subnormal x */
+	    for(i=0;(ix&0x00800000L)==0;i++) ix<<=1;
+	    m -= i-1;
+	}
+	m -= 127;	/* unbias exponent */
+	ix = (ix&0x007fffffL)|0x00800000L;
+	if(m&1)	/* odd m, double x to make it even */
+	    ix += ix;
+	m >>= 1;	/* m = [m/2] */
+
+    /* generate sqrt(x) bit by bit */
+	ix += ix;
+	q = s = 0;		/* q = sqrt(x) */
+	r = 0x01000000L;		/* r = moving bit from right to left */
+
+	while(r!=0) {
+	    t = s+r;
+	    if(t<=ix) {
+		s    = t+r;
+		ix  -= t;
+		q   += r;
+	    }
+	    ix += ix;
+	    r>>=1;
+	}
+
+    /* use floating add to find out rounding direction */
+	if(ix!=0) {
+	    z = one-tiny; /* trigger inexact flag */
+	    if (z>=one) {
+	        z = one+tiny;
+		if (z>one)
+		    q += 2;
+		else
+		    q += (q&1);
+	    }
+	}
+	ix = (q>>1)+0x3f000000L;
+	ix += (m <<23);
+	SET_FLOAT_WORD(z,ix);
+	return z;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF ef_sqrt.c
diff --git a/packages/language/c/libm/current/src/float/internal/kf_cos.c b/packages/language/c/libm/current/src/float/internal/kf_cos.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/internal/kf_cos.c
@@ -0,0 +1,126 @@
+//===========================================================================
+//
+//      kf_cos.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* kf_cos.c -- float version of k_cos.c
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+one =  1.0000000000e+00, /* 0x3f800000 */
+C1  =  4.1666667908e-02, /* 0x3d2aaaab */
+C2  = -1.3888889225e-03, /* 0xbab60b61 */
+C3  =  2.4801587642e-05, /* 0x37d00d01 */
+C4  = -2.7557314297e-07, /* 0xb493f27c */
+C5  =  2.0875723372e-09, /* 0x310f74f6 */
+C6  = -1.1359647598e-11; /* 0xad47d74e */
+
+#ifdef __STDC__
+	float __kernel_cosf(float x, float y)
+#else
+	float __kernel_cosf(x, y)
+	float x,y;
+#endif
+{
+	float a,hz,z,r,qx;
+	__int32_t ix;
+	ix = CYG_LIBM_WORD(x);
+	ix &= 0x7fffffff;			/* ix = |x|'s high word*/
+	if(ix<0x32000000) {			/* if x < 2**27 */
+	    if(((int)x)==0) return one;		/* generate inexact */
+	}
+	z  = x*x;
+	r  = z*(C1+z*(C2+z*(C3+z*(C4+z*(C5+z*C6)))));
+	if(ix < 0x3e99999a)			/* if |x| < 0.3 */
+	    return one - ((float)0.5*z - (z*r - x*y));
+	else {
+	    if(ix > 0x3f480000) {		/* x > 0.78125 */
+		qx = (float)0.28125;
+	    } else {
+	        SET_FLOAT_WORD(qx,ix-0x01000000);	/* x/4 */
+	    }
+	    hz = (float)0.5*z-qx;
+	    a  = one-qx;
+	    return a - (hz - (z*r-x*y));
+	}
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF kf_cos.c
diff --git a/packages/language/c/libm/current/src/float/internal/kf_rem_pio2.c b/packages/language/c/libm/current/src/float/internal/kf_rem_pio2.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/internal/kf_rem_pio2.c
@@ -0,0 +1,275 @@
+//===========================================================================
+//
+//      kf_rem_pio2.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* kf_rem_pio2.c -- float version of k_rem_pio2.c
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+/* In the float version, the input parameter x contains 8 bit
+   integers, not 24 bit integers.  113 bit precision is not supported.  */
+
+#ifdef __STDC__
+static const int init_jk[] = {4,7,9}; /* initial value for jk */
+#else
+static int init_jk[] = {4,7,9};
+#endif
+
+#ifdef __STDC__
+static const float PIo2[] = {
+#else
+static float PIo2[] = {
+#endif
+  1.5703125000e+00, /* 0x3fc90000 */
+  4.5776367188e-04, /* 0x39f00000 */
+  2.5987625122e-05, /* 0x37da0000 */
+  7.5437128544e-08, /* 0x33a20000 */
+  6.0026650317e-11, /* 0x2e840000 */
+  7.3896444519e-13, /* 0x2b500000 */
+  5.3845816694e-15, /* 0x27c20000 */
+  5.6378512969e-18, /* 0x22d00000 */
+  8.3009228831e-20, /* 0x1fc40000 */
+  3.2756352257e-22, /* 0x1bc60000 */
+  6.3331015649e-25, /* 0x17440000 */
+};
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+zero   = 0.0,
+one    = 1.0,
+two8   =  2.5600000000e+02, /* 0x43800000 */
+twon8  =  3.9062500000e-03; /* 0x3b800000 */
+
+#ifdef __STDC__
+	int __kernel_rem_pio2f(float *x, float *y, int e0, int nx, int prec, const __int32_t *ipio2)
+#else
+	int __kernel_rem_pio2f(x,y,e0,nx,prec,ipio2)
+	float x[], y[]; int e0,nx,prec; __int32_t ipio2[];
+#endif
+{
+	__int32_t jz,jx,jv,jp,jk,carry,n,iq[20],i,j,k,m,q0,ih;
+	float z,fw,f[20],fq[20],q[20];
+
+    /* initialize jk*/
+	jk = init_jk[prec];
+	jp = jk;
+
+    /* determine jx,jv,q0, note that 3>q0 */
+	jx =  nx-1;
+	jv = (e0-3)/8; if(jv<0) jv=0;
+	q0 =  e0-8*(jv+1);
+
+    /* set up f[0] to f[jx+jk] where f[jx+jk] = ipio2[jv+jk] */
+	j = jv-jx; m = jx+jk;
+	for(i=0;i<=m;i++,j++) f[i] = (j<0)? zero : (float) ipio2[j];
+
+    /* compute q[0],q[1],...q[jk] */
+	for (i=0;i<=jk;i++) {
+	    for(j=0,fw=0.0;j<=jx;j++) fw += x[j]*f[jx+i-j]; q[i] = fw;
+	}
+
+	jz = jk;
+recompute:
+    /* distill q[] into iq[] reversingly */
+	for(i=0,j=jz,z=q[jz];j>0;i++,j--) {
+	    fw    =  (float)((__int32_t)(twon8* z));
+	    iq[i] =  (__int32_t)(z-two8*fw);
+	    z     =  q[j-1]+fw;
+	}
+
+    /* compute n */
+	z  =    scalbnf(z,(int)q0);	/* actual value of z */
+	z -= (float)8.0*floorf(z*(float)0.125);	/* trim off integer >= 8 */
+	n  = (__int32_t) z;
+	z -= (float)n;
+	ih = 0;
+	if(q0>0) {	/* need iq[jz-1] to determine n */
+	    i  = (iq[jz-1]>>(8-q0)); n += i;
+	    iq[jz-1] -= i<<(8-q0);
+	    ih = iq[jz-1]>>(7-q0);
+	}
+	else if(q0==0) ih = iq[jz-1]>>8;
+	else if(z>=(float)0.5) ih=2;
+
+	if(ih>0) {	/* q > 0.5 */
+	    n += 1; carry = 0;
+	    for(i=0;i<jz ;i++) {	/* compute 1-q */
+		j = iq[i];
+		if(carry==0) {
+		    if(j!=0) {
+			carry = 1; iq[i] = 0x100- j;
+		    }
+		} else  iq[i] = 0xff - j;
+	    }
+	    if(q0>0) {		/* rare case: chance is 1 in 12 */
+	        switch(q0) {
+	        case 1:
+		   iq[jz-1] &= 0x7f; break;
+		case 2:
+		   iq[jz-1] &= 0x3f; break;
+	        }
+	    }
+	    if(ih==2) {
+		z = one - z;
+		if(carry!=0) z -= scalbnf(one,(int)q0);
+	    }
+	}
+
+    /* check if recomputation is needed */
+	if(z==zero) {
+	    j = 0;
+	    for (i=jz-1;i>=jk;i--) j |= iq[i];
+	    if(j==0) { /* need recomputation */
+		for(k=1;iq[jk-k]==0;k++);   /* k = no. of terms needed */
+
+		for(i=jz+1;i<=jz+k;i++) {   /* add q[jz+1] to q[jz+k] */
+		    f[jx+i] = (float) ipio2[jv+i];
+		    for(j=0,fw=0.0;j<=jx;j++) fw += x[j]*f[jx+i-j];
+		    q[i] = fw;
+		}
+		jz += k;
+		goto recompute;
+	    }
+	}
+
+    /* chop off zero terms */
+	if(z==(float)0.0) {
+	    jz -= 1; q0 -= 8;
+	    while(iq[jz]==0) { jz--; q0-=8;}
+	} else { /* break z into 8-bit if necessary */
+	    z = scalbnf(z,-(int)q0);
+	    if(z>=two8) {
+		fw = (float)((__int32_t)(twon8*z));
+		iq[jz] = (__int32_t)(z-two8*fw);
+		jz += 1; q0 += 8;
+		iq[jz] = (__int32_t) fw;
+	    } else iq[jz] = (__int32_t) z ;
+	}
+
+    /* convert integer "bit" chunk to floating-point value */
+	fw = scalbnf(one,(int)q0);
+	for(i=jz;i>=0;i--) {
+	    q[i] = fw*(float)iq[i]; fw*=twon8;
+	}
+
+    /* compute PIo2[0,...,jp]*q[jz,...,0] */
+	for(i=jz;i>=0;i--) {
+	    for(fw=0.0,k=0;k<=jp&&k<=jz-i;k++) fw += PIo2[k]*q[i+k];
+	    fq[jz-i] = fw;
+	}
+
+    /* compress fq[] into y[] */
+	switch(prec) {
+	    case 0:
+		fw = 0.0;
+		for (i=jz;i>=0;i--) fw += fq[i];
+		y[0] = (ih==0)? fw: -fw;
+		break;
+	    case 1:
+	    case 2:
+		fw = 0.0;
+		for (i=jz;i>=0;i--) fw += fq[i];
+		y[0] = (ih==0)? fw: -fw;
+		fw = fq[0]-fw;
+		for (i=1;i<=jz;i++) fw += fq[i];
+		y[1] = (ih==0)? fw: -fw;
+		break;
+	    case 3:	/* painful */
+		for (i=jz;i>0;i--) {
+		    fw      = fq[i-1]+fq[i];
+		    fq[i]  += fq[i-1]-fw;
+		    fq[i-1] = fw;
+		}
+		for (i=jz;i>1;i--) {
+		    fw      = fq[i-1]+fq[i];
+		    fq[i]  += fq[i-1]-fw;
+		    fq[i-1] = fw;
+		}
+		for (fw=0.0,i=jz;i>=2;i--) fw += fq[i];
+		if(ih==0) {
+		    y[0] =  fq[0]; y[1] =  fq[1]; y[2] =  fw;
+		} else {
+		    y[0] = -fq[0]; y[1] = -fq[1]; y[2] = -fw;
+		}
+	}
+	return n&7;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF kf_rem_pio2.c
diff --git a/packages/language/c/libm/current/src/float/internal/kf_sin.c b/packages/language/c/libm/current/src/float/internal/kf_sin.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/internal/kf_sin.c
@@ -0,0 +1,116 @@
+//===========================================================================
+//
+//      kf_sin.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* kf_sin.c -- float version of k_sin.c
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+half =  5.0000000000e-01,/* 0x3f000000 */
+S1  = -1.6666667163e-01, /* 0xbe2aaaab */
+S2  =  8.3333337680e-03, /* 0x3c088889 */
+S3  = -1.9841270114e-04, /* 0xb9500d01 */
+S4  =  2.7557314297e-06, /* 0x3638ef1b */
+S5  = -2.5050759689e-08, /* 0xb2d72f34 */
+S6  =  1.5896910177e-10; /* 0x2f2ec9d3 */
+
+#ifdef __STDC__
+	float __kernel_sinf(float x, float y, int iy)
+#else
+	float __kernel_sinf(x, y, iy)
+	float x,y; int iy;		/* iy=0 if y is zero */
+#endif
+{
+	float z,r,v;
+	__int32_t ix;
+	ix = CYG_LIBM_WORD(x);
+	ix &= 0x7fffffff;			/* high word of x */
+	if(ix<0x32000000)			/* |x| < 2**-27 */
+	   {if((int)x==0) return x;}		/* generate inexact */
+	z	=  x*x;
+	v	=  z*x;
+	r	=  S2+z*(S3+z*(S4+z*(S5+z*S6)));
+	if(iy==0) return x+v*(S1+z*r);
+	else      return x-((z*(half*y-v*r)-y)-v*S1);
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF kf_sin.c
diff --git a/packages/language/c/libm/current/src/float/internal/kf_tan.c b/packages/language/c/libm/current/src/float/internal/kf_tan.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/internal/kf_tan.c
@@ -0,0 +1,163 @@
+//===========================================================================
+//
+//      kf_tan.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* kf_tan.c -- float version of k_tan.c
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+one   =  1.0000000000e+00, /* 0x3f800000 */
+pio4  =  7.8539812565e-01, /* 0x3f490fda */
+pio4lo=  3.7748947079e-08, /* 0x33222168 */
+T[] =  {
+  3.3333334327e-01, /* 0x3eaaaaab */
+  1.3333334029e-01, /* 0x3e088889 */
+  5.3968254477e-02, /* 0x3d5d0dd1 */
+  2.1869488060e-02, /* 0x3cb327a4 */
+  8.8632395491e-03, /* 0x3c11371f */
+  3.5920790397e-03, /* 0x3b6b6916 */
+  1.4562094584e-03, /* 0x3abede48 */
+  5.8804126456e-04, /* 0x3a1a26c8 */
+  2.4646313977e-04, /* 0x398137b9 */
+  7.8179444245e-05, /* 0x38a3f445 */
+  7.1407252108e-05, /* 0x3895c07a */
+ -1.8558637748e-05, /* 0xb79bae5f */
+  2.5907305826e-05, /* 0x37d95384 */
+};
+
+#ifdef __STDC__
+	float __kernel_tanf(float x, float y, int iy)
+#else
+	float __kernel_tanf(x, y, iy)
+	float x,y; int iy;
+#endif
+{
+	float z,r,v,w,s;
+	__int32_t ix,hx;
+	hx = CYG_LIBM_WORD(x);
+	ix = hx&0x7fffffff;	/* high word of |x| */
+	if(ix<0x31800000)			/* x < 2**-28 */
+	    {if((int)x==0) {			/* generate inexact */
+		if((ix|(iy+1))==0) return one/fabsf(x);
+		else return (iy==1)? x: -one/x;
+	    }
+	    }
+	if(ix>=0x3f2ca140) {			/* |x|>=0.6744 */
+	    if(hx<0) {x = -x; y = -y;}
+	    z = pio4-x;
+	    w = pio4lo-y;
+	    x = z+w; y = 0.0;
+	}
+	z	=  x*x;
+	w	=  z*z;
+    /* Break x^5*(T[1]+x^2*T[2]+...) into
+     *	  x^5(T[1]+x^4*T[3]+...+x^20*T[11]) +
+     *	  x^5(x^2*(T[2]+x^4*T[4]+...+x^22*[T12]))
+     */
+	r = T[1]+w*(T[3]+w*(T[5]+w*(T[7]+w*(T[9]+w*T[11]))));
+	v = z*(T[2]+w*(T[4]+w*(T[6]+w*(T[8]+w*(T[10]+w*T[12])))));
+	s = z*x;
+	r = y + z*(s*(r+v)+y);
+	r += T[0]*s;
+	w = x+r;
+	if(ix>=0x3f2ca140) {
+	    v = (float)iy;
+	    return (float)(1-((hx>>30)&2))*(v-(float)2.0*(x-(w*w/(w+v)-r)));
+	}
+	if(iy==1) return w;
+	else {		/* if allow error up to 2 ulp,
+			   simply return -1.0/(x+r) here */
+     /*  compute -1.0/(x+r) accurately */
+	    float a,t;
+	    __int32_t i;
+	    z  = w;
+	    i = CYG_LIBM_WORD(z);
+	    SET_FLOAT_WORD(z,i&0xfffff000);
+	    v  = r-(z - x);	/* z+v = r+x */
+	    t = a  = -(float)1.0/w;	/* a = -1.0/w */
+	    i = CYG_LIBM_WORD(t);
+	    SET_FLOAT_WORD(t,i&0xfffff000);
+	    s  = (float)1.0+t*z;
+	    return t+a*(s+t*v);
+	}
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF kf_tan.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_asinh.c b/packages/language/c/libm/current/src/float/portable-api/sf_asinh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_asinh.c
@@ -0,0 +1,118 @@
+//===========================================================================
+//
+//      sf_asinh.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_asinh.c -- float version of s_asinh.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+one =  1.0000000000e+00, /* 0x3F800000 */
+ln2 =  6.9314718246e-01, /* 0x3f317218 */
+huge=  1.0000000000e+30;
+
+#ifdef __STDC__
+	float asinhf(float x)
+#else
+	float asinhf(x)
+	float x;
+#endif
+{
+	float t,w;
+	__int32_t hx,ix;
+	hx = CYG_LIBM_WORD(x);
+	ix = hx&0x7fffffff;
+	if(!FLT_UWORD_IS_FINITE(ix)) return x+x;	/* x is inf or NaN */
+	if(ix< 0x31800000) {	/* |x|<2**-28 */
+	    if(huge+x>one) return x;	/* return x inexact except 0 */
+	}
+	if(ix>0x4d800000) {	/* |x| > 2**28 */
+	    w = __ieee754_logf(fabsf(x))+ln2;
+	} else if (ix>0x40000000) {	/* 2**28 > |x| > 2.0 */
+	    t = fabsf(x);
+	    w = __ieee754_logf((float)2.0*t+one/(__ieee754_sqrtf(x*x+one)+t));
+	} else {		/* 2.0 > |x| > 2**-28 */
+	    t = x*x;
+	    w =log1pf(fabsf(x)+t/(one+__ieee754_sqrtf(one+t)));
+	}
+	if(hx>0) return w; else return -w;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_asinh.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_atan.c b/packages/language/c/libm/current/src/float/portable-api/sf_atan.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_atan.c
@@ -0,0 +1,183 @@
+//===========================================================================
+//
+//      sf_atan.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_atan.c -- float version of s_atan.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float atanhi[] = {
+#else
+static float atanhi[] = {
+#endif
+  4.6364760399e-01, /* atan(0.5)hi 0x3eed6338 */
+  7.8539812565e-01, /* atan(1.0)hi 0x3f490fda */
+  9.8279368877e-01, /* atan(1.5)hi 0x3f7b985e */
+  1.5707962513e+00, /* atan(inf)hi 0x3fc90fda */
+};
+
+#ifdef __STDC__
+static const float atanlo[] = {
+#else
+static float atanlo[] = {
+#endif
+  5.0121582440e-09, /* atan(0.5)lo 0x31ac3769 */
+  3.7748947079e-08, /* atan(1.0)lo 0x33222168 */
+  3.4473217170e-08, /* atan(1.5)lo 0x33140fb4 */
+  7.5497894159e-08, /* atan(inf)lo 0x33a22168 */
+};
+
+#ifdef __STDC__
+static const float aT[] = {
+#else
+static float aT[] = {
+#endif
+  3.3333334327e-01, /* 0x3eaaaaaa */
+ -2.0000000298e-01, /* 0xbe4ccccd */
+  1.4285714924e-01, /* 0x3e124925 */
+ -1.1111110449e-01, /* 0xbde38e38 */
+  9.0908870101e-02, /* 0x3dba2e6e */
+ -7.6918758452e-02, /* 0xbd9d8795 */
+  6.6610731184e-02, /* 0x3d886b35 */
+ -5.8335702866e-02, /* 0xbd6ef16b */
+  4.9768779427e-02, /* 0x3d4bda59 */
+ -3.6531571299e-02, /* 0xbd15a221 */
+  1.6285819933e-02, /* 0x3c8569d7 */
+};
+
+#ifdef __STDC__
+	static const float
+#else
+	static float
+#endif
+one   = 1.0,
+huge   = 1.0e30;
+
+#ifdef __STDC__
+	float atanf(float x)
+#else
+	float atanf(x)
+	float x;
+#endif
+{
+	float w,s1,s2,z;
+	__int32_t ix,hx,id;
+
+	hx = CYG_LIBM_WORD(x);
+	ix = hx&0x7fffffff;
+	if(ix>=0x50800000) {	/* if |x| >= 2^34 */
+	    if(FLT_UWORD_IS_NAN(ix))
+		return x+x;		/* NaN */
+	    if(hx>0) return  atanhi[3]+atanlo[3];
+	    else     return -atanhi[3]-atanlo[3];
+	} if (ix < 0x3ee00000) {	/* |x| < 0.4375 */
+	    if (ix < 0x31000000) {	/* |x| < 2^-29 */
+		if(huge+x>one) return x;	/* raise inexact */
+	    }
+	    id = -1;
+	} else {
+	x = fabsf(x);
+	if (ix < 0x3f980000) {		/* |x| < 1.1875 */
+	    if (ix < 0x3f300000) {	/* 7/16 <=|x|<11/16 */
+		id = 0; x = ((float)2.0*x-one)/((float)2.0+x);
+	    } else {			/* 11/16<=|x|< 19/16 */
+		id = 1; x  = (x-one)/(x+one);
+	    }
+	} else {
+	    if (ix < 0x401c0000) {	/* |x| < 2.4375 */
+		id = 2; x  = (x-(float)1.5)/(one+(float)1.5*x);
+	    } else {			/* 2.4375 <= |x| < 2^66 */
+		id = 3; x  = -(float)1.0/x;
+	    }
+	}}
+    /* end of argument reduction */
+	z = x*x;
+	w = z*z;
+    /* break sum from i=0 to 10 aT[i]z**(i+1) into odd and even poly */
+	s1 = z*(aT[0]+w*(aT[2]+w*(aT[4]+w*(aT[6]+w*(aT[8]+w*aT[10])))));
+	s2 = w*(aT[1]+w*(aT[3]+w*(aT[5]+w*(aT[7]+w*aT[9]))));
+	if (id<0) return x - x*(s1+s2);
+	else {
+	    z = atanhi[id] - ((x*(s1+s2) - atanlo[id]) - x);
+	    return (hx<0)? -z:z;
+	}
+}
+
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_atan.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_cbrt.c b/packages/language/c/libm/current/src/float/portable-api/sf_cbrt.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_cbrt.c
@@ -0,0 +1,147 @@
+//===========================================================================
+//
+//      sf_cbrt.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_cbrt.c -- float version of s_cbrt.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+/* cbrtf(x)
+ * Return cube root of x
+ */
+#ifdef __STDC__
+static const __uint32_t
+#else
+static __uint32_t
+#endif
+	B1 = 709958130, /* B1 = (84+2/3-0.03306235651)*2**23 */
+	B2 = 642849266; /* B2 = (76+2/3-0.03306235651)*2**23 */
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+C =  5.4285717010e-01, /* 19/35     = 0x3f0af8b0 */
+D = -7.0530611277e-01, /* -864/1225 = 0xbf348ef1 */
+E =  1.4142856598e+00, /* 99/70     = 0x3fb50750 */
+F =  1.6071428061e+00, /* 45/28     = 0x3fcdb6db */
+G =  3.5714286566e-01; /* 5/14      = 0x3eb6db6e */
+
+#ifdef __STDC__
+	float cbrtf(float x)
+#else
+	float cbrtf(x)
+	float x;
+#endif
+{
+	__int32_t	hx;
+	float r,s,t;
+	__uint32_t sign;
+	__uint32_t high;
+
+	hx = CYG_LIBM_WORD(x);
+	sign=hx&0x80000000;		/* sign= sign(x) */
+	hx  ^=sign;
+	if(!FLT_UWORD_IS_FINITE(hx))
+	    return(x+x);		/* cbrt(NaN,INF) is itself */
+	if(FLT_UWORD_IS_ZERO(hx))
+	    return(x);			/* cbrt(0) is itself */
+
+	SET_FLOAT_WORD(x,hx);	/* x <- |x| */
+    /* rough cbrt to 5 bits */
+	if(FLT_UWORD_IS_SUBNORMAL(hx))		/* subnormal number */
+	  {SET_FLOAT_WORD(t,0x4b800000); /* set t= 2**24 */
+	   t*=x; high = CYG_LIBM_WORD(t); SET_FLOAT_WORD(t,high/3+B2);
+	  }
+	else
+	  SET_FLOAT_WORD(t,hx/3+B1);
+
+
+    /* new cbrt to 23 bits */
+	r=t*t/x;
+	s=C+r*t;
+	t*=G+F/(s+E+D/s);
+
+    /* retore the sign bit */
+	high = CYG_LIBM_WORD(t);
+	SET_FLOAT_WORD(t,high|sign);
+	return(t);
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_cbrt.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_ceil.c b/packages/language/c/libm/current/src/float/portable-api/sf_ceil.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_ceil.c
@@ -0,0 +1,124 @@
+//===========================================================================
+//
+//      sf_ceil.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_ceil.c -- float version of s_ceil.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float huge = 1.0e30;
+#else
+static float huge = 1.0e30;
+#endif
+
+#ifdef __STDC__
+	float ceilf(float x)
+#else
+	float ceilf(x)
+	float x;
+#endif
+{
+	__int32_t i0,j0;
+	__uint32_t i,ix;
+	i0 = CYG_LIBM_WORD(x);
+	ix = (i0&0x7fffffff);
+	j0 = (ix>>23)-0x7f;
+	if(j0<23) {
+	    if(j0<0) {	/* raise inexact if x != 0 */
+		if(huge+x>(float)0.0) {/* return 0*sign(x) if |x|<1 */
+		    if(i0<0) {i0=0x80000000;}
+		    else if(!FLT_UWORD_IS_ZERO(ix)) { i0=0x3f800000;}
+		}
+	    } else {
+		i = (0x007fffff)>>j0;
+		if((i0&i)==0) return x; /* x is integral */
+		if(huge+x>(float)0.0) {	/* raise inexact flag */
+		    if(i0>0) i0 += (0x00800000)>>j0;
+		    i0 &= (~i);
+		}
+	    }
+	} else {
+	    if(!FLT_UWORD_IS_FINITE(ix)) return x+x; /* inf or NaN */
+	    else return x;		/* x is integral */
+	}
+	SET_FLOAT_WORD(x,i0);
+	return x;
+}
+
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_ceil.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_copysign.c b/packages/language/c/libm/current/src/float/portable-api/sf_copysign.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_copysign.c
@@ -0,0 +1,103 @@
+//===========================================================================
+//
+//      sf_copysign.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_copysign.c -- float version of s_copysign.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * copysignf(float x, float y)
+ * copysignf(x,y) returns a value with the magnitude of x and
+ * with the sign bit of y.
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float copysignf(float x, float y)
+#else
+	float copysignf(x,y)
+	float x,y;
+#endif
+{
+	__uint32_t ix,iy;
+	ix = CYG_LIBM_WORD(x);
+	iy = CYG_LIBM_WORD(y);
+	SET_FLOAT_WORD(x,(ix&0x7fffffff)|(iy&0x80000000));
+        return x;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_copysign.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_cos.c b/packages/language/c/libm/current/src/float/portable-api/sf_cos.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_cos.c
@@ -0,0 +1,120 @@
+//===========================================================================
+//
+//      sf_cos.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+/* sf_cos.c -- float version of s_cos.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float one=1.0;
+#else
+static float one=1.0;
+#endif
+
+#ifdef __STDC__
+	float cosf(float x)
+#else
+	float cosf(x)
+	float x;
+#endif
+{
+	float y[2],z=0.0;
+	__int32_t n,ix;
+
+	ix = CYG_LIBM_WORD(x);
+
+    /* |x| ~< pi/4 */
+	ix &= 0x7fffffff;
+	if(ix <= 0x3f490fd8) return __kernel_cosf(x,z);
+
+    /* cos(Inf or NaN) is NaN */
+	else if (!FLT_UWORD_IS_FINITE(ix)) return x-x;
+
+    /* argument reduction needed */
+	else {
+	    n = __ieee754_rem_pio2f(x,y);
+	    switch(n&3) {
+		case 0: return  __kernel_cosf(y[0],y[1]);
+		case 1: return -__kernel_sinf(y[0],y[1],1);
+		case 2: return -__kernel_cosf(y[0],y[1]);
+		default:
+		        return  __kernel_sinf(y[0],y[1],1);
+	    }
+	}
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_cos.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_erf.c b/packages/language/c/libm/current/src/float/portable-api/sf_erf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_erf.c
@@ -0,0 +1,285 @@
+//===========================================================================
+//
+//      sf_erf.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_erf.c -- float version of s_erf.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+tiny	    = 1e-30,
+half=  5.0000000000e-01, /* 0x3F000000 */
+one =  1.0000000000e+00, /* 0x3F800000 */
+two =  2.0000000000e+00, /* 0x40000000 */
+	/* c = (subfloat)0.84506291151 */
+erx =  8.4506291151e-01, /* 0x3f58560b */
+/*
+ * Coefficients for approximation to  erf on [0,0.84375]
+ */
+efx =  1.2837916613e-01, /* 0x3e0375d4 */
+efx8=  1.0270333290e+00, /* 0x3f8375d4 */
+pp0  =  1.2837916613e-01, /* 0x3e0375d4 */
+pp1  = -3.2504209876e-01, /* 0xbea66beb */
+pp2  = -2.8481749818e-02, /* 0xbce9528f */
+pp3  = -5.7702702470e-03, /* 0xbbbd1489 */
+pp4  = -2.3763017452e-05, /* 0xb7c756b1 */
+qq1  =  3.9791721106e-01, /* 0x3ecbbbce */
+qq2  =  6.5022252500e-02, /* 0x3d852a63 */
+qq3  =  5.0813062117e-03, /* 0x3ba68116 */
+qq4  =  1.3249473704e-04, /* 0x390aee49 */
+qq5  = -3.9602282413e-06, /* 0xb684e21a */
+/*
+ * Coefficients for approximation to  erf  in [0.84375,1.25]
+ */
+pa0  = -2.3621185683e-03, /* 0xbb1acdc6 */
+pa1  =  4.1485610604e-01, /* 0x3ed46805 */
+pa2  = -3.7220788002e-01, /* 0xbebe9208 */
+pa3  =  3.1834661961e-01, /* 0x3ea2fe54 */
+pa4  = -1.1089469492e-01, /* 0xbde31cc2 */
+pa5  =  3.5478305072e-02, /* 0x3d1151b3 */
+pa6  = -2.1663755178e-03, /* 0xbb0df9c0 */
+qa1  =  1.0642088205e-01, /* 0x3dd9f331 */
+qa2  =  5.4039794207e-01, /* 0x3f0a5785 */
+qa3  =  7.1828655899e-02, /* 0x3d931ae7 */
+qa4  =  1.2617121637e-01, /* 0x3e013307 */
+qa5  =  1.3637083583e-02, /* 0x3c5f6e13 */
+qa6  =  1.1984500103e-02, /* 0x3c445aa3 */
+/*
+ * Coefficients for approximation to  erfc in [1.25,1/0.35]
+ */
+ra0  = -9.8649440333e-03, /* 0xbc21a093 */
+ra1  = -6.9385856390e-01, /* 0xbf31a0b7 */
+ra2  = -1.0558626175e+01, /* 0xc128f022 */
+ra3  = -6.2375331879e+01, /* 0xc2798057 */
+ra4  = -1.6239666748e+02, /* 0xc322658c */
+ra5  = -1.8460508728e+02, /* 0xc3389ae7 */
+ra6  = -8.1287437439e+01, /* 0xc2a2932b */
+ra7  = -9.8143291473e+00, /* 0xc11d077e */
+sa1  =  1.9651271820e+01, /* 0x419d35ce */
+sa2  =  1.3765776062e+02, /* 0x4309a863 */
+sa3  =  4.3456588745e+02, /* 0x43d9486f */
+sa4  =  6.4538726807e+02, /* 0x442158c9 */
+sa5  =  4.2900814819e+02, /* 0x43d6810b */
+sa6  =  1.0863500214e+02, /* 0x42d9451f */
+sa7  =  6.5702495575e+00, /* 0x40d23f7c */
+sa8  = -6.0424413532e-02, /* 0xbd777f97 */
+/*
+ * Coefficients for approximation to  erfc in [1/.35,28]
+ */
+rb0  = -9.8649431020e-03, /* 0xbc21a092 */
+rb1  = -7.9928326607e-01, /* 0xbf4c9dd4 */
+rb2  = -1.7757955551e+01, /* 0xc18e104b */
+rb3  = -1.6063638306e+02, /* 0xc320a2ea */
+rb4  = -6.3756646729e+02, /* 0xc41f6441 */
+rb5  = -1.0250950928e+03, /* 0xc480230b */
+rb6  = -4.8351919556e+02, /* 0xc3f1c275 */
+sb1  =  3.0338060379e+01, /* 0x41f2b459 */
+sb2  =  3.2579251099e+02, /* 0x43a2e571 */
+sb3  =  1.5367296143e+03, /* 0x44c01759 */
+sb4  =  3.1998581543e+03, /* 0x4547fdbb */
+sb5  =  2.5530502930e+03, /* 0x451f90ce */
+sb6  =  4.7452853394e+02, /* 0x43ed43a7 */
+sb7  = -2.2440952301e+01; /* 0xc1b38712 */
+
+#ifdef __STDC__
+	float erff(float x)
+#else
+	float erff(x)
+	float x;
+#endif
+{
+	__int32_t hx,ix,i;
+	float R,S,P,Q,s,y,z,r;
+	hx = CYG_LIBM_WORD(x);
+	ix = hx&0x7fffffff;
+	if(!FLT_UWORD_IS_FINITE(ix)) {		/* erf(nan)=nan */
+	    i = ((__uint32_t)hx>>31)<<1;
+	    return (float)(1-i)+one/x;	/* erf(+-inf)=+-1 */
+	}
+
+	if(ix < 0x3f580000) {		/* |x|<0.84375 */
+	    if(ix < 0x31800000) {	/* |x|<2**-28 */
+	        if (ix < 0x04000000)
+		    /*avoid underflow */
+		    return (float)0.125*((float)8.0*x+efx8*x);
+		return x + efx*x;
+	    }
+	    z = x*x;
+	    r = pp0+z*(pp1+z*(pp2+z*(pp3+z*pp4)));
+	    s = one+z*(qq1+z*(qq2+z*(qq3+z*(qq4+z*qq5))));
+	    y = r/s;
+	    return x + x*y;
+	}
+	if(ix < 0x3fa00000) {		/* 0.84375 <= |x| < 1.25 */
+	    s = fabsf(x)-one;
+	    P = pa0+s*(pa1+s*(pa2+s*(pa3+s*(pa4+s*(pa5+s*pa6)))));
+	    Q = one+s*(qa1+s*(qa2+s*(qa3+s*(qa4+s*(qa5+s*qa6)))));
+	    if(hx>=0) return erx + P/Q; else return -erx - P/Q;
+	}
+	if (ix >= 0x40c00000) {		/* inf>|x|>=6 */
+	    if(hx>=0) return one-tiny; else return tiny-one;
+	}
+	x = fabsf(x);
+	s = one/(x*x);
+	if(ix< 0x4036DB6E) {	/* |x| < 1/0.35 */
+	    R=ra0+s*(ra1+s*(ra2+s*(ra3+s*(ra4+s*(
+				ra5+s*(ra6+s*ra7))))));
+	    S=one+s*(sa1+s*(sa2+s*(sa3+s*(sa4+s*(
+				sa5+s*(sa6+s*(sa7+s*sa8)))))));
+	} else {	/* |x| >= 1/0.35 */
+	    R=rb0+s*(rb1+s*(rb2+s*(rb3+s*(rb4+s*(
+				rb5+s*rb6)))));
+	    S=one+s*(sb1+s*(sb2+s*(sb3+s*(sb4+s*(
+				sb5+s*(sb6+s*sb7))))));
+	}
+	ix = CYG_LIBM_WORD(x);
+	SET_FLOAT_WORD(z,ix&0xfffff000);
+	r  =  __ieee754_expf(-z*z-(float)0.5625)*__ieee754_expf((z-x)*(z+x)+R/S);
+	if(hx>=0) return one-r/x; else return  r/x-one;
+}
+
+#ifdef __STDC__
+	float erfcf(float x)
+#else
+	float erfcf(x)
+	float x;
+#endif
+{
+	__int32_t hx,ix;
+	float R,S,P,Q,s,y,z,r;
+	hx = CYG_LIBM_WORD(x);
+	ix = hx&0x7fffffff;
+	if(!FLT_UWORD_IS_FINITE(ix)) {			/* erfc(nan)=nan */
+						/* erfc(+-inf)=0,2 */
+	    return (float)(((__uint32_t)hx>>31)<<1)+one/x;
+	}
+
+	if(ix < 0x3f580000) {		/* |x|<0.84375 */
+	    if(ix < 0x23800000)	/* |x|<2**-56 */
+		return one-x;
+	    z = x*x;
+	    r = pp0+z*(pp1+z*(pp2+z*(pp3+z*pp4)));
+	    s = one+z*(qq1+z*(qq2+z*(qq3+z*(qq4+z*qq5))));
+	    y = r/s;
+	    if(hx < 0x3e800000) {	/* x<1/4 */
+		return one-(x+x*y);
+	    } else {
+		r = x*y;
+		r += (x-half);
+	        return half - r ;
+	    }
+	}
+	if(ix < 0x3fa00000) {		/* 0.84375 <= |x| < 1.25 */
+	    s = fabsf(x)-one;
+	    P = pa0+s*(pa1+s*(pa2+s*(pa3+s*(pa4+s*(pa5+s*pa6)))));
+	    Q = one+s*(qa1+s*(qa2+s*(qa3+s*(qa4+s*(qa5+s*qa6)))));
+	    if(hx>=0) {
+	        z  = one-erx; return z - P/Q;
+	    } else {
+		z = erx+P/Q; return one+z;
+	    }
+	}
+	if (ix < 0x41e00000) {		/* |x|<28 */
+	    x = fabsf(x);
+	    s = one/(x*x);
+	    if(ix< 0x4036DB6D) {	/* |x| < 1/.35 ~ 2.857143*/
+	        R=ra0+s*(ra1+s*(ra2+s*(ra3+s*(ra4+s*(
+				ra5+s*(ra6+s*ra7))))));
+	        S=one+s*(sa1+s*(sa2+s*(sa3+s*(sa4+s*(
+				sa5+s*(sa6+s*(sa7+s*sa8)))))));
+	    } else {			/* |x| >= 1/.35 ~ 2.857143 */
+		if(hx<0&&ix>=0x40c00000) return two-tiny;/* x < -6 */
+	        R=rb0+s*(rb1+s*(rb2+s*(rb3+s*(rb4+s*(
+				rb5+s*rb6)))));
+	        S=one+s*(sb1+s*(sb2+s*(sb3+s*(sb4+s*(
+				sb5+s*(sb6+s*sb7))))));
+	    }
+	    ix = CYG_LIBM_WORD(x);
+	    SET_FLOAT_WORD(z,ix&0xfffff000);
+	    r  =  __ieee754_expf(-z*z-(float)0.5625)*
+			__ieee754_expf((z-x)*(z+x)+R/S);
+	    if(hx>0) return r/x; else return two-r/x;
+	} else {
+	    if(hx>0) return tiny*tiny; else return two-tiny;
+	}
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_erf.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_expm1.c b/packages/language/c/libm/current/src/float/portable-api/sf_expm1.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_expm1.c
@@ -0,0 +1,186 @@
+//===========================================================================
+//
+//      s_expm1.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour
+// Contributors:
+// Date:         2001-07-20
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+/* sf_expm1.c -- float version of s_expm1.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+one		= 1.0,
+huge		= 1.0e+30,
+tiny		= 1.0e-30,
+ln2_hi		= 6.9313812256e-01,/* 0x3f317180 */
+ln2_lo		= 9.0580006145e-06,/* 0x3717f7d1 */
+invln2		= 1.4426950216e+00,/* 0x3fb8aa3b */
+	/* scaled coefficients related to expm1 */
+Q1  =  -3.3333335072e-02, /* 0xbd088889 */
+Q2  =   1.5873016091e-03, /* 0x3ad00d01 */
+Q3  =  -7.9365076090e-05, /* 0xb8a670cd */
+Q4  =   4.0082177293e-06, /* 0x36867e54 */
+Q5  =  -2.0109921195e-07; /* 0xb457edbb */
+
+#ifdef __STDC__
+	float expm1f(float x)
+#else
+	float expm1f(x)
+	float x;
+#endif
+{
+	float y,hi,lo,c,t,e,hxs,hfx,r1;
+	__int32_t k,xsb;
+	__uint32_t hx;
+
+	hx = CYG_LIBM_WORD(x);
+	xsb = hx&0x80000000;		/* sign bit of x */
+	if(xsb==0) y=x; else y= -x;	/* y = |x| */
+	hx &= 0x7fffffff;		/* high word of |x| */
+
+    /* filter out huge and non-finite argument */
+	if(hx >= 0x4195b844) {			/* if |x|>=27*ln2 */
+	    if(FLT_UWORD_IS_NAN(hx))
+	        return x+x;
+	    if(FLT_UWORD_IS_INFINITE(hx))
+		return (xsb==0)? x:-1.0;/* exp(+-inf)={inf,-1} */
+	    if(xsb == 0 && hx > FLT_UWORD_LOG_MAX) /* if x>=o_threshold */
+		return huge*huge; /* overflow */
+	    if(xsb!=0) { /* x < -27*ln2, return -1.0 with inexact */
+		if(x+tiny<(float)0.0)	/* raise inexact */
+		return tiny-one;	/* return -1 */
+	    }
+	}
+
+    /* argument reduction */
+	if(hx > 0x3eb17218) {		/* if  |x| > 0.5 ln2 */
+	    if(hx < 0x3F851592) {	/* and |x| < 1.5 ln2 */
+		if(xsb==0)
+		    {hi = x - ln2_hi; lo =  ln2_lo;  k =  1;}
+		else
+		    {hi = x + ln2_hi; lo = -ln2_lo;  k = -1;}
+	    } else {
+		k  = invln2*x+((xsb==0)?(float)0.5:(float)-0.5);
+		t  = k;
+		hi = x - t*ln2_hi;	/* t*ln2_hi is exact here */
+		lo = t*ln2_lo;
+	    }
+	    x  = hi - lo;
+	    c  = (hi-x)-lo;
+	}
+	else if(hx < 0x33000000) {	/* when |x|<2**-25, return x */
+	    t = huge+x;	/* return x with inexact flags when x!=0 */
+	    return x - (t-(huge+x));
+	}
+	else k = 0;
+
+    /* x is now in primary range */
+	hfx = (float)0.5*x;
+	hxs = x*hfx;
+	r1 = one+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5))));
+	t  = (float)3.0-r1*hfx;
+	e  = hxs*((r1-t)/((float)6.0 - x*t));
+	if(k==0) return x - (x*e-hxs);		/* c is 0 */
+	else {
+	    e  = (x*(e-c)-c);
+	    e -= hxs;
+	    if(k== -1) return (float)0.5*(x-e)-(float)0.5;
+           if(k==1) {
+		if(x < (float)-0.25) return -(float)2.0*(e-(x+(float)0.5));
+		else	      return  one+(float)2.0*(x-e);
+           }
+	    if (k <= -2 || k>56) {   /* suffice to return exp(x)-1 */
+	        __int32_t i;
+	        y = one-(e-x);
+		i = CYG_LIBM_WORD(y);
+		SET_FLOAT_WORD(y,i+(k<<23));	/* add k to y's exponent */
+	        return y-one;
+	    }
+	    t = one;
+	    if(k<23) {
+	        __int32_t i;
+	        SET_FLOAT_WORD(t,0x3f800000 - (0x1000000>>k)); /* t=1-2^-k */
+		y = t-(e-x);
+		i = CYG_LIBM_WORD(y);
+		SET_FLOAT_WORD(y,i+(k<<23));	/* add k to y's exponent */
+	   } else {
+	        __int32_t i;
+		SET_FLOAT_WORD(t,((0x7f-k)<<23));	/* 2^-k */
+		y = x-(e+t);
+		y += one;
+		i = CYG_LIBM_WORD(y);
+		SET_FLOAT_WORD(y,i+(k<<23));	/* add k to y's exponent */
+	    }
+	}
+	return y;
+}
+
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_fabs.c b/packages/language/c/libm/current/src/float/portable-api/sf_fabs.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_fabs.c
@@ -0,0 +1,100 @@
+//===========================================================================
+//
+//      sf_fabs.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_fabs.c -- float version of s_fabs.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * fabsf(x) returns the absolute value of x.
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float fabsf(float x)
+#else
+	float fabsf(x)
+	float x;
+#endif
+{
+	__uint32_t ix;
+	ix = CYG_LIBM_WORD(x);
+	SET_FLOAT_WORD(x,ix&0x7fffffff);
+        return x;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_fabs.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_finite.c b/packages/language/c/libm/current/src/float/portable-api/sf_finite.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_finite.c
@@ -0,0 +1,101 @@
+//===========================================================================
+//
+//      sf_finite.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_finite.c -- float version of s_finite.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * finitef(x) returns 1 is x is finite, else 0;
+ * no branching!
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	int finitef(float x)
+#else
+	int finitef(x)
+	float x;
+#endif
+{
+	__int32_t ix;
+	ix =    CYG_LIBM_WORD(x);
+	ix &= 0x7fffffff;
+	return (FLT_UWORD_IS_FINITE(ix));
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_finite.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_floor.c b/packages/language/c/libm/current/src/float/portable-api/sf_floor.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_floor.c
@@ -0,0 +1,133 @@
+//===========================================================================
+//
+//      sf_floor.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_floor.c -- float version of s_floor.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * floorf(x)
+ * Return x rounded toward -inf to integral value
+ * Method:
+ *	Bit twiddling.
+ * Exception:
+ *	Inexact flag raised if x not equal to floorf(x).
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float huge = 1.0e30;
+#else
+static float huge = 1.0e30;
+#endif
+
+#ifdef __STDC__
+	float floorf(float x)
+#else
+	float floorf(x)
+	float x;
+#endif
+{
+	__int32_t i0,j0;
+	__uint32_t i,ix;
+	i0 = CYG_LIBM_WORD(x);
+	ix = (i0&0x7fffffff);
+	j0 = (ix>>23)-0x7f;
+	if(j0<23) {
+	    if(j0<0) {	/* raise inexact if x != 0 */
+		if(huge+x>(float)0.0) {/* return 0*sign(x) if |x|<1 */
+		    if(i0>=0) {i0=0;}
+		    else if(!FLT_UWORD_IS_ZERO(ix))
+			{ i0=0xbf800000;}
+		}
+	    } else {
+		i = (0x007fffff)>>j0;
+		if((i0&i)==0) return x; /* x is integral */
+		if(huge+x>(float)0.0) {	/* raise inexact flag */
+		    if(i0<0) i0 += (0x00800000)>>j0;
+		    i0 &= (~i);
+		}
+	    }
+	} else {
+	    if(!FLT_UWORD_IS_FINITE(ix)) return x+x;	/* inf or NaN */
+	    else return x;		/* x is integral */
+	}
+	SET_FLOAT_WORD(x,i0);
+	return x;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_floor.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_frexp.c b/packages/language/c/libm/current/src/float/portable-api/sf_frexp.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_frexp.c
@@ -0,0 +1,113 @@
+//===========================================================================
+//
+//      sf_frexp.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+/* sf_frexp.c -- float version of s_frexp.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+two25 =  3.3554432000e+07; /* 0x4c000000 */
+
+#ifdef __STDC__
+	float frexpf(float x, int *eptr)
+#else
+	float frexpf(x, eptr)
+	float x; int *eptr;
+#endif
+{
+	__int32_t hx, ix;
+	hx = CYG_LIBM_WORD(x);
+	ix = 0x7fffffff&hx;
+	*eptr = 0;
+	if(!FLT_UWORD_IS_FINITE(ix)||FLT_UWORD_IS_ZERO(ix)) return x;	/* 0,inf,nan */
+	if (FLT_UWORD_IS_SUBNORMAL(ix)) {		/* subnormal */
+	    x *= two25;
+	    hx = CYG_LIBM_WORD(x);
+	    ix = hx&0x7fffffff;
+	    *eptr = -25;
+	}
+	*eptr += (ix>>23)-126;
+	hx = (hx&0x807fffff)|0x3f000000;
+	SET_FLOAT_WORD(x,hx);
+	return x;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_frexp.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_ilogb.c b/packages/language/c/libm/current/src/float/portable-api/sf_ilogb.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_ilogb.c
@@ -0,0 +1,109 @@
+//===========================================================================
+//
+//      sf_ilogb.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_ilogb.c -- float version of s_ilogb.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include <limits.h>
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	int ilogbf(float x)
+#else
+	int ilogbf(x)
+	float x;
+#endif
+{
+	__int32_t hx,ix;
+
+	hx = CYG_LIBM_WORD(x);
+	hx &= 0x7fffffff;
+	if(FLT_UWORD_IS_ZERO(hx))
+	    return 0x80000001;	/* ilogb(0) = special case error */
+	if(FLT_UWORD_IS_SUBNORMAL(hx)) {
+	    for (ix = -126,hx<<=8; hx>0; hx<<=1) ix -=1;
+	    return ix;
+	}
+	#if FP_ILOGBNAN != INT_MAX
+	else if (FLT_UWORD_IS_NAN(hx)) return FP_ILOGBNAN;	/* NAN */
+	#endif
+	else if (!FLT_UWORD_IS_FINITE(hx)) return INT_MAX;
+	else
+		return (hx>>=23)-127;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_ilogb.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_isnan.c b/packages/language/c/libm/current/src/float/portable-api/sf_isnan.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_isnan.c
@@ -0,0 +1,99 @@
+//===========================================================================
+//
+//      sf_isnan.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_c_isnan.c -- float version of s_c_isnan.c.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/*
+ * isnanf(x) returns 1 is x is nan, else 0;
+ *
+ * isnanf is an extension declared in <ieeefp.h>.
+ */
+
+
+#include "mathincl/fdlibm.h"
+//#include <ieeefp.h>
+
+#undef isnanf
+
+    int isnanf(float x)
+{
+	__int32_t ix;
+	ix = CYG_LIBM_WORD(x);
+	ix &= 0x7fffffff;
+	return FLT_UWORD_IS_NAN(ix);
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_isnan.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_ldexp.c b/packages/language/c/libm/current/src/float/portable-api/sf_ldexp.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_ldexp.c
@@ -0,0 +1,109 @@
+//===========================================================================
+//
+//      sf_ldexp.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_ldexp.c -- float version of s_ldexp.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+#include <errno.h>
+
+#ifdef __STDC__
+	float ldexpf(float value, int exp)
+#else
+	float ldexpf(value, exp)
+	float value; int exp;
+#endif
+{
+	float z;
+
+    z = scalbnf(value,exp);
+
+#ifndef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+    if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE) return z;
+    if(!(finitef(z)||isnanf(z))&&finitef(value)) {
+        return __kernel_standard(value,(float)exp,43); /* ldexp overflow */
+    }
+    if(z==0.0&&z!=value) {
+        return __kernel_standard(value,(float)exp,44); /* ldexp underflow */
+    }
+#endif
+
+    return z;
+}
+
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_ldexp.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_log1p.c b/packages/language/c/libm/current/src/float/portable-api/sf_log1p.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_log1p.c
@@ -0,0 +1,174 @@
+//===========================================================================
+//
+//      sf_log1p.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_log1p.c -- float version of s_log1p.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+ln2_hi =   6.9313812256e-01,	/* 0x3f317180 */
+ln2_lo =   9.0580006145e-06,	/* 0x3717f7d1 */
+two25 =    3.355443200e+07,	/* 0x4c000000 */
+Lp1 = 6.6666668653e-01,	/* 3F2AAAAB */
+Lp2 = 4.0000000596e-01,	/* 3ECCCCCD */
+Lp3 = 2.8571429849e-01, /* 3E924925 */
+Lp4 = 2.2222198546e-01, /* 3E638E29 */
+Lp5 = 1.8183572590e-01, /* 3E3A3325 */
+Lp6 = 1.5313838422e-01, /* 3E1CD04F */
+Lp7 = 1.4798198640e-01; /* 3E178897 */
+
+#ifdef __STDC__
+static const float zero = 0.0;
+#else
+static float zero = 0.0;
+#endif
+
+#ifdef __STDC__
+	float log1pf(float x)
+#else
+	float log1pf(x)
+	float x;
+#endif
+{
+	float hfsq,f,c,s,z,R,u;
+	__int32_t k,hx,hu,ax;
+
+	hx = CYG_LIBM_WORD(x);
+	ax = hx&0x7fffffff;
+
+	k = 1;
+	if (!FLT_UWORD_IS_FINITE(hx)) return x+x;
+	if (hx < 0x3ed413d7) {			/* x < 0.41422  */
+	    if(ax>=0x3f800000) {		/* x <= -1.0 */
+		if(x==(float)-1.0) return -two25/zero; /* log1p(-1)=+inf */
+		else return (x-x)/(x-x);	/* log1p(x<-1)=NaN */
+	    }
+	    if(ax<0x31000000) {			/* |x| < 2**-29 */
+		if(two25+x>zero			/* raise inexact */
+	            &&ax<0x24800000)		/* |x| < 2**-54 */
+		    return x;
+		else
+		    return x - x*x*(float)0.5;
+	    }
+	    if(hx>0||hx<=((__int32_t)0xbe95f61f)) {
+		k=0;f=x;hu=1;}	/* -0.2929<x<0.41422 */
+	}
+	if(k!=0) {
+	    if(hx<0x5a000000) {
+		u  = (float)1.0+x;
+		hu = CYG_LIBM_WORD(u);
+	        k  = (hu>>23)-127;
+		/* correction term */
+	        c  = (k>0)? (float)1.0-(u-x):x-(u-(float)1.0);
+		c /= u;
+	    } else {
+		u  = x;
+		hu = CYG_LIBM_WORD(u);
+	        k  = (hu>>23)-127;
+		c  = 0;
+	    }
+	    hu &= 0x007fffff;
+	    if(hu<0x3504f7) {
+	        SET_FLOAT_WORD(u,hu|0x3f800000);/* normalize u */
+	    } else {
+	        k += 1;
+		SET_FLOAT_WORD(u,hu|0x3f000000);	/* normalize u/2 */
+	        hu = (0x00800000-hu)>>2;
+	    }
+	    f = u-(float)1.0;
+	}
+	hfsq=(float)0.5*f*f;
+	if(hu==0) {	/* |f| < 2**-20 */
+           if(f==zero) { if(k==0) return zero;
+                       else {c += k*ln2_lo; return k*ln2_hi+c;}}
+	    R = hfsq*((float)1.0-(float)0.66666666666666666*f);
+	    if(k==0) return f-R; else
+		     return k*ln2_hi-((R-(k*ln2_lo+c))-f);
+	}
+	s = f/((float)2.0+f);
+	z = s*s;
+	R = z*(Lp1+z*(Lp2+z*(Lp3+z*(Lp4+z*(Lp5+z*(Lp6+z*Lp7))))));
+	if(k==0) return f-(hfsq-s*(hfsq+R)); else
+		 return k*ln2_hi-((hfsq-(s*(hfsq+R)+(k*ln2_lo+c)))-f);
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_log1p.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_logb.c b/packages/language/c/libm/current/src/float/portable-api/sf_logb.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_logb.c
@@ -0,0 +1,114 @@
+//===========================================================================
+//
+//      sf_logb.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+/* 2009 for Newlib:  Sun's sf_ilogb.c converted to be sf_logb.c.  */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/* float logb(float x)
+ * return the binary exponent of non-zero x
+ * logbf(0) = -inf, raise divide-by-zero floating point exception
+ * logbf(+inf|-inf) = +inf (no signal is raised)
+ * logbf(NaN) = NaN (no signal is raised)
+ * Per C99 recommendation, a NaN argument is returned unchanged.
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+float
+#ifdef __STDC__
+logbf(float x)
+#else
+logbf(x)
+float x;
+#endif
+{
+	__int32_t hx,ix;
+
+	hx = CYG_LIBM_WORD(x);
+	hx &= 0x7fffffff;
+	if(FLT_UWORD_IS_ZERO(hx))  {
+		float  xx;
+		/* arg==0:  return -inf and raise divide-by-zero exception */
+		SET_FLOAT_WORD(xx,hx);	/* +0.0 */
+		return -1./xx;	/* logbf(0) = -inf */
+		}
+	if(FLT_UWORD_IS_SUBNORMAL(hx)) {
+	    for (ix = -126,hx<<=8; hx>0; hx<<=1) ix -=1;
+	    return (float) ix;
+	}
+	else if (FLT_UWORD_IS_INFINITE(hx)) return HUGE_VALF;	/* x==+|-inf */
+	else if (FLT_UWORD_IS_NAN(hx)) return x;
+	else return (float) ((hx>>23)-127);
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_logb.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_modf.c b/packages/language/c/libm/current/src/float/portable-api/sf_modf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_modf.c
@@ -0,0 +1,126 @@
+//===========================================================================
+//
+//      sf_modf.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_modf.c -- float version of s_modf.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float one = 1.0;
+#else
+static float one = 1.0;
+#endif
+
+#ifdef __STDC__
+	float modff(float x, float *iptr)
+#else
+	float modff(x, iptr)
+	float x,*iptr;
+#endif
+{
+	__int32_t i0,j0;
+	__uint32_t i;
+	i0 = CYG_LIBM_WORD(x);
+	j0 = ((i0>>23)&0xff)-0x7f;	/* exponent of x */
+	if(j0<23) {			/* integer part in x */
+	    if(j0<0) {			/* |x|<1 */
+	        SET_FLOAT_WORD(*iptr,i0&0x80000000);	/* *iptr = +-0 */
+		return x;
+	    } else {
+		i = (0x007fffff)>>j0;
+		if((i0&i)==0) {			/* x is integral */
+		    __uint32_t ix;
+		    *iptr = x;
+		    ix = CYG_LIBM_WORD(x);
+		    SET_FLOAT_WORD(x,ix&0x80000000);	/* return +-0 */
+		    return x;
+		} else {
+		    SET_FLOAT_WORD(*iptr,i0&(~i));
+		    return x - *iptr;
+		}
+	    }
+	} else {			/* no fraction part */
+	    __uint32_t ix;
+	    *iptr = x*one;
+	    ix = CYG_LIBM_WORD(x);
+	    SET_FLOAT_WORD(x,ix&0x80000000);	/* return +-0 */
+	    return x;
+	}
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_modf.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_nextafter.c b/packages/language/c/libm/current/src/float/portable-api/sf_nextafter.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_nextafter.c
@@ -0,0 +1,132 @@
+//===========================================================================
+//
+//      sf_nextafter.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_nextafter.c -- float version of s_nextafter.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float nextafterf(float x, float y)
+#else
+	float nextafterf(x,y)
+	float x,y;
+#endif
+{
+	__int32_t	hx,hy,ix,iy;
+
+	hx = CYG_LIBM_WORD(x);
+	hy = CYG_LIBM_WORD(y);
+	ix = hx&0x7fffffff;		/* |x| */
+	iy = hy&0x7fffffff;		/* |y| */
+
+	if(FLT_UWORD_IS_NAN(ix) ||
+	   FLT_UWORD_IS_NAN(iy))
+	   return x+y;
+	if(x==y) return x;		/* x=y, return x */
+	if(FLT_UWORD_IS_ZERO(ix)) {		/* x == 0 */
+	    SET_FLOAT_WORD(x,(hy&0x80000000)|FLT_UWORD_MIN);
+	    y = x*x;
+	    if(y==x) return y; else return x;	/* raise underflow flag */
+	}
+	if(hx>=0) {				/* x > 0 */
+	    if(hx>hy) {				/* x > y, x -= ulp */
+		hx -= 1;
+	    } else {				/* x < y, x += ulp */
+		hx += 1;
+	    }
+	} else {				/* x < 0 */
+	    if(hy>=0||hx>hy){			/* x < y, x -= ulp */
+		hx -= 1;
+	    } else {				/* x > y, x += ulp */
+		hx += 1;
+	    }
+	}
+	hy = hx&0x7f800000;
+	if(hy>FLT_UWORD_MAX) return x+x;	/* overflow  */
+	if(hy<0x00800000) {		/* underflow */
+	    y = x*x;
+	    if(y!=x) {		/* raise underflow flag */
+	        SET_FLOAT_WORD(y,hx);
+		return y;
+	    }
+	}
+	SET_FLOAT_WORD(x,hx);
+	return x;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_nextafter.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_rint.c b/packages/language/c/libm/current/src/float/portable-api/sf_rint.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_rint.c
@@ -0,0 +1,137 @@
+//===========================================================================
+//
+//      sf_rint.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_rint.c -- float version of s_rint.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+TWO23[2]={
+  8.3886080000e+06, /* 0x4b000000 */
+ -8.3886080000e+06, /* 0xcb000000 */
+};
+
+#ifdef __STDC__
+	float rintf(float x)
+#else
+	float rintf(x)
+	float x;
+#endif
+{
+	__int32_t i0,j0,sx;
+	__uint32_t i,i1,ix;
+	float t;
+	volatile float w;
+	i0 = CYG_LIBM_WORD(x);
+	sx = (i0>>31)&1;
+	ix = (i0&0x7fffffff);
+	j0 = (ix>>23)-0x7f;
+	if(j0<23) {
+	    if(FLT_UWORD_IS_ZERO(ix))
+	        return x;
+	    if(j0<0) {
+		i1 = (i0&0x07fffff);
+		i0 &= 0xfff00000;
+		i0 |= ((i1|-i1)>>9)&0x400000;
+		SET_FLOAT_WORD(x,i0);
+	        w = TWO23[sx]+x;
+	        t =  w-TWO23[sx];
+		i0 = CYG_LIBM_WORD(t);
+		SET_FLOAT_WORD(t,(i0&0x7fffffff)|(sx<<31));
+	        return t;
+	    } else {
+		i = (0x007fffff)>>j0;
+		if((i0&i)==0) return x; /* x is integral */
+		i>>=1;
+		if((i0&i)!=0) i0 = (i0&(~i))|((0x200000)>>j0);
+	    }
+	} else {
+	    if(!FLT_UWORD_IS_FINITE(ix)) return x+x; /* inf or NaN */
+	    else
+	      return x;		/* x is integral */
+	}
+	SET_FLOAT_WORD(x,i0);
+	w = TWO23[sx]+x;
+	return w-TWO23[sx];
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_rint.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_scalbn.c b/packages/language/c/libm/current/src/float/portable-api/sf_scalbn.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_scalbn.c
@@ -0,0 +1,136 @@
+//===========================================================================
+//
+//      sf_scalbn.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_scalbn.c -- float version of s_scalbn.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+// VAE #if INT_MAX > 50000
+#define OVERFLOW_INT 50000
+//#else
+//#define OVERFLOW_INT 30000
+//#endif
+
+#ifdef __STDC__
+static const float
+#else
+static float
+#endif
+two25   =  3.355443200e+07,	/* 0x4c000000 */
+twom25  =  2.9802322388e-08,	/* 0x33000000 */
+huge   = 1.0e+30,
+tiny   = 1.0e-30;
+
+#ifdef __STDC__
+	float scalbnf (float x, int n)
+#else
+	float scalbnf (x,n)
+	float x; int n;
+#endif
+{
+	__int32_t  k,ix;
+	__uint32_t hx;
+
+	ix = CYG_LIBM_WORD(x);
+	hx = ix&0x7fffffff;
+        k = hx>>23;		/* extract exponent */
+	if (FLT_UWORD_IS_ZERO(hx))
+	    return x;
+        if (!FLT_UWORD_IS_FINITE(hx))
+	    return x+x;		/* NaN or Inf */
+        if (FLT_UWORD_IS_SUBNORMAL(hx)) {
+	    x *= two25;
+	    ix = CYG_LIBM_WORD(x);
+	    k = ((ix&0x7f800000)>>23) - 25;
+            if (n< -50000) return tiny*x;	/*underflow*/
+        }
+        k = k+n;
+        if (k > FLT_LARGEST_EXP) return huge*copysignf(huge,x); /* overflow  */
+        if (k > 0)				/* normal result */
+	    {SET_FLOAT_WORD(x,(ix&0x807fffff)|(k<<23)); return x;}
+        if (k < FLT_SMALLEST_EXP) {
+            if (n > OVERFLOW_INT)	/* in case integer overflow in n+k */
+		return huge*copysignf(huge,x);	/*overflow*/
+	    else return tiny*copysignf(tiny,x);	/*underflow*/
+        }
+        k += 25;				/* subnormal result */
+	SET_FLOAT_WORD(x,(ix&0x807fffff)|(k<<23));
+        return x*twom25;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_scalbn.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_significand.c b/packages/language/c/libm/current/src/float/portable-api/sf_significand.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_significand.c
@@ -0,0 +1,93 @@
+//===========================================================================
+//
+//      sf_significand.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_signif.c -- float version of s_signif.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+#include "mathincl/fdlibm.h"
+
+
+#ifdef __STDC__
+	float significandf(float x)
+#else
+	float significandf(x)
+	float x;
+#endif
+{
+	return __ieee754_scalbf(x,(float) -ilogbf(x));
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_significand.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_sin.c b/packages/language/c/libm/current/src/float/portable-api/sf_sin.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_sin.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      sf_sin.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_sin.c -- float version of s_sin.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float sinf(float x)
+#else
+	float sinf(x)
+	float x;
+#endif
+{
+	float y[2],z=0.0;
+	__int32_t n,ix;
+
+	ix = CYG_LIBM_WORD(x);
+
+    /* |x| ~< pi/4 */
+	ix &= 0x7fffffff;
+	if(ix <= 0x3f490fd8) return __kernel_sinf(x,z,0);
+
+    /* sin(Inf or NaN) is NaN */
+	else if (!FLT_UWORD_IS_FINITE(ix)) return x-x;
+
+    /* argument reduction needed */
+	else {
+	    n = __ieee754_rem_pio2f(x,y);
+	    switch(n&3) {
+		case 0: return  __kernel_sinf(y[0],y[1],1);
+		case 1: return  __kernel_cosf(y[0],y[1]);
+		case 2: return -__kernel_sinf(y[0],y[1],1);
+		default:
+			return -__kernel_cosf(y[0],y[1]);
+	    }
+	}
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_cos.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_tan.c b/packages/language/c/libm/current/src/float/portable-api/sf_tan.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_tan.c
@@ -0,0 +1,110 @@
+//===========================================================================
+//
+//      sf_tan.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_tan.c -- float version of s_tan.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+	float tanf(float x)
+#else
+	float tanf(x)
+	float x;
+#endif
+{
+	float y[2],z=0.0;
+	__int32_t n,ix;
+
+	ix = CYG_LIBM_WORD(x);
+
+    /* |x| ~< pi/4 */
+	ix &= 0x7fffffff;
+	if(ix <= 0x3f490fda) return __kernel_tanf(x,z,1);
+
+    /* tan(Inf or NaN) is NaN */
+	else if (!FLT_UWORD_IS_FINITE(ix)) return x-x;		/* NaN */
+
+    /* argument reduction needed */
+	else {
+	    n = __ieee754_rem_pio2f(x,y);
+	    return __kernel_tanf(y[0],y[1],1-((n&1)<<1)); /*   1 -- n even
+							      -1 -- n odd */
+	}
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_tan.c
diff --git a/packages/language/c/libm/current/src/float/portable-api/sf_tanh.c b/packages/language/c/libm/current/src/float/portable-api/sf_tanh.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/float/portable-api/sf_tanh.c
@@ -0,0 +1,126 @@
+//===========================================================================
+//
+//      sf_tanh.c
+//
+//      Part of the standard mathematical function library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors: visar, ilijak
+// Date:        2012-03-08
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// Derived from code with the following copyright
+
+
+/* sf_tanh.c -- float version of s_tanh.c.
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+
+#include "mathincl/fdlibm.h"
+
+#ifdef __STDC__
+static const float one=1.0, two=2.0, tiny = 1.0e-30;
+#else
+static float one=1.0, two=2.0, tiny = 1.0e-30;
+#endif
+
+#ifdef __STDC__
+	float tanhf(float x)
+#else
+	float tanhf(x)
+	float x;
+#endif
+{
+	float t,z;
+	__int32_t jx,ix;
+
+	jx = CYG_LIBM_WORD(x);
+	ix = jx&0x7fffffff;
+
+    /* x is INF or NaN */
+	if(!FLT_UWORD_IS_FINITE(ix)) {
+	    if (jx>=0) return one/x+one;    /* tanh(+-inf)=+-1 */
+	    else       return one/x-one;    /* tanh(NaN) = NaN */
+	}
+
+    /* |x| < 22 */
+	if (ix < 0x41b00000) {		/* |x|<22 */
+	    if (ix<0x24000000)		/* |x|<2**-55 */
+		return x*(one+x);	/* tanh(small) = small */
+	    if (ix>=0x3f800000) {	/* |x|>=1  */
+		t = expm1f(two*fabsf(x));
+		z = one - two/(t+two);
+	    } else {
+	        t = expm1f(-two*fabsf(x));
+	        z= -t/(t+two);
+	    }
+    /* |x| > 22, return +-1 */
+	} else {
+	    z = one - tiny;		/* raised inexact flag */
+	}
+	return (jx>=0)? z: -z;
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF sf_tanh.c
diff --git a/packages/language/c/libm/current/src/mathincl/fdlibm.h b/packages/language/c/libm/current/src/mathincl/fdlibm.h
--- a/packages/language/c/libm/current/src/mathincl/fdlibm.h
+++ b/packages/language/c/libm/current/src/mathincl/fdlibm.h
@@ -84,6 +84,111 @@
 typedef cyg_int32   __int32_t;
 typedef cyg_uint32  __uint32_t;
 typedef Cyg_libm_ieee_double_shape_type ieee_double_shape_type;
+typedef Cyg_libm_ieee_float_shape_type ieee_float_shape_type;
+
+/* Most routines need to check whether a float is finite, infinite, or not a
+   number, and many need to know whether the result of an operation will
+   overflow.  These conditions depend on whether the largest exponent is
+   used for NaNs & infinities, or whether it's used for finite numbers.  The
+   macros below wrap up that kind of information:
+
+   FLT_UWORD_IS_FINITE(X)
+	True if a positive float with bitmask X is finite.
+
+   FLT_UWORD_IS_NAN(X)
+	True if a positive float with bitmask X is not a number.
+
+   FLT_UWORD_IS_INFINITE(X)
+	True if a positive float with bitmask X is +infinity.
+
+   FLT_UWORD_MAX
+	The bitmask of FLT_MAX.
+
+   FLT_UWORD_HALF_MAX
+	The bitmask of FLT_MAX/2.
+
+   FLT_UWORD_EXP_MAX
+	The bitmask of the largest finite exponent (129 if the largest
+	exponent is used for finite numbers, 128 otherwise).
+
+   FLT_UWORD_LOG_MAX
+	The bitmask of log(FLT_MAX), rounded down.  This value is the largest
+	input that can be passed to exp() without producing overflow.
+
+   FLT_UWORD_LOG_2MAX
+	The bitmask of log(2*FLT_MAX), rounded down.  This value is the
+	largest input than can be passed to cosh() without producing
+	overflow.
+
+   FLT_LARGEST_EXP
+	The largest biased exponent that can be used for finite numbers
+	(255 if the largest exponent is used for finite numbers, 254
+	otherwise) */
+
+#ifdef _FLT_LARGEST_EXPONENT_IS_NORMAL
+#define FLT_UWORD_IS_FINITE(x) 1
+#define FLT_UWORD_IS_NAN(x) 0
+#define FLT_UWORD_IS_INFINITE(x) 0
+#define FLT_UWORD_MAX 0x7fffffff
+#define FLT_UWORD_EXP_MAX 0x43010000
+#define FLT_UWORD_LOG_MAX 0x42b2d4fc
+#define FLT_UWORD_LOG_2MAX 0x42b437e0
+//#define HUGE ((float)0X1.FFFFFEP128)
+#else
+#define FLT_UWORD_IS_FINITE(x) ((x)<0x7f800000L)
+#define FLT_UWORD_IS_NAN(x) ((x)>0x7f800000L)
+#define FLT_UWORD_IS_INFINITE(x) ((x)==0x7f800000L)
+#define FLT_UWORD_MAX 0x7f7fffffL
+#define FLT_UWORD_EXP_MAX 0x43000000
+#define FLT_UWORD_LOG_MAX 0x42b17217
+#define FLT_UWORD_LOG_2MAX 0x42b2d4fc
+//#define HUGE ((float)3.40282346638528860e+38)
+#endif
+#define FLT_UWORD_HALF_MAX (FLT_UWORD_MAX-(1L<<23))
+#define FLT_LARGEST_EXP (FLT_UWORD_MAX>>23)
+
+/* Many routines check for zero and subnormal numbers.  Such things depend
+   on whether the target supports denormals or not:
+
+   FLT_UWORD_IS_ZERO(X)
+	True if a positive float with bitmask X is +0.	Without denormals,
+	any float with a zero exponent is a +0 representation.	With
+	denormals, the only +0 representation is a 0 bitmask.
+
+   FLT_UWORD_IS_SUBNORMAL(X)
+	True if a non-zero positive float with bitmask X is subnormal.
+	(Routines should check for zeros first.)
+
+   FLT_UWORD_MIN
+	The bitmask of the smallest float above +0.  Call this number
+	REAL_FLT_MIN...
+
+   FLT_UWORD_EXP_MIN
+	The bitmask of the float representation of REAL_FLT_MIN's exponent.
+
+   FLT_UWORD_LOG_MIN
+	The bitmask of |log(REAL_FLT_MIN)|, rounding down.
+
+   FLT_SMALLEST_EXP
+	REAL_FLT_MIN's exponent - EXP_BIAS (1 if denormals are not supported,
+	-22 if they are).
+*/
+
+#ifdef _FLT_NO_DENORMALS
+#define FLT_UWORD_IS_ZERO(x) ((x)<0x00800000L)
+#define FLT_UWORD_IS_SUBNORMAL(x) 0
+#define FLT_UWORD_MIN 0x00800000
+#define FLT_UWORD_EXP_MIN 0x42fc0000
+#define FLT_UWORD_LOG_MIN 0x42aeac50
+#define FLT_SMALLEST_EXP 1
+#else
+#define FLT_UWORD_IS_ZERO(x) ((x)==0)
+#define FLT_UWORD_IS_SUBNORMAL(x) ((x)<0x00800000L)
+#define FLT_UWORD_MIN 0x00000001
+#define FLT_UWORD_EXP_MIN 0x43160000
+#define FLT_UWORD_LOG_MIN 0x42cff1b5
+#define FLT_SMALLEST_EXP -22
+#endif
 
 // MACRO DEFINITIONS
 
@@ -95,7 +200,25 @@ typedef Cyg_libm_ieee_double_shape_type 
 #define CYG_LIBM_HIp(__x) (((Cyg_libm_ieee_double_shape_type *)__x)->parts.msw)
 #define CYG_LIBM_LOp(__x) (((Cyg_libm_ieee_double_shape_type *)__x)->parts.lsw)
 
+#define CYG_LIBM_WORD(__x)  (((Cyg_libm_ieee_float_shape_type *)&__x)->asi32)
 
+/* Get a 32 bit int from a float.  */
+
+#define GET_FLOAT_WORD(i,f)					\
+do {								\
+  Cyg_libm_ieee_float_shape_type gf_u;					\
+  gf_u.value = (f);						\
+  (i) = gf_u.asi32;						\
+} while (0)
+
+/* Set a float from a 32 bit int.  */
+
+#define SET_FLOAT_WORD(f,i)					\
+do {								\
+  Cyg_libm_ieee_float_shape_type sf_u;					\
+  sf_u.asi32 = (i);						\
+  (f) = sf_u.value;						\
+} while (0)
 
 /* Get two 32 bit ints from a double.  */
 
@@ -179,9 +302,19 @@ struct exception {
 externC int
 matherr( struct exception * );    // User-overridable error handling - see
                                   // <pkgconf/libm.h> for a discussion
+struct exceptionf {
+    int type;       // One of DOMAIN, SING, OVERFLOW, UNDERFLOW, TLOSS, PLOSS
+    char *name;     // Name of the function generating the exception
+    float arg1;     // First argument to the function
+    float arg2;     // Second argument to the function
+    float retval;   // Value to be returned - can be altered by matherr()
+};
+
+externC int
+matherrf( struct exceptionf * );
+
 #endif // ifdef CYGSYM_LIBM_NO_XOPEN_SVID_NAMESPACE_POLLUTION
 
-
 // FUNCTION PROTOTYPES
 
 // IEEE-754 style elementary functions */
@@ -289,6 +422,85 @@ externC double
 externC int
 __kernel_rem_pio2( double *, double *, int, int, int, const int * );
 
+/* ieee style elementary float functions */
+externC float __ieee754_sqrtf (float);
+externC float __ieee754_acosf (float);
+externC float __ieee754_acoshf (float);
+externC float __ieee754_logf (float);
+externC float __ieee754_atanhf (float);
+externC float __ieee754_asinf (float);
+externC float __ieee754_atan2f (float,float);
+externC float __ieee754_expf (float);
+externC float __ieee754_coshf (float);
+externC float __ieee754_fmodf (float,float);
+externC float __ieee754_powf (float,float);
+externC float
+__ieee754_lgammaf_r( float, int * );
+
+externC float
+__ieee754_gammaf_r( float, int * );
+
+externC float
+__ieee754_lgammaf( float );
+
+externC float
+__ieee754_gammaf( float );
+externC float __ieee754_log10f (float);
+externC float __ieee754_sinhf (float);
+externC float __ieee754_hypotf (float,float);
+externC float __ieee754_j0f (float);
+externC float __ieee754_j1f (float);
+externC float __ieee754_y0f (float);
+externC float __ieee754_y1f (float);
+externC float __ieee754_jnf (int,float);
+externC float __ieee754_ynf (int,float);
+externC float __ieee754_remainderf (float,float);
+externC cyg_int32 __ieee754_rem_pio2f (float,float*);
+#ifdef _SCALB_INT
+externC float __ieee754_scalbf ((float,int));
+#else
+externC float __ieee754_scalbf (float,float);
+#endif
+
+/* float versions of fdlibm kernel functions */
+externC float __kernel_standard_float( float, float, int );
+externC float __kernel_sinf (float,float,int);
+externC float __kernel_cosf (float,float);
+externC float __kernel_tanf (float,float,int);
+externC int   __kernel_rem_pio2f (float*,float*,int,int,int,const cyg_int32*);
+
+#ifdef  _COMPLEX_H
+
+/*
+ * Quoting from ISO/IEC 9899:TC2:
+ *
+ * 6.2.5.13 Types
+ * Each complex type has the same representation and alignment requirements as
+ * an array type containing exactly two elements of the corresponding real type;
+ * the first element is equal to the real part, and the second element to the
+ * imaginary part, of the complex number.
+ */
+typedef union {
+        float complex z;
+        float parts[2];
+} float_complex;
+
+typedef union {
+        double complex z;
+        double parts[2];
+} double_complex;
+
+typedef union {
+        long double complex z;
+        long double parts[2];
+} long_double_complex;
+
+#define REAL_PART(z)    ((z).parts[0])
+#define IMAG_PART(z)    ((z).parts[1])
+
+#endif  /* _COMPLEX_H */
+
+
 #endif // ifdef CYGPKG_LIBM     
 
 #endif // CYGONCE_LIBM_MATHINCL_FDLIBM_H multiple inclusion protection
diff --git a/packages/language/c/libm/current/src/misc/matherr.c b/packages/language/c/libm/current/src/misc/matherr.c
--- a/packages/language/c/libm/current/src/misc/matherr.c
+++ b/packages/language/c/libm/current/src/misc/matherr.c
@@ -74,13 +74,28 @@ matherr( struct exception *x )
 {
     CYG_REPORT_FUNCNAMETYPE( "matherr", "returning %d" );
 
-    CYG_UNUSED_PARAM( struct exception *, x );
+//    CYG_UNUSED_PARAM( struct exception *, x );
     CYG_EMPTY_STATEMENT;
 
     CYG_REPORT_RETVAL( 0 );
     return 0;
 } // matherr()
 
+int
+matherrf( struct exceptionf *x ) __attribute__ ((weak));
+
+int
+matherrf( struct exceptionf *x )
+{
+    CYG_REPORT_FUNCNAMETYPE( "matherrf", "returning %d" );
+
+//    CYG_UNUSED_PARAM( struct exceptionf *, x );
+    CYG_EMPTY_STATEMENT;
+
+    CYG_REPORT_RETVAL( 0 );
+    return 0;
+} // matherrf()
+
 
 #endif // if defined(CYGPKG_LIBM)
 
diff --git a/packages/language/c/libm/current/src/misc/standard.c b/packages/language/c/libm/current/src/misc/standard.c
--- a/packages/language/c/libm/current/src/misc/standard.c
+++ b/packages/language/c/libm/current/src/misc/standard.c
@@ -1,14 +1,14 @@
 //===========================================================================
 //
-//      signgam.cxx
+//      standard_float.c
 //
-//      Support sign of the gamma*() functions in Math library
+//      Standard conformance (non-IEEE) on exception cases.
 //
 //===========================================================================
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+// Copyright (C) 2013 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -39,793 +39,21 @@
 //===========================================================================
 //#####DESCRIPTIONBEGIN####
 //
-// Author(s):   jlarmour
-// Contributors:  jlarmour
-// Date:        1998-02-13
+// Author(s):   ilijak
+// Contributors:  
+// Date:        2013-06-17
 // Purpose:     
-// Description: Contains the accessor functions to get and set the stored sign
-//              of the gamma*() functions in the math library
+// Description: 
+//              
 // Usage:       
 //
 //####DESCRIPTIONEND####
 //
 //===========================================================================
 
-/* @(#)k_standard.c 1.3 95/01/18 */
-/*
- * ====================================================
- * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
- *
- * Developed at SunSoft, a Sun Microsystems, Inc. business.
- * Permission to use, copy, modify, and distribute this
- * software is freely granted, provided that this notice 
- * is preserved.
- * ====================================================
- *
- */
-
-// CONFIGURATION
-
-#include <pkgconf/libm.h>   // Configuration header
-
-// Include the Math library?
-#ifdef CYGPKG_LIBM
-
-// INCLUDES
-
-#include <cyg/infra/cyg_type.h>    // Common type definitions and support
-#include <cyg/infra/cyg_trac.h>    // Tracing macros
-
-#include <math.h>                  // Main header for math library
-#include "mathincl/fdlibm.h"       // Internal header for math library
-
-#include <cyg/error/codes.h>       // standard error codes
-
-#ifndef CYGSEM_LIBM_COMPAT_IEEE_ONLY
-#include <errno.h>
-#else
-static int errno; // this whole file won't be used if we're IEEE only, but
-                  // doing this keeps the compiler happy
-#endif
-
-#ifdef CYGSEM_LIBM_USE_STDERR
-
-#include <stdio.h>
-#define WRITE2(u,v)     fputs(u, stderr)
-
-#else
-
-#define WRITE2(u,v)     0
-
-#endif // ifdef CYGSEM_LIBM_USE_STDERR
-
-
-// GLOBALS
-
-static const double zero = 0.0;
-
-// FUNCTIONS
-
-/* 
- * Standard conformance (non-IEEE) on exception cases.
- * Mapping:
- *      1 -- acos(|x|>1)
- *      2 -- asin(|x|>1)
- *      3 -- atan2(+-0,+-0)
- *      4 -- hypot overflow
- *      5 -- cosh overflow
- *      6 -- exp overflow
- *      7 -- exp underflow
- *      8 -- y0(0)
- *      9 -- y0(-ve)
- *      10-- y1(0)
- *      11-- y1(-ve)
- *      12-- yn(0)
- *      13-- yn(-ve)
- *      14-- lgamma(finite) overflow
- *      15-- lgamma(-integer)
- *      16-- log(0)
- *      17-- log(x<0)
- *      18-- log10(0)
- *      19-- log10(x<0)
- *      20-- pow(0.0,0.0)
- *      21-- pow(x,y) overflow
- *      22-- pow(x,y) underflow
- *      23-- pow(0,negative) 
- *      24-- pow(neg,non-integral)
- *      25-- sinh(finite) overflow
- *      26-- sqrt(negative)
- *      27-- fmod(x,0)
- *      28-- remainder(x,0)
- *      29-- acosh(x<1)
- *      30-- atanh(|x|>1)
- *      31-- atanh(|x|=1)
- *      32-- scalb overflow
- *      33-- scalb underflow
- *      34-- j0(|x|>X_TLOSS)
- *      35-- y0(x>X_TLOSS)
- *      36-- j1(|x|>X_TLOSS)
- *      37-- y1(x>X_TLOSS)
- *      38-- jn(|x|>X_TLOSS, n)
- *      39-- yn(x>X_TLOSS, n)
- *      40-- gamma(finite) overflow
- *      41-- gamma(-integer)
- *      42-- pow(NaN,0.0)
- *      43-- ldexp overflow
- *      44-- ldexp underflow
- */
-
-
-double
-__kernel_standard(double x, double y, int type) 
-{
-        struct exception exc;
+#define CYG_STANDARD_FLOAT_T double
+#define CYGSTR_FLOAT_SUFFIX
+#define MATHERR(__exc_p) matherr(__exc_p)
+#include "standard.inl"
 
-#ifdef CYGSEM_LIBM_USE_STDERR
-        (void) fflush(stdout);
-#endif
-        exc.arg1 = x;
-        exc.arg2 = y;
-        switch(type) {
-            case 1:
-                /* acos(|x|>1) */
-                exc.type = DOMAIN;
-                exc.name = "acos";
-                exc.retval = zero;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                    (void) WRITE2("acos: DOMAIN error\n", 19);
-                  }
-                  errno = EDOM;
-                }
-                break;
-            case 2:
-                /* asin(|x|>1) */
-                exc.type = DOMAIN;
-                exc.name = "asin";
-                exc.retval = zero;
-                if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("asin: DOMAIN error\n", 19);
-                  }
-                  errno = EDOM;
-                }
-                break;
-            case 3:
-                /* atan2(+-0,+-0) */
-                exc.arg1 = y;
-                exc.arg2 = x;
-                exc.type = DOMAIN;
-                exc.name = "atan2";
-                exc.retval = zero;
-                if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("atan2: DOMAIN error\n", 20);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 4:
-                /* hypot(finite,finite) overflow */
-                exc.type = OVERFLOW;
-                exc.name = "hypot";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = HUGE;
-                else
-                  exc.retval = HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        errno = ERANGE;
-                }
-                break;
-            case 5:
-                /* cosh(finite) overflow */
-                exc.type = OVERFLOW;
-                exc.name = "cosh";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = HUGE;
-                else
-                  exc.retval = HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        errno = ERANGE;
-                }
-                break;
-            case 6:
-                /* exp(finite) overflow */
-                exc.type = OVERFLOW;
-                exc.name = "exp";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = HUGE;
-                else
-                  exc.retval = HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        errno = ERANGE;
-                }
-                break;
-            case 7:
-                /* exp(finite) underflow */
-                exc.type = UNDERFLOW;
-                exc.name = "exp";
-                exc.retval = zero;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        errno = ERANGE;
-                }
-                break;
-            case 8:
-                /* y0(0) = -inf */
-                exc.type = DOMAIN;      /* should be SING for IEEE */
-                exc.name = "y0";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = -HUGE;
-                else
-                  exc.retval = -HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("y0: DOMAIN error\n", 17);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 9:
-                /* y0(x<0) = NaN */
-                exc.type = DOMAIN;
-                exc.name = "y0";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = -HUGE;
-                else
-                  exc.retval = -HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("y0: DOMAIN error\n", 17);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 10:
-                /* y1(0) = -inf */
-                exc.type = DOMAIN;      /* should be SING for IEEE */
-                exc.name = "y1";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = -HUGE;
-                else
-                  exc.retval = -HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("y1: DOMAIN error\n", 17);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 11:
-                /* y1(x<0) = NaN */
-                exc.type = DOMAIN;
-                exc.name = "y1";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = -HUGE;
-                else
-                  exc.retval = -HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("y1: DOMAIN error\n", 17);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 12:
-                /* yn(n,0) = -inf */
-                exc.type = DOMAIN;      /* should be SING for IEEE */
-                exc.name = "yn";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = -HUGE;
-                else
-                  exc.retval = -HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("yn: DOMAIN error\n", 17);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 13:
-                /* yn(x<0) = NaN */
-                exc.type = DOMAIN;
-                exc.name = "yn";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = -HUGE;
-                else
-                  exc.retval = -HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("yn: DOMAIN error\n", 17);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 14:
-                /* lgamma(finite) overflow */
-                exc.type = OVERFLOW;
-                exc.name = "lgamma";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = HUGE;
-                else
-                  exc.retval = HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                        errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        errno = ERANGE;
-                }
-                break;
-            case 15:
-                /* lgamma(-integer) or lgamma(0) */
-                exc.type = SING;
-                exc.name = "lgamma";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = HUGE;
-                else
-                  exc.retval = HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("lgamma: SING error\n", 19);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 16:
-                /* log(0) */
-                exc.type = SING;
-                exc.name = "log";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = -HUGE;
-                else
-                  exc.retval = -HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = ERANGE;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("log: SING error\n", 16);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 17:
-                /* log(x<0) */
-                exc.type = DOMAIN;
-                exc.name = "log";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = -HUGE;
-                else
-                  exc.retval = -HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("log: DOMAIN error\n", 18);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 18:
-                /* log10(0) */
-                exc.type = SING;
-                exc.name = "log10";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = -HUGE;
-                else
-                  exc.retval = -HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = ERANGE;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("log10: SING error\n", 18);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 19:
-                /* log10(x<0) */
-                exc.type = DOMAIN;
-                exc.name = "log10";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = -HUGE;
-                else
-                  exc.retval = -HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("log10: DOMAIN error\n", 20);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 20:
-                /* pow(0.0,0.0) */
-                /* error only if cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID */
-                exc.type = DOMAIN;
-                exc.name = "pow";
-                exc.retval = zero;
-                if (cyg_libm_get_compat_mode() != CYGNUM_LIBM_COMPAT_SVID) exc.retval = 1.0;
-                else if (!matherr(&exc)) {
-                        (void) WRITE2("pow(0,0): DOMAIN error\n", 23);
-                        errno = EDOM;
-                }
-                break;
-            case 21:
-                /* pow(x,y) overflow */
-                exc.type = OVERFLOW;
-                exc.name = "pow";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                  exc.retval = HUGE;
-                  y *= 0.5;
-                  if(x<zero&&rint(y)!=y) exc.retval = -HUGE;
-                } else {
-                  exc.retval = HUGE_VAL;
-                  y *= 0.5;
-                  if(x<zero&&rint(y)!=y) exc.retval = -HUGE_VAL;
-                }
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        errno = ERANGE;
-                }
-                break;
-            case 22:
-                /* pow(x,y) underflow */
-                exc.type = UNDERFLOW;
-                exc.name = "pow";
-                exc.retval =  zero;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        errno = ERANGE;
-                }
-                break;
-            case 23:
-                /* 0**neg */
-                exc.type = DOMAIN;
-                exc.name = "pow";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) 
-                  exc.retval = zero;
-                else
-                  exc.retval = -HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("pow(0,neg): DOMAIN error\n", 25);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 24:
-                /* neg**non-integral */
-                exc.type = DOMAIN;
-                exc.name = "pow";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) 
-                    exc.retval = zero;
-                else 
-                    exc.retval = zero/zero;     /* X/Open allow NaN */
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX) 
-                   errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("neg**non-integral: DOMAIN error\n", 32);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 25:
-                /* sinh(finite) overflow */
-                exc.type = OVERFLOW;
-                exc.name = "sinh";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = ( (x>zero) ? HUGE : -HUGE);
-                else
-                  exc.retval = ( (x>zero) ? HUGE_VAL : -HUGE_VAL);
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        errno = ERANGE;
-                }
-                break;
-            case 26:
-                /* sqrt(x<0) */
-                exc.type = DOMAIN;
-                exc.name = "sqrt";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = zero;
-                else
-                  exc.retval = zero/zero;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("sqrt: DOMAIN error\n", 19);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 27:
-                /* fmod(x,0) */
-                exc.type = DOMAIN;
-                exc.name = "fmod";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                    exc.retval = x;
-                else
-                    exc.retval = zero/zero;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                    (void) WRITE2("fmod:  DOMAIN error\n", 20);
-                  }
-                  errno = EDOM;
-                }
-                break;
-            case 28:
-                /* remainder(x,0) */
-                exc.type = DOMAIN;
-                exc.name = "remainder";
-                exc.retval = zero/zero;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                    (void) WRITE2("remainder: DOMAIN error\n", 24);
-                  }
-                  errno = EDOM;
-                }
-                break;
-            case 29:
-                /* acosh(x<1) */
-                exc.type = DOMAIN;
-                exc.name = "acosh";
-                exc.retval = zero/zero;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                    (void) WRITE2("acosh: DOMAIN error\n", 20);
-                  }
-                  errno = EDOM;
-                }
-                break;
-            case 30:
-                /* atanh(|x|>1) */
-                exc.type = DOMAIN;
-                exc.name = "atanh";
-                exc.retval = zero/zero;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                    (void) WRITE2("atanh: DOMAIN error\n", 20);
-                  }
-                  errno = EDOM;
-                }
-                break;
-            case 31:
-                /* atanh(|x|=1) */
-                exc.type = SING;
-                exc.name = "atanh";
-                exc.retval = x/zero;    /* sign(x)*inf */
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                    (void) WRITE2("atanh: SING error\n", 18);
-                  }
-                  errno = EDOM;
-                }
-                break;
-            case 32:
-                /* scalb overflow; SVID also returns +-HUGE_VAL */
-                exc.type = OVERFLOW;
-                exc.name = "scalb";
-                exc.retval = x > zero ? HUGE_VAL : -HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        errno = ERANGE;
-                }
-                break;
-            case 33:
-                /* scalb underflow */
-                exc.type = UNDERFLOW;
-                exc.name = "scalb";
-                exc.retval = copysign(zero,x);
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        errno = ERANGE;
-                }
-                break;
-            case 34:
-                /* j0(|x|>X_TLOSS) */
-                exc.type = TLOSS;
-                exc.name = "j0";
-                exc.retval = zero;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                        errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                                (void) WRITE2(exc.name, 2);
-                                (void) WRITE2(": TLOSS error\n", 14);
-                        }
-                        errno = ERANGE;
-                }        
-                break;
-            case 35:
-                /* y0(x>X_TLOSS) */
-                exc.type = TLOSS;
-                exc.name = "y0";
-                exc.retval = zero;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                        errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                                (void) WRITE2(exc.name, 2);
-                                (void) WRITE2(": TLOSS error\n", 14);
-                        }
-                        errno = ERANGE;
-                }        
-                break;
-            case 36:
-                /* j1(|x|>X_TLOSS) */
-                exc.type = TLOSS;
-                exc.name = "j1";
-                exc.retval = zero;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                        errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                                (void) WRITE2(exc.name, 2);
-                                (void) WRITE2(": TLOSS error\n", 14);
-                        }
-                        errno = ERANGE;
-                }        
-                break;
-            case 37:
-                /* y1(x>X_TLOSS) */
-                exc.type = TLOSS;
-                exc.name = "y1";
-                exc.retval = zero;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                        errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                                (void) WRITE2(exc.name, 2);
-                                (void) WRITE2(": TLOSS error\n", 14);
-                        }
-                        errno = ERANGE;
-                }        
-                break;
-            case 38:
-                /* jn(|x|>X_TLOSS) */
-                exc.type = TLOSS;
-                exc.name = "jn";
-                exc.retval = zero;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                        errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                                (void) WRITE2(exc.name, 2);
-                                (void) WRITE2(": TLOSS error\n", 14);
-                        }
-                        errno = ERANGE;
-                }        
-                break;
-            case 39:
-                /* yn(x>X_TLOSS) */
-                exc.type = TLOSS;
-                exc.name = "yn";
-                exc.retval = zero;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                        errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                                (void) WRITE2(exc.name, 2);
-                                (void) WRITE2(": TLOSS error\n", 14);
-                        }
-                        errno = ERANGE;
-                }        
-                break;
-            case 40:
-                /* gamma(finite) overflow */
-                exc.type = OVERFLOW;
-                exc.name = "gamma";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = HUGE;
-                else
-                  exc.retval = HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = ERANGE;
-                else if (!matherr(&exc)) {
-                  errno = ERANGE;
-                }
-                break;
-            case 41:
-                /* gamma(-integer) or gamma(0) */
-                exc.type = SING;
-                exc.name = "gamma";
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
-                  exc.retval = HUGE;
-                else
-                  exc.retval = HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = EDOM;
-                else if (!matherr(&exc)) {
-                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
-                        (void) WRITE2("gamma: SING error\n", 18);
-                      }
-                  errno = EDOM;
-                }
-                break;
-            case 42:
-                /* pow(NaN,0.0) */
-                /* error only if cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID & CYGNUM_LIBM_COMPAT_XOPEN */
-                exc.type = DOMAIN;
-                exc.name = "pow";
-                exc.retval = x;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE ||
-                    cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX) exc.retval = 1.0;
-                else if (!matherr(&exc)) {
-                        errno = EDOM;
-                }
-                break;
-            case 43:
-                /* ldexp overflow; SVID also returns +-HUGE_VAL */
-                exc.type = OVERFLOW;
-                exc.name = "ldexp";
-                exc.retval = x > zero ? HUGE_VAL : -HUGE_VAL;
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        errno = ERANGE;
-                }
-                break;
-            case 44:
-                /* ldexp underflow */
-                exc.type = UNDERFLOW;
-                exc.name = "ldexp";
-                exc.retval = copysign(zero,x);
-                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
-                  errno = ERANGE;
-                else if (!matherr(&exc)) {
-                        errno = ERANGE;
-                }
-                break;
-        }
-        return exc.retval; 
-}
-
-#endif // ifdef CYGPKG_LIBM
-
-// EOF standard.c
+// EOF standard_float.c
diff --git a/packages/language/c/libm/current/src/misc/standard.inl b/packages/language/c/libm/current/src/misc/standard.inl
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/misc/standard.inl
@@ -0,0 +1,860 @@
+//===========================================================================
+//
+//      standard.inl
+//
+//      
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour
+// Contributors: ilijak
+// Date:         1998-02-13
+// Purpose:     
+// Description:
+//
+// Usage:        This file is included by standard.c and standard_float.c
+// Note:         The contents of this file originally existed in standard.c
+//               with addition of single precision math library the body was
+//               transfered here, while standard.c and standard_float.c include
+//               and instantiate this file for double and single precision floats
+//               respectively.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+/* @(#)k_standard.c 1.3 95/01/18 */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunSoft, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice 
+ * is preserved.
+ * ====================================================
+ *
+ */
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// Include the Math library?
+#ifdef CYGPKG_LIBM
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/cyg_trac.h>    // Tracing macros
+
+#include <math.h>                  // Main header for math library
+#include "mathincl/fdlibm.h"       // Internal header for math library
+
+#include <cyg/error/codes.h>       // standard error codes
+
+#ifndef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+#include <errno.h>
+#else
+static int errno; // this whole file won't be used if we're IEEE only, but
+                  // doing this keeps the compiler happy
+#endif
+
+#ifdef CYGSEM_LIBM_USE_STDERR
+
+#include <stdio.h>
+#define WRITE2(u,v)     fputs(u, stderr)
+
+#else
+
+#define WRITE2(u,v)     0
+
+#endif // ifdef CYGSEM_LIBM_USE_STDERR
+
+
+// GLOBALS
+
+static const CYG_STANDARD_FLOAT_T zero = (CYG_STANDARD_FLOAT_T)0.0;
+
+// FUNCTIONS
+
+/* 
+ * Standard conformance (non-IEEE) on exception cases.
+ * Mapping:
+ *      1 -- acos(|x|>1)
+ *      2 -- asin(|x|>1)
+ *      3 -- atan2(+-0,+-0)
+ *      4 -- hypot overflow
+ *      5 -- cosh overflow
+ *      6 -- exp overflow
+ *      7 -- exp underflow
+ *      8 -- y0(0)
+ *      9 -- y0(-ve)
+ *      10-- y1(0)
+ *      11-- y1(-ve)
+ *      12-- yn(0)
+ *      13-- yn(-ve)
+ *      14-- lgamma(finite) overflow
+ *      15-- lgamma(-integer)
+ *      16-- log(0)
+ *      17-- log(x<0)
+ *      18-- log10(0)
+ *      19-- log10(x<0)
+ *      20-- pow(0.0,0.0)
+ *      21-- pow(x,y) overflow
+ *      22-- pow(x,y) underflow
+ *      23-- pow(0,negative) 
+ *      24-- pow(neg,non-integral)
+ *      25-- sinh(finite) overflow
+ *      26-- sqrt(negative)
+ *      27-- fmod(x,0)
+ *      28-- remainder(x,0)
+ *      29-- acosh(x<1)
+ *      30-- atanh(|x|>1)
+ *      31-- atanh(|x|=1)
+ *      32-- scalb overflow
+ *      33-- scalb underflow
+ *      34-- j0(|x|>X_TLOSS)
+ *      35-- y0(x>X_TLOSS)
+ *      36-- j1(|x|>X_TLOSS)
+ *      37-- y1(x>X_TLOSS)
+ *      38-- jn(|x|>X_TLOSS, n)
+ *      39-- yn(x>X_TLOSS, n)
+ *      40-- gamma(finite) overflow
+ *      41-- gamma(-integer)
+ *      42-- pow(NaN,0.0)
+ *      43-- ldexp overflow
+ *      44-- ldexp underflow
+ */
+
+#ifdef FLOAT_SINGLE_PRECISION
+float
+__kernel_standard_float(float x, float y, int type) 
+{
+        struct exceptionf exc;
+
+#else
+double
+__kernel_standard(double x, double y, int type) 
+{
+        struct exception exc;
+
+#endif
+
+#ifdef CYGSEM_LIBM_USE_STDERR
+        (void) fflush(stdout);
+#endif
+        exc.arg1 = x;
+        exc.arg2 = y;
+        switch(type) {
+            case 1:
+                /* acos(|x|>1) */
+                exc.type = DOMAIN;
+                exc.name = "acos" CYGSTR_FLOAT_SUFFIX;
+#ifdef CYGOPT_LIBM_COMPAT_POSIX_IEEE
+                exc.retval = (x-x)/(x-x);
+#else
+                exc.retval = zero;
+#endif
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                    (void) WRITE2("acos: DOMAIN error\n", 19);
+                  }
+                  errno = EDOM;
+                }
+                break;
+            case 2:
+                /* asin(|x|>1) */
+                exc.type = DOMAIN;
+                exc.name = "asin" CYGSTR_FLOAT_SUFFIX;
+#ifdef CYGOPT_LIBM_COMPAT_POSIX_IEEE
+                exc.retval = (x-x)/(x-x);
+#else
+                exc.retval = zero;
+#endif
+                if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("asin: DOMAIN error\n", 19);
+                  }
+                  errno = EDOM;
+                }
+                break;
+            case 3:
+                /* atan2(+-0,+-0) */
+                exc.arg1 = y;
+                exc.arg2 = x;
+                exc.type = DOMAIN;
+                exc.name = "atan2" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = zero;
+                if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if(cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("atan2: DOMAIN error\n", 20);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 4:
+                /* hypot(finite,finite) overflow */
+                exc.type = OVERFLOW;
+                exc.name = "hypot" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = HUGE;
+                else
+                  exc.retval = HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        errno = ERANGE;
+                }
+                break;
+            case 5:
+                /* cosh(finite) overflow */
+                exc.type = OVERFLOW;
+                exc.name = "cosh" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = HUGE;
+                else
+                  exc.retval = HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        errno = ERANGE;
+                }
+                break;
+            case 6:
+                /* exp(finite) overflow */
+                exc.type = OVERFLOW;
+                exc.name = "exp" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = HUGE;
+                else
+                  exc.retval = HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        errno = ERANGE;
+                }
+                break;
+            case 7:
+                /* exp(finite) underflow */
+                exc.type = UNDERFLOW;
+                exc.name = "exp" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = zero;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        errno = ERANGE;
+                }
+                break;
+            case 8:
+                /* y0(0) = -inf */
+                exc.type = DOMAIN;      /* should be SING for IEEE */
+                exc.name = "y0" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = -HUGE;
+                else
+                  exc.retval = -HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("y0: DOMAIN error\n", 17);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 9:
+                /* y0(x<0) = NaN */
+                exc.type = DOMAIN;
+                exc.name = "y0" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = -HUGE;
+                else
+                  exc.retval = -HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("y0: DOMAIN error\n", 17);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 10:
+                /* y1(0) = -inf */
+                exc.type = DOMAIN;      /* should be SING for IEEE */
+                exc.name = "y1" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = -HUGE;
+                else
+                  exc.retval = -HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("y1: DOMAIN error\n", 17);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 11:
+                /* y1(x<0) = NaN */
+                exc.type = DOMAIN;
+                exc.name = "y1" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = -HUGE;
+                else
+                  exc.retval = -HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("y1: DOMAIN error\n", 17);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 12:
+                /* yn(n,0) = -inf */
+                exc.type = DOMAIN;      /* should be SING for IEEE */
+                exc.name = "yn" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = -HUGE;
+                else
+                  exc.retval = -HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("yn: DOMAIN error\n", 17);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 13:
+                /* yn(x<0) = NaN */
+                exc.type = DOMAIN;
+                exc.name = "yn" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = -HUGE;
+                else
+                  exc.retval = -HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("yn: DOMAIN error\n", 17);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 14:
+                /* lgamma(finite) overflow */
+                exc.type = OVERFLOW;
+                exc.name = "lgamma" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = HUGE;
+                else
+                  exc.retval = HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                        errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        errno = ERANGE;
+                }
+                break;
+            case 15:
+                /* lgamma(-integer) or lgamma(0) */
+                exc.type = SING;
+                exc.name = "lgamma" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = HUGE;
+                else
+                  exc.retval = HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("lgamma: SING error\n", 19);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 16:
+                /* log(0) */
+                exc.type = SING;
+                exc.name = "log" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = -HUGE;
+                else
+                  exc.retval = -HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("log: SING error\n", 16);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 17:
+                /* log(x<0) */
+                exc.type = DOMAIN;
+                exc.name = "log" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = -HUGE;
+                else
+#ifdef CYGOPT_LIBM_COMPAT_POSIX_IEEE
+                  exc.retval = (x-x)/(x-x);
+#else
+                  exc.retval = -HUGE_VAL;
+#endif
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("log: DOMAIN error\n", 18);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 18:
+                /* log10(0) */
+                exc.type = SING;
+                exc.name = "log10" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = -HUGE;
+                else
+                  exc.retval = -HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("log10: SING error\n", 18);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 19:
+                /* log10(x<0) */
+                exc.type = DOMAIN;
+                exc.name = "log10" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = -HUGE;
+                else
+#ifdef CYGOPT_LIBM_COMPAT_POSIX_IEEE
+                  exc.retval = (x-x)/(x-x);
+#else
+                  exc.retval = -HUGE_VAL;
+#endif
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("log10: DOMAIN error\n", 20);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 20:
+                /* pow(0.0,0.0) */
+                /* error only if cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID */
+                exc.type = DOMAIN;
+                exc.name = "pow" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = zero;
+                if (cyg_libm_get_compat_mode() != CYGNUM_LIBM_COMPAT_SVID) exc.retval = 1.0;
+                else if (!MATHERR(&exc)) {
+                        (void) WRITE2("pow(0,0): DOMAIN error\n", 23);
+                        errno = EDOM;
+                }
+                break;
+            case 21:
+                /* pow(x,y) overflow */
+                exc.type = OVERFLOW;
+                exc.name = "pow" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                  exc.retval = HUGE;
+                  y *= 0.5;
+                  if(x<zero&&rint(y)!=y) exc.retval = -HUGE;
+                } else {
+                  exc.retval = HUGE_VAL;
+                  y *= 0.5;
+                  if(x<zero&&rint(y)!=y) exc.retval = -HUGE_VAL;
+                }
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        errno = ERANGE;
+                }
+                break;
+            case 22:
+                /* pow(x,y) underflow */
+                exc.type = UNDERFLOW;
+                exc.name = "pow" CYGSTR_FLOAT_SUFFIX;
+                exc.retval =  zero;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        errno = ERANGE;
+                }
+                break;
+            case 23:
+                /* 0**neg */
+                exc.type = DOMAIN;
+                exc.name = "pow" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) 
+                  exc.retval = zero;
+                else
+                  exc.retval = -HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("pow(0,neg): DOMAIN error\n", 25);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 24:
+                /* neg**non-integral */
+                exc.type = DOMAIN;
+                exc.name = "pow" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) 
+                    exc.retval = zero;
+                else 
+                    exc.retval = zero/zero;     /* X/Open allow NaN */
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX) 
+                   errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("neg**non-integral: DOMAIN error\n", 32);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 25:
+                /* sinh(finite) overflow */
+                exc.type = OVERFLOW;
+                exc.name = "sinh" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = ( (x>zero) ? HUGE : -HUGE);
+                else
+                  exc.retval = ( (x>zero) ? HUGE_VAL : -HUGE_VAL);
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        errno = ERANGE;
+                }
+                break;
+            case 26:
+                /* sqrt(x<0) */
+                exc.type = DOMAIN;
+                exc.name = "sqrt" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = zero;
+                else
+                  exc.retval = zero/zero;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("sqrt: DOMAIN error\n", 19);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 27:
+                /* fmod(x,0) */
+                exc.type = DOMAIN;
+                exc.name = "fmod" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                    exc.retval = x;
+                else
+                    exc.retval = zero/zero;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                    (void) WRITE2("fmod:  DOMAIN error\n", 20);
+                  }
+                  errno = EDOM;
+                }
+                break;
+            case 28:
+                /* remainder(x,0) */
+                exc.type = DOMAIN;
+                exc.name = "remainder" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = zero/zero;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                    (void) WRITE2("remainder: DOMAIN error\n", 24);
+                  }
+                  errno = EDOM;
+                }
+                break;
+            case 29:
+                /* acosh(x<1) */
+                exc.type = DOMAIN;
+                exc.name = "acosh" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = zero/zero;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                    (void) WRITE2("acosh: DOMAIN error\n", 20);
+                  }
+                  errno = EDOM;
+                }
+                break;
+            case 30:
+                /* atanh(|x|>1) */
+                exc.type = DOMAIN;
+                exc.name = "atanh" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = zero/zero;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                    (void) WRITE2("atanh: DOMAIN error\n", 20);
+                  }
+                  errno = EDOM;
+                }
+                break;
+            case 31:
+                /* atanh(|x|=1) */
+                exc.type = SING;
+                exc.name = "atanh" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = x/zero;    /* sign(x)*inf */
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                    (void) WRITE2("atanh: SING error\n", 18);
+                  }
+                  errno = EDOM;
+                }
+                break;
+            case 32:
+                /* scalb overflow; SVID also returns +-HUGE_VAL */
+                exc.type = OVERFLOW;
+                exc.name = "scalb" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = x > zero ? HUGE_VAL : -HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        errno = ERANGE;
+                }
+                break;
+            case 33:
+                /* scalb underflow */
+                exc.type = UNDERFLOW;
+                exc.name = "scalb" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = copysign(zero,x);
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        errno = ERANGE;
+                }
+                break;
+            case 34:
+                /* j0(|x|>X_TLOSS) */
+                exc.type = TLOSS;
+                exc.name = "j0" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = zero;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                        errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                                (void) WRITE2(exc.name, 2);
+                                (void) WRITE2(": TLOSS error\n", 14);
+                        }
+                        errno = ERANGE;
+                }        
+                break;
+            case 35:
+                /* y0(x>X_TLOSS) */
+                exc.type = TLOSS;
+                exc.name = "y0" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = zero;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                        errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                                (void) WRITE2(exc.name, 2);
+                                (void) WRITE2(": TLOSS error\n", 14);
+                        }
+                        errno = ERANGE;
+                }        
+                break;
+            case 36:
+                /* j1(|x|>X_TLOSS) */
+                exc.type = TLOSS;
+                exc.name = "j1" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = zero;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                        errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                                (void) WRITE2(exc.name, 2);
+                                (void) WRITE2(": TLOSS error\n", 14);
+                        }
+                        errno = ERANGE;
+                }        
+                break;
+            case 37:
+                /* y1(x>X_TLOSS) */
+                exc.type = TLOSS;
+                exc.name = "y1" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = zero;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                        errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                                (void) WRITE2(exc.name, 2);
+                                (void) WRITE2(": TLOSS error\n", 14);
+                        }
+                        errno = ERANGE;
+                }        
+                break;
+            case 38:
+                /* jn(|x|>X_TLOSS) */
+                exc.type = TLOSS;
+                exc.name = "jn" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = zero;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                        errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                                (void) WRITE2(exc.name, 2);
+                                (void) WRITE2(": TLOSS error\n", 14);
+                        }
+                        errno = ERANGE;
+                }        
+                break;
+            case 39:
+                /* yn(x>X_TLOSS) */
+                exc.type = TLOSS;
+                exc.name = "yn" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = zero;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                        errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                                (void) WRITE2(exc.name, 2);
+                                (void) WRITE2(": TLOSS error\n", 14);
+                        }
+                        errno = ERANGE;
+                }        
+                break;
+            case 40:
+                /* gamma(finite) overflow */
+                exc.type = OVERFLOW;
+                exc.name = "gamma" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = HUGE;
+                else
+                  exc.retval = HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                  errno = ERANGE;
+                }
+                break;
+            case 41:
+                /* gamma(-integer) or gamma(0) */
+                exc.type = SING;
+                exc.name = "gamma" CYGSTR_FLOAT_SUFFIX;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID)
+                  exc.retval = HUGE;
+                else
+                  exc.retval = HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = EDOM;
+                else if (!MATHERR(&exc)) {
+                  if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID) {
+                        (void) WRITE2("gamma: SING error\n", 18);
+                      }
+                  errno = EDOM;
+                }
+                break;
+            case 42:
+                /* pow(NaN,0.0) */
+                /* error only if cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_SVID & CYGNUM_LIBM_COMPAT_XOPEN */
+                exc.type = DOMAIN;
+                exc.name = "pow" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = x;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_IEEE ||
+                    cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX) exc.retval = 1.0;
+                else if (!MATHERR(&exc)) {
+                        errno = EDOM;
+                }
+                break;
+            case 43:
+                /* ldexp overflow; SVID also returns +-HUGE_VAL */
+                exc.type = OVERFLOW;
+                exc.name = "ldexp" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = x > zero ? HUGE_VAL : -HUGE_VAL;
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        errno = ERANGE;
+                }
+                break;
+            case 44:
+                /* ldexp underflow */
+                exc.type = UNDERFLOW;
+                exc.name = "ldexp" CYGSTR_FLOAT_SUFFIX;
+                exc.retval = copysign(zero,x);
+                if (cyg_libm_get_compat_mode() == CYGNUM_LIBM_COMPAT_POSIX)
+                  errno = ERANGE;
+                else if (!MATHERR(&exc)) {
+                        errno = ERANGE;
+                }
+                break;
+        }
+        return exc.retval; 
+}
+
+#endif // ifdef CYGPKG_LIBM
+
+// EOF standard.c
diff --git a/packages/language/c/libm/current/src/misc/standard_float.c b/packages/language/c/libm/current/src/misc/standard_float.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/src/misc/standard_float.c
@@ -0,0 +1,60 @@
+//===========================================================================
+//
+//      standard_float.c
+//
+//      Standard conformance (non-IEEE) on exception cases.
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Contributors:  
+// Date:        2013-06-17
+// Purpose:     
+// Description: 
+//              
+// Usage:       
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+#define FLOAT_SINGLE_PRECISION
+#define CYG_STANDARD_FLOAT_T float
+#define CYGSTR_FLOAT_SUFFIX "f"
+#define MATHERR(__exc_p) matherrf(__exc_p)
+#include "standard.inl"
+
+// EOF standard_float.c
diff --git a/packages/language/c/libm/current/tests/vectors/acosf.c b/packages/language/c/libm/current/tests/vectors/acosf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/acosf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      acosf.c
+//
+//      Test of acosf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/acosf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(acosf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &acosf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &acosf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("acosf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("acosf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library acosf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "acosf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF acosf.c
diff --git a/packages/language/c/libm/current/tests/vectors/acosf.h b/packages/language/c/libm/current/tests/vectors/acosf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/acosf.h
@@ -0,0 +1,901 @@
+#ifndef CYGONCE_LIBM_ACOS_H
+#define CYGONCE_LIBM_ACOS_H
+//===========================================================================
+//
+//      acosf.h
+//
+//      Test vectors for testing of acosf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/acosf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define ACOS_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t acosf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
+{1, 3214430700u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
+{2, 3214346813u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
+{3, 3214262927u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
+{4, 3214179041u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
+{5, 3214095155u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
+{6, 3214011269u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
+{7, 3213927383u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
+{8, 3213843497u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
+{9, 3213759611u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
+{10, 3213675725u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
+{11, 3213591839u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
+{12, 3213507953u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
+{13, 3213424067u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
+{14, 3213340180u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
+{15, 3213256294u, 1115684864u, 2143289344u, EDOM, ACOS_TOLERANCE, 0},
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+{673, 409663799u, 3322946721u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{674, 2147483648u, 3286432366u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{675, 2147483648u, 3250061248u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{676, 2147483648u, 1195896327u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{677, 2147483648u, 1171219623u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{678, 2147483648u, 1093697541u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{679, 2147483648u, 3032135104u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{680, 2147483648u, 3411964796u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{681, 244369307u, 3136168070u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{682, 2147483648u, 1147204146u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{683, 2169506506u, 952770933u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{684, 2147483648u, 1038197181u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{685, 31340u, 812862946u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{686, 2147483650u, 1327912576u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{687, 197631173u, 3443552129u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{688, 2147483648u, 2953199494u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{689, 2147483648u, 1184612738u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{690, 2147483648u, 3402547824u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{691, 2147483648u, 894632143u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{692, 2728370577u, 897541752u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{693, 2147483648u, 1261942977u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{694, 2147483648u, 1099200954u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{695, 2147483648u, 3154292435u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{696, 2147483648u, 3152683606u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{697, 2147483648u, 1121826464u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{698, 2147483648u, 880804546u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{699, 2147483648u, 3141673859u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{700, 2446012935u, 3133522904u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{701, 2147483648u, 954983712u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{702, 2147483648u, 854348972u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{703, 308447u, 3231395033u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{704, 2147483648u, 3231323929u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{705, 236u, 3463576490u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{706, 2147483648u, 3276600049u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{707, 2147483648u, 1012037114u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{708, 428667909u, 827589466u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{709, 2709748098u, 3349525030u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{710, 2147483648u, 3030201286u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{711, 2147483648u, 3395574276u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{712, 2147483648u, 3037433263u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{713, 2147483648u, 3367144216u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{714, 2147483648u, 3296624630u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{715, 2147483648u, 3185505910u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{716, 225982867u, 855857523u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{717, 2147483648u, 1190400416u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{718, 2147483648u, 3268819116u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{719, 487188428u, 3025581813u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{720, 2147483648u, 3452213962u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{721, 2147483648u, 2994137867u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{722, 2147483648u, 1097262576u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{723, 71316482u, 3285809933u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{724, 2147483648u, 891257783u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{725, 1131u, 3188660897u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{726, 2147483648u, 3448533274u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{727, 2345099095u, 1024052164u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{728, 2147483648u, 893873945u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{729, 2147483648u, 1318917723u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{730, 2811770800u, 1094056396u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{731, 2147483648u, 971406232u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{732, 2147483648u, 1156679346u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{733, 505481166u, 1327433469u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{734, 2147483648u, 1158002738u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{735, 80634256u, 3217565926u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{736, 2147483648u, 3348046043u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{737, 2147483648u, 3042603886u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{738, 2147483648u, 3401478939u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{739, 117882441u, 2975268107u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{740, 622405526u, 933456504u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{741, 2147483648u, 1275983938u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{742, 2147483648u, 3064757885u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{743, 2147483648u, 3213261231u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{744, 2147483648u, 1257170393u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{745, 2147483648u, 968803479u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{746, 2147483648u, 3190256226u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{747, 2147483648u, 3107269354u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{748, 2147483648u, 3276193236u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{749, 651028769u, 3381966453u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{750, 2147483648u, 3137791426u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{751, 2147483648u, 3392203888u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{752, 2678157437u, 959123675u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{753, 372854u, 2997685349u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{754, 2147483648u, 3365775178u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{755, 2147483648u, 1200179013u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{756, 788951227u, 3254453434u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{757, 2957296123u, 2972152223u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{758, 2147483648u, 1273440283u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{759, 701665361u, 1227824408u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{760, 2147483648u, 938291177u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{761, 2147483648u, 3086279225u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{762, 2147483648u, 1223209034u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{763, 2147483648u, 1154573712u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{764, 2147483648u, 955325067u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{765, 2147483648u, 3113982619u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{766, 2147483648u, 1295331892u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{767, 2147483648u, 3134912135u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{768, 2863444097u, 815271840u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{769, 491705664u, 1193124813u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{770, 2147483648u, 1130046118u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{771, 2147483648u, 3422483143u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{772, 2147483648u, 963588452u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{773, 2147483648u, 3040968274u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{774, 2147483648u, 1029390534u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{775, 2147495995u, 1200467128u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{776, 2584489366u, 3233768835u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{777, 2147483648u, 3410148475u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{778, 2151563707u, 913267570u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{779, 2147483648u, 3388531942u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{780, 2147483648u, 3200345720u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{781, 780554677u, 1168166977u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{782, 2984790262u, 1225900941u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{783, 2147483648u, 3225037855u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{784, 2147483648u, 3391018698u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{785, 2147483648u, 1069185756u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{786, 2147483648u, 3123041418u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{787, 2147483648u, 1066846928u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{788, 2147483648u, 3461136033u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{789, 2147483648u, 912815101u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{790, 730526127u, 3412416876u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{791, 2147483654u, 1015752130u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{792, 2147483648u, 826306215u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{793, 2147483648u, 3169816394u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{794, 2915338033u, 3341154295u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{795, 2147483648u, 956765468u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{796, 635019546u, 3395476366u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{797, 2147483648u, 903755282u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{798, 2147483648u, 1184548899u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{799, 230260625u, 3475052132u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{800, 2147483648u, 3061939312u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{801, 2147483648u, 1130024229u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{802, 2147483648u, 2992012112u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{803, 15126300u, 3116086293u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{804, 2147483648u, 1247679409u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{805, 2147483648u, 1206496619u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{806, 632617934u, 3033764041u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{807, 256321691u, 3371852521u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{808, 2147483648u, 3320833608u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{809, 2147483648u, 893808771u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{810, 504952999u, 1266922074u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{811, 2147483648u, 1180498658u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{812, 2677787743u, 3136744746u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{813, 2147483648u, 992654477u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{814, 2147483648u, 1244289498u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{815, 154625229u, 2984576643u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{816, 2147483649u, 3184572184u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{817, 2147483648u, 3328004548u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{818, 2147483648u, 1110034241u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{819, 2147483648u, 3342934766u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{820, 2147483648u, 965658941u, 1070141403u, 0, ACOS_TOLERANCE, 0},
+{821, 2147483648u, 3037575685u, 1070141403u, 0, ACOS_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_ACOS_H multiple inclusion protection
+
+// EOF acosf.h
diff --git a/packages/language/c/libm/current/tests/vectors/acoshf.c b/packages/language/c/libm/current/tests/vectors/acoshf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/acoshf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      acoshf.c
+//
+//      Test of acoshf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/acoshf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(acoshf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &acoshf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &acoshf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("acoshf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("acoshf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library acoshf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "acoshf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF acoshf.c
diff --git a/packages/language/c/libm/current/tests/vectors/acoshf.h b/packages/language/c/libm/current/tests/vectors/acoshf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/acoshf.h
@@ -0,0 +1,360 @@
+#ifndef CYGONCE_LIBM_ACOSH_H
+#define CYGONCE_LIBM_ACOSH_H
+//===========================================================================
+//
+//      acoshf.h
+//
+//      Test vectors for testing of acoshf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/acoshf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define ACOSH_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t acoshf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{1, 3214430700u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{2, 3214346813u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{3, 3214262927u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{4, 3214179041u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{5, 3214095155u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{6, 3214011269u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{7, 3213927383u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
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+{218, 1065185444u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{219, 1065437102u, 1041281514u, 1041281514u, 0, ACOSH_TOLERANCE, 0},
+{220, 1065520988u, 1045198281u, 1045198281u, 0, ACOSH_TOLERANCE, 0},
+{221, 1065604874u, 1048196204u, 1048196204u, 0, ACOSH_TOLERANCE, 0},
+{222, 1065688760u, 1049646660u, 1049646660u, 0, ACOSH_TOLERANCE, 0},
+{223, 1065772646u, 1050754509u, 1050754509u, 0, ACOSH_TOLERANCE, 0},
+{224, 1065856532u, 1051753636u, 1051753636u, 0, ACOSH_TOLERANCE, 0},
+{225, 1065940419u, 1052670210u, 1052670210u, 0, ACOSH_TOLERANCE, 0},
+{226, 1066024305u, 1053521262u, 1053521262u, 0, ACOSH_TOLERANCE, 0},
+{227, 1066108191u, 1054318670u, 1054318670u, 0, ACOSH_TOLERANCE, 0},
+{228, 1066192077u, 1055071074u, 1055071074u, 0, ACOSH_TOLERANCE, 0},
+{229, 1066275963u, 1055785005u, 1055785005u, 0, ACOSH_TOLERANCE, 0},
+{230, 1066359849u, 1056465542u, 1056465542u, 0, ACOSH_TOLERANCE, 0},
+{231, 1066443735u, 1057040669u, 1057040669u, 0, ACOSH_TOLERANCE, 0},
+{232, 1066527621u, 1057353227u, 1057353227u, 0, ACOSH_TOLERANCE, 0},
+{233, 1066611507u, 1057654105u, 1057654105u, 0, ACOSH_TOLERANCE, 0},
+{234, 1066695393u, 1057944433u, 1057944433u, 0, ACOSH_TOLERANCE, 0},
+{235, 1066779279u, 1058225171u, 1058225171u, 0, ACOSH_TOLERANCE, 0},
+{236, 1066863165u, 1058497140u, 1058497140u, 0, ACOSH_TOLERANCE, 0},
+{237, 1066947052u, 1058761049u, 1058761049u, 0, ACOSH_TOLERANCE, 0},
+{238, 3234402267u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{239, 3231108068u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{240, 3226013659u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{241, 3217625051u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{242, 1070141403u, 1065548063u, 1065548063u, 0, ACOSH_TOLERANCE, 0},
+{243, 1078530011u, 1072160792u, 1072160792u, 0, ACOSH_TOLERANCE, 0},
+{244, 1083624420u, 1074714438u, 1074714438u, 0, ACOSH_TOLERANCE, 0},
+{245, 3253731328u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{246, 3252840038u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{247, 3251948749u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{248, 3251057459u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{249, 3250166170u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{250, 3249274880u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{251, 3248383590u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{252, 3247492301u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{253, 3246601011u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{254, 3245028147u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{255, 3243245568u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{256, 3241462989u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{257, 3239680410u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{258, 3237792973u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{259, 3234227814u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{260, 3230662656u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{261, 3224580915u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{262, 3213675725u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{263, 1058642330u, 1115684864u, 2143289344u, EDOM, ACOSH_TOLERANCE, 0},
+{264, 1075000115u, 1069338181u, 1069338181u, 0, ACOSH_TOLERANCE, 0},
+{265, 1082130432u, 1074007898u, 1074007898u, 0, ACOSH_TOLERANCE, 0},
+{266, 1085695590u, 1075527877u, 1075527877u, 0, ACOSH_TOLERANCE, 0},
+{267, 1089260749u, 1076636021u, 1076636021u, 0, ACOSH_TOLERANCE, 0},
+{268, 1091672474u, 1077509940u, 1077509940u, 0, ACOSH_TOLERANCE, 0},
+{269, 1093455053u, 1078232007u, 1078232007u, 0, ACOSH_TOLERANCE, 0},
+{270, 1095237632u, 1078847433u, 1078847433u, 0, ACOSH_TOLERANCE, 0},
+{271, 1097020211u, 1079383779u, 1079383779u, 0, ACOSH_TOLERANCE, 0},
+{272, 1098802790u, 1079859115u, 1079859115u, 0, ACOSH_TOLERANCE, 0},
+{273, 1099746509u, 1080285937u, 1080285937u, 0, ACOSH_TOLERANCE, 0},
+{274, 1100637798u, 1080673248u, 1080673248u, 0, ACOSH_TOLERANCE, 0},
+{275, 1101529088u, 1081027759u, 1081027759u, 0, ACOSH_TOLERANCE, 0},
+{276, 1102420378u, 1081354598u, 1081354598u, 0, ACOSH_TOLERANCE, 0},
+{277, 1103311667u, 1081657776u, 1081657776u, 0, ACOSH_TOLERANCE, 0},
+{278, 1104202957u, 1081940495u, 1081940495u, 0, ACOSH_TOLERANCE, 0},
+{279, 1105094246u, 1082167886u, 1082167886u, 0, ACOSH_TOLERANCE, 0},
+{280, 1105985536u, 1082292437u, 1082292437u, 0, ACOSH_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_ACOSH_H multiple inclusion protection
+
+// EOF acoshf.h
diff --git a/packages/language/c/libm/current/tests/vectors/asinf.c b/packages/language/c/libm/current/tests/vectors/asinf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/asinf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      asin.c
+//
+//      Test of asin() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_double_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/asinf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(asinf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &asinf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &asinf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("asinf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("asinf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library asinf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "asinf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF asin.c
diff --git a/packages/language/c/libm/current/tests/vectors/asinf.h b/packages/language/c/libm/current/tests/vectors/asinf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/asinf.h
@@ -0,0 +1,820 @@
+#ifndef CYGONCE_LIBM_ASIN_H
+#define CYGONCE_LIBM_ASIN_H
+//===========================================================================
+//
+//      asin.h
+//
+//      Test vectors for testing of asin() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/asin.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define ASIN_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t asinf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{1, 3214430700u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{2, 3214346813u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{3, 3214262927u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{4, 3214179041u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{5, 3214095155u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{6, 3214011269u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{7, 3213927383u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{8, 3213843497u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{9, 3213759611u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{10, 3213675725u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{11, 3213591839u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{12, 3213507953u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{13, 3213424067u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{14, 3213340180u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{15, 3213256294u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{16, 3213172408u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{17, 3213088522u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{18, 3213004636u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{19, 3212920750u, 1115684864u, 2143289344u, EDOM, ASIN_TOLERANCE, 0},
+{20, 3212836864u, 3217625051u, 3217625051u, 0, ASIN_TOLERANCE, 0},
+{21, 3212669092u, 3216437732u, 3216437732u, 0, ASIN_TOLERANCE, 0},
+{22, 3212501320u, 3215944521u, 3215944521u, 0, ASIN_TOLERANCE, 0},
+{23, 3212333548u, 3215565099u, 3215565099u, 0, ASIN_TOLERANCE, 0},
+{24, 3212165775u, 3215244413u, 3215244413u, 0, ASIN_TOLERANCE, 0},
+{25, 3211998003u, 3214961161u, 3214961161u, 0, ASIN_TOLERANCE, 0},
+{26, 3211830231u, 3214704423u, 3214704423u, 0, ASIN_TOLERANCE, 0},
+{27, 3211662459u, 3214467718u, 3214467718u, 0, ASIN_TOLERANCE, 0},
+{28, 3211494687u, 3214246826u, 3214246826u, 0, ASIN_TOLERANCE, 0},
+{29, 3211326915u, 3214038819u, 3214038819u, 0, ASIN_TOLERANCE, 0},
+{30, 3211159142u, 3213841564u, 3213841564u, 0, ASIN_TOLERANCE, 0},
+{31, 3210991370u, 3213653454u, 3213653454u, 0, ASIN_TOLERANCE, 0},
+{32, 3210823598u, 3213473242u, 3213473242u, 0, ASIN_TOLERANCE, 0},
+{33, 3210655826u, 3213299935u, 3213299935u, 0, ASIN_TOLERANCE, 0},
+{34, 3210488054u, 3213132728u, 3213132728u, 0, ASIN_TOLERANCE, 0},
+{35, 3210320282u, 3212970959u, 3212970959u, 0, ASIN_TOLERANCE, 0},
+{36, 3210152509u, 3212791284u, 3212791284u, 0, ASIN_TOLERANCE, 0},
+{37, 3209984737u, 3212486350u, 3212486350u, 0, ASIN_TOLERANCE, 0},
+{38, 3209816965u, 3212189449u, 3212189449u, 0, ASIN_TOLERANCE, 0},
+{39, 3209649193u, 3211899893u, 3211899893u, 0, ASIN_TOLERANCE, 0},
+{40, 3209481421u, 3211617081u, 3211617081u, 0, ASIN_TOLERANCE, 0},
+{41, 3209313649u, 3211340489u, 3211340489u, 0, ASIN_TOLERANCE, 0},
+{42, 3209145876u, 3211069649u, 3211069649u, 0, ASIN_TOLERANCE, 0},
+{43, 3208978104u, 3210804156u, 3210804156u, 0, ASIN_TOLERANCE, 0},
+{44, 3208810332u, 3210543640u, 3210543640u, 0, ASIN_TOLERANCE, 0},
+{45, 3208642560u, 3210287770u, 3210287770u, 0, ASIN_TOLERANCE, 0},
+{46, 3208474788u, 3210036251u, 3210036251u, 0, ASIN_TOLERANCE, 0},
+{47, 3208307016u, 3209788813u, 3209788813u, 0, ASIN_TOLERANCE, 0},
+{48, 3208139244u, 3209545215u, 3209545215u, 0, ASIN_TOLERANCE, 0},
+{49, 3207971471u, 3209305230u, 3209305230u, 0, ASIN_TOLERANCE, 0},
+{50, 3207803699u, 3209068660u, 3209068660u, 0, ASIN_TOLERANCE, 0},
+{51, 3207635927u, 3208835315u, 3208835315u, 0, ASIN_TOLERANCE, 0},
+{52, 3207468155u, 3208605024u, 3208605024u, 0, ASIN_TOLERANCE, 0},
+{53, 3207300383u, 3208377629u, 3208377629u, 0, ASIN_TOLERANCE, 0},
+{54, 3207132611u, 3208152982u, 3208152982u, 0, ASIN_TOLERANCE, 0},
+{55, 3206964838u, 3207930946u, 3207930946u, 0, ASIN_TOLERANCE, 0},
+{56, 3206797066u, 3207711396u, 3207711396u, 0, ASIN_TOLERANCE, 0},
+{57, 3206629294u, 3207494214u, 3207494214u, 0, ASIN_TOLERANCE, 0},
+{58, 3206461522u, 3207279289u, 3207279289u, 0, ASIN_TOLERANCE, 0},
+{59, 3206293750u, 3207066519u, 3207066519u, 0, ASIN_TOLERANCE, 0},
+{60, 3206125978u, 3206855806u, 3206855806u, 0, ASIN_TOLERANCE, 0},
+{61, 3205958205u, 3206647058u, 3206647058u, 0, ASIN_TOLERANCE, 0},
+{62, 3205790433u, 3206440193u, 3206440193u, 0, ASIN_TOLERANCE, 0},
+{63, 3205622661u, 3206235129u, 3206235129u, 0, ASIN_TOLERANCE, 0},
+{64, 3205454889u, 3206031787u, 3206031787u, 0, ASIN_TOLERANCE, 0},
+{65, 3205287117u, 3205830100u, 3205830100u, 0, ASIN_TOLERANCE, 0},
+{66, 3205119345u, 3205629996u, 3205629996u, 0, ASIN_TOLERANCE, 0},
+{67, 3204951572u, 3205431410u, 3205431410u, 0, ASIN_TOLERANCE, 0},
+{68, 3204783800u, 3205234284u, 3205234284u, 0, ASIN_TOLERANCE, 0},
+{69, 3204616028u, 3205038560u, 3205038560u, 0, ASIN_TOLERANCE, 0},
+{70, 3204448256u, 3204844178u, 3204844178u, 0, ASIN_TOLERANCE, 0},
+{71, 3204112712u, 3204651089u, 3204651089u, 0, ASIN_TOLERANCE, 0},
+{72, 3203777167u, 3204459240u, 3204459240u, 0, ASIN_TOLERANCE, 0},
+{73, 3203441623u, 3204088914u, 3204088914u, 0, ASIN_TOLERANCE, 0},
+{74, 3203106079u, 3203709898u, 3203709898u, 0, ASIN_TOLERANCE, 0},
+{75, 3202770534u, 3203333085u, 3203333085u, 0, ASIN_TOLERANCE, 0},
+{76, 3202434990u, 3202958395u, 3202958395u, 0, ASIN_TOLERANCE, 0},
+{77, 3202099446u, 3202585743u, 3202585743u, 0, ASIN_TOLERANCE, 0},
+{78, 3201763901u, 3202215051u, 3202215051u, 0, ASIN_TOLERANCE, 0},
+{79, 3201428357u, 3201846246u, 3201846246u, 0, ASIN_TOLERANCE, 0},
+{80, 3201092813u, 3201479254u, 3201479254u, 0, ASIN_TOLERANCE, 0},
+{81, 3200757268u, 3201114005u, 3201114005u, 0, ASIN_TOLERANCE, 0},
+{82, 3200421724u, 3200750433u, 3200750433u, 0, ASIN_TOLERANCE, 0},
+{83, 3200086180u, 3200388473u, 3200388473u, 0, ASIN_TOLERANCE, 0},
+{84, 3199750636u, 3200028060u, 3200028060u, 0, ASIN_TOLERANCE, 0},
+{85, 3199415091u, 3199669135u, 3199669135u, 0, ASIN_TOLERANCE, 0},
+{86, 3199079547u, 3199311640u, 3199311640u, 0, ASIN_TOLERANCE, 0},
+{87, 3198744003u, 3198955516u, 3198955516u, 0, ASIN_TOLERANCE, 0},
+{88, 3198408458u, 3198600708u, 3198600708u, 0, ASIN_TOLERANCE, 0},
+{89, 3198072914u, 3198247163u, 3198247163u, 0, ASIN_TOLERANCE, 0},
+{90, 3197737370u, 3197894829u, 3197894829u, 0, ASIN_TOLERANCE, 0},
+{91, 3197401825u, 3197543654u, 3197543654u, 0, ASIN_TOLERANCE, 0},
+{92, 3197066281u, 3197193590u, 3197193590u, 0, ASIN_TOLERANCE, 0},
+{93, 3196730737u, 3196844588u, 3196844588u, 0, ASIN_TOLERANCE, 0},
+{94, 3196395192u, 3196496600u, 3196496600u, 0, ASIN_TOLERANCE, 0},
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+{587, 0u, 1181934749u, 0u, 0, ASIN_TOLERANCE, 0},
+{588, 0u, 1190838126u, 0u, 0, ASIN_TOLERANCE, 0},
+{589, 0u, 867988931u, 0u, 0, ASIN_TOLERANCE, 0},
+{590, 0u, 991229856u, 0u, 0, ASIN_TOLERANCE, 0},
+{591, 0u, 3364998151u, 0u, 0, ASIN_TOLERANCE, 0},
+{592, 0u, 1315543293u, 0u, 0, ASIN_TOLERANCE, 0},
+{593, 0u, 1057448325u, 0u, 0, ASIN_TOLERANCE, 0},
+{594, 0u, 1267482842u, 0u, 0, ASIN_TOLERANCE, 0},
+{595, 0u, 934466263u, 0u, 0, ASIN_TOLERANCE, 0},
+{596, 0u, 1245869105u, 0u, 0, ASIN_TOLERANCE, 0},
+{597, 0u, 1108490809u, 0u, 0, ASIN_TOLERANCE, 0},
+{598, 0u, 3400104881u, 0u, 0, ASIN_TOLERANCE, 0},
+{599, 0u, 1319516167u, 0u, 0, ASIN_TOLERANCE, 0},
+{600, 0u, 1340013152u, 0u, 0, ASIN_TOLERANCE, 0},
+{601, 0u, 1178045349u, 0u, 0, ASIN_TOLERANCE, 0},
+{602, 0u, 999587166u, 0u, 0, ASIN_TOLERANCE, 0},
+{603, 0u, 1311927022u, 0u, 0, ASIN_TOLERANCE, 0},
+{604, 0u, 3367551312u, 0u, 0, ASIN_TOLERANCE, 0},
+{605, 0u, 1288794633u, 0u, 0, ASIN_TOLERANCE, 0},
+{606, 0u, 3187139195u, 0u, 0, ASIN_TOLERANCE, 0},
+{607, 0u, 3454228018u, 0u, 0, ASIN_TOLERANCE, 0},
+{608, 0u, 1027563924u, 0u, 0, ASIN_TOLERANCE, 0},
+{609, 0u, 1113104661u, 0u, 0, ASIN_TOLERANCE, 0},
+{610, 0u, 3245719778u, 0u, 0, ASIN_TOLERANCE, 0},
+{611, 0u, 3316389232u, 0u, 0, ASIN_TOLERANCE, 0},
+{612, 0u, 1282310126u, 0u, 0, ASIN_TOLERANCE, 0},
+{613, 0u, 1054537352u, 0u, 0, ASIN_TOLERANCE, 0},
+{614, 0u, 1030482448u, 0u, 0, ASIN_TOLERANCE, 0},
+{615, 0u, 898656161u, 0u, 0, ASIN_TOLERANCE, 0},
+{616, 0u, 3168363256u, 0u, 0, ASIN_TOLERANCE, 0},
+{617, 0u, 3100289712u, 0u, 0, ASIN_TOLERANCE, 0},
+{618, 0u, 1002569587u, 0u, 0, ASIN_TOLERANCE, 0},
+{619, 0u, 1295189320u, 0u, 0, ASIN_TOLERANCE, 0},
+{620, 0u, 3292709189u, 0u, 0, ASIN_TOLERANCE, 0},
+{621, 0u, 1154162408u, 0u, 0, ASIN_TOLERANCE, 0},
+{622, 0u, 1163075690u, 0u, 0, ASIN_TOLERANCE, 0},
+{623, 0u, 876100581u, 0u, 0, ASIN_TOLERANCE, 0},
+{624, 0u, 2992721023u, 0u, 0, ASIN_TOLERANCE, 0},
+{625, 0u, 822384047u, 0u, 0, ASIN_TOLERANCE, 0},
+{626, 0u, 1028558726u, 0u, 0, ASIN_TOLERANCE, 0},
+{627, 0u, 979448121u, 0u, 0, ASIN_TOLERANCE, 0},
+{628, 0u, 1258114435u, 0u, 0, ASIN_TOLERANCE, 0},
+{629, 0u, 3391984950u, 0u, 0, ASIN_TOLERANCE, 0},
+{630, 0u, 3106769746u, 0u, 0, ASIN_TOLERANCE, 0},
+{631, 0u, 3401317856u, 0u, 0, ASIN_TOLERANCE, 0},
+{632, 0u, 941984293u, 0u, 0, ASIN_TOLERANCE, 0},
+{633, 0u, 3104817582u, 0u, 0, ASIN_TOLERANCE, 0},
+{634, 0u, 887134496u, 0u, 0, ASIN_TOLERANCE, 0},
+{635, 0u, 3355201503u, 0u, 0, ASIN_TOLERANCE, 0},
+{636, 0u, 977588436u, 0u, 0, ASIN_TOLERANCE, 0},
+{637, 0u, 1191609115u, 0u, 0, ASIN_TOLERANCE, 0},
+{638, 0u, 1047298999u, 0u, 0, ASIN_TOLERANCE, 0},
+{639, 0u, 3483356946u, 0u, 0, ASIN_TOLERANCE, 0},
+{640, 0u, 3353529760u, 0u, 0, ASIN_TOLERANCE, 0},
+{641, 0u, 928612885u, 0u, 0, ASIN_TOLERANCE, 0},
+{642, 0u, 3162606086u, 0u, 0, ASIN_TOLERANCE, 0},
+{643, 3042097453u, 3471777274u, 3042097453u, 0, ASIN_TOLERANCE, 0},
+{644, 0u, 3202575407u, 0u, 0, ASIN_TOLERANCE, 0},
+{645, 0u, 1255148034u, 0u, 0, ASIN_TOLERANCE, 0},
+{646, 0u, 1218488455u, 0u, 0, ASIN_TOLERANCE, 0},
+{647, 0u, 1043585640u, 0u, 0, ASIN_TOLERANCE, 0},
+{648, 0u, 860904453u, 0u, 0, ASIN_TOLERANCE, 0},
+{649, 0u, 3070312723u, 0u, 0, ASIN_TOLERANCE, 0},
+{650, 0u, 3269996350u, 0u, 0, ASIN_TOLERANCE, 0},
+{651, 0u, 3451862908u, 0u, 0, ASIN_TOLERANCE, 0},
+{652, 0u, 3159551767u, 0u, 0, ASIN_TOLERANCE, 0},
+{653, 0u, 3150026558u, 0u, 0, ASIN_TOLERANCE, 0},
+{654, 0u, 3018474595u, 0u, 0, ASIN_TOLERANCE, 0},
+{655, 0u, 3092228268u, 0u, 0, ASIN_TOLERANCE, 0},
+{656, 0u, 3177295669u, 0u, 0, ASIN_TOLERANCE, 0},
+{657, 0u, 1281912088u, 0u, 0, ASIN_TOLERANCE, 0},
+{658, 0u, 1011694414u, 0u, 0, ASIN_TOLERANCE, 0},
+{659, 0u, 3017590098u, 0u, 0, ASIN_TOLERANCE, 0},
+{660, 0u, 932275550u, 0u, 0, ASIN_TOLERANCE, 0},
+{661, 0u, 925977317u, 0u, 0, ASIN_TOLERANCE, 0},
+{662, 0u, 3172338958u, 0u, 0, ASIN_TOLERANCE, 0},
+{663, 0u, 950074301u, 0u, 0, ASIN_TOLERANCE, 0},
+{664, 0u, 1031925638u, 0u, 0, ASIN_TOLERANCE, 0},
+{665, 0u, 3234909547u, 0u, 0, ASIN_TOLERANCE, 0},
+{666, 0u, 1309726409u, 0u, 0, ASIN_TOLERANCE, 0},
+{667, 0u, 2975716887u, 0u, 0, ASIN_TOLERANCE, 0},
+{668, 0u, 3070622494u, 0u, 0, ASIN_TOLERANCE, 0},
+{669, 3097616807u, 1185177793u, 3097616807u, 0, ASIN_TOLERANCE, 0},
+{670, 0u, 1086032676u, 0u, 0, ASIN_TOLERANCE, 0},
+{671, 0u, 3143814681u, 0u, 0, ASIN_TOLERANCE, 0},
+{672, 0u, 3071087132u, 0u, 0, ASIN_TOLERANCE, 0},
+{673, 0u, 868114980u, 0u, 0, ASIN_TOLERANCE, 0},
+{674, 0u, 1082239587u, 0u, 0, ASIN_TOLERANCE, 0},
+{675, 928394985u, 3470455863u, 928394985u, 0, ASIN_TOLERANCE, 0},
+{676, 0u, 3038104593u, 0u, 0, ASIN_TOLERANCE, 0},
+{677, 0u, 3266487747u, 0u, 0, ASIN_TOLERANCE, 0},
+{678, 0u, 931954492u, 0u, 0, ASIN_TOLERANCE, 0},
+{679, 0u, 845877036u, 0u, 0, ASIN_TOLERANCE, 0},
+{680, 0u, 3361912856u, 0u, 0, ASIN_TOLERANCE, 0},
+{681, 0u, 1288217553u, 0u, 0, ASIN_TOLERANCE, 0},
+{682, 994042498u, 1228207362u, 994042516u, 0, ASIN_TOLERANCE, 0},
+{683, 3026246945u, 3323646643u, 3026246945u, 0, ASIN_TOLERANCE, 0},
+{684, 0u, 931002785u, 0u, 0, ASIN_TOLERANCE, 0},
+{685, 0u, 852275082u, 0u, 0, ASIN_TOLERANCE, 0},
+{686, 0u, 3208517087u, 0u, 0, ASIN_TOLERANCE, 0},
+{687, 0u, 950619617u, 0u, 0, ASIN_TOLERANCE, 0},
+{688, 0u, 3062617950u, 0u, 0, ASIN_TOLERANCE, 0},
+{689, 0u, 2954695230u, 0u, 0, ASIN_TOLERANCE, 0},
+{690, 0u, 1249768800u, 0u, 0, ASIN_TOLERANCE, 0},
+{691, 0u, 3430381004u, 0u, 0, ASIN_TOLERANCE, 0},
+{692, 0u, 3468526321u, 0u, 0, ASIN_TOLERANCE, 0},
+{693, 0u, 3314169584u, 0u, 0, ASIN_TOLERANCE, 0},
+{694, 0u, 1252586244u, 0u, 0, ASIN_TOLERANCE, 0},
+{695, 0u, 807089907u, 0u, 0, ASIN_TOLERANCE, 0},
+{696, 0u, 1273960227u, 0u, 0, ASIN_TOLERANCE, 0},
+{697, 0u, 847765686u, 0u, 0, ASIN_TOLERANCE, 0},
+{698, 0u, 925967342u, 0u, 0, ASIN_TOLERANCE, 0},
+{699, 0u, 1232375752u, 0u, 0, ASIN_TOLERANCE, 0},
+{700, 0u, 1315058051u, 0u, 0, ASIN_TOLERANCE, 0},
+{701, 0u, 1134517149u, 0u, 0, ASIN_TOLERANCE, 0},
+{702, 0u, 1277946299u, 0u, 0, ASIN_TOLERANCE, 0},
+{703, 0u, 1071856519u, 0u, 0, ASIN_TOLERANCE, 0},
+{704, 0u, 1146993272u, 0u, 0, ASIN_TOLERANCE, 0},
+{705, 0u, 3474395292u, 0u, 0, ASIN_TOLERANCE, 0},
+{706, 0u, 3483908964u, 0u, 0, ASIN_TOLERANCE, 0},
+{707, 951674212u, 815317784u, 951674212u, 0, ASIN_TOLERANCE, 0},
+{708, 0u, 865935606u, 0u, 0, ASIN_TOLERANCE, 0},
+{709, 0u, 1318415694u, 0u, 0, ASIN_TOLERANCE, 0},
+{710, 0u, 880973446u, 0u, 0, ASIN_TOLERANCE, 0},
+{711, 0u, 949780485u, 0u, 0, ASIN_TOLERANCE, 0},
+{712, 0u, 986578339u, 0u, 0, ASIN_TOLERANCE, 0},
+{713, 0u, 3045907993u, 0u, 0, ASIN_TOLERANCE, 0},
+{714, 0u, 3092473439u, 0u, 0, ASIN_TOLERANCE, 0},
+{715, 0u, 1284508208u, 0u, 0, ASIN_TOLERANCE, 0},
+{716, 0u, 845285114u, 0u, 0, ASIN_TOLERANCE, 0},
+{717, 0u, 3251252972u, 0u, 0, ASIN_TOLERANCE, 0},
+{718, 0u, 3057474479u, 0u, 0, ASIN_TOLERANCE, 0},
+{719, 0u, 1335933001u, 0u, 0, ASIN_TOLERANCE, 0},
+{720, 0u, 843284752u, 0u, 0, ASIN_TOLERANCE, 0},
+{721, 0u, 3431817697u, 0u, 0, ASIN_TOLERANCE, 0},
+{722, 0u, 3245903485u, 0u, 0, ASIN_TOLERANCE, 0},
+{723, 0u, 1173153950u, 0u, 0, ASIN_TOLERANCE, 0},
+{724, 0u, 919202446u, 0u, 0, ASIN_TOLERANCE, 0},
+{725, 0u, 3274909610u, 0u, 0, ASIN_TOLERANCE, 0},
+{726, 0u, 913211241u, 0u, 0, ASIN_TOLERANCE, 0},
+{727, 0u, 994489862u, 0u, 0, ASIN_TOLERANCE, 0},
+{728, 0u, 1157022610u, 0u, 0, ASIN_TOLERANCE, 0},
+{729, 0u, 2962468497u, 0u, 0, ASIN_TOLERANCE, 0},
+{730, 0u, 3371554093u, 0u, 0, ASIN_TOLERANCE, 0},
+{731, 0u, 3188178213u, 0u, 0, ASIN_TOLERANCE, 0},
+{732, 0u, 860714230u, 0u, 0, ASIN_TOLERANCE, 0},
+{733, 0u, 3031764695u, 0u, 0, ASIN_TOLERANCE, 0},
+{734, 0u, 3438580893u, 0u, 0, ASIN_TOLERANCE, 0},
+{735, 0u, 1174324978u, 0u, 0, ASIN_TOLERANCE, 0},
+{736, 0u, 3489323653u, 0u, 0, ASIN_TOLERANCE, 0},
+{737, 0u, 3302139250u, 0u, 0, ASIN_TOLERANCE, 0},
+{738, 0u, 808328507u, 0u, 0, ASIN_TOLERANCE, 0},
+{739, 0u, 1030880169u, 0u, 0, ASIN_TOLERANCE, 0},
+{740, 0u, 831593944u, 0u, 0, ASIN_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_ASIN_H multiple inclusion protection
+
+// EOF asin.h
diff --git a/packages/language/c/libm/current/tests/vectors/asinhf.c b/packages/language/c/libm/current/tests/vectors/asinhf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/asinhf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      asin.c
+//
+//      Test of asin() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_double_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/asinhf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(asinhf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &asinhf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &asinhf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("asinhf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("asinhf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library asinhf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "asinhf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF asin.c
diff --git a/packages/language/c/libm/current/tests/vectors/asinhf.h b/packages/language/c/libm/current/tests/vectors/asinhf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/asinhf.h
@@ -0,0 +1,364 @@
+#ifndef CYGONCE_LIBM_ASINH_H
+#define CYGONCE_LIBM_ASINH_H
+//===========================================================================
+//
+//      asinh.h
+//
+//      Test vectors for testing of asinh() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/asinh.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define ASINH_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t asinhf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 2147495668u, 3212970857u, 0, ASINH_TOLERANCE, 0},
+{1, 3214430700u, 2147495668u, 3212917021u, 0, ASINH_TOLERANCE, 0},
+{2, 3214346813u, 2147495668u, 3212862920u, 0, ASINH_TOLERANCE, 0},
+{3, 3214262927u, 2147495668u, 3212780240u, 0, ASINH_TOLERANCE, 0},
+{4, 3214179041u, 2147495668u, 3212670966u, 0, ASINH_TOLERANCE, 0},
+{5, 3214095155u, 2147495668u, 3212561149u, 0, ASINH_TOLERANCE, 0},
+{6, 3214011269u, 2147495668u, 3212450788u, 0, ASINH_TOLERANCE, 0},
+{7, 3213927383u, 2147495668u, 3212339878u, 0, ASINH_TOLERANCE, 0},
+{8, 3213843497u, 2147495668u, 3212228416u, 0, ASINH_TOLERANCE, 0},
+{9, 3213759611u, 2147495668u, 3212116399u, 0, ASINH_TOLERANCE, 0},
+{10, 3213675725u, 2147495668u, 3212003823u, 0, ASINH_TOLERANCE, 0},
+{11, 3213591839u, 2147495668u, 3211890687u, 0, ASINH_TOLERANCE, 0},
+{12, 3213507953u, 2147495668u, 3211776985u, 0, ASINH_TOLERANCE, 0},
+{13, 3213424067u, 2147495668u, 3211662714u, 0, ASINH_TOLERANCE, 0},
+{14, 3213340180u, 2147495668u, 3211547871u, 0, ASINH_TOLERANCE, 0},
+{15, 3213256294u, 2147495668u, 3211432455u, 0, ASINH_TOLERANCE, 0},
+{16, 3213172408u, 2147495668u, 3211316461u, 0, ASINH_TOLERANCE, 0},
+{17, 3213088522u, 2147495668u, 3211199885u, 0, ASINH_TOLERANCE, 0},
+{18, 3213004636u, 2147495668u, 3211082726u, 0, ASINH_TOLERANCE, 0},
+{19, 3212920750u, 2147495668u, 3210964979u, 0, ASINH_TOLERANCE, 0},
+{20, 3212836864u, 2147495668u, 3210846643u, 0, ASINH_TOLERANCE, 0},
+{21, 3212669092u, 2147495668u, 3210727713u, 0, ASINH_TOLERANCE, 0},
+{22, 3212501320u, 2147495668u, 3210608188u, 0, ASINH_TOLERANCE, 0},
+{23, 3212333548u, 2147495668u, 3210488062u, 0, ASINH_TOLERANCE, 0},
+{24, 3212165775u, 2147495668u, 3210367335u, 0, ASINH_TOLERANCE, 0},
+{25, 3211998003u, 2147495668u, 3210246003u, 0, ASINH_TOLERANCE, 0},
+{26, 3211830231u, 2147495668u, 3210124064u, 0, ASINH_TOLERANCE, 0},
+{27, 3211662459u, 2147495668u, 3210001516u, 0, ASINH_TOLERANCE, 0},
+{28, 3211494687u, 2147495668u, 3209878354u, 0, ASINH_TOLERANCE, 0},
+{29, 3211326915u, 2147495668u, 3209754578u, 0, ASINH_TOLERANCE, 0},
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+{246, 1078530011u, 2147495668u, 1072586677u, 0, ASINH_TOLERANCE, 0},
+{247, 1083624420u, 2147495668u, 1074808916u, 0, ASINH_TOLERANCE, 0},
+{248, 3253731328u, 2147495668u, 3229812517u, 0, ASINH_TOLERANCE, 0},
+{249, 3252840038u, 2147495668u, 3229690251u, 0, ASINH_TOLERANCE, 0},
+{250, 3251948749u, 2147495668u, 3229506754u, 0, ASINH_TOLERANCE, 0},
+{251, 3251057459u, 2147495668u, 3229229957u, 0, ASINH_TOLERANCE, 0},
+{252, 3250166170u, 2147495668u, 3228933611u, 0, ASINH_TOLERANCE, 0},
+{253, 3249274880u, 2147495668u, 3228614747u, 0, ASINH_TOLERANCE, 0},
+{254, 3248383590u, 2147495668u, 3228269663u, 0, ASINH_TOLERANCE, 0},
+{255, 3247492301u, 2147495668u, 3227893666u, 0, ASINH_TOLERANCE, 0},
+{256, 3246601011u, 2147495668u, 3227480676u, 0, ASINH_TOLERANCE, 0},
+{257, 3245028147u, 2147495668u, 3227022627u, 0, ASINH_TOLERANCE, 0},
+{258, 3243245568u, 2147495668u, 3226508502u, 0, ASINH_TOLERANCE, 0},
+{259, 3241462989u, 2147495668u, 3225922682u, 0, ASINH_TOLERANCE, 0},
+{260, 3239680410u, 2147495668u, 3225241988u, 0, ASINH_TOLERANCE, 0},
+{261, 3237792973u, 2147495668u, 3224429886u, 0, ASINH_TOLERANCE, 0},
+{262, 3234227814u, 2147495668u, 3223423864u, 0, ASINH_TOLERANCE, 0},
+{263, 3230662656u, 2147495668u, 3222103540u, 0, ASINH_TOLERANCE, 0},
+{264, 3224580915u, 2147495668u, 3219155405u, 0, ASINH_TOLERANCE, 0},
+{265, 3213675725u, 2147495668u, 3212003823u, 0, ASINH_TOLERANCE, 0},
+{266, 1058642330u, 2147495668u, 1058119298u, 0, ASINH_TOLERANCE, 0},
+{267, 1075000115u, 2147495668u, 1070137059u, 0, ASINH_TOLERANCE, 0},
+{268, 1082130432u, 2147495668u, 1074139077u, 0, ASINH_TOLERANCE, 0},
+{269, 1085695590u, 2147495668u, 1075592438u, 0, ASINH_TOLERANCE, 0},
+{270, 1089260749u, 2147495668u, 1076674320u, 0, ASINH_TOLERANCE, 0},
+{271, 1091672474u, 2147495668u, 1077535266u, 0, ASINH_TOLERANCE, 0},
+{272, 1093455053u, 2147495668u, 1078249987u, 0, ASINH_TOLERANCE, 0},
+{273, 1095237632u, 2147495668u, 1078860855u, 0, ASINH_TOLERANCE, 0},
+{274, 1097020211u, 2147495668u, 1079394180u, 0, ASINH_TOLERANCE, 0},
+{275, 1098802790u, 2147495668u, 1079867411u, 0, ASINH_TOLERANCE, 0},
+{276, 1099746509u, 2147495668u, 1080292707u, 0, ASINH_TOLERANCE, 0},
+{277, 1100637798u, 2147495668u, 1080678879u, 0, ASINH_TOLERANCE, 0},
+{278, 1101529088u, 2147495668u, 1081032514u, 0, ASINH_TOLERANCE, 0},
+{279, 1102420378u, 2147495668u, 1081358667u, 0, ASINH_TOLERANCE, 0},
+{280, 1103311667u, 2147495668u, 1081661299u, 0, ASINH_TOLERANCE, 0},
+{281, 1104202957u, 2147495668u, 1081943573u, 0, ASINH_TOLERANCE, 0},
+{282, 1105094246u, 2147495668u, 1082169243u, 0, ASINH_TOLERANCE, 0},
+{283, 1105985536u, 2147495668u, 1082293642u, 0, ASINH_TOLERANCE, 0},
+{284, 0u, 2147495668u, 0u, 0, ASINH_TOLERANCE, 0},
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_ASINH_H multiple inclusion protection
+
+// EOF asinh.h
diff --git a/packages/language/c/libm/current/tests/vectors/atan2f.c b/packages/language/c/libm/current/tests/vectors/atan2f.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/atan2f.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      atan2f.c
+//
+//      Test of atan2f() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/atan2f.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(atan2f_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &atan2f, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_FLOAT, CYG_LIBM_TEST_VEC_FLOAT,
+                     &atan2f_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("atan2f() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("atan2f() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library atan2f() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "atan2f() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF atan2f.c
diff --git a/packages/language/c/libm/current/tests/vectors/atan2f.h b/packages/language/c/libm/current/tests/vectors/atan2f.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/atan2f.h
@@ -0,0 +1,2294 @@
+#ifndef CYGONCE_LIBM_ATAN2_H
+#define CYGONCE_LIBM_ATAN2_H
+//===========================================================================
+//
+//      atan2f.h
+//
+//      Test vectors for testing of atan2f() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/atan2f.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define ATAN2_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t atan2f_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3212836864u, 3212836864u, 3222719460u, 0, ATAN2_TOLERANCE, 0},
+{1, 3212836864u, 3211998003u, 3222611937u, 0, ATAN2_TOLERANCE, 0},
+{2, 3212836864u, 3211159142u, 3222498911u, 0, ATAN2_TOLERANCE, 0},
+{3, 3212836864u, 3210320282u, 3222380124u, 0, ATAN2_TOLERANCE, 0},
+{4, 3212836864u, 3209481421u, 3222255330u, 0, ATAN2_TOLERANCE, 0},
+{5, 3212836864u, 3208642560u, 3222124301u, 0, ATAN2_TOLERANCE, 0},
+{6, 3212836864u, 3207803699u, 3221986832u, 0, ATAN2_TOLERANCE, 0},
+{7, 3212836864u, 3206964838u, 3221842754u, 0, ATAN2_TOLERANCE, 0},
+{8, 3212836864u, 3206125978u, 3221691945u, 0, ATAN2_TOLERANCE, 0},
+{9, 3212836864u, 3205287117u, 3221534339u, 0, ATAN2_TOLERANCE, 0},
+{10, 3212836864u, 3204448256u, 3221369940u, 0, ATAN2_TOLERANCE, 0},
+{11, 3212836864u, 3202770534u, 3221172206u, 0, ATAN2_TOLERANCE, 0},
+{12, 3212836864u, 3201092813u, 3220816969u, 0, ATAN2_TOLERANCE, 0},
+{13, 3212836864u, 3199415091u, 3220449284u, 0, ATAN2_TOLERANCE, 0},
+{14, 3212836864u, 3197737370u, 3220069967u, 0, ATAN2_TOLERANCE, 0},
+{15, 3212836864u, 3196059648u, 3219680081u, 0, ATAN2_TOLERANCE, 0},
+{16, 3212836864u, 3192704205u, 3219280925u, 0, ATAN2_TOLERANCE, 0},
+{17, 3212836864u, 3189348762u, 3218874030u, 0, ATAN2_TOLERANCE, 0},
+{18, 3212836864u, 3184315597u, 3218461132u, 0, ATAN2_TOLERANCE, 0},
+{19, 3212836864u, 3175926989u, 3218044132u, 0, ATAN2_TOLERANCE, 0},
+{20, 3212836864u, 1028443341u, 3217205969u, 0, ATAN2_TOLERANCE, 0},
+{21, 3212836864u, 1036831949u, 3216788969u, 0, ATAN2_TOLERANCE, 0},
+{22, 3212836864u, 1041865114u, 3216376071u, 0, ATAN2_TOLERANCE, 0},
+{23, 3212836864u, 1045220557u, 3215969177u, 0, ATAN2_TOLERANCE, 0},
+{24, 3212836864u, 1048576000u, 3215570021u, 0, ATAN2_TOLERANCE, 0},
+{25, 3212836864u, 1050253722u, 3215180134u, 0, ATAN2_TOLERANCE, 0},
+{26, 3212836864u, 1051931443u, 3214800818u, 0, ATAN2_TOLERANCE, 0},
+{27, 3212836864u, 1053609165u, 3214433132u, 0, ATAN2_TOLERANCE, 0},
+{28, 3212836864u, 1055286886u, 3214077895u, 0, ATAN2_TOLERANCE, 0},
+{29, 3212836864u, 1056964608u, 3213735693u, 0, ATAN2_TOLERANCE, 0},
+{30, 3212836864u, 1057803469u, 3213406896u, 0, ATAN2_TOLERANCE, 0},
+{31, 3212836864u, 1058642330u, 3213091683u, 0, ATAN2_TOLERANCE, 0},
+{32, 3212836864u, 1059481190u, 3212743266u, 0, ATAN2_TOLERANCE, 0},
+{33, 3212836864u, 1060320051u, 3212166956u, 0, ATAN2_TOLERANCE, 0},
+{34, 3212836864u, 1061158912u, 3211617080u, 0, ATAN2_TOLERANCE, 0},
+{35, 3212836864u, 1061997773u, 3211092963u, 0, ATAN2_TOLERANCE, 0},
+{36, 3212836864u, 1062836634u, 3210593788u, 0, ATAN2_TOLERANCE, 0},
+{37, 3212836864u, 1063675494u, 3210118640u, 0, ATAN2_TOLERANCE, 0},
+{38, 3212836864u, 1064514355u, 3209666533u, 0, ATAN2_TOLERANCE, 0},
+{39, 3211998003u, 3212836864u, 3222826983u, 0, ATAN2_TOLERANCE, 0},
+{40, 3211998003u, 3211998003u, 3222719460u, 0, ATAN2_TOLERANCE, 0},
+{41, 3211998003u, 3211159142u, 3222606128u, 0, ATAN2_TOLERANCE, 0},
+{42, 3211998003u, 3210320282u, 3222486682u, 0, ATAN2_TOLERANCE, 0},
+{43, 3211998003u, 3209481421u, 3222360825u, 0, ATAN2_TOLERANCE, 0},
+{44, 3211998003u, 3208642560u, 3222228270u, 0, ATAN2_TOLERANCE, 0},
+{45, 3211998003u, 3207803699u, 3222088756u, 0, ATAN2_TOLERANCE, 0},
+{46, 3211998003u, 3206964838u, 3221942054u, 0, ATAN2_TOLERANCE, 0},
+{47, 3211998003u, 3206125978u, 3221787981u, 0, ATAN2_TOLERANCE, 0},
+{48, 3211998003u, 3205287117u, 3221626414u, 0, ATAN2_TOLERANCE, 0},
+{49, 3211998003u, 3204448256u, 3221457309u, 0, ATAN2_TOLERANCE, 0},
+{50, 3211998003u, 3202770534u, 3221280713u, 0, ATAN2_TOLERANCE, 0},
+{51, 3211998003u, 3201092813u, 3220968099u, 0, ATAN2_TOLERANCE, 0},
+{52, 3211998003u, 3199415091u, 3220586149u, 0, ATAN2_TOLERANCE, 0},
+{53, 3211998003u, 3197737370u, 3220190949u, 0, ATAN2_TOLERANCE, 0},
+{54, 3211998003u, 3196059648u, 3219783638u, 0, ATAN2_TOLERANCE, 0},
+{55, 3211998003u, 3192704205u, 3219365655u, 0, ATAN2_TOLERANCE, 0},
+{56, 3211998003u, 3189348762u, 3218938722u, 0, ATAN2_TOLERANCE, 0},
+{57, 3211998003u, 3184315597u, 3218504822u, 0, ATAN2_TOLERANCE, 0},
+{58, 3211998003u, 3175926989u, 3218066149u, 0, ATAN2_TOLERANCE, 0},
+{59, 3211998003u, 1028443341u, 3217183952u, 0, ATAN2_TOLERANCE, 0},
+{60, 3211998003u, 1036831949u, 3216745279u, 0, ATAN2_TOLERANCE, 0},
+{61, 3211998003u, 1041865114u, 3216311379u, 0, ATAN2_TOLERANCE, 0},
+{62, 3211998003u, 1045220557u, 3215884446u, 0, ATAN2_TOLERANCE, 0},
+{63, 3211998003u, 1048576000u, 3215466463u, 0, ATAN2_TOLERANCE, 0},
+{64, 3211998003u, 1050253722u, 3215059153u, 0, ATAN2_TOLERANCE, 0},
+{65, 3211998003u, 1051931443u, 3214663953u, 0, ATAN2_TOLERANCE, 0},
+{66, 3211998003u, 1053609165u, 3214282002u, 0, ATAN2_TOLERANCE, 0},
+{67, 3211998003u, 1055286886u, 3213914147u, 0, ATAN2_TOLERANCE, 0},
+{68, 3211998003u, 1056964608u, 3213560955u, 0, ATAN2_TOLERANCE, 0},
+{69, 3211998003u, 1057803469u, 3213222745u, 0, ATAN2_TOLERANCE, 0},
+{70, 3211998003u, 1058642330u, 3212899611u, 0, ATAN2_TOLERANCE, 0},
+{71, 3211998003u, 1059481190u, 3212346065u, 0, ATAN2_TOLERANCE, 0},
+{72, 3211998003u, 1060320051u, 3211759257u, 0, ATAN2_TOLERANCE, 0},
+{73, 3211998003u, 1061158912u, 3211201201u, 0, ATAN2_TOLERANCE, 0},
+{74, 3211998003u, 1061997773u, 3210670983u, 0, ATAN2_TOLERANCE, 0},
+{75, 3211998003u, 1062836634u, 3210167553u, 0, ATAN2_TOLERANCE, 0},
+{76, 3211998003u, 1063675494u, 3209689771u, 0, ATAN2_TOLERANCE, 0},
+{77, 3211998003u, 1064514355u, 3209236443u, 0, ATAN2_TOLERANCE, 0},
+{78, 3211159142u, 3212836864u, 3222940009u, 0, ATAN2_TOLERANCE, 0},
+{79, 3211159142u, 3211998003u, 3222832792u, 0, ATAN2_TOLERANCE, 0},
+{80, 3211159142u, 3211159142u, 3222719460u, 0, ATAN2_TOLERANCE, 0},
+{81, 3211159142u, 3210320282u, 3222599655u, 0, ATAN2_TOLERANCE, 0},
+{82, 3211159142u, 3209481421u, 3222473020u, 0, ATAN2_TOLERANCE, 0},
+{83, 3211159142u, 3208642560u, 3222339205u, 0, ATAN2_TOLERANCE, 0},
+{84, 3211159142u, 3207803699u, 3222197877u, 0, ATAN2_TOLERANCE, 0},
+{85, 3211159142u, 3206964838u, 3222048736u, 0, ATAN2_TOLERANCE, 0},
+{86, 3211159142u, 3206125978u, 3221891523u, 0, ATAN2_TOLERANCE, 0},
+{87, 3211159142u, 3205287117u, 3221726044u, 0, ATAN2_TOLERANCE, 0},
+{88, 3211159142u, 3204448256u, 3221552187u, 0, ATAN2_TOLERANCE, 0},
+{89, 3211159142u, 3202770534u, 3221369940u, 0, ATAN2_TOLERANCE, 0},
+{90, 3211159142u, 3201092813u, 3221133371u, 0, ATAN2_TOLERANCE, 0},
+{91, 3211159142u, 3199415091u, 3220736312u, 0, ATAN2_TOLERANCE, 0},
+{92, 3211159142u, 3197737370u, 3220324090u, 0, ATAN2_TOLERANCE, 0},
+{93, 3211159142u, 3196059648u, 3219897918u, 0, ATAN2_TOLERANCE, 0},
+{94, 3211159142u, 3192704205u, 3219459379u, 0, ATAN2_TOLERANCE, 0},
+{95, 3211159142u, 3189348762u, 3219010418u, 0, ATAN2_TOLERANCE, 0},
+{96, 3211159142u, 3184315597u, 3218553311u, 0, ATAN2_TOLERANCE, 0},
+{97, 3211159142u, 3175926989u, 3218090606u, 0, ATAN2_TOLERANCE, 0},
+{98, 3211159142u, 1028443341u, 3217159495u, 0, ATAN2_TOLERANCE, 0},
+{99, 3211159142u, 1036831949u, 3216696791u, 0, ATAN2_TOLERANCE, 0},
+{100, 3211159142u, 1041865114u, 3216239683u, 0, ATAN2_TOLERANCE, 0},
+{101, 3211159142u, 1045220557u, 3215790723u, 0, ATAN2_TOLERANCE, 0},
+{102, 3211159142u, 1048576000u, 3215352184u, 0, ATAN2_TOLERANCE, 0},
+{103, 3211159142u, 1050253722u, 3214926011u, 0, ATAN2_TOLERANCE, 0},
+{104, 3211159142u, 1051931443u, 3214513789u, 0, ATAN2_TOLERANCE, 0},
+{105, 3211159142u, 1053609165u, 3214116731u, 0, ATAN2_TOLERANCE, 0},
+{106, 3211159142u, 1055286886u, 3213735693u, 0, ATAN2_TOLERANCE, 0},
+{107, 3211159142u, 1056964608u, 3213371200u, 0, ATAN2_TOLERANCE, 0},
+{108, 3211159142u, 1057803469u, 3213023485u, 0, ATAN2_TOLERANCE, 0},
+{109, 3211159142u, 1058642330u, 3212548191u, 0, ATAN2_TOLERANCE, 0},
+{110, 3211159142u, 1059481190u, 3211919340u, 0, ATAN2_TOLERANCE, 0},
+{111, 3211159142u, 1060320051u, 3211322773u, 0, ATAN2_TOLERANCE, 0},
+{112, 3211159142u, 1061158912u, 3210757463u, 0, ATAN2_TOLERANCE, 0},
+{113, 3211159142u, 1061997773u, 3210222202u, 0, ATAN2_TOLERANCE, 0},
+{114, 3211159142u, 1062836634u, 3209715661u, 0, ATAN2_TOLERANCE, 0},
+{115, 3211159142u, 1063675494u, 3209236443u, 0, ATAN2_TOLERANCE, 0},
+{116, 3211159142u, 1064514355u, 3208783115u, 0, ATAN2_TOLERANCE, 0},
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+{2015, 1015670780u, 1101217251u, 978863264u, 0, ATAN2_TOLERANCE, 0},
+{2016, 1012543234u, 1116520440u, 960916317u, 0, ATAN2_TOLERANCE, 0},
+{2017, 3316611992u, 3394732912u, 3226006988u, 0, ATAN2_TOLERANCE, 0},
+{2018, 1087942795u, 3316660295u, 1078524974u, 0, ATAN2_TOLERANCE, 0},
+{2019, 3426365713u, 3069778532u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2020, 3066654389u, 3443934204u, 3226013659u, 0, ATAN2_TOLERANCE, 0},
+{2021, 3295326432u, 1313396175u, 3046478811u, 0, ATAN2_TOLERANCE, 0},
+{2022, 3318835308u, 3277583511u, 3217900300u, 0, ATAN2_TOLERANCE, 0},
+{2023, 3283555717u, 891875120u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2024, 3040485181u, 3375450886u, 3226013659u, 0, ATAN2_TOLERANCE, 0},
+{2025, 3388772093u, 1032597076u, 3217625050u, 0, ATAN2_TOLERANCE, 0},
+{2026, 954670189u, 1144923689u, 874222309u, 0, ATAN2_TOLERANCE, 0},
+{2027, 1319200415u, 3387555900u, 1070153279u, 0, ATAN2_TOLERANCE, 0},
+{2028, 1279324488u, 3228401212u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2029, 3455131757u, 1260217257u, 3217453967u, 0, ATAN2_TOLERANCE, 0},
+{2030, 1246947517u, 1087951909u, 1070141386u, 0, ATAN2_TOLERANCE, 0},
+{2031, 3433761025u, 3060143904u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2032, 3201187455u, 900233172u, 3217625024u, 0, ATAN2_TOLERANCE, 0},
+{2033, 1173247961u, 1191127979u, 1047193748u, 0, ATAN2_TOLERANCE, 0},
+{2034, 3037297123u, 3346394818u, 3226013659u, 0, ATAN2_TOLERANCE, 0},
+{2035, 3083019343u, 3033309444u, 3217762483u, 0, ATAN2_TOLERANCE, 0},
+{2036, 3042018375u, 3203882372u, 3226013652u, 0, ATAN2_TOLERANCE, 0},
+{2037, 1082862511u, 3032804719u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2038, 3157626955u, 3483653298u, 3226013659u, 0, ATAN2_TOLERANCE, 0},
+{2039, 3182695954u, 3256861672u, 3226004425u, 0, ATAN2_TOLERANCE, 0},
+{2040, 1105291533u, 3482971524u, 1078530011u, 0, ATAN2_TOLERANCE, 0},
+{2041, 1016023520u, 3227712090u, 1078509325u, 0, ATAN2_TOLERANCE, 0},
+{2042, 3370691006u, 1295870514u, 3139254705u, 0, ATAN2_TOLERANCE, 0},
+{2043, 1156767169u, 1049756240u, 1070140171u, 0, ATAN2_TOLERANCE, 0},
+{2044, 3077020499u, 894671462u, 3217146564u, 0, ATAN2_TOLERANCE, 0},
+{2045, 1104284039u, 3040211914u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2046, 3335212901u, 3486414589u, 3226013643u, 0, ATAN2_TOLERANCE, 0},
+{2047, 1093697541u, 3193708441u, 1070304849u, 0, ATAN2_TOLERANCE, 0},
+{2048, 3266691185u, 1160074593u, 3171723218u, 0, ATAN2_TOLERANCE, 0},
+{2049, 3179003144u, 1108615803u, 3134817668u, 0, ATAN2_TOLERANCE, 0},
+{2050, 3424086808u, 3260140004u, 3217625062u, 0, ATAN2_TOLERANCE, 0},
+{2051, 3353608773u, 1134068114u, 3217603133u, 0, ATAN2_TOLERANCE, 0},
+{2052, 882878091u, 3136970767u, 1078529358u, 0, ATAN2_TOLERANCE, 0},
+{2053, 927582555u, 947955456u, 1044791214u, 0, ATAN2_TOLERANCE, 0},
+{2054, 3111440310u, 3067634077u, 3217856693u, 0, ATAN2_TOLERANCE, 0},
+{2055, 3476083859u, 966439623u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2056, 3038754840u, 932009686u, 3171980751u, 0, ATAN2_TOLERANCE, 0},
+{2057, 3464546616u, 3205527253u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2058, 1002542205u, 3152136093u, 1075557233u, 0, ATAN2_TOLERANCE, 0},
+{2059, 3443552129u, 3165561391u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2060, 1287620154u, 3119707283u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2061, 3073260205u, 3093124531u, 3225198660u, 0, ATAN2_TOLERANCE, 0},
+{2062, 1245702957u, 894348966u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2063, 1002715618u, 1191006977u, 877022332u, 0, ATAN2_TOLERANCE, 0},
+{2064, 3087802274u, 897541752u, 3217386213u, 0, ATAN2_TOLERANCE, 0},
+{2065, 3415763001u, 3032518431u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2066, 3283471961u, 1260093226u, 3088427057u, 0, ATAN2_TOLERANCE, 0},
+{2067, 3311210827u, 1192192264u, 3183785110u, 0, ATAN2_TOLERANCE, 0},
+{2068, 1198307901u, 1116328249u, 1070131864u, 0, ATAN2_TOLERANCE, 0},
+{2069, 1288901567u, 1296370667u, 1056686848u, 0, ATAN2_TOLERANCE, 0},
+{2070, 922255363u, 958305289u, 1028156442u, 0, ATAN2_TOLERANCE, 0},
+{2071, 1113104661u, 944376032u, 1070141395u, 0, ATAN2_TOLERANCE, 0},
+{2072, 948856035u, 1015466475u, 998717622u, 0, ATAN2_TOLERANCE, 0},
+{2073, 1062512367u, 3229559531u, 1077668471u, 0, ATAN2_TOLERANCE, 0},
+{2074, 1162027071u, 3308983387u, 1075147524u, 0, ATAN2_TOLERANCE, 0},
+{2075, 1034561811u, 1054043114u, 1045123831u, 0, ATAN2_TOLERANCE, 0},
+{2076, 3271615417u, 3209997200u, 3217679118u, 0, ATAN2_TOLERANCE, 0},
+{2077, 1042014529u, 1146708584u, 959943147u, 0, ATAN2_TOLERANCE, 0},
+{2078, 1177157787u, 3090208179u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2079, 3196144817u, 1056118717u, 3204073657u, 0, ATAN2_TOLERANCE, 0},
+{2080, 1309658335u, 1010219988u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2081, 3100289712u, 3456334210u, 3226013659u, 0, ATAN2_TOLERANCE, 0},
+{2082, 3375507013u, 1306310823u, 3134103462u, 0, ATAN2_TOLERANCE, 0},
+{2083, 3460699001u, 3096700943u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2084, 3079231719u, 1044386263u, 3099004977u, 0, ATAN2_TOLERANCE, 0},
+{2085, 3093951884u, 1014115231u, 3145159061u, 0, ATAN2_TOLERANCE, 0},
+{2086, 3468023178u, 1209565017u, 3217624192u, 0, ATAN2_TOLERANCE, 0},
+{2087, 1204196034u, 3298625731u, 1070245051u, 0, ATAN2_TOLERANCE, 0},
+{2088, 1161439847u, 943449277u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2089, 908663107u, 939489763u, 1034489716u, 0, ATAN2_TOLERANCE, 0},
+{2090, 1055319316u, 3261813492u, 1078497860u, 0, ATAN2_TOLERANCE, 0},
+{2091, 1084378658u, 1009650785u, 1070123833u, 0, ATAN2_TOLERANCE, 0},
+{2092, 3053887750u, 3341786453u, 3226013659u, 0, ATAN2_TOLERANCE, 0},
+{2093, 3022828828u, 881335251u, 3205544878u, 0, ATAN2_TOLERANCE, 0},
+{2094, 1123114742u, 1229815537u, 957765780u, 0, ATAN2_TOLERANCE, 0},
+{2095, 1258114435u, 1291336083u, 1031958809u, 0, ATAN2_TOLERANCE, 0},
+{2096, 3468040845u, 3066966245u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2097, 1178825761u, 1113195286u, 1070104853u, 0, ATAN2_TOLERANCE, 0},
+{2098, 3059266302u, 878503862u, 3217091308u, 0, ATAN2_TOLERANCE, 0},
+{2099, 3223384012u, 1130486973u, 3157682004u, 0, ATAN2_TOLERANCE, 0},
+{2100, 3445262427u, 3465211174u, 3225199336u, 0, ATAN2_TOLERANCE, 0},
+{2101, 1125653081u, 1207799746u, 983142602u, 0, ATAN2_TOLERANCE, 0},
+{2102, 3337652712u, 3025581813u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2103, 1184753508u, 3147374485u, 1070141405u, 0, ATAN2_TOLERANCE, 0},
+{2104, 996404791u, 3353251979u, 1078530011u, 0, ATAN2_TOLERANCE, 0},
+{2105, 1188439315u, 1113484271u, 1070124385u, 0, ATAN2_TOLERANCE, 0},
+{2106, 916831283u, 999465787u, 982559633u, 0, ATAN2_TOLERANCE, 0},
+{2107, 996786317u, 3179221951u, 1078290045u, 0, ATAN2_TOLERANCE, 0},
+{2108, 3461635065u, 1004690387u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2109, 1188167943u, 1200744896u, 1051776672u, 0, ATAN2_TOLERANCE, 0},
+{2110, 1102061604u, 3424449935u, 1078530008u, 0, ATAN2_TOLERANCE, 0},
+{2111, 1282351521u, 3039376424u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2112, 3458861065u, 3392466405u, 3217659919u, 0, ATAN2_TOLERANCE, 0},
+{2113, 3095256878u, 1023623326u, 3136787620u, 0, ATAN2_TOLERANCE, 0},
+{2114, 3422194733u, 893873945u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2115, 3083885296u, 974543672u, 3174122414u, 0, ATAN2_TOLERANCE, 0},
+{2116, 1261940623u, 3402349985u, 1074065444u, 0, ATAN2_TOLERANCE, 0},
+{2117, 3400603081u, 3234396843u, 3217625060u, 0, ATAN2_TOLERANCE, 0},
+{2118, 3139250800u, 3079109479u, 3217681544u, 0, ATAN2_TOLERANCE, 0},
+{2119, 886201503u, 3272760705u, 1078530011u, 0, ATAN2_TOLERANCE, 0},
+{2120, 3297366026u, 1089966380u, 3217566187u, 0, ATAN2_TOLERANCE, 0},
+{2121, 1218488455u, 3309646450u, 1070221841u, 0, ATAN2_TOLERANCE, 0},
+{2122, 3040358923u, 3093401553u, 3225960144u, 0, ATAN2_TOLERANCE, 0},
+{2123, 1283938137u, 1196383822u, 1070135127u, 0, ATAN2_TOLERANCE, 0},
+{2124, 3182551696u, 3029982441u, 3217625078u, 0, ATAN2_TOLERANCE, 0},
+{2125, 1317098613u, 949986176u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2126, 3116209179u, 3303588342u, 3226013658u, 0, ATAN2_TOLERANCE, 0},
+{2127, 3239728775u, 927815421u, 3217625040u, 0, ATAN2_TOLERANCE, 0},
+{2128, 3207141672u, 933456504u, 3217624803u, 0, ATAN2_TOLERANCE, 0},
+{2129, 3154378805u, 905462392u, 3217623125u, 0, ATAN2_TOLERANCE, 0},
+{2130, 3069658155u, 1041452042u, 3092701021u, 0, ATAN2_TOLERANCE, 0},
+{2131, 3207056527u, 3384206601u, 3226013657u, 0, ATAN2_TOLERANCE, 0},
+{2132, 1284174954u, 3436881197u, 1076155477u, 0, ATAN2_TOLERANCE, 0},
+{2133, 3156081645u, 3308839704u, 3226013645u, 0, ATAN2_TOLERANCE, 0},
+{2134, 1063693032u, 976661408u, 1070134915u, 0, ATAN2_TOLERANCE, 0},
+{2135, 1102631663u, 3396951425u, 1078529987u, 0, ATAN2_TOLERANCE, 0},
+{2136, 968803479u, 992989712u, 1040845349u, 0, ATAN2_TOLERANCE, 0},
+{2137, 3273080388u, 3109405906u, 3217625062u, 0, ATAN2_TOLERANCE, 0},
+{2138, 1172529774u, 3294550127u, 1071163952u, 0, ATAN2_TOLERANCE, 0},
+{2139, 1306695905u, 1292690378u, 1067612994u, 0, ATAN2_TOLERANCE, 0},
+{2140, 3158855023u, 3151283866u, 3221473110u, 0, ATAN2_TOLERANCE, 0},
+{2141, 1165177679u, 3276237026u, 1070570911u, 0, ATAN2_TOLERANCE, 0},
+{2142, 3403009513u, 3381966453u, 3219069294u, 0, ATAN2_TOLERANCE, 0},
+{2143, 952348506u, 3377573987u, 1078530011u, 0, ATAN2_TOLERANCE, 0},
+{2144, 1222777442u, 1125769920u, 1070138615u, 0, ATAN2_TOLERANCE, 0},
+{2145, 1325324763u, 978336043u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2146, 3363524213u, 3202991311u, 3217625066u, 0, ATAN2_TOLERANCE, 0},
+{2147, 1158950321u, 1073578913u, 1070134395u, 0, ATAN2_TOLERANCE, 0},
+{2148, 903129873u, 3416864271u, 1078530011u, 0, ATAN2_TOLERANCE, 0},
+{2149, 3078339944u, 988173985u, 3154895797u, 0, ATAN2_TOLERANCE, 0},
+{2150, 1208345407u, 1254181270u, 1018252503u, 0, ATAN2_TOLERANCE, 0},
+{2151, 1258634105u, 1247426200u, 1066881297u, 0, ATAN2_TOLERANCE, 0},
+{2152, 1248478509u, 1287895126u, 1025057766u, 0, ATAN2_TOLERANCE, 0},
+{2153, 1153863988u, 3430539165u, 1078529909u, 0, ATAN2_TOLERANCE, 0},
+{2154, 1097120930u, 3221726305u, 1071376032u, 0, ATAN2_TOLERANCE, 0},
+{2155, 3469778622u, 1200179013u, 3217624714u, 0, ATAN2_TOLERANCE, 0},
+{2156, 1147712200u, 931865525u, 1070141402u, 0, ATAN2_TOLERANCE, 0},
+{2157, 1124721745u, 3058969650u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2158, 3261744304u, 1043806501u, 3217599423u, 0, ATAN2_TOLERANCE, 0},
+{2159, 3303160152u, 3075455322u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2160, 1315090496u, 3269683237u, 1070141404u, 0, ATAN2_TOLERANCE, 0},
+{2161, 1335399673u, 974138676u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2162, 1072458508u, 3372833993u, 1078529997u, 0, ATAN2_TOLERANCE, 0},
+{2163, 3252139741u, 1059615003u, 3217420395u, 0, ATAN2_TOLERANCE, 0},
+{2164, 3468519966u, 3113982619u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2165, 1006231203u, 897530770u, 1070140357u, 0, ATAN2_TOLERANCE, 0},
+{2166, 951554138u, 1001144381u, 1015571681u, 0, ATAN2_TOLERANCE, 0},
+{2167, 942046828u, 986341002u, 1020432919u, 0, ATAN2_TOLERANCE, 0},
+{2168, 3319723279u, 3414482416u, 3226011940u, 0, ATAN2_TOLERANCE, 0},
+{2169, 3255104167u, 928827688u, 3217625047u, 0, ATAN2_TOLERANCE, 0},
+{2170, 1155477903u, 3104812800u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2171, 3273889176u, 980486479u, 3217625003u, 0, ATAN2_TOLERANCE, 0},
+{2172, 3237813668u, 3441016803u, 3226013658u, 0, ATAN2_TOLERANCE, 0},
+{2173, 981908840u, 3314038398u, 1078530010u, 0, ATAN2_TOLERANCE, 0},
+{2174, 941187647u, 1107765599u, 898711988u, 0, ATAN2_TOLERANCE, 0},
+{2175, 1214223128u, 3225536822u, 1070141514u, 0, ATAN2_TOLERANCE, 0},
+{2176, 3422922584u, 1086391131u, 3217625049u, 0, ATAN2_TOLERANCE, 0},
+{2177, 1315857601u, 3487600045u, 1077976642u, 0, ATAN2_TOLERANCE, 0},
+{2178, 3453226030u, 3233768835u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2179, 1078359574u, 3199175230u, 1071065122u, 0, ATAN2_TOLERANCE, 0},
+{2180, 1029557624u, 3302959071u, 1078529883u, 0, ATAN2_TOLERANCE, 0},
+{2181, 1207675424u, 3042692550u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2182, 1028355074u, 3442294040u, 1078530011u, 0, ATAN2_TOLERANCE, 0},
+{2183, 1248421894u, 3367769132u, 1070983505u, 0, ATAN2_TOLERANCE, 0},
+{2184, 3353251994u, 1095517730u, 3217624111u, 0, ATAN2_TOLERANCE, 0},
+{2185, 876926659u, 3288089977u, 1078530011u, 0, ATAN2_TOLERANCE, 0},
+{2186, 1076752219u, 876236939u, 1070141402u, 0, ATAN2_TOLERANCE, 0},
+{2187, 1273395082u, 3031189261u, 1070141403u, 0, ATAN2_TOLERANCE, 0},
+{2188, 3385588183u, 3258252464u, 3217625278u, 0, ATAN2_TOLERANCE, 0},
+{2189, 3192315328u, 3289489214u, 3226012260u, 0, ATAN2_TOLERANCE, 0},
+{2190, 3441804648u, 3274638356u, 3217625059u, 0, ATAN2_TOLERANCE, 0},
+{2191, 3392827417u, 1277961150u, 3179965369u, 0, ATAN2_TOLERANCE, 0},
+{2192, 1161241793u, 1328003707u, 898352014u, 0, ATAN2_TOLERANCE, 0},
+{2193, 3034494183u, 3041579130u, 3223907672u, 0, ATAN2_TOLERANCE, 0},
+{2194, 1171318485u, 3374409104u, 1078487599u, 0, ATAN2_TOLERANCE, 0},
+{2195, 1001216371u, 3052357038u, 1070144229u, 0, ATAN2_TOLERANCE, 0},
+{2196, 912515889u, 1074635609u, 902689232u, 0, ATAN2_TOLERANCE, 0},
+{2197, 3391452505u, 897989232u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2198, 3249603369u, 3147662248u, 3217626873u, 0, ATAN2_TOLERANCE, 0},
+{2199, 3169816394u, 988430929u, 3217113000u, 0, ATAN2_TOLERANCE, 0},
+{2200, 3282212423u, 3174079140u, 3217626163u, 0, ATAN2_TOLERANCE, 0},
+{2201, 3352293320u, 3247843425u, 3217626530u, 0, ATAN2_TOLERANCE, 0},
+{2202, 3296358441u, 875645354u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2203, 1197828352u, 3245614728u, 1070143582u, 0, ATAN2_TOLERANCE, 0},
+{2204, 3340510371u, 914930263u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2205, 1127109339u, 3368125489u, 1078528166u, 0, ATAN2_TOLERANCE, 0},
+{2206, 3192887808u, 3191848339u, 3222552959u, 0, ATAN2_TOLERANCE, 0},
+{2207, 3237183876u, 3179379969u, 3217694749u, 0, ATAN2_TOLERANCE, 0},
+{2208, 939285924u, 3056079386u, 1070838127u, 0, ATAN2_TOLERANCE, 0},
+{2209, 944050180u, 3452557879u, 1078530011u, 0, ATAN2_TOLERANCE, 0},
+{2210, 3058135703u, 3090284601u, 3225720409u, 0, ATAN2_TOLERANCE, 0},
+{2211, 3480592662u, 3261728191u, 3217625051u, 0, ATAN2_TOLERANCE, 0},
+{2212, 3061939312u, 3274418540u, 3226013659u, 0, ATAN2_TOLERANCE, 0},
+{2213, 1155775526u, 1255814444u, 965056178u, 0, ATAN2_TOLERANCE, 0},
+{2214, 1234491880u, 3408568717u, 1078074444u, 0, ATAN2_TOLERANCE, 0},
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_ATAN2_H multiple inclusion protection
+
+// EOF atan2f.h
diff --git a/packages/language/c/libm/current/tests/vectors/atanf.c b/packages/language/c/libm/current/tests/vectors/atanf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/atanf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      atanf.c
+//
+//      Test of atanf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_double_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/atanf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(atanf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &atanf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &atanf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("atanf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("atanf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library atanf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "atanf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF atanf.c
diff --git a/packages/language/c/libm/current/tests/vectors/atanf.h b/packages/language/c/libm/current/tests/vectors/atanf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/atanf.h
@@ -0,0 +1,1235 @@
+#ifndef CYGONCE_LIBM_ATANF_H
+#define CYGONCE_LIBM_ATANF_H
+//===========================================================================
+//
+//      atanf.h
+//
+//      Test vectors for testing of atanf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/atanf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define ATANF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t atanf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 0u, 3210757463u, 0, ATANF_TOLERANCE, 0},
+{1, 3214430700u, 0u, 3210688365u, 0, ATANF_TOLERANCE, 0},
+{2, 3214346813u, 0u, 3210618582u, 0, ATANF_TOLERANCE, 0},
+{3, 3214262927u, 0u, 3210548107u, 0, ATANF_TOLERANCE, 0},
+{4, 3214179041u, 0u, 3210476934u, 0, ATANF_TOLERANCE, 0},
+{5, 3214095155u, 0u, 3210405052u, 0, ATANF_TOLERANCE, 0},
+{6, 3214011269u, 0u, 3210332456u, 0, ATANF_TOLERANCE, 0},
+{7, 3213927383u, 0u, 3210259136u, 0, ATANF_TOLERANCE, 0},
+{8, 3213843497u, 0u, 3210185084u, 0, ATANF_TOLERANCE, 0},
+{9, 3213759611u, 0u, 3210110293u, 0, ATANF_TOLERANCE, 0},
+{10, 3213675725u, 0u, 3210034755u, 0, ATANF_TOLERANCE, 0},
+{11, 3213591839u, 0u, 3209958461u, 0, ATANF_TOLERANCE, 0},
+{12, 3213507953u, 0u, 3209881403u, 0, ATANF_TOLERANCE, 0},
+{13, 3213424067u, 0u, 3209803572u, 0, ATANF_TOLERANCE, 0},
+{14, 3213340180u, 0u, 3209724961u, 0, ATANF_TOLERANCE, 0},
+{15, 3213256294u, 0u, 3209645562u, 0, ATANF_TOLERANCE, 0},
+{16, 3213172408u, 0u, 3209565365u, 0, ATANF_TOLERANCE, 0},
+{17, 3213088522u, 0u, 3209484364u, 0, ATANF_TOLERANCE, 0},
+{18, 3213004636u, 0u, 3209402548u, 0, ATANF_TOLERANCE, 0},
+{19, 3212920750u, 0u, 3209319911u, 0, ATANF_TOLERANCE, 0},
+{20, 3212836864u, 0u, 3209236443u, 0, ATANF_TOLERANCE, 0},
+{21, 3212669092u, 0u, 3209152136u, 0, ATANF_TOLERANCE, 0},
+{22, 3212501320u, 0u, 3209066982u, 0, ATANF_TOLERANCE, 0},
+{23, 3212333548u, 0u, 3208980972u, 0, ATANF_TOLERANCE, 0},
+{24, 3212165775u, 0u, 3208894098u, 0, ATANF_TOLERANCE, 0},
+{25, 3211998003u, 0u, 3208806352u, 0, ATANF_TOLERANCE, 0},
+{26, 3211830231u, 0u, 3208717725u, 0, ATANF_TOLERANCE, 0},
+{27, 3211662459u, 0u, 3208628209u, 0, ATANF_TOLERANCE, 0},
+{28, 3211494687u, 0u, 3208537796u, 0, ATANF_TOLERANCE, 0},
+{29, 3211326915u, 0u, 3208446478u, 0, ATANF_TOLERANCE, 0},
+{30, 3211159142u, 0u, 3208354245u, 0, ATANF_TOLERANCE, 0},
+{31, 3210991370u, 0u, 3208261091u, 0, ATANF_TOLERANCE, 0},
+{32, 3210823598u, 0u, 3208167007u, 0, ATANF_TOLERANCE, 0},
+{33, 3210655826u, 0u, 3208071986u, 0, ATANF_TOLERANCE, 0},
+{34, 3210488054u, 0u, 3207976018u, 0, ATANF_TOLERANCE, 0},
+{35, 3210320282u, 0u, 3207879097u, 0, ATANF_TOLERANCE, 0},
+{36, 3210152509u, 0u, 3207781215u, 0, ATANF_TOLERANCE, 0},
+{37, 3209984737u, 0u, 3207682363u, 0, ATANF_TOLERANCE, 0},
+{38, 3209816965u, 0u, 3207582536u, 0, ATANF_TOLERANCE, 0},
+{39, 3209649193u, 0u, 3207481725u, 0, ATANF_TOLERANCE, 0},
+{40, 3209481421u, 0u, 3207379923u, 0, ATANF_TOLERANCE, 0},
+{41, 3209313649u, 0u, 3207277122u, 0, ATANF_TOLERANCE, 0},
+{42, 3209145876u, 0u, 3207173317u, 0, ATANF_TOLERANCE, 0},
+{43, 3208978104u, 0u, 3207068500u, 0, ATANF_TOLERANCE, 0},
+{44, 3208810332u, 0u, 3206962665u, 0, ATANF_TOLERANCE, 0},
+{45, 3208642560u, 0u, 3206855805u, 0, ATANF_TOLERANCE, 0},
+{46, 3208474788u, 0u, 3206747915u, 0, ATANF_TOLERANCE, 0},
+{47, 3208307016u, 0u, 3206638987u, 0, ATANF_TOLERANCE, 0},
+{48, 3208139244u, 0u, 3206529018u, 0, ATANF_TOLERANCE, 0},
+{49, 3207971471u, 0u, 3206418000u, 0, ATANF_TOLERANCE, 0},
+{50, 3207803699u, 0u, 3206305929u, 0, ATANF_TOLERANCE, 0},
+{51, 3207635927u, 0u, 3206192801u, 0, ATANF_TOLERANCE, 0},
+{52, 3207468155u, 0u, 3206078610u, 0, ATANF_TOLERANCE, 0},
+{53, 3207300383u, 0u, 3205963352u, 0, ATANF_TOLERANCE, 0},
+{54, 3207132611u, 0u, 3205847023u, 0, ATANF_TOLERANCE, 0},
+{55, 3206964838u, 0u, 3205729619u, 0, ATANF_TOLERANCE, 0},
+{56, 3206797066u, 0u, 3205611138u, 0, ATANF_TOLERANCE, 0},
+{57, 3206629294u, 0u, 3205491576u, 0, ATANF_TOLERANCE, 0},
+{58, 3206461522u, 0u, 3205370931u, 0, ATANF_TOLERANCE, 0},
+{59, 3206293750u, 0u, 3205249201u, 0, ATANF_TOLERANCE, 0},
+{60, 3206125978u, 0u, 3205126383u, 0, ATANF_TOLERANCE, 0},
+{61, 3205958205u, 0u, 3205002476u, 0, ATANF_TOLERANCE, 0},
+{62, 3205790433u, 0u, 3204877480u, 0, ATANF_TOLERANCE, 0},
+{63, 3205622661u, 0u, 3204751396u, 0, ATANF_TOLERANCE, 0},
+{64, 3205454889u, 0u, 3204624221u, 0, ATANF_TOLERANCE, 0},
+{65, 3205287117u, 0u, 3204495957u, 0, ATANF_TOLERANCE, 0},
+{66, 3205119345u, 0u, 3204284955u, 0, ATANF_TOLERANCE, 0},
+{67, 3204951572u, 0u, 3204024080u, 0, ATANF_TOLERANCE, 0},
+{68, 3204783800u, 0u, 3203761037u, 0, ATANF_TOLERANCE, 0},
+{69, 3204616028u, 0u, 3203495832u, 0, ATANF_TOLERANCE, 0},
+{70, 3204448256u, 0u, 3203228473u, 0, ATANF_TOLERANCE, 0},
+{71, 3204112712u, 0u, 3202958965u, 0, ATANF_TOLERANCE, 0},
+{72, 3203777167u, 0u, 3202687318u, 0, ATANF_TOLERANCE, 0},
+{73, 3203441623u, 0u, 3202413545u, 0, ATANF_TOLERANCE, 0},
+{74, 3203106079u, 0u, 3202137655u, 0, ATANF_TOLERANCE, 0},
+{75, 3202770534u, 0u, 3201859663u, 0, ATANF_TOLERANCE, 0},
+{76, 3202434990u, 0u, 3201579583u, 0, ATANF_TOLERANCE, 0},
+{77, 3202099446u, 0u, 3201297430u, 0, ATANF_TOLERANCE, 0},
+{78, 3201763901u, 0u, 3201013221u, 0, ATANF_TOLERANCE, 0},
+{79, 3201428357u, 0u, 3200726976u, 0, ATANF_TOLERANCE, 0},
+{80, 3201092813u, 0u, 3200438715u, 0, ATANF_TOLERANCE, 0},
+{81, 3200757268u, 0u, 3200148459u, 0, ATANF_TOLERANCE, 0},
+{82, 3200421724u, 0u, 3199856232u, 0, ATANF_TOLERANCE, 0},
+{83, 3200086180u, 0u, 3199562057u, 0, ATANF_TOLERANCE, 0},
+{84, 3199750636u, 0u, 3199265962u, 0, ATANF_TOLERANCE, 0},
+{85, 3199415091u, 0u, 3198967972u, 0, ATANF_TOLERANCE, 0},
+{86, 3199079547u, 0u, 3198668120u, 0, ATANF_TOLERANCE, 0},
+{87, 3198744003u, 0u, 3198366433u, 0, ATANF_TOLERANCE, 0},
+{88, 3198408458u, 0u, 3198062946u, 0, ATANF_TOLERANCE, 0},
+{89, 3198072914u, 0u, 3197757693u, 0, ATANF_TOLERANCE, 0},
+{90, 3197737370u, 0u, 3197450707u, 0, ATANF_TOLERANCE, 0},
+{91, 3197401825u, 0u, 3197142027u, 0, ATANF_TOLERANCE, 0},
+{92, 3197066281u, 0u, 3196831691u, 0, ATANF_TOLERANCE, 0},
+{93, 3196730737u, 0u, 3196519741u, 0, ATANF_TOLERANCE, 0},
+{94, 3196395192u, 0u, 3196206216u, 0, ATANF_TOLERANCE, 0},
+{95, 3196059648u, 0u, 3195722672u, 0, ATANF_TOLERANCE, 0},
+{96, 3195388559u, 0u, 3195089588u, 0, ATANF_TOLERANCE, 0},
+{97, 3194717471u, 0u, 3194453624u, 0, ATANF_TOLERANCE, 0},
+{98, 3194046382u, 0u, 3193814877u, 0, ATANF_TOLERANCE, 0},
+{99, 3193375293u, 0u, 3193173443u, 0, ATANF_TOLERANCE, 0},
+{100, 3192704205u, 0u, 3192529424u, 0, ATANF_TOLERANCE, 0},
+{101, 3192033116u, 0u, 3191882923u, 0, ATANF_TOLERANCE, 0},
+{102, 3191362028u, 0u, 3191234047u, 0, ATANF_TOLERANCE, 0},
+{103, 3190690939u, 0u, 3190582904u, 0, ATANF_TOLERANCE, 0},
+{104, 3190019850u, 0u, 3189929606u, 0, ATANF_TOLERANCE, 0},
+{105, 3189348762u, 0u, 3189274267u, 0, ATANF_TOLERANCE, 0},
+{106, 3188677673u, 0u, 3188617003u, 0, ATANF_TOLERANCE, 0},
+{107, 3188006584u, 0u, 3187957930u, 0, ATANF_TOLERANCE, 0},
+{108, 3186999951u, 0u, 3186923303u, 0, ATANF_TOLERANCE, 0},
+{109, 3185657774u, 0u, 3185598655u, 0, ATANF_TOLERANCE, 0},
+{110, 3184315597u, 0u, 3184271124u, 0, ATANF_TOLERANCE, 0},
+{111, 3182973420u, 0u, 3182940963u, 0, ATANF_TOLERANCE, 0},
+{112, 3181631242u, 0u, 3181608423u, 0, ATANF_TOLERANCE, 0},
+{113, 3180289065u, 0u, 3180273764u, 0, ATANF_TOLERANCE, 0},
+{114, 3178611343u, 0u, 3178592058u, 0, ATANF_TOLERANCE, 0},
+{115, 3175926989u, 0u, 3175915821u, 0, ATANF_TOLERANCE, 0},
+{116, 3173242634u, 0u, 3173236913u, 0, ATANF_TOLERANCE, 0},
+{117, 3170222735u, 0u, 3170217906u, 0, ATANF_TOLERANCE, 0},
+{118, 3164854026u, 0u, 3164852594u, 0, ATANF_TOLERANCE, 0},
+{119, 3156465418u, 0u, 3156465060u, 0, ATANF_TOLERANCE, 0},
+{120, 646742016u, 0u, 646742016u, 0, ATANF_TOLERANCE, 0},
+{121, 1008981770u, 0u, 1008981412u, 0, ATANF_TOLERANCE, 0},
+{122, 1017370378u, 0u, 1017368946u, 0, ATANF_TOLERANCE, 0},
+{123, 1022739087u, 0u, 1022734258u, 0, ATANF_TOLERANCE, 0},
+{124, 1025758986u, 0u, 1025753265u, 0, ATANF_TOLERANCE, 0},
+{125, 1028443341u, 0u, 1028432173u, 0, ATANF_TOLERANCE, 0},
+{126, 1031127695u, 0u, 1031108410u, 0, ATANF_TOLERANCE, 0},
+{127, 1032805417u, 0u, 1032790116u, 0, ATANF_TOLERANCE, 0},
+{128, 1034147594u, 0u, 1034124775u, 0, ATANF_TOLERANCE, 0},
+{129, 1035489772u, 0u, 1035457315u, 0, ATANF_TOLERANCE, 0},
+{130, 1036831949u, 0u, 1036787476u, 0, ATANF_TOLERANCE, 0},
+{131, 1038174126u, 0u, 1038115007u, 0, ATANF_TOLERANCE, 0},
+{132, 1039516303u, 0u, 1039439655u, 0, ATANF_TOLERANCE, 0},
+{133, 1040522936u, 0u, 1040474282u, 0, ATANF_TOLERANCE, 0},
+{134, 1041194025u, 0u, 1041133355u, 0, ATANF_TOLERANCE, 0},
+{135, 1041865114u, 0u, 1041790619u, 0, ATANF_TOLERANCE, 0},
+{136, 1042536202u, 0u, 1042445958u, 0, ATANF_TOLERANCE, 0},
+{137, 1043207291u, 0u, 1043099256u, 0, ATANF_TOLERANCE, 0},
+{138, 1043878380u, 0u, 1043750399u, 0, ATANF_TOLERANCE, 0},
+{139, 1044549468u, 0u, 1044399275u, 0, ATANF_TOLERANCE, 0},
+{140, 1045220557u, 0u, 1045045776u, 0, ATANF_TOLERANCE, 0},
+{141, 1045891645u, 0u, 1045689795u, 0, ATANF_TOLERANCE, 0},
+{142, 1046562734u, 0u, 1046331229u, 0, ATANF_TOLERANCE, 0},
+{143, 1047233823u, 0u, 1046969976u, 0, ATANF_TOLERANCE, 0},
+{144, 1047904911u, 0u, 1047605940u, 0, ATANF_TOLERANCE, 0},
+{145, 1048576000u, 0u, 1048239024u, 0, ATANF_TOLERANCE, 0},
+{146, 1048911544u, 0u, 1048722568u, 0, ATANF_TOLERANCE, 0},
+{147, 1049247089u, 0u, 1049036093u, 0, ATANF_TOLERANCE, 0},
+{148, 1049582633u, 0u, 1049348043u, 0, ATANF_TOLERANCE, 0},
+{149, 1049918177u, 0u, 1049658379u, 0, ATANF_TOLERANCE, 0},
+{150, 1050253722u, 0u, 1049967059u, 0, ATANF_TOLERANCE, 0},
+{151, 1050589266u, 0u, 1050274045u, 0, ATANF_TOLERANCE, 0},
+{152, 1050924810u, 0u, 1050579298u, 0, ATANF_TOLERANCE, 0},
+{153, 1051260355u, 0u, 1050882785u, 0, ATANF_TOLERANCE, 0},
+{154, 1051595899u, 0u, 1051184472u, 0, ATANF_TOLERANCE, 0},
+{155, 1051931443u, 0u, 1051484324u, 0, ATANF_TOLERANCE, 0},
+{156, 1052266988u, 0u, 1051782314u, 0, ATANF_TOLERANCE, 0},
+{157, 1052602532u, 0u, 1052078409u, 0, ATANF_TOLERANCE, 0},
+{158, 1052938076u, 0u, 1052372584u, 0, ATANF_TOLERANCE, 0},
+{159, 1053273620u, 0u, 1052664811u, 0, ATANF_TOLERANCE, 0},
+{160, 1053609165u, 0u, 1052955067u, 0, ATANF_TOLERANCE, 0},
+{161, 1053944709u, 0u, 1053243328u, 0, ATANF_TOLERANCE, 0},
+{162, 1054280253u, 0u, 1053529573u, 0, ATANF_TOLERANCE, 0},
+{163, 1054615798u, 0u, 1053813782u, 0, ATANF_TOLERANCE, 0},
+{164, 1054951342u, 0u, 1054095935u, 0, ATANF_TOLERANCE, 0},
+{165, 1055286886u, 0u, 1054376015u, 0, ATANF_TOLERANCE, 0},
+{166, 1055622431u, 0u, 1054654007u, 0, ATANF_TOLERANCE, 0},
+{167, 1055957975u, 0u, 1054929897u, 0, ATANF_TOLERANCE, 0},
+{168, 1056293519u, 0u, 1055203670u, 0, ATANF_TOLERANCE, 0},
+{169, 1056629064u, 0u, 1055475317u, 0, ATANF_TOLERANCE, 0},
+{170, 1056964608u, 0u, 1055744825u, 0, ATANF_TOLERANCE, 0},
+{171, 1057132380u, 0u, 1056012184u, 0, ATANF_TOLERANCE, 0},
+{172, 1057300152u, 0u, 1056277389u, 0, ATANF_TOLERANCE, 0},
+{173, 1057467924u, 0u, 1056540432u, 0, ATANF_TOLERANCE, 0},
+{174, 1057635697u, 0u, 1056801307u, 0, ATANF_TOLERANCE, 0},
+{175, 1057803469u, 0u, 1057012309u, 0, ATANF_TOLERANCE, 0},
+{176, 1057971241u, 0u, 1057140573u, 0, ATANF_TOLERANCE, 0},
+{177, 1058139013u, 0u, 1057267748u, 0, ATANF_TOLERANCE, 0},
+{178, 1058306785u, 0u, 1057393832u, 0, ATANF_TOLERANCE, 0},
+{179, 1058474557u, 0u, 1057518828u, 0, ATANF_TOLERANCE, 0},
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+{1048, 3239728775u, 927815421u, 3216758511u, 0, ATANF_TOLERANCE, 0},
+{1049, 3207141672u, 933456504u, 3205853333u, 0, ATANF_TOLERANCE, 0},
+{1050, 3154378805u, 905462392u, 3154378618u, 0, ATANF_TOLERANCE, 0},
+{1051, 3069658155u, 1041452042u, 3069658155u, 0, ATANF_TOLERANCE, 0},
+{1052, 3313160088u, 2964063309u, 3217622960u, 0, ATANF_TOLERANCE, 0},
+{1053, 3207056527u, 3384206601u, 3205793915u, 0, ATANF_TOLERANCE, 0},
+{1054, 1284174954u, 3436881197u, 1070141403u, 0, ATANF_TOLERANCE, 0},
+{1055, 3156081645u, 3308839704u, 3156081325u, 0, ATANF_TOLERANCE, 0},
+{1056, 1063693032u, 976661408u, 1060880281u, 0, ATANF_TOLERANCE, 0},
+{1057, 3036026175u, 1251203998u, 3036026175u, 0, ATANF_TOLERANCE, 0},
+{1058, 1102631663u, 3396951425u, 1069778533u, 0, ATANF_TOLERANCE, 0},
+{1059, 968803479u, 992989712u, 968803479u, 0, ATANF_TOLERANCE, 0},
+{1060, 3273080388u, 3109405906u, 3217569587u, 0, ATANF_TOLERANCE, 0},
+{1061, 1172529774u, 3294550127u, 1070140250u, 0, ATANF_TOLERANCE, 0},
+{1062, 1306695905u, 1292690378u, 1070141403u, 0, ATANF_TOLERANCE, 0},
+{1063, 1003649752u, 1218792138u, 1003649562u, 0, ATANF_TOLERANCE, 0},
+{1064, 1078478376u, 1326246424u, 1067546758u, 0, ATANF_TOLERANCE, 0},
+{1065, 3158855023u, 3151283866u, 3158854369u, 0, ATANF_TOLERANCE, 0},
+{1066, 1165177679u, 3276237026u, 1070139247u, 0, ATANF_TOLERANCE, 0},
+{1067, 3403009513u, 3381966453u, 3217625049u, 0, ATANF_TOLERANCE, 0},
+{1068, 952348506u, 3377573987u, 952348506u, 0, ATANF_TOLERANCE, 0},
+{1069, 1222777442u, 1125769920u, 1070141385u, 0, ATANF_TOLERANCE, 0},
+{1070, 1325324763u, 978336043u, 1070141403u, 0, ATANF_TOLERANCE, 0},
+{1071, 3363524213u, 3202991311u, 3217625018u, 0, ATANF_TOLERANCE, 0},
+{1072, 1158950321u, 1073578913u, 1070137864u, 0, ATANF_TOLERANCE, 0},
+{1073, 903129873u, 3416864271u, 903129873u, 0, ATANF_TOLERANCE, 0},
+{1074, 3078339944u, 988173985u, 3078339944u, 0, ATANF_TOLERANCE, 0},
+{1075, 1208345407u, 1254181270u, 1070141341u, 0, ATANF_TOLERANCE, 0},
+{1076, 1258634105u, 1247426200u, 1070141402u, 0, ATANF_TOLERANCE, 0},
+{1077, 1248478509u, 1287895126u, 1070141400u, 0, ATANF_TOLERANCE, 0},
+{1078, 1153863988u, 3430539165u, 1070136122u, 0, ATANF_TOLERANCE, 0},
+{1079, 1235620969u, 866627358u, 1070141396u, 0, ATANF_TOLERANCE, 0},
+{1080, 1097120930u, 3221726305u, 1069555579u, 0, ATANF_TOLERANCE, 0},
+{1081, 3469778622u, 1200179013u, 3217625051u, 0, ATANF_TOLERANCE, 0},
+{1082, 1147712200u, 931865525u, 1070132390u, 0, ATANF_TOLERANCE, 0},
+{1083, 1124721745u, 3058969650u, 1070080569u, 0, ATANF_TOLERANCE, 0},
+{1084, 3261744304u, 1043806501u, 3217481834u, 0, ATANF_TOLERANCE, 0},
+{1085, 1064922416u, 1320485628u, 1061534605u, 0, ATANF_TOLERANCE, 0},
+{1086, 3303160152u, 3075455322u, 3217620416u, 0, ATANF_TOLERANCE, 0},
+{1087, 1315090496u, 3269683237u, 1070141403u, 0, ATANF_TOLERANCE, 0},
+{1088, 3230403187u, 1322841992u, 3215740568u, 0, ATANF_TOLERANCE, 0},
+{1089, 1335399673u, 974138676u, 1070141403u, 0, ATANF_TOLERANCE, 0},
+{1090, 1072458508u, 3372833993u, 1065978748u, 0, ATANF_TOLERANCE, 0},
+{1091, 3303015249u, 3015039539u, 3217620370u, 0, ATANF_TOLERANCE, 0},
+{1092, 3252139741u, 1059615003u, 3217314092u, 0, ATANF_TOLERANCE, 0},
+{1093, 3468519966u, 3113982619u, 3217625051u, 0, ATANF_TOLERANCE, 0},
+{1094, 1006231203u, 897530770u, 1006230885u, 0, ATANF_TOLERANCE, 0},
+{1095, 951554138u, 1001144381u, 951554138u, 0, ATANF_TOLERANCE, 0},
+{1096, 942046828u, 986341002u, 942046828u, 0, ATANF_TOLERANCE, 0},
+{1097, 3319723279u, 3414482416u, 3217623875u, 0, ATANF_TOLERANCE, 0},
+{1098, 3255104167u, 928827688u, 3217372739u, 0, ATANF_TOLERANCE, 0},
+{1099, 1155477903u, 3104812800u, 1070136705u, 0, ATANF_TOLERANCE, 0},
+{1100, 3273889176u, 980486479u, 3217573771u, 0, ATANF_TOLERANCE, 0},
+{1101, 3237813668u, 3441016803u, 3216570123u, 0, ATANF_TOLERANCE, 0},
+{1102, 1228207362u, 2985476579u, 1070141391u, 0, ATANF_TOLERANCE, 0},
+{1103, 975349337u, 1311932596u, 975349336u, 0, ATANF_TOLERANCE, 0},
+{1104, 1290175785u, 3008182462u, 1070141403u, 0, ATANF_TOLERANCE, 0},
+{1105, 981908840u, 3314038398u, 981908837u, 0, ATANF_TOLERANCE, 0},
+{1106, 941187647u, 1107765599u, 941187647u, 0, ATANF_TOLERANCE, 0},
+{1107, 1214223128u, 3225536822u, 1070141366u, 0, ATANF_TOLERANCE, 0},
+{1108, 3422922584u, 1086391131u, 3217625050u, 0, ATANF_TOLERANCE, 0},
+{1109, 1315857601u, 3487600045u, 1070141403u, 0, ATANF_TOLERANCE, 0},
+{1110, 3453226030u, 3233768835u, 3217625051u, 0, ATANF_TOLERANCE, 0},
+{1111, 1078359574u, 3199175230u, 1067524560u, 0, ATANF_TOLERANCE, 0},
+{1112, 1029557624u, 3302959071u, 1029543441u, 0, ATANF_TOLERANCE, 0},
+{1113, 1207675424u, 3042692550u, 1070141338u, 0, ATANF_TOLERANCE, 0},
+{1114, 1028355074u, 3442294040u, 1028344125u, 0, ATANF_TOLERANCE, 0},
+{1115, 3119299090u, 1187096397u, 3119299089u, 0, ATANF_TOLERANCE, 0},
+{1116, 1248421894u, 3367769132u, 1070141400u, 0, ATANF_TOLERANCE, 0},
+{1117, 3353251994u, 1095517730u, 3217624977u, 0, ATANF_TOLERANCE, 0},
+{1118, 876926659u, 3288089977u, 876926659u, 0, ATANF_TOLERANCE, 0},
+{1119, 1076752219u, 876236939u, 1067183758u, 0, ATANF_TOLERANCE, 0},
+{1120, 3388531942u, 2988520062u, 3217625047u, 0, ATANF_TOLERANCE, 0},
+{1121, 1273395082u, 3031189261u, 1070141402u, 0, ATANF_TOLERANCE, 0},
+{1122, 3385588183u, 3258252464u, 3217625046u, 0, ATANF_TOLERANCE, 0},
+{1123, 3192315328u, 3289489214u, 3192155091u, 0, ATANF_TOLERANCE, 0},
+{1124, 3441804648u, 3274638356u, 3217625051u, 0, ATANF_TOLERANCE, 0},
+{1125, 3392827417u, 1277961150u, 3217625048u, 0, ATANF_TOLERANCE, 0},
+{1126, 1161241793u, 1328003707u, 1070138540u, 0, ATANF_TOLERANCE, 0},
+{1127, 3034494183u, 3041579130u, 3034494183u, 0, ATANF_TOLERANCE, 0},
+{1128, 1171318485u, 3374409104u, 1070140148u, 0, ATANF_TOLERANCE, 0},
+{1129, 3047748143u, 831102792u, 3047748143u, 0, ATANF_TOLERANCE, 0},
+{1130, 1001216371u, 3052357038u, 1001216265u, 0, ATANF_TOLERANCE, 0},
+{1131, 912515889u, 1074635609u, 912515889u, 0, ATANF_TOLERANCE, 0},
+{1132, 3391452505u, 897989232u, 3217625048u, 0, ATANF_TOLERANCE, 0},
+{1133, 3249603369u, 3147662248u, 3217246189u, 0, ATANF_TOLERANCE, 0},
+{1134, 1220264047u, 2960450369u, 1070141381u, 0, ATANF_TOLERANCE, 0},
+{1135, 3169816394u, 988430929u, 3169811921u, 0, ATANF_TOLERANCE, 0},
+{1136, 3098997418u, 3002162688u, 3098997418u, 0, ATANF_TOLERANCE, 0},
+{1137, 3282212423u, 3174079140u, 3217599253u, 0, ATANF_TOLERANCE, 0},
+{1138, 3352293320u, 3247843425u, 3217624972u, 0, ATANF_TOLERANCE, 0},
+{1139, 3296358441u, 875645354u, 3217616677u, 0, ATANF_TOLERANCE, 0},
+{1140, 1197828352u, 3245614728u, 1070141260u, 0, ATANF_TOLERANCE, 0},
+{1141, 3340510371u, 914930263u, 3217624841u, 0, ATANF_TOLERANCE, 0},
+{1142, 1127109339u, 3368125489u, 1070093282u, 0, ATANF_TOLERANCE, 0},
+{1143, 909467381u, 1232375752u, 909467381u, 0, ATANF_TOLERANCE, 0},
+{1144, 1200599955u, 2981200675u, 1070141289u, 0, ATANF_TOLERANCE, 0},
+{1145, 962230977u, 2988248037u, 962230977u, 0, ATANF_TOLERANCE, 0},
+{1146, 3192887808u, 3191848339u, 3192705872u, 0, ATANF_TOLERANCE, 0},
+{1147, 3237183876u, 3179379969u, 3216528954u, 0, ATANF_TOLERANCE, 0},
+{1148, 939285924u, 3056079386u, 939285924u, 0, ATANF_TOLERANCE, 0},
+{1149, 944050180u, 3452557879u, 944050180u, 0, ATANF_TOLERANCE, 0},
+{1150, 3058135703u, 3090284601u, 3058135703u, 0, ATANF_TOLERANCE, 0},
+{1151, 3480592662u, 3261728191u, 3217625051u, 0, ATANF_TOLERANCE, 0},
+{1152, 3061939312u, 3274418540u, 3061939312u, 0, ATANF_TOLERANCE, 0},
+{1153, 1003299981u, 853295521u, 1003299805u, 0, ATANF_TOLERANCE, 0},
+{1154, 1155775526u, 1255814444u, 1070136798u, 0, ATANF_TOLERANCE, 0},
+{1155, 1234491880u, 3408568717u, 1070141396u, 0, ATANF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_ATANF_H multiple inclusion protection
+
+// EOF atanf.h
diff --git a/packages/language/c/libm/current/tests/vectors/atanhf.c b/packages/language/c/libm/current/tests/vectors/atanhf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/atanhf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      atanhf.c
+//
+//      Test of atanhf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/atanhf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(atanhf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &atanhf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &atanhf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("atanhf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("atanhf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library atanhf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "atanhf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF atanhf.c
diff --git a/packages/language/c/libm/current/tests/vectors/atanhf.h b/packages/language/c/libm/current/tests/vectors/atanhf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/atanhf.h
@@ -0,0 +1,361 @@
+#ifndef CYGONCE_LIBM_ATANHF_H
+#define CYGONCE_LIBM_ATANHF_H
+//===========================================================================
+//
+//      atanhf.h
+//
+//      Test vectors for testing of atanhf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/atanhf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define ATANH_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t atanhf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{1, 3214430700u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{2, 3214346813u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{3, 3214262927u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{4, 3214179041u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{5, 3214095155u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{6, 3214011269u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{7, 3213927383u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{8, 3213843497u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{9, 3213759611u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{10, 3213675725u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{11, 3213591839u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{12, 3213507953u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{13, 3213424067u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{14, 3213340180u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{15, 3213256294u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{16, 3213172408u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{17, 3213088522u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{18, 3213004636u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{19, 3212920750u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{20, 3212836864u, 1115684864u, 4286578688u, EDOM, ATANH_TOLERANCE, 0},
+{21, 3212669092u, 3223937731u, 3223937731u, 0, ATANH_TOLERANCE, 0},
+{22, 3212501320u, 3222473531u, 3222473531u, 0, ATANH_TOLERANCE, 0},
+{23, 3212333548u, 3221612590u, 3221612590u, 0, ATANH_TOLERANCE, 0},
+{24, 3212165775u, 3220771731u, 3220771731u, 0, ATANH_TOLERANCE, 0},
+{25, 3211998003u, 3219814346u, 3219814346u, 0, ATANH_TOLERANCE, 0},
+{26, 3211830231u, 3219028070u, 3219028070u, 0, ATANH_TOLERANCE, 0},
+{27, 3211662459u, 3218359840u, 3218359840u, 0, ATANH_TOLERANCE, 0},
+{28, 3211494687u, 3217777981u, 3217777981u, 0, ATANH_TOLERANCE, 0},
+{29, 3211326915u, 3217262061u, 3217262061u, 0, ATANH_TOLERANCE, 0},
+{30, 3211159142u, 3216798127u, 3216798127u, 0, ATANH_TOLERANCE, 0},
+{31, 3210991370u, 3216376234u, 3216376234u, 0, ATANH_TOLERANCE, 0},
+{32, 3210823598u, 3215989031u, 3215989031u, 0, ATANH_TOLERANCE, 0},
+{33, 3210655826u, 3215630939u, 3215630939u, 0, ATANH_TOLERANCE, 0},
+{34, 3210488054u, 3215297618u, 3215297618u, 0, ATANH_TOLERANCE, 0},
+{35, 3210320282u, 3214985630u, 3214985630u, 0, ATANH_TOLERANCE, 0},
+{36, 3210152509u, 3214692201u, 3214692201u, 0, ATANH_TOLERANCE, 0},
+{37, 3209984737u, 3214415066u, 3214415066u, 0, ATANH_TOLERANCE, 0},
+{38, 3209816965u, 3214152344u, 3214152344u, 0, ATANH_TOLERANCE, 0},
+{39, 3209649193u, 3213902461u, 3213902461u, 0, ATANH_TOLERANCE, 0},
+{40, 3209481421u, 3213664084u, 3213664084u, 0, ATANH_TOLERANCE, 0},
+{41, 3209313649u, 3213436077u, 3213436077u, 0, ATANH_TOLERANCE, 0},
+{42, 3209145876u, 3213217459u, 3213217459u, 0, ATANH_TOLERANCE, 0},
+{43, 3208978104u, 3213007385u, 3213007385u, 0, ATANH_TOLERANCE, 0},
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+{256, 3243245568u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{257, 3241462989u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{258, 3239680410u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{259, 3237792973u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{260, 3234227814u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{261, 3230662656u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{262, 3224580915u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{263, 3213675725u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{264, 1058642330u, 1060205080u, 1060205080u, 0, ATANH_TOLERANCE, 0},
+{265, 1075000115u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{266, 1082130432u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{267, 1085695590u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{268, 1089260749u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{269, 1091672474u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{270, 1093455053u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{271, 1095237632u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{272, 1097020211u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{273, 1098802790u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{274, 1099746509u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{275, 1100637798u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{276, 1101529088u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{277, 1102420378u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{278, 1103311667u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{279, 1104202957u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{280, 1105094246u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0},
+{281, 1105985536u, 1115684864u, 2143289344u, EDOM, ATANH_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_ATANHF_H multiple inclusion protection
+
+// EOF atanhf.h
diff --git a/packages/language/c/libm/current/tests/vectors/cbrtf.c b/packages/language/c/libm/current/tests/vectors/cbrtf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/cbrtf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      cbrtf.c
+//
+//      Test of cbrtf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_double_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/cbrtf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(cbrtf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &cbrtf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &cbrtf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("cbrtf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("cbrtf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library cbrtf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "cbrtf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF cbrtf.c
diff --git a/packages/language/c/libm/current/tests/vectors/cbrtf.h b/packages/language/c/libm/current/tests/vectors/cbrtf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/cbrtf.h
@@ -0,0 +1,363 @@
+#ifndef CYGONCE_LIBM_CBRTF_H
+#define CYGONCE_LIBM_CBRTF_H
+//===========================================================================
+//
+//      cbrtf.h
+//
+//      Test vectors for testing of cbrtf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/cbrtf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define CBRTF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t cbrtf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 2147497108u, 3213362482u, 0, CBRTF_TOLERANCE, 0},
+{1, 3214430700u, 2147497108u, 3213337651u, 0, CBRTF_TOLERANCE, 0},
+{2, 3214346813u, 2147497108u, 3213312681u, 0, CBRTF_TOLERANCE, 0},
+{3, 3214262927u, 2147497108u, 3213287569u, 0, CBRTF_TOLERANCE, 0},
+{4, 3214179041u, 2147497108u, 3213262314u, 0, CBRTF_TOLERANCE, 0},
+{5, 3214095155u, 2147497108u, 3213236913u, 0, CBRTF_TOLERANCE, 0},
+{6, 3214011269u, 2147497108u, 3213211364u, 0, CBRTF_TOLERANCE, 0},
+{7, 3213927383u, 2147497108u, 3213185666u, 0, CBRTF_TOLERANCE, 0},
+{8, 3213843497u, 2147497108u, 3213159816u, 0, CBRTF_TOLERANCE, 0},
+{9, 3213759611u, 2147497108u, 3213133811u, 0, CBRTF_TOLERANCE, 0},
+{10, 3213675725u, 2147497108u, 3213107649u, 0, CBRTF_TOLERANCE, 0},
+{11, 3213591839u, 2147497108u, 3213081329u, 0, CBRTF_TOLERANCE, 0},
+{12, 3213507953u, 2147497108u, 3213054847u, 0, CBRTF_TOLERANCE, 0},
+{13, 3213424067u, 2147497108u, 3213028201u, 0, CBRTF_TOLERANCE, 0},
+{14, 3213340180u, 2147497108u, 3213001388u, 0, CBRTF_TOLERANCE, 0},
+{15, 3213256294u, 2147497108u, 3212974407u, 0, CBRTF_TOLERANCE, 0},
+{16, 3213172408u, 2147497108u, 3212947253u, 0, CBRTF_TOLERANCE, 0},
+{17, 3213088522u, 2147497108u, 3212919925u, 0, CBRTF_TOLERANCE, 0},
+{18, 3213004636u, 2147497108u, 3212892419u, 0, CBRTF_TOLERANCE, 0},
+{19, 3212920750u, 2147497108u, 3212864733u, 0, CBRTF_TOLERANCE, 0},
+{20, 3212836864u, 2147497108u, 3212836864u, 0, CBRTF_TOLERANCE, 0},
+{21, 3212669092u, 2147497108u, 3212780752u, 0, CBRTF_TOLERANCE, 0},
+{22, 3212501320u, 2147497108u, 3212724262u, 0, CBRTF_TOLERANCE, 0},
+{23, 3212333548u, 2147497108u, 3212667386u, 0, CBRTF_TOLERANCE, 0},
+{24, 3212165775u, 2147497108u, 3212610117u, 0, CBRTF_TOLERANCE, 0},
+{25, 3211998003u, 2147497108u, 3212552449u, 0, CBRTF_TOLERANCE, 0},
+{26, 3211830231u, 2147497108u, 3212494376u, 0, CBRTF_TOLERANCE, 0},
+{27, 3211662459u, 2147497108u, 3212435889u, 0, CBRTF_TOLERANCE, 0},
+{28, 3211494687u, 2147497108u, 3212376981u, 0, CBRTF_TOLERANCE, 0},
+{29, 3211326915u, 2147497108u, 3212317645u, 0, CBRTF_TOLERANCE, 0},
+{30, 3211159142u, 2147497108u, 3212257872u, 0, CBRTF_TOLERANCE, 0},
+{31, 3210991370u, 2147497108u, 3212197655u, 0, CBRTF_TOLERANCE, 0},
+{32, 3210823598u, 2147497108u, 3212136985u, 0, CBRTF_TOLERANCE, 0},
+{33, 3210655826u, 2147497108u, 3212075854u, 0, CBRTF_TOLERANCE, 0},
+{34, 3210488054u, 2147497108u, 3212014253u, 0, CBRTF_TOLERANCE, 0},
+{35, 3210320282u, 2147497108u, 3211952172u, 0, CBRTF_TOLERANCE, 0},
+{36, 3210152509u, 2147497108u, 3211889602u, 0, CBRTF_TOLERANCE, 0},
+{37, 3209984737u, 2147497108u, 3211826534u, 0, CBRTF_TOLERANCE, 0},
+{38, 3209816965u, 2147497108u, 3211762957u, 0, CBRTF_TOLERANCE, 0},
+{39, 3209649193u, 2147497108u, 3211698861u, 0, CBRTF_TOLERANCE, 0},
+{40, 3209481421u, 2147497108u, 3211634236u, 0, CBRTF_TOLERANCE, 0},
+{41, 3209313649u, 2147497108u, 3211569069u, 0, CBRTF_TOLERANCE, 0},
+{42, 3209145876u, 2147497108u, 3211503351u, 0, CBRTF_TOLERANCE, 0},
+{43, 3208978104u, 2147497108u, 3211437068u, 0, CBRTF_TOLERANCE, 0},
+{44, 3208810332u, 2147497108u, 3211370209u, 0, CBRTF_TOLERANCE, 0},
+{45, 3208642560u, 2147497108u, 3211302760u, 0, CBRTF_TOLERANCE, 0},
+{46, 3208474788u, 2147497108u, 3211234710u, 0, CBRTF_TOLERANCE, 0},
+{47, 3208307016u, 2147497108u, 3211166043u, 0, CBRTF_TOLERANCE, 0},
+{48, 3208139244u, 2147497108u, 3211096747u, 0, CBRTF_TOLERANCE, 0},
+{49, 3207971471u, 2147497108u, 3211026806u, 0, CBRTF_TOLERANCE, 0},
+{50, 3207803699u, 2147497108u, 3210956205u, 0, CBRTF_TOLERANCE, 0},
+{51, 3207635927u, 2147497108u, 3210884929u, 0, CBRTF_TOLERANCE, 0},
+{52, 3207468155u, 2147497108u, 3210812960u, 0, CBRTF_TOLERANCE, 0},
+{53, 3207300383u, 2147497108u, 3210740283u, 0, CBRTF_TOLERANCE, 0},
+{54, 3207132611u, 2147497108u, 3210666878u, 0, CBRTF_TOLERANCE, 0},
+{55, 3206964838u, 2147497108u, 3210592729u, 0, CBRTF_TOLERANCE, 0},
+{56, 3206797066u, 2147497108u, 3210517814u, 0, CBRTF_TOLERANCE, 0},
+{57, 3206629294u, 2147497108u, 3210442116u, 0, CBRTF_TOLERANCE, 0},
+{58, 3206461522u, 2147497108u, 3210365612u, 0, CBRTF_TOLERANCE, 0},
+{59, 3206293750u, 2147497108u, 3210288281u, 0, CBRTF_TOLERANCE, 0},
+{60, 3206125978u, 2147497108u, 3210210100u, 0, CBRTF_TOLERANCE, 0},
+{61, 3205958205u, 2147497108u, 3210131046u, 0, CBRTF_TOLERANCE, 0},
+{62, 3205790433u, 2147497108u, 3210051093u, 0, CBRTF_TOLERANCE, 0},
+{63, 3205622661u, 2147497108u, 3209970215u, 0, CBRTF_TOLERANCE, 0},
+{64, 3205454889u, 2147497108u, 3209888387u, 0, CBRTF_TOLERANCE, 0},
+{65, 3205287117u, 2147497108u, 3209805578u, 0, CBRTF_TOLERANCE, 0},
+{66, 3205119345u, 2147497108u, 3209721759u, 0, CBRTF_TOLERANCE, 0},
+{67, 3204951572u, 2147497108u, 3209636899u, 0, CBRTF_TOLERANCE, 0},
+{68, 3204783800u, 2147497108u, 3209550965u, 0, CBRTF_TOLERANCE, 0},
+{69, 3204616028u, 2147497108u, 3209463922u, 0, CBRTF_TOLERANCE, 0},
+{70, 3204448256u, 2147497108u, 3209375733u, 0, CBRTF_TOLERANCE, 0},
+{71, 3204112712u, 2147497108u, 3209286361u, 0, CBRTF_TOLERANCE, 0},
+{72, 3203777167u, 2147497108u, 3209195764u, 0, CBRTF_TOLERANCE, 0},
+{73, 3203441623u, 2147497108u, 3209103900u, 0, CBRTF_TOLERANCE, 0},
+{74, 3203106079u, 2147497108u, 3209010724u, 0, CBRTF_TOLERANCE, 0},
+{75, 3202770534u, 2147497108u, 3208916187u, 0, CBRTF_TOLERANCE, 0},
+{76, 3202434990u, 2147497108u, 3208820239u, 0, CBRTF_TOLERANCE, 0},
+{77, 3202099446u, 2147497108u, 3208722826u, 0, CBRTF_TOLERANCE, 0},
+{78, 3201763901u, 2147497108u, 3208623891u, 0, CBRTF_TOLERANCE, 0},
+{79, 3201428357u, 2147497108u, 3208523373u, 0, CBRTF_TOLERANCE, 0},
+{80, 3201092813u, 2147497108u, 3208421206u, 0, CBRTF_TOLERANCE, 0},
+{81, 3200757268u, 2147497108u, 3208317323u, 0, CBRTF_TOLERANCE, 0},
+{82, 3200421724u, 2147497108u, 3208211648u, 0, CBRTF_TOLERANCE, 0},
+{83, 3200086180u, 2147497108u, 3208104103u, 0, CBRTF_TOLERANCE, 0},
+{84, 3199750636u, 2147497108u, 3207994601u, 0, CBRTF_TOLERANCE, 0},
+{85, 3199415091u, 2147497108u, 3207883053u, 0, CBRTF_TOLERANCE, 0},
+{86, 3199079547u, 2147497108u, 3207769360u, 0, CBRTF_TOLERANCE, 0},
+{87, 3198744003u, 2147497108u, 3207653414u, 0, CBRTF_TOLERANCE, 0},
+{88, 3198408458u, 2147497108u, 3207535102u, 0, CBRTF_TOLERANCE, 0},
+{89, 3198072914u, 2147497108u, 3207414299u, 0, CBRTF_TOLERANCE, 0},
+{90, 3197737370u, 2147497108u, 3207290869u, 0, CBRTF_TOLERANCE, 0},
+{91, 3197401825u, 2147497108u, 3207164665u, 0, CBRTF_TOLERANCE, 0},
+{92, 3197066281u, 2147497108u, 3207035525u, 0, CBRTF_TOLERANCE, 0},
+{93, 3196730737u, 2147497108u, 3206903273u, 0, CBRTF_TOLERANCE, 0},
+{94, 3196395192u, 2147497108u, 3206767713u, 0, CBRTF_TOLERANCE, 0},
+{95, 3196059648u, 2147497108u, 3206628632u, 0, CBRTF_TOLERANCE, 0},
+{96, 3195388559u, 2147497108u, 3206485790u, 0, CBRTF_TOLERANCE, 0},
+{97, 3194717471u, 2147497108u, 3206338924u, 0, CBRTF_TOLERANCE, 0},
+{98, 3194046382u, 2147497108u, 3206187736u, 0, CBRTF_TOLERANCE, 0},
+{99, 3193375293u, 2147497108u, 3206031894u, 0, CBRTF_TOLERANCE, 0},
+{100, 3192704205u, 2147497108u, 3205871023u, 0, CBRTF_TOLERANCE, 0},
+{101, 3192033116u, 2147497108u, 3205704697u, 0, CBRTF_TOLERANCE, 0},
+{102, 3191362028u, 2147497108u, 3205532427u, 0, CBRTF_TOLERANCE, 0},
+{103, 3190690939u, 2147497108u, 3205353652u, 0, CBRTF_TOLERANCE, 0},
+{104, 3190019850u, 2147497108u, 3205167722u, 0, CBRTF_TOLERANCE, 0},
+{105, 3189348762u, 2147497108u, 3204973874u, 0, CBRTF_TOLERANCE, 0},
+{106, 3188677673u, 2147497108u, 3204771208u, 0, CBRTF_TOLERANCE, 0},
+{107, 3188006584u, 2147497108u, 3204558645u, 0, CBRTF_TOLERANCE, 0},
+{108, 3186999951u, 2147497108u, 3204221509u, 0, CBRTF_TOLERANCE, 0},
+{109, 3185657774u, 2147497108u, 3203748377u, 0, CBRTF_TOLERANCE, 0},
+{110, 3184315597u, 2147497108u, 3203245628u, 0, CBRTF_TOLERANCE, 0},
+{111, 3182973420u, 2147497108u, 3202708139u, 0, CBRTF_TOLERANCE, 0},
+{112, 3181631242u, 2147497108u, 3202129206u, 0, CBRTF_TOLERANCE, 0},
+{113, 3180289065u, 2147497108u, 3201499779u, 0, CBRTF_TOLERANCE, 0},
+{114, 3178611343u, 2147497108u, 3200807156u, 0, CBRTF_TOLERANCE, 0},
+{115, 3175926989u, 2147497108u, 3200032598u, 0, CBRTF_TOLERANCE, 0},
+{116, 3173242634u, 2147497108u, 3199146494u, 0, CBRTF_TOLERANCE, 0},
+{117, 3170222735u, 2147497108u, 3198097182u, 0, CBRTF_TOLERANCE, 0},
+{118, 3164854026u, 2147497108u, 3196779114u, 0, CBRTF_TOLERANCE, 0},
+{119, 3156465418u, 2147497108u, 3193740598u, 0, CBRTF_TOLERANCE, 0},
+{120, 646742016u, 2147497108u, 925260670u, 0, CBRTF_TOLERANCE, 0},
+{121, 1008981770u, 2147497108u, 1046256950u, 0, CBRTF_TOLERANCE, 0},
+{122, 1017370378u, 2147497108u, 1049295466u, 0, CBRTF_TOLERANCE, 0},
+{123, 1022739087u, 2147497108u, 1050613534u, 0, CBRTF_TOLERANCE, 0},
+{124, 1025758986u, 2147497108u, 1051662846u, 0, CBRTF_TOLERANCE, 0},
+{125, 1028443341u, 2147497108u, 1052548950u, 0, CBRTF_TOLERANCE, 0},
+{126, 1031127695u, 2147497108u, 1053323508u, 0, CBRTF_TOLERANCE, 0},
+{127, 1032805417u, 2147497108u, 1054016131u, 0, CBRTF_TOLERANCE, 0},
+{128, 1034147594u, 2147497108u, 1054645558u, 0, CBRTF_TOLERANCE, 0},
+{129, 1035489772u, 2147497108u, 1055224491u, 0, CBRTF_TOLERANCE, 0},
+{130, 1036831949u, 2147497108u, 1055761980u, 0, CBRTF_TOLERANCE, 0},
+{131, 1038174126u, 2147497108u, 1056264729u, 0, CBRTF_TOLERANCE, 0},
+{132, 1039516303u, 2147497108u, 1056737861u, 0, CBRTF_TOLERANCE, 0},
+{133, 1040522936u, 2147497108u, 1057074997u, 0, CBRTF_TOLERANCE, 0},
+{134, 1041194025u, 2147497108u, 1057287560u, 0, CBRTF_TOLERANCE, 0},
+{135, 1041865114u, 2147497108u, 1057490226u, 0, CBRTF_TOLERANCE, 0},
+{136, 1042536202u, 2147497108u, 1057684074u, 0, CBRTF_TOLERANCE, 0},
+{137, 1043207291u, 2147497108u, 1057870004u, 0, CBRTF_TOLERANCE, 0},
+{138, 1043878380u, 2147497108u, 1058048779u, 0, CBRTF_TOLERANCE, 0},
+{139, 1044549468u, 2147497108u, 1058221049u, 0, CBRTF_TOLERANCE, 0},
+{140, 1045220557u, 2147497108u, 1058387375u, 0, CBRTF_TOLERANCE, 0},
+{141, 1045891645u, 2147497108u, 1058548246u, 0, CBRTF_TOLERANCE, 0},
+{142, 1046562734u, 2147497108u, 1058704088u, 0, CBRTF_TOLERANCE, 0},
+{143, 1047233823u, 2147497108u, 1058855276u, 0, CBRTF_TOLERANCE, 0},
+{144, 1047904911u, 2147497108u, 1059002142u, 0, CBRTF_TOLERANCE, 0},
+{145, 1048576000u, 2147497108u, 1059144984u, 0, CBRTF_TOLERANCE, 0},
+{146, 1048911544u, 2147497108u, 1059284065u, 0, CBRTF_TOLERANCE, 0},
+{147, 1049247089u, 2147497108u, 1059419625u, 0, CBRTF_TOLERANCE, 0},
+{148, 1049582633u, 2147497108u, 1059551877u, 0, CBRTF_TOLERANCE, 0},
+{149, 1049918177u, 2147497108u, 1059681017u, 0, CBRTF_TOLERANCE, 0},
+{150, 1050253722u, 2147497108u, 1059807221u, 0, CBRTF_TOLERANCE, 0},
+{151, 1050589266u, 2147497108u, 1059930651u, 0, CBRTF_TOLERANCE, 0},
+{152, 1050924810u, 2147497108u, 1060051454u, 0, CBRTF_TOLERANCE, 0},
+{153, 1051260355u, 2147497108u, 1060169766u, 0, CBRTF_TOLERANCE, 0},
+{154, 1051595899u, 2147497108u, 1060285712u, 0, CBRTF_TOLERANCE, 0},
+{155, 1051931443u, 2147497108u, 1060399405u, 0, CBRTF_TOLERANCE, 0},
+{156, 1052266988u, 2147497108u, 1060510953u, 0, CBRTF_TOLERANCE, 0},
+{157, 1052602532u, 2147497108u, 1060620455u, 0, CBRTF_TOLERANCE, 0},
+{158, 1052938076u, 2147497108u, 1060728000u, 0, CBRTF_TOLERANCE, 0},
+{159, 1053273620u, 2147497108u, 1060833675u, 0, CBRTF_TOLERANCE, 0},
+{160, 1053609165u, 2147497108u, 1060937558u, 0, CBRTF_TOLERANCE, 0},
+{161, 1053944709u, 2147497108u, 1061039725u, 0, CBRTF_TOLERANCE, 0},
+{162, 1054280253u, 2147497108u, 1061140243u, 0, CBRTF_TOLERANCE, 0},
+{163, 1054615798u, 2147497108u, 1061239178u, 0, CBRTF_TOLERANCE, 0},
+{164, 1054951342u, 2147497108u, 1061336591u, 0, CBRTF_TOLERANCE, 0},
+{165, 1055286886u, 2147497108u, 1061432539u, 0, CBRTF_TOLERANCE, 0},
+{166, 1055622431u, 2147497108u, 1061527076u, 0, CBRTF_TOLERANCE, 0},
+{167, 1055957975u, 2147497108u, 1061620252u, 0, CBRTF_TOLERANCE, 0},
+{168, 1056293519u, 2147497108u, 1061712116u, 0, CBRTF_TOLERANCE, 0},
+{169, 1056629064u, 2147497108u, 1061802713u, 0, CBRTF_TOLERANCE, 0},
+{170, 1056964608u, 2147497108u, 1061892085u, 0, CBRTF_TOLERANCE, 0},
+{171, 1057132380u, 2147497108u, 1061980274u, 0, CBRTF_TOLERANCE, 0},
+{172, 1057300152u, 2147497108u, 1062067317u, 0, CBRTF_TOLERANCE, 0},
+{173, 1057467924u, 2147497108u, 1062153251u, 0, CBRTF_TOLERANCE, 0},
+{174, 1057635697u, 2147497108u, 1062238111u, 0, CBRTF_TOLERANCE, 0},
+{175, 1057803469u, 2147497108u, 1062321930u, 0, CBRTF_TOLERANCE, 0},
+{176, 1057971241u, 2147497108u, 1062404739u, 0, CBRTF_TOLERANCE, 0},
+{177, 1058139013u, 2147497108u, 1062486567u, 0, CBRTF_TOLERANCE, 0},
+{178, 1058306785u, 2147497108u, 1062567445u, 0, CBRTF_TOLERANCE, 0},
+{179, 1058474557u, 2147497108u, 1062647398u, 0, CBRTF_TOLERANCE, 0},
+{180, 1058642330u, 2147497108u, 1062726452u, 0, CBRTF_TOLERANCE, 0},
+{181, 1058810102u, 2147497108u, 1062804633u, 0, CBRTF_TOLERANCE, 0},
+{182, 1058977874u, 2147497108u, 1062881964u, 0, CBRTF_TOLERANCE, 0},
+{183, 1059145646u, 2147497108u, 1062958468u, 0, CBRTF_TOLERANCE, 0},
+{184, 1059313418u, 2147497108u, 1063034166u, 0, CBRTF_TOLERANCE, 0},
+{185, 1059481190u, 2147497108u, 1063109081u, 0, CBRTF_TOLERANCE, 0},
+{186, 1059648963u, 2147497108u, 1063183230u, 0, CBRTF_TOLERANCE, 0},
+{187, 1059816735u, 2147497108u, 1063256635u, 0, CBRTF_TOLERANCE, 0},
+{188, 1059984507u, 2147497108u, 1063329312u, 0, CBRTF_TOLERANCE, 0},
+{189, 1060152279u, 2147497108u, 1063401281u, 0, CBRTF_TOLERANCE, 0},
+{190, 1060320051u, 2147497108u, 1063472557u, 0, CBRTF_TOLERANCE, 0},
+{191, 1060487823u, 2147497108u, 1063543158u, 0, CBRTF_TOLERANCE, 0},
+{192, 1060655596u, 2147497108u, 1063613099u, 0, CBRTF_TOLERANCE, 0},
+{193, 1060823368u, 2147497108u, 1063682395u, 0, CBRTF_TOLERANCE, 0},
+{194, 1060991140u, 2147497108u, 1063751062u, 0, CBRTF_TOLERANCE, 0},
+{195, 1061158912u, 2147497108u, 1063819112u, 0, CBRTF_TOLERANCE, 0},
+{196, 1061326684u, 2147497108u, 1063886561u, 0, CBRTF_TOLERANCE, 0},
+{197, 1061494456u, 2147497108u, 1063953420u, 0, CBRTF_TOLERANCE, 0},
+{198, 1061662228u, 2147497108u, 1064019703u, 0, CBRTF_TOLERANCE, 0},
+{199, 1061830001u, 2147497108u, 1064085421u, 0, CBRTF_TOLERANCE, 0},
+{200, 1061997773u, 2147497108u, 1064150588u, 0, CBRTF_TOLERANCE, 0},
+{201, 1062165545u, 2147497108u, 1064215213u, 0, CBRTF_TOLERANCE, 0},
+{202, 1062333317u, 2147497108u, 1064279309u, 0, CBRTF_TOLERANCE, 0},
+{203, 1062501089u, 2147497108u, 1064342886u, 0, CBRTF_TOLERANCE, 0},
+{204, 1062668861u, 2147497108u, 1064405954u, 0, CBRTF_TOLERANCE, 0},
+{205, 1062836634u, 2147497108u, 1064468524u, 0, CBRTF_TOLERANCE, 0},
+{206, 1063004406u, 2147497108u, 1064530605u, 0, CBRTF_TOLERANCE, 0},
+{207, 1063172178u, 2147497108u, 1064592206u, 0, CBRTF_TOLERANCE, 0},
+{208, 1063339950u, 2147497108u, 1064653337u, 0, CBRTF_TOLERANCE, 0},
+{209, 1063507722u, 2147497108u, 1064714007u, 0, CBRTF_TOLERANCE, 0},
+{210, 1063675494u, 2147497108u, 1064774224u, 0, CBRTF_TOLERANCE, 0},
+{211, 1063843267u, 2147497108u, 1064833997u, 0, CBRTF_TOLERANCE, 0},
+{212, 1064011039u, 2147497108u, 1064893333u, 0, CBRTF_TOLERANCE, 0},
+{213, 1064178811u, 2147497108u, 1064952241u, 0, CBRTF_TOLERANCE, 0},
+{214, 1064346583u, 2147497108u, 1065010728u, 0, CBRTF_TOLERANCE, 0},
+{215, 1064514355u, 2147497108u, 1065068801u, 0, CBRTF_TOLERANCE, 0},
+{216, 1064682127u, 2147497108u, 1065126469u, 0, CBRTF_TOLERANCE, 0},
+{217, 1064849900u, 2147497108u, 1065183738u, 0, CBRTF_TOLERANCE, 0},
+{218, 1065017672u, 2147497108u, 1065240614u, 0, CBRTF_TOLERANCE, 0},
+{219, 1065185444u, 2147497108u, 1065297104u, 0, CBRTF_TOLERANCE, 0},
+{220, 1065353216u, 2147497108u, 1065353216u, 0, CBRTF_TOLERANCE, 0},
+{221, 1065437102u, 2147497108u, 1065381085u, 0, CBRTF_TOLERANCE, 0},
+{222, 1065520988u, 2147497108u, 1065408771u, 0, CBRTF_TOLERANCE, 0},
+{223, 1065604874u, 2147497108u, 1065436277u, 0, CBRTF_TOLERANCE, 0},
+{224, 1065688760u, 2147497108u, 1065463605u, 0, CBRTF_TOLERANCE, 0},
+{225, 1065772646u, 2147497108u, 1065490759u, 0, CBRTF_TOLERANCE, 0},
+{226, 1065856532u, 2147497108u, 1065517740u, 0, CBRTF_TOLERANCE, 0},
+{227, 1065940419u, 2147497108u, 1065544553u, 0, CBRTF_TOLERANCE, 0},
+{228, 1066024305u, 2147497108u, 1065571199u, 0, CBRTF_TOLERANCE, 0},
+{229, 1066108191u, 2147497108u, 1065597681u, 0, CBRTF_TOLERANCE, 0},
+{230, 1066192077u, 2147497108u, 1065624001u, 0, CBRTF_TOLERANCE, 0},
+{231, 1066275963u, 2147497108u, 1065650163u, 0, CBRTF_TOLERANCE, 0},
+{232, 1066359849u, 2147497108u, 1065676168u, 0, CBRTF_TOLERANCE, 0},
+{233, 1066443735u, 2147497108u, 1065702018u, 0, CBRTF_TOLERANCE, 0},
+{234, 1066527621u, 2147497108u, 1065727716u, 0, CBRTF_TOLERANCE, 0},
+{235, 1066611507u, 2147497108u, 1065753265u, 0, CBRTF_TOLERANCE, 0},
+{236, 1066695393u, 2147497108u, 1065778666u, 0, CBRTF_TOLERANCE, 0},
+{237, 1066779279u, 2147497108u, 1065803921u, 0, CBRTF_TOLERANCE, 0},
+{238, 1066863165u, 2147497108u, 1065829033u, 0, CBRTF_TOLERANCE, 0},
+{239, 1066947052u, 2147497108u, 1065854003u, 0, CBRTF_TOLERANCE, 0},
+{240, 3234402267u, 2147497108u, 3219927504u, 0, CBRTF_TOLERANCE, 0},
+{241, 3231108068u, 2147497108u, 3218512086u, 0, CBRTF_TOLERANCE, 0},
+{242, 3226013659u, 2147497108u, 3216734143u, 0, CBRTF_TOLERANCE, 0},
+{243, 3217625051u, 2147497108u, 3214199571u, 0, CBRTF_TOLERANCE, 0},
+{244, 0u, 2147497108u, 0u, 0, CBRTF_TOLERANCE, 0},
+{245, 1070141403u, 2147497108u, 1066715923u, 0, CBRTF_TOLERANCE, 0},
+{246, 1078530011u, 2147497108u, 1069250495u, 0, CBRTF_TOLERANCE, 0},
+{247, 1083624420u, 2147497108u, 1071028438u, 0, CBRTF_TOLERANCE, 0},
+{248, 3253731328u, 2147497108u, 3225869542u, 0, CBRTF_TOLERANCE, 0},
+{249, 3252840038u, 2147497108u, 3225618567u, 0, CBRTF_TOLERANCE, 0},
+{250, 3251948749u, 2147497108u, 3225357329u, 0, CBRTF_TOLERANCE, 0},
+{251, 3251057459u, 2147497108u, 3225084709u, 0, CBRTF_TOLERANCE, 0},
+{252, 3250166170u, 2147497108u, 3224799381u, 0, CBRTF_TOLERANCE, 0},
+{253, 3249274880u, 2147497108u, 3224499751u, 0, CBRTF_TOLERANCE, 0},
+{254, 3248383590u, 2147497108u, 3224183879u, 0, CBRTF_TOLERANCE, 0},
+{255, 3247492301u, 2147497108u, 3223849368u, 0, CBRTF_TOLERANCE, 0},
+{256, 3246601011u, 2147497108u, 3223493199u, 0, CBRTF_TOLERANCE, 0},
+{257, 3245028147u, 2147497108u, 3223111482u, 0, CBRTF_TOLERANCE, 0},
+{258, 3243245568u, 2147497108u, 3222699076u, 0, CBRTF_TOLERANCE, 0},
+{259, 3241462989u, 2147497108u, 3222248954u, 0, CBRTF_TOLERANCE, 0},
+{260, 3239680410u, 2147497108u, 3221751090u, 0, CBRTF_TOLERANCE, 0},
+{261, 3237792973u, 2147497108u, 3221155274u, 0, CBRTF_TOLERANCE, 0},
+{262, 3234227814u, 2147497108u, 3219858888u, 0, CBRTF_TOLERANCE, 0},
+{263, 3230662656u, 2147497108u, 3218297543u, 0, CBRTF_TOLERANCE, 0},
+{264, 3224580915u, 2147497108u, 3216271661u, 0, CBRTF_TOLERANCE, 0},
+{265, 3213675725u, 2147497108u, 3213107649u, 0, CBRTF_TOLERANCE, 0},
+{266, 1058642330u, 2147497108u, 1062726452u, 0, CBRTF_TOLERANCE, 0},
+{267, 1075000115u, 2147497108u, 1068037622u, 0, CBRTF_TOLERANCE, 0},
+{268, 1082130432u, 2147497108u, 1070280693u, 0, CBRTF_TOLERANCE, 0},
+{269, 1085695590u, 2147497108u, 1071949313u, 0, CBRTF_TOLERANCE, 0},
+{270, 1089260749u, 2147497108u, 1073311448u, 0, CBRTF_TOLERANCE, 0},
+{271, 1091672474u, 2147497108u, 1074109914u, 0, CBRTF_TOLERANCE, 0},
+{272, 1093455053u, 2147497108u, 1074624385u, 0, CBRTF_TOLERANCE, 0},
+{273, 1095237632u, 2147497108u, 1075087333u, 0, CBRTF_TOLERANCE, 0},
+{274, 1097020211u, 2147497108u, 1075509995u, 0, CBRTF_TOLERANCE, 0},
+{275, 1098802790u, 2147497108u, 1075900135u, 0, CBRTF_TOLERANCE, 0},
+{276, 1099746509u, 2147497108u, 1076263368u, 0, CBRTF_TOLERANCE, 0},
+{277, 1100637798u, 2147497108u, 1076603902u, 0, CBRTF_TOLERANCE, 0},
+{278, 1101529088u, 2147497108u, 1076924983u, 0, CBRTF_TOLERANCE, 0},
+{279, 1102420378u, 2147497108u, 1077229170u, 0, CBRTF_TOLERANCE, 0},
+{280, 1103311667u, 2147497108u, 1077518526u, 0, CBRTF_TOLERANCE, 0},
+{281, 1104202957u, 2147497108u, 1077794735u, 0, CBRTF_TOLERANCE, 0},
+{282, 1105094246u, 2147497108u, 1078059196u, 0, CBRTF_TOLERANCE, 0},
+{283, 1105985536u, 2147497108u, 1078313084u, 0, CBRTF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_CBRTF_H multiple inclusion protection
+
+// EOF cbrtf.h
diff --git a/packages/language/c/libm/current/tests/vectors/ceilf.c b/packages/language/c/libm/current/tests/vectors/ceilf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/ceilf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      ceilf.c
+//
+//      Test of ceilf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/ceilf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(ceilf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &ceilf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &ceilf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("ceilf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("ceilf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library ceilf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "ceilf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF ceilf.c
diff --git a/packages/language/c/libm/current/tests/vectors/ceilf.h b/packages/language/c/libm/current/tests/vectors/ceilf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/ceilf.h
@@ -0,0 +1,1048 @@
+#ifndef CYGONCE_LIBM_CEILF_H
+#define CYGONCE_LIBM_CEILF_H
+//===========================================================================
+//
+//      ceilf.h
+//
+//      Test vectors for testing of ceilf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/ceilf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define CEILF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t ceilf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 0u, 3212836864u, 0, CEILF_TOLERANCE, 0},
+{1, 3214430700u, 0u, 3212836864u, 0, CEILF_TOLERANCE, 0},
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+{888, 1078478376u, 1326246424u, 1082130432u, 0, CEILF_TOLERANCE, 0},
+{889, 1165177679u, 3276237026u, 1165180928u, 0, CEILF_TOLERANCE, 0},
+{890, 3403009513u, 3381966453u, 3403009512u, 0, CEILF_TOLERANCE, 0},
+{891, 952348506u, 3377573987u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{892, 1222777442u, 1125769920u, 1222777472u, 0, CEILF_TOLERANCE, 0},
+{893, 1325324763u, 978336043u, 1325324763u, 0, CEILF_TOLERANCE, 0},
+{894, 3363524213u, 3202991311u, 3363524160u, 0, CEILF_TOLERANCE, 0},
+{895, 1158950321u, 1073578913u, 1158950912u, 0, CEILF_TOLERANCE, 0},
+{896, 903129873u, 3416864271u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{897, 1208345407u, 1254181270u, 1208345408u, 0, CEILF_TOLERANCE, 0},
+{898, 1258634105u, 1247426200u, 1258634105u, 0, CEILF_TOLERANCE, 0},
+{899, 1248478509u, 1287895126u, 1248478512u, 0, CEILF_TOLERANCE, 0},
+{900, 1153863988u, 3430539165u, 1153867776u, 0, CEILF_TOLERANCE, 0},
+{901, 1235620969u, 866627358u, 1235620976u, 0, CEILF_TOLERANCE, 0},
+{902, 1097120930u, 3221726305u, 1097859072u, 0, CEILF_TOLERANCE, 0},
+{903, 3469778622u, 1200179013u, 3469778622u, 0, CEILF_TOLERANCE, 0},
+{904, 1147712200u, 931865525u, 1147715584u, 0, CEILF_TOLERANCE, 0},
+{905, 1124721745u, 3058969650u, 1124728832u, 0, CEILF_TOLERANCE, 0},
+{906, 3261744304u, 1043806501u, 3261595648u, 0, CEILF_TOLERANCE, 0},
+{907, 1064922416u, 1320485628u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{908, 3303160152u, 3075455322u, 3303153664u, 0, CEILF_TOLERANCE, 0},
+{909, 1315090496u, 3269683237u, 1315090496u, 0, CEILF_TOLERANCE, 0},
+{910, 3230403187u, 1322841992u, 3229614080u, 0, CEILF_TOLERANCE, 0},
+{911, 1335399673u, 974138676u, 1335399673u, 0, CEILF_TOLERANCE, 0},
+{912, 1072458508u, 3372833993u, 1073741824u, 0, CEILF_TOLERANCE, 0},
+{913, 3303015249u, 3015039539u, 3303014400u, 0, CEILF_TOLERANCE, 0},
+{914, 3252139741u, 1059615003u, 3251634176u, 0, CEILF_TOLERANCE, 0},
+{915, 3468519966u, 3113982619u, 3468519966u, 0, CEILF_TOLERANCE, 0},
+{916, 1006231203u, 897530770u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{917, 951554138u, 1001144381u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{918, 942046828u, 986341002u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{919, 3319723279u, 3414482416u, 3319721984u, 0, CEILF_TOLERANCE, 0},
+{920, 3255104167u, 928827688u, 3255042048u, 0, CEILF_TOLERANCE, 0},
+{921, 1155477903u, 3104812800u, 1155481600u, 0, CEILF_TOLERANCE, 0},
+{922, 3273889176u, 980486479u, 3273850880u, 0, CEILF_TOLERANCE, 0},
+{923, 3237813668u, 3441016803u, 3235905536u, 0, CEILF_TOLERANCE, 0},
+{924, 1228207362u, 2985476579u, 1228207376u, 0, CEILF_TOLERANCE, 0},
+{925, 975349337u, 1311932596u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{926, 1290175785u, 3008182462u, 1290175786u, 0, CEILF_TOLERANCE, 0},
+{927, 981908840u, 3314038398u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{928, 941187647u, 1107765599u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{929, 1214223128u, 3225536822u, 1214223168u, 0, CEILF_TOLERANCE, 0},
+{930, 3422922584u, 1086391131u, 3422922584u, 0, CEILF_TOLERANCE, 0},
+{931, 1315857601u, 3487600045u, 1315857601u, 0, CEILF_TOLERANCE, 0},
+{932, 3453226030u, 3233768835u, 3453226030u, 0, CEILF_TOLERANCE, 0},
+{933, 1078359574u, 3199175230u, 1082130432u, 0, CEILF_TOLERANCE, 0},
+{934, 1029557624u, 3302959071u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{935, 1207675424u, 3042692550u, 1207675520u, 0, CEILF_TOLERANCE, 0},
+{936, 1028355074u, 3442294040u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{937, 1248421894u, 3367769132u, 1248421896u, 0, CEILF_TOLERANCE, 0},
+{938, 3353251994u, 1095517730u, 3353251968u, 0, CEILF_TOLERANCE, 0},
+{939, 876926659u, 3288089977u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{940, 1076752219u, 876236939u, 1077936128u, 0, CEILF_TOLERANCE, 0},
+{941, 3388531942u, 2988520062u, 3388531936u, 0, CEILF_TOLERANCE, 0},
+{942, 1273395082u, 3031189261u, 1273395082u, 0, CEILF_TOLERANCE, 0},
+{943, 3385588183u, 3258252464u, 3385588176u, 0, CEILF_TOLERANCE, 0},
+{944, 3441804648u, 3274638356u, 3441804648u, 0, CEILF_TOLERANCE, 0},
+{945, 3392827417u, 1277961150u, 3392827416u, 0, CEILF_TOLERANCE, 0},
+{946, 1161241793u, 1328003707u, 1161244672u, 0, CEILF_TOLERANCE, 0},
+{947, 1171318485u, 3374409104u, 1171318784u, 0, CEILF_TOLERANCE, 0},
+{948, 1001216371u, 3052357038u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{949, 912515889u, 1074635609u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{950, 3391452505u, 897989232u, 3391452504u, 0, CEILF_TOLERANCE, 0},
+{951, 3249603369u, 3147662248u, 3249537024u, 0, CEILF_TOLERANCE, 0},
+{952, 1220264047u, 2960450369u, 1220264064u, 0, CEILF_TOLERANCE, 0},
+{953, 3282212423u, 3174079140u, 3282206720u, 0, CEILF_TOLERANCE, 0},
+{954, 3352293320u, 3247843425u, 3352293248u, 0, CEILF_TOLERANCE, 0},
+{955, 3296358441u, 875645354u, 3296346112u, 0, CEILF_TOLERANCE, 0},
+{956, 1197828352u, 3245614728u, 1197828352u, 0, CEILF_TOLERANCE, 0},
+{957, 3340510371u, 914930263u, 3340510208u, 0, CEILF_TOLERANCE, 0},
+{958, 1127109339u, 3368125489u, 1127153664u, 0, CEILF_TOLERANCE, 0},
+{959, 909467381u, 1232375752u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{960, 1200599955u, 2981200675u, 1200600064u, 0, CEILF_TOLERANCE, 0},
+{961, 962230977u, 2988248037u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{962, 3237183876u, 3179379969u, 3235905536u, 0, CEILF_TOLERANCE, 0},
+{963, 939285924u, 3056079386u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{964, 944050180u, 3452557879u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{965, 3480592662u, 3261728191u, 3480592662u, 0, CEILF_TOLERANCE, 0},
+{966, 1003299981u, 853295521u, 1065353216u, 0, CEILF_TOLERANCE, 0},
+{967, 1155775526u, 1255814444u, 1155776512u, 0, CEILF_TOLERANCE, 0},
+{968, 1234491880u, 3408568717u, 1234491888u, 0, CEILF_TOLERANCE, 0},
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_CEILF_H multiple inclusion protection
+
+// EOF ceilf.h
diff --git a/packages/language/c/libm/current/tests/vectors/copysignf.c b/packages/language/c/libm/current/tests/vectors/copysignf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/copysignf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      copysignf.c
+//
+//      Test of copysignf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/copysignf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(copysignf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &copysignf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_FLOAT, CYG_LIBM_TEST_VEC_FLOAT,
+                     &copysignf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("copysignf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("copysignf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library copysignf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "copysignf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF copysignf.c
diff --git a/packages/language/c/libm/current/tests/vectors/copysignf.h b/packages/language/c/libm/current/tests/vectors/copysignf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/copysignf.h
@@ -0,0 +1,2551 @@
+#ifndef CYGONCE_LIBM_COPYSIGNF_H
+#define CYGONCE_LIBM_COPYSIGNF_H
+//===========================================================================
+//
+//      copysignf.h
+//
+//      Test vectors for testing of copysignf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/copysignf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define COPYSIGNF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t copysignf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3212836864u, 3212836864u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{1, 3212836864u, 3211998003u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{2, 3212836864u, 3211159142u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{3, 3212836864u, 3210320282u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{4, 3212836864u, 3209481421u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{5, 3212836864u, 3208642560u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{6, 3212836864u, 3207803699u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{7, 3212836864u, 3206964838u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{8, 3212836864u, 3206125978u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{9, 3212836864u, 3205287117u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{10, 3212836864u, 3204448256u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{11, 3212836864u, 3202770534u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{12, 3212836864u, 3201092813u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{13, 3212836864u, 3199415091u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{14, 3212836864u, 3197737370u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{15, 3212836864u, 3196059648u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{16, 3212836864u, 3192704205u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{17, 3212836864u, 3189348762u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{18, 3212836864u, 3184315597u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{19, 3212836864u, 3175926989u, 3212836864u, 0, COPYSIGNF_TOLERANCE, 0},
+{20, 3212836864u, 632815616u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{21, 3212836864u, 1028443341u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{22, 3212836864u, 1036831949u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{23, 3212836864u, 1041865114u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{24, 3212836864u, 1045220557u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{25, 3212836864u, 1048576000u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{26, 3212836864u, 1050253722u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{27, 3212836864u, 1051931443u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{28, 3212836864u, 1053609165u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{29, 3212836864u, 1055286886u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{30, 3212836864u, 1056964608u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{31, 3212836864u, 1057803469u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{32, 3212836864u, 1058642330u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{33, 3212836864u, 1059481190u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{34, 3212836864u, 1060320051u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{35, 3212836864u, 1061158912u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{36, 3212836864u, 1061997773u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{37, 3212836864u, 1062836634u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{38, 3212836864u, 1063675494u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{39, 3212836864u, 1064514355u, 1065353216u, 0, COPYSIGNF_TOLERANCE, 0},
+{40, 3211998003u, 3212836864u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{41, 3211998003u, 3211998003u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{42, 3211998003u, 3211159142u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{43, 3211998003u, 3210320282u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{44, 3211998003u, 3209481421u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{45, 3211998003u, 3208642560u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{46, 3211998003u, 3207803699u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{47, 3211998003u, 3206964838u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{48, 3211998003u, 3206125978u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{49, 3211998003u, 3205287117u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{50, 3211998003u, 3204448256u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{51, 3211998003u, 3202770534u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{52, 3211998003u, 3201092813u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{53, 3211998003u, 3199415091u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{54, 3211998003u, 3197737370u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{55, 3211998003u, 3196059648u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{56, 3211998003u, 3192704205u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{57, 3211998003u, 3189348762u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{58, 3211998003u, 3184315597u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{59, 3211998003u, 3175926989u, 3211998003u, 0, COPYSIGNF_TOLERANCE, 0},
+{60, 3211998003u, 632815616u, 1064514355u, 0, COPYSIGNF_TOLERANCE, 0},
+{61, 3211998003u, 1028443341u, 1064514355u, 0, COPYSIGNF_TOLERANCE, 0},
+{62, 3211998003u, 1036831949u, 1064514355u, 0, COPYSIGNF_TOLERANCE, 0},
+{63, 3211998003u, 1041865114u, 1064514355u, 0, COPYSIGNF_TOLERANCE, 0},
+{64, 3211998003u, 1045220557u, 1064514355u, 0, COPYSIGNF_TOLERANCE, 0},
+{65, 3211998003u, 1048576000u, 1064514355u, 0, COPYSIGNF_TOLERANCE, 0},
+{66, 3211998003u, 1050253722u, 1064514355u, 0, COPYSIGNF_TOLERANCE, 0},
+{67, 3211998003u, 1051931443u, 1064514355u, 0, COPYSIGNF_TOLERANCE, 0},
+{68, 3211998003u, 1053609165u, 1064514355u, 0, COPYSIGNF_TOLERANCE, 0},
+{69, 3211998003u, 1055286886u, 1064514355u, 0, COPYSIGNF_TOLERANCE, 0},
+{70, 3211998003u, 1056964608u, 1064514355u, 0, COPYSIGNF_TOLERANCE, 0},
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+{2331, 996404791u, 3353251979u, 3143888439u, 0, COPYSIGNF_TOLERANCE, 0},
+{2332, 1188439315u, 1113484271u, 1188439315u, 0, COPYSIGNF_TOLERANCE, 0},
+{2333, 906557513u, 3006513432u, 3054041161u, 0, COPYSIGNF_TOLERANCE, 0},
+{2334, 916831283u, 999465787u, 916831283u, 0, COPYSIGNF_TOLERANCE, 0},
+{2335, 996786317u, 3179221951u, 3144269965u, 0, COPYSIGNF_TOLERANCE, 0},
+{2336, 3461635065u, 1004690387u, 1314151417u, 0, COPYSIGNF_TOLERANCE, 0},
+{2337, 1188167943u, 1200744896u, 1188167943u, 0, COPYSIGNF_TOLERANCE, 0},
+{2338, 3036502395u, 1172597364u, 889018747u, 0, COPYSIGNF_TOLERANCE, 0},
+{2339, 891257783u, 1267560050u, 891257783u, 0, COPYSIGNF_TOLERANCE, 0},
+{2340, 3290079438u, 846519377u, 1142595790u, 0, COPYSIGNF_TOLERANCE, 0},
+{2341, 3350690327u, 2967953392u, 3350690327u, 0, COPYSIGNF_TOLERANCE, 0},
+{2342, 1102061604u, 3424449935u, 3249545252u, 0, COPYSIGNF_TOLERANCE, 0},
+{2343, 1282351521u, 3039376424u, 3429835169u, 0, COPYSIGNF_TOLERANCE, 0},
+{2344, 3458861065u, 3392466405u, 3458861065u, 0, COPYSIGNF_TOLERANCE, 0},
+{2345, 3095256878u, 1023623326u, 947773230u, 0, COPYSIGNF_TOLERANCE, 0},
+{2346, 3163373610u, 843150426u, 1015889962u, 0, COPYSIGNF_TOLERANCE, 0},
+{2347, 3228793330u, 855146890u, 1081309682u, 0, COPYSIGNF_TOLERANCE, 0},
+{2348, 3422194733u, 893873945u, 1274711085u, 0, COPYSIGNF_TOLERANCE, 0},
+{2349, 3083885296u, 974543672u, 936401648u, 0, COPYSIGNF_TOLERANCE, 0},
+{2350, 1261940623u, 3402349985u, 3409424271u, 0, COPYSIGNF_TOLERANCE, 0},
+{2351, 3400603081u, 3234396843u, 3400603081u, 0, COPYSIGNF_TOLERANCE, 0},
+{2352, 1219411812u, 2961857939u, 3366895460u, 0, COPYSIGNF_TOLERANCE, 0},
+{2353, 3094833770u, 805351108u, 947350122u, 0, COPYSIGNF_TOLERANCE, 0},
+{2354, 3139250800u, 3079109479u, 3139250800u, 0, COPYSIGNF_TOLERANCE, 0},
+{2355, 886201503u, 3272760705u, 3033685151u, 0, COPYSIGNF_TOLERANCE, 0},
+{2356, 3297366026u, 1089966380u, 1149882378u, 0, COPYSIGNF_TOLERANCE, 0},
+{2357, 1218488455u, 3309646450u, 3365972103u, 0, COPYSIGNF_TOLERANCE, 0},
+{2358, 3040358923u, 3093401553u, 3040358923u, 0, COPYSIGNF_TOLERANCE, 0},
+{2359, 1283938137u, 1196383822u, 1283938137u, 0, COPYSIGNF_TOLERANCE, 0},
+{2360, 3182551696u, 3029982441u, 3182551696u, 0, COPYSIGNF_TOLERANCE, 0},
+{2361, 1317098613u, 949986176u, 1317098613u, 0, COPYSIGNF_TOLERANCE, 0},
+{2362, 3116209179u, 3303588342u, 3116209179u, 0, COPYSIGNF_TOLERANCE, 0},
+{2363, 3431703657u, 3014443710u, 3431703657u, 0, COPYSIGNF_TOLERANCE, 0},
+{2364, 3239728775u, 927815421u, 1092245127u, 0, COPYSIGNF_TOLERANCE, 0},
+{2365, 3207141672u, 933456504u, 1059658024u, 0, COPYSIGNF_TOLERANCE, 0},
+{2366, 3154378805u, 905462392u, 1006895157u, 0, COPYSIGNF_TOLERANCE, 0},
+{2367, 3069658155u, 1041452042u, 922174507u, 0, COPYSIGNF_TOLERANCE, 0},
+{2368, 3313160088u, 2964063309u, 3313160088u, 0, COPYSIGNF_TOLERANCE, 0},
+{2369, 3207056527u, 3384206601u, 3207056527u, 0, COPYSIGNF_TOLERANCE, 0},
+{2370, 1284174954u, 3436881197u, 3431658602u, 0, COPYSIGNF_TOLERANCE, 0},
+{2371, 3156081645u, 3308839704u, 3156081645u, 0, COPYSIGNF_TOLERANCE, 0},
+{2372, 1063693032u, 976661408u, 1063693032u, 0, COPYSIGNF_TOLERANCE, 0},
+{2373, 3036026175u, 1251203998u, 888542527u, 0, COPYSIGNF_TOLERANCE, 0},
+{2374, 1102631663u, 3396951425u, 3250115311u, 0, COPYSIGNF_TOLERANCE, 0},
+{2375, 968803479u, 992989712u, 968803479u, 0, COPYSIGNF_TOLERANCE, 0},
+{2376, 3273080388u, 3109405906u, 3273080388u, 0, COPYSIGNF_TOLERANCE, 0},
+{2377, 1172529774u, 3294550127u, 3320013422u, 0, COPYSIGNF_TOLERANCE, 0},
+{2378, 1306695905u, 1292690378u, 1306695905u, 0, COPYSIGNF_TOLERANCE, 0},
+{2379, 1003649752u, 1218792138u, 1003649752u, 0, COPYSIGNF_TOLERANCE, 0},
+{2380, 1078478376u, 1326246424u, 1078478376u, 0, COPYSIGNF_TOLERANCE, 0},
+{2381, 3158855023u, 3151283866u, 3158855023u, 0, COPYSIGNF_TOLERANCE, 0},
+{2382, 1165177679u, 3276237026u, 3312661327u, 0, COPYSIGNF_TOLERANCE, 0},
+{2383, 3403009513u, 3381966453u, 3403009513u, 0, COPYSIGNF_TOLERANCE, 0},
+{2384, 952348506u, 3377573987u, 3099832154u, 0, COPYSIGNF_TOLERANCE, 0},
+{2385, 1222777442u, 1125769920u, 1222777442u, 0, COPYSIGNF_TOLERANCE, 0},
+{2386, 1325324763u, 978336043u, 1325324763u, 0, COPYSIGNF_TOLERANCE, 0},
+{2387, 3363524213u, 3202991311u, 3363524213u, 0, COPYSIGNF_TOLERANCE, 0},
+{2388, 1158950321u, 1073578913u, 1158950321u, 0, COPYSIGNF_TOLERANCE, 0},
+{2389, 903129873u, 3416864271u, 3050613521u, 0, COPYSIGNF_TOLERANCE, 0},
+{2390, 3078339944u, 988173985u, 930856296u, 0, COPYSIGNF_TOLERANCE, 0},
+{2391, 1208345407u, 1254181270u, 1208345407u, 0, COPYSIGNF_TOLERANCE, 0},
+{2392, 1258634105u, 1247426200u, 1258634105u, 0, COPYSIGNF_TOLERANCE, 0},
+{2393, 1248478509u, 1287895126u, 1248478509u, 0, COPYSIGNF_TOLERANCE, 0},
+{2394, 1153863988u, 3430539165u, 3301347636u, 0, COPYSIGNF_TOLERANCE, 0},
+{2395, 1235620969u, 866627358u, 1235620969u, 0, COPYSIGNF_TOLERANCE, 0},
+{2396, 1097120930u, 3221726305u, 3244604578u, 0, COPYSIGNF_TOLERANCE, 0},
+{2397, 3469778622u, 1200179013u, 1322294974u, 0, COPYSIGNF_TOLERANCE, 0},
+{2398, 1147712200u, 931865525u, 1147712200u, 0, COPYSIGNF_TOLERANCE, 0},
+{2399, 1124721745u, 3058969650u, 3272205393u, 0, COPYSIGNF_TOLERANCE, 0},
+{2400, 3261744304u, 1043806501u, 1114260656u, 0, COPYSIGNF_TOLERANCE, 0},
+{2401, 1064922416u, 1320485628u, 1064922416u, 0, COPYSIGNF_TOLERANCE, 0},
+{2402, 3303160152u, 3075455322u, 3303160152u, 0, COPYSIGNF_TOLERANCE, 0},
+{2403, 1315090496u, 3269683237u, 3462574144u, 0, COPYSIGNF_TOLERANCE, 0},
+{2404, 3230403187u, 1322841992u, 1082919539u, 0, COPYSIGNF_TOLERANCE, 0},
+{2405, 1335399673u, 974138676u, 1335399673u, 0, COPYSIGNF_TOLERANCE, 0},
+{2406, 1072458508u, 3372833993u, 3219942156u, 0, COPYSIGNF_TOLERANCE, 0},
+{2407, 3303015249u, 3015039539u, 3303015249u, 0, COPYSIGNF_TOLERANCE, 0},
+{2408, 3252139741u, 1059615003u, 1104656093u, 0, COPYSIGNF_TOLERANCE, 0},
+{2409, 3468519966u, 3113982619u, 3468519966u, 0, COPYSIGNF_TOLERANCE, 0},
+{2410, 1006231203u, 897530770u, 1006231203u, 0, COPYSIGNF_TOLERANCE, 0},
+{2411, 951554138u, 1001144381u, 951554138u, 0, COPYSIGNF_TOLERANCE, 0},
+{2412, 942046828u, 986341002u, 942046828u, 0, COPYSIGNF_TOLERANCE, 0},
+{2413, 3319723279u, 3414482416u, 3319723279u, 0, COPYSIGNF_TOLERANCE, 0},
+{2414, 3255104167u, 928827688u, 1107620519u, 0, COPYSIGNF_TOLERANCE, 0},
+{2415, 1155477903u, 3104812800u, 3302961551u, 0, COPYSIGNF_TOLERANCE, 0},
+{2416, 3273889176u, 980486479u, 1126405528u, 0, COPYSIGNF_TOLERANCE, 0},
+{2417, 3237813668u, 3441016803u, 3237813668u, 0, COPYSIGNF_TOLERANCE, 0},
+{2418, 1228207362u, 2985476579u, 3375691010u, 0, COPYSIGNF_TOLERANCE, 0},
+{2419, 975349337u, 1311932596u, 975349337u, 0, COPYSIGNF_TOLERANCE, 0},
+{2420, 1290175785u, 3008182462u, 3437659433u, 0, COPYSIGNF_TOLERANCE, 0},
+{2421, 981908840u, 3314038398u, 3129392488u, 0, COPYSIGNF_TOLERANCE, 0},
+{2422, 941187647u, 1107765599u, 941187647u, 0, COPYSIGNF_TOLERANCE, 0},
+{2423, 1214223128u, 3225536822u, 3361706776u, 0, COPYSIGNF_TOLERANCE, 0},
+{2424, 3422922584u, 1086391131u, 1275438936u, 0, COPYSIGNF_TOLERANCE, 0},
+{2425, 1315857601u, 3487600045u, 3463341249u, 0, COPYSIGNF_TOLERANCE, 0},
+{2426, 3453226030u, 3233768835u, 3453226030u, 0, COPYSIGNF_TOLERANCE, 0},
+{2427, 1078359574u, 3199175230u, 3225843222u, 0, COPYSIGNF_TOLERANCE, 0},
+{2428, 1029557624u, 3302959071u, 3177041272u, 0, COPYSIGNF_TOLERANCE, 0},
+{2429, 1207675424u, 3042692550u, 3355159072u, 0, COPYSIGNF_TOLERANCE, 0},
+{2430, 1028355074u, 3442294040u, 3175838722u, 0, COPYSIGNF_TOLERANCE, 0},
+{2431, 3119299090u, 1187096397u, 971815442u, 0, COPYSIGNF_TOLERANCE, 0},
+{2432, 1248421894u, 3367769132u, 3395905542u, 0, COPYSIGNF_TOLERANCE, 0},
+{2433, 3353251994u, 1095517730u, 1205768346u, 0, COPYSIGNF_TOLERANCE, 0},
+{2434, 876926659u, 3288089977u, 3024410307u, 0, COPYSIGNF_TOLERANCE, 0},
+{2435, 1076752219u, 876236939u, 1076752219u, 0, COPYSIGNF_TOLERANCE, 0},
+{2436, 3388531942u, 2988520062u, 3388531942u, 0, COPYSIGNF_TOLERANCE, 0},
+{2437, 1273395082u, 3031189261u, 3420878730u, 0, COPYSIGNF_TOLERANCE, 0},
+{2438, 3385588183u, 3258252464u, 3385588183u, 0, COPYSIGNF_TOLERANCE, 0},
+{2439, 3192315328u, 3289489214u, 3192315328u, 0, COPYSIGNF_TOLERANCE, 0},
+{2440, 3441804648u, 3274638356u, 3441804648u, 0, COPYSIGNF_TOLERANCE, 0},
+{2441, 3392827417u, 1277961150u, 1245343769u, 0, COPYSIGNF_TOLERANCE, 0},
+{2442, 1161241793u, 1328003707u, 1161241793u, 0, COPYSIGNF_TOLERANCE, 0},
+{2443, 3034494183u, 3041579130u, 3034494183u, 0, COPYSIGNF_TOLERANCE, 0},
+{2444, 1171318485u, 3374409104u, 3318802133u, 0, COPYSIGNF_TOLERANCE, 0},
+{2445, 3047748143u, 831102792u, 900264495u, 0, COPYSIGNF_TOLERANCE, 0},
+{2446, 1001216371u, 3052357038u, 3148700019u, 0, COPYSIGNF_TOLERANCE, 0},
+{2447, 912515889u, 1074635609u, 912515889u, 0, COPYSIGNF_TOLERANCE, 0},
+{2448, 3391452505u, 897989232u, 1243968857u, 0, COPYSIGNF_TOLERANCE, 0},
+{2449, 3249603369u, 3147662248u, 3249603369u, 0, COPYSIGNF_TOLERANCE, 0},
+{2450, 1220264047u, 2960450369u, 3367747695u, 0, COPYSIGNF_TOLERANCE, 0},
+{2451, 3169816394u, 988430929u, 1022332746u, 0, COPYSIGNF_TOLERANCE, 0},
+{2452, 3098997418u, 3002162688u, 3098997418u, 0, COPYSIGNF_TOLERANCE, 0},
+{2453, 3282212423u, 3174079140u, 3282212423u, 0, COPYSIGNF_TOLERANCE, 0},
+{2454, 3352293320u, 3247843425u, 3352293320u, 0, COPYSIGNF_TOLERANCE, 0},
+{2455, 3296358441u, 875645354u, 1148874793u, 0, COPYSIGNF_TOLERANCE, 0},
+{2456, 1197828352u, 3245614728u, 3345312000u, 0, COPYSIGNF_TOLERANCE, 0},
+{2457, 3340510371u, 914930263u, 1193026723u, 0, COPYSIGNF_TOLERANCE, 0},
+{2458, 1127109339u, 3368125489u, 3274592987u, 0, COPYSIGNF_TOLERANCE, 0},
+{2459, 909467381u, 1232375752u, 909467381u, 0, COPYSIGNF_TOLERANCE, 0},
+{2460, 1200599955u, 2981200675u, 3348083603u, 0, COPYSIGNF_TOLERANCE, 0},
+{2461, 962230977u, 2988248037u, 3109714625u, 0, COPYSIGNF_TOLERANCE, 0},
+{2462, 3192887808u, 3191848339u, 3192887808u, 0, COPYSIGNF_TOLERANCE, 0},
+{2463, 3237183876u, 3179379969u, 3237183876u, 0, COPYSIGNF_TOLERANCE, 0},
+{2464, 939285924u, 3056079386u, 3086769572u, 0, COPYSIGNF_TOLERANCE, 0},
+{2465, 944050180u, 3452557879u, 3091533828u, 0, COPYSIGNF_TOLERANCE, 0},
+{2466, 3058135703u, 3090284601u, 3058135703u, 0, COPYSIGNF_TOLERANCE, 0},
+{2467, 3480592662u, 3261728191u, 3480592662u, 0, COPYSIGNF_TOLERANCE, 0},
+{2468, 3061939312u, 3274418540u, 3061939312u, 0, COPYSIGNF_TOLERANCE, 0},
+{2469, 1003299981u, 853295521u, 1003299981u, 0, COPYSIGNF_TOLERANCE, 0},
+{2470, 1155775526u, 1255814444u, 1155775526u, 0, COPYSIGNF_TOLERANCE, 0},
+{2471, 1234491880u, 3408568717u, 3381975528u, 0, COPYSIGNF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_COPYSIGNF_H multiple inclusion protection
+
+// EOF copysignf.h
diff --git a/packages/language/c/libm/current/tests/vectors/cosf.c b/packages/language/c/libm/current/tests/vectors/cosf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/cosf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      cosf.c
+//
+//      Test of cosf() math library function
+//
+//===========================================================================
+// ####ECOSFGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSFGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/cosf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(cosf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &cosf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &cosf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("cosf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("cosf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library cosf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "cosf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF cosf.c
diff --git a/packages/language/c/libm/current/tests/vectors/cosf.h b/packages/language/c/libm/current/tests/vectors/cosf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/cosf.h
@@ -0,0 +1,1234 @@
+#ifndef CYGONCE_LIBM_COSF_H
+#define CYGONCE_LIBM_COSF_H
+//===========================================================================
+//
+//      cosf.h
+//
+//      Test vectors for testing of cosf() math library function
+//
+//===========================================================================
+// ####ECOSFGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSFGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/cosf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define COSF_TOLERANCE 1.0E4
+
+static const Cyg_libm_test_float_vec_t cosf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 0u, 1052346099u, 0, COSF_TOLERANCE, 0},
+{1, 3214430700u, 0u, 1052658226u, 0, COSF_TOLERANCE, 0},
+{2, 3214346813u, 0u, 1052969110u, 0, COSF_TOLERANCE, 0},
+{3, 3214262927u, 0u, 1053278711u, 0, COSF_TOLERANCE, 0},
+{4, 3214179041u, 0u, 1053587004u, 0, COSF_TOLERANCE, 0},
+{5, 3214095155u, 0u, 1053893957u, 0, COSF_TOLERANCE, 0},
+{6, 3214011269u, 0u, 1054199539u, 0, COSF_TOLERANCE, 0},
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+{1122, 3192315328u, 3289489214u, 1065037827u, 0, COSF_TOLERANCE, 0},
+{1123, 3441804648u, 3274638356u, 3194945623u, 0, COSF_TOLERANCE, 0},
+{1124, 3392827417u, 1277961150u, 3210261568u, 0, COSF_TOLERANCE, 0},
+{1125, 1161241793u, 1328003707u, 3207641762u, 0, COSF_TOLERANCE, 0},
+{1126, 3034494183u, 3041579130u, 1065353216u, 0, COSF_TOLERANCE, 0},
+{1127, 1171318485u, 3374409104u, 1063645118u, 0, COSF_TOLERANCE, 0},
+{1128, 3047748143u, 831102792u, 1065353216u, 0, COSF_TOLERANCE, 0},
+{1129, 1001216371u, 3052357038u, 1065352981u, 0, COSF_TOLERANCE, 0},
+{1130, 912515889u, 1074635609u, 1065353216u, 0, COSF_TOLERANCE, 0},
+{1131, 3391452505u, 897989232u, 3209655482u, 0, COSF_TOLERANCE, 0},
+{1132, 3249603369u, 3147662248u, 3212683322u, 0, COSF_TOLERANCE, 0},
+{1133, 1220264047u, 2960450369u, 3212372154u, 0, COSF_TOLERANCE, 0},
+{1134, 3169816394u, 988430929u, 1065346043u, 0, COSF_TOLERANCE, 0},
+{1135, 3098997418u, 3002162688u, 1065353216u, 0, COSF_TOLERANCE, 0},
+{1136, 3282212423u, 3174079140u, 1016941376u, 0, COSF_TOLERANCE, 0},
+{1137, 3352293320u, 3247843425u, 1050107930u, 0, COSF_TOLERANCE, 0},
+{1138, 3296358441u, 875645354u, 3211409002u, 0, COSF_TOLERANCE, 0},
+{1139, 1197828352u, 3245614728u, 1065315648u, 0, COSF_TOLERANCE, 0},
+{1140, 3340510371u, 914930263u, 1057806643u, 0, COSF_TOLERANCE, 0},
+{1141, 1127109339u, 3368125489u, 3171828278u, 0, COSF_TOLERANCE, 0},
+{1142, 909467381u, 1232375752u, 1065353216u, 0, COSF_TOLERANCE, 0},
+{1143, 1200599955u, 2981200675u, 1058314411u, 0, COSF_TOLERANCE, 0},
+{1144, 962230977u, 2988248037u, 1065353216u, 0, COSF_TOLERANCE, 0},
+{1145, 3192887808u, 3191848339u, 1065009608u, 0, COSF_TOLERANCE, 0},
+{1146, 3237183876u, 3179379969u, 1048038805u, 0, COSF_TOLERANCE, 0},
+{1147, 939285924u, 3056079386u, 1065353216u, 0, COSF_TOLERANCE, 0},
+{1148, 944050180u, 3452557879u, 1065353216u, 0, COSF_TOLERANCE, 0},
+{1149, 3058135703u, 3090284601u, 1065353216u, 0, COSF_TOLERANCE, 0},
+{1150, 3480592662u, 3261728191u, 3210584153u, 0, COSF_TOLERANCE, 0},
+{1151, 3061939312u, 3274418540u, 1065353216u, 0, COSF_TOLERANCE, 0},
+{1152, 1003299981u, 853295521u, 1065352887u, 0, COSF_TOLERANCE, 0},
+{1153, 1155775526u, 1255814444u, 1064855858u, 0, COSF_TOLERANCE, 0},
+{1154, 1234491880u, 3408568717u, 1047219695u, 0, COSF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_COSF_H multiple inclusion protection
+
+// EOF cosf.h
diff --git a/packages/language/c/libm/current/tests/vectors/coshf.c b/packages/language/c/libm/current/tests/vectors/coshf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/coshf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      coshf.c
+//
+//      Test of coshf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/coshf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(coshf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &coshf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &coshf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("coshf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("coshf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library coshf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "coshf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF coshf.c
diff --git a/packages/language/c/libm/current/tests/vectors/coshf.h b/packages/language/c/libm/current/tests/vectors/coshf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/coshf.h
@@ -0,0 +1,517 @@
+#ifndef CYGONCE_LIBM_COSH_H
+#define CYGONCE_LIBM_COSH_H
+//===========================================================================
+//
+//      coshf.h
+//
+//      Test vectors for testing of coshf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/coshf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define COSH_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t coshf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 1072153489u, 1072153489u, 0, COSH_TOLERANCE, 0},
+{1, 3214430700u, 1072027623u, 1072027623u, 0, COSH_TOLERANCE, 0},
+{2, 3214346813u, 1071903263u, 1071903263u, 0, COSH_TOLERANCE, 0},
+{3, 3214262927u, 1071780397u, 1071780397u, 0, COSH_TOLERANCE, 0},
+{4, 3214179041u, 1071659013u, 1071659013u, 0, COSH_TOLERANCE, 0},
+{5, 3214095155u, 1071539100u, 1071539100u, 0, COSH_TOLERANCE, 0},
+{6, 3214011269u, 1071420643u, 1071420643u, 0, COSH_TOLERANCE, 0},
+{7, 3213927383u, 1071303632u, 1071303632u, 0, COSH_TOLERANCE, 0},
+{8, 3213843497u, 1071188056u, 1071188056u, 0, COSH_TOLERANCE, 0},
+{9, 3213759611u, 1071073900u, 1071073900u, 0, COSH_TOLERANCE, 0},
+{10, 3213675725u, 1070961157u, 1070961157u, 0, COSH_TOLERANCE, 0},
+{11, 3213591839u, 1070849813u, 1070849813u, 0, COSH_TOLERANCE, 0},
+{12, 3213507953u, 1070739857u, 1070739857u, 0, COSH_TOLERANCE, 0},
+{13, 3213424067u, 1070631278u, 1070631278u, 0, COSH_TOLERANCE, 0},
+{14, 3213340180u, 1070524066u, 1070524066u, 0, COSH_TOLERANCE, 0},
+{15, 3213256294u, 1070418210u, 1070418210u, 0, COSH_TOLERANCE, 0},
+{16, 3213172408u, 1070313701u, 1070313701u, 0, COSH_TOLERANCE, 0},
+{17, 3213088522u, 1070210525u, 1070210525u, 0, COSH_TOLERANCE, 0},
+{18, 3213004636u, 1070108675u, 1070108675u, 0, COSH_TOLERANCE, 0},
+{19, 3212920750u, 1070008138u, 1070008138u, 0, COSH_TOLERANCE, 0},
+{20, 3212836864u, 1069908906u, 1069908906u, 0, COSH_TOLERANCE, 0},
+{21, 3212669092u, 1069810970u, 1069810970u, 0, COSH_TOLERANCE, 0},
+{22, 3212501320u, 1069714317u, 1069714317u, 0, COSH_TOLERANCE, 0},
+{23, 3212333548u, 1069618939u, 1069618939u, 0, COSH_TOLERANCE, 0},
+{24, 3212165775u, 1069524826u, 1069524826u, 0, COSH_TOLERANCE, 0},
+{25, 3211998003u, 1069431969u, 1069431969u, 0, COSH_TOLERANCE, 0},
+{26, 3211830231u, 1069340360u, 1069340360u, 0, COSH_TOLERANCE, 0},
+{27, 3211662459u, 1069249988u, 1069249988u, 0, COSH_TOLERANCE, 0},
+{28, 3211494687u, 1069160844u, 1069160844u, 0, COSH_TOLERANCE, 0},
+{29, 3211326915u, 1069072921u, 1069072921u, 0, COSH_TOLERANCE, 0},
+{30, 3211159142u, 1068986208u, 1068986208u, 0, COSH_TOLERANCE, 0},
+{31, 3210991370u, 1068900697u, 1068900697u, 0, COSH_TOLERANCE, 0},
+{32, 3210823598u, 1068816380u, 1068816380u, 0, COSH_TOLERANCE, 0},
+{33, 3210655826u, 1068733248u, 1068733248u, 0, COSH_TOLERANCE, 0},
+{34, 3210488054u, 1068651292u, 1068651292u, 0, COSH_TOLERANCE, 0},
+{35, 3210320282u, 1068570506u, 1068570506u, 0, COSH_TOLERANCE, 0},
+{36, 3210152509u, 1068490879u, 1068490879u, 0, COSH_TOLERANCE, 0},
+{37, 3209984737u, 1068412406u, 1068412406u, 0, COSH_TOLERANCE, 0},
+{38, 3209816965u, 1068335079u, 1068335079u, 0, COSH_TOLERANCE, 0},
+{39, 3209649193u, 1068258888u, 1068258888u, 0, COSH_TOLERANCE, 0},
+{40, 3209481421u, 1068183826u, 1068183826u, 0, COSH_TOLERANCE, 0},
+{41, 3209313649u, 1068109886u, 1068109886u, 0, COSH_TOLERANCE, 0},
+{42, 3209145876u, 1068037060u, 1068037060u, 0, COSH_TOLERANCE, 0},
+{43, 3208978104u, 1067965341u, 1067965341u, 0, COSH_TOLERANCE, 0},
+{44, 3208810332u, 1067894723u, 1067894723u, 0, COSH_TOLERANCE, 0},
+{45, 3208642560u, 1067825198u, 1067825198u, 0, COSH_TOLERANCE, 0},
+{46, 3208474788u, 1067756759u, 1067756759u, 0, COSH_TOLERANCE, 0},
+{47, 3208307016u, 1067689400u, 1067689400u, 0, COSH_TOLERANCE, 0},
+{48, 3208139244u, 1067623113u, 1067623113u, 0, COSH_TOLERANCE, 0},
+{49, 3207971471u, 1067557890u, 1067557890u, 0, COSH_TOLERANCE, 0},
+{50, 3207803699u, 1067493729u, 1067493729u, 0, COSH_TOLERANCE, 0},
+{51, 3207635927u, 1067430620u, 1067430620u, 0, COSH_TOLERANCE, 0},
+{52, 3207468155u, 1067368557u, 1067368557u, 0, COSH_TOLERANCE, 0},
+{53, 3207300383u, 1067307535u, 1067307535u, 0, COSH_TOLERANCE, 0},
+{54, 3207132611u, 1067247547u, 1067247547u, 0, COSH_TOLERANCE, 0},
+{55, 3206964838u, 1067188587u, 1067188587u, 0, COSH_TOLERANCE, 0},
+{56, 3206797066u, 1067130650u, 1067130650u, 0, COSH_TOLERANCE, 0},
+{57, 3206629294u, 1067073729u, 1067073729u, 0, COSH_TOLERANCE, 0},
+{58, 3206461522u, 1067017820u, 1067017820u, 0, COSH_TOLERANCE, 0},
+{59, 3206293750u, 1066962916u, 1066962916u, 0, COSH_TOLERANCE, 0},
+{60, 3206125978u, 1066909011u, 1066909011u, 0, COSH_TOLERANCE, 0},
+{61, 3205958205u, 1066856101u, 1066856101u, 0, COSH_TOLERANCE, 0},
+{62, 3205790433u, 1066804180u, 1066804180u, 0, COSH_TOLERANCE, 0},
+{63, 3205622661u, 1066753243u, 1066753243u, 0, COSH_TOLERANCE, 0},
+{64, 3205454889u, 1066703285u, 1066703285u, 0, COSH_TOLERANCE, 0},
+{65, 3205287117u, 1066654301u, 1066654301u, 0, COSH_TOLERANCE, 0},
+{66, 3205119345u, 1066606286u, 1066606286u, 0, COSH_TOLERANCE, 0},
+{67, 3204951572u, 1066559235u, 1066559235u, 0, COSH_TOLERANCE, 0},
+{68, 3204783800u, 1066513143u, 1066513143u, 0, COSH_TOLERANCE, 0},
+{69, 3204616028u, 1066468007u, 1066468007u, 0, COSH_TOLERANCE, 0},
+{70, 3204448256u, 1066423820u, 1066423820u, 0, COSH_TOLERANCE, 0},
+{71, 3204112712u, 1066380580u, 1066380580u, 0, COSH_TOLERANCE, 0},
+{72, 3203777167u, 1066338281u, 1066338281u, 0, COSH_TOLERANCE, 0},
+{73, 3203441623u, 1066296920u, 1066296920u, 0, COSH_TOLERANCE, 0},
+{74, 3203106079u, 1066256491u, 1066256491u, 0, COSH_TOLERANCE, 0},
+{75, 3202770534u, 1066216992u, 1066216992u, 0, COSH_TOLERANCE, 0},
+{76, 3202434990u, 1066178419u, 1066178419u, 0, COSH_TOLERANCE, 0},
+{77, 3202099446u, 1066140766u, 1066140766u, 0, COSH_TOLERANCE, 0},
+{78, 3201763901u, 1066104032u, 1066104032u, 0, COSH_TOLERANCE, 0},
+{79, 3201428357u, 1066068211u, 1066068211u, 0, COSH_TOLERANCE, 0},
+{80, 3201092813u, 1066033300u, 1066033300u, 0, COSH_TOLERANCE, 0},
+{81, 3200757268u, 1065999297u, 1065999297u, 0, COSH_TOLERANCE, 0},
+{82, 3200421724u, 1065966197u, 1065966197u, 0, COSH_TOLERANCE, 0},
+{83, 3200086180u, 1065933997u, 1065933997u, 0, COSH_TOLERANCE, 0},
+{84, 3199750636u, 1065902694u, 1065902694u, 0, COSH_TOLERANCE, 0},
+{85, 3199415091u, 1065872285u, 1065872285u, 0, COSH_TOLERANCE, 0},
+{86, 3199079547u, 1065842767u, 1065842767u, 0, COSH_TOLERANCE, 0},
+{87, 3198744003u, 1065814136u, 1065814136u, 0, COSH_TOLERANCE, 0},
+{88, 3198408458u, 1065786390u, 1065786390u, 0, COSH_TOLERANCE, 0},
+{89, 3198072914u, 1065759527u, 1065759527u, 0, COSH_TOLERANCE, 0},
+{90, 3197737370u, 1065733543u, 1065733543u, 0, COSH_TOLERANCE, 0},
+{91, 3197401825u, 1065708436u, 1065708436u, 0, COSH_TOLERANCE, 0},
+{92, 3197066281u, 1065684204u, 1065684204u, 0, COSH_TOLERANCE, 0},
+{93, 3196730737u, 1065660843u, 1065660843u, 0, COSH_TOLERANCE, 0},
+{94, 3196395192u, 1065638352u, 1065638352u, 0, COSH_TOLERANCE, 0},
+{95, 3196059648u, 1065616728u, 1065616728u, 0, COSH_TOLERANCE, 0},
+{96, 3195388559u, 1065595970u, 1065595970u, 0, COSH_TOLERANCE, 0},
+{97, 3194717471u, 1065576075u, 1065576075u, 0, COSH_TOLERANCE, 0},
+{98, 3194046382u, 1065557040u, 1065557040u, 0, COSH_TOLERANCE, 0},
+{99, 3193375293u, 1065538865u, 1065538865u, 0, COSH_TOLERANCE, 0},
+{100, 3192704205u, 1065521548u, 1065521548u, 0, COSH_TOLERANCE, 0},
+{101, 3192033116u, 1065505086u, 1065505086u, 0, COSH_TOLERANCE, 0},
+{102, 3191362028u, 1065489479u, 1065489479u, 0, COSH_TOLERANCE, 0},
+{103, 3190690939u, 1065474723u, 1065474723u, 0, COSH_TOLERANCE, 0},
+{104, 3190019850u, 1065460819u, 1065460819u, 0, COSH_TOLERANCE, 0},
+{105, 3189348762u, 1065447765u, 1065447765u, 0, COSH_TOLERANCE, 0},
+{106, 3188677673u, 1065435559u, 1065435559u, 0, COSH_TOLERANCE, 0},
+{107, 3188006584u, 1065424200u, 1065424200u, 0, COSH_TOLERANCE, 0},
+{108, 3186999951u, 1065413686u, 1065413686u, 0, COSH_TOLERANCE, 0},
+{109, 3185657774u, 1065404018u, 1065404018u, 0, COSH_TOLERANCE, 0},
+{110, 3184315597u, 1065395194u, 1065395194u, 0, COSH_TOLERANCE, 0},
+{111, 3182973420u, 1065387213u, 1065387213u, 0, COSH_TOLERANCE, 0},
+{112, 3181631242u, 1065380074u, 1065380074u, 0, COSH_TOLERANCE, 0},
+{113, 3180289065u, 1065373776u, 1065373776u, 0, COSH_TOLERANCE, 0},
+{114, 3178611343u, 1065368320u, 1065368320u, 0, COSH_TOLERANCE, 0},
+{115, 3175926989u, 1065363704u, 1065363704u, 0, COSH_TOLERANCE, 0},
+{116, 3173242634u, 1065359928u, 1065359928u, 0, COSH_TOLERANCE, 0},
+{117, 3170222735u, 1065356991u, 1065356991u, 0, COSH_TOLERANCE, 0},
+{118, 3164854026u, 1065354894u, 1065354894u, 0, COSH_TOLERANCE, 0},
+{119, 3156465418u, 1065353635u, 1065353635u, 0, COSH_TOLERANCE, 0},
+{120, 1008981770u, 1065353635u, 1065353635u, 0, COSH_TOLERANCE, 0},
+{121, 1017370378u, 1065354894u, 1065354894u, 0, COSH_TOLERANCE, 0},
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+{344, 3273269173u, 3434026174u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{345, 1135545828u, 1254918706u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{346, 1135988587u, 3461361185u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{347, 3283879654u, 3253874001u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{348, 3274295536u, 1139193797u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{349, 1134855236u, 3334899880u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{350, 1121073826u, 3064047808u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{351, 1133146865u, 870681806u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{352, 1123929207u, 3104759211u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{353, 3286633183u, 3331372071u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{354, 3267729753u, 1111437780u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{355, 1138742759u, 1009396165u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{356, 1119456624u, 928393353u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{357, 1129220730u, 3148135875u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{358, 3282572423u, 3023584354u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{359, 3286124867u, 3444030332u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{360, 1123536012u, 3278686216u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{361, 1129936658u, 3079166173u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{362, 3267758292u, 3481843070u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{363, 1126423020u, 3487506626u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{364, 1136073813u, 3488844154u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{365, 3270332384u, 1182798837u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{366, 1131115907u, 3176633124u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{367, 3284070129u, 1331845018u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{368, 3278696475u, 3107114149u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{369, 1127951444u, 825129857u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{370, 1129418756u, 811863044u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{371, 1126654193u, 961171401u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{372, 3271088163u, 3066326686u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{373, 1130359793u, 957302464u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{374, 1138775588u, 2985592532u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{375, 3282114235u, 1284049853u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{376, 3267398588u, 3271879112u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{377, 1120256985u, 1219003129u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{378, 1137354019u, 1166078045u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{379, 3267924701u, 2953541915u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{380, 1139056475u, 3396371713u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{381, 3282508977u, 3033299853u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{382, 3279527710u, 3333091960u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{383, 3276970123u, 1174967495u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{384, 1131911667u, 966031619u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{385, 3275501055u, 3029593823u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{386, 3280406230u, 1017987696u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{387, 1120190670u, 850632217u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{388, 3275370769u, 3069778532u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{389, 1134651039u, 3387555900u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{390, 1128329544u, 3228401212u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{391, 3278970989u, 1260217257u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{392, 1121118397u, 1087951909u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{393, 3270894457u, 869285240u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{394, 3274377473u, 3060143904u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{395, 1140495091u, 3003675365u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{396, 3273091864u, 3260140004u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{397, 3283145875u, 966439623u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{398, 3279997240u, 3205527253u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{399, 3275779969u, 3165561391u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{400, 1128236602u, 3119707283u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{401, 1119873837u, 894348966u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{402, 1129518015u, 1296370667u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{403, 3285580500u, 823220784u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{404, 3272701000u, 2997091781u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{405, 1133497567u, 1010219988u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{406, 3284538233u, 3096700943u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{407, 3283473802u, 1209565017u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{408, 3283716643u, 2960476959u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{409, 1123896707u, 1291336083u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{410, 3283491469u, 3066966245u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{411, 3277490267u, 3465211174u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{412, 3285474297u, 1004690387u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{413, 1131356577u, 3039376424u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{414, 3282700297u, 3392466405u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{415, 3271199789u, 893873945u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{416, 1119334287u, 3402349985u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{417, 1124554585u, 1196383822u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{418, 1132549237u, 949986176u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{419, 3272320105u, 3014443710u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{420, 1124791402u, 3436881197u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{421, 1130535137u, 1292690378u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{422, 3268791785u, 3381966453u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{423, 1140775387u, 978336043u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{424, 1122649389u, 1287895126u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{425, 3285229246u, 1200179013u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{426, 1138929728u, 3269683237u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{427, 1134073081u, 974138676u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{428, 3283970590u, 3113982619u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{429, 1130792233u, 3008182462u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{430, 3271927640u, 1086391131u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{431, 1139696833u, 3487600045u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{432, 3277065262u, 3233768835u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{433, 1122592774u, 3367769132u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{434, 1122400138u, 3031189261u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{435, 3274032488u, 3274638356u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{436, 3266998297u, 1277961150u, 2139095040u, 0, COSH_TOLERANCE, 0},
+{437, 3287654678u, 3261728191u, 2139095040u, 0, COSH_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_COSH_H multiple inclusion protection
+
+// EOF coshf.h
diff --git a/packages/language/c/libm/current/tests/vectors/erfcf.c b/packages/language/c/libm/current/tests/vectors/erfcf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/erfcf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      erfcf.c
+//
+//      Test of erfcf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####EERFFGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/erfcf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(erfcf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &erfcf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &erfcf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("erfcf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("erfcf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library erfcf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "erfcf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF erfcf.c
diff --git a/packages/language/c/libm/current/tests/vectors/erfcf.h b/packages/language/c/libm/current/tests/vectors/erfcf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/erfcf.h
@@ -0,0 +1,361 @@
+#ifndef CYGONCE_LIBM_ERFCF_H
+#define CYGONCE_LIBM_ERFCF_H
+//===========================================================================
+//
+//      erfcf.h
+//
+//      Test vectors for testing of erfcf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####EERFCFGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/erfcf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define ERFCF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t erfcf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 2147493556u, 1072989483u, 0, ERFCF_TOLERANCE, 0},
+{1, 3214430700u, 2147493556u, 1072966786u, 0, ERFCF_TOLERANCE, 0},
+{2, 3214346813u, 2147493556u, 1072943542u, 0, ERFCF_TOLERANCE, 0},
+{3, 3214262927u, 2147493556u, 1072919744u, 0, ERFCF_TOLERANCE, 0},
+{4, 3214179041u, 2147493556u, 1072895382u, 0, ERFCF_TOLERANCE, 0},
+{5, 3214095155u, 2147493556u, 1072870448u, 0, ERFCF_TOLERANCE, 0},
+{6, 3214011269u, 2147493556u, 1072844934u, 0, ERFCF_TOLERANCE, 0},
+{7, 3213927383u, 2147493556u, 1072818831u, 0, ERFCF_TOLERANCE, 0},
+{8, 3213843497u, 2147493556u, 1072792132u, 0, ERFCF_TOLERANCE, 0},
+{9, 3213759611u, 2147493556u, 1072764828u, 0, ERFCF_TOLERANCE, 0},
+{10, 3213675725u, 2147493556u, 1072736911u, 0, ERFCF_TOLERANCE, 0},
+{11, 3213591839u, 2147493556u, 1072708374u, 0, ERFCF_TOLERANCE, 0},
+{12, 3213507953u, 2147493556u, 1072679207u, 0, ERFCF_TOLERANCE, 0},
+{13, 3213424067u, 2147493556u, 1072649403u, 0, ERFCF_TOLERANCE, 0},
+{14, 3213340180u, 2147493556u, 1072618955u, 0, ERFCF_TOLERANCE, 0},
+{15, 3213256294u, 2147493556u, 1072587854u, 0, ERFCF_TOLERANCE, 0},
+{16, 3213172408u, 2147493556u, 1072556094u, 0, ERFCF_TOLERANCE, 0},
+{17, 3213088522u, 2147493556u, 1072523666u, 0, ERFCF_TOLERANCE, 0},
+{18, 3213004636u, 2147493556u, 1072490563u, 0, ERFCF_TOLERANCE, 0},
+{19, 3212920750u, 2147493556u, 1072456777u, 0, ERFCF_TOLERANCE, 0},
+{20, 3212836864u, 2147493556u, 1072422303u, 0, ERFCF_TOLERANCE, 0},
+{21, 3212669092u, 2147493556u, 1072387132u, 0, ERFCF_TOLERANCE, 0},
+{22, 3212501320u, 2147493556u, 1072351257u, 0, ERFCF_TOLERANCE, 0},
+{23, 3212333548u, 2147493556u, 1072314673u, 0, ERFCF_TOLERANCE, 0},
+{24, 3212165775u, 2147493556u, 1072277371u, 0, ERFCF_TOLERANCE, 0},
+{25, 3211998003u, 2147493556u, 1072239347u, 0, ERFCF_TOLERANCE, 0},
+{26, 3211662459u, 2147493556u, 1072161105u, 0, ERFCF_TOLERANCE, 0},
+{27, 3211494687u, 2147493556u, 1072120874u, 0, ERFCF_TOLERANCE, 0},
+{28, 3211326915u, 2147493556u, 1072079897u, 0, ERFCF_TOLERANCE, 0},
+{29, 3211159142u, 2147493556u, 1072038167u, 0, ERFCF_TOLERANCE, 0},
+{30, 3210991370u, 2147493556u, 1071995679u, 0, ERFCF_TOLERANCE, 0},
+{31, 3210823598u, 2147493556u, 1071952428u, 0, ERFCF_TOLERANCE, 0},
+{32, 3210655826u, 2147493556u, 1071908409u, 0, ERFCF_TOLERANCE, 0},
+{33, 3210488054u, 2147493556u, 1071863617u, 0, ERFCF_TOLERANCE, 0},
+{34, 3210320282u, 2147493556u, 1071818048u, 0, ERFCF_TOLERANCE, 0},
+{35, 3210152509u, 2147493556u, 1071771698u, 0, ERFCF_TOLERANCE, 0},
+{36, 3209984737u, 2147493556u, 1071724563u, 0, ERFCF_TOLERANCE, 0},
+{37, 3209816965u, 2147493556u, 1071676639u, 0, ERFCF_TOLERANCE, 0},
+{38, 3209649193u, 2147493556u, 1071627922u, 0, ERFCF_TOLERANCE, 0},
+{39, 3209481421u, 2147493556u, 1071578410u, 0, ERFCF_TOLERANCE, 0},
+{40, 3209313649u, 2147493556u, 1071528099u, 0, ERFCF_TOLERANCE, 0},
+{41, 3209145876u, 2147493556u, 1071476987u, 0, ERFCF_TOLERANCE, 0},
+{42, 3208978104u, 2147493556u, 1071425072u, 0, ERFCF_TOLERANCE, 0},
+{43, 3208810332u, 2147493556u, 1071372351u, 0, ERFCF_TOLERANCE, 0},
+{44, 3208642560u, 2147493556u, 1071318822u, 0, ERFCF_TOLERANCE, 0},
+{45, 3208474788u, 2147493556u, 1071264484u, 0, ERFCF_TOLERANCE, 0},
+{46, 3208307016u, 2147493556u, 1071209336u, 0, ERFCF_TOLERANCE, 0},
+{47, 3208139244u, 2147493556u, 1071153378u, 0, ERFCF_TOLERANCE, 0},
+{48, 3207971471u, 2147493556u, 1071096607u, 0, ERFCF_TOLERANCE, 0},
+{49, 3207803699u, 2147493556u, 1071039024u, 0, ERFCF_TOLERANCE, 0},
+{50, 3207635927u, 2147493556u, 1070980630u, 0, ERFCF_TOLERANCE, 0},
+{51, 3207468155u, 2147493556u, 1070921425u, 0, ERFCF_TOLERANCE, 0},
+{52, 3207300383u, 2147493556u, 1070861409u, 0, ERFCF_TOLERANCE, 0},
+{53, 3207132611u, 2147493556u, 1070800583u, 0, ERFCF_TOLERANCE, 0},
+{54, 3206964838u, 2147493556u, 1070738948u, 0, ERFCF_TOLERANCE, 0},
+{55, 3206797066u, 2147493556u, 1070676508u, 0, ERFCF_TOLERANCE, 0},
+{56, 3206629294u, 2147493556u, 1070613263u, 0, ERFCF_TOLERANCE, 0},
+{57, 3206461522u, 2147493556u, 1070549216u, 0, ERFCF_TOLERANCE, 0},
+{58, 3206293750u, 2147493556u, 1070484370u, 0, ERFCF_TOLERANCE, 0},
+{59, 3206125978u, 2147493556u, 1070418728u, 0, ERFCF_TOLERANCE, 0},
+{60, 3205958205u, 2147493556u, 1070352294u, 0, ERFCF_TOLERANCE, 0},
+{61, 3205790433u, 2147493556u, 1070285071u, 0, ERFCF_TOLERANCE, 0},
+{62, 3205622661u, 2147493556u, 1070217063u, 0, ERFCF_TOLERANCE, 0},
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+{273, 1098802790u, 2147493556u, 0u, 0, ERFCF_TOLERANCE, 0},
+{274, 1099746509u, 2147493556u, 0u, 0, ERFCF_TOLERANCE, 0},
+{275, 1100637798u, 2147493556u, 0u, 0, ERFCF_TOLERANCE, 0},
+{276, 1101529088u, 2147493556u, 0u, 0, ERFCF_TOLERANCE, 0},
+{277, 1102420378u, 2147493556u, 0u, 0, ERFCF_TOLERANCE, 0},
+{278, 1103311667u, 2147493556u, 0u, 0, ERFCF_TOLERANCE, 0},
+{279, 1104202957u, 2147493556u, 0u, 0, ERFCF_TOLERANCE, 0},
+{280, 1105094246u, 2147493556u, 0u, 0, ERFCF_TOLERANCE, 0},
+{281, 1105985536u, 2147493556u, 0u, 0, ERFCF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_ERFCF_H multiple inclusion protection
+
+// EOF erfcf.h
diff --git a/packages/language/c/libm/current/tests/vectors/erff.c b/packages/language/c/libm/current/tests/vectors/erff.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/erff.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      erff.c
+//
+//      Test of erff() math library function
+//
+//===========================================================================
+// ####EERFFGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####EERFFGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/erff.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(erff_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &erff, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &erff_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("erff() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("erff() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library erff() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "erff() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF erff.c
diff --git a/packages/language/c/libm/current/tests/vectors/erff.h b/packages/language/c/libm/current/tests/vectors/erff.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/erff.h
@@ -0,0 +1,361 @@
+#ifndef CYGONCE_LIBM_ERFF_H
+#define CYGONCE_LIBM_ERFF_H
+//===========================================================================
+//
+//      erff.h
+//
+//      Test vectors for testing of erff() math library function
+//
+//===========================================================================
+// ####EERFFGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####EERFFGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/erff.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define ERFF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t erff_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 2147516072u, 3211332182u, 0, ERFF_TOLERANCE, 0},
+{1, 3214430700u, 2147516072u, 3211286788u, 0, ERFF_TOLERANCE, 0},
+{2, 3214346813u, 2147516072u, 3211240301u, 0, ERFF_TOLERANCE, 0},
+{3, 3214262927u, 2147516072u, 3211192703u, 0, ERFF_TOLERANCE, 0},
+{4, 3214179041u, 2147516072u, 3211143979u, 0, ERFF_TOLERANCE, 0},
+{5, 3214095155u, 2147516072u, 3211094111u, 0, ERFF_TOLERANCE, 0},
+{6, 3214011269u, 2147516072u, 3211043083u, 0, ERFF_TOLERANCE, 0},
+{7, 3213927383u, 2147516072u, 3210990878u, 0, ERFF_TOLERANCE, 0},
+{8, 3213843497u, 2147516072u, 3210937480u, 0, ERFF_TOLERANCE, 0},
+{9, 3213759611u, 2147516072u, 3210882872u, 0, ERFF_TOLERANCE, 0},
+{10, 3213675725u, 2147516072u, 3210827039u, 0, ERFF_TOLERANCE, 0},
+{11, 3213591839u, 2147516072u, 3210769963u, 0, ERFF_TOLERANCE, 0},
+{12, 3213507953u, 2147516072u, 3210711630u, 0, ERFF_TOLERANCE, 0},
+{13, 3213424067u, 2147516072u, 3210652023u, 0, ERFF_TOLERANCE, 0},
+{14, 3213340180u, 2147516072u, 3210591126u, 0, ERFF_TOLERANCE, 0},
+{15, 3213256294u, 2147516072u, 3210528924u, 0, ERFF_TOLERANCE, 0},
+{16, 3213172408u, 2147516072u, 3210465403u, 0, ERFF_TOLERANCE, 0},
+{17, 3213088522u, 2147516072u, 3210400547u, 0, ERFF_TOLERANCE, 0},
+{18, 3213004636u, 2147516072u, 3210334341u, 0, ERFF_TOLERANCE, 0},
+{19, 3212920750u, 2147516072u, 3210266770u, 0, ERFF_TOLERANCE, 0},
+{20, 3212836864u, 2147516072u, 3210197821u, 0, ERFF_TOLERANCE, 0},
+{21, 3212669092u, 2147516072u, 3210127479u, 0, ERFF_TOLERANCE, 0},
+{22, 3212501320u, 2147516072u, 3210055730u, 0, ERFF_TOLERANCE, 0},
+{23, 3212333548u, 2147516072u, 3209982561u, 0, ERFF_TOLERANCE, 0},
+{24, 3212165775u, 2147516072u, 3209907959u, 0, ERFF_TOLERANCE, 0},
+{25, 3211998003u, 2147516072u, 3209831910u, 0, ERFF_TOLERANCE, 0},
+{26, 3211662459u, 2147516072u, 3209675425u, 0, ERFF_TOLERANCE, 0},
+{27, 3211494687u, 2147516072u, 3209594964u, 0, ERFF_TOLERANCE, 0},
+{28, 3211326915u, 2147516072u, 3209513009u, 0, ERFF_TOLERANCE, 0},
+{29, 3211159142u, 2147516072u, 3209429548u, 0, ERFF_TOLERANCE, 0},
+{30, 3210991370u, 2147516072u, 3209344573u, 0, ERFF_TOLERANCE, 0},
+{31, 3210823598u, 2147516072u, 3209258071u, 0, ERFF_TOLERANCE, 0},
+{32, 3210655826u, 2147516072u, 3209170033u, 0, ERFF_TOLERANCE, 0},
+{33, 3210488054u, 2147516072u, 3209080450u, 0, ERFF_TOLERANCE, 0},
+{34, 3210320282u, 2147516072u, 3208989312u, 0, ERFF_TOLERANCE, 0},
+{35, 3210152509u, 2147516072u, 3208896612u, 0, ERFF_TOLERANCE, 0},
+{36, 3209984737u, 2147516072u, 3208802342u, 0, ERFF_TOLERANCE, 0},
+{37, 3209816965u, 2147516072u, 3208706493u, 0, ERFF_TOLERANCE, 0},
+{38, 3209649193u, 2147516072u, 3208609060u, 0, ERFF_TOLERANCE, 0},
+{39, 3209481421u, 2147516072u, 3208510036u, 0, ERFF_TOLERANCE, 0},
+{40, 3209313649u, 2147516072u, 3208409415u, 0, ERFF_TOLERANCE, 0},
+{41, 3209145876u, 2147516072u, 3208307190u, 0, ERFF_TOLERANCE, 0},
+{42, 3208978104u, 2147516072u, 3208203360u, 0, ERFF_TOLERANCE, 0},
+{43, 3208810332u, 2147516072u, 3208097918u, 0, ERFF_TOLERANCE, 0},
+{44, 3208642560u, 2147516072u, 3207990860u, 0, ERFF_TOLERANCE, 0},
+{45, 3208474788u, 2147516072u, 3207882184u, 0, ERFF_TOLERANCE, 0},
+{46, 3208307016u, 2147516072u, 3207771889u, 0, ERFF_TOLERANCE, 0},
+{47, 3208139244u, 2147516072u, 3207659971u, 0, ERFF_TOLERANCE, 0},
+{48, 3207971471u, 2147516072u, 3207546430u, 0, ERFF_TOLERANCE, 0},
+{49, 3207803699u, 2147516072u, 3207431265u, 0, ERFF_TOLERANCE, 0},
+{50, 3207635927u, 2147516072u, 3207314476u, 0, ERFF_TOLERANCE, 0},
+{51, 3207468155u, 2147516072u, 3207196066u, 0, ERFF_TOLERANCE, 0},
+{52, 3207300383u, 2147516072u, 3207076033u, 0, ERFF_TOLERANCE, 0},
+{53, 3207132611u, 2147516072u, 3206954381u, 0, ERFF_TOLERANCE, 0},
+{54, 3206964838u, 2147516072u, 3206831112u, 0, ERFF_TOLERANCE, 0},
+{55, 3206797066u, 2147516072u, 3206706232u, 0, ERFF_TOLERANCE, 0},
+{56, 3206629294u, 2147516072u, 3206579741u, 0, ERFF_TOLERANCE, 0},
+{57, 3206461522u, 2147516072u, 3206451648u, 0, ERFF_TOLERANCE, 0},
+{58, 3206293750u, 2147516072u, 3206321956u, 0, ERFF_TOLERANCE, 0},
+{59, 3206125978u, 2147516072u, 3206190672u, 0, ERFF_TOLERANCE, 0},
+{60, 3205958205u, 2147516072u, 3206057802u, 0, ERFF_TOLERANCE, 0},
+{61, 3205790433u, 2147516072u, 3205923357u, 0, ERFF_TOLERANCE, 0},
+{62, 3205622661u, 2147516072u, 3205787343u, 0, ERFF_TOLERANCE, 0},
+{63, 3205454889u, 2147516072u, 3205649769u, 0, ERFF_TOLERANCE, 0},
+{64, 3205287117u, 2147516072u, 3205510646u, 0, ERFF_TOLERANCE, 0},
+{65, 3205119345u, 2147516072u, 3205369984u, 0, ERFF_TOLERANCE, 0},
+{66, 3204951572u, 2147516072u, 3205227794u, 0, ERFF_TOLERANCE, 0},
+{67, 3204783800u, 2147516072u, 3205084089u, 0, ERFF_TOLERANCE, 0},
+{68, 3204616028u, 2147516072u, 3204938882u, 0, ERFF_TOLERANCE, 0},
+{69, 3204448256u, 2147516072u, 3204792187u, 0, ERFF_TOLERANCE, 0},
+{70, 3204112712u, 2147516072u, 3204644016u, 0, ERFF_TOLERANCE, 0},
+{71, 3203777167u, 2147516072u, 3204494388u, 0, ERFF_TOLERANCE, 0},
+{72, 3203441623u, 2147516072u, 3204238374u, 0, ERFF_TOLERANCE, 0},
+{73, 3203106079u, 2147516072u, 3203933377u, 0, ERFF_TOLERANCE, 0},
+{74, 3202770534u, 2147516072u, 3203625559u, 0, ERFF_TOLERANCE, 0},
+{75, 3202434990u, 2147516072u, 3203314959u, 0, ERFF_TOLERANCE, 0},
+{76, 3202099446u, 2147516072u, 3203001614u, 0, ERFF_TOLERANCE, 0},
+{77, 3201763901u, 2147516072u, 3202685561u, 0, ERFF_TOLERANCE, 0},
+{78, 3201428357u, 2147516072u, 3202366844u, 0, ERFF_TOLERANCE, 0},
+{79, 3201092813u, 2147516072u, 3202045502u, 0, ERFF_TOLERANCE, 0},
+{80, 3200757268u, 2147516072u, 3201721579u, 0, ERFF_TOLERANCE, 0},
+{81, 3200421724u, 2147516072u, 3201395120u, 0, ERFF_TOLERANCE, 0},
+{82, 3200086180u, 2147516072u, 3201066170u, 0, ERFF_TOLERANCE, 0},
+{83, 3199750636u, 2147516072u, 3200734777u, 0, ERFF_TOLERANCE, 0},
+{84, 3199415091u, 2147516072u, 3200400989u, 0, ERFF_TOLERANCE, 0},
+{85, 3199079547u, 2147516072u, 3200064857u, 0, ERFF_TOLERANCE, 0},
+{86, 3198744003u, 2147516072u, 3199726432u, 0, ERFF_TOLERANCE, 0},
+{87, 3198408458u, 2147516072u, 3199385764u, 0, ERFF_TOLERANCE, 0},
+{88, 3198072914u, 2147516072u, 3199042911u, 0, ERFF_TOLERANCE, 0},
+{89, 3197737370u, 2147516072u, 3198697925u, 0, ERFF_TOLERANCE, 0},
+{90, 3197401825u, 2147516072u, 3198350862u, 0, ERFF_TOLERANCE, 0},
+{91, 3197066281u, 2147516072u, 3198001781u, 0, ERFF_TOLERANCE, 0},
+{92, 3196730737u, 2147516072u, 3197650740u, 0, ERFF_TOLERANCE, 0},
+{93, 3196395192u, 2147516072u, 3197297797u, 0, ERFF_TOLERANCE, 0},
+{94, 3196059648u, 2147516072u, 3196943015u, 0, ERFF_TOLERANCE, 0},
+{95, 3195388559u, 2147516072u, 3196586454u, 0, ERFF_TOLERANCE, 0},
+{96, 3194717471u, 2147516072u, 3196228179u, 0, ERFF_TOLERANCE, 0},
+{97, 3194046382u, 2147516072u, 3195676853u, 0, ERFF_TOLERANCE, 0},
+{98, 3193375293u, 2147516072u, 3194953822u, 0, ERFF_TOLERANCE, 0},
+{99, 3192704205u, 2147516072u, 3194227750u, 0, ERFF_TOLERANCE, 0},
+{100, 3192033116u, 2147516072u, 3193498766u, 0, ERFF_TOLERANCE, 0},
+{101, 3191362028u, 2147516072u, 3192767008u, 0, ERFF_TOLERANCE, 0},
+{102, 3190690939u, 2147516072u, 3192032610u, 0, ERFF_TOLERANCE, 0},
+{103, 3190019850u, 2147516072u, 3191295711u, 0, ERFF_TOLERANCE, 0},
+{104, 3189348762u, 2147516072u, 3190556451u, 0, ERFF_TOLERANCE, 0},
+{105, 3188677673u, 2147516072u, 3189814969u, 0, ERFF_TOLERANCE, 0},
+{106, 3188006584u, 2147516072u, 3189071408u, 0, ERFF_TOLERANCE, 0},
+{107, 3186999951u, 2147516072u, 3188325912u, 0, ERFF_TOLERANCE, 0},
+{108, 3185657774u, 2147516072u, 3187486208u, 0, ERFF_TOLERANCE, 0},
+{109, 3184315597u, 2147516072u, 3185988341u, 0, ERFF_TOLERANCE, 0},
+{110, 3182973420u, 2147516072u, 3184487476u, 0, ERFF_TOLERANCE, 0},
+{111, 3181631242u, 2147516072u, 3182983905u, 0, ERFF_TOLERANCE, 0},
+{112, 3180289065u, 2147516072u, 3181477928u, 0, ERFF_TOLERANCE, 0},
+{113, 3178611343u, 2147516072u, 3179969841u, 0, ERFF_TOLERANCE, 0},
+{114, 3175926989u, 2147516072u, 3177637454u, 0, ERFF_TOLERANCE, 0},
+{115, 3173242634u, 2147516072u, 3174614636u, 0, ERFF_TOLERANCE, 0},
+{116, 3170222735u, 2147516072u, 3171589400u, 0, ERFF_TOLERANCE, 0},
+{117, 3164854026u, 2147516072u, 3166230872u, 0, ERFF_TOLERANCE, 0},
+{118, 3156465418u, 2147516072u, 3157843475u, 0, ERFF_TOLERANCE, 0},
+{119, 646742016u, 2147516072u, 647924107u, 0, ERFF_TOLERANCE, 0},
+{120, 1008981770u, 2147516072u, 1010359827u, 0, ERFF_TOLERANCE, 0},
+{121, 1017370378u, 2147516072u, 1018747224u, 0, ERFF_TOLERANCE, 0},
+{122, 1022739087u, 2147516072u, 1024105752u, 0, ERFF_TOLERANCE, 0},
+{123, 1025758986u, 2147516072u, 1027130988u, 0, ERFF_TOLERANCE, 0},
+{124, 1028443341u, 2147516072u, 1030153806u, 0, ERFF_TOLERANCE, 0},
+{125, 1031127695u, 2147516072u, 1032486193u, 0, ERFF_TOLERANCE, 0},
+{126, 1032805417u, 2147516072u, 1033994280u, 0, ERFF_TOLERANCE, 0},
+{127, 1034147594u, 2147516072u, 1035500257u, 0, ERFF_TOLERANCE, 0},
+{128, 1035489772u, 2147516072u, 1037003828u, 0, ERFF_TOLERANCE, 0},
+{129, 1036831949u, 2147516072u, 1038504693u, 0, ERFF_TOLERANCE, 0},
+{130, 1038174126u, 2147516072u, 1040002560u, 0, ERFF_TOLERANCE, 0},
+{131, 1039516303u, 2147516072u, 1040842264u, 0, ERFF_TOLERANCE, 0},
+{132, 1040522936u, 2147516072u, 1041587760u, 0, ERFF_TOLERANCE, 0},
+{133, 1041194025u, 2147516072u, 1042331321u, 0, ERFF_TOLERANCE, 0},
+{134, 1041865114u, 2147516072u, 1043072803u, 0, ERFF_TOLERANCE, 0},
+{135, 1042536202u, 2147516072u, 1043812063u, 0, ERFF_TOLERANCE, 0},
+{136, 1043207291u, 2147516072u, 1044548962u, 0, ERFF_TOLERANCE, 0},
+{137, 1043878380u, 2147516072u, 1045283360u, 0, ERFF_TOLERANCE, 0},
+{138, 1044549468u, 2147516072u, 1046015118u, 0, ERFF_TOLERANCE, 0},
+{139, 1045220557u, 2147516072u, 1046744102u, 0, ERFF_TOLERANCE, 0},
+{140, 1045891645u, 2147516072u, 1047470174u, 0, ERFF_TOLERANCE, 0},
+{141, 1046562734u, 2147516072u, 1048193205u, 0, ERFF_TOLERANCE, 0},
+{142, 1047233823u, 2147516072u, 1048744531u, 0, ERFF_TOLERANCE, 0},
+{143, 1047904911u, 2147516072u, 1049102806u, 0, ERFF_TOLERANCE, 0},
+{144, 1048576000u, 2147516072u, 1049459367u, 0, ERFF_TOLERANCE, 0},
+{145, 1048911544u, 2147516072u, 1049814149u, 0, ERFF_TOLERANCE, 0},
+{146, 1049247089u, 2147516072u, 1050167092u, 0, ERFF_TOLERANCE, 0},
+{147, 1049582633u, 2147516072u, 1050518133u, 0, ERFF_TOLERANCE, 0},
+{148, 1049918177u, 2147516072u, 1050867214u, 0, ERFF_TOLERANCE, 0},
+{149, 1050253722u, 2147516072u, 1051214277u, 0, ERFF_TOLERANCE, 0},
+{150, 1050589266u, 2147516072u, 1051559263u, 0, ERFF_TOLERANCE, 0},
+{151, 1050924810u, 2147516072u, 1051902116u, 0, ERFF_TOLERANCE, 0},
+{152, 1051260355u, 2147516072u, 1052242784u, 0, ERFF_TOLERANCE, 0},
+{153, 1051595899u, 2147516072u, 1052581209u, 0, ERFF_TOLERANCE, 0},
+{154, 1051931443u, 2147516072u, 1052917341u, 0, ERFF_TOLERANCE, 0},
+{155, 1052266988u, 2147516072u, 1053251129u, 0, ERFF_TOLERANCE, 0},
+{156, 1052602532u, 2147516072u, 1053582522u, 0, ERFF_TOLERANCE, 0},
+{157, 1052938076u, 2147516072u, 1053911472u, 0, ERFF_TOLERANCE, 0},
+{158, 1053273620u, 2147516072u, 1054237931u, 0, ERFF_TOLERANCE, 0},
+{159, 1053609165u, 2147516072u, 1054561854u, 0, ERFF_TOLERANCE, 0},
+{160, 1053944709u, 2147516072u, 1054883196u, 0, ERFF_TOLERANCE, 0},
+{161, 1054280253u, 2147516072u, 1055201913u, 0, ERFF_TOLERANCE, 0},
+{162, 1054615798u, 2147516072u, 1055517966u, 0, ERFF_TOLERANCE, 0},
+{163, 1054951342u, 2147516072u, 1055831311u, 0, ERFF_TOLERANCE, 0},
+{164, 1055286886u, 2147516072u, 1056141911u, 0, ERFF_TOLERANCE, 0},
+{165, 1055622431u, 2147516072u, 1056449729u, 0, ERFF_TOLERANCE, 0},
+{166, 1055957975u, 2147516072u, 1056754726u, 0, ERFF_TOLERANCE, 0},
+{167, 1056293519u, 2147516072u, 1057010740u, 0, ERFF_TOLERANCE, 0},
+{168, 1056629064u, 2147516072u, 1057160368u, 0, ERFF_TOLERANCE, 0},
+{169, 1056964608u, 2147516072u, 1057308539u, 0, ERFF_TOLERANCE, 0},
+{170, 1057132380u, 2147516072u, 1057455234u, 0, ERFF_TOLERANCE, 0},
+{171, 1057300152u, 2147516072u, 1057600441u, 0, ERFF_TOLERANCE, 0},
+{172, 1057467924u, 2147516072u, 1057744146u, 0, ERFF_TOLERANCE, 0},
+{173, 1057635697u, 2147516072u, 1057886336u, 0, ERFF_TOLERANCE, 0},
+{174, 1057803469u, 2147516072u, 1058026998u, 0, ERFF_TOLERANCE, 0},
+{175, 1057971241u, 2147516072u, 1058166121u, 0, ERFF_TOLERANCE, 0},
+{176, 1058139013u, 2147516072u, 1058303695u, 0, ERFF_TOLERANCE, 0},
+{177, 1058306785u, 2147516072u, 1058439709u, 0, ERFF_TOLERANCE, 0},
+{178, 1058474557u, 2147516072u, 1058574154u, 0, ERFF_TOLERANCE, 0},
+{179, 1058642330u, 2147516072u, 1058707024u, 0, ERFF_TOLERANCE, 0},
+{180, 1058810102u, 2147516072u, 1058838308u, 0, ERFF_TOLERANCE, 0},
+{181, 1058977874u, 2147516072u, 1058968000u, 0, ERFF_TOLERANCE, 0},
+{182, 1059145646u, 2147516072u, 1059096093u, 0, ERFF_TOLERANCE, 0},
+{183, 1059313418u, 2147516072u, 1059222584u, 0, ERFF_TOLERANCE, 0},
+{184, 1059481190u, 2147516072u, 1059347464u, 0, ERFF_TOLERANCE, 0},
+{185, 1059648963u, 2147516072u, 1059470733u, 0, ERFF_TOLERANCE, 0},
+{186, 1059816735u, 2147516072u, 1059592385u, 0, ERFF_TOLERANCE, 0},
+{187, 1059984507u, 2147516072u, 1059712418u, 0, ERFF_TOLERANCE, 0},
+{188, 1060152279u, 2147516072u, 1059830828u, 0, ERFF_TOLERANCE, 0},
+{189, 1060320051u, 2147516072u, 1059947617u, 0, ERFF_TOLERANCE, 0},
+{190, 1060487823u, 2147516072u, 1060062782u, 0, ERFF_TOLERANCE, 0},
+{191, 1060655596u, 2147516072u, 1060176323u, 0, ERFF_TOLERANCE, 0},
+{192, 1060823368u, 2147516072u, 1060288241u, 0, ERFF_TOLERANCE, 0},
+{193, 1060991140u, 2147516072u, 1060398536u, 0, ERFF_TOLERANCE, 0},
+{194, 1061158912u, 2147516072u, 1060507212u, 0, ERFF_TOLERANCE, 0},
+{195, 1061326684u, 2147516072u, 1060614270u, 0, ERFF_TOLERANCE, 0},
+{196, 1061494456u, 2147516072u, 1060719712u, 0, ERFF_TOLERANCE, 0},
+{197, 1061662228u, 2147516072u, 1060823542u, 0, ERFF_TOLERANCE, 0},
+{198, 1061830001u, 2147516072u, 1060925767u, 0, ERFF_TOLERANCE, 0},
+{199, 1061997773u, 2147516072u, 1061026388u, 0, ERFF_TOLERANCE, 0},
+{200, 1062165545u, 2147516072u, 1061125412u, 0, ERFF_TOLERANCE, 0},
+{201, 1062333317u, 2147516072u, 1061222845u, 0, ERFF_TOLERANCE, 0},
+{202, 1062501089u, 2147516072u, 1061318694u, 0, ERFF_TOLERANCE, 0},
+{203, 1062668861u, 2147516072u, 1061412964u, 0, ERFF_TOLERANCE, 0},
+{204, 1062836634u, 2147516072u, 1061505664u, 0, ERFF_TOLERANCE, 0},
+{205, 1063004406u, 2147516072u, 1061596802u, 0, ERFF_TOLERANCE, 0},
+{206, 1063172178u, 2147516072u, 1061686385u, 0, ERFF_TOLERANCE, 0},
+{207, 1063339950u, 2147516072u, 1061774423u, 0, ERFF_TOLERANCE, 0},
+{208, 1063507722u, 2147516072u, 1061860925u, 0, ERFF_TOLERANCE, 0},
+{209, 1063675494u, 2147516072u, 1061945900u, 0, ERFF_TOLERANCE, 0},
+{210, 1063843267u, 2147516072u, 1062029361u, 0, ERFF_TOLERANCE, 0},
+{211, 1064011039u, 2147516072u, 1062111316u, 0, ERFF_TOLERANCE, 0},
+{212, 1064178811u, 2147516072u, 1062191777u, 0, ERFF_TOLERANCE, 0},
+{213, 1064514355u, 2147516072u, 1062348262u, 0, ERFF_TOLERANCE, 0},
+{214, 1064682127u, 2147516072u, 1062424311u, 0, ERFF_TOLERANCE, 0},
+{215, 1064849900u, 2147516072u, 1062498913u, 0, ERFF_TOLERANCE, 0},
+{216, 1065017672u, 2147516072u, 1062572082u, 0, ERFF_TOLERANCE, 0},
+{217, 1065185444u, 2147516072u, 1062643831u, 0, ERFF_TOLERANCE, 0},
+{218, 1065353216u, 2147516072u, 1062714173u, 0, ERFF_TOLERANCE, 0},
+{219, 1065437102u, 2147516072u, 1062783122u, 0, ERFF_TOLERANCE, 0},
+{220, 1065520988u, 2147516072u, 1062850693u, 0, ERFF_TOLERANCE, 0},
+{221, 1065604874u, 2147516072u, 1062916899u, 0, ERFF_TOLERANCE, 0},
+{222, 1065688760u, 2147516072u, 1062981755u, 0, ERFF_TOLERANCE, 0},
+{223, 1065772646u, 2147516072u, 1063045276u, 0, ERFF_TOLERANCE, 0},
+{224, 1065856532u, 2147516072u, 1063107478u, 0, ERFF_TOLERANCE, 0},
+{225, 1065940419u, 2147516072u, 1063168375u, 0, ERFF_TOLERANCE, 0},
+{226, 1066024305u, 2147516072u, 1063227982u, 0, ERFF_TOLERANCE, 0},
+{227, 1066108191u, 2147516072u, 1063286315u, 0, ERFF_TOLERANCE, 0},
+{228, 1066192077u, 2147516072u, 1063343391u, 0, ERFF_TOLERANCE, 0},
+{229, 1066275963u, 2147516072u, 1063399224u, 0, ERFF_TOLERANCE, 0},
+{230, 1066359849u, 2147516072u, 1063453832u, 0, ERFF_TOLERANCE, 0},
+{231, 1066443735u, 2147516072u, 1063507230u, 0, ERFF_TOLERANCE, 0},
+{232, 1066527621u, 2147516072u, 1063559435u, 0, ERFF_TOLERANCE, 0},
+{233, 1066611507u, 2147516072u, 1063610463u, 0, ERFF_TOLERANCE, 0},
+{234, 1066695393u, 2147516072u, 1063660331u, 0, ERFF_TOLERANCE, 0},
+{235, 1066779279u, 2147516072u, 1063709055u, 0, ERFF_TOLERANCE, 0},
+{236, 1066863165u, 2147516072u, 1063756653u, 0, ERFF_TOLERANCE, 0},
+{237, 1066947052u, 2147516072u, 1063803140u, 0, ERFF_TOLERANCE, 0},
+{238, 3234402267u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{239, 3231108068u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{240, 3226013659u, 2147516072u, 3212836715u, 0, ERFF_TOLERANCE, 0},
+{241, 3217625051u, 2147516072u, 3212395270u, 0, ERFF_TOLERANCE, 0},
+{242, 0u, 2147516072u, 0u, 0, ERFF_TOLERANCE, 0},
+{243, 1070141403u, 2147516072u, 1064911622u, 0, ERFF_TOLERANCE, 0},
+{244, 1078530011u, 2147516072u, 1065353067u, 0, ERFF_TOLERANCE, 0},
+{245, 1083624420u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{246, 3253731328u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{247, 3252840038u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{248, 3251948749u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{249, 3251057459u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{250, 3250166170u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{251, 3249274880u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{252, 3248383590u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{253, 3247492301u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{254, 3246601011u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{255, 3245028147u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{256, 3243245568u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{257, 3241462989u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{258, 3239680410u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{259, 3237792973u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{260, 3234227814u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{261, 3230662656u, 2147516072u, 3212836864u, 0, ERFF_TOLERANCE, 0},
+{262, 3224580915u, 2147516072u, 3212835605u, 0, ERFF_TOLERANCE, 0},
+{263, 3213675725u, 2147516072u, 3210827039u, 0, ERFF_TOLERANCE, 0},
+{264, 1058642330u, 2147516072u, 1058707024u, 0, ERFF_TOLERANCE, 0},
+{265, 1075000115u, 2147516072u, 1065334037u, 0, ERFF_TOLERANCE, 0},
+{266, 1082130432u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{267, 1085695590u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{268, 1089260749u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{269, 1091672474u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{270, 1093455053u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{271, 1095237632u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{272, 1097020211u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{273, 1098802790u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{274, 1099746509u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{275, 1100637798u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{276, 1101529088u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{277, 1102420378u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{278, 1103311667u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{279, 1104202957u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{280, 1105094246u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0},
+{281, 1105985536u, 2147516072u, 1065353216u, 0, ERFF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_ERFF_H multiple inclusion protection
+
+// EOF erff.h
diff --git a/packages/language/c/libm/current/tests/vectors/expf.c b/packages/language/c/libm/current/tests/vectors/expf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/expf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      expf.c
+//
+//      Test of expf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_double_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/expf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(expf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &expf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &expf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("expf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("expf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library exp() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "exp() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF expf.c
diff --git a/packages/language/c/libm/current/tests/vectors/expf.h b/packages/language/c/libm/current/tests/vectors/expf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/expf.h
@@ -0,0 +1,647 @@
+#ifndef CYGONCE_LIBM_EXPF_H
+#define CYGONCE_LIBM_EXPF_H
+//===========================================================================
+//
+//      expf.h
+//
+//      Test vectors for testing of expf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/exp.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define EXP_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t expf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 646742016u, 1065353216u, 1065353216u, 0, EXP_TOLERANCE, 0},
+{1, 1008981770u, 1065437523u, 1065437523u, 0, EXP_TOLERANCE, 0},
+{2, 1017370378u, 1065522677u, 1065522677u, 0, EXP_TOLERANCE, 0},
+{3, 1022739087u, 1065608687u, 1065608687u, 0, EXP_TOLERANCE, 0},
+{4, 1025758986u, 1065695562u, 1065695562u, 0, EXP_TOLERANCE, 0},
+{5, 1028443341u, 1065783309u, 1065783309u, 0, EXP_TOLERANCE, 0},
+{6, 1031127695u, 1065871938u, 1065871938u, 0, EXP_TOLERANCE, 0},
+{7, 1032805417u, 1065961458u, 1065961458u, 0, EXP_TOLERANCE, 0},
+{8, 1034147594u, 1066051878u, 1066051878u, 0, EXP_TOLERANCE, 0},
+{9, 1035489772u, 1066143207u, 1066143207u, 0, EXP_TOLERANCE, 0},
+{10, 1036831949u, 1066235454u, 1066235454u, 0, EXP_TOLERANCE, 0},
+{11, 1038174126u, 1066328627u, 1066328627u, 0, EXP_TOLERANCE, 0},
+{12, 1039516303u, 1066422737u, 1066422737u, 0, EXP_TOLERANCE, 0},
+{13, 1040522936u, 1066517792u, 1066517792u, 0, EXP_TOLERANCE, 0},
+{14, 1041194025u, 1066613804u, 1066613804u, 0, EXP_TOLERANCE, 0},
+{15, 1041865114u, 1066710780u, 1066710780u, 0, EXP_TOLERANCE, 0},
+{16, 1042536202u, 1066808730u, 1066808730u, 0, EXP_TOLERANCE, 0},
+{17, 1043207291u, 1066907665u, 1066907665u, 0, EXP_TOLERANCE, 0},
+{18, 1043878380u, 1067007595u, 1067007595u, 0, EXP_TOLERANCE, 0},
+{19, 1044549468u, 1067108528u, 1067108528u, 0, EXP_TOLERANCE, 0},
+{20, 1045220557u, 1067210477u, 1067210477u, 0, EXP_TOLERANCE, 0},
+{21, 1045891645u, 1067313449u, 1067313449u, 0, EXP_TOLERANCE, 0},
+{22, 1046562734u, 1067417457u, 1067417457u, 0, EXP_TOLERANCE, 0},
+{23, 1047233823u, 1067522510u, 1067522510u, 0, EXP_TOLERANCE, 0},
+{24, 1047904911u, 1067628618u, 1067628618u, 0, EXP_TOLERANCE, 0},
+{25, 1048576000u, 1067735793u, 1067735793u, 0, EXP_TOLERANCE, 0},
+{26, 1048911544u, 1067844046u, 1067844046u, 0, EXP_TOLERANCE, 0},
+{27, 1049247089u, 1067953387u, 1067953387u, 0, EXP_TOLERANCE, 0},
+{28, 1049582633u, 1068063826u, 1068063826u, 0, EXP_TOLERANCE, 0},
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+{470, 1087938837u, 1146732848u, 1146732848u, 0, EXP_TOLERANCE, 0},
+{471, 1086382700u, 1137663500u, 1137663500u, 0, EXP_TOLERANCE, 0},
+{472, 1041130723u, 1066604706u, 1066604706u, 0, EXP_TOLERANCE, 0},
+{473, 1070900975u, 1084786236u, 1084786236u, 0, EXP_TOLERANCE, 0},
+{474, 1094918207u, 1212234718u, 1212234718u, 0, EXP_TOLERANCE, 0},
+{475, 1059727635u, 1073271108u, 1073271108u, 0, EXP_TOLERANCE, 0},
+{476, 1021599538u, 1065590359u, 1065590359u, 0, EXP_TOLERANCE, 0},
+{477, 1067180353u, 1079529057u, 1079529057u, 0, EXP_TOLERANCE, 0},
+{478, 1101660315u, 1321856380u, 1321856380u, 0, EXP_TOLERANCE, 0},
+{479, 1109054467u, 1533379708u, 1533379708u, 0, EXP_TOLERANCE, 0},
+{480, 1103532738u, 1365273754u, 1365273754u, 0, EXP_TOLERANCE, 0},
+{481, 1035525679u, 1066145663u, 1066145663u, 0, EXP_TOLERANCE, 0},
+{482, 1094330983u, 1205649366u, 1205649366u, 0, EXP_TOLERANCE, 0},
+{483, 1034492227u, 1066075242u, 1066075242u, 0, EXP_TOLERANCE, 0},
+{484, 1072096532u, 1086477996u, 1086477996u, 0, EXP_TOLERANCE, 0},
+{485, 1075990050u, 1095373204u, 1095373204u, 0, EXP_TOLERANCE, 0},
+{486, 1109033185u, 1532206806u, 1532206806u, 0, EXP_TOLERANCE, 0},
+{487, 1089560310u, 1156310516u, 1156310516u, 0, EXP_TOLERANCE, 0},
+{488, 1103328289u, 1360524395u, 1360524395u, 0, EXP_TOLERANCE, 0},
+{489, 1061907666u, 1074637811u, 1074637811u, 0, EXP_TOLERANCE, 0},
+{490, 1083710041u, 1122494921u, 1122494921u, 0, EXP_TOLERANCE, 0},
+{491, 1100867428u, 1303512311u, 1303512311u, 0, EXP_TOLERANCE, 0},
+{492, 1055125047u, 1070057263u, 1070057263u, 0, EXP_TOLERANCE, 0},
+{493, 1104553235u, 1388607970u, 1388607970u, 0, EXP_TOLERANCE, 0},
+{494, 1032386633u, 1065933431u, 1065933431u, 0, EXP_TOLERANCE, 0},
+{495, 1034271795u, 1066060291u, 1066060291u, 0, EXP_TOLERANCE, 0},
+{496, 1055506573u, 1070206981u, 1070206981u, 0, EXP_TOLERANCE, 0},
+{497, 1104281863u, 1382690251u, 1382690251u, 0, EXP_TOLERANCE, 0},
+{498, 1025475511u, 1065686346u, 1065686346u, 0, EXP_TOLERANCE, 0},
+{499, 1076895780u, 1098565127u, 1098565127u, 0, EXP_TOLERANCE, 0},
+{500, 1009589036u, 1065442316u, 1065442316u, 0, EXP_TOLERANCE, 0},
+{501, 1110359908u, 1593993278u, 1593993278u, 0, EXP_TOLERANCE, 0},
+{502, 1028807839u, 1065795292u, 1065795292u, 0, EXP_TOLERANCE, 0},
+{503, 1109436551u, 1551267569u, 1551267569u, 0, EXP_TOLERANCE, 0},
+{504, 1021730413u, 1065592462u, 1065592462u, 0, EXP_TOLERANCE, 0},
+{505, 1072081640u, 1086455406u, 1086455406u, 0, EXP_TOLERANCE, 0},
+{506, 1077465839u, 1099932685u, 1099932685u, 0, EXP_TOLERANCE, 0},
+{507, 1044300951u, 1067071033u, 1067071033u, 0, EXP_TOLERANCE, 0},
+{508, 1097032302u, 1236623967u, 1236623967u, 0, EXP_TOLERANCE, 0},
+{509, 1053981400u, 1069618541u, 1069618541u, 0, EXP_TOLERANCE, 0},
+{510, 1078478376u, 1102502986u, 1102502986u, 0, EXP_TOLERANCE, 0},
+{511, 1098068815u, 1249096941u, 1249096941u, 0, EXP_TOLERANCE, 0},
+{512, 1021467071u, 1065588231u, 1065588231u, 0, EXP_TOLERANCE, 0},
+{513, 1009763492u, 1065443694u, 1065443694u, 0, EXP_TOLERANCE, 0},
+{514, 1044623194u, 1067119679u, 1067119679u, 0, EXP_TOLERANCE, 0},
+{515, 1015705469u, 1065496179u, 1065496179u, 0, EXP_TOLERANCE, 0},
+{516, 1113725538u, 1748718730u, 1748718730u, 0, EXP_TOLERANCE, 0},
+{517, 1091841457u, 1176790302u, 1176790302u, 0, EXP_TOLERANCE, 0},
+{518, 1028958993u, 1065800266u, 1065800266u, 0, EXP_TOLERANCE, 0},
+{519, 1107682111u, 1469872413u, 1469872413u, 0, EXP_TOLERANCE, 0},
+{520, 1116027769u, 1871304107u, 1871304107u, 0, EXP_TOLERANCE, 0},
+{521, 1095143732u, 1215273481u, 1215273481u, 0, EXP_TOLERANCE, 0},
+{522, 1109791849u, 1567552701u, 1567552701u, 0, EXP_TOLERANCE, 0},
+{523, 1080343714u, 1108255550u, 1108255550u, 0, EXP_TOLERANCE, 0},
+{524, 1097380552u, 1241306521u, 1241306521u, 0, EXP_TOLERANCE, 0},
+{525, 1014020764u, 1065477379u, 1065477379u, 0, EXP_TOLERANCE, 0},
+{526, 1021650291u, 1065591174u, 1065591174u, 0, EXP_TOLERANCE, 0},
+{527, 1082778705u, 1117044746u, 1117044746u, 0, EXP_TOLERANCE, 0},
+{528, 1008484823u, 1065433602u, 1065433602u, 0, EXP_TOLERANCE, 0},
+{529, 1007086271u, 1065422579u, 1065422579u, 0, EXP_TOLERANCE, 0},
+{530, 1073311024u, 1088462085u, 1088462085u, 0, EXP_TOLERANCE, 0},
+{531, 1019109924u, 1065550452u, 1065550452u, 0, EXP_TOLERANCE, 0},
+{532, 1018648250u, 1065543071u, 1065543071u, 0, EXP_TOLERANCE, 0},
+{533, 1072458508u, 1087039603u, 1087039603u, 0, EXP_TOLERANCE, 0},
+{534, 1056562851u, 1070630475u, 1070630475u, 0, EXP_TOLERANCE, 0},
+{535, 1043828826u, 1067000182u, 1067000182u, 0, EXP_TOLERANCE, 0},
+{536, 1042710124u, 1066834276u, 1066834276u, 0, EXP_TOLERANCE, 0},
+{537, 1096757647u, 1233884720u, 1233884720u, 0, EXP_TOLERANCE, 0},
+{538, 1110766850u, 1612314434u, 1612314434u, 0, EXP_TOLERANCE, 0},
+{539, 1050846809u, 1068489970u, 1068489970u, 0, EXP_TOLERANCE, 0},
+{540, 1049017704u, 1067878521u, 1067878521u, 0, EXP_TOLERANCE, 0},
+{541, 1041850943u, 1066708722u, 1066708722u, 0, EXP_TOLERANCE, 0},
+{542, 1113559832u, 1741102728u, 1741102728u, 0, EXP_TOLERANCE, 0},
+{543, 1078359574u, 1102168308u, 1102168308u, 0, EXP_TOLERANCE, 0},
+{544, 1063112056u, 1075328834u, 1075328834u, 0, EXP_TOLERANCE, 0},
+{545, 1107012128u, 1445401767u, 1445401767u, 0, EXP_TOLERANCE, 0},
+{546, 1061909506u, 1074638830u, 1074638830u, 0, EXP_TOLERANCE, 0},
+{547, 1027921603u, 1065766186u, 1065766186u, 0, EXP_TOLERANCE, 0},
+{548, 1076752219u, 1098012128u, 1098012128u, 0, EXP_TOLERANCE, 0},
+{549, 1021430647u, 1065587646u, 1065587646u, 0, EXP_TOLERANCE, 0},
+{550, 1013529335u, 1065473484u, 1065473484u, 0, EXP_TOLERANCE, 0},
+{551, 1094132929u, 1203159396u, 1203159396u, 0, EXP_TOLERANCE, 0},
+{552, 1015879284u, 1065498941u, 1065498941u, 0, EXP_TOLERANCE, 0},
+{553, 1095821013u, 1222937523u, 1222937523u, 0, EXP_TOLERANCE, 0},
+{554, 1051548019u, 1068733358u, 1068733358u, 0, EXP_TOLERANCE, 0},
+{555, 1038345009u, 1066340557u, 1066340557u, 0, EXP_TOLERANCE, 0},
+{556, 1111212143u, 1632791232u, 1632791232u, 0, EXP_TOLERANCE, 0},
+{557, 1105553664u, 1411746926u, 1411746926u, 0, EXP_TOLERANCE, 0},
+{558, 1085166299u, 1130902555u, 1130902555u, 0, EXP_TOLERANCE, 0},
+{559, 1009111476u, 1065438546u, 1065438546u, 0, EXP_TOLERANCE, 0},
+{560, 1035296501u, 1066130000u, 1066130000u, 0, EXP_TOLERANCE, 0},
+{561, 1099936659u, 1282493540u, 1282493540u, 0, EXP_TOLERANCE, 0},
+{562, 1046117057u, 1067348269u, 1067348269u, 0, EXP_TOLERANCE, 0},
+{563, 1039949220u, 1066453293u, 1066453293u, 0, EXP_TOLERANCE, 0},
+{564, 1044713476u, 1067133350u, 1067133350u, 0, EXP_TOLERANCE, 0},
+{565, 1053631629u, 1069487322u, 1069487322u, 0, EXP_TOLERANCE, 0},
+{566, 1097055270u, 1236887207u, 1236887207u, 0, EXP_TOLERANCE, 0},
+{567, 1108662760u, 1515063328u, 1515063328u, 0, EXP_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_EXPF_H multiple inclusion protection
+
+// EOF expf.h
diff --git a/packages/language/c/libm/current/tests/vectors/expm1f.c b/packages/language/c/libm/current/tests/vectors/expm1f.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/expm1f.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      expm1f.c
+//
+//      Test of expm1f() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/expm1f.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(expm1f_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &expm1f, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &expm1f_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("expm1f() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("expm1f() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library expm1f() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "expm1f() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF expm1f.c
diff --git a/packages/language/c/libm/current/tests/vectors/expm1f.h b/packages/language/c/libm/current/tests/vectors/expm1f.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/expm1f.h
@@ -0,0 +1,2551 @@
+#ifndef CYGONCE_LIBM_EXPM1F_H
+#define CYGONCE_LIBM_EXPM1F_H
+//===========================================================================
+//
+//      expm1f.h
+//
+//      Test vectors for testing of expm1f() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/expm1f.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define EXPM1F_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t expm1f_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{1, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{2, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{3, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{4, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{5, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{6, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{7, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{8, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{9, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{10, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{11, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{12, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{13, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{14, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{15, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{16, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{17, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{18, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{19, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{20, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{21, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{22, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{23, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{24, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{25, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{26, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{27, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{28, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{29, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{30, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{31, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{32, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{33, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{34, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{35, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{36, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{37, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{38, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{39, 3212836864u, 3079358544u, 3206664871u, 0, EXPM1F_TOLERANCE, 0},
+{40, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
+{41, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
+{42, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
+{43, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
+{44, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
+{45, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
+{46, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
+{47, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
+{48, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
+{49, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
+{50, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
+{51, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
+{52, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
+{53, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
+{54, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
+{55, 3211998003u, 3079358544u, 3206348426u, 0, EXPM1F_TOLERANCE, 0},
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+{2276, 946058434u, 3079358544u, 946058839u, 0, EXPM1F_TOLERANCE, 0},
+{2277, 3073260205u, 3079358544u, 3073260146u, 0, EXPM1F_TOLERANCE, 0},
+{2278, 1245702957u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2279, 989655126u, 3079358544u, 989671131u, 0, EXPM1F_TOLERANCE, 0},
+{2280, 1002715618u, 3079358544u, 1002754200u, 0, EXPM1F_TOLERANCE, 0},
+{2281, 3087802274u, 3079358544u, 3087802121u, 0, EXPM1F_TOLERANCE, 0},
+{2282, 1000863905u, 3079358544u, 1000892168u, 0, EXPM1F_TOLERANCE, 0},
+{2283, 3415763001u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2284, 3283471961u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2285, 3311210827u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2286, 3026311911u, 3079358544u, 3026311909u, 0, EXPM1F_TOLERANCE, 0},
+{2287, 1198307901u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2288, 1288901567u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2289, 922255363u, 3079358544u, 922255423u, 0, EXPM1F_TOLERANCE, 0},
+{2290, 1113104661u, 3079358544u, 1720471412u, 0, EXPM1F_TOLERANCE, 0},
+{2291, 1136714348u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2292, 948856035u, 3079358544u, 948856352u, 0, EXPM1F_TOLERANCE, 0},
+{2293, 1062512367u, 3079358544u, 1067826688u, 0, EXPM1F_TOLERANCE, 0},
+{2294, 3486907092u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2295, 1162027071u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2296, 1034561811u, 3079358544u, 1035038186u, 0, EXPM1F_TOLERANCE, 0},
+{2297, 3271615417u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2298, 1042014529u, 3079358544u, 1042833086u, 0, EXPM1F_TOLERANCE, 0},
+{2299, 1177157787u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2300, 3196144817u, 3079358544u, 3194259351u, 0, EXPM1F_TOLERANCE, 0},
+{2301, 3432084552u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2302, 1309658335u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2303, 1226494979u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2304, 3100289712u, 3079358544u, 3100289070u, 0, EXPM1F_TOLERANCE, 0},
+{2305, 3375507013u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2306, 3460699001u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2307, 3079231719u, 3079358544u, 3079231645u, 0, EXPM1F_TOLERANCE, 0},
+{2308, 3093951884u, 3079358544u, 3093951456u, 0, EXPM1F_TOLERANCE, 0},
+{2309, 3468023178u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2310, 1204196034u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2311, 3459877411u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2312, 909696559u, 3079358544u, 909696576u, 0, EXPM1F_TOLERANCE, 0},
+{2313, 1161439847u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2314, 908663107u, 3079358544u, 908663121u, 0, EXPM1F_TOLERANCE, 0},
+{2315, 1055319316u, 3079358544u, 1058136138u, 0, EXPM1F_TOLERANCE, 0},
+{2316, 1084378658u, 3079358544u, 1126072255u, 0, EXPM1F_TOLERANCE, 0},
+{2317, 3053887750u, 3079358544u, 3053887741u, 0, EXPM1F_TOLERANCE, 0},
+{2318, 3022828828u, 3079358544u, 3022828827u, 0, EXPM1F_TOLERANCE, 0},
+{2319, 1226473697u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2320, 1123114742u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2321, 1258114435u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2322, 3468040845u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2323, 1178825761u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2324, 3059266302u, 3079358544u, 3059266279u, 0, EXPM1F_TOLERANCE, 0},
+{2325, 3223384012u, 3079358544u, 3211479716u, 0, EXPM1F_TOLERANCE, 0},
+{2326, 1019964626u, 3079358544u, 1020131532u, 0, EXPM1F_TOLERANCE, 0},
+{2327, 3445262427u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2328, 1125653081u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2329, 3337652712u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2330, 1184753508u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2331, 996404791u, 3079358544u, 996430797u, 0, EXPM1F_TOLERANCE, 0},
+{2332, 1188439315u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2333, 906557513u, 3079358544u, 906557522u, 0, EXPM1F_TOLERANCE, 0},
+{2334, 916831283u, 3079358544u, 916831310u, 0, EXPM1F_TOLERANCE, 0},
+{2335, 996786317u, 3079358544u, 996813670u, 0, EXPM1F_TOLERANCE, 0},
+{2336, 3461635065u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2337, 1188167943u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2338, 3036502395u, 3079358544u, 3036502391u, 0, EXPM1F_TOLERANCE, 0},
+{2339, 891257783u, 3079358544u, 891257786u, 0, EXPM1F_TOLERANCE, 0},
+{2340, 3290079438u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2341, 3350690327u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2342, 1102061604u, 3079358544u, 1331236523u, 0, EXPM1F_TOLERANCE, 0},
+{2343, 1282351521u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2344, 3458861065u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2345, 3095256878u, 3079358544u, 3095256374u, 0, EXPM1F_TOLERANCE, 0},
+{2346, 3163373610u, 3079358544u, 3163294260u, 0, EXPM1F_TOLERANCE, 0},
+{2347, 3228793330u, 3079358544u, 3212463162u, 0, EXPM1F_TOLERANCE, 0},
+{2348, 3422194733u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2349, 3083885296u, 3079358544u, 3083885126u, 0, EXPM1F_TOLERANCE, 0},
+{2350, 1261940623u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2351, 3400603081u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2352, 1219411812u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2353, 3094833770u, 3079358544u, 3094833292u, 0, EXPM1F_TOLERANCE, 0},
+{2354, 3139250800u, 3079358544u, 3139238459u, 0, EXPM1F_TOLERANCE, 0},
+{2355, 886201503u, 3079358544u, 886201506u, 0, EXPM1F_TOLERANCE, 0},
+{2356, 3297366026u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2357, 1218488455u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2358, 3040358923u, 3079358544u, 3040358919u, 0, EXPM1F_TOLERANCE, 0},
+{2359, 1283938137u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2360, 3182551696u, 3079358544u, 3182059752u, 0, EXPM1F_TOLERANCE, 0},
+{2361, 1317098613u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2362, 3116209179u, 3079358544u, 3116206933u, 0, EXPM1F_TOLERANCE, 0},
+{2363, 3431703657u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2364, 3239728775u, 3079358544u, 3212835779u, 0, EXPM1F_TOLERANCE, 0},
+{2365, 3207141672u, 3079358544u, 3203892183u, 0, EXPM1F_TOLERANCE, 0},
+{2366, 3154378805u, 3079358544u, 3154344050u, 0, EXPM1F_TOLERANCE, 0},
+{2367, 3069658155u, 3079358544u, 3069658095u, 0, EXPM1F_TOLERANCE, 0},
+{2368, 3313160088u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2369, 3207056527u, 3079358544u, 3203803993u, 0, EXPM1F_TOLERANCE, 0},
+{2370, 1284174954u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2371, 3156081645u, 3079358544u, 3156031887u, 0, EXPM1F_TOLERANCE, 0},
+{2372, 1063693032u, 3079358544u, 1069230225u, 0, EXPM1F_TOLERANCE, 0},
+{2373, 3036026175u, 3079358544u, 3036026171u, 0, EXPM1F_TOLERANCE, 0},
+{2374, 1102631663u, 3079358544u, 1344337477u, 0, EXPM1F_TOLERANCE, 0},
+{2375, 968803479u, 3079358544u, 968805754u, 0, EXPM1F_TOLERANCE, 0},
+{2376, 3273080388u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2377, 1172529774u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2378, 1306695905u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2379, 1003649752u, 3079358544u, 1003694149u, 0, EXPM1F_TOLERANCE, 0},
+{2380, 1078478376u, 3079358544u, 1101978697u, 0, EXPM1F_TOLERANCE, 0},
+{2381, 3158855023u, 3079358544u, 3158775107u, 0, EXPM1F_TOLERANCE, 0},
+{2382, 1165177679u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2383, 3403009513u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2384, 952348506u, 3079358544u, 952349104u, 0, EXPM1F_TOLERANCE, 0},
+{2385, 1222777442u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2386, 1325324763u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2387, 3363524213u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2388, 1158950321u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2389, 903129873u, 3079358544u, 903129884u, 0, EXPM1F_TOLERANCE, 0},
+{2390, 3078339944u, 3079358544u, 3078339820u, 0, EXPM1F_TOLERANCE, 0},
+{2391, 1208345407u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2392, 1258634105u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2393, 1248478509u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2394, 1153863988u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2395, 1235620969u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2396, 1097120930u, 3079358544u, 1237672369u, 0, EXPM1F_TOLERANCE, 0},
+{2397, 3469778622u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2398, 1147712200u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2399, 1124721745u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2400, 3261744304u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2401, 1064922416u, 3079358544u, 1070800536u, 0, EXPM1F_TOLERANCE, 0},
+{2402, 3303160152u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2403, 1315090496u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2404, 3230403187u, 3079358544u, 3212625939u, 0, EXPM1F_TOLERANCE, 0},
+{2405, 1335399673u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2406, 1072458508u, 3079358544u, 1084942451u, 0, EXPM1F_TOLERANCE, 0},
+{2407, 3303015249u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2408, 3252139741u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2409, 3468519966u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2410, 1006231203u, 3079358544u, 1006293797u, 0, EXPM1F_TOLERANCE, 0},
+{2411, 951554138u, 3079358544u, 951554665u, 0, EXPM1F_TOLERANCE, 0},
+{2412, 942046828u, 3079358544u, 942047045u, 0, EXPM1F_TOLERANCE, 0},
+{2413, 3319723279u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2414, 3255104167u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2415, 1155477903u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2416, 3273889176u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2417, 3237813668u, 3079358544u, 3212830705u, 0, EXPM1F_TOLERANCE, 0},
+{2418, 1228207362u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2419, 975349337u, 3079358544u, 975352645u, 0, EXPM1F_TOLERANCE, 0},
+{2420, 1290175785u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2421, 981908840u, 3079358544u, 981913380u, 0, EXPM1F_TOLERANCE, 0},
+{2422, 941187647u, 3079358544u, 941187831u, 0, EXPM1F_TOLERANCE, 0},
+{2423, 1214223128u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2424, 3422922584u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2425, 1315857601u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2426, 3453226030u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2427, 1078359574u, 3079358544u, 1101644019u, 0, EXPM1F_TOLERANCE, 0},
+{2428, 1029557624u, 3079358544u, 1029958397u, 0, EXPM1F_TOLERANCE, 0},
+{2429, 1207675424u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2430, 1028355074u, 3079358544u, 1028691771u, 0, EXPM1F_TOLERANCE, 0},
+{2431, 3119299090u, 3079358544u, 3119295588u, 0, EXPM1F_TOLERANCE, 0},
+{2432, 1248421894u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2433, 3353251994u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2434, 876926659u, 3079358544u, 876926660u, 0, EXPM1F_TOLERANCE, 0},
+{2435, 1076752219u, 3079358544u, 1096963550u, 0, EXPM1F_TOLERANCE, 0},
+{2436, 3388531942u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2437, 1273395082u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2438, 3385588183u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2439, 3192315328u, 3079358544u, 3191127896u, 0, EXPM1F_TOLERANCE, 0},
+{2440, 3441804648u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2441, 3392827417u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2442, 1161241793u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2443, 3034494183u, 3079358544u, 3034494180u, 0, EXPM1F_TOLERANCE, 0},
+{2444, 1171318485u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2445, 3047748143u, 3079358544u, 3047748136u, 0, EXPM1F_TOLERANCE, 0},
+{2446, 1001216371u, 3079358544u, 1001246474u, 0, EXPM1F_TOLERANCE, 0},
+{2447, 912515889u, 3079358544u, 912515914u, 0, EXPM1F_TOLERANCE, 0},
+{2448, 3391452505u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2449, 3249603369u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2450, 1220264047u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2451, 3169816394u, 3079358544u, 3169589060u, 0, EXPM1F_TOLERANCE, 0},
+{2452, 3098997418u, 3079358544u, 3098996895u, 0, EXPM1F_TOLERANCE, 0},
+{2453, 3282212423u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2454, 3352293320u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2455, 3296358441u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2456, 1197828352u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2457, 3340510371u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2458, 1127109339u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2459, 909467381u, 3079358544u, 909467397u, 0, EXPM1F_TOLERANCE, 0},
+{2460, 1200599955u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2461, 962230977u, 3079358544u, 962232469u, 0, EXPM1F_TOLERANCE, 0},
+{2462, 3192887808u, 3079358544u, 3191597321u, 0, EXPM1F_TOLERANCE, 0},
+{2463, 3237183876u, 3079358544u, 3212828548u, 0, EXPM1F_TOLERANCE, 0},
+{2464, 939285924u, 3079358544u, 939286173u, 0, EXPM1F_TOLERANCE, 0},
+{2465, 944050180u, 3079358544u, 944050483u, 0, EXPM1F_TOLERANCE, 0},
+{2466, 3058135703u, 3079358544u, 3058135684u, 0, EXPM1F_TOLERANCE, 0},
+{2467, 3480592662u, 3079358544u, 3212836864u, 0, EXPM1F_TOLERANCE, 0},
+{2468, 3061939312u, 3079358544u, 3061939296u, 0, EXPM1F_TOLERANCE, 0},
+{2469, 1003299981u, 3079358544u, 1003342153u, 0, EXPM1F_TOLERANCE, 0},
+{2470, 1155775526u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0},
+{2471, 1234491880u, 3079358544u, 2139095040u, 0, EXPM1F_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_EXPM1F_H multiple inclusion protection
+
+// EOF expm1f.h
diff --git a/packages/language/c/libm/current/tests/vectors/fabsf.c b/packages/language/c/libm/current/tests/vectors/fabsf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/fabsf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      fabsf.c
+//
+//      Test of fabsf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/fabsf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(fabsf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &fabsf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &fabsf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("fabsf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("fabsf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library fabsf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "fabsf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF fabsf.c
diff --git a/packages/language/c/libm/current/tests/vectors/fabsf.h b/packages/language/c/libm/current/tests/vectors/fabsf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/fabsf.h
@@ -0,0 +1,1235 @@
+#ifndef CYGONCE_LIBM_FABSF_H
+#define CYGONCE_LIBM_FABSF_H
+//===========================================================================
+//
+//      fabsf.h
+//
+//      Test vectors for testing of fabsf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/fabsf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define FABSF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t fabsf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 0u, 1067030938u, 0, FABSF_TOLERANCE, 0},
+{1, 3214430700u, 0u, 1066947052u, 0, FABSF_TOLERANCE, 0},
+{2, 3214346813u, 0u, 1066863165u, 0, FABSF_TOLERANCE, 0},
+{3, 3214262927u, 0u, 1066779279u, 0, FABSF_TOLERANCE, 0},
+{4, 3214179041u, 0u, 1066695393u, 0, FABSF_TOLERANCE, 0},
+{5, 3214095155u, 0u, 1066611507u, 0, FABSF_TOLERANCE, 0},
+{6, 3214011269u, 0u, 1066527621u, 0, FABSF_TOLERANCE, 0},
+{7, 3213927383u, 0u, 1066443735u, 0, FABSF_TOLERANCE, 0},
+{8, 3213843497u, 0u, 1066359849u, 0, FABSF_TOLERANCE, 0},
+{9, 3213759611u, 0u, 1066275963u, 0, FABSF_TOLERANCE, 0},
+{10, 3213675725u, 0u, 1066192077u, 0, FABSF_TOLERANCE, 0},
+{11, 3213591839u, 0u, 1066108191u, 0, FABSF_TOLERANCE, 0},
+{12, 3213507953u, 0u, 1066024305u, 0, FABSF_TOLERANCE, 0},
+{13, 3213424067u, 0u, 1065940419u, 0, FABSF_TOLERANCE, 0},
+{14, 3213340180u, 0u, 1065856532u, 0, FABSF_TOLERANCE, 0},
+{15, 3213256294u, 0u, 1065772646u, 0, FABSF_TOLERANCE, 0},
+{16, 3213172408u, 0u, 1065688760u, 0, FABSF_TOLERANCE, 0},
+{17, 3213088522u, 0u, 1065604874u, 0, FABSF_TOLERANCE, 0},
+{18, 3213004636u, 0u, 1065520988u, 0, FABSF_TOLERANCE, 0},
+{19, 3212920750u, 0u, 1065437102u, 0, FABSF_TOLERANCE, 0},
+{20, 3212836864u, 0u, 1065353216u, 0, FABSF_TOLERANCE, 0},
+{21, 3212669092u, 0u, 1065185444u, 0, FABSF_TOLERANCE, 0},
+{22, 3212501320u, 0u, 1065017672u, 0, FABSF_TOLERANCE, 0},
+{23, 3212333548u, 0u, 1064849900u, 0, FABSF_TOLERANCE, 0},
+{24, 3212165775u, 0u, 1064682127u, 0, FABSF_TOLERANCE, 0},
+{25, 3211998003u, 0u, 1064514355u, 0, FABSF_TOLERANCE, 0},
+{26, 3211830231u, 0u, 1064346583u, 0, FABSF_TOLERANCE, 0},
+{27, 3211662459u, 0u, 1064178811u, 0, FABSF_TOLERANCE, 0},
+{28, 3211494687u, 0u, 1064011039u, 0, FABSF_TOLERANCE, 0},
+{29, 3211326915u, 0u, 1063843267u, 0, FABSF_TOLERANCE, 0},
+{30, 3211159142u, 0u, 1063675494u, 0, FABSF_TOLERANCE, 0},
+{31, 3210991370u, 0u, 1063507722u, 0, FABSF_TOLERANCE, 0},
+{32, 3210823598u, 0u, 1063339950u, 0, FABSF_TOLERANCE, 0},
+{33, 3210655826u, 0u, 1063172178u, 0, FABSF_TOLERANCE, 0},
+{34, 3210488054u, 0u, 1063004406u, 0, FABSF_TOLERANCE, 0},
+{35, 3210320282u, 0u, 1062836634u, 0, FABSF_TOLERANCE, 0},
+{36, 3210152509u, 0u, 1062668861u, 0, FABSF_TOLERANCE, 0},
+{37, 3209984737u, 0u, 1062501089u, 0, FABSF_TOLERANCE, 0},
+{38, 3209816965u, 0u, 1062333317u, 0, FABSF_TOLERANCE, 0},
+{39, 3209649193u, 0u, 1062165545u, 0, FABSF_TOLERANCE, 0},
+{40, 3209481421u, 0u, 1061997773u, 0, FABSF_TOLERANCE, 0},
+{41, 3209313649u, 0u, 1061830001u, 0, FABSF_TOLERANCE, 0},
+{42, 3209145876u, 0u, 1061662228u, 0, FABSF_TOLERANCE, 0},
+{43, 3208978104u, 0u, 1061494456u, 0, FABSF_TOLERANCE, 0},
+{44, 3208810332u, 0u, 1061326684u, 0, FABSF_TOLERANCE, 0},
+{45, 3208642560u, 0u, 1061158912u, 0, FABSF_TOLERANCE, 0},
+{46, 3208474788u, 0u, 1060991140u, 0, FABSF_TOLERANCE, 0},
+{47, 3208307016u, 0u, 1060823368u, 0, FABSF_TOLERANCE, 0},
+{48, 3208139244u, 0u, 1060655596u, 0, FABSF_TOLERANCE, 0},
+{49, 3207971471u, 0u, 1060487823u, 0, FABSF_TOLERANCE, 0},
+{50, 3207803699u, 0u, 1060320051u, 0, FABSF_TOLERANCE, 0},
+{51, 3207635927u, 0u, 1060152279u, 0, FABSF_TOLERANCE, 0},
+{52, 3207468155u, 0u, 1059984507u, 0, FABSF_TOLERANCE, 0},
+{53, 3207300383u, 0u, 1059816735u, 0, FABSF_TOLERANCE, 0},
+{54, 3207132611u, 0u, 1059648963u, 0, FABSF_TOLERANCE, 0},
+{55, 3206964838u, 0u, 1059481190u, 0, FABSF_TOLERANCE, 0},
+{56, 3206797066u, 0u, 1059313418u, 0, FABSF_TOLERANCE, 0},
+{57, 3206629294u, 0u, 1059145646u, 0, FABSF_TOLERANCE, 0},
+{58, 3206461522u, 0u, 1058977874u, 0, FABSF_TOLERANCE, 0},
+{59, 3206293750u, 0u, 1058810102u, 0, FABSF_TOLERANCE, 0},
+{60, 3206125978u, 0u, 1058642330u, 0, FABSF_TOLERANCE, 0},
+{61, 3205958205u, 0u, 1058474557u, 0, FABSF_TOLERANCE, 0},
+{62, 3205790433u, 0u, 1058306785u, 0, FABSF_TOLERANCE, 0},
+{63, 3205622661u, 0u, 1058139013u, 0, FABSF_TOLERANCE, 0},
+{64, 3205454889u, 0u, 1057971241u, 0, FABSF_TOLERANCE, 0},
+{65, 3205287117u, 0u, 1057803469u, 0, FABSF_TOLERANCE, 0},
+{66, 3205119345u, 0u, 1057635697u, 0, FABSF_TOLERANCE, 0},
+{67, 3204951572u, 0u, 1057467924u, 0, FABSF_TOLERANCE, 0},
+{68, 3204783800u, 0u, 1057300152u, 0, FABSF_TOLERANCE, 0},
+{69, 3204616028u, 0u, 1057132380u, 0, FABSF_TOLERANCE, 0},
+{70, 3204448256u, 0u, 1056964608u, 0, FABSF_TOLERANCE, 0},
+{71, 3204112712u, 0u, 1056629064u, 0, FABSF_TOLERANCE, 0},
+{72, 3203777167u, 0u, 1056293519u, 0, FABSF_TOLERANCE, 0},
+{73, 3203441623u, 0u, 1055957975u, 0, FABSF_TOLERANCE, 0},
+{74, 3203106079u, 0u, 1055622431u, 0, FABSF_TOLERANCE, 0},
+{75, 3202770534u, 0u, 1055286886u, 0, FABSF_TOLERANCE, 0},
+{76, 3202434990u, 0u, 1054951342u, 0, FABSF_TOLERANCE, 0},
+{77, 3202099446u, 0u, 1054615798u, 0, FABSF_TOLERANCE, 0},
+{78, 3201763901u, 0u, 1054280253u, 0, FABSF_TOLERANCE, 0},
+{79, 3201428357u, 0u, 1053944709u, 0, FABSF_TOLERANCE, 0},
+{80, 3201092813u, 0u, 1053609165u, 0, FABSF_TOLERANCE, 0},
+{81, 3200757268u, 0u, 1053273620u, 0, FABSF_TOLERANCE, 0},
+{82, 3200421724u, 0u, 1052938076u, 0, FABSF_TOLERANCE, 0},
+{83, 3200086180u, 0u, 1052602532u, 0, FABSF_TOLERANCE, 0},
+{84, 3199750636u, 0u, 1052266988u, 0, FABSF_TOLERANCE, 0},
+{85, 3199415091u, 0u, 1051931443u, 0, FABSF_TOLERANCE, 0},
+{86, 3199079547u, 0u, 1051595899u, 0, FABSF_TOLERANCE, 0},
+{87, 3198744003u, 0u, 1051260355u, 0, FABSF_TOLERANCE, 0},
+{88, 3198408458u, 0u, 1050924810u, 0, FABSF_TOLERANCE, 0},
+{89, 3198072914u, 0u, 1050589266u, 0, FABSF_TOLERANCE, 0},
+{90, 3197737370u, 0u, 1050253722u, 0, FABSF_TOLERANCE, 0},
+{91, 3197401825u, 0u, 1049918177u, 0, FABSF_TOLERANCE, 0},
+{92, 3197066281u, 0u, 1049582633u, 0, FABSF_TOLERANCE, 0},
+{93, 3196730737u, 0u, 1049247089u, 0, FABSF_TOLERANCE, 0},
+{94, 3196395192u, 0u, 1048911544u, 0, FABSF_TOLERANCE, 0},
+{95, 3196059648u, 0u, 1048576000u, 0, FABSF_TOLERANCE, 0},
+{96, 3195388559u, 0u, 1047904911u, 0, FABSF_TOLERANCE, 0},
+{97, 3194717471u, 0u, 1047233823u, 0, FABSF_TOLERANCE, 0},
+{98, 3194046382u, 0u, 1046562734u, 0, FABSF_TOLERANCE, 0},
+{99, 3193375293u, 0u, 1045891645u, 0, FABSF_TOLERANCE, 0},
+{100, 3192704205u, 0u, 1045220557u, 0, FABSF_TOLERANCE, 0},
+{101, 3192033116u, 0u, 1044549468u, 0, FABSF_TOLERANCE, 0},
+{102, 3191362028u, 0u, 1043878380u, 0, FABSF_TOLERANCE, 0},
+{103, 3190690939u, 0u, 1043207291u, 0, FABSF_TOLERANCE, 0},
+{104, 3190019850u, 0u, 1042536202u, 0, FABSF_TOLERANCE, 0},
+{105, 3189348762u, 0u, 1041865114u, 0, FABSF_TOLERANCE, 0},
+{106, 3188677673u, 0u, 1041194025u, 0, FABSF_TOLERANCE, 0},
+{107, 3188006584u, 0u, 1040522936u, 0, FABSF_TOLERANCE, 0},
+{108, 3186999951u, 0u, 1039516303u, 0, FABSF_TOLERANCE, 0},
+{109, 3185657774u, 0u, 1038174126u, 0, FABSF_TOLERANCE, 0},
+{110, 3184315597u, 0u, 1036831949u, 0, FABSF_TOLERANCE, 0},
+{111, 3182973420u, 0u, 1035489772u, 0, FABSF_TOLERANCE, 0},
+{112, 3181631242u, 0u, 1034147594u, 0, FABSF_TOLERANCE, 0},
+{113, 3180289065u, 0u, 1032805417u, 0, FABSF_TOLERANCE, 0},
+{114, 3178611343u, 0u, 1031127695u, 0, FABSF_TOLERANCE, 0},
+{115, 3175926989u, 0u, 1028443341u, 0, FABSF_TOLERANCE, 0},
+{116, 3173242634u, 0u, 1025758986u, 0, FABSF_TOLERANCE, 0},
+{117, 3170222735u, 0u, 1022739087u, 0, FABSF_TOLERANCE, 0},
+{118, 3164854026u, 0u, 1017370378u, 0, FABSF_TOLERANCE, 0},
+{119, 3156465418u, 0u, 1008981770u, 0, FABSF_TOLERANCE, 0},
+{120, 646742016u, 0u, 646742016u, 0, FABSF_TOLERANCE, 0},
+{121, 1008981770u, 0u, 1008981770u, 0, FABSF_TOLERANCE, 0},
+{122, 1017370378u, 0u, 1017370378u, 0, FABSF_TOLERANCE, 0},
+{123, 1022739087u, 0u, 1022739087u, 0, FABSF_TOLERANCE, 0},
+{124, 1025758986u, 0u, 1025758986u, 0, FABSF_TOLERANCE, 0},
+{125, 1028443341u, 0u, 1028443341u, 0, FABSF_TOLERANCE, 0},
+{126, 1031127695u, 0u, 1031127695u, 0, FABSF_TOLERANCE, 0},
+{127, 1032805417u, 0u, 1032805417u, 0, FABSF_TOLERANCE, 0},
+{128, 1034147594u, 0u, 1034147594u, 0, FABSF_TOLERANCE, 0},
+{129, 1035489772u, 0u, 1035489772u, 0, FABSF_TOLERANCE, 0},
+{130, 1036831949u, 0u, 1036831949u, 0, FABSF_TOLERANCE, 0},
+{131, 1038174126u, 0u, 1038174126u, 0, FABSF_TOLERANCE, 0},
+{132, 1039516303u, 0u, 1039516303u, 0, FABSF_TOLERANCE, 0},
+{133, 1040522936u, 0u, 1040522936u, 0, FABSF_TOLERANCE, 0},
+{134, 1041194025u, 0u, 1041194025u, 0, FABSF_TOLERANCE, 0},
+{135, 1041865114u, 0u, 1041865114u, 0, FABSF_TOLERANCE, 0},
+{136, 1042536202u, 0u, 1042536202u, 0, FABSF_TOLERANCE, 0},
+{137, 1043207291u, 0u, 1043207291u, 0, FABSF_TOLERANCE, 0},
+{138, 1043878380u, 0u, 1043878380u, 0, FABSF_TOLERANCE, 0},
+{139, 1044549468u, 0u, 1044549468u, 0, FABSF_TOLERANCE, 0},
+{140, 1045220557u, 0u, 1045220557u, 0, FABSF_TOLERANCE, 0},
+{141, 1045891645u, 0u, 1045891645u, 0, FABSF_TOLERANCE, 0},
+{142, 1046562734u, 0u, 1046562734u, 0, FABSF_TOLERANCE, 0},
+{143, 1047233823u, 0u, 1047233823u, 0, FABSF_TOLERANCE, 0},
+{144, 1047904911u, 0u, 1047904911u, 0, FABSF_TOLERANCE, 0},
+{145, 1048576000u, 0u, 1048576000u, 0, FABSF_TOLERANCE, 0},
+{146, 1048911544u, 0u, 1048911544u, 0, FABSF_TOLERANCE, 0},
+{147, 1049247089u, 0u, 1049247089u, 0, FABSF_TOLERANCE, 0},
+{148, 1049582633u, 0u, 1049582633u, 0, FABSF_TOLERANCE, 0},
+{149, 1049918177u, 0u, 1049918177u, 0, FABSF_TOLERANCE, 0},
+{150, 1050253722u, 0u, 1050253722u, 0, FABSF_TOLERANCE, 0},
+{151, 1050589266u, 0u, 1050589266u, 0, FABSF_TOLERANCE, 0},
+{152, 1050924810u, 0u, 1050924810u, 0, FABSF_TOLERANCE, 0},
+{153, 1051260355u, 0u, 1051260355u, 0, FABSF_TOLERANCE, 0},
+{154, 1051595899u, 0u, 1051595899u, 0, FABSF_TOLERANCE, 0},
+{155, 1051931443u, 0u, 1051931443u, 0, FABSF_TOLERANCE, 0},
+{156, 1052266988u, 0u, 1052266988u, 0, FABSF_TOLERANCE, 0},
+{157, 1052602532u, 0u, 1052602532u, 0, FABSF_TOLERANCE, 0},
+{158, 1052938076u, 0u, 1052938076u, 0, FABSF_TOLERANCE, 0},
+{159, 1053273620u, 0u, 1053273620u, 0, FABSF_TOLERANCE, 0},
+{160, 1053609165u, 0u, 1053609165u, 0, FABSF_TOLERANCE, 0},
+{161, 1053944709u, 0u, 1053944709u, 0, FABSF_TOLERANCE, 0},
+{162, 1054280253u, 0u, 1054280253u, 0, FABSF_TOLERANCE, 0},
+{163, 1054615798u, 0u, 1054615798u, 0, FABSF_TOLERANCE, 0},
+{164, 1054951342u, 0u, 1054951342u, 0, FABSF_TOLERANCE, 0},
+{165, 1055286886u, 0u, 1055286886u, 0, FABSF_TOLERANCE, 0},
+{166, 1055622431u, 0u, 1055622431u, 0, FABSF_TOLERANCE, 0},
+{167, 1055957975u, 0u, 1055957975u, 0, FABSF_TOLERANCE, 0},
+{168, 1056293519u, 0u, 1056293519u, 0, FABSF_TOLERANCE, 0},
+{169, 1056629064u, 0u, 1056629064u, 0, FABSF_TOLERANCE, 0},
+{170, 1056964608u, 0u, 1056964608u, 0, FABSF_TOLERANCE, 0},
+{171, 1057132380u, 0u, 1057132380u, 0, FABSF_TOLERANCE, 0},
+{172, 1057300152u, 0u, 1057300152u, 0, FABSF_TOLERANCE, 0},
+{173, 1057467924u, 0u, 1057467924u, 0, FABSF_TOLERANCE, 0},
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+{1043, 1283938137u, 1196383822u, 1283938137u, 0, FABSF_TOLERANCE, 0},
+{1044, 3182551696u, 3029982441u, 1035068048u, 0, FABSF_TOLERANCE, 0},
+{1045, 1317098613u, 949986176u, 1317098613u, 0, FABSF_TOLERANCE, 0},
+{1046, 3116209179u, 3303588342u, 968725531u, 0, FABSF_TOLERANCE, 0},
+{1047, 3431703657u, 3014443710u, 1284220009u, 0, FABSF_TOLERANCE, 0},
+{1048, 3239728775u, 927815421u, 1092245127u, 0, FABSF_TOLERANCE, 0},
+{1049, 3207141672u, 933456504u, 1059658024u, 0, FABSF_TOLERANCE, 0},
+{1050, 3154378805u, 905462392u, 1006895157u, 0, FABSF_TOLERANCE, 0},
+{1051, 3069658155u, 1041452042u, 922174507u, 0, FABSF_TOLERANCE, 0},
+{1052, 3313160088u, 2964063309u, 1165676440u, 0, FABSF_TOLERANCE, 0},
+{1053, 3207056527u, 3384206601u, 1059572879u, 0, FABSF_TOLERANCE, 0},
+{1054, 1284174954u, 3436881197u, 1284174954u, 0, FABSF_TOLERANCE, 0},
+{1055, 3156081645u, 3308839704u, 1008597997u, 0, FABSF_TOLERANCE, 0},
+{1056, 1063693032u, 976661408u, 1063693032u, 0, FABSF_TOLERANCE, 0},
+{1057, 3036026175u, 1251203998u, 888542527u, 0, FABSF_TOLERANCE, 0},
+{1058, 1102631663u, 3396951425u, 1102631663u, 0, FABSF_TOLERANCE, 0},
+{1059, 968803479u, 992989712u, 968803479u, 0, FABSF_TOLERANCE, 0},
+{1060, 3273080388u, 3109405906u, 1125596740u, 0, FABSF_TOLERANCE, 0},
+{1061, 1172529774u, 3294550127u, 1172529774u, 0, FABSF_TOLERANCE, 0},
+{1062, 1306695905u, 1292690378u, 1306695905u, 0, FABSF_TOLERANCE, 0},
+{1063, 1003649752u, 1218792138u, 1003649752u, 0, FABSF_TOLERANCE, 0},
+{1064, 1078478376u, 1326246424u, 1078478376u, 0, FABSF_TOLERANCE, 0},
+{1065, 3158855023u, 3151283866u, 1011371375u, 0, FABSF_TOLERANCE, 0},
+{1066, 1165177679u, 3276237026u, 1165177679u, 0, FABSF_TOLERANCE, 0},
+{1067, 3403009513u, 3381966453u, 1255525865u, 0, FABSF_TOLERANCE, 0},
+{1068, 952348506u, 3377573987u, 952348506u, 0, FABSF_TOLERANCE, 0},
+{1069, 1222777442u, 1125769920u, 1222777442u, 0, FABSF_TOLERANCE, 0},
+{1070, 1325324763u, 978336043u, 1325324763u, 0, FABSF_TOLERANCE, 0},
+{1071, 3363524213u, 3202991311u, 1216040565u, 0, FABSF_TOLERANCE, 0},
+{1072, 1158950321u, 1073578913u, 1158950321u, 0, FABSF_TOLERANCE, 0},
+{1073, 903129873u, 3416864271u, 903129873u, 0, FABSF_TOLERANCE, 0},
+{1074, 3078339944u, 988173985u, 930856296u, 0, FABSF_TOLERANCE, 0},
+{1075, 1208345407u, 1254181270u, 1208345407u, 0, FABSF_TOLERANCE, 0},
+{1076, 1258634105u, 1247426200u, 1258634105u, 0, FABSF_TOLERANCE, 0},
+{1077, 1248478509u, 1287895126u, 1248478509u, 0, FABSF_TOLERANCE, 0},
+{1078, 1153863988u, 3430539165u, 1153863988u, 0, FABSF_TOLERANCE, 0},
+{1079, 1235620969u, 866627358u, 1235620969u, 0, FABSF_TOLERANCE, 0},
+{1080, 1097120930u, 3221726305u, 1097120930u, 0, FABSF_TOLERANCE, 0},
+{1081, 3469778622u, 1200179013u, 1322294974u, 0, FABSF_TOLERANCE, 0},
+{1082, 1147712200u, 931865525u, 1147712200u, 0, FABSF_TOLERANCE, 0},
+{1083, 1124721745u, 3058969650u, 1124721745u, 0, FABSF_TOLERANCE, 0},
+{1084, 3261744304u, 1043806501u, 1114260656u, 0, FABSF_TOLERANCE, 0},
+{1085, 1064922416u, 1320485628u, 1064922416u, 0, FABSF_TOLERANCE, 0},
+{1086, 3303160152u, 3075455322u, 1155676504u, 0, FABSF_TOLERANCE, 0},
+{1087, 1315090496u, 3269683237u, 1315090496u, 0, FABSF_TOLERANCE, 0},
+{1088, 3230403187u, 1322841992u, 1082919539u, 0, FABSF_TOLERANCE, 0},
+{1089, 1335399673u, 974138676u, 1335399673u, 0, FABSF_TOLERANCE, 0},
+{1090, 1072458508u, 3372833993u, 1072458508u, 0, FABSF_TOLERANCE, 0},
+{1091, 3303015249u, 3015039539u, 1155531601u, 0, FABSF_TOLERANCE, 0},
+{1092, 3252139741u, 1059615003u, 1104656093u, 0, FABSF_TOLERANCE, 0},
+{1093, 3468519966u, 3113982619u, 1321036318u, 0, FABSF_TOLERANCE, 0},
+{1094, 1006231203u, 897530770u, 1006231203u, 0, FABSF_TOLERANCE, 0},
+{1095, 951554138u, 1001144381u, 951554138u, 0, FABSF_TOLERANCE, 0},
+{1096, 942046828u, 986341002u, 942046828u, 0, FABSF_TOLERANCE, 0},
+{1097, 3319723279u, 3414482416u, 1172239631u, 0, FABSF_TOLERANCE, 0},
+{1098, 3255104167u, 928827688u, 1107620519u, 0, FABSF_TOLERANCE, 0},
+{1099, 1155477903u, 3104812800u, 1155477903u, 0, FABSF_TOLERANCE, 0},
+{1100, 3273889176u, 980486479u, 1126405528u, 0, FABSF_TOLERANCE, 0},
+{1101, 3237813668u, 3441016803u, 1090330020u, 0, FABSF_TOLERANCE, 0},
+{1102, 1228207362u, 2985476579u, 1228207362u, 0, FABSF_TOLERANCE, 0},
+{1103, 975349337u, 1311932596u, 975349337u, 0, FABSF_TOLERANCE, 0},
+{1104, 1290175785u, 3008182462u, 1290175785u, 0, FABSF_TOLERANCE, 0},
+{1105, 981908840u, 3314038398u, 981908840u, 0, FABSF_TOLERANCE, 0},
+{1106, 941187647u, 1107765599u, 941187647u, 0, FABSF_TOLERANCE, 0},
+{1107, 1214223128u, 3225536822u, 1214223128u, 0, FABSF_TOLERANCE, 0},
+{1108, 3422922584u, 1086391131u, 1275438936u, 0, FABSF_TOLERANCE, 0},
+{1109, 1315857601u, 3487600045u, 1315857601u, 0, FABSF_TOLERANCE, 0},
+{1110, 3453226030u, 3233768835u, 1305742382u, 0, FABSF_TOLERANCE, 0},
+{1111, 1078359574u, 3199175230u, 1078359574u, 0, FABSF_TOLERANCE, 0},
+{1112, 1029557624u, 3302959071u, 1029557624u, 0, FABSF_TOLERANCE, 0},
+{1113, 1207675424u, 3042692550u, 1207675424u, 0, FABSF_TOLERANCE, 0},
+{1114, 1028355074u, 3442294040u, 1028355074u, 0, FABSF_TOLERANCE, 0},
+{1115, 3119299090u, 1187096397u, 971815442u, 0, FABSF_TOLERANCE, 0},
+{1116, 1248421894u, 3367769132u, 1248421894u, 0, FABSF_TOLERANCE, 0},
+{1117, 3353251994u, 1095517730u, 1205768346u, 0, FABSF_TOLERANCE, 0},
+{1118, 876926659u, 3288089977u, 876926659u, 0, FABSF_TOLERANCE, 0},
+{1119, 1076752219u, 876236939u, 1076752219u, 0, FABSF_TOLERANCE, 0},
+{1120, 3388531942u, 2988520062u, 1241048294u, 0, FABSF_TOLERANCE, 0},
+{1121, 1273395082u, 3031189261u, 1273395082u, 0, FABSF_TOLERANCE, 0},
+{1122, 3385588183u, 3258252464u, 1238104535u, 0, FABSF_TOLERANCE, 0},
+{1123, 3192315328u, 3289489214u, 1044831680u, 0, FABSF_TOLERANCE, 0},
+{1124, 3441804648u, 3274638356u, 1294321000u, 0, FABSF_TOLERANCE, 0},
+{1125, 3392827417u, 1277961150u, 1245343769u, 0, FABSF_TOLERANCE, 0},
+{1126, 1161241793u, 1328003707u, 1161241793u, 0, FABSF_TOLERANCE, 0},
+{1127, 3034494183u, 3041579130u, 887010535u, 0, FABSF_TOLERANCE, 0},
+{1128, 1171318485u, 3374409104u, 1171318485u, 0, FABSF_TOLERANCE, 0},
+{1129, 3047748143u, 831102792u, 900264495u, 0, FABSF_TOLERANCE, 0},
+{1130, 1001216371u, 3052357038u, 1001216371u, 0, FABSF_TOLERANCE, 0},
+{1131, 912515889u, 1074635609u, 912515889u, 0, FABSF_TOLERANCE, 0},
+{1132, 3391452505u, 897989232u, 1243968857u, 0, FABSF_TOLERANCE, 0},
+{1133, 3249603369u, 3147662248u, 1102119721u, 0, FABSF_TOLERANCE, 0},
+{1134, 1220264047u, 2960450369u, 1220264047u, 0, FABSF_TOLERANCE, 0},
+{1135, 3169816394u, 988430929u, 1022332746u, 0, FABSF_TOLERANCE, 0},
+{1136, 3098997418u, 3002162688u, 951513770u, 0, FABSF_TOLERANCE, 0},
+{1137, 3282212423u, 3174079140u, 1134728775u, 0, FABSF_TOLERANCE, 0},
+{1138, 3352293320u, 3247843425u, 1204809672u, 0, FABSF_TOLERANCE, 0},
+{1139, 3296358441u, 875645354u, 1148874793u, 0, FABSF_TOLERANCE, 0},
+{1140, 1197828352u, 3245614728u, 1197828352u, 0, FABSF_TOLERANCE, 0},
+{1141, 3340510371u, 914930263u, 1193026723u, 0, FABSF_TOLERANCE, 0},
+{1142, 1127109339u, 3368125489u, 1127109339u, 0, FABSF_TOLERANCE, 0},
+{1143, 909467381u, 1232375752u, 909467381u, 0, FABSF_TOLERANCE, 0},
+{1144, 1200599955u, 2981200675u, 1200599955u, 0, FABSF_TOLERANCE, 0},
+{1145, 962230977u, 2988248037u, 962230977u, 0, FABSF_TOLERANCE, 0},
+{1146, 3192887808u, 3191848339u, 1045404160u, 0, FABSF_TOLERANCE, 0},
+{1147, 3237183876u, 3179379969u, 1089700228u, 0, FABSF_TOLERANCE, 0},
+{1148, 939285924u, 3056079386u, 939285924u, 0, FABSF_TOLERANCE, 0},
+{1149, 944050180u, 3452557879u, 944050180u, 0, FABSF_TOLERANCE, 0},
+{1150, 3058135703u, 3090284601u, 910652055u, 0, FABSF_TOLERANCE, 0},
+{1151, 3480592662u, 3261728191u, 1333109014u, 0, FABSF_TOLERANCE, 0},
+{1152, 3061939312u, 3274418540u, 914455664u, 0, FABSF_TOLERANCE, 0},
+{1153, 1003299981u, 853295521u, 1003299981u, 0, FABSF_TOLERANCE, 0},
+{1154, 1155775526u, 1255814444u, 1155775526u, 0, FABSF_TOLERANCE, 0},
+{1155, 1234491880u, 3408568717u, 1234491880u, 0, FABSF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_FABSF_H multiple inclusion protection
+
+// EOF fabsf.h
diff --git a/packages/language/c/libm/current/tests/vectors/finitef.c b/packages/language/c/libm/current/tests/vectors/finitef.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/finitef.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      finitef.c
+//
+//      Test of finitef() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/finitef.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(finitef_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &finitef, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &finitef_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("finitef() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("finitef() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library finitef() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "finitef() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF finitef.c
diff --git a/packages/language/c/libm/current/tests/vectors/finitef.h b/packages/language/c/libm/current/tests/vectors/finitef.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/finitef.h
@@ -0,0 +1,1362 @@
+#ifndef CYGONCE_LIBM_FINITEF_H
+#define CYGONCE_LIBM_FINITEF_H
+//===========================================================================
+//
+//      finitef.h
+//
+//      Test vectors for testing of finitef() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/finitef.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define FINITEF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t finitef_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1, 3214430700u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{2, 3214346813u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{3, 3214262927u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{4, 3214179041u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{5, 3214095155u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{6, 3214011269u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{7, 3213927383u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{8, 3213843497u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{9, 3213759611u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{10, 3213675725u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{11, 3213591839u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{12, 3213507953u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{13, 3213424067u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{14, 3213340180u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{15, 3213256294u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{16, 3213172408u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{17, 3213088522u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{18, 3213004636u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{19, 3212920750u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{20, 3212836864u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{21, 3212669092u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{22, 3212501320u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{23, 3212333548u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{24, 3212165775u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{25, 3211998003u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{26, 3211830231u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{27, 3211662459u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{28, 3211494687u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{29, 3211326915u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{30, 3211159142u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{31, 3210991370u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{32, 3210823598u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{33, 3210655826u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{34, 3210488054u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{35, 3210320282u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{36, 3210152509u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{37, 3209984737u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{38, 3209816965u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{39, 3209649193u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{40, 3209481421u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{41, 3209313649u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{42, 3209145876u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{43, 3208978104u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{44, 3208810332u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{45, 3208642560u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
+{46, 3208474788u, 0u, 1u, 0, FINITEF_TOLERANCE, 0},
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+{1236, 3119299090u, 1187096397u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1237, 1248421894u, 3367769132u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1238, 3353251994u, 1095517730u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1239, 876926659u, 3288089977u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1240, 1076752219u, 876236939u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1241, 3388531942u, 2988520062u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1242, 1273395082u, 3031189261u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1243, 3385588183u, 3258252464u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1244, 862047095u, 829323655u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1245, 3192315328u, 3289489214u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1246, 3441804648u, 3274638356u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1247, 837368567u, 3228474927u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1248, 3392827417u, 1277961150u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1249, 1161241793u, 1328003707u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1250, 856495732u, 3123041418u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1251, 3034494183u, 3041579130u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1252, 1171318485u, 3374409104u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1253, 3047748143u, 831102792u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1254, 1001216371u, 3052357038u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1255, 2999541351u, 3085461799u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1256, 912515889u, 1074635609u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1257, 3391452505u, 897989232u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1258, 3249603369u, 3147662248u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1259, 1220264047u, 2960450369u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1260, 3169816394u, 988430929u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1261, 3098997418u, 3002162688u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1262, 3282212423u, 3174079140u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1263, 3352293320u, 3247843425u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1264, 3296358441u, 875645354u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1265, 1197828352u, 3245614728u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1266, 3340510371u, 914930263u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1267, 1127109339u, 3368125489u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1268, 816173492u, 1083268662u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1269, 909467381u, 1232375752u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1270, 1200599955u, 2981200675u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1271, 962230977u, 2988248037u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1272, 2996667337u, 1068572835u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1273, 3192887808u, 3191848339u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1274, 3237183876u, 3179379969u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1275, 939285924u, 3056079386u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1276, 944050180u, 3452557879u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1277, 3058135703u, 3090284601u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1278, 3480592662u, 3261728191u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1279, 3061939312u, 3274418540u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1280, 1003299981u, 853295521u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1281, 1155775526u, 1255814444u, 1u, 0, FINITEF_TOLERANCE, 0},
+{1282, 1234491880u, 3408568717u, 1u, 0, FINITEF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_FINITEF_H multiple inclusion protection
+
+// EOF finitef.h
diff --git a/packages/language/c/libm/current/tests/vectors/floorf.c b/packages/language/c/libm/current/tests/vectors/floorf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/floorf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      floorf.c
+//
+//      Test of floorf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/floorf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(floorf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &floorf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &floorf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("floorf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("floorf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library floorf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "floorf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF floorf.c
diff --git a/packages/language/c/libm/current/tests/vectors/floorf.h b/packages/language/c/libm/current/tests/vectors/floorf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/floorf.h
@@ -0,0 +1,1235 @@
+#ifndef CYGONCE_LIBM_FLOORF_H
+#define CYGONCE_LIBM_FLOORF_H
+//===========================================================================
+//
+//      floorf.h
+//
+//      Test vectors for testing of floorf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/floorf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define FLOORF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t floorf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{1, 3214430700u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{2, 3214346813u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{3, 3214262927u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{4, 3214179041u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{5, 3214095155u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{6, 3214011269u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{7, 3213927383u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{8, 3213843497u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{9, 3213759611u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{10, 3213675725u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{11, 3213591839u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{12, 3213507953u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{13, 3213424067u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{14, 3213340180u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{15, 3213256294u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{16, 3213172408u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{17, 3213088522u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{18, 3213004636u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{19, 3212920750u, 0u, 3221225472u, 0, FLOORF_TOLERANCE, 0},
+{20, 3212836864u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{21, 3212669092u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{22, 3212501320u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{23, 3212333548u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{24, 3212165775u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{25, 3211998003u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{26, 3211830231u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{27, 3211662459u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{28, 3211494687u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{29, 3211326915u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{30, 3211159142u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{31, 3210991370u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{32, 3210823598u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{33, 3210655826u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{34, 3210488054u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{35, 3210320282u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{36, 3210152509u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{37, 3209984737u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{38, 3209816965u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{39, 3209649193u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{40, 3209481421u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{41, 3209313649u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{42, 3209145876u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{43, 3208978104u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{44, 3208810332u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{45, 3208642560u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{46, 3208474788u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{47, 3208307016u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{48, 3208139244u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{49, 3207971471u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{50, 3207803699u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{51, 3207635927u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{52, 3207468155u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{53, 3207300383u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{54, 3207132611u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{55, 3206964838u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{56, 3206797066u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{57, 3206629294u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{58, 3206461522u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{59, 3206293750u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{60, 3206125978u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{61, 3205958205u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{62, 3205790433u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{63, 3205622661u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{64, 3205454889u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{65, 3205287117u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{66, 3205119345u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{67, 3204951572u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{68, 3204783800u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{69, 3204616028u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{70, 3204448256u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{71, 3204112712u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{72, 3203777167u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{73, 3203441623u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{74, 3203106079u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{75, 3202770534u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{76, 3202434990u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{77, 3202099446u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{78, 3201763901u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{79, 3201428357u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{80, 3201092813u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{81, 3200757268u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{82, 3200421724u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{83, 3200086180u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{84, 3199750636u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{85, 3199415091u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{86, 3199079547u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{87, 3198744003u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{88, 3198408458u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{89, 3198072914u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{90, 3197737370u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{91, 3197401825u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{92, 3197066281u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{93, 3196730737u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{94, 3196395192u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{95, 3196059648u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{96, 3195388559u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{97, 3194717471u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{98, 3194046382u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{99, 3193375293u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{100, 3192704205u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{101, 3192033116u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{102, 3191362028u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{103, 3190690939u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{104, 3190019850u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{105, 3189348762u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{106, 3188677673u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{107, 3188006584u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{108, 3186999951u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{109, 3185657774u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{110, 3184315597u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{111, 3182973420u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{112, 3181631242u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{113, 3180289065u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{114, 3178611343u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{115, 3175926989u, 0u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
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+{976, 948856035u, 1015466475u, 0u, 0, FLOORF_TOLERANCE, 0},
+{977, 1062512367u, 3229559531u, 0u, 0, FLOORF_TOLERANCE, 0},
+{978, 3486907092u, 823220784u, 3486907092u, 0, FLOORF_TOLERANCE, 0},
+{979, 1162027071u, 3308983387u, 1162027008u, 0, FLOORF_TOLERANCE, 0},
+{980, 1034561811u, 1054043114u, 0u, 0, FLOORF_TOLERANCE, 0},
+{981, 3271615417u, 3209997200u, 3271622656u, 0, FLOORF_TOLERANCE, 0},
+{982, 1042014529u, 1146708584u, 0u, 0, FLOORF_TOLERANCE, 0},
+{983, 1177157787u, 3090208179u, 1177157632u, 0, FLOORF_TOLERANCE, 0},
+{984, 3196144817u, 1056118717u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{985, 3432084552u, 2997091781u, 3432084552u, 0, FLOORF_TOLERANCE, 0},
+{986, 1309658335u, 1010219988u, 1309658335u, 0, FLOORF_TOLERANCE, 0},
+{987, 1226494979u, 2991604792u, 1226494976u, 0, FLOORF_TOLERANCE, 0},
+{988, 3100289712u, 3456334210u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{989, 3375507013u, 1306310823u, 3375507024u, 0, FLOORF_TOLERANCE, 0},
+{990, 3460699001u, 3096700943u, 3460699001u, 0, FLOORF_TOLERANCE, 0},
+{991, 3079231719u, 1044386263u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{992, 3093951884u, 1014115231u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{993, 3468023178u, 1209565017u, 3468023178u, 0, FLOORF_TOLERANCE, 0},
+{994, 1204196034u, 3298625731u, 1204195968u, 0, FLOORF_TOLERANCE, 0},
+{995, 3459877411u, 2960476959u, 3459877411u, 0, FLOORF_TOLERANCE, 0},
+{996, 909696559u, 1163075690u, 0u, 0, FLOORF_TOLERANCE, 0},
+{997, 1161439847u, 943449277u, 1161437184u, 0, FLOORF_TOLERANCE, 0},
+{998, 908663107u, 939489763u, 0u, 0, FLOORF_TOLERANCE, 0},
+{999, 1055319316u, 3261813492u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1000, 1084378658u, 1009650785u, 1084227584u, 0, FLOORF_TOLERANCE, 0},
+{1001, 3053887750u, 3341786453u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1002, 3022828828u, 881335251u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1003, 1226473697u, 821025132u, 1226473696u, 0, FLOORF_TOLERANCE, 0},
+{1004, 1123114742u, 1229815537u, 1123024896u, 0, FLOORF_TOLERANCE, 0},
+{1005, 1258114435u, 1291336083u, 1258114434u, 0, FLOORF_TOLERANCE, 0},
+{1006, 3468040845u, 3066966245u, 3468040845u, 0, FLOORF_TOLERANCE, 0},
+{1007, 1178825761u, 1113195286u, 1178825728u, 0, FLOORF_TOLERANCE, 0},
+{1008, 3059266302u, 878503862u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1009, 3223384012u, 1130486973u, 3225419776u, 0, FLOORF_TOLERANCE, 0},
+{1010, 1019964626u, 1235133609u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1011, 3445262427u, 3465211174u, 3445262427u, 0, FLOORF_TOLERANCE, 0},
+{1012, 1125653081u, 1207799746u, 1125646336u, 0, FLOORF_TOLERANCE, 0},
+{1013, 3337652712u, 3025581813u, 3337652736u, 0, FLOORF_TOLERANCE, 0},
+{1014, 1184753508u, 3147374485u, 1184753152u, 0, FLOORF_TOLERANCE, 0},
+{1015, 996404791u, 3353251979u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1016, 1188439315u, 1113484271u, 1188439040u, 0, FLOORF_TOLERANCE, 0},
+{1017, 906557513u, 3006513432u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1018, 916831283u, 999465787u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1019, 996786317u, 3179221951u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1020, 3461635065u, 1004690387u, 3461635065u, 0, FLOORF_TOLERANCE, 0},
+{1021, 1188167943u, 1200744896u, 1188167680u, 0, FLOORF_TOLERANCE, 0},
+{1022, 3036502395u, 1172597364u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1023, 891257783u, 1267560050u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1024, 3290079438u, 846519377u, 3290087424u, 0, FLOORF_TOLERANCE, 0},
+{1025, 3350690327u, 2967953392u, 3350690432u, 0, FLOORF_TOLERANCE, 0},
+{1026, 1102061604u, 3424449935u, 1102053376u, 0, FLOORF_TOLERANCE, 0},
+{1027, 1282351521u, 3039376424u, 1282351521u, 0, FLOORF_TOLERANCE, 0},
+{1028, 3458861065u, 3392466405u, 3458861065u, 0, FLOORF_TOLERANCE, 0},
+{1029, 3095256878u, 1023623326u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1030, 3163373610u, 843150426u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1031, 3228793330u, 855146890u, 3229614080u, 0, FLOORF_TOLERANCE, 0},
+{1032, 3422194733u, 893873945u, 3422194733u, 0, FLOORF_TOLERANCE, 0},
+{1033, 3083885296u, 974543672u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1034, 1261940623u, 3402349985u, 1261940622u, 0, FLOORF_TOLERANCE, 0},
+{1035, 3400603081u, 3234396843u, 3400603082u, 0, FLOORF_TOLERANCE, 0},
+{1036, 1219411812u, 2961857939u, 1219411808u, 0, FLOORF_TOLERANCE, 0},
+{1037, 3094833770u, 805351108u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1038, 3139250800u, 3079109479u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1039, 886201503u, 3272760705u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1040, 3297366026u, 1089966380u, 3297370112u, 0, FLOORF_TOLERANCE, 0},
+{1041, 1218488455u, 3309646450u, 1218488448u, 0, FLOORF_TOLERANCE, 0},
+{1042, 3040358923u, 3093401553u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1043, 1283938137u, 1196383822u, 1283938137u, 0, FLOORF_TOLERANCE, 0},
+{1044, 3182551696u, 3029982441u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1045, 1317098613u, 949986176u, 1317098613u, 0, FLOORF_TOLERANCE, 0},
+{1046, 3116209179u, 3303588342u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1047, 3431703657u, 3014443710u, 3431703657u, 0, FLOORF_TOLERANCE, 0},
+{1048, 3239728775u, 927815421u, 3240099840u, 0, FLOORF_TOLERANCE, 0},
+{1049, 3207141672u, 933456504u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1050, 3154378805u, 905462392u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1051, 3069658155u, 1041452042u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1052, 3313160088u, 2964063309u, 3313160192u, 0, FLOORF_TOLERANCE, 0},
+{1053, 3207056527u, 3384206601u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1054, 1284174954u, 3436881197u, 1284174954u, 0, FLOORF_TOLERANCE, 0},
+{1055, 3156081645u, 3308839704u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1056, 1063693032u, 976661408u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1057, 3036026175u, 1251203998u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1058, 1102631663u, 3396951425u, 1102577664u, 0, FLOORF_TOLERANCE, 0},
+{1059, 968803479u, 992989712u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1060, 3273080388u, 3109405906u, 3273129984u, 0, FLOORF_TOLERANCE, 0},
+{1061, 1172529774u, 3294550127u, 1172529152u, 0, FLOORF_TOLERANCE, 0},
+{1062, 1306695905u, 1292690378u, 1306695905u, 0, FLOORF_TOLERANCE, 0},
+{1063, 1003649752u, 1218792138u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1064, 1078478376u, 1326246424u, 1077936128u, 0, FLOORF_TOLERANCE, 0},
+{1065, 3158855023u, 3151283866u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1066, 1165177679u, 3276237026u, 1165176832u, 0, FLOORF_TOLERANCE, 0},
+{1067, 3403009513u, 3381966453u, 3403009514u, 0, FLOORF_TOLERANCE, 0},
+{1068, 952348506u, 3377573987u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1069, 1222777442u, 1125769920u, 1222777440u, 0, FLOORF_TOLERANCE, 0},
+{1070, 1325324763u, 978336043u, 1325324763u, 0, FLOORF_TOLERANCE, 0},
+{1071, 3363524213u, 3202991311u, 3363524224u, 0, FLOORF_TOLERANCE, 0},
+{1072, 1158950321u, 1073578913u, 1158946816u, 0, FLOORF_TOLERANCE, 0},
+{1073, 903129873u, 3416864271u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1074, 3078339944u, 988173985u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1075, 1208345407u, 1254181270u, 1208345344u, 0, FLOORF_TOLERANCE, 0},
+{1076, 1258634105u, 1247426200u, 1258634104u, 0, FLOORF_TOLERANCE, 0},
+{1077, 1248478509u, 1287895126u, 1248478508u, 0, FLOORF_TOLERANCE, 0},
+{1078, 1153863988u, 3430539165u, 1153859584u, 0, FLOORF_TOLERANCE, 0},
+{1079, 1235620969u, 866627358u, 1235620968u, 0, FLOORF_TOLERANCE, 0},
+{1080, 1097120930u, 3221726305u, 1096810496u, 0, FLOORF_TOLERANCE, 0},
+{1081, 3469778622u, 1200179013u, 3469778622u, 0, FLOORF_TOLERANCE, 0},
+{1082, 1147712200u, 931865525u, 1147699200u, 0, FLOORF_TOLERANCE, 0},
+{1083, 1124721745u, 3058969650u, 1124663296u, 0, FLOORF_TOLERANCE, 0},
+{1084, 3261744304u, 1043806501u, 3261857792u, 0, FLOORF_TOLERANCE, 0},
+{1085, 1064922416u, 1320485628u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1086, 3303160152u, 3075455322u, 3303161856u, 0, FLOORF_TOLERANCE, 0},
+{1087, 1315090496u, 3269683237u, 1315090496u, 0, FLOORF_TOLERANCE, 0},
+{1088, 3230403187u, 1322841992u, 3231711232u, 0, FLOORF_TOLERANCE, 0},
+{1089, 1335399673u, 974138676u, 1335399673u, 0, FLOORF_TOLERANCE, 0},
+{1090, 1072458508u, 3372833993u, 1065353216u, 0, FLOORF_TOLERANCE, 0},
+{1091, 3303015249u, 3015039539u, 3303022592u, 0, FLOORF_TOLERANCE, 0},
+{1092, 3252139741u, 1059615003u, 3252158464u, 0, FLOORF_TOLERANCE, 0},
+{1093, 3468519966u, 3113982619u, 3468519966u, 0, FLOORF_TOLERANCE, 0},
+{1094, 1006231203u, 897530770u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1095, 951554138u, 1001144381u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1096, 942046828u, 986341002u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1097, 3319723279u, 3414482416u, 3319724032u, 0, FLOORF_TOLERANCE, 0},
+{1098, 3255104167u, 928827688u, 3255304192u, 0, FLOORF_TOLERANCE, 0},
+{1099, 1155477903u, 3104812800u, 1155473408u, 0, FLOORF_TOLERANCE, 0},
+{1100, 3273889176u, 980486479u, 3273916416u, 0, FLOORF_TOLERANCE, 0},
+{1101, 3237813668u, 3441016803u, 3238002688u, 0, FLOORF_TOLERANCE, 0},
+{1102, 1228207362u, 2985476579u, 1228207360u, 0, FLOORF_TOLERANCE, 0},
+{1103, 975349337u, 1311932596u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1104, 1290175785u, 3008182462u, 1290175785u, 0, FLOORF_TOLERANCE, 0},
+{1105, 981908840u, 3314038398u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1106, 941187647u, 1107765599u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1107, 1214223128u, 3225536822u, 1214223104u, 0, FLOORF_TOLERANCE, 0},
+{1108, 3422922584u, 1086391131u, 3422922584u, 0, FLOORF_TOLERANCE, 0},
+{1109, 1315857601u, 3487600045u, 1315857601u, 0, FLOORF_TOLERANCE, 0},
+{1110, 3453226030u, 3233768835u, 3453226030u, 0, FLOORF_TOLERANCE, 0},
+{1111, 1078359574u, 3199175230u, 1077936128u, 0, FLOORF_TOLERANCE, 0},
+{1112, 1029557624u, 3302959071u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1113, 1207675424u, 3042692550u, 1207675392u, 0, FLOORF_TOLERANCE, 0},
+{1114, 1028355074u, 3442294040u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1115, 3119299090u, 1187096397u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1116, 1248421894u, 3367769132u, 1248421892u, 0, FLOORF_TOLERANCE, 0},
+{1117, 3353251994u, 1095517730u, 3353252096u, 0, FLOORF_TOLERANCE, 0},
+{1118, 876926659u, 3288089977u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1119, 1076752219u, 876236939u, 1073741824u, 0, FLOORF_TOLERANCE, 0},
+{1120, 3388531942u, 2988520062u, 3388531944u, 0, FLOORF_TOLERANCE, 0},
+{1121, 1273395082u, 3031189261u, 1273395082u, 0, FLOORF_TOLERANCE, 0},
+{1122, 3385588183u, 3258252464u, 3385588184u, 0, FLOORF_TOLERANCE, 0},
+{1123, 3192315328u, 3289489214u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1124, 3441804648u, 3274638356u, 3441804648u, 0, FLOORF_TOLERANCE, 0},
+{1125, 3392827417u, 1277961150u, 3392827420u, 0, FLOORF_TOLERANCE, 0},
+{1126, 1161241793u, 1328003707u, 1161240576u, 0, FLOORF_TOLERANCE, 0},
+{1127, 3034494183u, 3041579130u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1128, 1171318485u, 3374409104u, 1171316736u, 0, FLOORF_TOLERANCE, 0},
+{1129, 3047748143u, 831102792u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1130, 1001216371u, 3052357038u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1131, 912515889u, 1074635609u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1132, 3391452505u, 897989232u, 3391452508u, 0, FLOORF_TOLERANCE, 0},
+{1133, 3249603369u, 3147662248u, 3250061312u, 0, FLOORF_TOLERANCE, 0},
+{1134, 1220264047u, 2960450369u, 1220264032u, 0, FLOORF_TOLERANCE, 0},
+{1135, 3169816394u, 988430929u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1136, 3098997418u, 3002162688u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1137, 3282212423u, 3174079140u, 3282239488u, 0, FLOORF_TOLERANCE, 0},
+{1138, 3352293320u, 3247843425u, 3352293376u, 0, FLOORF_TOLERANCE, 0},
+{1139, 3296358441u, 875645354u, 3296362496u, 0, FLOORF_TOLERANCE, 0},
+{1140, 1197828352u, 3245614728u, 1197828096u, 0, FLOORF_TOLERANCE, 0},
+{1141, 3340510371u, 914930263u, 3340510464u, 0, FLOORF_TOLERANCE, 0},
+{1142, 1127109339u, 3368125489u, 1127088128u, 0, FLOORF_TOLERANCE, 0},
+{1143, 909467381u, 1232375752u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1144, 1200599955u, 2981200675u, 1200599936u, 0, FLOORF_TOLERANCE, 0},
+{1145, 962230977u, 2988248037u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1146, 3192887808u, 3191848339u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1147, 3237183876u, 3179379969u, 3238002688u, 0, FLOORF_TOLERANCE, 0},
+{1148, 939285924u, 3056079386u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1149, 944050180u, 3452557879u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1150, 3058135703u, 3090284601u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1151, 3480592662u, 3261728191u, 3480592662u, 0, FLOORF_TOLERANCE, 0},
+{1152, 3061939312u, 3274418540u, 3212836864u, 0, FLOORF_TOLERANCE, 0},
+{1153, 1003299981u, 853295521u, 0u, 0, FLOORF_TOLERANCE, 0},
+{1154, 1155775526u, 1255814444u, 1155768320u, 0, FLOORF_TOLERANCE, 0},
+{1155, 1234491880u, 3408568717u, 1234491880u, 0, FLOORF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_FLOORF_H multiple inclusion protection
+
+// EOF floorf.h
diff --git a/packages/language/c/libm/current/tests/vectors/fmodf.c b/packages/language/c/libm/current/tests/vectors/fmodf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/fmodf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      fmod.c
+//
+//      Test of fmod() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_double_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/fmodf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(fmodf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &fmodf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_FLOAT, CYG_LIBM_TEST_VEC_FLOAT,
+                     &fmodf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("fmodf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("fmodf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library fmodf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "fmod() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF fmod.c
diff --git a/packages/language/c/libm/current/tests/vectors/fmodf.h b/packages/language/c/libm/current/tests/vectors/fmodf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/fmodf.h
@@ -0,0 +1,629 @@
+#ifndef CYGONCE_LIBM_FMOD_H
+#define CYGONCE_LIBM_FMOD_H
+//===========================================================================
+//
+//      fmod.h
+//
+//      Test vectors for testing of fmod() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/fmod.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define FMOD_TOLERANCE 2.0E-04
+
+static const Cyg_libm_test_float_vec_t fmodf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 1077097267u, 3214514586u, 0, FMOD_TOLERANCE, 0},
+{1, 3214430700u, 1077139210u, 3214430700u, 0, FMOD_TOLERANCE, 0},
+{2, 3214346813u, 1077181153u, 3214346813u, 0, FMOD_TOLERANCE, 0},
+{3, 3214262927u, 1077223096u, 3214262927u, 0, FMOD_TOLERANCE, 0},
+{4, 3214179041u, 1077265039u, 3214179041u, 0, FMOD_TOLERANCE, 0},
+{5, 3214095155u, 1077306982u, 3214095155u, 0, FMOD_TOLERANCE, 0},
+{6, 3214011269u, 1077348925u, 3214011269u, 0, FMOD_TOLERANCE, 0},
+{7, 3213927383u, 1077390868u, 3213927383u, 0, FMOD_TOLERANCE, 0},
+{8, 3213843497u, 1077432812u, 3213843497u, 0, FMOD_TOLERANCE, 0},
+{9, 3213759611u, 1077474755u, 3213759611u, 0, FMOD_TOLERANCE, 0},
+{10, 3213675725u, 1077516698u, 3213675725u, 0, FMOD_TOLERANCE, 0},
+{11, 3213591839u, 1077558641u, 3213591839u, 0, FMOD_TOLERANCE, 0},
+{12, 3213507953u, 1077600584u, 3213507953u, 0, FMOD_TOLERANCE, 0},
+{13, 3213424067u, 1077642527u, 3213424067u, 0, FMOD_TOLERANCE, 0},
+{14, 3213340180u, 1077684470u, 3213340180u, 0, FMOD_TOLERANCE, 0},
+{15, 3213256294u, 1077726413u, 3213256294u, 0, FMOD_TOLERANCE, 0},
+{16, 3213172408u, 1077768356u, 3213172408u, 0, FMOD_TOLERANCE, 0},
+{17, 3213088522u, 1077810299u, 3213088522u, 0, FMOD_TOLERANCE, 0},
+{18, 3213004636u, 1077852242u, 3213004636u, 0, FMOD_TOLERANCE, 0},
+{19, 3212920750u, 1077894185u, 3212920750u, 0, FMOD_TOLERANCE, 0},
+{20, 3212836864u, 1077936128u, 3212836864u, 0, FMOD_TOLERANCE, 0},
+{21, 3212669092u, 1077978071u, 3212669092u, 0, FMOD_TOLERANCE, 0},
+{22, 3212501320u, 1078020014u, 3212501320u, 0, FMOD_TOLERANCE, 0},
+{23, 3212333548u, 1078061957u, 3212333548u, 0, FMOD_TOLERANCE, 0},
+{24, 3212165775u, 1078103900u, 3212165775u, 0, FMOD_TOLERANCE, 0},
+{25, 3211998003u, 1078145843u, 3211998003u, 0, FMOD_TOLERANCE, 0},
+{26, 3211830231u, 1078187786u, 3211830231u, 0, FMOD_TOLERANCE, 0},
+{27, 3211662459u, 1078229729u, 3211662459u, 0, FMOD_TOLERANCE, 0},
+{28, 3211494687u, 1078271672u, 3211494687u, 0, FMOD_TOLERANCE, 0},
+{29, 3211326915u, 1078313615u, 3211326915u, 0, FMOD_TOLERANCE, 0},
+{30, 3211159142u, 1078355558u, 3211159142u, 0, FMOD_TOLERANCE, 0},
+{31, 3210991370u, 1078397501u, 3210991370u, 0, FMOD_TOLERANCE, 0},
+{32, 3210823598u, 1078439444u, 3210823598u, 0, FMOD_TOLERANCE, 0},
+{33, 3210655826u, 1078481388u, 3210655826u, 0, FMOD_TOLERANCE, 0},
+{34, 3210488054u, 1078523331u, 3210488054u, 0, FMOD_TOLERANCE, 0},
+{35, 3210320282u, 1078565274u, 3210320282u, 0, FMOD_TOLERANCE, 0},
+{36, 3210152509u, 1078607217u, 3210152509u, 0, FMOD_TOLERANCE, 0},
+{37, 3209984737u, 1078649160u, 3209984737u, 0, FMOD_TOLERANCE, 0},
+{38, 3209816965u, 1078691103u, 3209816965u, 0, FMOD_TOLERANCE, 0},
+{39, 3209649193u, 1078733046u, 3209649193u, 0, FMOD_TOLERANCE, 0},
+{40, 3209481421u, 1078774989u, 3209481421u, 0, FMOD_TOLERANCE, 0},
+{41, 3209313649u, 1078816932u, 3209313649u, 0, FMOD_TOLERANCE, 0},
+{42, 3209145876u, 1078858875u, 3209145876u, 0, FMOD_TOLERANCE, 0},
+{43, 3208978104u, 1078900818u, 3208978104u, 0, FMOD_TOLERANCE, 0},
+{44, 3208810332u, 1078942761u, 3208810332u, 0, FMOD_TOLERANCE, 0},
+{45, 3208642560u, 1078984704u, 3208642560u, 0, FMOD_TOLERANCE, 0},
+{46, 3208474788u, 1079026647u, 3208474788u, 0, FMOD_TOLERANCE, 0},
+{47, 3208307016u, 1079068590u, 3208307016u, 0, FMOD_TOLERANCE, 0},
+{48, 3208139244u, 1079110533u, 3208139244u, 0, FMOD_TOLERANCE, 0},
+{49, 3207971471u, 1079152476u, 3207971471u, 0, FMOD_TOLERANCE, 0},
+{50, 3207803699u, 1079194419u, 3207803699u, 0, FMOD_TOLERANCE, 0},
+{51, 3207635927u, 1079236362u, 3207635927u, 0, FMOD_TOLERANCE, 0},
+{52, 3207468155u, 1079278305u, 3207468155u, 0, FMOD_TOLERANCE, 0},
+{53, 3207300383u, 1079320248u, 3207300383u, 0, FMOD_TOLERANCE, 0},
+{54, 3207132611u, 1079362191u, 3207132611u, 0, FMOD_TOLERANCE, 0},
+{55, 3206964838u, 1079404134u, 3206964838u, 0, FMOD_TOLERANCE, 0},
+{56, 3206797066u, 1079446077u, 3206797066u, 0, FMOD_TOLERANCE, 0},
+{57, 3206629294u, 1079488020u, 3206629294u, 0, FMOD_TOLERANCE, 0},
+{58, 3206461522u, 1079529964u, 3206461522u, 0, FMOD_TOLERANCE, 0},
+{59, 3206293750u, 1079571907u, 3206293750u, 0, FMOD_TOLERANCE, 0},
+{60, 3206125978u, 1079613850u, 3206125978u, 0, FMOD_TOLERANCE, 0},
+{61, 3205958205u, 1079655793u, 3205958205u, 0, FMOD_TOLERANCE, 0},
+{62, 3205790433u, 1079697736u, 3205790433u, 0, FMOD_TOLERANCE, 0},
+{63, 3205622661u, 1079739679u, 3205622661u, 0, FMOD_TOLERANCE, 0},
+{64, 3205454889u, 1079781622u, 3205454889u, 0, FMOD_TOLERANCE, 0},
+{65, 3205287117u, 1079823565u, 3205287117u, 0, FMOD_TOLERANCE, 0},
+{66, 3205119345u, 1079865508u, 3205119345u, 0, FMOD_TOLERANCE, 0},
+{67, 3204951572u, 1079907451u, 3204951572u, 0, FMOD_TOLERANCE, 0},
+{68, 3204783800u, 1079949394u, 3204783800u, 0, FMOD_TOLERANCE, 0},
+{69, 3204616028u, 1079991337u, 3204616028u, 0, FMOD_TOLERANCE, 0},
+{70, 3204448256u, 1080033280u, 3204448256u, 0, FMOD_TOLERANCE, 0},
+{71, 3204112712u, 1080075223u, 3204112712u, 0, FMOD_TOLERANCE, 0},
+{72, 3203777167u, 1080117166u, 3203777167u, 0, FMOD_TOLERANCE, 0},
+{73, 3203441623u, 1080159109u, 3203441623u, 0, FMOD_TOLERANCE, 0},
+{74, 3203106079u, 1080201052u, 3203106079u, 0, FMOD_TOLERANCE, 0},
+{75, 3202770534u, 1080242995u, 3202770534u, 0, FMOD_TOLERANCE, 0},
+{76, 3202434990u, 1080284938u, 3202434990u, 0, FMOD_TOLERANCE, 0},
+{77, 3202099446u, 1080326881u, 3202099446u, 0, FMOD_TOLERANCE, 0},
+{78, 3201763901u, 1080368824u, 3201763901u, 0, FMOD_TOLERANCE, 0},
+{79, 3201428357u, 1080410767u, 3201428357u, 0, FMOD_TOLERANCE, 0},
+{80, 3201092813u, 1080452710u, 3201092813u, 0, FMOD_TOLERANCE, 0},
+{81, 3200757268u, 1080494653u, 3200757268u, 0, FMOD_TOLERANCE, 0},
+{82, 3200421724u, 1080536596u, 3200421724u, 0, FMOD_TOLERANCE, 0},
+{83, 3200086180u, 1080578540u, 3200086180u, 0, FMOD_TOLERANCE, 0},
+{84, 3199750636u, 1080620483u, 3199750636u, 0, FMOD_TOLERANCE, 0},
+{85, 3199415091u, 1080662426u, 3199415091u, 0, FMOD_TOLERANCE, 0},
+{86, 3199079547u, 1080704369u, 3199079547u, 0, FMOD_TOLERANCE, 0},
+{87, 3198744003u, 1080746312u, 3198744003u, 0, FMOD_TOLERANCE, 0},
+{88, 3198408458u, 1080788255u, 3198408458u, 0, FMOD_TOLERANCE, 0},
+{89, 3198072914u, 1080830198u, 3198072914u, 0, FMOD_TOLERANCE, 0},
+{90, 3197737370u, 1080872141u, 3197737370u, 0, FMOD_TOLERANCE, 0},
+{91, 3197401825u, 1080914084u, 3197401825u, 0, FMOD_TOLERANCE, 0},
+{92, 3197066281u, 1080956027u, 3197066281u, 0, FMOD_TOLERANCE, 0},
+{93, 3196730737u, 1080997970u, 3196730737u, 0, FMOD_TOLERANCE, 0},
+{94, 3196395192u, 1081039913u, 3196395192u, 0, FMOD_TOLERANCE, 0},
+{95, 3196059648u, 1081081856u, 3196059648u, 0, FMOD_TOLERANCE, 0},
+{96, 3195388559u, 1081123799u, 3195388559u, 0, FMOD_TOLERANCE, 0},
+{97, 3194717471u, 1081165742u, 3194717471u, 0, FMOD_TOLERANCE, 0},
+{98, 3194046382u, 1081207685u, 3194046382u, 0, FMOD_TOLERANCE, 0},
+{99, 3193375293u, 1081249628u, 3193375293u, 0, FMOD_TOLERANCE, 0},
+{100, 3192704205u, 1081291571u, 3192704205u, 0, FMOD_TOLERANCE, 0},
+{101, 3192033116u, 1081333514u, 3192033116u, 0, FMOD_TOLERANCE, 0},
+{102, 3191362028u, 1081375457u, 3191362028u, 0, FMOD_TOLERANCE, 0},
+{103, 3190690939u, 1081417400u, 3190690939u, 0, FMOD_TOLERANCE, 0},
+{104, 3190019850u, 1081459343u, 3190019850u, 0, FMOD_TOLERANCE, 0},
+{105, 3189348762u, 1081501286u, 3189348762u, 0, FMOD_TOLERANCE, 0},
+{106, 3188677673u, 1081543229u, 3188677673u, 0, FMOD_TOLERANCE, 0},
+{107, 3188006584u, 1081585172u, 3188006584u, 0, FMOD_TOLERANCE, 0},
+{108, 3186999951u, 1081627116u, 3186999951u, 0, FMOD_TOLERANCE, 0},
+{109, 3185657774u, 1081669059u, 3185657774u, 0, FMOD_TOLERANCE, 0},
+{110, 3184315597u, 1081711002u, 3184315597u, 0, FMOD_TOLERANCE, 0},
+{111, 3182973420u, 1081752945u, 3182973420u, 0, FMOD_TOLERANCE, 0},
+{112, 3181631242u, 1081794888u, 3181631242u, 0, FMOD_TOLERANCE, 0},
+{113, 3180289065u, 1081836831u, 3180289065u, 0, FMOD_TOLERANCE, 0},
+{114, 3178611343u, 1081878774u, 3178611343u, 0, FMOD_TOLERANCE, 0},
+{115, 3175926989u, 1081920717u, 3175926989u, 0, FMOD_TOLERANCE, 0},
+{116, 3173242634u, 1081962660u, 3173242634u, 0, FMOD_TOLERANCE, 0},
+{117, 3170222735u, 1082004603u, 3170222735u, 0, FMOD_TOLERANCE, 0},
+{118, 3164854026u, 1082046546u, 3164854026u, 0, FMOD_TOLERANCE, 0},
+{119, 3156465418u, 1082088489u, 3156465418u, 0, FMOD_TOLERANCE, 0},
+{120, 1008981770u, 1082151404u, 1008981770u, 0, FMOD_TOLERANCE, 0},
+{121, 1017370378u, 1082172375u, 1017370378u, 0, FMOD_TOLERANCE, 0},
+{122, 1022739087u, 1082193347u, 1022739087u, 0, FMOD_TOLERANCE, 0},
+{123, 1025758986u, 1082214318u, 1025758986u, 0, FMOD_TOLERANCE, 0},
+{124, 1028443341u, 1082235290u, 1028443341u, 0, FMOD_TOLERANCE, 0},
+{125, 1031127695u, 1082256261u, 1031127695u, 0, FMOD_TOLERANCE, 0},
+{126, 1032805417u, 1082277233u, 1032805417u, 0, FMOD_TOLERANCE, 0},
+{127, 1034147594u, 1082298204u, 1034147594u, 0, FMOD_TOLERANCE, 0},
+{128, 1035489772u, 1082319176u, 1035489772u, 0, FMOD_TOLERANCE, 0},
+{129, 1036831949u, 1082340147u, 1036831949u, 0, FMOD_TOLERANCE, 0},
+{130, 1038174126u, 1082361119u, 1038174126u, 0, FMOD_TOLERANCE, 0},
+{131, 1039516303u, 1082382090u, 1039516303u, 0, FMOD_TOLERANCE, 0},
+{132, 1040522936u, 1082403062u, 1040522936u, 0, FMOD_TOLERANCE, 0},
+{133, 1041194025u, 1082424033u, 1041194025u, 0, FMOD_TOLERANCE, 0},
+{134, 1041865114u, 1082445005u, 1041865114u, 0, FMOD_TOLERANCE, 0},
+{135, 1042536202u, 1082465976u, 1042536202u, 0, FMOD_TOLERANCE, 0},
+{136, 1043207291u, 1082486948u, 1043207291u, 0, FMOD_TOLERANCE, 0},
+{137, 1043878380u, 1082507919u, 1043878380u, 0, FMOD_TOLERANCE, 0},
+{138, 1044549468u, 1082528891u, 1044549468u, 0, FMOD_TOLERANCE, 0},
+{139, 1045220557u, 1082549862u, 1045220557u, 0, FMOD_TOLERANCE, 0},
+{140, 1045891645u, 1082570834u, 1045891645u, 0, FMOD_TOLERANCE, 0},
+{141, 1046562734u, 1082591805u, 1046562734u, 0, FMOD_TOLERANCE, 0},
+{142, 1047233823u, 1082612777u, 1047233823u, 0, FMOD_TOLERANCE, 0},
+{143, 1047904911u, 1082633748u, 1047904911u, 0, FMOD_TOLERANCE, 0},
+{144, 1048576000u, 1082654720u, 1048576000u, 0, FMOD_TOLERANCE, 0},
+{145, 1048911544u, 1082675692u, 1048911544u, 0, FMOD_TOLERANCE, 0},
+{146, 1049247089u, 1082696663u, 1049247089u, 0, FMOD_TOLERANCE, 0},
+{147, 1049582633u, 1082717635u, 1049582633u, 0, FMOD_TOLERANCE, 0},
+{148, 1049918177u, 1082738606u, 1049918177u, 0, FMOD_TOLERANCE, 0},
+{149, 1050253722u, 1082759578u, 1050253722u, 0, FMOD_TOLERANCE, 0},
+{150, 1050589266u, 1082780549u, 1050589266u, 0, FMOD_TOLERANCE, 0},
+{151, 1050924810u, 1082801521u, 1050924810u, 0, FMOD_TOLERANCE, 0},
+{152, 1051260355u, 1082822492u, 1051260355u, 0, FMOD_TOLERANCE, 0},
+{153, 1051595899u, 1082843464u, 1051595899u, 0, FMOD_TOLERANCE, 0},
+{154, 1051931443u, 1082864435u, 1051931443u, 0, FMOD_TOLERANCE, 0},
+{155, 1052266988u, 1082885407u, 1052266988u, 0, FMOD_TOLERANCE, 0},
+{156, 1052602532u, 1082906378u, 1052602532u, 0, FMOD_TOLERANCE, 0},
+{157, 1052938076u, 1082927350u, 1052938076u, 0, FMOD_TOLERANCE, 0},
+{158, 1053273620u, 1082948321u, 1053273620u, 0, FMOD_TOLERANCE, 0},
+{159, 1053609165u, 1082969293u, 1053609165u, 0, FMOD_TOLERANCE, 0},
+{160, 1053944709u, 1082990264u, 1053944709u, 0, FMOD_TOLERANCE, 0},
+{161, 1054280253u, 1083011236u, 1054280253u, 0, FMOD_TOLERANCE, 0},
+{162, 1054615798u, 1083032207u, 1054615798u, 0, FMOD_TOLERANCE, 0},
+{163, 1054951342u, 1083053179u, 1054951342u, 0, FMOD_TOLERANCE, 0},
+{164, 1055286886u, 1083074150u, 1055286886u, 0, FMOD_TOLERANCE, 0},
+{165, 1055622431u, 1083095122u, 1055622431u, 0, FMOD_TOLERANCE, 0},
+{166, 1055957975u, 1083116093u, 1055957975u, 0, FMOD_TOLERANCE, 0},
+{167, 1056293519u, 1083137065u, 1056293519u, 0, FMOD_TOLERANCE, 0},
+{168, 1056629064u, 1083158036u, 1056629064u, 0, FMOD_TOLERANCE, 0},
+{169, 1056964608u, 1083179008u, 1056964608u, 0, FMOD_TOLERANCE, 0},
+{170, 1057132380u, 1083199980u, 1057132380u, 0, FMOD_TOLERANCE, 0},
+{171, 1057300152u, 1083220951u, 1057300152u, 0, FMOD_TOLERANCE, 0},
+{172, 1057467924u, 1083241923u, 1057467924u, 0, FMOD_TOLERANCE, 0},
+{173, 1057635697u, 1083262894u, 1057635697u, 0, FMOD_TOLERANCE, 0},
+{174, 1057803469u, 1083283866u, 1057803469u, 0, FMOD_TOLERANCE, 0},
+{175, 1057971241u, 1083304837u, 1057971241u, 0, FMOD_TOLERANCE, 0},
+{176, 1058139013u, 1083325809u, 1058139013u, 0, FMOD_TOLERANCE, 0},
+{177, 1058306785u, 1083346780u, 1058306785u, 0, FMOD_TOLERANCE, 0},
+{178, 1058474557u, 1083367752u, 1058474557u, 0, FMOD_TOLERANCE, 0},
+{179, 1058642330u, 1083388723u, 1058642330u, 0, FMOD_TOLERANCE, 0},
+{180, 1058810102u, 1083409695u, 1058810102u, 0, FMOD_TOLERANCE, 0},
+{181, 1058977874u, 1083430666u, 1058977874u, 0, FMOD_TOLERANCE, 0},
+{182, 1059145646u, 1083451638u, 1059145646u, 0, FMOD_TOLERANCE, 0},
+{183, 1059313418u, 1083472609u, 1059313418u, 0, FMOD_TOLERANCE, 0},
+{184, 1059481190u, 1083493581u, 1059481190u, 0, FMOD_TOLERANCE, 0},
+{185, 1059648963u, 1083514552u, 1059648963u, 0, FMOD_TOLERANCE, 0},
+{186, 1059816735u, 1083535524u, 1059816735u, 0, FMOD_TOLERANCE, 0},
+{187, 1059984507u, 1083556495u, 1059984507u, 0, FMOD_TOLERANCE, 0},
+{188, 1060152279u, 1083577467u, 1060152279u, 0, FMOD_TOLERANCE, 0},
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+{412, 1045232522u, 3234993273u, 1045232522u, 0, FMOD_TOLERANCE, 0},
+{413, 3228795133u, 3273940030u, 3228795133u, 0, FMOD_TOLERANCE, 0},
+{414, 3388153589u, 3426245389u, 3388153589u, 0, FMOD_TOLERANCE, 0},
+{415, 1133410485u, 3329658993u, 1133410485u, 0, FMOD_TOLERANCE, 0},
+{416, 3136790322u, 1088652637u, 3136790322u, 0, FMOD_TOLERANCE, 0},
+{417, 1001897182u, 3191875320u, 1001897182u, 0, FMOD_TOLERANCE, 0},
+{418, 3152777939u, 3245830463u, 3152777939u, 0, FMOD_TOLERANCE, 0},
+{419, 985903305u, 3333087577u, 985903305u, 0, FMOD_TOLERANCE, 0},
+{420, 3267868136u, 1208301947u, 3267868136u, 0, FMOD_TOLERANCE, 0},
+{421, 3319048157u, 1172271145u, 3319048157u, 0, FMOD_TOLERANCE, 0},
+{422, 3301461672u, 1233693827u, 3301461672u, 0, FMOD_TOLERANCE, 0},
+{423, 3130670309u, 3192399254u, 3130670309u, 0, FMOD_TOLERANCE, 0},
+{424, 1258369714u, 3462258576u, 1258369714u, 0, FMOD_TOLERANCE, 0},
+{425, 1216602683u, 3371396332u, 1216602683u, 0, FMOD_TOLERANCE, 0},
+{426, 3297265739u, 1214184410u, 3297265739u, 0, FMOD_TOLERANCE, 0},
+{427, 1071940738u, 3311731012u, 1071940738u, 0, FMOD_TOLERANCE, 0},
+{428, 3131219358u, 3471261157u, 3131219358u, 0, FMOD_TOLERANCE, 0},
+{429, 3222096285u, 1198013705u, 3222096285u, 0, FMOD_TOLERANCE, 0},
+{430, 3345532722u, 3383708463u, 3345532722u, 0, FMOD_TOLERANCE, 0},
+{431, 3418753236u, 3481843070u, 3418753236u, 0, FMOD_TOLERANCE, 0},
+{432, 1277417964u, 3487506626u, 1277417964u, 0, FMOD_TOLERANCE, 0},
+{433, 987577257u, 1152077087u, 987577257u, 0, FMOD_TOLERANCE, 0},
+{434, 3161606610u, 3190282989u, 3161606610u, 0, FMOD_TOLERANCE, 0},
+{435, 1043442869u, 3311393817u, 1043442869u, 0, FMOD_TOLERANCE, 0},
+{436, 3320923228u, 3464544249u, 3320923228u, 0, FMOD_TOLERANCE, 0},
+{437, 1337400405u, 3488844154u, 1337400405u, 0, FMOD_TOLERANCE, 0},
+{438, 3284411233u, 1173613526u, 3284411233u, 0, FMOD_TOLERANCE, 0},
+{439, 1215968622u, 3469884568u, 1215968622u, 0, FMOD_TOLERANCE, 0},
+{440, 1025404104u, 1066370251u, 1025404104u, 0, FMOD_TOLERANCE, 0},
+{441, 3138086437u, 3195983510u, 3138086437u, 0, FMOD_TOLERANCE, 0},
+{442, 3362748242u, 3369843597u, 3362748242u, 0, FMOD_TOLERANCE, 0},
+{443, 3327895594u, 1224511805u, 3327895594u, 0, FMOD_TOLERANCE, 0},
+{444, 1157186482u, 1288722647u, 1157186482u, 0, FMOD_TOLERANCE, 0},
+{445, 3477008113u, 1331845018u, 3477008113u, 0, FMOD_TOLERANCE, 0},
+{446, 3292127294u, 3409957764u, 3292127294u, 0, FMOD_TOLERANCE, 0},
+{447, 1123357102u, 3281307320u, 1123357102u, 0, FMOD_TOLERANCE, 0},
+{448, 1049949008u, 1130799489u, 1049949008u, 0, FMOD_TOLERANCE, 0},
+{449, 1108543194u, 3281299199u, 1108543194u, 0, FMOD_TOLERANCE, 0},
+{450, 3163283126u, 1328636961u, 3163283126u, 0, FMOD_TOLERANCE, 0},
+{451, 1160162706u, 1264067367u, 1160162706u, 0, FMOD_TOLERANCE, 0},
+{452, 972485427u, 1124312043u, 972485427u, 0, FMOD_TOLERANCE, 0},
+{453, 3222106584u, 1183748648u, 3222106584u, 0, FMOD_TOLERANCE, 0},
+{454, 3167730654u, 3195765940u, 3167730654u, 0, FMOD_TOLERANCE, 0},
+{455, 1098530298u, 3255870890u, 1098530298u, 0, FMOD_TOLERANCE, 0},
+{456, 3203377685u, 1306427476u, 3203377685u, 0, FMOD_TOLERANCE, 0},
+{457, 1096155623u, 1256423752u, 1096155623u, 0, FMOD_TOLERANCE, 0},
+{458, 3238729605u, 1298769842u, 3238729605u, 0, FMOD_TOLERANCE, 0},
+{459, 3154720153u, 3443720494u, 3154720153u, 0, FMOD_TOLERANCE, 0},
+{460, 3136364836u, 1018492227u, 3136364836u, 0, FMOD_TOLERANCE, 0},
+{461, 1011225926u, 1180485180u, 1011225926u, 0, FMOD_TOLERANCE, 0},
+{462, 3137758475u, 1039403054u, 3137758475u, 0, FMOD_TOLERANCE, 0},
+{463, 1040617590u, 1034835971u, 1027445202u, 0, FMOD_TOLERANCE, 0},
+{464, 1039827284u, 1072928888u, 1039827284u, 0, FMOD_TOLERANCE, 0},
+{465, 1021564080u, 1064468397u, 1021564080u, 0, FMOD_TOLERANCE, 0},
+{466, 3327516316u, 3405380971u, 3327516316u, 0, FMOD_TOLERANCE, 0},
+{467, 1040711112u, 3229444200u, 1040711112u, 0, FMOD_TOLERANCE, 0},
+{468, 1134528351u, 3365952513u, 1134528351u, 0, FMOD_TOLERANCE, 0},
+{469, 1066157309u, 3241712664u, 1066157309u, 0, FMOD_TOLERANCE, 0},
+{470, 3272661536u, 3461799138u, 3272661536u, 0, FMOD_TOLERANCE, 0},
+{471, 1170245333u, 1233406410u, 1170245333u, 0, FMOD_TOLERANCE, 0},
+{472, 1219052056u, 3369557946u, 1219052056u, 0, FMOD_TOLERANCE, 0},
+{473, 3190796331u, 1320011850u, 3190796331u, 0, FMOD_TOLERANCE, 0},
+{474, 3257224022u, 3361778245u, 3257224022u, 0, FMOD_TOLERANCE, 0},
+{475, 1086717248u, 3423795374u, 1086717248u, 0, FMOD_TOLERANCE, 0},
+{476, 1200927971u, 1317167489u, 1200927971u, 0, FMOD_TOLERANCE, 0},
+{477, 3326858092u, 3452602832u, 3326858092u, 0, FMOD_TOLERANCE, 0},
+{478, 3184801644u, 1137974313u, 3184801644u, 0, FMOD_TOLERANCE, 0},
+{479, 1015670780u, 1101217251u, 1015670780u, 0, FMOD_TOLERANCE, 0},
+{480, 1012543234u, 1116520440u, 1012543234u, 0, FMOD_TOLERANCE, 0},
+{481, 3316611992u, 3394732912u, 3316611992u, 0, FMOD_TOLERANCE, 0},
+{482, 1087942795u, 3316660295u, 1087942795u, 0, FMOD_TOLERANCE, 0},
+{483, 3295326432u, 1313396175u, 3295326432u, 0, FMOD_TOLERANCE, 0},
+{484, 1173247961u, 1191127979u, 1173247961u, 0, FMOD_TOLERANCE, 0},
+{485, 3248534678u, 1323683800u, 3248534678u, 0, FMOD_TOLERANCE, 0},
+{486, 3157626955u, 3483653298u, 3157626955u, 0, FMOD_TOLERANCE, 0},
+{487, 3182695954u, 3256861672u, 3182695954u, 0, FMOD_TOLERANCE, 0},
+{488, 1105291533u, 3482971524u, 1105291533u, 0, FMOD_TOLERANCE, 0},
+{489, 1016023520u, 3227712090u, 1016023520u, 0, FMOD_TOLERANCE, 0},
+{490, 3370691006u, 1295870514u, 3370691006u, 0, FMOD_TOLERANCE, 0},
+{491, 3335212901u, 3486414589u, 3335212901u, 0, FMOD_TOLERANCE, 0},
+{492, 3266691185u, 1160074593u, 3266691185u, 0, FMOD_TOLERANCE, 0},
+{493, 3179003144u, 1108615803u, 3179003144u, 0, FMOD_TOLERANCE, 0},
+{494, 973664327u, 1319516167u, 973664327u, 0, FMOD_TOLERANCE, 0},
+{495, 979878744u, 1232482646u, 979878744u, 0, FMOD_TOLERANCE, 0},
+{496, 1002542205u, 3152136093u, 1002542205u, 0, FMOD_TOLERANCE, 0},
+{497, 989655126u, 1308376568u, 989655126u, 0, FMOD_TOLERANCE, 0},
+{498, 1002715618u, 1191006977u, 1002715618u, 0, FMOD_TOLERANCE, 0},
+{499, 1000863905u, 1196831314u, 1000863905u, 0, FMOD_TOLERANCE, 0},
+{500, 3283471961u, 1260093226u, 3283471961u, 0, FMOD_TOLERANCE, 0},
+{501, 3311210827u, 1192192264u, 3311210827u, 0, FMOD_TOLERANCE, 0},
+{502, 1288901567u, 1296370667u, 1288901567u, 0, FMOD_TOLERANCE, 0},
+{503, 1062512367u, 3229559531u, 1062512367u, 0, FMOD_TOLERANCE, 0},
+{504, 1034561811u, 1054043114u, 1034561811u, 0, FMOD_TOLERANCE, 0},
+{505, 1042014529u, 1146708584u, 1042014529u, 0, FMOD_TOLERANCE, 0},
+{506, 3196144817u, 1056118717u, 3196144817u, 0, FMOD_TOLERANCE, 0},
+{507, 3375507013u, 1306310823u, 3375507013u, 0, FMOD_TOLERANCE, 0},
+{508, 1055319316u, 3261813492u, 1055319316u, 0, FMOD_TOLERANCE, 0},
+{509, 1123114742u, 1229815537u, 1123114742u, 0, FMOD_TOLERANCE, 0},
+{510, 1258114435u, 1291336083u, 1258114435u, 0, FMOD_TOLERANCE, 0},
+{511, 3223384012u, 1130486973u, 3223384012u, 0, FMOD_TOLERANCE, 0},
+{512, 1019964626u, 1235133609u, 1019964626u, 0, FMOD_TOLERANCE, 0},
+{513, 3445262427u, 3465211174u, 3445262427u, 0, FMOD_TOLERANCE, 0},
+{514, 1125653081u, 1207799746u, 1125653081u, 0, FMOD_TOLERANCE, 0},
+{515, 996404791u, 3353251979u, 996404791u, 0, FMOD_TOLERANCE, 0},
+{516, 996786317u, 3179221951u, 996786317u, 0, FMOD_TOLERANCE, 0},
+{517, 1188167943u, 1200744896u, 1188167943u, 0, FMOD_TOLERANCE, 0},
+{518, 1102061604u, 3424449935u, 1102061604u, 0, FMOD_TOLERANCE, 0},
+{519, 3116209179u, 3303588342u, 3116209179u, 0, FMOD_TOLERANCE, 0},
+{520, 3207056527u, 3384206601u, 3207056527u, 0, FMOD_TOLERANCE, 0},
+{521, 1284174954u, 3436881197u, 1284174954u, 0, FMOD_TOLERANCE, 0},
+{522, 3156081645u, 3308839704u, 3156081645u, 0, FMOD_TOLERANCE, 0},
+{523, 1102631663u, 3396951425u, 1102631663u, 0, FMOD_TOLERANCE, 0},
+{524, 968803479u, 992989712u, 968803479u, 0, FMOD_TOLERANCE, 0},
+{525, 1003649752u, 1218792138u, 1003649752u, 0, FMOD_TOLERANCE, 0},
+{526, 1078478376u, 1326246424u, 1078478376u, 0, FMOD_TOLERANCE, 0},
+{527, 3158855023u, 3151283866u, 3149648964u, 0, FMOD_TOLERANCE, 0},
+{528, 1165177679u, 3276237026u, 1120720980u, 0, FMOD_TOLERANCE, 0},
+{529, 1208345407u, 1254181270u, 1208345407u, 0, FMOD_TOLERANCE, 0},
+{530, 1248478509u, 1287895126u, 1248478509u, 0, FMOD_TOLERANCE, 0},
+{531, 1153863988u, 3430539165u, 1153863988u, 0, FMOD_TOLERANCE, 0},
+{532, 1064922416u, 1320485628u, 1064922416u, 0, FMOD_TOLERANCE, 0},
+{533, 3230403187u, 1322841992u, 3230403187u, 0, FMOD_TOLERANCE, 0},
+{534, 1072458508u, 3372833993u, 1072458508u, 0, FMOD_TOLERANCE, 0},
+{535, 3319723279u, 3414482416u, 3319723279u, 0, FMOD_TOLERANCE, 0},
+{536, 3237813668u, 3441016803u, 3237813668u, 0, FMOD_TOLERANCE, 0},
+{537, 975349337u, 1311932596u, 975349337u, 0, FMOD_TOLERANCE, 0},
+{538, 981908840u, 3314038398u, 981908840u, 0, FMOD_TOLERANCE, 0},
+{539, 1315857601u, 3487600045u, 1315857601u, 0, FMOD_TOLERANCE, 0},
+{540, 1029557624u, 3302959071u, 1029557624u, 0, FMOD_TOLERANCE, 0},
+{541, 1028355074u, 3442294040u, 1028355074u, 0, FMOD_TOLERANCE, 0},
+{542, 3119299090u, 1187096397u, 3119299090u, 0, FMOD_TOLERANCE, 0},
+{543, 3192315328u, 3289489214u, 3192315328u, 0, FMOD_TOLERANCE, 0},
+{544, 3392827417u, 1277961150u, 3392827417u, 0, FMOD_TOLERANCE, 0},
+{545, 1161241793u, 1328003707u, 1161241793u, 0, FMOD_TOLERANCE, 0},
+{546, 1171318485u, 3374409104u, 1171318485u, 0, FMOD_TOLERANCE, 0},
+{547, 1127109339u, 3368125489u, 1127109339u, 0, FMOD_TOLERANCE, 0},
+{548, 1155775526u, 1255814444u, 1155775526u, 0, FMOD_TOLERANCE, 0},
+{549, 1234491880u, 3408568717u, 1234491880u, 0, FMOD_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_FMOD_H multiple inclusion protection
+
+// EOF fmod.h
diff --git a/packages/language/c/libm/current/tests/vectors/frexpf.c b/packages/language/c/libm/current/tests/vectors/frexpf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/frexpf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      frexpf.c
+//
+//      Test of frexpf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/frexpf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(frexpf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &frexpf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_INT_P, CYG_LIBM_TEST_VEC_FLOAT,
+                     &frexpf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("frexpf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("frexpf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library frexpf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "frexpf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF frexpf.c
diff --git a/packages/language/c/libm/current/tests/vectors/frexpf.h b/packages/language/c/libm/current/tests/vectors/frexpf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/frexpf.h
@@ -0,0 +1,528 @@
+#ifndef CYGONCE_LIBM_FREXPF_H
+#define CYGONCE_LIBM_FREXPF_H
+//===========================================================================
+//
+//      frexpf.h
+//
+//      Test vectors for testing of frexpf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  ilijak
+// Date:        2013-06-26
+// Purpose:
+// Description:
+// Usage:       #include "vectors/frexpf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define FREXPF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t frexpf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+{0, 3519987949u, 37u, 3209609453u, 0, FREXPF_TOLERANCE, 0 }, // -1.1100E+11=F( -0.8076, +37)
+{1, 3518632969u, 37u, 3208254473u, 0, FREXPF_TOLERANCE, 0 }, // -9.9900E+10=F( -0.7269, +37)
+{2, 3517277989u, 37u, 3206899493u, 0, FREXPF_TOLERANCE, 0 }, // -8.8800E+10=F( -0.6461, +37)
+{3, 3515923009u, 37u, 3205544513u, 0, FREXPF_TOLERANCE, 0 }, // -7.7700E+10=F( -0.5653, +37)
+{4, 3514309305u, 36u, 3212319417u, 0, FREXPF_TOLERANCE, 0 }, // -6.6600E+10=F( -0.9692, +36)
+{5, 3511599344u, 36u, 3209609456u, 0, FREXPF_TOLERANCE, 0 }, // -5.5500E+10=F( -0.8076, +36)
+{6, 3508889383u, 36u, 3206899495u, 0, FREXPF_TOLERANCE, 0 }, // -4.4400E+10=F( -0.6461, +36)
+{7, 3505920700u, 35u, 3212319420u, 0, FREXPF_TOLERANCE, 0 }, // -3.3300E+10=F( -0.9692, +35)
+{8, 3500500778u, 35u, 3206899498u, 0, FREXPF_TOLERANCE, 0 }, // -2.2200E+10=F( -0.6461, +35)
+{9, 3492112176u, 34u, 3206899504u, 0, FREXPF_TOLERANCE, 0 }, // -1.1100E+10=F( -0.6461, +34)
+{10, 3326345216u, 14u, 3208904704u, 0, FREXPF_TOLERANCE, 0 }, // -1.2544E+04=F( -0.7656, +14)
+{11, 3297435648u, 11u, 3205160960u, 0, FREXPF_TOLERANCE, 0 }, // -1.1110E+03=F( -0.5425, +11)
+{12, 3296329728u, 10u, 3212443648u, 0, FREXPF_TOLERANCE, 0 }, // -1.0000E+03=F( -0.9766, +10)
+{13, 3294511104u, 10u, 3210625024u, 0, FREXPF_TOLERANCE, 0 }, // -8.8900E+02=F( -0.8682, +10)
+{14, 3292692480u, 10u, 3208806400u, 0, FREXPF_TOLERANCE, 0 }, // -7.7800E+02=F( -0.7598, +10)
+{15, 3290873856u, 10u, 3206987776u, 0, FREXPF_TOLERANCE, 0 }, // -6.6700E+02=F( -0.6514, +10)
+{16, 3289055232u, 10u, 3205169152u, 0, FREXPF_TOLERANCE, 0 }, // -5.5600E+02=F(  -0.543, +10)
+{17, 3286138880u, 9u, 3210641408u, 0, FREXPF_TOLERANCE, 0 }, // -4.4500E+02=F( -0.8691, +9)
+{18, 3282501632u, 9u, 3207004160u, 0, FREXPF_TOLERANCE, 0 }, // -3.3400E+02=F( -0.6523, +9)
+{19, 3277783040u, 8u, 3210674176u, 0, FREXPF_TOLERANCE, 0 }, // -2.2300E+02=F( -0.8711, +8)
+{20, 3269459968u, 7u, 3210739712u, 0, FREXPF_TOLERANCE, 0 }, // -1.1200E+02=F(  -0.875, +7)
+{21, 3269328896u, 7u, 3210608640u, 0, FREXPF_TOLERANCE, 0 }, // -1.1100E+02=F( -0.8672, +7)
+{22, 3269184717u, 7u, 3210464461u, 0, FREXPF_TOLERANCE, 0 }, // -1.0990E+02=F( -0.8586, +7)
+{23, 3269040538u, 7u, 3210320282u, 0, FREXPF_TOLERANCE, 0 }, // -1.0880E+02=F(   -0.85, +7)
+{24, 3268896359u, 7u, 3210176103u, 0, FREXPF_TOLERANCE, 0 }, // -1.0770E+02=F( -0.8414, +7)
+{25, 3268752180u, 7u, 3210031924u, 0, FREXPF_TOLERANCE, 0 }, // -1.0660E+02=F( -0.8328, +7)
+{26, 3268608001u, 7u, 3209887745u, 0, FREXPF_TOLERANCE, 0 }, // -1.0550E+02=F( -0.8242, +7)
+{27, 3268463822u, 7u, 3209743566u, 0, FREXPF_TOLERANCE, 0 }, // -1.0440E+02=F( -0.8156, +7)
+{28, 3268319643u, 7u, 3209599387u, 0, FREXPF_TOLERANCE, 0 }, // -1.0330E+02=F(  -0.807, +7)
+{29, 3268175464u, 7u, 3209455208u, 0, FREXPF_TOLERANCE, 0 }, // -1.0220E+02=F( -0.7984, +7)
+{30, 3268031285u, 7u, 3209311029u, 0, FREXPF_TOLERANCE, 0 }, // -1.0110E+02=F( -0.7898, +7)
+{31, 3267887106u, 7u, 3209166850u, 0, FREXPF_TOLERANCE, 0 }, // -1.0000E+02=F( -0.7813, +7)
+{32, 3267742927u, 7u, 3209022671u, 0, FREXPF_TOLERANCE, 0 }, // -9.8900E+01=F( -0.7727, +7)
+{33, 3267598748u, 7u, 3208878492u, 0, FREXPF_TOLERANCE, 0 }, // -9.7800E+01=F( -0.7641, +7)
+{34, 3267454569u, 7u, 3208734313u, 0, FREXPF_TOLERANCE, 0 }, // -9.6700E+01=F( -0.7555, +7)
+{35, 3267310390u, 7u, 3208590134u, 0, FREXPF_TOLERANCE, 0 }, // -9.5600E+01=F( -0.7469, +7)
+{36, 3267166211u, 7u, 3208445955u, 0, FREXPF_TOLERANCE, 0 }, // -9.4500E+01=F( -0.7383, +7)
+{37, 3267022032u, 7u, 3208301776u, 0, FREXPF_TOLERANCE, 0 }, // -9.3400E+01=F( -0.7297, +7)
+{38, 3266877853u, 7u, 3208157597u, 0, FREXPF_TOLERANCE, 0 }, // -9.2300E+01=F( -0.7211, +7)
+{39, 3266733674u, 7u, 3208013418u, 0, FREXPF_TOLERANCE, 0 }, // -9.1200E+01=F( -0.7125, +7)
+{40, 3266589495u, 7u, 3207869239u, 0, FREXPF_TOLERANCE, 0 }, // -9.0100E+01=F( -0.7039, +7)
+{41, 3266445316u, 7u, 3207725060u, 0, FREXPF_TOLERANCE, 0 }, // -8.9000E+01=F( -0.6953, +7)
+{42, 3266301137u, 7u, 3207580881u, 0, FREXPF_TOLERANCE, 0 }, // -8.7900E+01=F( -0.6867, +7)
+{43, 3266156958u, 7u, 3207436702u, 0, FREXPF_TOLERANCE, 0 }, // -8.6800E+01=F( -0.6781, +7)
+{44, 3266012779u, 7u, 3207292523u, 0, FREXPF_TOLERANCE, 0 }, // -8.5700E+01=F( -0.6695, +7)
+{45, 3265868600u, 7u, 3207148344u, 0, FREXPF_TOLERANCE, 0 }, // -8.4600E+01=F( -0.6609, +7)
+{46, 3265724421u, 7u, 3207004165u, 0, FREXPF_TOLERANCE, 0 }, // -8.3500E+01=F( -0.6523, +7)
+{47, 3265580242u, 7u, 3206859986u, 0, FREXPF_TOLERANCE, 0 }, // -8.2400E+01=F( -0.6438, +7)
+{48, 3265436063u, 7u, 3206715807u, 0, FREXPF_TOLERANCE, 0 }, // -8.1300E+01=F( -0.6352, +7)
+{49, 3265291884u, 7u, 3206571628u, 0, FREXPF_TOLERANCE, 0 }, // -8.0200E+01=F( -0.6266, +7)
+{50, 3265147705u, 7u, 3206427449u, 0, FREXPF_TOLERANCE, 0 }, // -7.9100E+01=F(  -0.618, +7)
+{51, 3265003526u, 7u, 3206283270u, 0, FREXPF_TOLERANCE, 0 }, // -7.8000E+01=F( -0.6094, +7)
+{52, 3264859347u, 7u, 3206139091u, 0, FREXPF_TOLERANCE, 0 }, // -7.6900E+01=F( -0.6008, +7)
+{53, 3264715168u, 7u, 3205994912u, 0, FREXPF_TOLERANCE, 0 }, // -7.5800E+01=F( -0.5922, +7)
+{54, 3264570989u, 7u, 3205850733u, 0, FREXPF_TOLERANCE, 0 }, // -7.4700E+01=F( -0.5836, +7)
+{55, 3264426810u, 7u, 3205706554u, 0, FREXPF_TOLERANCE, 0 }, // -7.3600E+01=F(  -0.575, +7)
+{56, 3264282631u, 7u, 3205562375u, 0, FREXPF_TOLERANCE, 0 }, // -7.2500E+01=F( -0.5664, +7)
+{57, 3264138452u, 7u, 3205418196u, 0, FREXPF_TOLERANCE, 0 }, // -7.1400E+01=F( -0.5578, +7)
+{58, 3263994273u, 7u, 3205274017u, 0, FREXPF_TOLERANCE, 0 }, // -7.0300E+01=F( -0.5492, +7)
+{59, 3263850094u, 7u, 3205129838u, 0, FREXPF_TOLERANCE, 0 }, // -6.9200E+01=F( -0.5406, +7)
+{60, 3263705915u, 7u, 3204985659u, 0, FREXPF_TOLERANCE, 0 }, // -6.8100E+01=F(  -0.532, +7)
+{61, 3263561736u, 7u, 3204841480u, 0, FREXPF_TOLERANCE, 0 }, // -6.7000E+01=F( -0.5234, +7)
+{62, 3263417557u, 7u, 3204697301u, 0, FREXPF_TOLERANCE, 0 }, // -6.5900E+01=F( -0.5148, +7)
+{63, 3263273378u, 7u, 3204553122u, 0, FREXPF_TOLERANCE, 0 }, // -6.4800E+01=F( -0.5063, +7)
+{64, 3263089886u, 6u, 3212758238u, 0, FREXPF_TOLERANCE, 0 }, // -6.3700E+01=F( -0.9953, +6)
+{65, 3262801528u, 6u, 3212469880u, 0, FREXPF_TOLERANCE, 0 }, // -6.2600E+01=F( -0.9781, +6)
+{66, 3262513170u, 6u, 3212181522u, 0, FREXPF_TOLERANCE, 0 }, // -6.1500E+01=F( -0.9609, +6)
+{67, 3262224812u, 6u, 3211893164u, 0, FREXPF_TOLERANCE, 0 }, // -6.0400E+01=F( -0.9438, +6)
+{68, 3261936454u, 6u, 3211604806u, 0, FREXPF_TOLERANCE, 0 }, // -5.9300E+01=F( -0.9266, +6)
+{69, 3261648096u, 6u, 3211316448u, 0, FREXPF_TOLERANCE, 0 }, // -5.8200E+01=F( -0.9094, +6)
+{70, 3261359738u, 6u, 3211028090u, 0, FREXPF_TOLERANCE, 0 }, // -5.7100E+01=F( -0.8922, +6)
+{71, 3261071380u, 6u, 3210739732u, 0, FREXPF_TOLERANCE, 0 }, // -5.6000E+01=F(  -0.875, +6)
+{72, 3260783022u, 6u, 3210451374u, 0, FREXPF_TOLERANCE, 0 }, // -5.4900E+01=F( -0.8578, +6)
+{73, 3260494664u, 6u, 3210163016u, 0, FREXPF_TOLERANCE, 0 }, // -5.3800E+01=F( -0.8406, +6)
+{74, 3260206306u, 6u, 3209874658u, 0, FREXPF_TOLERANCE, 0 }, // -5.2700E+01=F( -0.8234, +6)
+{75, 3259917948u, 6u, 3209586300u, 0, FREXPF_TOLERANCE, 0 }, // -5.1600E+01=F( -0.8063, +6)
+{76, 3259629590u, 6u, 3209297942u, 0, FREXPF_TOLERANCE, 0 }, // -5.0500E+01=F( -0.7891, +6)
+{77, 3259341232u, 6u, 3209009584u, 0, FREXPF_TOLERANCE, 0 }, // -4.9400E+01=F( -0.7719, +6)
+{78, 3259052874u, 6u, 3208721226u, 0, FREXPF_TOLERANCE, 0 }, // -4.8300E+01=F( -0.7547, +6)
+{79, 3258764516u, 6u, 3208432868u, 0, FREXPF_TOLERANCE, 0 }, // -4.7200E+01=F( -0.7375, +6)
+{80, 3258476158u, 6u, 3208144510u, 0, FREXPF_TOLERANCE, 0 }, // -4.6100E+01=F( -0.7203, +6)
+{81, 3258187800u, 6u, 3207856152u, 0, FREXPF_TOLERANCE, 0 }, // -4.5000E+01=F( -0.7031, +6)
+{82, 3257899442u, 6u, 3207567794u, 0, FREXPF_TOLERANCE, 0 }, // -4.3900E+01=F( -0.6859, +6)
+{83, 3257611084u, 6u, 3207279436u, 0, FREXPF_TOLERANCE, 0 }, // -4.2800E+01=F( -0.6688, +6)
+{84, 3257322726u, 6u, 3206991078u, 0, FREXPF_TOLERANCE, 0 }, // -4.1700E+01=F( -0.6516, +6)
+{85, 3257034368u, 6u, 3206702720u, 0, FREXPF_TOLERANCE, 0 }, // -4.0600E+01=F( -0.6344, +6)
+{86, 3256746010u, 6u, 3206414362u, 0, FREXPF_TOLERANCE, 0 }, // -3.9500E+01=F( -0.6172, +6)
+{87, 3256457652u, 6u, 3206126004u, 0, FREXPF_TOLERANCE, 0 }, // -3.8400E+01=F(    -0.6, +6)
+{88, 3256169294u, 6u, 3205837646u, 0, FREXPF_TOLERANCE, 0 }, // -3.7300E+01=F( -0.5828, +6)
+{89, 3255880936u, 6u, 3205549288u, 0, FREXPF_TOLERANCE, 0 }, // -3.6200E+01=F( -0.5656, +6)
+{90, 3255592578u, 6u, 3205260930u, 0, FREXPF_TOLERANCE, 0 }, // -3.5100E+01=F( -0.5484, +6)
+{91, 3255304220u, 6u, 3204972572u, 0, FREXPF_TOLERANCE, 0 }, // -3.4000E+01=F( -0.5313, +6)
+{92, 3255015862u, 6u, 3204684214u, 0, FREXPF_TOLERANCE, 0 }, // -3.2900E+01=F( -0.5141, +6)
+{93, 3254675103u, 5u, 3212732063u, 0, FREXPF_TOLERANCE, 0 }, // -3.1800E+01=F( -0.9938, +5)
+{94, 3254098386u, 5u, 3212155346u, 0, FREXPF_TOLERANCE, 0 }, // -3.0700E+01=F( -0.9594, +5)
+{95, 3253521669u, 5u, 3211578629u, 0, FREXPF_TOLERANCE, 0 }, // -2.9600E+01=F(  -0.925, +5)
+{96, 3252944952u, 5u, 3211001912u, 0, FREXPF_TOLERANCE, 0 }, // -2.8500E+01=F( -0.8906, +5)
+{97, 3252368235u, 5u, 3210425195u, 0, FREXPF_TOLERANCE, 0 }, // -2.7400E+01=F( -0.8563, +5)
+{98, 3251791518u, 5u, 3209848478u, 0, FREXPF_TOLERANCE, 0 }, // -2.6300E+01=F( -0.8219, +5)
+{99, 3251214801u, 5u, 3209271761u, 0, FREXPF_TOLERANCE, 0 }, // -2.5200E+01=F( -0.7875, +5)
+{100, 3250638084u, 5u, 3208695044u, 0, FREXPF_TOLERANCE, 0 }, // -2.4100E+01=F( -0.7531, +5)
+{101, 3250061367u, 5u, 3208118327u, 0, FREXPF_TOLERANCE, 0 }, // -2.3000E+01=F( -0.7188, +5)
+{102, 3249484650u, 5u, 3207541610u, 0, FREXPF_TOLERANCE, 0 }, // -2.1900E+01=F( -0.6844, +5)
+{103, 3248907933u, 5u, 3206964893u, 0, FREXPF_TOLERANCE, 0 }, // -2.0800E+01=F(   -0.65, +5)
+{104, 3248331216u, 5u, 3206388176u, 0, FREXPF_TOLERANCE, 0 }, // -1.9700E+01=F( -0.6156, +5)
+{105, 3247754499u, 5u, 3205811459u, 0, FREXPF_TOLERANCE, 0 }, // -1.8600E+01=F( -0.5813, +5)
+{106, 3247177782u, 5u, 3205234742u, 0, FREXPF_TOLERANCE, 0 }, // -1.7500E+01=F( -0.5469, +5)
+{107, 3246601065u, 5u, 3204658025u, 0, FREXPF_TOLERANCE, 0 }, // -1.6400E+01=F( -0.5125, +5)
+{108, 3245657400u, 4u, 3212102968u, 0, FREXPF_TOLERANCE, 0 }, // -1.5300E+01=F( -0.9563, +4)
+{109, 3244503966u, 4u, 3210949534u, 0, FREXPF_TOLERANCE, 0 }, // -1.4200E+01=F( -0.8875, +4)
+{110, 3243350532u, 4u, 3209796100u, 0, FREXPF_TOLERANCE, 0 }, // -1.3100E+01=F( -0.8188, +4)
+{111, 3242197098u, 4u, 3208642666u, 0, FREXPF_TOLERANCE, 0 }, // -1.2000E+01=F(   -0.75, +4)
+{112, 3241043664u, 4u, 3207489232u, 0, FREXPF_TOLERANCE, 0 }, // -1.0900E+01=F( -0.6813, +4)
+{113, 3239890230u, 4u, 3206335798u, 0, FREXPF_TOLERANCE, 0 }, // -9.8001E+00=F( -0.6125, +4)
+{114, 3238736796u, 4u, 3205182364u, 0, FREXPF_TOLERANCE, 0 }, // -8.7001E+00=F( -0.5438, +4)
+{115, 3237164037u, 3u, 3211998213u, 0, FREXPF_TOLERANCE, 0 }, // -7.6001E+00=F(   -0.95, +3)
+{116, 3234857170u, 3u, 3209691346u, 0, FREXPF_TOLERANCE, 0 }, // -6.5001E+00=F( -0.8125, +3)
+{117, 3232550303u, 3u, 3207384479u, 0, FREXPF_TOLERANCE, 0 }, // -5.4001E+00=F(  -0.675, +3)
+{118, 3230243436u, 3u, 3205077612u, 0, FREXPF_TOLERANCE, 0 }, // -4.3001E+00=F( -0.5375, +3)
+{119, 3226259058u, 2u, 3209481842u, 0, FREXPF_TOLERANCE, 0 }, // -3.2001E+00=F(    -0.8, +2)
+{120, 3221645324u, 2u, 3204868108u, 0, FREXPF_TOLERANCE, 0 }, // -2.1001E+00=F(  -0.525, +2)
+{121, 3213675725u, 1u, 3205287117u, 0, FREXPF_TOLERANCE, 0 }, // -1.1000E+00=F(   -0.55, +1)
+{122, 3213583450u, 1u, 3205194842u, 0, FREXPF_TOLERANCE, 0 }, // -1.0890E+00=F( -0.5445, +1)
+{123, 3213491175u, 1u, 3205102567u, 0, FREXPF_TOLERANCE, 0 }, // -1.0780E+00=F(  -0.539, +1)
+{124, 3213398900u, 1u, 3205010292u, 0, FREXPF_TOLERANCE, 0 }, // -1.0670E+00=F( -0.5335, +1)
+{125, 3213306625u, 1u, 3204918017u, 0, FREXPF_TOLERANCE, 0 }, // -1.0560E+00=F(  -0.528, +1)
+{126, 3213214350u, 1u, 3204825742u, 0, FREXPF_TOLERANCE, 0 }, // -1.0450E+00=F( -0.5225, +1)
+{127, 3213122075u, 1u, 3204733467u, 0, FREXPF_TOLERANCE, 0 }, // -1.0340E+00=F(  -0.517, +1)
+{128, 3213029800u, 1u, 3204641192u, 0, FREXPF_TOLERANCE, 0 }, // -1.0230E+00=F( -0.5115, +1)
+{129, 3212937525u, 1u, 3204548917u, 0, FREXPF_TOLERANCE, 0 }, // -1.0120E+00=F(  -0.506, +1)
+{130, 3212845250u, 1u, 3204456642u, 0, FREXPF_TOLERANCE, 0 }, // -1.0010E+00=F( -0.5005, +1)
+{131, 3212669087u, 0u, 3212669087u, 0, FREXPF_TOLERANCE, 0 }, // -9.9000E-01=F(   -0.99, +0)
+{132, 3212484538u, 0u, 3212484538u, 0, FREXPF_TOLERANCE, 0 }, // -9.7900E-01=F(  -0.979, +0)
+{133, 3212299989u, 0u, 3212299989u, 0, FREXPF_TOLERANCE, 0 }, // -9.6800E-01=F(  -0.968, +0)
+{134, 3212115440u, 0u, 3212115440u, 0, FREXPF_TOLERANCE, 0 }, // -9.5700E-01=F(  -0.957, +0)
+{135, 3211930891u, 0u, 3211930891u, 0, FREXPF_TOLERANCE, 0 }, // -9.4600E-01=F(  -0.946, +0)
+{136, 3211746342u, 0u, 3211746342u, 0, FREXPF_TOLERANCE, 0 }, // -9.3500E-01=F(  -0.935, +0)
+{137, 3211561793u, 0u, 3211561793u, 0, FREXPF_TOLERANCE, 0 }, // -9.2400E-01=F(  -0.924, +0)
+{138, 3211377244u, 0u, 3211377244u, 0, FREXPF_TOLERANCE, 0 }, // -9.1300E-01=F(  -0.913, +0)
+{139, 3211192695u, 0u, 3211192695u, 0, FREXPF_TOLERANCE, 0 }, // -9.0200E-01=F(  -0.902, +0)
+{140, 3211008146u, 0u, 3211008146u, 0, FREXPF_TOLERANCE, 0 }, // -8.9100E-01=F(  -0.891, +0)
+{141, 3210823597u, 0u, 3210823597u, 0, FREXPF_TOLERANCE, 0 }, // -8.8000E-01=F(   -0.88, +0)
+{142, 3210639048u, 0u, 3210639048u, 0, FREXPF_TOLERANCE, 0 }, // -8.6900E-01=F(  -0.869, +0)
+{143, 3210454499u, 0u, 3210454499u, 0, FREXPF_TOLERANCE, 0 }, // -8.5800E-01=F(  -0.858, +0)
+{144, 3210269950u, 0u, 3210269950u, 0, FREXPF_TOLERANCE, 0 }, // -8.4700E-01=F(  -0.847, +0)
+{145, 3210085401u, 0u, 3210085401u, 0, FREXPF_TOLERANCE, 0 }, // -8.3600E-01=F(  -0.836, +0)
+{146, 3209900852u, 0u, 3209900852u, 0, FREXPF_TOLERANCE, 0 }, // -8.2500E-01=F(  -0.825, +0)
+{147, 3209716303u, 0u, 3209716303u, 0, FREXPF_TOLERANCE, 0 }, // -8.1400E-01=F(  -0.814, +0)
+{148, 3209531754u, 0u, 3209531754u, 0, FREXPF_TOLERANCE, 0 }, // -8.0300E-01=F(  -0.803, +0)
+{149, 3209347205u, 0u, 3209347205u, 0, FREXPF_TOLERANCE, 0 }, // -7.9200E-01=F(  -0.792, +0)
+{150, 3209162656u, 0u, 3209162656u, 0, FREXPF_TOLERANCE, 0 }, // -7.8100E-01=F(  -0.781, +0)
+{151, 3208978107u, 0u, 3208978107u, 0, FREXPF_TOLERANCE, 0 }, // -7.7000E-01=F(   -0.77, +0)
+{152, 3208793558u, 0u, 3208793558u, 0, FREXPF_TOLERANCE, 0 }, // -7.5900E-01=F(  -0.759, +0)
+{153, 3208609009u, 0u, 3208609009u, 0, FREXPF_TOLERANCE, 0 }, // -7.4800E-01=F(  -0.748, +0)
+{154, 3208424460u, 0u, 3208424460u, 0, FREXPF_TOLERANCE, 0 }, // -7.3700E-01=F(  -0.737, +0)
+{155, 3208239911u, 0u, 3208239911u, 0, FREXPF_TOLERANCE, 0 }, // -7.2600E-01=F(  -0.726, +0)
+{156, 3208055362u, 0u, 3208055362u, 0, FREXPF_TOLERANCE, 0 }, // -7.1500E-01=F(  -0.715, +0)
+{157, 3207870813u, 0u, 3207870813u, 0, FREXPF_TOLERANCE, 0 }, // -7.0400E-01=F(  -0.704, +0)
+{158, 3207686264u, 0u, 3207686264u, 0, FREXPF_TOLERANCE, 0 }, // -6.9300E-01=F(  -0.693, +0)
+{159, 3207501715u, 0u, 3207501715u, 0, FREXPF_TOLERANCE, 0 }, // -6.8200E-01=F(  -0.682, +0)
+{160, 3207317166u, 0u, 3207317166u, 0, FREXPF_TOLERANCE, 0 }, // -6.7100E-01=F(  -0.671, +0)
+{161, 3207132617u, 0u, 3207132617u, 0, FREXPF_TOLERANCE, 0 }, // -6.6000E-01=F(   -0.66, +0)
+{162, 3206948068u, 0u, 3206948068u, 0, FREXPF_TOLERANCE, 0 }, // -6.4900E-01=F(  -0.649, +0)
+{163, 3206763519u, 0u, 3206763519u, 0, FREXPF_TOLERANCE, 0 }, // -6.3800E-01=F(  -0.638, +0)
+{164, 3206578970u, 0u, 3206578970u, 0, FREXPF_TOLERANCE, 0 }, // -6.2700E-01=F(  -0.627, +0)
+{165, 3206394421u, 0u, 3206394421u, 0, FREXPF_TOLERANCE, 0 }, // -6.1600E-01=F(  -0.616, +0)
+{166, 3206209872u, 0u, 3206209872u, 0, FREXPF_TOLERANCE, 0 }, // -6.0500E-01=F(  -0.605, +0)
+{167, 3206025323u, 0u, 3206025323u, 0, FREXPF_TOLERANCE, 0 }, // -5.9400E-01=F(  -0.594, +0)
+{168, 3205840774u, 0u, 3205840774u, 0, FREXPF_TOLERANCE, 0 }, // -5.8300E-01=F(  -0.583, +0)
+{169, 3205656225u, 0u, 3205656225u, 0, FREXPF_TOLERANCE, 0 }, // -5.7200E-01=F(  -0.572, +0)
+{170, 3205471676u, 0u, 3205471676u, 0, FREXPF_TOLERANCE, 0 }, // -5.6100E-01=F(  -0.561, +0)
+{171, 3205287127u, 0u, 3205287127u, 0, FREXPF_TOLERANCE, 0 }, // -5.5000E-01=F(   -0.55, +0)
+{172, 3205102578u, 0u, 3205102578u, 0, FREXPF_TOLERANCE, 0 }, // -5.3900E-01=F(  -0.539, +0)
+{173, 3204918029u, 0u, 3204918029u, 0, FREXPF_TOLERANCE, 0 }, // -5.2800E-01=F(  -0.528, +0)
+{174, 3204733480u, 0u, 3204733480u, 0, FREXPF_TOLERANCE, 0 }, // -5.1700E-01=F(  -0.517, +0)
+{175, 3204548931u, 0u, 3204548931u, 0, FREXPF_TOLERANCE, 0 }, // -5.0600E-01=F(  -0.506, +0)
+{176, 3204280507u, 4294967295u, 3212669115u, 0, FREXPF_TOLERANCE, 0 }, // -4.9500E-01=F(   -0.99, -1)
+{177, 3203911408u, 4294967295u, 3212300016u, 0, FREXPF_TOLERANCE, 0 }, // -4.8400E-01=F(  -0.968, -1)
+{178, 3203542309u, 4294967295u, 3211930917u, 0, FREXPF_TOLERANCE, 0 }, // -4.7300E-01=F(  -0.946, -1)
+{179, 3203173210u, 4294967295u, 3211561818u, 0, FREXPF_TOLERANCE, 0 }, // -4.6200E-01=F(  -0.924, -1)
+{180, 3202804111u, 4294967295u, 3211192719u, 0, FREXPF_TOLERANCE, 0 }, // -4.5100E-01=F(  -0.902, -1)
+{181, 3202435012u, 4294967295u, 3210823620u, 0, FREXPF_TOLERANCE, 0 }, // -4.4000E-01=F(   -0.88, -1)
+{182, 3202065913u, 4294967295u, 3210454521u, 0, FREXPF_TOLERANCE, 0 }, // -4.2900E-01=F(  -0.858, -1)
+{183, 3201696814u, 4294967295u, 3210085422u, 0, FREXPF_TOLERANCE, 0 }, // -4.1800E-01=F(  -0.836, -1)
+{184, 3201327715u, 4294967295u, 3209716323u, 0, FREXPF_TOLERANCE, 0 }, // -4.0700E-01=F(  -0.814, -1)
+{185, 3200958616u, 4294967295u, 3209347224u, 0, FREXPF_TOLERANCE, 0 }, // -3.9600E-01=F(  -0.792, -1)
+{186, 3200589517u, 4294967295u, 3208978125u, 0, FREXPF_TOLERANCE, 0 }, // -3.8500E-01=F(   -0.77, -1)
+{187, 3200220418u, 4294967295u, 3208609026u, 0, FREXPF_TOLERANCE, 0 }, // -3.7400E-01=F(  -0.748, -1)
+{188, 3199851319u, 4294967295u, 3208239927u, 0, FREXPF_TOLERANCE, 0 }, // -3.6300E-01=F(  -0.726, -1)
+{189, 3199482220u, 4294967295u, 3207870828u, 0, FREXPF_TOLERANCE, 0 }, // -3.5200E-01=F(  -0.704, -1)
+{190, 3199113121u, 4294967295u, 3207501729u, 0, FREXPF_TOLERANCE, 0 }, // -3.4100E-01=F(  -0.682, -1)
+{191, 3198744022u, 4294967295u, 3207132630u, 0, FREXPF_TOLERANCE, 0 }, // -3.3000E-01=F(   -0.66, -1)
+{192, 3198374923u, 4294967295u, 3206763531u, 0, FREXPF_TOLERANCE, 0 }, // -3.1900E-01=F(  -0.638, -1)
+{193, 3198005824u, 4294967295u, 3206394432u, 0, FREXPF_TOLERANCE, 0 }, // -3.0800E-01=F(  -0.616, -1)
+{194, 3197636725u, 4294967295u, 3206025333u, 0, FREXPF_TOLERANCE, 0 }, // -2.9700E-01=F(  -0.594, -1)
+{195, 3197267626u, 4294967295u, 3205656234u, 0, FREXPF_TOLERANCE, 0 }, // -2.8600E-01=F(  -0.572, -1)
+{196, 3196898527u, 4294967295u, 3205287135u, 0, FREXPF_TOLERANCE, 0 }, // -2.7500E-01=F(   -0.55, -1)
+{197, 3196529428u, 4294967295u, 3204918036u, 0, FREXPF_TOLERANCE, 0 }, // -2.6400E-01=F(  -0.528, -1)
+{198, 3196160329u, 4294967295u, 3204548937u, 0, FREXPF_TOLERANCE, 0 }, // -2.5300E-01=F(  -0.506, -1)
+{199, 3195522812u, 4294967294u, 3212300028u, 0, FREXPF_TOLERANCE, 0 }, // -2.4200E-01=F(  -0.968, -2)
+{200, 3194784614u, 4294967294u, 3211561830u, 0, FREXPF_TOLERANCE, 0 }, // -2.3100E-01=F(  -0.924, -2)
+{201, 3194046416u, 4294967294u, 3210823632u, 0, FREXPF_TOLERANCE, 0 }, // -2.2000E-01=F(   -0.88, -2)
+{202, 3193308218u, 4294967294u, 3210085434u, 0, FREXPF_TOLERANCE, 0 }, // -2.0900E-01=F(  -0.836, -2)
+{203, 3192570020u, 4294967294u, 3209347236u, 0, FREXPF_TOLERANCE, 0 }, // -1.9800E-01=F(  -0.792, -2)
+{204, 3191831822u, 4294967294u, 3208609038u, 0, FREXPF_TOLERANCE, 0 }, // -1.8700E-01=F(  -0.748, -2)
+{205, 3191093624u, 4294967294u, 3207870840u, 0, FREXPF_TOLERANCE, 0 }, // -1.7600E-01=F(  -0.704, -2)
+{206, 3190355426u, 4294967294u, 3207132642u, 0, FREXPF_TOLERANCE, 0 }, // -1.6500E-01=F(   -0.66, -2)
+{207, 3189617228u, 4294967294u, 3206394444u, 0, FREXPF_TOLERANCE, 0 }, // -1.5400E-01=F(  -0.616, -2)
+{208, 3188879030u, 4294967294u, 3205656246u, 0, FREXPF_TOLERANCE, 0 }, // -1.4300E-01=F(  -0.572, -2)
+{209, 3188140832u, 4294967294u, 3204918048u, 0, FREXPF_TOLERANCE, 0 }, // -1.3200E-01=F(  -0.528, -2)
+{210, 3187134229u, 4294967293u, 3212300053u, 0, FREXPF_TOLERANCE, 0 }, // -1.2100E-01=F(  -0.968, -3)
+{211, 3185657834u, 4294967293u, 3210823658u, 0, FREXPF_TOLERANCE, 0 }, // -1.1000E-01=F(   -0.88, -3)
+{212, 3184181439u, 4294967293u, 3209347263u, 0, FREXPF_TOLERANCE, 0 }, // -9.9000E-02=F(  -0.792, -3)
+{213, 3182705044u, 4294967293u, 3207870868u, 0, FREXPF_TOLERANCE, 0 }, // -8.8000E-02=F(  -0.704, -3)
+{214, 3181228649u, 4294967293u, 3206394473u, 0, FREXPF_TOLERANCE, 0 }, // -7.7000E-02=F(  -0.616, -3)
+{215, 3179752254u, 4294967293u, 3204918078u, 0, FREXPF_TOLERANCE, 0 }, // -6.6000E-02=F(  -0.528, -3)
+{216, 3177269286u, 4294967292u, 3210823718u, 0, FREXPF_TOLERANCE, 0 }, // -5.5000E-02=F(   -0.88, -4)
+{217, 3174316496u, 4294967292u, 3207870928u, 0, FREXPF_TOLERANCE, 0 }, // -4.4000E-02=F(  -0.704, -4)
+{218, 3171363706u, 4294967292u, 3204918138u, 0, FREXPF_TOLERANCE, 0 }, // -3.3000E-02=F(  -0.528, -4)
+{219, 3165928008u, 4294967291u, 3207871048u, 0, FREXPF_TOLERANCE, 0 }, // -2.2000E-02=F(  -0.704, -5)
+{220, 3157539640u, 4294967290u, 3207871288u, 0, FREXPF_TOLERANCE, 0 }, // -1.1000E-02=F(  -0.704, -6)
+{221, 3035625423u, 4294967275u, 3211786191u, 0, FREXPF_TOLERANCE, 0 }, // -4.4698E-07=F( -0.9374, -21)
+{222, 1010055032u, 4294967290u, 1060386680u, 0, FREXPF_TOLERANCE, 0 }, // +1.1000E-02=F(  +0.704, -6)
+{223, 1018443880u, 4294967291u, 1060386920u, 0, FREXPF_TOLERANCE, 0 }, // +2.2000E-02=F(  +0.704, -5)
+{224, 1023879818u, 4294967292u, 1057434250u, 0, FREXPF_TOLERANCE, 0 }, // +3.3000E-02=F(  +0.528, -4)
+{225, 1026832608u, 4294967292u, 1060387040u, 0, FREXPF_TOLERANCE, 0 }, // +4.4000E-02=F(  +0.704, -4)
+{226, 1029785398u, 4294967292u, 1063339830u, 0, FREXPF_TOLERANCE, 0 }, // +5.5000E-02=F(   +0.88, -4)
+{227, 1032268486u, 4294967293u, 1057434310u, 0, FREXPF_TOLERANCE, 0 }, // +6.6000E-02=F(  +0.528, -3)
+{228, 1033744881u, 4294967293u, 1058910705u, 0, FREXPF_TOLERANCE, 0 }, // +7.7000E-02=F(  +0.616, -3)
+{229, 1035221276u, 4294967293u, 1060387100u, 0, FREXPF_TOLERANCE, 0 }, // +8.8000E-02=F(  +0.704, -3)
+{230, 1036697671u, 4294967293u, 1061863495u, 0, FREXPF_TOLERANCE, 0 }, // +9.9000E-02=F(  +0.792, -3)
+{231, 1038174066u, 4294967293u, 1063339890u, 0, FREXPF_TOLERANCE, 0 }, // +1.1000E-01=F(   +0.88, -3)
+{232, 1039650461u, 4294967293u, 1064816285u, 0, FREXPF_TOLERANCE, 0 }, // +1.2100E-01=F(  +0.968, -3)
+{233, 1040657124u, 4294967294u, 1057434340u, 0, FREXPF_TOLERANCE, 0 }, // +1.3200E-01=F(  +0.528, -2)
+{234, 1041395322u, 4294967294u, 1058172538u, 0, FREXPF_TOLERANCE, 0 }, // +1.4300E-01=F(  +0.572, -2)
+{235, 1042133520u, 4294967294u, 1058910736u, 0, FREXPF_TOLERANCE, 0 }, // +1.5400E-01=F(  +0.616, -2)
+{236, 1042871718u, 4294967294u, 1059648934u, 0, FREXPF_TOLERANCE, 0 }, // +1.6500E-01=F(   +0.66, -2)
+{237, 1043609916u, 4294967294u, 1060387132u, 0, FREXPF_TOLERANCE, 0 }, // +1.7600E-01=F(  +0.704, -2)
+{238, 1044348114u, 4294967294u, 1061125330u, 0, FREXPF_TOLERANCE, 0 }, // +1.8700E-01=F(  +0.748, -2)
+{239, 1045086312u, 4294967294u, 1061863528u, 0, FREXPF_TOLERANCE, 0 }, // +1.9800E-01=F(  +0.792, -2)
+{240, 1045824510u, 4294967294u, 1062601726u, 0, FREXPF_TOLERANCE, 0 }, // +2.0900E-01=F(  +0.836, -2)
+{241, 1046562708u, 4294967294u, 1063339924u, 0, FREXPF_TOLERANCE, 0 }, // +2.2000E-01=F(   +0.88, -2)
+{242, 1047300906u, 4294967294u, 1064078122u, 0, FREXPF_TOLERANCE, 0 }, // +2.3100E-01=F(  +0.924, -2)
+{243, 1048039104u, 4294967294u, 1064816320u, 0, FREXPF_TOLERANCE, 0 }, // +2.4200E-01=F(  +0.968, -2)
+{244, 1048676651u, 4294967295u, 1057065259u, 0, FREXPF_TOLERANCE, 0 }, // +2.5300E-01=F(  +0.506, -1)
+{245, 1049045750u, 4294967295u, 1057434358u, 0, FREXPF_TOLERANCE, 0 }, // +2.6400E-01=F(  +0.528, -1)
+{246, 1049414849u, 4294967295u, 1057803457u, 0, FREXPF_TOLERANCE, 0 }, // +2.7500E-01=F(   +0.55, -1)
+{247, 1049783948u, 4294967295u, 1058172556u, 0, FREXPF_TOLERANCE, 0 }, // +2.8600E-01=F(  +0.572, -1)
+{248, 1050153047u, 4294967295u, 1058541655u, 0, FREXPF_TOLERANCE, 0 }, // +2.9700E-01=F(  +0.594, -1)
+{249, 1050522146u, 4294967295u, 1058910754u, 0, FREXPF_TOLERANCE, 0 }, // +3.0800E-01=F(  +0.616, -1)
+{250, 1050891245u, 4294967295u, 1059279853u, 0, FREXPF_TOLERANCE, 0 }, // +3.1900E-01=F(  +0.638, -1)
+{251, 1051260344u, 4294967295u, 1059648952u, 0, FREXPF_TOLERANCE, 0 }, // +3.3000E-01=F(   +0.66, -1)
+{252, 1051629443u, 4294967295u, 1060018051u, 0, FREXPF_TOLERANCE, 0 }, // +3.4100E-01=F(  +0.682, -1)
+{253, 1051998542u, 4294967295u, 1060387150u, 0, FREXPF_TOLERANCE, 0 }, // +3.5200E-01=F(  +0.704, -1)
+{254, 1052367641u, 4294967295u, 1060756249u, 0, FREXPF_TOLERANCE, 0 }, // +3.6300E-01=F(  +0.726, -1)
+{255, 1052736740u, 4294967295u, 1061125348u, 0, FREXPF_TOLERANCE, 0 }, // +3.7400E-01=F(  +0.748, -1)
+{256, 1053105839u, 4294967295u, 1061494447u, 0, FREXPF_TOLERANCE, 0 }, // +3.8500E-01=F(   +0.77, -1)
+{257, 1053474938u, 4294967295u, 1061863546u, 0, FREXPF_TOLERANCE, 0 }, // +3.9600E-01=F(  +0.792, -1)
+{258, 1053844037u, 4294967295u, 1062232645u, 0, FREXPF_TOLERANCE, 0 }, // +4.0700E-01=F(  +0.814, -1)
+{259, 1054213136u, 4294967295u, 1062601744u, 0, FREXPF_TOLERANCE, 0 }, // +4.1800E-01=F(  +0.836, -1)
+{260, 1054582235u, 4294967295u, 1062970843u, 0, FREXPF_TOLERANCE, 0 }, // +4.2900E-01=F(  +0.858, -1)
+{261, 1054951334u, 4294967295u, 1063339942u, 0, FREXPF_TOLERANCE, 0 }, // +4.4000E-01=F(   +0.88, -1)
+{262, 1055320433u, 4294967295u, 1063709041u, 0, FREXPF_TOLERANCE, 0 }, // +4.5100E-01=F(  +0.902, -1)
+{263, 1055689532u, 4294967295u, 1064078140u, 0, FREXPF_TOLERANCE, 0 }, // +4.6200E-01=F(  +0.924, -1)
+{264, 1056058631u, 4294967295u, 1064447239u, 0, FREXPF_TOLERANCE, 0 }, // +4.7300E-01=F(  +0.946, -1)
+{265, 1056427730u, 4294967295u, 1064816338u, 0, FREXPF_TOLERANCE, 0 }, // +4.8400E-01=F(  +0.968, -1)
+{266, 1056796829u, 4294967295u, 1065185437u, 0, FREXPF_TOLERANCE, 0 }, // +4.9500E-01=F(   +0.99, -1)
+{267, 1057065268u, 0u, 1057065268u, 0, FREXPF_TOLERANCE, 0 }, // +5.0600E-01=F(  +0.506, +0)
+{268, 1057249817u, 0u, 1057249817u, 0, FREXPF_TOLERANCE, 0 }, // +5.1700E-01=F(  +0.517, +0)
+{269, 1057434366u, 0u, 1057434366u, 0, FREXPF_TOLERANCE, 0 }, // +5.2800E-01=F(  +0.528, +0)
+{270, 1057618915u, 0u, 1057618915u, 0, FREXPF_TOLERANCE, 0 }, // +5.3900E-01=F(  +0.539, +0)
+{271, 1057803464u, 0u, 1057803464u, 0, FREXPF_TOLERANCE, 0 }, // +5.5000E-01=F(   +0.55, +0)
+{272, 1057988013u, 0u, 1057988013u, 0, FREXPF_TOLERANCE, 0 }, // +5.6100E-01=F(  +0.561, +0)
+{273, 1058172562u, 0u, 1058172562u, 0, FREXPF_TOLERANCE, 0 }, // +5.7200E-01=F(  +0.572, +0)
+{274, 1058357111u, 0u, 1058357111u, 0, FREXPF_TOLERANCE, 0 }, // +5.8300E-01=F(  +0.583, +0)
+{275, 1058541660u, 0u, 1058541660u, 0, FREXPF_TOLERANCE, 0 }, // +5.9400E-01=F(  +0.594, +0)
+{276, 1058726209u, 0u, 1058726209u, 0, FREXPF_TOLERANCE, 0 }, // +6.0500E-01=F(  +0.605, +0)
+{277, 1058910758u, 0u, 1058910758u, 0, FREXPF_TOLERANCE, 0 }, // +6.1600E-01=F(  +0.616, +0)
+{278, 1059095307u, 0u, 1059095307u, 0, FREXPF_TOLERANCE, 0 }, // +6.2700E-01=F(  +0.627, +0)
+{279, 1059279856u, 0u, 1059279856u, 0, FREXPF_TOLERANCE, 0 }, // +6.3800E-01=F(  +0.638, +0)
+{280, 1059464405u, 0u, 1059464405u, 0, FREXPF_TOLERANCE, 0 }, // +6.4900E-01=F(  +0.649, +0)
+{281, 1059648954u, 0u, 1059648954u, 0, FREXPF_TOLERANCE, 0 }, // +6.6000E-01=F(   +0.66, +0)
+{282, 1059833503u, 0u, 1059833503u, 0, FREXPF_TOLERANCE, 0 }, // +6.7100E-01=F(  +0.671, +0)
+{283, 1060018052u, 0u, 1060018052u, 0, FREXPF_TOLERANCE, 0 }, // +6.8200E-01=F(  +0.682, +0)
+{284, 1060202601u, 0u, 1060202601u, 0, FREXPF_TOLERANCE, 0 }, // +6.9300E-01=F(  +0.693, +0)
+{285, 1060387150u, 0u, 1060387150u, 0, FREXPF_TOLERANCE, 0 }, // +7.0400E-01=F(  +0.704, +0)
+{286, 1060571699u, 0u, 1060571699u, 0, FREXPF_TOLERANCE, 0 }, // +7.1500E-01=F(  +0.715, +0)
+{287, 1060756248u, 0u, 1060756248u, 0, FREXPF_TOLERANCE, 0 }, // +7.2600E-01=F(  +0.726, +0)
+{288, 1060940797u, 0u, 1060940797u, 0, FREXPF_TOLERANCE, 0 }, // +7.3700E-01=F(  +0.737, +0)
+{289, 1061125346u, 0u, 1061125346u, 0, FREXPF_TOLERANCE, 0 }, // +7.4800E-01=F(  +0.748, +0)
+{290, 1061309895u, 0u, 1061309895u, 0, FREXPF_TOLERANCE, 0 }, // +7.5900E-01=F(  +0.759, +0)
+{291, 1061494444u, 0u, 1061494444u, 0, FREXPF_TOLERANCE, 0 }, // +7.7000E-01=F(   +0.77, +0)
+{292, 1061678993u, 0u, 1061678993u, 0, FREXPF_TOLERANCE, 0 }, // +7.8100E-01=F(  +0.781, +0)
+{293, 1061863542u, 0u, 1061863542u, 0, FREXPF_TOLERANCE, 0 }, // +7.9200E-01=F(  +0.792, +0)
+{294, 1062048091u, 0u, 1062048091u, 0, FREXPF_TOLERANCE, 0 }, // +8.0300E-01=F(  +0.803, +0)
+{295, 1062232640u, 0u, 1062232640u, 0, FREXPF_TOLERANCE, 0 }, // +8.1400E-01=F(  +0.814, +0)
+{296, 1062417189u, 0u, 1062417189u, 0, FREXPF_TOLERANCE, 0 }, // +8.2500E-01=F(  +0.825, +0)
+{297, 1062601738u, 0u, 1062601738u, 0, FREXPF_TOLERANCE, 0 }, // +8.3600E-01=F(  +0.836, +0)
+{298, 1062786287u, 0u, 1062786287u, 0, FREXPF_TOLERANCE, 0 }, // +8.4700E-01=F(  +0.847, +0)
+{299, 1062970836u, 0u, 1062970836u, 0, FREXPF_TOLERANCE, 0 }, // +8.5800E-01=F(  +0.858, +0)
+{300, 1063155385u, 0u, 1063155385u, 0, FREXPF_TOLERANCE, 0 }, // +8.6900E-01=F(  +0.869, +0)
+{301, 1063339934u, 0u, 1063339934u, 0, FREXPF_TOLERANCE, 0 }, // +8.8000E-01=F(   +0.88, +0)
+{302, 1063524483u, 0u, 1063524483u, 0, FREXPF_TOLERANCE, 0 }, // +8.9100E-01=F(  +0.891, +0)
+{303, 1063709032u, 0u, 1063709032u, 0, FREXPF_TOLERANCE, 0 }, // +9.0200E-01=F(  +0.902, +0)
+{304, 1063893581u, 0u, 1063893581u, 0, FREXPF_TOLERANCE, 0 }, // +9.1300E-01=F(  +0.913, +0)
+{305, 1064078130u, 0u, 1064078130u, 0, FREXPF_TOLERANCE, 0 }, // +9.2400E-01=F(  +0.924, +0)
+{306, 1064262679u, 0u, 1064262679u, 0, FREXPF_TOLERANCE, 0 }, // +9.3500E-01=F(  +0.935, +0)
+{307, 1064447228u, 0u, 1064447228u, 0, FREXPF_TOLERANCE, 0 }, // +9.4600E-01=F(  +0.946, +0)
+{308, 1064631777u, 0u, 1064631777u, 0, FREXPF_TOLERANCE, 0 }, // +9.5700E-01=F(  +0.957, +0)
+{309, 1064816326u, 0u, 1064816326u, 0, FREXPF_TOLERANCE, 0 }, // +9.6800E-01=F(  +0.968, +0)
+{310, 1065000875u, 0u, 1065000875u, 0, FREXPF_TOLERANCE, 0 }, // +9.7900E-01=F(  +0.979, +0)
+{311, 1065185424u, 0u, 1065185424u, 0, FREXPF_TOLERANCE, 0 }, // +9.9000E-01=F(   +0.99, +0)
+{312, 1065361595u, 1u, 1056972987u, 0, FREXPF_TOLERANCE, 0 }, // +1.0010E+00=F( +0.5005, +1)
+{313, 1065453870u, 1u, 1057065262u, 0, FREXPF_TOLERANCE, 0 }, // +1.0120E+00=F(  +0.506, +1)
+{314, 1065546145u, 1u, 1057157537u, 0, FREXPF_TOLERANCE, 0 }, // +1.0230E+00=F( +0.5115, +1)
+{315, 1065638420u, 1u, 1057249812u, 0, FREXPF_TOLERANCE, 0 }, // +1.0340E+00=F(  +0.517, +1)
+{316, 1065730695u, 1u, 1057342087u, 0, FREXPF_TOLERANCE, 0 }, // +1.0450E+00=F( +0.5225, +1)
+{317, 1065822970u, 1u, 1057434362u, 0, FREXPF_TOLERANCE, 0 }, // +1.0560E+00=F(  +0.528, +1)
+{318, 1065915245u, 1u, 1057526637u, 0, FREXPF_TOLERANCE, 0 }, // +1.0670E+00=F( +0.5335, +1)
+{319, 1066007520u, 1u, 1057618912u, 0, FREXPF_TOLERANCE, 0 }, // +1.0780E+00=F(  +0.539, +1)
+{320, 1066099795u, 1u, 1057711187u, 0, FREXPF_TOLERANCE, 0 }, // +1.0890E+00=F( +0.5445, +1)
+{321, 1066192070u, 1u, 1057803462u, 0, FREXPF_TOLERANCE, 0 }, // +1.1000E+00=F(   +0.55, +1)
+{322, 3213675725u, 1u, 3205287117u, 0, FREXPF_TOLERANCE, 0 }, // -1.1000E+00=F(   -0.55, +1)
+{323, 2999766221u, 4294967271u, 3209481421u, 0, FREXPF_TOLERANCE, 0 }, // -2.3842E-08=F(    -0.8, -25)
+{324, 1066192077u, 1u, 1057803469u, 0, FREXPF_TOLERANCE, 0 }, // +1.1000E+00=F(   +0.55, +1)
+{325, 1074580685u, 2u, 1057803469u, 0, FREXPF_TOLERANCE, 0 }, // +2.2000E+00=F(   +0.55, +2)
+{326, 1079194419u, 2u, 1062417203u, 0, FREXPF_TOLERANCE, 0 }, // +3.3000E+00=F(  +0.825, +2)
+{327, 1082969293u, 3u, 1057803469u, 0, FREXPF_TOLERANCE, 0 }, // +4.4000E+00=F(   +0.55, +3)
+{328, 1085276160u, 3u, 1060110336u, 0, FREXPF_TOLERANCE, 0 }, // +5.5000E+00=F( +0.6875, +3)
+{329, 1087583027u, 3u, 1062417203u, 0, FREXPF_TOLERANCE, 0 }, // +6.6000E+00=F(  +0.825, +3)
+{330, 1089889894u, 3u, 1064724070u, 0, FREXPF_TOLERANCE, 0 }, // +7.7000E+00=F( +0.9625, +3)
+{331, 1091357901u, 4u, 1057803469u, 0, FREXPF_TOLERANCE, 0 }, // +8.8000E+00=F(   +0.55, +4)
+{332, 1092511335u, 4u, 1058956903u, 0, FREXPF_TOLERANCE, 0 }, // +9.9000E+00=F( +0.6188, +4)
+{333, 1093664769u, 4u, 1060110337u, 0, FREXPF_TOLERANCE, 0 }, // +1.1000E+01=F( +0.6875, +4)
+{334, 1094818203u, 4u, 1061263771u, 0, FREXPF_TOLERANCE, 0 }, // +1.2100E+01=F( +0.7563, +4)
+{335, 1095971637u, 4u, 1062417205u, 0, FREXPF_TOLERANCE, 0 }, // +1.3200E+01=F(  +0.825, +4)
+{336, 1097125071u, 4u, 1063570639u, 0, FREXPF_TOLERANCE, 0 }, // +1.4300E+01=F( +0.8938, +4)
+{337, 1098278505u, 4u, 1064724073u, 0, FREXPF_TOLERANCE, 0 }, // +1.5400E+01=F( +0.9625, +4)
+{338, 1099169793u, 5u, 1057226753u, 0, FREXPF_TOLERANCE, 0 }, // +1.6500E+01=F( +0.5156, +5)
+{339, 1099746510u, 5u, 1057803470u, 0, FREXPF_TOLERANCE, 0 }, // +1.7600E+01=F(   +0.55, +5)
+{340, 1100323227u, 5u, 1058380187u, 0, FREXPF_TOLERANCE, 0 }, // +1.8700E+01=F( +0.5844, +5)
+{341, 1100899944u, 5u, 1058956904u, 0, FREXPF_TOLERANCE, 0 }, // +1.9800E+01=F( +0.6188, +5)
+{342, 1101476661u, 5u, 1059533621u, 0, FREXPF_TOLERANCE, 0 }, // +2.0900E+01=F( +0.6531, +5)
+{343, 1102053378u, 5u, 1060110338u, 0, FREXPF_TOLERANCE, 0 }, // +2.2000E+01=F( +0.6875, +5)
+{344, 1102630095u, 5u, 1060687055u, 0, FREXPF_TOLERANCE, 0 }, // +2.3100E+01=F( +0.7219, +5)
+{345, 1103206812u, 5u, 1061263772u, 0, FREXPF_TOLERANCE, 0 }, // +2.4200E+01=F( +0.7563, +5)
+{346, 1103783529u, 5u, 1061840489u, 0, FREXPF_TOLERANCE, 0 }, // +2.5300E+01=F( +0.7906, +5)
+{347, 1104360246u, 5u, 1062417206u, 0, FREXPF_TOLERANCE, 0 }, // +2.6400E+01=F(  +0.825, +5)
+{348, 1104936963u, 5u, 1062993923u, 0, FREXPF_TOLERANCE, 0 }, // +2.7500E+01=F( +0.8594, +5)
+{349, 1105513680u, 5u, 1063570640u, 0, FREXPF_TOLERANCE, 0 }, // +2.8600E+01=F( +0.8938, +5)
+{350, 1106090397u, 5u, 1064147357u, 0, FREXPF_TOLERANCE, 0 }, // +2.9700E+01=F( +0.9281, +5)
+{351, 1106667114u, 5u, 1064724074u, 0, FREXPF_TOLERANCE, 0 }, // +3.0800E+01=F( +0.9625, +5)
+{352, 1107243831u, 5u, 1065300791u, 0, FREXPF_TOLERANCE, 0 }, // +3.1900E+01=F( +0.9969, +5)
+{353, 1107558402u, 6u, 1057226754u, 0, FREXPF_TOLERANCE, 0 }, // +3.3000E+01=F( +0.5156, +6)
+{354, 1107846760u, 6u, 1057515112u, 0, FREXPF_TOLERANCE, 0 }, // +3.4100E+01=F( +0.5328, +6)
+{355, 1108135118u, 6u, 1057803470u, 0, FREXPF_TOLERANCE, 0 }, // +3.5200E+01=F(   +0.55, +6)
+{356, 1108423476u, 6u, 1058091828u, 0, FREXPF_TOLERANCE, 0 }, // +3.6300E+01=F( +0.5672, +6)
+{357, 1108711834u, 6u, 1058380186u, 0, FREXPF_TOLERANCE, 0 }, // +3.7400E+01=F( +0.5844, +6)
+{358, 1109000192u, 6u, 1058668544u, 0, FREXPF_TOLERANCE, 0 }, // +3.8500E+01=F( +0.6016, +6)
+{359, 1109288550u, 6u, 1058956902u, 0, FREXPF_TOLERANCE, 0 }, // +3.9600E+01=F( +0.6187, +6)
+{360, 1109576908u, 6u, 1059245260u, 0, FREXPF_TOLERANCE, 0 }, // +4.0700E+01=F( +0.6359, +6)
+{361, 1109865266u, 6u, 1059533618u, 0, FREXPF_TOLERANCE, 0 }, // +4.1800E+01=F( +0.6531, +6)
+{362, 1110153624u, 6u, 1059821976u, 0, FREXPF_TOLERANCE, 0 }, // +4.2900E+01=F( +0.6703, +6)
+{363, 1110441982u, 6u, 1060110334u, 0, FREXPF_TOLERANCE, 0 }, // +4.4000E+01=F( +0.6875, +6)
+{364, 1110730340u, 6u, 1060398692u, 0, FREXPF_TOLERANCE, 0 }, // +4.5100E+01=F( +0.7047, +6)
+{365, 1111018698u, 6u, 1060687050u, 0, FREXPF_TOLERANCE, 0 }, // +4.6200E+01=F( +0.7219, +6)
+{366, 1111307056u, 6u, 1060975408u, 0, FREXPF_TOLERANCE, 0 }, // +4.7300E+01=F( +0.7391, +6)
+{367, 1111595414u, 6u, 1061263766u, 0, FREXPF_TOLERANCE, 0 }, // +4.8400E+01=F( +0.7562, +6)
+{368, 1111883772u, 6u, 1061552124u, 0, FREXPF_TOLERANCE, 0 }, // +4.9500E+01=F( +0.7734, +6)
+{369, 1112172130u, 6u, 1061840482u, 0, FREXPF_TOLERANCE, 0 }, // +5.0600E+01=F( +0.7906, +6)
+{370, 1112460488u, 6u, 1062128840u, 0, FREXPF_TOLERANCE, 0 }, // +5.1700E+01=F( +0.8078, +6)
+{371, 1112748846u, 6u, 1062417198u, 0, FREXPF_TOLERANCE, 0 }, // +5.2800E+01=F(  +0.825, +6)
+{372, 1113037204u, 6u, 1062705556u, 0, FREXPF_TOLERANCE, 0 }, // +5.3900E+01=F( +0.8422, +6)
+{373, 1113325562u, 6u, 1062993914u, 0, FREXPF_TOLERANCE, 0 }, // +5.5000E+01=F( +0.8594, +6)
+{374, 1113613920u, 6u, 1063282272u, 0, FREXPF_TOLERANCE, 0 }, // +5.6100E+01=F( +0.8766, +6)
+{375, 1113902278u, 6u, 1063570630u, 0, FREXPF_TOLERANCE, 0 }, // +5.7200E+01=F( +0.8937, +6)
+{376, 1114190636u, 6u, 1063858988u, 0, FREXPF_TOLERANCE, 0 }, // +5.8300E+01=F( +0.9109, +6)
+{377, 1114478994u, 6u, 1064147346u, 0, FREXPF_TOLERANCE, 0 }, // +5.9400E+01=F( +0.9281, +6)
+{378, 1114767352u, 6u, 1064435704u, 0, FREXPF_TOLERANCE, 0 }, // +6.0500E+01=F( +0.9453, +6)
+{379, 1115055710u, 6u, 1064724062u, 0, FREXPF_TOLERANCE, 0 }, // +6.1600E+01=F( +0.9625, +6)
+{380, 1115344068u, 6u, 1065012420u, 0, FREXPF_TOLERANCE, 0 }, // +6.2700E+01=F( +0.9797, +6)
+{381, 1115632426u, 6u, 1065300778u, 0, FREXPF_TOLERANCE, 0 }, // +6.3800E+01=F( +0.9969, +6)
+{382, 1115802824u, 7u, 1057082568u, 0, FREXPF_TOLERANCE, 0 }, // +6.4900E+01=F(  +0.507, +7)
+{383, 1115947003u, 7u, 1057226747u, 0, FREXPF_TOLERANCE, 0 }, // +6.6000E+01=F( +0.5156, +7)
+{384, 1116091182u, 7u, 1057370926u, 0, FREXPF_TOLERANCE, 0 }, // +6.7100E+01=F( +0.5242, +7)
+{385, 1116235361u, 7u, 1057515105u, 0, FREXPF_TOLERANCE, 0 }, // +6.8200E+01=F( +0.5328, +7)
+{386, 1116379540u, 7u, 1057659284u, 0, FREXPF_TOLERANCE, 0 }, // +6.9300E+01=F( +0.5414, +7)
+{387, 1116523719u, 7u, 1057803463u, 0, FREXPF_TOLERANCE, 0 }, // +7.0400E+01=F(   +0.55, +7)
+{388, 1116667898u, 7u, 1057947642u, 0, FREXPF_TOLERANCE, 0 }, // +7.1500E+01=F( +0.5586, +7)
+{389, 1116812077u, 7u, 1058091821u, 0, FREXPF_TOLERANCE, 0 }, // +7.2600E+01=F( +0.5672, +7)
+{390, 1116956256u, 7u, 1058236000u, 0, FREXPF_TOLERANCE, 0 }, // +7.3700E+01=F( +0.5758, +7)
+{391, 1117100435u, 7u, 1058380179u, 0, FREXPF_TOLERANCE, 0 }, // +7.4800E+01=F( +0.5844, +7)
+{392, 1117244614u, 7u, 1058524358u, 0, FREXPF_TOLERANCE, 0 }, // +7.5900E+01=F(  +0.593, +7)
+{393, 1117388793u, 7u, 1058668537u, 0, FREXPF_TOLERANCE, 0 }, // +7.7000E+01=F( +0.6016, +7)
+{394, 1117532972u, 7u, 1058812716u, 0, FREXPF_TOLERANCE, 0 }, // +7.8100E+01=F( +0.6102, +7)
+{395, 1117677151u, 7u, 1058956895u, 0, FREXPF_TOLERANCE, 0 }, // +7.9200E+01=F( +0.6187, +7)
+{396, 1117821330u, 7u, 1059101074u, 0, FREXPF_TOLERANCE, 0 }, // +8.0300E+01=F( +0.6273, +7)
+{397, 1117965509u, 7u, 1059245253u, 0, FREXPF_TOLERANCE, 0 }, // +8.1400E+01=F( +0.6359, +7)
+{398, 1118109688u, 7u, 1059389432u, 0, FREXPF_TOLERANCE, 0 }, // +8.2500E+01=F( +0.6445, +7)
+{399, 1118253867u, 7u, 1059533611u, 0, FREXPF_TOLERANCE, 0 }, // +8.3600E+01=F( +0.6531, +7)
+{400, 1118398046u, 7u, 1059677790u, 0, FREXPF_TOLERANCE, 0 }, // +8.4700E+01=F( +0.6617, +7)
+{401, 1118542225u, 7u, 1059821969u, 0, FREXPF_TOLERANCE, 0 }, // +8.5800E+01=F( +0.6703, +7)
+{402, 1118686404u, 7u, 1059966148u, 0, FREXPF_TOLERANCE, 0 }, // +8.6900E+01=F( +0.6789, +7)
+{403, 1118830583u, 7u, 1060110327u, 0, FREXPF_TOLERANCE, 0 }, // +8.8000E+01=F( +0.6875, +7)
+{404, 1118974762u, 7u, 1060254506u, 0, FREXPF_TOLERANCE, 0 }, // +8.9100E+01=F( +0.6961, +7)
+{405, 1119118941u, 7u, 1060398685u, 0, FREXPF_TOLERANCE, 0 }, // +9.0200E+01=F( +0.7047, +7)
+{406, 1119263120u, 7u, 1060542864u, 0, FREXPF_TOLERANCE, 0 }, // +9.1300E+01=F( +0.7133, +7)
+{407, 1119407299u, 7u, 1060687043u, 0, FREXPF_TOLERANCE, 0 }, // +9.2400E+01=F( +0.7219, +7)
+{408, 1119551478u, 7u, 1060831222u, 0, FREXPF_TOLERANCE, 0 }, // +9.3500E+01=F( +0.7305, +7)
+{409, 1119695657u, 7u, 1060975401u, 0, FREXPF_TOLERANCE, 0 }, // +9.4600E+01=F( +0.7391, +7)
+{410, 1119839836u, 7u, 1061119580u, 0, FREXPF_TOLERANCE, 0 }, // +9.5700E+01=F( +0.7477, +7)
+{411, 1119984015u, 7u, 1061263759u, 0, FREXPF_TOLERANCE, 0 }, // +9.6800E+01=F( +0.7562, +7)
+{412, 1120128194u, 7u, 1061407938u, 0, FREXPF_TOLERANCE, 0 }, // +9.7900E+01=F( +0.7648, +7)
+{413, 1120272373u, 7u, 1061552117u, 0, FREXPF_TOLERANCE, 0 }, // +9.9000E+01=F( +0.7734, +7)
+{414, 1120416552u, 7u, 1061696296u, 0, FREXPF_TOLERANCE, 0 }, // +1.0010E+02=F(  +0.782, +7)
+{415, 1120560731u, 7u, 1061840475u, 0, FREXPF_TOLERANCE, 0 }, // +1.0120E+02=F( +0.7906, +7)
+{416, 1120704910u, 7u, 1061984654u, 0, FREXPF_TOLERANCE, 0 }, // +1.0230E+02=F( +0.7992, +7)
+{417, 1120849089u, 7u, 1062128833u, 0, FREXPF_TOLERANCE, 0 }, // +1.0340E+02=F( +0.8078, +7)
+{418, 1120993268u, 7u, 1062273012u, 0, FREXPF_TOLERANCE, 0 }, // +1.0450E+02=F( +0.8164, +7)
+{419, 1121137447u, 7u, 1062417191u, 0, FREXPF_TOLERANCE, 0 }, // +1.0560E+02=F(  +0.825, +7)
+{420, 1121281626u, 7u, 1062561370u, 0, FREXPF_TOLERANCE, 0 }, // +1.0670E+02=F( +0.8336, +7)
+{421, 1121425805u, 7u, 1062705549u, 0, FREXPF_TOLERANCE, 0 }, // +1.0780E+02=F( +0.8422, +7)
+{422, 1121569984u, 7u, 1062849728u, 0, FREXPF_TOLERANCE, 0 }, // +1.0890E+02=F( +0.8508, +7)
+{423, 1121714163u, 7u, 1062993907u, 0, FREXPF_TOLERANCE, 0 }, // +1.1000E+02=F( +0.8594, +7)
+{424, 1121845248u, 7u, 1063124992u, 0, FREXPF_TOLERANCE, 0 }, // +1.1100E+02=F( +0.8672, +7)
+{425, 1130233856u, 8u, 1063124992u, 0, FREXPF_TOLERANCE, 0 }, // +2.2200E+02=F( +0.8672, +8)
+{426, 1134985216u, 9u, 1059487744u, 0, FREXPF_TOLERANCE, 0 }, // +3.3300E+02=F( +0.6504, +9)
+{427, 1138622464u, 9u, 1063124992u, 0, FREXPF_TOLERANCE, 0 }, // +4.4400E+02=F( +0.8672, +9)
+{428, 1141555200u, 10u, 1057669120u, 0, FREXPF_TOLERANCE, 0 }, // +5.5500E+02=F(  +0.542, +10)
+{429, 1143373824u, 10u, 1059487744u, 0, FREXPF_TOLERANCE, 0 }, // +6.6600E+02=F( +0.6504, +10)
+{430, 1145192448u, 10u, 1061306368u, 0, FREXPF_TOLERANCE, 0 }, // +7.7700E+02=F( +0.7588, +10)
+{431, 1147011072u, 10u, 1063124992u, 0, FREXPF_TOLERANCE, 0 }, // +8.8800E+02=F( +0.8672, +10)
+{432, 1148829696u, 10u, 1064943616u, 0, FREXPF_TOLERANCE, 0 }, // +9.9900E+02=F( +0.9756, +10)
+{433, 1149943808u, 11u, 1057669120u, 0, FREXPF_TOLERANCE, 0 }, // +1.1100E+03=F(  +0.542, +11)
+{434, 1149952000u, 11u, 1057677312u, 0, FREXPF_TOLERANCE, 0 }, // +1.1110E+03=F( +0.5425, +11)
+{435, 1344628517u, 34u, 1059415845u, 0, FREXPF_TOLERANCE, 0 }, // +1.1100E+10=F( +0.6461, +34)
+{436, 1353017124u, 35u, 1059415844u, 0, FREXPF_TOLERANCE, 0 }, // +2.2200E+10=F( +0.6461, +35)
+{437, 1358437046u, 35u, 1064835766u, 0, FREXPF_TOLERANCE, 0 }, // +3.3300E+10=F( +0.9692, +35)
+{438, 1361405732u, 36u, 1059415844u, 0, FREXPF_TOLERANCE, 0 }, // +4.4400E+10=F( +0.6461, +36)
+{439, 1364115693u, 36u, 1062125805u, 0, FREXPF_TOLERANCE, 0 }, // +5.5500E+10=F( +0.8076, +36)
+{440, 1366825654u, 36u, 1064835766u, 0, FREXPF_TOLERANCE, 0 }, // +6.6600E+10=F( +0.9692, +36)
+{441, 1368439359u, 37u, 1058060863u, 0, FREXPF_TOLERANCE, 0 }, // +7.7700E+10=F( +0.5653, +37)
+{442, 1369794339u, 37u, 1059415843u, 0, FREXPF_TOLERANCE, 0 }, // +8.8800E+10=F( +0.6461, +37)
+{443, 1371149319u, 37u, 1060770823u, 0, FREXPF_TOLERANCE, 0 }, // +9.9900E+10=F( +0.7269, +37)
+{444, 1372504299u, 37u, 1062125803u, 0, FREXPF_TOLERANCE, 0 }, // +1.1100E+11=F( +0.8076, +37)
+{445, 0u, 0u, 0u, 0, FREXPF_TOLERANCE, 0 }, // +0.0000E+00=F(      +0, +0)
+{446, 8388608u, 4294967171u, 1056964608u, 0, FREXPF_TOLERANCE, 0 }, // +1.1755E-38=F(    +0.5, -125)
+{447, 2139095039u, 128u, 1065353215u, 0, FREXPF_TOLERANCE, 0 }, // +3.4028E+38=F(      +1, +128)
+{448, 2143289344u, 0u, 2143289344u, 0, FREXPF_TOLERANCE, 0 }, // +NAN       =F(    +nan, +0)
+{449, 2139095040u, 0u, 2139095040u, 0, FREXPF_TOLERANCE, 0 }, // +INF       =F(    +inf, +0)
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_FREXPF_H multiple inclusion protection
+
+// EOF frexpf.h
diff --git a/packages/language/c/libm/current/tests/vectors/gammaf.c b/packages/language/c/libm/current/tests/vectors/gammaf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/gammaf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      gammaf.c
+//
+//      Test of gammaf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/gammaf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(gammaf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &gammaf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &gammaf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("gammaf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("gammaf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library gammaf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "gammaf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF gammaf.c
diff --git a/packages/language/c/libm/current/tests/vectors/gammaf.h b/packages/language/c/libm/current/tests/vectors/gammaf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/gammaf.h
@@ -0,0 +1,363 @@
+#ifndef CYGONCE_LIBM_GAMMA_H
+#define CYGONCE_LIBM_GAMMA_H
+//===========================================================================
+//
+//      gammaf.h
+//
+//      Test vectors for testing of gammaf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/gammaf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define GAMMA_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t gammaf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 2147508200u, 3182352542u, 0, GAMMA_TOLERANCE, 0},
+{1, 3214430700u, 2147508200u, 3181956062u, 0, GAMMA_TOLERANCE, 0},
+{2, 3214346813u, 2147508200u, 3181542364u, 0, GAMMA_TOLERANCE, 0},
+{3, 3214262927u, 2147508200u, 3181111256u, 0, GAMMA_TOLERANCE, 0},
+{4, 3214179041u, 2147508200u, 3180662520u, 0, GAMMA_TOLERANCE, 0},
+{5, 3214095155u, 2147508200u, 3180195945u, 0, GAMMA_TOLERANCE, 0},
+{6, 3214011269u, 2147508200u, 3179711309u, 0, GAMMA_TOLERANCE, 0},
+{7, 3213927383u, 2147508200u, 3179134344u, 0, GAMMA_TOLERANCE, 0},
+{8, 3213843497u, 2147508200u, 3178091474u, 0, GAMMA_TOLERANCE, 0},
+{9, 3213759611u, 2147508200u, 3177011103u, 0, GAMMA_TOLERANCE, 0},
+{10, 3213675725u, 2147508200u, 3175892750u, 0, GAMMA_TOLERANCE, 0},
+{11, 3213591839u, 2147508200u, 3174735922u, 0, GAMMA_TOLERANCE, 0},
+{12, 3213507953u, 2147508200u, 3173540112u, 0, GAMMA_TOLERANCE, 0},
+{13, 3213424067u, 2147508200u, 3172304802u, 0, GAMMA_TOLERANCE, 0},
+{14, 3213340180u, 2147508200u, 3171029445u, 0, GAMMA_TOLERANCE, 0},
+{15, 3213256294u, 2147508200u, 3168533229u, 0, GAMMA_TOLERANCE, 0},
+{16, 3213172408u, 2147508200u, 3165819122u, 0, GAMMA_TOLERANCE, 0},
+{17, 3213088522u, 2147508200u, 3163021599u, 0, GAMMA_TOLERANCE, 0},
+{18, 3213004636u, 2147508200u, 3157773750u, 0, GAMMA_TOLERANCE, 0},
+{19, 3212920750u, 2147508200u, 3149559224u, 0, GAMMA_TOLERANCE, 0},
+{20, 3212836864u, 2147508200u, 0u, 0, GAMMA_TOLERANCE, 0},
+{21, 3212669092u, 2147508200u, 1002428834u, 0, GAMMA_TOLERANCE, 0},
+{22, 3212501320u, 2147508200u, 1010996688u, 0, GAMMA_TOLERANCE, 0},
+{23, 3212333548u, 2147508200u, 1016332991u, 0, GAMMA_TOLERANCE, 0},
+{24, 3212165775u, 2147508200u, 1019749225u, 0, GAMMA_TOLERANCE, 0},
+{25, 3211998003u, 2147508200u, 1023259210u, 0, GAMMA_TOLERANCE, 0},
+{26, 3211830231u, 2147508200u, 1025137303u, 0, GAMMA_TOLERANCE, 0},
+{27, 3211662459u, 2147508200u, 1026988282u, 0, GAMMA_TOLERANCE, 0},
+{28, 3211494687u, 2147508200u, 1028888405u, 0, GAMMA_TOLERANCE, 0},
+{29, 3211326915u, 2147508200u, 1030838469u, 0, GAMMA_TOLERANCE, 0},
+{30, 3211159142u, 2147508200u, 1032319047u, 0, GAMMA_TOLERANCE, 0},
+{31, 3210991370u, 2147508200u, 1033345266u, 0, GAMMA_TOLERANCE, 0},
+{32, 3210823598u, 2147508200u, 1034397726u, 0, GAMMA_TOLERANCE, 0},
+{33, 3210655826u, 2147508200u, 1035476878u, 0, GAMMA_TOLERANCE, 0},
+{34, 3210488054u, 2147508200u, 1036583185u, 0, GAMMA_TOLERANCE, 0},
+{35, 3210320282u, 2147508200u, 1037717128u, 0, GAMMA_TOLERANCE, 0},
+{36, 3210152509u, 2147508200u, 1038879207u, 0, GAMMA_TOLERANCE, 0},
+{37, 3209984737u, 2147508200u, 1040069921u, 0, GAMMA_TOLERANCE, 0},
+{38, 3209816965u, 2147508200u, 1040738598u, 0, GAMMA_TOLERANCE, 0},
+{39, 3209649193u, 2147508200u, 1041363397u, 0, GAMMA_TOLERANCE, 0},
+{40, 3209481421u, 2147508200u, 1042003336u, 0, GAMMA_TOLERANCE, 0},
+{41, 3209313649u, 2147508200u, 1042658707u, 0, GAMMA_TOLERANCE, 0},
+{42, 3209145876u, 2147508200u, 1043329818u, 0, GAMMA_TOLERANCE, 0},
+{43, 3208978104u, 2147508200u, 1044016973u, 0, GAMMA_TOLERANCE, 0},
+{44, 3208810332u, 2147508200u, 1044720500u, 0, GAMMA_TOLERANCE, 0},
+{45, 3208642560u, 2147508200u, 1045440738u, 0, GAMMA_TOLERANCE, 0},
+{46, 3208474788u, 2147508200u, 1046178035u, 0, GAMMA_TOLERANCE, 0},
+{47, 3208307016u, 2147508200u, 1046932755u, 0, GAMMA_TOLERANCE, 0},
+{48, 3208139244u, 2147508200u, 1047705272u, 0, GAMMA_TOLERANCE, 0},
+{49, 3207971471u, 2147508200u, 1048495986u, 0, GAMMA_TOLERANCE, 0},
+{50, 3207803699u, 2147508200u, 1048940645u, 0, GAMMA_TOLERANCE, 0},
+{51, 3207635927u, 2147508200u, 1049354808u, 0, GAMMA_TOLERANCE, 0},
+{52, 3207468155u, 2147508200u, 1049778702u, 0, GAMMA_TOLERANCE, 0},
+{53, 3207300383u, 2147508200u, 1050212555u, 0, GAMMA_TOLERANCE, 0},
+{54, 3207132611u, 2147508200u, 1050656608u, 0, GAMMA_TOLERANCE, 0},
+{55, 3206964838u, 2147508200u, 1051111112u, 0, GAMMA_TOLERANCE, 0},
+{56, 3206797066u, 2147508200u, 1051576324u, 0, GAMMA_TOLERANCE, 0},
+{57, 3206629294u, 2147508200u, 1052052518u, 0, GAMMA_TOLERANCE, 0},
+{58, 3206461522u, 2147508200u, 1052539978u, 0, GAMMA_TOLERANCE, 0},
+{59, 3206293750u, 2147508200u, 1053039002u, 0, GAMMA_TOLERANCE, 0},
+{60, 3206125978u, 2147508200u, 1053549901u, 0, GAMMA_TOLERANCE, 0},
+{61, 3205958205u, 2147508200u, 1054073007u, 0, GAMMA_TOLERANCE, 0},
+{62, 3205790433u, 2147508200u, 1054608655u, 0, GAMMA_TOLERANCE, 0},
+{63, 3205622661u, 2147508200u, 1055157205u, 0, GAMMA_TOLERANCE, 0},
+{64, 3205454889u, 2147508200u, 1055719041u, 0, GAMMA_TOLERANCE, 0},
+{65, 3205287117u, 2147508200u, 1056294554u, 0, GAMMA_TOLERANCE, 0},
+{66, 3205119345u, 2147508200u, 1056884165u, 0, GAMMA_TOLERANCE, 0},
+{67, 3204951572u, 2147508200u, 1057226463u, 0, GAMMA_TOLERANCE, 0},
+{68, 3204783800u, 2147508200u, 1057536039u, 0, GAMMA_TOLERANCE, 0},
+{69, 3204616028u, 2147508200u, 1057853361u, 0, GAMMA_TOLERANCE, 0},
+{70, 3204448256u, 2147508200u, 1058178690u, 0, GAMMA_TOLERANCE, 0},
+{71, 3204112712u, 2147508200u, 1058512300u, 0, GAMMA_TOLERANCE, 0},
+{72, 3203777167u, 2147508200u, 1058854482u, 0, GAMMA_TOLERANCE, 0},
+{73, 3203441623u, 2147508200u, 1059205542u, 0, GAMMA_TOLERANCE, 0},
+{74, 3203106079u, 2147508200u, 1059565811u, 0, GAMMA_TOLERANCE, 0},
+{75, 3202770534u, 2147508200u, 1059935636u, 0, GAMMA_TOLERANCE, 0},
+{76, 3202434990u, 2147508200u, 1060315390u, 0, GAMMA_TOLERANCE, 0},
+{77, 3202099446u, 2147508200u, 1060705468u, 0, GAMMA_TOLERANCE, 0},
+{78, 3201763901u, 2147508200u, 1061106295u, 0, GAMMA_TOLERANCE, 0},
+{79, 3201428357u, 2147508200u, 1061518321u, 0, GAMMA_TOLERANCE, 0},
+{80, 3201092813u, 2147508200u, 1061942035u, 0, GAMMA_TOLERANCE, 0},
+{81, 3200757268u, 2147508200u, 1062377960u, 0, GAMMA_TOLERANCE, 0},
+{82, 3200421724u, 2147508200u, 1062826654u, 0, GAMMA_TOLERANCE, 0},
+{83, 3200086180u, 2147508200u, 1063288726u, 0, GAMMA_TOLERANCE, 0},
+{84, 3199750636u, 2147508200u, 1063764827u, 0, GAMMA_TOLERANCE, 0},
+{85, 3199415091u, 2147508200u, 1064255670u, 0, GAMMA_TOLERANCE, 0},
+{86, 3199079547u, 2147508200u, 1064762021u, 0, GAMMA_TOLERANCE, 0},
+{87, 3198744003u, 2147508200u, 1065284717u, 0, GAMMA_TOLERANCE, 0},
+{88, 3198408458u, 2147508200u, 1065588944u, 0, GAMMA_TOLERANCE, 0},
+{89, 3198072914u, 2147508200u, 1065868048u, 0, GAMMA_TOLERANCE, 0},
+{90, 3197737370u, 2147508200u, 1066156828u, 0, GAMMA_TOLERANCE, 0},
+{91, 3197401825u, 2147508200u, 1066455885u, 0, GAMMA_TOLERANCE, 0},
+{92, 3197066281u, 2147508200u, 1066765884u, 0, GAMMA_TOLERANCE, 0},
+{93, 3196730737u, 2147508200u, 1067087562u, 0, GAMMA_TOLERANCE, 0},
+{94, 3196395192u, 2147508200u, 1067421737u, 0, GAMMA_TOLERANCE, 0},
+{95, 3196059648u, 2147508200u, 1067769324u, 0, GAMMA_TOLERANCE, 0},
+{96, 3195388559u, 2147508200u, 1068131348u, 0, GAMMA_TOLERANCE, 0},
+{97, 3194717471u, 2147508200u, 1068508963u, 0, GAMMA_TOLERANCE, 0},
+{98, 3194046382u, 2147508200u, 1068903479u, 0, GAMMA_TOLERANCE, 0},
+{99, 3193375293u, 2147508200u, 1069316383u, 0, GAMMA_TOLERANCE, 0},
+{100, 3192704205u, 2147508200u, 1069749382u, 0, GAMMA_TOLERANCE, 0},
+{101, 3192033116u, 2147508200u, 1070204441u, 0, GAMMA_TOLERANCE, 0},
+{102, 3191362028u, 2147508200u, 1070683845u, 0, GAMMA_TOLERANCE, 0},
+{103, 3190690939u, 2147508200u, 1071190269u, 0, GAMMA_TOLERANCE, 0},
+{104, 3190019850u, 2147508200u, 1071726872u, 0, GAMMA_TOLERANCE, 0},
+{105, 3189348762u, 2147508200u, 1072297421u, 0, GAMMA_TOLERANCE, 0},
+{106, 3188677673u, 2147508200u, 1072906465u, 0, GAMMA_TOLERANCE, 0},
+{107, 3188006584u, 2147508200u, 1073559562u, 0, GAMMA_TOLERANCE, 0},
+{108, 3186999951u, 2147508200u, 1074002711u, 0, GAMMA_TOLERANCE, 0},
+{109, 3185657774u, 2147508200u, 1074384544u, 0, GAMMA_TOLERANCE, 0},
+{110, 3184315597u, 2147508200u, 1074801778u, 0, GAMMA_TOLERANCE, 0},
+{111, 3182973420u, 2147508200u, 1075261767u, 0, GAMMA_TOLERANCE, 0},
+{112, 3181631242u, 2147508200u, 1075774470u, 0, GAMMA_TOLERANCE, 0},
+{113, 3180289065u, 2147508200u, 1076353843u, 0, GAMMA_TOLERANCE, 0},
+{114, 3178611343u, 2147508200u, 1077020325u, 0, GAMMA_TOLERANCE, 0},
+{115, 3175926989u, 2147508200u, 1077805598u, 0, GAMMA_TOLERANCE, 0},
+{116, 3173242634u, 2147508200u, 1078762734u, 0, GAMMA_TOLERANCE, 0},
+{117, 3170222735u, 2147508200u, 1079991216u, 0, GAMMA_TOLERANCE, 0},
+{118, 3164854026u, 2147508200u, 1081714376u, 0, GAMMA_TOLERANCE, 0},
+{119, 3156465418u, 2147508200u, 1083387633u, 0, GAMMA_TOLERANCE, 0},
+{120, 646742016u, 2147508200u, 1107968441u, 0, GAMMA_TOLERANCE, 0},
+{121, 1008981770u, 2147508200u, 1083387633u, 0, GAMMA_TOLERANCE, 0},
+{122, 1017370378u, 2147508200u, 1081714376u, 0, GAMMA_TOLERANCE, 0},
+{123, 1022739087u, 2147508200u, 1079991216u, 0, GAMMA_TOLERANCE, 0},
+{124, 1025758986u, 2147508200u, 1078762734u, 0, GAMMA_TOLERANCE, 0},
+{125, 1028443341u, 2147508200u, 1077805598u, 0, GAMMA_TOLERANCE, 0},
+{126, 1031127695u, 2147508200u, 1077020325u, 0, GAMMA_TOLERANCE, 0},
+{127, 1032805417u, 2147508200u, 1076353843u, 0, GAMMA_TOLERANCE, 0},
+{128, 1034147594u, 2147508200u, 1075774470u, 0, GAMMA_TOLERANCE, 0},
+{129, 1035489772u, 2147508200u, 1075261767u, 0, GAMMA_TOLERANCE, 0},
+{130, 1036831949u, 2147508200u, 1074801778u, 0, GAMMA_TOLERANCE, 0},
+{131, 1038174126u, 2147508200u, 1074384544u, 0, GAMMA_TOLERANCE, 0},
+{132, 1039516303u, 2147508200u, 1074002711u, 0, GAMMA_TOLERANCE, 0},
+{133, 1040522936u, 2147508200u, 1073559562u, 0, GAMMA_TOLERANCE, 0},
+{134, 1041194025u, 2147508200u, 1072906465u, 0, GAMMA_TOLERANCE, 0},
+{135, 1041865114u, 2147508200u, 1072297421u, 0, GAMMA_TOLERANCE, 0},
+{136, 1042536202u, 2147508200u, 1071726872u, 0, GAMMA_TOLERANCE, 0},
+{137, 1043207291u, 2147508200u, 1071190269u, 0, GAMMA_TOLERANCE, 0},
+{138, 1043878380u, 2147508200u, 1070683845u, 0, GAMMA_TOLERANCE, 0},
+{139, 1044549468u, 2147508200u, 1070204441u, 0, GAMMA_TOLERANCE, 0},
+{140, 1045220557u, 2147508200u, 1069749382u, 0, GAMMA_TOLERANCE, 0},
+{141, 1045891645u, 2147508200u, 1069316383u, 0, GAMMA_TOLERANCE, 0},
+{142, 1046562734u, 2147508200u, 1068903479u, 0, GAMMA_TOLERANCE, 0},
+{143, 1047233823u, 2147508200u, 1068508963u, 0, GAMMA_TOLERANCE, 0},
+{144, 1047904911u, 2147508200u, 1068131348u, 0, GAMMA_TOLERANCE, 0},
+{145, 1048576000u, 2147508200u, 1067769324u, 0, GAMMA_TOLERANCE, 0},
+{146, 1048911544u, 2147508200u, 1067421737u, 0, GAMMA_TOLERANCE, 0},
+{147, 1049247089u, 2147508200u, 1067087562u, 0, GAMMA_TOLERANCE, 0},
+{148, 1049582633u, 2147508200u, 1066765884u, 0, GAMMA_TOLERANCE, 0},
+{149, 1049918177u, 2147508200u, 1066455885u, 0, GAMMA_TOLERANCE, 0},
+{150, 1050253722u, 2147508200u, 1066156828u, 0, GAMMA_TOLERANCE, 0},
+{151, 1050589266u, 2147508200u, 1065868048u, 0, GAMMA_TOLERANCE, 0},
+{152, 1050924810u, 2147508200u, 1065588944u, 0, GAMMA_TOLERANCE, 0},
+{153, 1051260355u, 2147508200u, 1065284717u, 0, GAMMA_TOLERANCE, 0},
+{154, 1051595899u, 2147508200u, 1064762021u, 0, GAMMA_TOLERANCE, 0},
+{155, 1051931443u, 2147508200u, 1064255670u, 0, GAMMA_TOLERANCE, 0},
+{156, 1052266988u, 2147508200u, 1063764827u, 0, GAMMA_TOLERANCE, 0},
+{157, 1052602532u, 2147508200u, 1063288726u, 0, GAMMA_TOLERANCE, 0},
+{158, 1052938076u, 2147508200u, 1062826654u, 0, GAMMA_TOLERANCE, 0},
+{159, 1053273620u, 2147508200u, 1062377960u, 0, GAMMA_TOLERANCE, 0},
+{160, 1053609165u, 2147508200u, 1061942035u, 0, GAMMA_TOLERANCE, 0},
+{161, 1053944709u, 2147508200u, 1061518321u, 0, GAMMA_TOLERANCE, 0},
+{162, 1054280253u, 2147508200u, 1061106295u, 0, GAMMA_TOLERANCE, 0},
+{163, 1054615798u, 2147508200u, 1060705468u, 0, GAMMA_TOLERANCE, 0},
+{164, 1054951342u, 2147508200u, 1060315390u, 0, GAMMA_TOLERANCE, 0},
+{165, 1055286886u, 2147508200u, 1059935636u, 0, GAMMA_TOLERANCE, 0},
+{166, 1055622431u, 2147508200u, 1059565811u, 0, GAMMA_TOLERANCE, 0},
+{167, 1055957975u, 2147508200u, 1059205542u, 0, GAMMA_TOLERANCE, 0},
+{168, 1056293519u, 2147508200u, 1058854482u, 0, GAMMA_TOLERANCE, 0},
+{169, 1056629064u, 2147508200u, 1058512300u, 0, GAMMA_TOLERANCE, 0},
+{170, 1056964608u, 2147508200u, 1058178690u, 0, GAMMA_TOLERANCE, 0},
+{171, 1057132380u, 2147508200u, 1057853361u, 0, GAMMA_TOLERANCE, 0},
+{172, 1057300152u, 2147508200u, 1057536039u, 0, GAMMA_TOLERANCE, 0},
+{173, 1057467924u, 2147508200u, 1057226463u, 0, GAMMA_TOLERANCE, 0},
+{174, 1057635697u, 2147508200u, 1056884165u, 0, GAMMA_TOLERANCE, 0},
+{175, 1057803469u, 2147508200u, 1056294554u, 0, GAMMA_TOLERANCE, 0},
+{176, 1057971241u, 2147508200u, 1055719041u, 0, GAMMA_TOLERANCE, 0},
+{177, 1058139013u, 2147508200u, 1055157205u, 0, GAMMA_TOLERANCE, 0},
+{178, 1058306785u, 2147508200u, 1054608655u, 0, GAMMA_TOLERANCE, 0},
+{179, 1058474557u, 2147508200u, 1054073007u, 0, GAMMA_TOLERANCE, 0},
+{180, 1058642330u, 2147508200u, 1053549901u, 0, GAMMA_TOLERANCE, 0},
+{181, 1058810102u, 2147508200u, 1053039002u, 0, GAMMA_TOLERANCE, 0},
+{182, 1058977874u, 2147508200u, 1052539978u, 0, GAMMA_TOLERANCE, 0},
+{183, 1059145646u, 2147508200u, 1052052518u, 0, GAMMA_TOLERANCE, 0},
+{184, 1059313418u, 2147508200u, 1051576324u, 0, GAMMA_TOLERANCE, 0},
+{185, 1059481190u, 2147508200u, 1051111112u, 0, GAMMA_TOLERANCE, 0},
+{186, 1059648963u, 2147508200u, 1050656608u, 0, GAMMA_TOLERANCE, 0},
+{187, 1059816735u, 2147508200u, 1050212555u, 0, GAMMA_TOLERANCE, 0},
+{188, 1059984507u, 2147508200u, 1049778702u, 0, GAMMA_TOLERANCE, 0},
+{189, 1060152279u, 2147508200u, 1049354808u, 0, GAMMA_TOLERANCE, 0},
+{190, 1060320051u, 2147508200u, 1048940645u, 0, GAMMA_TOLERANCE, 0},
+{191, 1060487823u, 2147508200u, 1048495986u, 0, GAMMA_TOLERANCE, 0},
+{192, 1060655596u, 2147508200u, 1047705272u, 0, GAMMA_TOLERANCE, 0},
+{193, 1060823368u, 2147508200u, 1046932755u, 0, GAMMA_TOLERANCE, 0},
+{194, 1060991140u, 2147508200u, 1046178035u, 0, GAMMA_TOLERANCE, 0},
+{195, 1061158912u, 2147508200u, 1045440738u, 0, GAMMA_TOLERANCE, 0},
+{196, 1061326684u, 2147508200u, 1044720500u, 0, GAMMA_TOLERANCE, 0},
+{197, 1061494456u, 2147508200u, 1044016973u, 0, GAMMA_TOLERANCE, 0},
+{198, 1061662228u, 2147508200u, 1043329818u, 0, GAMMA_TOLERANCE, 0},
+{199, 1061830001u, 2147508200u, 1042658707u, 0, GAMMA_TOLERANCE, 0},
+{200, 1061997773u, 2147508200u, 1042003336u, 0, GAMMA_TOLERANCE, 0},
+{201, 1062165545u, 2147508200u, 1041363397u, 0, GAMMA_TOLERANCE, 0},
+{202, 1062333317u, 2147508200u, 1040738598u, 0, GAMMA_TOLERANCE, 0},
+{203, 1062501089u, 2147508200u, 1040069921u, 0, GAMMA_TOLERANCE, 0},
+{204, 1062668861u, 2147508200u, 1038879207u, 0, GAMMA_TOLERANCE, 0},
+{205, 1062836634u, 2147508200u, 1037717128u, 0, GAMMA_TOLERANCE, 0},
+{206, 1063004406u, 2147508200u, 1036583185u, 0, GAMMA_TOLERANCE, 0},
+{207, 1063172178u, 2147508200u, 1035476878u, 0, GAMMA_TOLERANCE, 0},
+{208, 1063339950u, 2147508200u, 1034397726u, 0, GAMMA_TOLERANCE, 0},
+{209, 1063507722u, 2147508200u, 1033345266u, 0, GAMMA_TOLERANCE, 0},
+{210, 1063675494u, 2147508200u, 1032319047u, 0, GAMMA_TOLERANCE, 0},
+{211, 1063843267u, 2147508200u, 1030838469u, 0, GAMMA_TOLERANCE, 0},
+{212, 1064011039u, 2147508200u, 1028888405u, 0, GAMMA_TOLERANCE, 0},
+{213, 1064178811u, 2147508200u, 1026988282u, 0, GAMMA_TOLERANCE, 0},
+{214, 1064346583u, 2147508200u, 1025137303u, 0, GAMMA_TOLERANCE, 0},
+{215, 1064514355u, 2147508200u, 1023259210u, 0, GAMMA_TOLERANCE, 0},
+{216, 1064682127u, 2147508200u, 1019749225u, 0, GAMMA_TOLERANCE, 0},
+{217, 1064849900u, 2147508200u, 1016332991u, 0, GAMMA_TOLERANCE, 0},
+{218, 1065017672u, 2147508200u, 1010996688u, 0, GAMMA_TOLERANCE, 0},
+{219, 1065185444u, 2147508200u, 1002428834u, 0, GAMMA_TOLERANCE, 0},
+{220, 1065353216u, 2147508200u, 0u, 0, GAMMA_TOLERANCE, 0},
+{221, 1065437102u, 2147508200u, 3149559224u, 0, GAMMA_TOLERANCE, 0},
+{222, 1065520988u, 2147508200u, 3157773750u, 0, GAMMA_TOLERANCE, 0},
+{223, 1065604874u, 2147508200u, 3163021599u, 0, GAMMA_TOLERANCE, 0},
+{224, 1065688760u, 2147508200u, 3165819122u, 0, GAMMA_TOLERANCE, 0},
+{225, 1065772646u, 2147508200u, 3168533229u, 0, GAMMA_TOLERANCE, 0},
+{226, 1065856532u, 2147508200u, 3171029445u, 0, GAMMA_TOLERANCE, 0},
+{227, 1065940419u, 2147508200u, 3172304802u, 0, GAMMA_TOLERANCE, 0},
+{228, 1066024305u, 2147508200u, 3173540112u, 0, GAMMA_TOLERANCE, 0},
+{229, 1066108191u, 2147508200u, 3174735922u, 0, GAMMA_TOLERANCE, 0},
+{230, 1066192077u, 2147508200u, 3175892750u, 0, GAMMA_TOLERANCE, 0},
+{231, 1066275963u, 2147508200u, 3177011103u, 0, GAMMA_TOLERANCE, 0},
+{232, 1066359849u, 2147508200u, 3178091474u, 0, GAMMA_TOLERANCE, 0},
+{233, 1066443735u, 2147508200u, 3179134344u, 0, GAMMA_TOLERANCE, 0},
+{234, 1066527621u, 2147508200u, 3179711309u, 0, GAMMA_TOLERANCE, 0},
+{235, 1066611507u, 2147508200u, 3180195945u, 0, GAMMA_TOLERANCE, 0},
+{236, 1066695393u, 2147508200u, 3180662520u, 0, GAMMA_TOLERANCE, 0},
+{237, 1066779279u, 2147508200u, 3181111256u, 0, GAMMA_TOLERANCE, 0},
+{238, 1066863165u, 2147508200u, 3181542364u, 0, GAMMA_TOLERANCE, 0},
+{239, 1066947052u, 2147508200u, 3181956062u, 0, GAMMA_TOLERANCE, 0},
+{240, 3234402267u, 2147508200u, 1084810150u, 0, GAMMA_TOLERANCE, 0},
+{241, 3231108068u, 2147508200u, 1076905300u, 0, GAMMA_TOLERANCE, 0},
+{242, 3226013659u, 2147508200u, 1062462412u, 0, GAMMA_TOLERANCE, 0},
+{243, 3217625051u, 2147508200u, 3186450168u, 0, GAMMA_TOLERANCE, 0},
+{244, 0u, 2147508200u, 1115684864u, 0, GAMMA_TOLERANCE, 0},
+{245, 1070141403u, 2147508200u, 3186450168u, 0, GAMMA_TOLERANCE, 0},
+{246, 1078530011u, 2147508200u, 1062462412u, 0, GAMMA_TOLERANCE, 0},
+{247, 1083624420u, 2147508200u, 1076905300u, 0, GAMMA_TOLERANCE, 0},
+{248, 3253731328u, 2147508200u, 1116636059u, 0, GAMMA_TOLERANCE, 0},
+{249, 3252840038u, 2147508200u, 1115888477u, 0, GAMMA_TOLERANCE, 0},
+{250, 3251948749u, 2147508200u, 1114624191u, 0, GAMMA_TOLERANCE, 0},
+{251, 3251057459u, 2147508200u, 1113185337u, 0, GAMMA_TOLERANCE, 0},
+{252, 3250166170u, 2147508200u, 1111777553u, 0, GAMMA_TOLERANCE, 0},
+{253, 3249274880u, 2147508200u, 1110403168u, 0, GAMMA_TOLERANCE, 0},
+{254, 3248383590u, 2147508200u, 1109064891u, 0, GAMMA_TOLERANCE, 0},
+{255, 3247492301u, 2147508200u, 1107765911u, 0, GAMMA_TOLERANCE, 0},
+{256, 3246601011u, 2147508200u, 1105723807u, 0, GAMMA_TOLERANCE, 0},
+{257, 3245028147u, 2147508200u, 1103307493u, 0, GAMMA_TOLERANCE, 0},
+{258, 3243245568u, 2147508200u, 1100998096u, 0, GAMMA_TOLERANCE, 0},
+{259, 3241462989u, 2147508200u, 1098712804u, 0, GAMMA_TOLERANCE, 0},
+{260, 3239680410u, 2147508200u, 1094618617u, 0, GAMMA_TOLERANCE, 0},
+{261, 3237792973u, 2147508200u, 1090859057u, 0, GAMMA_TOLERANCE, 0},
+{262, 3234227814u, 2147508200u, 1084505034u, 0, GAMMA_TOLERANCE, 0},
+{263, 3230662656u, 2147508200u, 1075644933u, 0, GAMMA_TOLERANCE, 0},
+{264, 3224580915u, 2147508200u, 1057244834u, 0, GAMMA_TOLERANCE, 0},
+{265, 3213675725u, 2147508200u, 3175892750u, 0, GAMMA_TOLERANCE, 0},
+{266, 1058642330u, 2147508200u, 1053549901u, 0, GAMMA_TOLERANCE, 0},
+{267, 1075000115u, 2147508200u, 1042146261u, 0, GAMMA_TOLERANCE, 0},
+{268, 1082130432u, 2147508200u, 1071994976u, 0, GAMMA_TOLERANCE, 0},
+{269, 1085695590u, 2147508200u, 1082725955u, 0, GAMMA_TOLERANCE, 0},
+{270, 1089260749u, 2147508200u, 1089135769u, 0, GAMMA_TOLERANCE, 0},
+{271, 1091672474u, 2147508200u, 1093475241u, 0, GAMMA_TOLERANCE, 0},
+{272, 1093455053u, 2147508200u, 1097477367u, 0, GAMMA_TOLERANCE, 0},
+{273, 1095237632u, 2147508200u, 1100341234u, 0, GAMMA_TOLERANCE, 0},
+{274, 1097020211u, 2147508200u, 1102616576u, 0, GAMMA_TOLERANCE, 0},
+{275, 1098802790u, 2147508200u, 1105002754u, 0, GAMMA_TOLERANCE, 0},
+{276, 1099746509u, 2147508200u, 1107391872u, 0, GAMMA_TOLERANCE, 0},
+{277, 1100637798u, 2147508200u, 1108678601u, 0, GAMMA_TOLERANCE, 0},
+{278, 1101529088u, 2147508200u, 1110005676u, 0, GAMMA_TOLERANCE, 0},
+{279, 1102420378u, 2147508200u, 1111369741u, 0, GAMMA_TOLERANCE, 0},
+{280, 1103311667u, 2147508200u, 1112767959u, 0, GAMMA_TOLERANCE, 0},
+{281, 1104202957u, 2147508200u, 1114197898u, 0, GAMMA_TOLERANCE, 0},
+{282, 1105094246u, 2147508200u, 1115657449u, 0, GAMMA_TOLERANCE, 0},
+{283, 1105985536u, 2147508200u, 1116414815u, 0, GAMMA_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_GAMMA_H multiple inclusion protection
+
+// EOF gammaf.h
diff --git a/packages/language/c/libm/current/tests/vectors/hypotf.c b/packages/language/c/libm/current/tests/vectors/hypotf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/hypotf.c
@@ -0,0 +1,58 @@
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_double_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/hypotf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(hypotf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &hypotf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_FLOAT, CYG_LIBM_TEST_VEC_FLOAT,
+                     &hypotf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("hypotf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("hypotf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library hypotf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "hypotf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF log10.c
diff --git a/packages/language/c/libm/current/tests/vectors/hypotf.h b/packages/language/c/libm/current/tests/vectors/hypotf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/hypotf.h
@@ -0,0 +1,310 @@
+#ifndef CYGONCE_LIBM_LOG10_H
+#define CYGONCE_LIBM_LOG10_H
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define HYPOT_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t hypotf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 1077097267u, 1078130363u, 0, HYPOT_TOLERANCE, 0},
+{1, 3214430700u, 1077139210u, 1078152510u, 0, HYPOT_TOLERANCE, 0},
+{2, 3214346813u, 1077181153u, 1078174894u, 0, HYPOT_TOLERANCE, 0},
+{3, 3214262927u, 1077223096u, 1078197514u, 0, HYPOT_TOLERANCE, 0},
+{4, 3214179041u, 1077265039u, 1078220367u, 0, HYPOT_TOLERANCE, 0},
+{5, 3214095155u, 1077306982u, 1078243452u, 0, HYPOT_TOLERANCE, 0},
+{6, 3214011269u, 1077348925u, 1078266769u, 0, HYPOT_TOLERANCE, 0},
+{7, 3213927383u, 1077390868u, 1078290314u, 0, HYPOT_TOLERANCE, 0},
+{8, 3213843497u, 1077432812u, 1078314091u, 0, HYPOT_TOLERANCE, 0},
+{9, 3213759611u, 1077474755u, 1078338093u, 0, HYPOT_TOLERANCE, 0},
+{10, 3213675725u, 1077516698u, 1078362322u, 0, HYPOT_TOLERANCE, 0},
+{11, 3213591839u, 1077558641u, 1078386776u, 0, HYPOT_TOLERANCE, 0},
+{12, 3213507953u, 1077600584u, 1078411453u, 0, HYPOT_TOLERANCE, 0},
+{13, 3213424067u, 1077642527u, 1078436352u, 0, HYPOT_TOLERANCE, 0},
+{14, 3213340180u, 1077684470u, 1078461474u, 0, HYPOT_TOLERANCE, 0},
+{15, 3213256294u, 1077726413u, 1078486814u, 0, HYPOT_TOLERANCE, 0},
+{16, 3213172408u, 1077768356u, 1078512373u, 0, HYPOT_TOLERANCE, 0},
+{17, 3213088522u, 1077810299u, 1078538149u, 0, HYPOT_TOLERANCE, 0},
+{18, 3213004636u, 1077852242u, 1078564142u, 0, HYPOT_TOLERANCE, 0},
+{19, 3212920750u, 1077894185u, 1078590350u, 0, HYPOT_TOLERANCE, 0},
+{20, 3212836864u, 1077936128u, 1078616770u, 0, HYPOT_TOLERANCE, 0},
+{21, 3212669092u, 1077978071u, 1078643403u, 0, HYPOT_TOLERANCE, 0},
+{22, 3212501320u, 1078020014u, 1078670247u, 0, HYPOT_TOLERANCE, 0},
+{23, 3212333548u, 1078061957u, 1078697300u, 0, HYPOT_TOLERANCE, 0},
+{24, 3212165775u, 1078103900u, 1078724562u, 0, HYPOT_TOLERANCE, 0},
+{25, 3211998003u, 1078145843u, 1078752032u, 0, HYPOT_TOLERANCE, 0},
+{26, 3211830231u, 1078187786u, 1078779706u, 0, HYPOT_TOLERANCE, 0},
+{27, 3211662459u, 1078229729u, 1078807586u, 0, HYPOT_TOLERANCE, 0},
+{28, 3211494687u, 1078271672u, 1078835668u, 0, HYPOT_TOLERANCE, 0},
+{29, 3211326915u, 1078313615u, 1078863953u, 0, HYPOT_TOLERANCE, 0},
+{30, 3211159142u, 1078355558u, 1078892439u, 0, HYPOT_TOLERANCE, 0},
+{31, 3210991370u, 1078397501u, 1078921124u, 0, HYPOT_TOLERANCE, 0},
+{32, 3210823598u, 1078439444u, 1078950007u, 0, HYPOT_TOLERANCE, 0},
+{33, 3210655826u, 1078481388u, 1078979089u, 0, HYPOT_TOLERANCE, 0},
+{34, 3210488054u, 1078523331u, 1079008365u, 0, HYPOT_TOLERANCE, 0},
+{35, 3210320282u, 1078565274u, 1079037837u, 0, HYPOT_TOLERANCE, 0},
+{36, 3210152509u, 1078607217u, 1079067501u, 0, HYPOT_TOLERANCE, 0},
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+{255, 3247492301u, 3244399002u, 1102548223u, 0, HYPOT_TOLERANCE, 0},
+{256, 3246601011u, 3242616422u, 1101298483u, 0, HYPOT_TOLERANCE, 0},
+{257, 3245028147u, 3240833843u, 1100051571u, 0, HYPOT_TOLERANCE, 0},
+{258, 3243245568u, 3239051264u, 1098709875u, 0, HYPOT_TOLERANCE, 0},
+{259, 3241462989u, 3236534682u, 1096236800u, 0, HYPOT_TOLERANCE, 0},
+{260, 3239680410u, 3232969523u, 1093784259u, 0, HYPOT_TOLERANCE, 0},
+{261, 3237792973u, 3229194650u, 1091368619u, 0, HYPOT_TOLERANCE, 0},
+{262, 3234227814u, 3222064333u, 1087538470u, 0, HYPOT_TOLERANCE, 0},
+{263, 3230662656u, 3204448256u, 1083237084u, 0, HYPOT_TOLERANCE, 0},
+{264, 3224580915u, 1067030938u, 1078130363u, 0, HYPOT_TOLERANCE, 0},
+{265, 3213675725u, 1077516698u, 1078362322u, 0, HYPOT_TOLERANCE, 0},
+{266, 1058642330u, 1083388723u, 1083470440u, 0, HYPOT_TOLERANCE, 0},
+{267, 1075000115u, 1086953882u, 1087806820u, 0, HYPOT_TOLERANCE, 0},
+{268, 1082130432u, 1090519040u, 1091509181u, 0, HYPOT_TOLERANCE, 0},
+{269, 1085695590u, 1092301619u, 1093927727u, 0, HYPOT_TOLERANCE, 0},
+{270, 1089260749u, 1094084198u, 1096381811u, 0, HYPOT_TOLERANCE, 0},
+{271, 1091672474u, 1095866778u, 1098855795u, 0, HYPOT_TOLERANCE, 0},
+{272, 1093455053u, 1097649357u, 1100124820u, 0, HYPOT_TOLERANCE, 0},
+{273, 1095237632u, 1099169792u, 1101371928u, 0, HYPOT_TOLERANCE, 0},
+{274, 1097020211u, 1100061082u, 1102621806u, 0, HYPOT_TOLERANCE, 0},
+{275, 1098802790u, 1100952371u, 1103873675u, 0, HYPOT_TOLERANCE, 0},
+{276, 1099746509u, 1101843661u, 1105127024u, 0, HYPOT_TOLERANCE, 0},
+{277, 1100637798u, 1102734950u, 1106381502u, 0, HYPOT_TOLERANCE, 0},
+{278, 1101529088u, 1103626240u, 1107466559u, 0, HYPOT_TOLERANCE, 0},
+{279, 1102420378u, 1104517530u, 1108094589u, 0, HYPOT_TOLERANCE, 0},
+{280, 1103311667u, 1105408819u, 1108722902u, 0, HYPOT_TOLERANCE, 0},
+{281, 1104202957u, 1106300109u, 1109351447u, 0, HYPOT_TOLERANCE, 0},
+{282, 1105094246u, 1107191398u, 1109980183u, 0, HYPOT_TOLERANCE, 0},
+{283, 1105985536u, 1107689472u, 1110609082u, 0, HYPOT_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_LOG10_H multiple inclusion protection
+
+// EOF log10.h
diff --git a/packages/language/c/libm/current/tests/vectors/ilogbf.c b/packages/language/c/libm/current/tests/vectors/ilogbf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/ilogbf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      ilogbf.c
+//
+//      Test of ilogbf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vetors/ilogbf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(ilogbf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &ilogbf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_INT,
+                     &ilogbf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("ilogbf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("ilogbf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library ilogbf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "ilogbf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF ilogbf.c
diff --git a/packages/language/c/libm/current/tests/vectors/ilogbf.h b/packages/language/c/libm/current/tests/vectors/ilogbf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/ilogbf.h
@@ -0,0 +1,1361 @@
+#ifndef CYGONCE_LIBM_ILOGBF_H
+#define CYGONCE_LIBM_ILOGBF_H
+//===========================================================================
+//
+//      ilogbf.h
+//
+//      Test vectors for testing of ilogbf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/ilogbf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define ILOGBF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t ilogbf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+/*
+{0, 3214514586u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{1, 3214430700u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{2, 3214346813u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{3, 3214262927u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{4, 3214179041u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{5, 3214095155u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{6, 3214011269u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{7, 3213927383u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{8, 3213843497u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{9, 3213759611u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{10, 3213675725u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{11, 3213591839u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{12, 3213507953u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{13, 3213424067u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{14, 3213340180u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{15, 3213256294u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{16, 3213172408u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{17, 3213088522u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{18, 3213004636u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{19, 3212920750u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{20, 3212836864u, 0u, 0u, 0, ILOGBF_TOLERANCE, 0},*/
+{21, 3212669092u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{22, 3212501320u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{23, 3212333548u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{24, 3212165775u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{25, 3211998003u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{26, 3211830231u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{27, 3211662459u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{28, 3211494687u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{29, 3211326915u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{30, 3211159142u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{31, 3210991370u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{32, 3210823598u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{33, 3210655826u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{34, 3210488054u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{35, 3210320282u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{36, 3210152509u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{37, 3209984737u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{38, 3209816965u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{39, 3209649193u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{40, 3209481421u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{41, 3209313649u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{42, 3209145876u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{43, 3208978104u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{44, 3208810332u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{45, 3208642560u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{46, 3208474788u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{47, 3208307016u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{48, 3208139244u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{49, 3207971471u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{50, 3207803699u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{51, 3207635927u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{52, 3207468155u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{53, 3207300383u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{54, 3207132611u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{55, 3206964838u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{56, 3206797066u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{57, 3206629294u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{58, 3206461522u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{59, 3206293750u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{60, 3206125978u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{61, 3205958205u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{62, 3205790433u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{63, 3205622661u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{64, 3205454889u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{65, 3205287117u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{66, 3205119345u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{67, 3204951572u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{68, 3204783800u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{69, 3204616028u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{70, 3204448256u, 0u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{71, 3204112712u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{72, 3203777167u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{73, 3203441623u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{74, 3203106079u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{75, 3202770534u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{76, 3202434990u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{77, 3202099446u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{78, 3201763901u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{79, 3201428357u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{80, 3201092813u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{81, 3200757268u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{82, 3200421724u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{83, 3200086180u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{84, 3199750636u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{85, 3199415091u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{86, 3199079547u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{87, 3198744003u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{88, 3198408458u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{89, 3198072914u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{90, 3197737370u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{91, 3197401825u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{92, 3197066281u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{93, 3196730737u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{94, 3196395192u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{95, 3196059648u, 0u, 3221225472u, 0, ILOGBF_TOLERANCE, 0},
+{96, 3195388559u, 0u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
+{97, 3194717471u, 0u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
+{98, 3194046382u, 0u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
+{99, 3193375293u, 0u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
+{100, 3192704205u, 0u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
+{101, 3192033116u, 0u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
+{102, 3191362028u, 0u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
+{103, 3190690939u, 0u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
+{104, 3190019850u, 0u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
+{105, 3189348762u, 0u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
+{106, 3188677673u, 0u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
+{107, 3188006584u, 0u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
+{108, 3186999951u, 0u, 3229614080u, 0, ILOGBF_TOLERANCE, 0},
+{109, 3185657774u, 0u, 3229614080u, 0, ILOGBF_TOLERANCE, 0},
+{110, 3184315597u, 0u, 3229614080u, 0, ILOGBF_TOLERANCE, 0},
+{111, 3182973420u, 0u, 3229614080u, 0, ILOGBF_TOLERANCE, 0},
+{112, 3181631242u, 0u, 3229614080u, 0, ILOGBF_TOLERANCE, 0},
+{113, 3180289065u, 0u, 3229614080u, 0, ILOGBF_TOLERANCE, 0},
+{114, 3178611343u, 0u, 3231711232u, 0, ILOGBF_TOLERANCE, 0},
+{115, 3175926989u, 0u, 3231711232u, 0, ILOGBF_TOLERANCE, 0},
+{116, 3173242634u, 0u, 3231711232u, 0, ILOGBF_TOLERANCE, 0},
+{117, 3170222735u, 0u, 3233808384u, 0, ILOGBF_TOLERANCE, 0},
+{118, 3164854026u, 0u, 3233808384u, 0, ILOGBF_TOLERANCE, 0},
+{119, 3156465418u, 0u, 3235905536u, 0, ILOGBF_TOLERANCE, 0},
+{120, 1008981770u, 0u, 3235905536u, 0, ILOGBF_TOLERANCE, 0},
+{121, 1017370378u, 0u, 3233808384u, 0, ILOGBF_TOLERANCE, 0},
+{122, 1022739087u, 0u, 3233808384u, 0, ILOGBF_TOLERANCE, 0},
+{123, 1025758986u, 0u, 3231711232u, 0, ILOGBF_TOLERANCE, 0},
+{124, 1028443341u, 0u, 3231711232u, 0, ILOGBF_TOLERANCE, 0},
+{125, 1031127695u, 0u, 3231711232u, 0, ILOGBF_TOLERANCE, 0},
+{126, 1032805417u, 0u, 3229614080u, 0, ILOGBF_TOLERANCE, 0},
+{127, 1034147594u, 0u, 3229614080u, 0, ILOGBF_TOLERANCE, 0},
+{128, 1035489772u, 0u, 3229614080u, 0, ILOGBF_TOLERANCE, 0},
+{129, 1036831949u, 0u, 3229614080u, 0, ILOGBF_TOLERANCE, 0},
+{130, 1038174126u, 0u, 3229614080u, 0, ILOGBF_TOLERANCE, 0},
+{131, 1039516303u, 0u, 3229614080u, 0, ILOGBF_TOLERANCE, 0},
+{132, 1040522936u, 0u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
+{133, 1041194025u, 0u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
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+{1192, 3469778622u, 1200179013u, 1106247680u, 0, ILOGBF_TOLERANCE, 0},
+{1193, 1147712200u, 931865525u, 1091567616u, 0, ILOGBF_TOLERANCE, 0},
+{1194, 812694172u, 1136276190u, 3254255616u, 0, ILOGBF_TOLERANCE, 0},
+{1195, 862266739u, 3139447362u, 3251109888u, 0, ILOGBF_TOLERANCE, 0},
+{1196, 1124721745u, 3058969650u, 1088421888u, 0, ILOGBF_TOLERANCE, 0},
+{1197, 3261744304u, 1043806501u, 1084227584u, 0, ILOGBF_TOLERANCE, 0},
+{1198, 832324055u, 2954061156u, 3252682752u, 0, ILOGBF_TOLERANCE, 0},
+{1199, 805759679u, 903848557u, 3254255616u, 0, ILOGBF_TOLERANCE, 0},
+{1200, 2983396015u, 872299138u, 3252682752u, 0, ILOGBF_TOLERANCE, 0},
+{1201, 1064922416u, 1320485628u, 3212836864u, 0, ILOGBF_TOLERANCE, 0},
+{1202, 868114980u, 3213276361u, 3250585600u, 0, ILOGBF_TOLERANCE, 0},
+{1203, 3303160152u, 3075455322u, 1092616192u, 0, ILOGBF_TOLERANCE, 0},
+{1204, 1315090496u, 3269683237u, 1105723392u, 0, ILOGBF_TOLERANCE, 0},
+{1205, 850876090u, 3365795667u, 3251634176u, 0, ILOGBF_TOLERANCE, 0},
+{1206, 3230403187u, 1322841992u, 1073741824u, 0, ILOGBF_TOLERANCE, 0},
+{1207, 1335399673u, 974138676u, 1107296256u, 0, ILOGBF_TOLERANCE, 0},
+{1208, 1072458508u, 3372833993u, 0u, 0, ILOGBF_TOLERANCE, 0},
+{1209, 3303015249u, 3015039539u, 1092616192u, 0, ILOGBF_TOLERANCE, 0},
+{1210, 3252139741u, 1059615003u, 1082130432u, 0, ILOGBF_TOLERANCE, 0},
+{1211, 3468519966u, 3113982619u, 1106247680u, 0, ILOGBF_TOLERANCE, 0},
+{1212, 1006231203u, 897530770u, 3238002688u, 0, ILOGBF_TOLERANCE, 0},
+{1213, 951554138u, 1001144381u, 3244294144u, 0, ILOGBF_TOLERANCE, 0},
+{1214, 942046828u, 986341002u, 3245342720u, 0, ILOGBF_TOLERANCE, 0},
+{1215, 2968517146u, 951832467u, 3253731328u, 0, ILOGBF_TOLERANCE, 0},
+{1216, 3319723279u, 3414482416u, 1094713344u, 0, ILOGBF_TOLERANCE, 0},
+{1217, 3255104167u, 928827688u, 1084227584u, 0, ILOGBF_TOLERANCE, 0},
+{1218, 1155477903u, 3104812800u, 1092616192u, 0, ILOGBF_TOLERANCE, 0},
+{1219, 3273889176u, 980486479u, 1088421888u, 0, ILOGBF_TOLERANCE, 0},
+{1220, 3237813668u, 3441016803u, 1073741824u, 0, ILOGBF_TOLERANCE, 0},
+{1221, 1228207362u, 2985476579u, 1100480512u, 0, ILOGBF_TOLERANCE, 0},
+{1222, 975349337u, 1311932596u, 3241148416u, 0, ILOGBF_TOLERANCE, 0},
+{1223, 2982583196u, 3132904446u, 3252682752u, 0, ILOGBF_TOLERANCE, 0},
+{1224, 1290175785u, 3008182462u, 1104150528u, 0, ILOGBF_TOLERANCE, 0},
+{1225, 981908840u, 3314038398u, 3240099840u, 0, ILOGBF_TOLERANCE, 0},
+{1226, 941187647u, 1107765599u, 3245342720u, 0, ILOGBF_TOLERANCE, 0},
+{1227, 1214223128u, 3225536822u, 1099431936u, 0, ILOGBF_TOLERANCE, 0},
+{1228, 3422922584u, 1086391131u, 1103626240u, 0, ILOGBF_TOLERANCE, 0},
+{1229, 1315857601u, 3487600045u, 1105723392u, 0, ILOGBF_TOLERANCE, 0},
+{1230, 3453226030u, 3233768835u, 1105199104u, 0, ILOGBF_TOLERANCE, 0},
+{1231, 1078359574u, 3199175230u, 1065353216u, 0, ILOGBF_TOLERANCE, 0},
+{1232, 1029557624u, 3302959071u, 3231711232u, 0, ILOGBF_TOLERANCE, 0},
+{1233, 1207675424u, 3042692550u, 1098907648u, 0, ILOGBF_TOLERANCE, 0},
+{1234, 1028355074u, 3442294040u, 3231711232u, 0, ILOGBF_TOLERANCE, 0},
+{1235, 3119299090u, 1187096397u, 3242196992u, 0, ILOGBF_TOLERANCE, 0},
+{1236, 1248421894u, 3367769132u, 1101529088u, 0, ILOGBF_TOLERANCE, 0},
+{1237, 3353251994u, 1095517730u, 1098907648u, 0, ILOGBF_TOLERANCE, 0},
+{1238, 876926659u, 3288089977u, 3250061312u, 0, ILOGBF_TOLERANCE, 0},
+{1239, 1076752219u, 876236939u, 1065353216u, 0, ILOGBF_TOLERANCE, 0},
+{1240, 3388531942u, 2988520062u, 1101004800u, 0, ILOGBF_TOLERANCE, 0},
+{1241, 1273395082u, 3031189261u, 1103101952u, 0, ILOGBF_TOLERANCE, 0},
+{1242, 3385588183u, 3258252464u, 1101004800u, 0, ILOGBF_TOLERANCE, 0},
+{1243, 862047095u, 829323655u, 3251109888u, 0, ILOGBF_TOLERANCE, 0},
+{1244, 3192315328u, 3289489214u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
+{1245, 3441804648u, 3274638356u, 1104674816u, 0, ILOGBF_TOLERANCE, 0},
+{1246, 837368567u, 3228474927u, 3252682752u, 0, ILOGBF_TOLERANCE, 0},
+{1247, 3392827417u, 1277961150u, 1101529088u, 0, ILOGBF_TOLERANCE, 0},
+{1248, 1161241793u, 1328003707u, 1093664768u, 0, ILOGBF_TOLERANCE, 0},
+{1249, 856495732u, 3123041418u, 3251109888u, 0, ILOGBF_TOLERANCE, 0},
+{1250, 3034494183u, 3041579130u, 3249537024u, 0, ILOGBF_TOLERANCE, 0},
+{1251, 1171318485u, 3374409104u, 1094713344u, 0, ILOGBF_TOLERANCE, 0},
+{1252, 3047748143u, 831102792u, 3248488448u, 0, ILOGBF_TOLERANCE, 0},
+{1253, 1001216371u, 3052357038u, 3238002688u, 0, ILOGBF_TOLERANCE, 0},
+{1254, 2999541351u, 3085461799u, 3251634176u, 0, ILOGBF_TOLERANCE, 0},
+{1255, 912515889u, 1074635609u, 3247964160u, 0, ILOGBF_TOLERANCE, 0},
+{1256, 3391452505u, 897989232u, 1101529088u, 0, ILOGBF_TOLERANCE, 0},
+{1257, 3249603369u, 3147662248u, 1082130432u, 0, ILOGBF_TOLERANCE, 0},
+{1258, 1220264047u, 2960450369u, 1099956224u, 0, ILOGBF_TOLERANCE, 0},
+{1259, 3169816394u, 988430929u, 3233808384u, 0, ILOGBF_TOLERANCE, 0},
+{1260, 3098997418u, 3002162688u, 3244294144u, 0, ILOGBF_TOLERANCE, 0},
+{1261, 3282212423u, 3174079140u, 1090519040u, 0, ILOGBF_TOLERANCE, 0},
+{1262, 3352293320u, 3247843425u, 1098907648u, 0, ILOGBF_TOLERANCE, 0},
+{1263, 3296358441u, 875645354u, 1091567616u, 0, ILOGBF_TOLERANCE, 0},
+{1264, 1197828352u, 3245614728u, 1097859072u, 0, ILOGBF_TOLERANCE, 0},
+{1265, 3340510371u, 914930263u, 1097859072u, 0, ILOGBF_TOLERANCE, 0},
+{1266, 1127109339u, 3368125489u, 1088421888u, 0, ILOGBF_TOLERANCE, 0},
+{1267, 816173492u, 1083268662u, 3253731328u, 0, ILOGBF_TOLERANCE, 0},
+{1268, 909467381u, 1232375752u, 3247964160u, 0, ILOGBF_TOLERANCE, 0},
+{1269, 1200599955u, 2981200675u, 1098907648u, 0, ILOGBF_TOLERANCE, 0},
+{1270, 962230977u, 2988248037u, 3243245568u, 0, ILOGBF_TOLERANCE, 0},
+{1271, 2996667337u, 1068572835u, 3251634176u, 0, ILOGBF_TOLERANCE, 0},
+{1272, 3192887808u, 3191848339u, 3225419776u, 0, ILOGBF_TOLERANCE, 0},
+{1273, 3237183876u, 3179379969u, 1073741824u, 0, ILOGBF_TOLERANCE, 0},
+{1274, 939285924u, 3056079386u, 3246391296u, 0, ILOGBF_TOLERANCE, 0},
+{1275, 944050180u, 3452557879u, 3245342720u, 0, ILOGBF_TOLERANCE, 0},
+{1276, 3058135703u, 3090284601u, 3247964160u, 0, ILOGBF_TOLERANCE, 0},
+{1277, 3480592662u, 3261728191u, 1106771968u, 0, ILOGBF_TOLERANCE, 0},
+{1278, 3061939312u, 3274418540u, 3247439872u, 0, ILOGBF_TOLERANCE, 0},
+{1279, 1003299981u, 853295521u, 3238002688u, 0, ILOGBF_TOLERANCE, 0},
+{1280, 1155775526u, 1255814444u, 1092616192u, 0, ILOGBF_TOLERANCE, 0},
+{1281, 1234491880u, 3408568717u, 1101004800u, 0, ILOGBF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_ILOGBF_H multiple inclusion protection
+
+// EOF ilogbf.h
diff --git a/packages/language/c/libm/current/tests/vectors/isnanf.c b/packages/language/c/libm/current/tests/vectors/isnanf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/isnanf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      isnanf.c
+//
+//      Test of isnanf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/isnanf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(isnanf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &isnanf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_INT,
+                     &isnanf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("isnanf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("isnanf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library isnanf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "isnanf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF isnanf.c
diff --git a/packages/language/c/libm/current/tests/vectors/isnanf.h b/packages/language/c/libm/current/tests/vectors/isnanf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/isnanf.h
@@ -0,0 +1,1401 @@
+#ifndef CYGONCE_LIBM_ISNANF_H
+#define CYGONCE_LIBM_ISNANF_H
+//===========================================================================
+//
+//      isnanf.h
+//
+//      Test vectors for testing of isnanf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/isnanf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define ISNANF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t isnanf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1, 3214430700u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{2, 3214346813u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{3, 3214262927u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{4, 3214179041u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{5, 3214095155u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{6, 3214011269u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{7, 3213927383u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{8, 3213843497u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{9, 3213759611u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{10, 3213675725u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{11, 3213591839u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{12, 3213507953u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{13, 3213424067u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{14, 3213340180u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{15, 3213256294u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{16, 3213172408u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{17, 3213088522u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{18, 3213004636u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{19, 3212920750u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{20, 3212836864u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{21, 3212669092u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{22, 3212501320u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{23, 3212333548u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{24, 3212165775u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{25, 3211998003u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{26, 3211830231u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{27, 3211662459u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{28, 3211494687u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{29, 3211326915u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{30, 3211159142u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{31, 3210991370u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{32, 3210823598u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{33, 3210655826u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{34, 3210488054u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{35, 3210320282u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{36, 3210152509u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{37, 3209984737u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{38, 3209816965u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{39, 3209649193u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{40, 3209481421u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{41, 3209313649u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{42, 3209145876u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{43, 3208978104u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{44, 3208810332u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{45, 3208642560u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{46, 3208474788u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{47, 3208307016u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{48, 3208139244u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{49, 3207971471u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{50, 3207803699u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{51, 3207635927u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{52, 3207468155u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{53, 3207300383u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{54, 3207132611u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{55, 3206964838u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{56, 3206797066u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{57, 3206629294u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{58, 3206461522u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{59, 3206293750u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{60, 3206125978u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{61, 3205958205u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{62, 3205790433u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{63, 3205622661u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{64, 3205454889u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{65, 3205287117u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{66, 3205119345u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{67, 3204951572u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{68, 3204783800u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
+{69, 3204616028u, 0u, 0u, 0, ISNANF_TOLERANCE, 0},
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+{1258, 1220264047u, 2960450369u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1259, 3169816394u, 988430929u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1260, 3098997418u, 3002162688u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1261, 3282212423u, 3174079140u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1262, 3352293320u, 3247843425u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1263, 3296358441u, 875645354u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1264, 1197828352u, 3245614728u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1265, 3340510371u, 914930263u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1266, 1127109339u, 3368125489u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1267, 816173492u, 1083268662u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1268, 909467381u, 1232375752u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1269, 1200599955u, 2981200675u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1270, 962230977u, 2988248037u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1271, 2996667337u, 1068572835u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1272, 3192887808u, 3191848339u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1273, 3237183876u, 3179379969u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1274, 939285924u, 3056079386u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1275, 944050180u, 3452557879u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1276, 3058135703u, 3090284601u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1277, 3480592662u, 3261728191u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1278, 3061939312u, 3274418540u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1279, 1003299981u, 853295521u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1280, 1155775526u, 1255814444u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1281, 1234491880u, 3408568717u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1282, 2143289344u, 2143289344u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1283, 4290772992u, 4290772992u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1284, 2139095040u, 2139095040u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1285, 4286578688u, 4286578688u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1286, 2143289344u, 2143289344u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1287, 4290772992u, 4290772992u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1288, 2139095040u, 2139095040u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1289, 4286578688u, 4286578688u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1290, 2143289344u, 2143289344u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1291, 4290772992u, 4290772992u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1292, 2139095040u, 2139095040u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1293, 4286578688u, 4286578688u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1294, 2143289344u, 2143289344u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1295, 4290772992u, 4290772992u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1296, 2139095040u, 2139095040u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1297, 4286578688u, 4286578688u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1298, 2143289344u, 2143289344u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1299, 4290772992u, 4290772992u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1300, 2139095040u, 2139095040u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1301, 4286578688u, 4286578688u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1302, 2143289344u, 2143289344u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1303, 4290772992u, 4290772992u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1304, 2139095040u, 2139095040u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1305, 4286578688u, 4286578688u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1306, 2143289344u, 2143289344u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1307, 4290772992u, 4290772992u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1308, 2139095040u, 2139095040u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1309, 4286578688u, 4286578688u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1310, 2143289344u, 2143289344u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1311, 4290772992u, 4290772992u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1312, 2139095040u, 2139095040u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1313, 4286578688u, 4286578688u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1314, 2143289344u, 2143289344u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1315, 4290772992u, 4290772992u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1316, 2139095040u, 2139095040u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1317, 4286578688u, 4286578688u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1318, 2143289344u, 2143289344u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1319, 4290772992u, 4290772992u, 1065353216u, 0, ISNANF_TOLERANCE, 0},
+{1320, 2139095040u, 2139095040u, 0u, 0, ISNANF_TOLERANCE, 0},
+{1321, 4286578688u, 4286578688u, 0u, 0, ISNANF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_ISNANF_H multiple inclusion protection
+
+// EOF isnanf.h
diff --git a/packages/language/c/libm/current/tests/vectors/j0f.c b/packages/language/c/libm/current/tests/vectors/j0f.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/j0f.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      j0f.c
+//
+//      Test of j0f() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/j0f.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(j0f_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &j0f, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &j0f_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("j0f() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("j0f() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library j0f() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "j0f() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF j0f.c
diff --git a/packages/language/c/libm/current/tests/vectors/j0f.h b/packages/language/c/libm/current/tests/vectors/j0f.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/j0f.h
@@ -0,0 +1,362 @@
+#ifndef CYGONCE_LIBM_J0_H
+#define CYGONCE_LIBM_J0_H
+//===========================================================================
+//
+//      j0f.h
+//
+//      Test vectors for testing of j0f() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/j0f.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define J0_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t j0f_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 1059835739u, 1059835739u, 0, J0_TOLERANCE, 0},
+{1, 3214430700u, 1059919122u, 1059919122u, 0, J0_TOLERANCE, 0},
+{2, 3214346813u, 1060002071u, 1060002071u, 0, J0_TOLERANCE, 0},
+{3, 3214262927u, 1060084577u, 1060084577u, 0, J0_TOLERANCE, 0},
+{4, 3214179041u, 1060166635u, 1060166635u, 0, J0_TOLERANCE, 0},
+{5, 3214095155u, 1060248241u, 1060248241u, 0, J0_TOLERANCE, 0},
+{6, 3214011269u, 1060329386u, 1060329386u, 0, J0_TOLERANCE, 0},
+{7, 3213927383u, 1060410067u, 1060410067u, 0, J0_TOLERANCE, 0},
+{8, 3213843497u, 1060490274u, 1060490274u, 0, J0_TOLERANCE, 0},
+{9, 3213759611u, 1060570006u, 1060570006u, 0, J0_TOLERANCE, 0},
+{10, 3213675725u, 1060649254u, 1060649254u, 0, J0_TOLERANCE, 0},
+{11, 3213591839u, 1060728013u, 1060728013u, 0, J0_TOLERANCE, 0},
+{12, 3213507953u, 1060806276u, 1060806276u, 0, J0_TOLERANCE, 0},
+{13, 3213424067u, 1060884039u, 1060884039u, 0, J0_TOLERANCE, 0},
+{14, 3213340180u, 1060961298u, 1060961298u, 0, J0_TOLERANCE, 0},
+{15, 3213256294u, 1061038042u, 1061038042u, 0, J0_TOLERANCE, 0},
+{16, 3213172408u, 1061114269u, 1061114269u, 0, J0_TOLERANCE, 0},
+{17, 3213088522u, 1061189972u, 1061189972u, 0, J0_TOLERANCE, 0},
+{18, 3213004636u, 1061265147u, 1061265147u, 0, J0_TOLERANCE, 0},
+{19, 3212920750u, 1061339787u, 1061339787u, 0, J0_TOLERANCE, 0},
+{20, 3212836864u, 1061413887u, 1061413887u, 0, J0_TOLERANCE, 0},
+{21, 3212669092u, 1061487442u, 1061487442u, 0, J0_TOLERANCE, 0},
+{22, 3212501320u, 1061560445u, 1061560445u, 0, J0_TOLERANCE, 0},
+{23, 3212333548u, 1061632891u, 1061632891u, 0, J0_TOLERANCE, 0},
+{24, 3212165775u, 1061704777u, 1061704777u, 0, J0_TOLERANCE, 0},
+{25, 3211998003u, 1061776097u, 1061776097u, 0, J0_TOLERANCE, 0},
+{26, 3211830231u, 1061846843u, 1061846843u, 0, J0_TOLERANCE, 0},
+{27, 3211662459u, 1061917012u, 1061917012u, 0, J0_TOLERANCE, 0},
+{28, 3211494687u, 1061986598u, 1061986598u, 0, J0_TOLERANCE, 0},
+{29, 3211326915u, 1062055596u, 1062055596u, 0, J0_TOLERANCE, 0},
+{30, 3211159142u, 1062124001u, 1062124001u, 0, J0_TOLERANCE, 0},
+{31, 3210991370u, 1062191808u, 1062191808u, 0, J0_TOLERANCE, 0},
+{32, 3210823598u, 1062259012u, 1062259012u, 0, J0_TOLERANCE, 0},
+{33, 3210655826u, 1062325608u, 1062325608u, 0, J0_TOLERANCE, 0},
+{34, 3210488054u, 1062391591u, 1062391591u, 0, J0_TOLERANCE, 0},
+{35, 3210320282u, 1062456956u, 1062456956u, 0, J0_TOLERANCE, 0},
+{36, 3210152509u, 1062521700u, 1062521700u, 0, J0_TOLERANCE, 0},
+{37, 3209984737u, 1062585814u, 1062585814u, 0, J0_TOLERANCE, 0},
+{38, 3209816965u, 1062649297u, 1062649297u, 0, J0_TOLERANCE, 0},
+{39, 3209649193u, 1062712142u, 1062712142u, 0, J0_TOLERANCE, 0},
+{40, 3209481421u, 1062774345u, 1062774345u, 0, J0_TOLERANCE, 0},
+{41, 3209313649u, 1062835904u, 1062835904u, 0, J0_TOLERANCE, 0},
+{42, 3209145876u, 1062896811u, 1062896811u, 0, J0_TOLERANCE, 0},
+{43, 3208978104u, 1062957061u, 1062957061u, 0, J0_TOLERANCE, 0},
+{44, 3208810332u, 1063016653u, 1063016653u, 0, J0_TOLERANCE, 0},
+{45, 3208642560u, 1063075578u, 1063075578u, 0, J0_TOLERANCE, 0},
+{46, 3208474788u, 1063133838u, 1063133838u, 0, J0_TOLERANCE, 0},
+{47, 3208307016u, 1063191423u, 1063191423u, 0, J0_TOLERANCE, 0},
+{48, 3208139244u, 1063248330u, 1063248330u, 0, J0_TOLERANCE, 0},
+{49, 3207971471u, 1063304557u, 1063304557u, 0, J0_TOLERANCE, 0},
+{50, 3207803699u, 1063360098u, 1063360098u, 0, J0_TOLERANCE, 0},
+{51, 3207635927u, 1063414948u, 1063414948u, 0, J0_TOLERANCE, 0},
+{52, 3207468155u, 1063469104u, 1063469104u, 0, J0_TOLERANCE, 0},
+{53, 3207300383u, 1063522564u, 1063522564u, 0, J0_TOLERANCE, 0},
+{54, 3207132611u, 1063575320u, 1063575320u, 0, J0_TOLERANCE, 0},
+{55, 3206964838u, 1063627371u, 1063627371u, 0, J0_TOLERANCE, 0},
+{56, 3206797066u, 1063678713u, 1063678713u, 0, J0_TOLERANCE, 0},
+{57, 3206629294u, 1063729339u, 1063729339u, 0, J0_TOLERANCE, 0},
+{58, 3206461522u, 1063779249u, 1063779249u, 0, J0_TOLERANCE, 0},
+{59, 3206293750u, 1063828438u, 1063828438u, 0, J0_TOLERANCE, 0},
+{60, 3206125978u, 1063876903u, 1063876903u, 0, J0_TOLERANCE, 0},
+{61, 3205958205u, 1063924638u, 1063924638u, 0, J0_TOLERANCE, 0},
+{62, 3205790433u, 1063971642u, 1063971642u, 0, J0_TOLERANCE, 0},
+{63, 3205622661u, 1064017911u, 1064017911u, 0, J0_TOLERANCE, 0},
+{64, 3205454889u, 1064063439u, 1064063439u, 0, J0_TOLERANCE, 0},
+{65, 3205287117u, 1064108226u, 1064108226u, 0, J0_TOLERANCE, 0},
+{66, 3205119345u, 1064152266u, 1064152266u, 0, J0_TOLERANCE, 0},
+{67, 3204951572u, 1064195560u, 1064195560u, 0, J0_TOLERANCE, 0},
+{68, 3204783800u, 1064238100u, 1064238100u, 0, J0_TOLERANCE, 0},
+{69, 3204616028u, 1064279884u, 1064279884u, 0, J0_TOLERANCE, 0},
+{70, 3204448256u, 1064320911u, 1064320911u, 0, J0_TOLERANCE, 0},
+{71, 3204112712u, 1064361174u, 1064361174u, 0, J0_TOLERANCE, 0},
+{72, 3203777167u, 1064400675u, 1064400675u, 0, J0_TOLERANCE, 0},
+{73, 3203441623u, 1064439408u, 1064439408u, 0, J0_TOLERANCE, 0},
+{74, 3203106079u, 1064477370u, 1064477370u, 0, J0_TOLERANCE, 0},
+{75, 3202770534u, 1064514559u, 1064514559u, 0, J0_TOLERANCE, 0},
+{76, 3202434990u, 1064550972u, 1064550972u, 0, J0_TOLERANCE, 0},
+{77, 3202099446u, 1064586606u, 1064586606u, 0, J0_TOLERANCE, 0},
+{78, 3201763901u, 1064621459u, 1064621459u, 0, J0_TOLERANCE, 0},
+{79, 3201428357u, 1064655526u, 1064655526u, 0, J0_TOLERANCE, 0},
+{80, 3201092813u, 1064688809u, 1064688809u, 0, J0_TOLERANCE, 0},
+{81, 3200757268u, 1064721302u, 1064721302u, 0, J0_TOLERANCE, 0},
+{82, 3200421724u, 1064753003u, 1064753003u, 0, J0_TOLERANCE, 0},
+{83, 3200086180u, 1064783911u, 1064783911u, 0, J0_TOLERANCE, 0},
+{84, 3199750636u, 1064814022u, 1064814022u, 0, J0_TOLERANCE, 0},
+{85, 3199415091u, 1064843334u, 1064843334u, 0, J0_TOLERANCE, 0},
+{86, 3199079547u, 1064871847u, 1064871847u, 0, J0_TOLERANCE, 0},
+{87, 3198744003u, 1064899556u, 1064899556u, 0, J0_TOLERANCE, 0},
+{88, 3198408458u, 1064926461u, 1064926461u, 0, J0_TOLERANCE, 0},
+{89, 3198072914u, 1064952558u, 1064952558u, 0, J0_TOLERANCE, 0},
+{90, 3197737370u, 1064977846u, 1064977846u, 0, J0_TOLERANCE, 0},
+{91, 3197401825u, 1065002325u, 1065002325u, 0, J0_TOLERANCE, 0},
+{92, 3197066281u, 1065025991u, 1065025991u, 0, J0_TOLERANCE, 0},
+{93, 3196730737u, 1065048842u, 1065048842u, 0, J0_TOLERANCE, 0},
+{94, 3196395192u, 1065070877u, 1065070877u, 0, J0_TOLERANCE, 0},
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+{107, 3188006584u, 1065282406u, 1065282406u, 0, J0_TOLERANCE, 0},
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+{116, 3173242634u, 1065346505u, 1065346505u, 0, J0_TOLERANCE, 0},
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+{119, 3156465418u, 1065352797u, 1065352797u, 0, J0_TOLERANCE, 0},
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+{124, 1028443341u, 1065342731u, 1065342731u, 0, J0_TOLERANCE, 0},
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+{126, 1032805417u, 1065332670u, 1065332670u, 0, J0_TOLERANCE, 0},
+{127, 1034147594u, 1065326383u, 1065326383u, 0, J0_TOLERANCE, 0},
+{128, 1035489772u, 1065319259u, 1065319259u, 0, J0_TOLERANCE, 0},
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+{134, 1041865114u, 1065258977u, 1065258977u, 0, J0_TOLERANCE, 0},
+{135, 1042536202u, 1065246014u, 1065246014u, 0, J0_TOLERANCE, 0},
+{136, 1043207291u, 1065232219u, 1065232219u, 0, J0_TOLERANCE, 0},
+{137, 1043878380u, 1065217596u, 1065217596u, 0, J0_TOLERANCE, 0},
+{138, 1044549468u, 1065202143u, 1065202143u, 0, J0_TOLERANCE, 0},
+{139, 1045220557u, 1065185863u, 1065185863u, 0, J0_TOLERANCE, 0},
+{140, 1045891645u, 1065168757u, 1065168757u, 0, J0_TOLERANCE, 0},
+{141, 1046562734u, 1065150825u, 1065150825u, 0, J0_TOLERANCE, 0},
+{142, 1047233823u, 1065132069u, 1065132069u, 0, J0_TOLERANCE, 0},
+{143, 1047904911u, 1065112493u, 1065112493u, 0, J0_TOLERANCE, 0},
+{144, 1048576000u, 1065092094u, 1065092094u, 0, J0_TOLERANCE, 0},
+{145, 1048911544u, 1065070877u, 1065070877u, 0, J0_TOLERANCE, 0},
+{146, 1049247089u, 1065048842u, 1065048842u, 0, J0_TOLERANCE, 0},
+{147, 1049582633u, 1065025991u, 1065025991u, 0, J0_TOLERANCE, 0},
+{148, 1049918177u, 1065002325u, 1065002325u, 0, J0_TOLERANCE, 0},
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+{156, 1052602532u, 1064783911u, 1064783911u, 0, J0_TOLERANCE, 0},
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+{161, 1054280253u, 1064621459u, 1064621459u, 0, J0_TOLERANCE, 0},
+{162, 1054615798u, 1064586606u, 1064586606u, 0, J0_TOLERANCE, 0},
+{163, 1054951342u, 1064550972u, 1064550972u, 0, J0_TOLERANCE, 0},
+{164, 1055286886u, 1064514559u, 1064514559u, 0, J0_TOLERANCE, 0},
+{165, 1055622431u, 1064477370u, 1064477370u, 0, J0_TOLERANCE, 0},
+{166, 1055957975u, 1064439408u, 1064439408u, 0, J0_TOLERANCE, 0},
+{167, 1056293519u, 1064400675u, 1064400675u, 0, J0_TOLERANCE, 0},
+{168, 1056629064u, 1064361174u, 1064361174u, 0, J0_TOLERANCE, 0},
+{169, 1056964608u, 1064320911u, 1064320911u, 0, J0_TOLERANCE, 0},
+{170, 1057132380u, 1064279884u, 1064279884u, 0, J0_TOLERANCE, 0},
+{171, 1057300152u, 1064238100u, 1064238100u, 0, J0_TOLERANCE, 0},
+{172, 1057467924u, 1064195560u, 1064195560u, 0, J0_TOLERANCE, 0},
+{173, 1057635697u, 1064152266u, 1064152266u, 0, J0_TOLERANCE, 0},
+{174, 1057803469u, 1064108226u, 1064108226u, 0, J0_TOLERANCE, 0},
+{175, 1057971241u, 1064063439u, 1064063439u, 0, J0_TOLERANCE, 0},
+{176, 1058139013u, 1064017911u, 1064017911u, 0, J0_TOLERANCE, 0},
+{177, 1058306785u, 1063971642u, 1063971642u, 0, J0_TOLERANCE, 0},
+{178, 1058474557u, 1063924638u, 1063924638u, 0, J0_TOLERANCE, 0},
+{179, 1058642330u, 1063876903u, 1063876903u, 0, J0_TOLERANCE, 0},
+{180, 1058810102u, 1063828438u, 1063828438u, 0, J0_TOLERANCE, 0},
+{181, 1058977874u, 1063779249u, 1063779249u, 0, J0_TOLERANCE, 0},
+{182, 1059145646u, 1063729339u, 1063729339u, 0, J0_TOLERANCE, 0},
+{183, 1059313418u, 1063678713u, 1063678713u, 0, J0_TOLERANCE, 0},
+{184, 1059481190u, 1063627371u, 1063627371u, 0, J0_TOLERANCE, 0},
+{185, 1059648963u, 1063575320u, 1063575320u, 0, J0_TOLERANCE, 0},
+{186, 1059816735u, 1063522564u, 1063522564u, 0, J0_TOLERANCE, 0},
+{187, 1059984507u, 1063469104u, 1063469104u, 0, J0_TOLERANCE, 0},
+{188, 1060152279u, 1063414948u, 1063414948u, 0, J0_TOLERANCE, 0},
+{189, 1060320051u, 1063360098u, 1063360098u, 0, J0_TOLERANCE, 0},
+{190, 1060487823u, 1063304557u, 1063304557u, 0, J0_TOLERANCE, 0},
+{191, 1060655596u, 1063248330u, 1063248330u, 0, J0_TOLERANCE, 0},
+{192, 1060823368u, 1063191423u, 1063191423u, 0, J0_TOLERANCE, 0},
+{193, 1060991140u, 1063133838u, 1063133838u, 0, J0_TOLERANCE, 0},
+{194, 1061158912u, 1063075578u, 1063075578u, 0, J0_TOLERANCE, 0},
+{195, 1061326684u, 1063016653u, 1063016653u, 0, J0_TOLERANCE, 0},
+{196, 1061494456u, 1062957061u, 1062957061u, 0, J0_TOLERANCE, 0},
+{197, 1061662228u, 1062896811u, 1062896811u, 0, J0_TOLERANCE, 0},
+{198, 1061830001u, 1062835904u, 1062835904u, 0, J0_TOLERANCE, 0},
+{199, 1061997773u, 1062774345u, 1062774345u, 0, J0_TOLERANCE, 0},
+{200, 1062165545u, 1062712142u, 1062712142u, 0, J0_TOLERANCE, 0},
+{201, 1062333317u, 1062649297u, 1062649297u, 0, J0_TOLERANCE, 0},
+{202, 1062501089u, 1062585814u, 1062585814u, 0, J0_TOLERANCE, 0},
+{203, 1062668861u, 1062521700u, 1062521700u, 0, J0_TOLERANCE, 0},
+{204, 1062836634u, 1062456956u, 1062456956u, 0, J0_TOLERANCE, 0},
+{205, 1063004406u, 1062391591u, 1062391591u, 0, J0_TOLERANCE, 0},
+{206, 1063172178u, 1062325608u, 1062325608u, 0, J0_TOLERANCE, 0},
+{207, 1063339950u, 1062259012u, 1062259012u, 0, J0_TOLERANCE, 0},
+{208, 1063507722u, 1062191808u, 1062191808u, 0, J0_TOLERANCE, 0},
+{209, 1063675494u, 1062124001u, 1062124001u, 0, J0_TOLERANCE, 0},
+{210, 1063843267u, 1062055596u, 1062055596u, 0, J0_TOLERANCE, 0},
+{211, 1064011039u, 1061986598u, 1061986598u, 0, J0_TOLERANCE, 0},
+{212, 1064178811u, 1061917012u, 1061917012u, 0, J0_TOLERANCE, 0},
+{213, 1064346583u, 1061846843u, 1061846843u, 0, J0_TOLERANCE, 0},
+{214, 1064514355u, 1061776097u, 1061776097u, 0, J0_TOLERANCE, 0},
+{215, 1064682127u, 1061704777u, 1061704777u, 0, J0_TOLERANCE, 0},
+{216, 1064849900u, 1061632891u, 1061632891u, 0, J0_TOLERANCE, 0},
+{217, 1065017672u, 1061560445u, 1061560445u, 0, J0_TOLERANCE, 0},
+{218, 1065185444u, 1061487442u, 1061487442u, 0, J0_TOLERANCE, 0},
+{219, 1065353216u, 1061413887u, 1061413887u, 0, J0_TOLERANCE, 0},
+{220, 1065437102u, 1061339787u, 1061339787u, 0, J0_TOLERANCE, 0},
+{221, 1065520988u, 1061265147u, 1061265147u, 0, J0_TOLERANCE, 0},
+{222, 1065604874u, 1061189972u, 1061189972u, 0, J0_TOLERANCE, 0},
+{223, 1065688760u, 1061114269u, 1061114269u, 0, J0_TOLERANCE, 0},
+{224, 1065772646u, 1061038042u, 1061038042u, 0, J0_TOLERANCE, 0},
+{225, 1065856532u, 1060961298u, 1060961298u, 0, J0_TOLERANCE, 0},
+{226, 1065940419u, 1060884039u, 1060884039u, 0, J0_TOLERANCE, 0},
+{227, 1066024305u, 1060806276u, 1060806276u, 0, J0_TOLERANCE, 0},
+{228, 1066108191u, 1060728013u, 1060728013u, 0, J0_TOLERANCE, 0},
+{229, 1066192077u, 1060649254u, 1060649254u, 0, J0_TOLERANCE, 0},
+{230, 1066275963u, 1060570006u, 1060570006u, 0, J0_TOLERANCE, 0},
+{231, 1066359849u, 1060490274u, 1060490274u, 0, J0_TOLERANCE, 0},
+{232, 1066443735u, 1060410067u, 1060410067u, 0, J0_TOLERANCE, 0},
+{233, 1066527621u, 1060329386u, 1060329386u, 0, J0_TOLERANCE, 0},
+{234, 1066611507u, 1060248241u, 1060248241u, 0, J0_TOLERANCE, 0},
+{235, 1066695393u, 1060166635u, 1060166635u, 0, J0_TOLERANCE, 0},
+{236, 1066779279u, 1060084577u, 1060084577u, 0, J0_TOLERANCE, 0},
+{237, 1066863165u, 1060002071u, 1060002071u, 0, J0_TOLERANCE, 0},
+{238, 1066947052u, 1059919122u, 1059919122u, 0, J0_TOLERANCE, 0},
+{239, 3234402267u, 1046581329u, 1046581329u, 0, J0_TOLERANCE, 0},
+{240, 3231108068u, 3196591726u, 3196591726u, 0, J0_TOLERANCE, 0},
+{241, 3226013659u, 3197879715u, 3197879715u, 0, J0_TOLERANCE, 0},
+{242, 3217625051u, 1056025123u, 1056025123u, 0, J0_TOLERANCE, 0},
+{243, 0u, 1065353216u, 1065353216u, 0, J0_TOLERANCE, 0},
+{244, 1070141403u, 1056025123u, 1056025123u, 0, J0_TOLERANCE, 0},
+{245, 1078530011u, 3197879715u, 3197879715u, 0, J0_TOLERANCE, 0},
+{246, 1083624420u, 3196591726u, 3196591726u, 0, J0_TOLERANCE, 0},
+{247, 3253731328u, 3182485944u, 3182485944u, 0, J0_TOLERANCE, 0},
+{248, 3252840038u, 3185426433u, 3185426433u, 0, J0_TOLERANCE, 0},
+{249, 3251948749u, 1039591153u, 1039591153u, 0, J0_TOLERANCE, 0},
+{250, 3251057459u, 1034583247u, 1034583247u, 0, J0_TOLERANCE, 0},
+{251, 3250166170u, 3189440518u, 3189440518u, 0, J0_TOLERANCE, 0},
+{252, 3249274880u, 3175642986u, 3175642986u, 0, J0_TOLERANCE, 0},
+{253, 3248383590u, 1043678978u, 1043678978u, 0, J0_TOLERANCE, 0},
+{254, 3247492301u, 1001510262u, 1001510262u, 0, J0_TOLERANCE, 0},
+{255, 3246601011u, 3192434080u, 3192434080u, 0, J0_TOLERANCE, 0},
+{256, 3245028147u, 1027810392u, 1027810392u, 0, J0_TOLERANCE, 0},
+{257, 3243245568u, 1045685354u, 1045685354u, 0, J0_TOLERANCE, 0},
+{258, 3241462989u, 3185935415u, 3185935415u, 0, J0_TOLERANCE, 0},
+{259, 3239680410u, 3193306751u, 3193306751u, 0, J0_TOLERANCE, 0},
+{260, 3237792973u, 1044842218u, 1044842218u, 0, J0_TOLERANCE, 0},
+{261, 3234227814u, 1045337775u, 1045337775u, 0, J0_TOLERANCE, 0},
+{262, 3230662656u, 3198426660u, 3198426660u, 0, J0_TOLERANCE, 0},
+{263, 3224580915u, 3191699990u, 3191699990u, 0, J0_TOLERANCE, 0},
+{264, 3213675725u, 1060649254u, 1060649254u, 0, J0_TOLERANCE, 0},
+{265, 1058642330u, 1063876903u, 1063876903u, 0, J0_TOLERANCE, 0},
+{266, 1075000115u, 1029930430u, 1029930430u, 0, J0_TOLERANCE, 0},
+{267, 1082130432u, 3200997175u, 3200997175u, 0, J0_TOLERANCE, 0},
+{268, 1085695590u, 1031106245u, 1031106245u, 0, J0_TOLERANCE, 0},
+{269, 1089260749u, 1049535541u, 1049535541u, 0, J0_TOLERANCE, 0},
+{270, 1091672474u, 3186226740u, 3186226740u, 0, J0_TOLERANCE, 0},
+{271, 1093455053u, 3192919090u, 3192919090u, 0, J0_TOLERANCE, 0},
+{272, 1095237632u, 1041655994u, 1041655994u, 0, J0_TOLERANCE, 0},
+{273, 1097020211u, 1041285935u, 1041285935u, 0, J0_TOLERANCE, 0},
+{274, 1098802790u, 3190353411u, 3190353411u, 0, J0_TOLERANCE, 0},
+{275, 1099746509u, 3182480552u, 3182480552u, 0, J0_TOLERANCE, 0},
+{276, 1100637798u, 1043281599u, 1043281599u, 0, J0_TOLERANCE, 0},
+{277, 1101529088u, 1024840698u, 1024840698u, 0, J0_TOLERANCE, 0},
+{278, 1102420378u, 3190481736u, 3190481736u, 0, J0_TOLERANCE, 0},
+{279, 1103311667u, 1006337519u, 1006337519u, 0, J0_TOLERANCE, 0},
+{280, 1104202957u, 1042114878u, 1042114878u, 0, J0_TOLERANCE, 0},
+{281, 1105094246u, 3174763439u, 3174763439u, 0, J0_TOLERANCE, 0},
+{282, 1105985536u, 3188217836u, 3188217836u, 0, J0_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_J0_H multiple inclusion protection
+
+// EOF j0f.h
diff --git a/packages/language/c/libm/current/tests/vectors/j1f.c b/packages/language/c/libm/current/tests/vectors/j1f.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/j1f.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      j1f.c
+//
+//      Test of j1f() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/j1f.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(j1f_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &j1f, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &j1f_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("j1f() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("j1f() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library j1f() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "j1f() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF j1f.c
diff --git a/packages/language/c/libm/current/tests/vectors/j1f.h b/packages/language/c/libm/current/tests/vectors/j1f.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/j1f.h
@@ -0,0 +1,362 @@
+#ifndef CYGONCE_LIBM_J1_H
+#define CYGONCE_LIBM_J1_H
+//===========================================================================
+//
+//      j1f.h
+//
+//      Test vectors for testing of j1f() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/j1f.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define J1_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t j1f_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 3204390847u, 3204390847u, 0, J1_TOLERANCE, 0},
+{1, 3214430700u, 3204304372u, 3204304372u, 0, J1_TOLERANCE, 0},
+{2, 3214346813u, 3204216675u, 3204216675u, 0, J1_TOLERANCE, 0},
+{3, 3214262927u, 3204127764u, 3204127764u, 0, J1_TOLERANCE, 0},
+{4, 3214179041u, 3204037646u, 3204037646u, 0, J1_TOLERANCE, 0},
+{5, 3214095155u, 3203946324u, 3203946324u, 0, J1_TOLERANCE, 0},
+{6, 3214011269u, 3203853807u, 3203853807u, 0, J1_TOLERANCE, 0},
+{7, 3213927383u, 3203760099u, 3203760099u, 0, J1_TOLERANCE, 0},
+{8, 3213843497u, 3203665208u, 3203665208u, 0, J1_TOLERANCE, 0},
+{9, 3213759611u, 3203569140u, 3203569140u, 0, J1_TOLERANCE, 0},
+{10, 3213675725u, 3203471902u, 3203471902u, 0, J1_TOLERANCE, 0},
+{11, 3213591839u, 3203373501u, 3203373501u, 0, J1_TOLERANCE, 0},
+{12, 3213507953u, 3203273943u, 3203273943u, 0, J1_TOLERANCE, 0},
+{13, 3213424067u, 3203173236u, 3203173236u, 0, J1_TOLERANCE, 0},
+{14, 3213340180u, 3203071384u, 3203071384u, 0, J1_TOLERANCE, 0},
+{15, 3213256294u, 3202968397u, 3202968397u, 0, J1_TOLERANCE, 0},
+{16, 3213172408u, 3202864283u, 3202864283u, 0, J1_TOLERANCE, 0},
+{17, 3213088522u, 3202759048u, 3202759048u, 0, J1_TOLERANCE, 0},
+{18, 3213004636u, 3202652698u, 3202652698u, 0, J1_TOLERANCE, 0},
+{19, 3212920750u, 3202545242u, 3202545242u, 0, J1_TOLERANCE, 0},
+{20, 3212836864u, 3202436688u, 3202436688u, 0, J1_TOLERANCE, 0},
+{21, 3212669092u, 3202327042u, 3202327042u, 0, J1_TOLERANCE, 0},
+{22, 3212501320u, 3202216313u, 3202216313u, 0, J1_TOLERANCE, 0},
+{23, 3212333548u, 3202104510u, 3202104510u, 0, J1_TOLERANCE, 0},
+{24, 3212165775u, 3201991637u, 3201991637u, 0, J1_TOLERANCE, 0},
+{25, 3211998003u, 3201877707u, 3201877707u, 0, J1_TOLERANCE, 0},
+{26, 3211830231u, 3201762724u, 3201762724u, 0, J1_TOLERANCE, 0},
+{27, 3211662459u, 3201646699u, 3201646699u, 0, J1_TOLERANCE, 0},
+{28, 3211494687u, 3201529639u, 3201529639u, 0, J1_TOLERANCE, 0},
+{29, 3211326915u, 3201411552u, 3201411552u, 0, J1_TOLERANCE, 0},
+{30, 3211159142u, 3201292447u, 3201292447u, 0, J1_TOLERANCE, 0},
+{31, 3210991370u, 3201172332u, 3201172332u, 0, J1_TOLERANCE, 0},
+{32, 3210823598u, 3201051217u, 3201051217u, 0, J1_TOLERANCE, 0},
+{33, 3210655826u, 3200929110u, 3200929110u, 0, J1_TOLERANCE, 0},
+{34, 3210488054u, 3200806018u, 3200806018u, 0, J1_TOLERANCE, 0},
+{35, 3210320282u, 3200681954u, 3200681954u, 0, J1_TOLERANCE, 0},
+{36, 3210152509u, 3200556922u, 3200556922u, 0, J1_TOLERANCE, 0},
+{37, 3209984737u, 3200430935u, 3200430935u, 0, J1_TOLERANCE, 0},
+{38, 3209816965u, 3200304001u, 3200304001u, 0, J1_TOLERANCE, 0},
+{39, 3209649193u, 3200176127u, 3200176127u, 0, J1_TOLERANCE, 0},
+{40, 3209481421u, 3200047325u, 3200047325u, 0, J1_TOLERANCE, 0},
+{41, 3209313649u, 3199917604u, 3199917604u, 0, J1_TOLERANCE, 0},
+{42, 3209145876u, 3199786971u, 3199786971u, 0, J1_TOLERANCE, 0},
+{43, 3208978104u, 3199655439u, 3199655439u, 0, J1_TOLERANCE, 0},
+{44, 3208810332u, 3199523016u, 3199523016u, 0, J1_TOLERANCE, 0},
+{45, 3208642560u, 3199389711u, 3199389711u, 0, J1_TOLERANCE, 0},
+{46, 3208474788u, 3199255534u, 3199255534u, 0, J1_TOLERANCE, 0},
+{47, 3208307016u, 3199120495u, 3199120495u, 0, J1_TOLERANCE, 0},
+{48, 3208139244u, 3198984604u, 3198984604u, 0, J1_TOLERANCE, 0},
+{49, 3207971471u, 3198847871u, 3198847871u, 0, J1_TOLERANCE, 0},
+{50, 3207803699u, 3198710305u, 3198710305u, 0, J1_TOLERANCE, 0},
+{51, 3207635927u, 3198571918u, 3198571918u, 0, J1_TOLERANCE, 0},
+{52, 3207468155u, 3198432718u, 3198432718u, 0, J1_TOLERANCE, 0},
+{53, 3207300383u, 3198292717u, 3198292717u, 0, J1_TOLERANCE, 0},
+{54, 3207132611u, 3198151925u, 3198151925u, 0, J1_TOLERANCE, 0},
+{55, 3206964838u, 3198010350u, 3198010350u, 0, J1_TOLERANCE, 0},
+{56, 3206797066u, 3197868004u, 3197868004u, 0, J1_TOLERANCE, 0},
+{57, 3206629294u, 3197724900u, 3197724900u, 0, J1_TOLERANCE, 0},
+{58, 3206461522u, 3197581046u, 3197581046u, 0, J1_TOLERANCE, 0},
+{59, 3206293750u, 3197436451u, 3197436451u, 0, J1_TOLERANCE, 0},
+{60, 3206125978u, 3197291130u, 3197291130u, 0, J1_TOLERANCE, 0},
+{61, 3205958205u, 3197145088u, 3197145088u, 0, J1_TOLERANCE, 0},
+{62, 3205790433u, 3196998341u, 3196998341u, 0, J1_TOLERANCE, 0},
+{63, 3205622661u, 3196850897u, 3196850897u, 0, J1_TOLERANCE, 0},
+{64, 3205454889u, 3196702768u, 3196702768u, 0, J1_TOLERANCE, 0},
+{65, 3205287117u, 3196553966u, 3196553966u, 0, J1_TOLERANCE, 0},
+{66, 3205119345u, 3196404499u, 3196404499u, 0, J1_TOLERANCE, 0},
+{67, 3204951572u, 3196254379u, 3196254379u, 0, J1_TOLERANCE, 0},
+{68, 3204783800u, 3196103619u, 3196103619u, 0, J1_TOLERANCE, 0},
+{69, 3204616028u, 3195844811u, 3195844811u, 0, J1_TOLERANCE, 0},
+{70, 3204448256u, 3195540793u, 3195540793u, 0, J1_TOLERANCE, 0},
+{71, 3204112712u, 3195235560u, 3195235560u, 0, J1_TOLERANCE, 0},
+{72, 3203777167u, 3194929135u, 3194929135u, 0, J1_TOLERANCE, 0},
+{73, 3203441623u, 3194621539u, 3194621539u, 0, J1_TOLERANCE, 0},
+{74, 3203106079u, 3194312798u, 3194312798u, 0, J1_TOLERANCE, 0},
+{75, 3202770534u, 3194002931u, 3194002931u, 0, J1_TOLERANCE, 0},
+{76, 3202434990u, 3193691965u, 3193691965u, 0, J1_TOLERANCE, 0},
+{77, 3202099446u, 3193379921u, 3193379921u, 0, J1_TOLERANCE, 0},
+{78, 3201763901u, 3193066821u, 3193066821u, 0, J1_TOLERANCE, 0},
+{79, 3201428357u, 3192752691u, 3192752691u, 0, J1_TOLERANCE, 0},
+{80, 3201092813u, 3192437553u, 3192437553u, 0, J1_TOLERANCE, 0},
+{81, 3200757268u, 3192121430u, 3192121430u, 0, J1_TOLERANCE, 0},
+{82, 3200421724u, 3191804346u, 3191804346u, 0, J1_TOLERANCE, 0},
+{83, 3200086180u, 3191486326u, 3191486326u, 0, J1_TOLERANCE, 0},
+{84, 3199750636u, 3191167393u, 3191167393u, 0, J1_TOLERANCE, 0},
+{85, 3199415091u, 3190847568u, 3190847568u, 0, J1_TOLERANCE, 0},
+{86, 3199079547u, 3190526878u, 3190526878u, 0, J1_TOLERANCE, 0},
+{87, 3198744003u, 3190205347u, 3190205347u, 0, J1_TOLERANCE, 0},
+{88, 3198408458u, 3189882997u, 3189882997u, 0, J1_TOLERANCE, 0},
+{89, 3198072914u, 3189559853u, 3189559853u, 0, J1_TOLERANCE, 0},
+{90, 3197737370u, 3189235939u, 3189235939u, 0, J1_TOLERANCE, 0},
+{91, 3197401825u, 3188911280u, 3188911280u, 0, J1_TOLERANCE, 0},
+{92, 3197066281u, 3188585899u, 3188585899u, 0, J1_TOLERANCE, 0},
+{93, 3196730737u, 3188259823u, 3188259823u, 0, J1_TOLERANCE, 0},
+{94, 3196395192u, 3187933072u, 3187933072u, 0, J1_TOLERANCE, 0},
+{95, 3196059648u, 3187540310u, 3187540310u, 0, J1_TOLERANCE, 0},
+{96, 3195388559u, 3186884265u, 3186884265u, 0, J1_TOLERANCE, 0},
+{97, 3194717471u, 3186227024u, 3186227024u, 0, J1_TOLERANCE, 0},
+{98, 3194046382u, 3185568632u, 3185568632u, 0, J1_TOLERANCE, 0},
+{99, 3193375293u, 3184909141u, 3184909141u, 0, J1_TOLERANCE, 0},
+{100, 3192704205u, 3184248599u, 3184248599u, 0, J1_TOLERANCE, 0},
+{101, 3192033116u, 3183587058u, 3183587058u, 0, J1_TOLERANCE, 0},
+{102, 3191362028u, 3182924563u, 3182924563u, 0, J1_TOLERANCE, 0},
+{103, 3190690939u, 3182261167u, 3182261167u, 0, J1_TOLERANCE, 0},
+{104, 3190019850u, 3181596918u, 3181596918u, 0, J1_TOLERANCE, 0},
+{105, 3189348762u, 3180931869u, 3180931869u, 0, J1_TOLERANCE, 0},
+{106, 3188677673u, 3180266065u, 3180266065u, 0, J1_TOLERANCE, 0},
+{107, 3188006584u, 3179599559u, 3179599559u, 0, J1_TOLERANCE, 0},
+{108, 3186999951u, 3178582370u, 3178582370u, 0, J1_TOLERANCE, 0},
+{109, 3185657774u, 3177246847u, 3177246847u, 0, J1_TOLERANCE, 0},
+{110, 3184315597u, 3175910219u, 3175910219u, 0, J1_TOLERANCE, 0},
+{111, 3182973420u, 3174572585u, 3174572585u, 0, J1_TOLERANCE, 0},
+{112, 3181631242u, 3173234046u, 3173234046u, 0, J1_TOLERANCE, 0},
+{113, 3180289065u, 3171894704u, 3171894704u, 0, J1_TOLERANCE, 0},
+{114, 3178611343u, 3170215488u, 3170215488u, 0, J1_TOLERANCE, 0},
+{115, 3175926989u, 3167534188u, 3167534188u, 0, J1_TOLERANCE, 0},
+{116, 3173242634u, 3164851878u, 3164851878u, 0, J1_TOLERANCE, 0},
+{117, 3170222735u, 3161832315u, 3161832315u, 0, J1_TOLERANCE, 0},
+{118, 3164854026u, 3156464881u, 3156464881u, 0, J1_TOLERANCE, 0},
+{119, 3156465418u, 3148076676u, 3148076676u, 0, J1_TOLERANCE, 0},
+{120, 1008981770u, 1000593028u, 1000593028u, 0, J1_TOLERANCE, 0},
+{121, 1017370378u, 1008981233u, 1008981233u, 0, J1_TOLERANCE, 0},
+{122, 1022739087u, 1014348667u, 1014348667u, 0, J1_TOLERANCE, 0},
+{123, 1025758986u, 1017368230u, 1017368230u, 0, J1_TOLERANCE, 0},
+{124, 1028443341u, 1020050540u, 1020050540u, 0, J1_TOLERANCE, 0},
+{125, 1031127695u, 1022731840u, 1022731840u, 0, J1_TOLERANCE, 0},
+{126, 1032805417u, 1024411056u, 1024411056u, 0, J1_TOLERANCE, 0},
+{127, 1034147594u, 1025750398u, 1025750398u, 0, J1_TOLERANCE, 0},
+{128, 1035489772u, 1027088937u, 1027088937u, 0, J1_TOLERANCE, 0},
+{129, 1036831949u, 1028426571u, 1028426571u, 0, J1_TOLERANCE, 0},
+{130, 1038174126u, 1029763199u, 1029763199u, 0, J1_TOLERANCE, 0},
+{131, 1039516303u, 1031098722u, 1031098722u, 0, J1_TOLERANCE, 0},
+{132, 1040522936u, 1032115911u, 1032115911u, 0, J1_TOLERANCE, 0},
+{133, 1041194025u, 1032782417u, 1032782417u, 0, J1_TOLERANCE, 0},
+{134, 1041865114u, 1033448221u, 1033448221u, 0, J1_TOLERANCE, 0},
+{135, 1042536202u, 1034113270u, 1034113270u, 0, J1_TOLERANCE, 0},
+{136, 1043207291u, 1034777519u, 1034777519u, 0, J1_TOLERANCE, 0},
+{137, 1043878380u, 1035440915u, 1035440915u, 0, J1_TOLERANCE, 0},
+{138, 1044549468u, 1036103410u, 1036103410u, 0, J1_TOLERANCE, 0},
+{139, 1045220557u, 1036764951u, 1036764951u, 0, J1_TOLERANCE, 0},
+{140, 1045891645u, 1037425493u, 1037425493u, 0, J1_TOLERANCE, 0},
+{141, 1046562734u, 1038084984u, 1038084984u, 0, J1_TOLERANCE, 0},
+{142, 1047233823u, 1038743376u, 1038743376u, 0, J1_TOLERANCE, 0},
+{143, 1047904911u, 1039400617u, 1039400617u, 0, J1_TOLERANCE, 0},
+{144, 1048576000u, 1040056662u, 1040056662u, 0, J1_TOLERANCE, 0},
+{145, 1048911544u, 1040449424u, 1040449424u, 0, J1_TOLERANCE, 0},
+{146, 1049247089u, 1040776175u, 1040776175u, 0, J1_TOLERANCE, 0},
+{147, 1049582633u, 1041102251u, 1041102251u, 0, J1_TOLERANCE, 0},
+{148, 1049918177u, 1041427632u, 1041427632u, 0, J1_TOLERANCE, 0},
+{149, 1050253722u, 1041752291u, 1041752291u, 0, J1_TOLERANCE, 0},
+{150, 1050589266u, 1042076205u, 1042076205u, 0, J1_TOLERANCE, 0},
+{151, 1050924810u, 1042399349u, 1042399349u, 0, J1_TOLERANCE, 0},
+{152, 1051260355u, 1042721699u, 1042721699u, 0, J1_TOLERANCE, 0},
+{153, 1051595899u, 1043043230u, 1043043230u, 0, J1_TOLERANCE, 0},
+{154, 1051931443u, 1043363920u, 1043363920u, 0, J1_TOLERANCE, 0},
+{155, 1052266988u, 1043683745u, 1043683745u, 0, J1_TOLERANCE, 0},
+{156, 1052602532u, 1044002678u, 1044002678u, 0, J1_TOLERANCE, 0},
+{157, 1052938076u, 1044320698u, 1044320698u, 0, J1_TOLERANCE, 0},
+{158, 1053273620u, 1044637782u, 1044637782u, 0, J1_TOLERANCE, 0},
+{159, 1053609165u, 1044953905u, 1044953905u, 0, J1_TOLERANCE, 0},
+{160, 1053944709u, 1045269043u, 1045269043u, 0, J1_TOLERANCE, 0},
+{161, 1054280253u, 1045583173u, 1045583173u, 0, J1_TOLERANCE, 0},
+{162, 1054615798u, 1045896273u, 1045896273u, 0, J1_TOLERANCE, 0},
+{163, 1054951342u, 1046208317u, 1046208317u, 0, J1_TOLERANCE, 0},
+{164, 1055286886u, 1046519283u, 1046519283u, 0, J1_TOLERANCE, 0},
+{165, 1055622431u, 1046829150u, 1046829150u, 0, J1_TOLERANCE, 0},
+{166, 1055957975u, 1047137891u, 1047137891u, 0, J1_TOLERANCE, 0},
+{167, 1056293519u, 1047445487u, 1047445487u, 0, J1_TOLERANCE, 0},
+{168, 1056629064u, 1047751912u, 1047751912u, 0, J1_TOLERANCE, 0},
+{169, 1056964608u, 1048057145u, 1048057145u, 0, J1_TOLERANCE, 0},
+{170, 1057132380u, 1048361163u, 1048361163u, 0, J1_TOLERANCE, 0},
+{171, 1057300152u, 1048619971u, 1048619971u, 0, J1_TOLERANCE, 0},
+{172, 1057467924u, 1048770731u, 1048770731u, 0, J1_TOLERANCE, 0},
+{173, 1057635697u, 1048920851u, 1048920851u, 0, J1_TOLERANCE, 0},
+{174, 1057803469u, 1049070318u, 1049070318u, 0, J1_TOLERANCE, 0},
+{175, 1057971241u, 1049219120u, 1049219120u, 0, J1_TOLERANCE, 0},
+{176, 1058139013u, 1049367249u, 1049367249u, 0, J1_TOLERANCE, 0},
+{177, 1058306785u, 1049514693u, 1049514693u, 0, J1_TOLERANCE, 0},
+{178, 1058474557u, 1049661440u, 1049661440u, 0, J1_TOLERANCE, 0},
+{179, 1058642330u, 1049807482u, 1049807482u, 0, J1_TOLERANCE, 0},
+{180, 1058810102u, 1049952803u, 1049952803u, 0, J1_TOLERANCE, 0},
+{181, 1058977874u, 1050097398u, 1050097398u, 0, J1_TOLERANCE, 0},
+{182, 1059145646u, 1050241252u, 1050241252u, 0, J1_TOLERANCE, 0},
+{183, 1059313418u, 1050384356u, 1050384356u, 0, J1_TOLERANCE, 0},
+{184, 1059481190u, 1050526702u, 1050526702u, 0, J1_TOLERANCE, 0},
+{185, 1059648963u, 1050668277u, 1050668277u, 0, J1_TOLERANCE, 0},
+{186, 1059816735u, 1050809069u, 1050809069u, 0, J1_TOLERANCE, 0},
+{187, 1059984507u, 1050949070u, 1050949070u, 0, J1_TOLERANCE, 0},
+{188, 1060152279u, 1051088270u, 1051088270u, 0, J1_TOLERANCE, 0},
+{189, 1060320051u, 1051226657u, 1051226657u, 0, J1_TOLERANCE, 0},
+{190, 1060487823u, 1051364223u, 1051364223u, 0, J1_TOLERANCE, 0},
+{191, 1060655596u, 1051500956u, 1051500956u, 0, J1_TOLERANCE, 0},
+{192, 1060823368u, 1051636847u, 1051636847u, 0, J1_TOLERANCE, 0},
+{193, 1060991140u, 1051771886u, 1051771886u, 0, J1_TOLERANCE, 0},
+{194, 1061158912u, 1051906063u, 1051906063u, 0, J1_TOLERANCE, 0},
+{195, 1061326684u, 1052039368u, 1052039368u, 0, J1_TOLERANCE, 0},
+{196, 1061494456u, 1052171791u, 1052171791u, 0, J1_TOLERANCE, 0},
+{197, 1061662228u, 1052303323u, 1052303323u, 0, J1_TOLERANCE, 0},
+{198, 1061830001u, 1052433956u, 1052433956u, 0, J1_TOLERANCE, 0},
+{199, 1061997773u, 1052563677u, 1052563677u, 0, J1_TOLERANCE, 0},
+{200, 1062165545u, 1052692479u, 1052692479u, 0, J1_TOLERANCE, 0},
+{201, 1062333317u, 1052820353u, 1052820353u, 0, J1_TOLERANCE, 0},
+{202, 1062501089u, 1052947287u, 1052947287u, 0, J1_TOLERANCE, 0},
+{203, 1062668861u, 1053073274u, 1053073274u, 0, J1_TOLERANCE, 0},
+{204, 1062836634u, 1053198306u, 1053198306u, 0, J1_TOLERANCE, 0},
+{205, 1063004406u, 1053322370u, 1053322370u, 0, J1_TOLERANCE, 0},
+{206, 1063172178u, 1053445462u, 1053445462u, 0, J1_TOLERANCE, 0},
+{207, 1063339950u, 1053567569u, 1053567569u, 0, J1_TOLERANCE, 0},
+{208, 1063507722u, 1053688684u, 1053688684u, 0, J1_TOLERANCE, 0},
+{209, 1063675494u, 1053808799u, 1053808799u, 0, J1_TOLERANCE, 0},
+{210, 1063843267u, 1053927904u, 1053927904u, 0, J1_TOLERANCE, 0},
+{211, 1064011039u, 1054045991u, 1054045991u, 0, J1_TOLERANCE, 0},
+{212, 1064178811u, 1054163051u, 1054163051u, 0, J1_TOLERANCE, 0},
+{213, 1064346583u, 1054279076u, 1054279076u, 0, J1_TOLERANCE, 0},
+{214, 1064514355u, 1054394059u, 1054394059u, 0, J1_TOLERANCE, 0},
+{215, 1064682127u, 1054507989u, 1054507989u, 0, J1_TOLERANCE, 0},
+{216, 1064849900u, 1054620862u, 1054620862u, 0, J1_TOLERANCE, 0},
+{217, 1065017672u, 1054732665u, 1054732665u, 0, J1_TOLERANCE, 0},
+{218, 1065185444u, 1054843394u, 1054843394u, 0, J1_TOLERANCE, 0},
+{219, 1065353216u, 1054953040u, 1054953040u, 0, J1_TOLERANCE, 0},
+{220, 1065437102u, 1055061594u, 1055061594u, 0, J1_TOLERANCE, 0},
+{221, 1065520988u, 1055169050u, 1055169050u, 0, J1_TOLERANCE, 0},
+{222, 1065604874u, 1055275400u, 1055275400u, 0, J1_TOLERANCE, 0},
+{223, 1065688760u, 1055380635u, 1055380635u, 0, J1_TOLERANCE, 0},
+{224, 1065772646u, 1055484749u, 1055484749u, 0, J1_TOLERANCE, 0},
+{225, 1065856532u, 1055587736u, 1055587736u, 0, J1_TOLERANCE, 0},
+{226, 1065940419u, 1055689588u, 1055689588u, 0, J1_TOLERANCE, 0},
+{227, 1066024305u, 1055790295u, 1055790295u, 0, J1_TOLERANCE, 0},
+{228, 1066108191u, 1055889853u, 1055889853u, 0, J1_TOLERANCE, 0},
+{229, 1066192077u, 1055988254u, 1055988254u, 0, J1_TOLERANCE, 0},
+{230, 1066275963u, 1056085492u, 1056085492u, 0, J1_TOLERANCE, 0},
+{231, 1066359849u, 1056181560u, 1056181560u, 0, J1_TOLERANCE, 0},
+{232, 1066443735u, 1056276451u, 1056276451u, 0, J1_TOLERANCE, 0},
+{233, 1066527621u, 1056370159u, 1056370159u, 0, J1_TOLERANCE, 0},
+{234, 1066611507u, 1056462676u, 1056462676u, 0, J1_TOLERANCE, 0},
+{235, 1066695393u, 1056553998u, 1056553998u, 0, J1_TOLERANCE, 0},
+{236, 1066779279u, 1056644116u, 1056644116u, 0, J1_TOLERANCE, 0},
+{237, 1066863165u, 1056733027u, 1056733027u, 0, J1_TOLERANCE, 0},
+{238, 1066947052u, 1056820724u, 1056820724u, 0, J1_TOLERANCE, 0},
+{239, 3234402267u, 1046051504u, 1046051504u, 0, J1_TOLERANCE, 0},
+{240, 3231108068u, 1049638262u, 1049638262u, 0, J1_TOLERANCE, 0},
+{241, 3226013659u, 3197221145u, 3197221145u, 0, J1_TOLERANCE, 0},
+{242, 3217625051u, 3205569378u, 3205569378u, 0, J1_TOLERANCE, 0},
+{243, 0u, 0u, 0u, 0, J1_TOLERANCE, 0},
+{244, 1070141403u, 1058085730u, 1058085730u, 0, J1_TOLERANCE, 0},
+{245, 1078530011u, 1049737497u, 1049737497u, 0, J1_TOLERANCE, 0},
+{246, 1083624420u, 3197121910u, 3197121910u, 0, J1_TOLERANCE, 0},
+{247, 3253731328u, 1039348685u, 1039348685u, 0, J1_TOLERANCE, 0},
+{248, 3252840038u, 3184567008u, 3184567008u, 0, J1_TOLERANCE, 0},
+{249, 3251948749u, 3184209412u, 3184209412u, 0, J1_TOLERANCE, 0},
+{250, 3251057459u, 1040848794u, 1040848794u, 0, J1_TOLERANCE, 0},
+{251, 3250166170u, 1032875620u, 1032875620u, 0, J1_TOLERANCE, 0},
+{252, 3249274880u, 3190278356u, 3190278356u, 0, J1_TOLERANCE, 0},
+{253, 3248383590u, 3171314413u, 3171314413u, 0, J1_TOLERANCE, 0},
+{254, 3247492301u, 1044371641u, 1044371641u, 0, J1_TOLERANCE, 0},
+{255, 3246601011u, 3160647523u, 3160647523u, 0, J1_TOLERANCE, 0},
+{256, 3245028147u, 3192989500u, 3192989500u, 0, J1_TOLERANCE, 0},
+{257, 3243245568u, 1032848118u, 1032848118u, 0, J1_TOLERANCE, 0},
+{258, 3241462989u, 1046177193u, 1046177193u, 0, J1_TOLERANCE, 0},
+{259, 3239680410u, 3188645785u, 3188645785u, 0, J1_TOLERANCE, 0},
+{260, 3237792973u, 3193991324u, 3193991324u, 0, J1_TOLERANCE, 0},
+{261, 3234227814u, 1047429570u, 1047429570u, 0, J1_TOLERANCE, 0},
+{262, 3230662656u, 1047304985u, 1047304985u, 0, J1_TOLERANCE, 0},
+{263, 3224580915u, 3201418603u, 3201418603u, 0, J1_TOLERANCE, 0},
+{264, 3213675725u, 3203471902u, 3203471902u, 0, J1_TOLERANCE, 0},
+{265, 1058642330u, 1049807482u, 1049807482u, 0, J1_TOLERANCE, 0},
+{266, 1075000115u, 1057633557u, 1057633557u, 0, J1_TOLERANCE, 0},
+{267, 1082130432u, 3179757989u, 3179757989u, 0, J1_TOLERANCE, 0},
+{268, 1085695590u, 3198547630u, 3198547630u, 0, J1_TOLERANCE, 0},
+{269, 1089260749u, 1038123701u, 1038123701u, 0, J1_TOLERANCE, 0},
+{270, 1091672474u, 1047396948u, 1047396948u, 0, J1_TOLERANCE, 0},
+{271, 1093455053u, 3188823064u, 3188823064u, 0, J1_TOLERANCE, 0},
+{272, 1095237632u, 3190387868u, 3190387868u, 0, J1_TOLERANCE, 0},
+{273, 1097020211u, 1042711397u, 1042711397u, 0, J1_TOLERANCE, 0},
+{274, 1098802790u, 1037909458u, 1037909458u, 0, J1_TOLERANCE, 0},
+{275, 1099746509u, 3190821313u, 3190821313u, 0, J1_TOLERANCE, 0},
+{276, 1100637798u, 3177642610u, 3177642610u, 0, J1_TOLERANCE, 0},
+{277, 1101529088u, 1043282474u, 1043282474u, 0, J1_TOLERANCE, 0},
+{278, 1102420378u, 1009037734u, 1009037734u, 0, J1_TOLERANCE, 0},
+{279, 1103311667u, 3190100663u, 3190100663u, 0, J1_TOLERANCE, 0},
+{280, 1104202957u, 1022984661u, 1022984661u, 0, J1_TOLERANCE, 0},
+{281, 1105094246u, 1041426372u, 1041426372u, 0, J1_TOLERANCE, 0},
+{282, 1105985536u, 3179524627u, 3179524627u, 0, J1_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_J1_H multiple inclusion protection
+
+// EOF j1f.h
diff --git a/packages/language/c/libm/current/tests/vectors/jnf.c b/packages/language/c/libm/current/tests/vectors/jnf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/jnf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      jnf.c
+//
+//      Test of jnf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/jnf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(jnf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &jnf, CYG_LIBM_TEST_VEC_INT,
+                     CYG_LIBM_TEST_VEC_FLOAT, CYG_LIBM_TEST_VEC_FLOAT,
+                     &jnf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("jnf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("jnf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library jnf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "jnf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF jnf.c
diff --git a/packages/language/c/libm/current/tests/vectors/jnf.h b/packages/language/c/libm/current/tests/vectors/jnf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/jnf.h
@@ -0,0 +1,279 @@
+#ifndef CYGONCE_LIBM_JN_H
+#define CYGONCE_LIBM_JN_H
+//===========================================================================
+//
+//      jnf.h
+//
+//      Test vectors for testing of jnf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/jnf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define JN_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t jnf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+/*{0, 0u, 0u, 1065353216u, 0, JN_TOLERANCE, 0},
+{1, 1065353216u, 0u, 0u, 0, JN_TOLERANCE, 0},
+{2, 1073741824u, 0u, 0u, 0, JN_TOLERANCE, 0},
+{3, 1077936128u, 0u, 0u, 0, JN_TOLERANCE, 0},
+{4, 1082130432u, 0u, 0u, 0, JN_TOLERANCE, 0},
+{5, 0u, 1028443341u, 1065342732u, 0, JN_TOLERANCE, 0},
+{6, 1065353216u, 1028443341u, 1020050539u, 0, JN_TOLERANCE, 0},
+{7, 1073741824u, 1028443341u, 967036493u, 0, JN_TOLERANCE, 0},
+{8, 1077936128u, 1028443341u, 909032513u, 0, JN_TOLERANCE, 0},
+{9, 1082130432u, 1028443341u, 848022252u, 0, JN_TOLERANCE, 0},
+{10, 0u, 1036831949u, 1065311299u, 0, JN_TOLERANCE, 0},*/
+{11, 1065353216u, 1036831949u, 1028426571u, 0, JN_TOLERANCE, 0},
+{12, 1073741824u, 1036831949u, 983807001u, 0, JN_TOLERANCE, 0},
+{13, 1077936128u, 1036831949u, 934192970u, 0, JN_TOLERANCE, 0},
+{14, 1082130432u, 1036831949u, 881573249u, 0, JN_TOLERANCE, 0},
+{15, 0u, 1041865114u, 1065258977u, 0, JN_TOLERANCE, 0},
+{16, 1065353216u, 1041865114u, 1033448221u, 0, JN_TOLERANCE, 0},
+{17, 1073741824u, 1041865114u, 993524098u, 0, JN_TOLERANCE, 0},
+{18, 1077936128u, 1041865114u, 949174191u, 0, JN_TOLERANCE, 0},
+{19, 1082130432u, 1041865114u, 900775820u, 0, JN_TOLERANCE, 0},
+{20, 0u, 1045220557u, 1065185863u, 0, JN_TOLERANCE, 0},
+{21, 1065353216u, 1045220557u, 1036764952u, 0, JN_TOLERANCE, 0},
+{22, 1073741824u, 1045220557u, 1000557416u, 0, JN_TOLERANCE, 0},
+{23, 1077936128u, 1045220557u, 959337346u, 0, JN_TOLERANCE, 0},
+{24, 1082130432u, 1045220557u, 915113951u, 0, JN_TOLERANCE, 0},
+{25, 0u, 1048576000u, 1065092094u, 0, JN_TOLERANCE, 0},
+{26, 1065353216u, 1048576000u, 1040056661u, 0, JN_TOLERANCE, 0},
+{27, 1073741824u, 1048576000u, 1006545749u, 0, JN_TOLERANCE, 0},
+{28, 1077936128u, 1048576000u, 967442500u, 0, JN_TOLERANCE, 0},
+{29, 1082130432u, 1048576000u, 925508176u, 0, JN_TOLERANCE, 0},
+{30, 0u, 1050253722u, 1064977847u, 0, JN_TOLERANCE, 0},
+{31, 1065353216u, 1050253722u, 1041752291u, 0, JN_TOLERANCE, 0},
+{32, 1073741824u, 1050253722u, 1010233605u, 0, JN_TOLERANCE, 0},
+{33, 1077936128u, 1050253722u, 974299360u, 0, JN_TOLERANCE, 0},
+{34, 1082130432u, 1050253722u, 934291206u, 0, JN_TOLERANCE, 0},
+{35, 0u, 1051931443u, 1064843334u, 0, JN_TOLERANCE, 0},
+{36, 1065353216u, 1051931443u, 1043363920u, 0, JN_TOLERANCE, 0},
+{37, 1073741824u, 1051931443u, 1014518823u, 0, JN_TOLERANCE, 0},
+{38, 1077936128u, 1051931443u, 979918350u, 0, JN_TOLERANCE, 0},
+{39, 1082130432u, 1051931443u, 941811754u, 0, JN_TOLERANCE, 0},
+{40, 0u, 1053609165u, 1064688808u, 0, JN_TOLERANCE, 0},
+{41, 1065353216u, 1053609165u, 1044953905u, 0, JN_TOLERANCE, 0},
+{42, 1073741824u, 1053609165u, 1017227927u, 0, JN_TOLERANCE, 0},
+{43, 1077936128u, 1053609165u, 984417699u, 0, JN_TOLERANCE, 0},
+{44, 1082130432u, 1053609165u, 948613636u, 0, JN_TOLERANCE, 0},
+{45, 0u, 1055286886u, 1064514559u, 0, JN_TOLERANCE, 0},
+{46, 1065353216u, 1055286886u, 1046519284u, 0, JN_TOLERANCE, 0},
+{47, 1073741824u, 1055286886u, 1019994628u, 0, JN_TOLERANCE, 0},
+{48, 1077936128u, 1055286886u, 989180633u, 0, JN_TOLERANCE, 0},
+{49, 1082130432u, 1055286886u, 954052828u, 0, JN_TOLERANCE, 0},
+{50, 0u, 1056964608u, 1064320911u, 0, JN_TOLERANCE, 0},
+{51, 1065353216u, 1056964608u, 1048057145u, 0, JN_TOLERANCE, 0},
+{52, 1073741824u, 1056964608u, 1023063370u, 0, JN_TOLERANCE, 0},
+{53, 1077936128u, 1056964608u, 992478272u, 0, JN_TOLERANCE, 0},
+{54, 1082130432u, 1056964608u, 958958431u, 0, JN_TOLERANCE, 0},
+{55, 0u, 1057803469u, 1064108226u, 0, JN_TOLERANCE, 0},
+{56, 1065353216u, 1057803469u, 1049070317u, 0, JN_TOLERANCE, 0},
+{57, 1073741824u, 1057803469u, 1024918320u, 0, JN_TOLERANCE, 0},
+{58, 1077936128u, 1057803469u, 996074782u, 0, JN_TOLERANCE, 0},
+{59, 1082130432u, 1057803469u, 964042258u, 0, JN_TOLERANCE, 0},
+{60, 0u, 1058642330u, 1063876903u, 0, JN_TOLERANCE, 0},
+{61, 1065353216u, 1058642330u, 1049807481u, 0, JN_TOLERANCE, 0},
+{62, 1073741824u, 1058642330u, 1026742828u, 0, JN_TOLERANCE, 0},
+{63, 1077936128u, 1058642330u, 999303935u, 0, JN_TOLERANCE, 0},
+{64, 1082130432u, 1058642330u, 967690547u, 0, JN_TOLERANCE, 0},
+{65, 0u, 1059481190u, 1063627371u, 0, JN_TOLERANCE, 0},
+{66, 1065353216u, 1059481190u, 1050526702u, 0, JN_TOLERANCE, 0},
+{67, 1073741824u, 1059481190u, 1028705720u, 0, JN_TOLERANCE, 0},
+{68, 1077936128u, 1059481190u, 1001821225u, 0, JN_TOLERANCE, 0},
+{69, 1082130432u, 1059481190u, 971939318u, 0, JN_TOLERANCE, 0},
+{70, 0u, 1060320051u, 1063360098u, 0, JN_TOLERANCE, 0},
+{71, 1065353216u, 1060320051u, 1051226657u, 0, JN_TOLERANCE, 0},
+{72, 1073741824u, 1060320051u, 1030802068u, 0, JN_TOLERANCE, 0},
+{73, 1077936128u, 1060320051u, 1004737064u, 0, JN_TOLERANCE, 0},
+{74, 1082130432u, 1060320051u, 975171307u, 0, JN_TOLERANCE, 0},
+{75, 0u, 1061158912u, 1063075579u, 0, JN_TOLERANCE, 0},
+{76, 1065353216u, 1061158912u, 1051906063u, 0, JN_TOLERANCE, 0},
+{77, 1073741824u, 1061158912u, 1032412696u, 0, JN_TOLERANCE, 0},
+{78, 1077936128u, 1061158912u, 1007354389u, 0, JN_TOLERANCE, 0},
+{79, 1082130432u, 1061158912u, 978452199u, 0, JN_TOLERANCE, 0},
+{80, 0u, 1061997773u, 1062774346u, 0, JN_TOLERANCE, 0},
+{81, 1065353216u, 1061997773u, 1052563677u, 0, JN_TOLERANCE, 0},
+{82, 1073741824u, 1061997773u, 1033586264u, 0, JN_TOLERANCE, 0},
+{83, 1077936128u, 1061997773u, 1009246734u, 0, JN_TOLERANCE, 0},
+{84, 1082130432u, 1061997773u, 981951802u, 0, JN_TOLERANCE, 0},
+{85, 0u, 1062836634u, 1062456957u, 0, JN_TOLERANCE, 0},
+{86, 1065353216u, 1062836634u, 1053198305u, 0, JN_TOLERANCE, 0},
+{87, 1073741824u, 1062836634u, 1034818178u, 0, JN_TOLERANCE, 0},
+{88, 1077936128u, 1062836634u, 1011372844u, 0, JN_TOLERANCE, 0},
+{89, 1082130432u, 1062836634u, 984340071u, 0, JN_TOLERANCE, 0},
+{90, 0u, 1063675494u, 1062124001u, 0, JN_TOLERANCE, 0},
+{91, 1065353216u, 1063675494u, 1053808798u, 0, JN_TOLERANCE, 0},
+{92, 1073741824u, 1063675494u, 1036105335u, 0, JN_TOLERANCE, 0},
+{93, 1077936128u, 1063675494u, 1013742772u, 0, JN_TOLERANCE, 0},
+{94, 1082130432u, 1063675494u, 987170764u, 0, JN_TOLERANCE, 0},
+{95, 0u, 1064514355u, 1061776097u, 0, JN_TOLERANCE, 0},
+{96, 1065353216u, 1064514355u, 1054394058u, 0, JN_TOLERANCE, 0},
+{97, 1073741824u, 1064514355u, 1037444489u, 0, JN_TOLERANCE, 0},
+{98, 1077936128u, 1064514355u, 1015693678u, 0, JN_TOLERANCE, 0},
+{99, 1082130432u, 1064514355u, 990173788u, 0, JN_TOLERANCE, 0},
+{100, 0u, 1065353216u, 1061413887u, 0, JN_TOLERANCE, 0},
+{101, 1065353216u, 1065353216u, 1054953039u, 0, JN_TOLERANCE, 0},
+{102, 1073741824u, 1065353216u, 1038832261u, 0, JN_TOLERANCE, 0},
+{103, 1077936128u, 1065353216u, 1017135956u, 0, JN_TOLERANCE, 0},
+{104, 1082130432u, 1065353216u, 992104219u, 0, JN_TOLERANCE, 0},
+{105, 0u, 1065772646u, 1061038041u, 0, JN_TOLERANCE, 0},
+{106, 1065353216u, 1065772646u, 1055484750u, 0, JN_TOLERANCE, 0},
+{107, 1073741824u, 1065772646u, 1040226267u, 0, JN_TOLERANCE, 0},
+{108, 1077936128u, 1065772646u, 1018712809u, 0, JN_TOLERANCE, 0},
+{109, 1082130432u, 1065772646u, 994329897u, 0, JN_TOLERANCE, 0},
+{110, 0u, 1066192077u, 1060649254u, 0, JN_TOLERANCE, 0},
+{111, 1065353216u, 1066192077u, 1055988254u, 0, JN_TOLERANCE, 0},
+{112, 1073741824u, 1066192077u, 1040963449u, 0, JN_TOLERANCE, 0},
+{113, 1077936128u, 1066192077u, 1020427605u, 0, JN_TOLERANCE, 0},
+{114, 1082130432u, 1066192077u, 996876707u, 0, JN_TOLERANCE, 0},
+{115, 0u, 1066611507u, 1060248241u, 0, JN_TOLERANCE, 0},
+{116, 1065353216u, 1066611507u, 1056462676u, 0, JN_TOLERANCE, 0},
+{117, 1073741824u, 1066611507u, 1041719505u, 0, JN_TOLERANCE, 0},
+{118, 1077936128u, 1066611507u, 1022283262u, 0, JN_TOLERANCE, 0},
+{119, 1082130432u, 1066611507u, 999007660u, 0, JN_TOLERANCE, 0},
+{120, 0u, 1067030938u, 1059835739u, 0, JN_TOLERANCE, 0},
+{121, 1065353216u, 1067030938u, 1056907198u, 0, JN_TOLERANCE, 0},
+{122, 1073741824u, 1067030938u, 1042492516u, 0, JN_TOLERANCE, 0},
+{123, 1077936128u, 1067030938u, 1023846206u, 0, JN_TOLERANCE, 0},
+{124, 1082130432u, 1067030938u, 1000641838u, 0, JN_TOLERANCE, 0},
+{125, 0u, 1067450368u, 1059412506u, 0, JN_TOLERANCE, 0},
+{126, 1065353216u, 1067450368u, 1057142837u, 0, JN_TOLERANCE, 0},
+{127, 1073741824u, 1067450368u, 1043280515u, 0, JN_TOLERANCE, 0},
+{128, 1077936128u, 1067450368u, 1024918343u, 0, JN_TOLERANCE, 0},
+{129, 1082130432u, 1067450368u, 1002476495u, 0, JN_TOLERANCE, 0},
+{130, 0u, 1067869798u, 1058979317u, 0, JN_TOLERANCE, 0},
+{131, 1065353216u, 1067869798u, 1057334097u, 0, JN_TOLERANCE, 0},
+{132, 1073741824u, 1067869798u, 1044081498u, 0, JN_TOLERANCE, 0},
+{133, 1077936128u, 1067869798u, 1026063882u, 0, JN_TOLERANCE, 0},
+{134, 1082130432u, 1067869798u, 1004525115u, 0, JN_TOLERANCE, 0},
+{135, 0u, 1068289229u, 1058536963u, 0, JN_TOLERANCE, 0},
+{136, 1065353216u, 1068289229u, 1057509369u, 0, JN_TOLERANCE, 0},
+{137, 1073741824u, 1068289229u, 1044893419u, 0, JN_TOLERANCE, 0},
+{138, 1077936128u, 1068289229u, 1027283330u, 0, JN_TOLERANCE, 0},
+{139, 1082130432u, 1068289229u, 1006717070u, 0, JN_TOLERANCE, 0},
+{140, 0u, 1068708659u, 1058086251u, 0, JN_TOLERANCE, 0},
+{141, 1065353216u, 1068708659u, 1057668374u, 0, JN_TOLERANCE, 0},
+{142, 1073741824u, 1068708659u, 1045714203u, 0, JN_TOLERANCE, 0},
+{143, 1077936128u, 1068708659u, 1028576945u, 0, JN_TOLERANCE, 0},
+{144, 1082130432u, 1068708659u, 1007975536u, 0, JN_TOLERANCE, 0},
+{145, 0u, 1069128090u, 1057628001u, 0, JN_TOLERANCE, 0},
+{146, 1065353216u, 1069128090u, 1057810862u, 0, JN_TOLERANCE, 0},
+{147, 1073741824u, 1069128090u, 1046541746u, 0, JN_TOLERANCE, 0},
+{148, 1077936128u, 1069128090u, 1029944734u, 0, JN_TOLERANCE, 0},
+{149, 1082130432u, 1069128090u, 1009361087u, 0, JN_TOLERANCE, 0},
+{150, 0u, 1069547520u, 1057163043u, 0, JN_TOLERANCE, 0},
+{151, 1065353216u, 1069547520u, 1057936621u, 0, JN_TOLERANCE, 0},
+{152, 1073741824u, 1069547520u, 1047373924u, 0, JN_TOLERANCE, 0},
+{153, 1077936128u, 1069547520u, 1031386454u, 0, JN_TOLERANCE, 0},
+{154, 1082130432u, 1069547520u, 1010880288u, 0, JN_TOLERANCE, 0},
+{155, 0u, 1069966950u, 1056419833u, 0, JN_TOLERANCE, 0},
+{156, 1065353216u, 1069966950u, 1058045471u, 0, JN_TOLERANCE, 0},
+{157, 1073741824u, 1069966950u, 1048208593u, 0, JN_TOLERANCE, 0},
+{158, 1077936128u, 1069966950u, 1032350194u, 0, JN_TOLERANCE, 0},
+{159, 1082130432u, 1069966950u, 1012539586u, 0, JN_TOLERANCE, 0},
+{160, 0u, 1070386381u, 1055468153u, 0, JN_TOLERANCE, 0},
+{161, 1065353216u, 1070386381u, 1058137267u, 0, JN_TOLERANCE, 0},
+{162, 1073741824u, 1070386381u, 1048809799u, 0, JN_TOLERANCE, 0},
+{163, 1077936128u, 1070386381u, 1033144108u, 0, JN_TOLERANCE, 0},
+{164, 1082130432u, 1070386381u, 1014345284u, 0, JN_TOLERANCE, 0},
+{165, 0u, 1070805811u, 1054508151u, 0, JN_TOLERANCE, 0},
+{166, 1065353216u, 1070805811u, 1058211899u, 0, JN_TOLERANCE, 0},
+{167, 1073741824u, 1070805811u, 1049226388u, 0, JN_TOLERANCE, 0},
+{168, 1077936128u, 1070805811u, 1033973855u, 0, JN_TOLERANCE, 0},
+{169, 1082130432u, 1070805811u, 1015662539u, 0, JN_TOLERANCE, 0},
+{170, 0u, 1071225242u, 1053541548u, 0, JN_TOLERANCE, 0},
+{171, 1065353216u, 1071225242u, 1058269292u, 0, JN_TOLERANCE, 0},
+{172, 1073741824u, 1071225242u, 1049640982u, 0, JN_TOLERANCE, 0},
+{173, 1077936128u, 1071225242u, 1034838806u, 0, JN_TOLERANCE, 0},
+{174, 1082130432u, 1071225242u, 1016720878u, 0, JN_TOLERANCE, 0},
+{175, 0u, 1071644672u, 1052570069u, 0, JN_TOLERANCE, 0},
+{176, 1065353216u, 1071644672u, 1058309406u, 0, JN_TOLERANCE, 0},
+{177, 1073741824u, 1071644672u, 1050052500u, 0, JN_TOLERANCE, 0},
+{178, 1077936128u, 1071644672u, 1035738201u, 0, JN_TOLERANCE, 0},
+{179, 1082130432u, 1071644672u, 1017861291u, 0, JN_TOLERANCE, 0},
+{180, 0u, 1072064102u, 1051595443u, 0, JN_TOLERANCE, 0},
+{181, 1065353216u, 1072064102u, 1058332236u, 0, JN_TOLERANCE, 0},
+{182, 1073741824u, 1072064102u, 1050459864u, 0, JN_TOLERANCE, 0},
+{183, 1077936128u, 1072064102u, 1036671158u, 0, JN_TOLERANCE, 0},
+{184, 1082130432u, 1072064102u, 1019086495u, 0, JN_TOLERANCE, 0},
+{185, 0u, 1072483533u, 1050619397u, 0, JN_TOLERANCE, 0},
+{186, 1065353216u, 1072483533u, 1058337811u, 0, JN_TOLERANCE, 0},
+{187, 1073741824u, 1072483533u, 1050862006u, 0, JN_TOLERANCE, 0},
+{188, 1077936128u, 1072483533u, 1037636670u, 0, JN_TOLERANCE, 0},
+{189, 1082130432u, 1072483533u, 1020399064u, 0, JN_TOLERANCE, 0},
+{190, 0u, 1072902963u, 1049643654u, 0, JN_TOLERANCE, 0},
+{191, 1065353216u, 1072902963u, 1058326198u, 0, JN_TOLERANCE, 0},
+{192, 1073741824u, 1072902963u, 1051257862u, 0, JN_TOLERANCE, 0},
+{193, 1077936128u, 1072902963u, 1038633608u, 0, JN_TOLERANCE, 0},
+{194, 1082130432u, 1072902963u, 1021801416u, 0, JN_TOLERANCE, 0},
+{195, 0u, 1073322394u, 1048669927u, 0, JN_TOLERANCE, 0},
+{196, 1065353216u, 1073322394u, 1058297495u, 0, JN_TOLERANCE, 0},
+{197, 1073741824u, 1073322394u, 1051646385u, 0, JN_TOLERANCE, 0},
+{198, 1077936128u, 1073322394u, 1039660722u, 0, JN_TOLERANCE, 0},
+{199, 1082130432u, 1073322394u, 1023295797u, 0, JN_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_JN_H multiple inclusion protection
+
+// EOF jnf.h
diff --git a/packages/language/c/libm/current/tests/vectors/ldexpf.c b/packages/language/c/libm/current/tests/vectors/ldexpf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/ldexpf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      ldexpf.c
+//
+//      Test of ldexpf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/ldexpf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(ldexpf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &ldexpf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_INT, CYG_LIBM_TEST_VEC_FLOAT,
+                     &ldexpf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("ldexpf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("ldexpf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library ldexpf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "ldexpf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF ldexpf.c
diff --git a/packages/language/c/libm/current/tests/vectors/ldexpf.h b/packages/language/c/libm/current/tests/vectors/ldexpf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/ldexpf.h
@@ -0,0 +1,887 @@
+#ifndef CYGONCE_LIBM_LDEXPF_H
+#define CYGONCE_LIBM_LDEXPF_H
+//===========================================================================
+//
+//      ldexpf.h
+//
+//      Test vectors for testing of ldexpf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/ldexpf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define LDEXPF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t ldexpf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3196650934u, 0u, 3196650934u, 0, LDEXPF_TOLERANCE, 0},
+{1, 1224242132u, 0u, 1224242132u, 0, LDEXPF_TOLERANCE, 0},
+{2, 1198712763u, 0u, 1198712763u, 0, LDEXPF_TOLERANCE, 0},
+{3, 3159309973u, 0u, 3159309973u, 0, LDEXPF_TOLERANCE, 0},
+{4, 954173073u, 0u, 954173073u, 0, LDEXPF_TOLERANCE, 0},
+{5, 3090780435u, 0u, 3090780435u, 0, LDEXPF_TOLERANCE, 0},
+{6, 966554515u, 4294967290u, 916222867u, 0, LDEXPF_TOLERANCE, 0},
+{7, 1166191415u, 0u, 1166191415u, 0, LDEXPF_TOLERANCE, 0},
+{8, 1234419246u, 0u, 1234419246u, 0, LDEXPF_TOLERANCE, 0},
+{9, 1302107128u, 4294492157u, 0u, 0, LDEXPF_TOLERANCE, 0},
+{10, 1052801068u, 0u, 1052801068u, 0, LDEXPF_TOLERANCE, 0},
+{11, 1060849628u, 0u, 1060849628u, 0, LDEXPF_TOLERANCE, 0},
+{12, 3484320003u, 0u, 3484320003u, 0, LDEXPF_TOLERANCE, 0},
+{13, 1167223673u, 0u, 1167223673u, 0, LDEXPF_TOLERANCE, 0},
+{14, 968192794u, 0u, 968192794u, 0, LDEXPF_TOLERANCE, 0},
+{15, 3122346862u, 48u, 3525000046u, 0, LDEXPF_TOLERANCE, 0},
+{16, 906701409u, 0u, 906701409u, 0, LDEXPF_TOLERANCE, 0},
+{17, 3231467496u, 0u, 3231467496u, 0, LDEXPF_TOLERANCE, 0},
+{18, 1341514497u, 3022046753u, 0u, 0, LDEXPF_TOLERANCE, 0},
+{19, 1272351391u, 4294363968u, 0u, 0, LDEXPF_TOLERANCE, 0},
+{20, 940236348u, 4294965375u, 0u, 0, LDEXPF_TOLERANCE, 0},
+{21, 3251541546u, 0u, 3251541546u, 0, LDEXPF_TOLERANCE, 0},
+{22, 3110358400u, 0u, 3110358400u, 0, LDEXPF_TOLERANCE, 0},
+{23, 3371863479u, 0u, 3371863479u, 0, LDEXPF_TOLERANCE, 0},
+{24, 3204069187u, 0u, 3204069187u, 0, LDEXPF_TOLERANCE, 0},
+{25, 1306460502u, 0u, 1306460502u, 0, LDEXPF_TOLERANCE, 0},
+{26, 1197542187u, 0u, 1197542187u, 0, LDEXPF_TOLERANCE, 0},
+{27, 1184239996u, 4294967294u, 1167462780u, 0, LDEXPF_TOLERANCE, 0},
+{28, 1001673627u, 3340510812u, 0u, 0, LDEXPF_TOLERANCE, 0},
+{29, 941796645u, 0u, 941796645u, 0, LDEXPF_TOLERANCE, 0},
+{30, 3287199470u, 0u, 3287199470u, 0, LDEXPF_TOLERANCE, 0},
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+{734, 1175743586u, 0u, 1175743586u, 0, LDEXPF_TOLERANCE, 0},
+{735, 3260712581u, 0u, 3260712581u, 0, LDEXPF_TOLERANCE, 0},
+{736, 3260874736u, 0u, 3260874736u, 0, LDEXPF_TOLERANCE, 0},
+{737, 1021540545u, 0u, 1021540545u, 0, LDEXPF_TOLERANCE, 0},
+{738, 938613078u, 0u, 938613078u, 0, LDEXPF_TOLERANCE, 0},
+{739, 915371924u, 0u, 915371924u, 0, LDEXPF_TOLERANCE, 0},
+{740, 3370829512u, 0u, 3370829512u, 0, LDEXPF_TOLERANCE, 0},
+{741, 3042270922u, 0u, 3042270922u, 0, LDEXPF_TOLERANCE, 0},
+{742, 935259591u, 0u, 935259591u, 0, LDEXPF_TOLERANCE, 0},
+{743, 3022705759u, 0u, 3022705759u, 0, LDEXPF_TOLERANCE, 0},
+{744, 1077763691u, 0u, 1077763691u, 0, LDEXPF_TOLERANCE, 0},
+{745, 3479409116u, 0u, 3479409116u, 0, LDEXPF_TOLERANCE, 0},
+{746, 3153568584u, 0u, 3153568584u, 0, LDEXPF_TOLERANCE, 0},
+{747, 1023846821u, 0u, 1023846821u, 0, LDEXPF_TOLERANCE, 0},
+{748, 930761742u, 0u, 930761742u, 0, LDEXPF_TOLERANCE, 0},
+{749, 3041242545u, 0u, 3041242545u, 0, LDEXPF_TOLERANCE, 0},
+{750, 1088950833u, 0u, 1088950833u, 0, LDEXPF_TOLERANCE, 0},
+{751, 3404968330u, 0u, 3404968330u, 0, LDEXPF_TOLERANCE, 0},
+{752, 3081647766u, 0u, 3081647766u, 0, LDEXPF_TOLERANCE, 0},
+{753, 1215278023u, 0u, 1215278023u, 0, LDEXPF_TOLERANCE, 0},
+{754, 1094198050u, 0u, 1094198050u, 0, LDEXPF_TOLERANCE, 0},
+{755, 884566767u, 0u, 884566767u, 0, LDEXPF_TOLERANCE, 0},
+{756, 1248601708u, 0u, 1248601708u, 0, LDEXPF_TOLERANCE, 0},
+{757, 3392876913u, 0u, 3392876913u, 0, LDEXPF_TOLERANCE, 0},
+{758, 892549317u, 0u, 892549317u, 0, LDEXPF_TOLERANCE, 0},
+{759, 3093450711u, 0u, 3093450711u, 0, LDEXPF_TOLERANCE, 0},
+{760, 3469899047u, 0u, 3469899047u, 0, LDEXPF_TOLERANCE, 0},
+{761, 996220168u, 0u, 996220168u, 0, LDEXPF_TOLERANCE, 0},
+{762, 3114161777u, 0u, 3114161777u, 0, LDEXPF_TOLERANCE, 0},
+{763, 1253240637u, 0u, 1253240637u, 0, LDEXPF_TOLERANCE, 0},
+{764, 3343677583u, 0u, 3343677583u, 0, LDEXPF_TOLERANCE, 0},
+{765, 3179241204u, 0u, 3179241204u, 0, LDEXPF_TOLERANCE, 0},
+{766, 3155113426u, 0u, 3155113426u, 0, LDEXPF_TOLERANCE, 0},
+{767, 1031613223u, 0u, 1031613223u, 0, LDEXPF_TOLERANCE, 0},
+{768, 1034712760u, 0u, 1034712760u, 0, LDEXPF_TOLERANCE, 0},
+{769, 1066116543u, 0u, 1066116543u, 0, LDEXPF_TOLERANCE, 0},
+{770, 1186234578u, 0u, 1186234578u, 0, LDEXPF_TOLERANCE, 0},
+{771, 1036186976u, 0u, 1036186976u, 0, LDEXPF_TOLERANCE, 0},
+{772, 3097296874u, 0u, 3097296874u, 0, LDEXPF_TOLERANCE, 0},
+{773, 1045232522u, 0u, 1045232522u, 0, LDEXPF_TOLERANCE, 0},
+{774, 1039321021u, 0u, 1039321021u, 0, LDEXPF_TOLERANCE, 0},
+{775, 3173254520u, 0u, 3173254520u, 0, LDEXPF_TOLERANCE, 0},
+{776, 932998692u, 0u, 932998692u, 0, LDEXPF_TOLERANCE, 0},
+{777, 1171238338u, 0u, 1171238338u, 0, LDEXPF_TOLERANCE, 0},
+{778, 1202333162u, 0u, 1202333162u, 0, LDEXPF_TOLERANCE, 0},
+{779, 1280215674u, 0u, 1280215674u, 0, LDEXPF_TOLERANCE, 0},
+{780, 3211934425u, 0u, 3211934425u, 0, LDEXPF_TOLERANCE, 0},
+{781, 3194999530u, 0u, 3194999530u, 0, LDEXPF_TOLERANCE, 0},
+{782, 3299927364u, 0u, 3299927364u, 0, LDEXPF_TOLERANCE, 0},
+{783, 3250437226u, 0u, 3250437226u, 0, LDEXPF_TOLERANCE, 0},
+{784, 3071118853u, 0u, 3071118853u, 0, LDEXPF_TOLERANCE, 0},
+{785, 3267868136u, 0u, 3267868136u, 0, LDEXPF_TOLERANCE, 0},
+{786, 3123250489u, 0u, 3123250489u, 0, LDEXPF_TOLERANCE, 0},
+{787, 3122362353u, 0u, 3122362353u, 0, LDEXPF_TOLERANCE, 0},
+{788, 3327511577u, 0u, 3327511577u, 0, LDEXPF_TOLERANCE, 0},
+{789, 3020140395u, 0u, 3020140395u, 0, LDEXPF_TOLERANCE, 0},
+{790, 1267995571u, 0u, 1267995571u, 0, LDEXPF_TOLERANCE, 0},
+{791, 3446392517u, 0u, 3446392517u, 0, LDEXPF_TOLERANCE, 0},
+{792, 3034243695u, 0u, 3034243695u, 0, LDEXPF_TOLERANCE, 0},
+{793, 3482416423u, 0u, 3482416423u, 0, LDEXPF_TOLERANCE, 0},
+{794, 3310269251u, 0u, 3310269251u, 0, LDEXPF_TOLERANCE, 0},
+{795, 1058296319u, 0u, 1058296319u, 0, LDEXPF_TOLERANCE, 0},
+{796, 3432295752u, 0u, 3432295752u, 0, LDEXPF_TOLERANCE, 0},
+{797, 1087881449u, 0u, 1087881449u, 0, LDEXPF_TOLERANCE, 0},
+{798, 3374929424u, 0u, 3374929424u, 0, LDEXPF_TOLERANCE, 0},
+{799, 1191811948u, 0u, 1191811948u, 0, LDEXPF_TOLERANCE, 0},
+{800, 3268693154u, 0u, 3268693154u, 0, LDEXPF_TOLERANCE, 0},
+{801, 3366511856u, 0u, 3366511856u, 0, LDEXPF_TOLERANCE, 0},
+{802, 3234857152u, 0u, 3234857152u, 0, LDEXPF_TOLERANCE, 0},
+{803, 3394693181u, 0u, 3394693181u, 0, LDEXPF_TOLERANCE, 0},
+{804, 3322380283u, 0u, 3322380283u, 0, LDEXPF_TOLERANCE, 0},
+{805, 3176526828u, 0u, 3176526828u, 0, LDEXPF_TOLERANCE, 0},
+{806, 962436491u, 0u, 962436491u, 0, LDEXPF_TOLERANCE, 0},
+{807, 1016021534u, 0u, 1016021534u, 0, LDEXPF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_LDEXPF_H multiple inclusion protection
+
+// EOF ldexpf.h
diff --git a/packages/language/c/libm/current/tests/vectors/log10f.c b/packages/language/c/libm/current/tests/vectors/log10f.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/log10f.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      log10.c
+//
+//      Test of log10() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_double_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/log10f.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(log10f_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &log10f, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &log10f_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("log10f() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("log10f() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library log10f() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "log10() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF log10.c
diff --git a/packages/language/c/libm/current/tests/vectors/log10f.h b/packages/language/c/libm/current/tests/vectors/log10f.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/log10f.h
@@ -0,0 +1,875 @@
+#ifndef CYGONCE_LIBM_LOG10_H
+#define CYGONCE_LIBM_LOG10_H
+//===========================================================================
+//
+//      log10.h
+//
+//      Test vectors for testing of log10() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/log10.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define LOG10_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t log10f_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{1, 3214430700u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{2, 3214346813u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{3, 3214262927u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{4, 3214179041u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{5, 3214095155u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{6, 3214011269u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{7, 3213927383u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{8, 3213843497u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{9, 3213759611u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{10, 3213675725u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{11, 3213591839u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{12, 3213507953u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{13, 3213424067u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{14, 3213340180u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{15, 3213256294u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{16, 3213172408u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{17, 3213088522u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{18, 3213004636u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{19, 3212920750u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{20, 3212836864u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{21, 3212669092u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{22, 3212501320u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{23, 3212333548u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{24, 3212165775u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{25, 3211998003u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{26, 3211830231u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{27, 3211662459u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{28, 3211494687u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{29, 3211326915u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{30, 3211159142u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{31, 3210991370u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{32, 3210823598u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{33, 3210655826u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{34, 3210488054u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{35, 3210320282u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{36, 3210152509u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{37, 3209984737u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{38, 3209816965u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{39, 3209649193u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{40, 3209481421u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{41, 3209313649u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{42, 3209145876u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{43, 3208978104u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{44, 3208810332u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{45, 3208642560u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{46, 3208474788u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{47, 3208307016u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{48, 3208139244u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{49, 3207971471u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{50, 3207803699u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{51, 3207635927u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{52, 3207468155u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{53, 3207300383u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{54, 3207132611u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{55, 3206964838u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{56, 3206797066u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{57, 3206629294u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{58, 3206461522u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{59, 3206293750u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{60, 3206125978u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{61, 3205958205u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{62, 3205790433u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{63, 3205622661u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{64, 3205454889u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{65, 3205287117u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{66, 3205119345u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{67, 3204951572u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{68, 3204783800u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{69, 3204616028u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{70, 3204448256u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{71, 3204112712u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{72, 3203777167u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{73, 3203441623u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{74, 3203106079u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{75, 3202770534u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{76, 3202434990u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{77, 3202099446u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{78, 3201763901u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{79, 3201428357u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{80, 3201092813u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{81, 3200757268u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{82, 3200421724u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{83, 3200086180u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{84, 3199750636u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
+{85, 3199415091u, 1115684864u, 2143289344u, EDOM, LOG10_TOLERANCE, 0},
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+{749, 1124721745u, 1074327092u, 1074327092u, 0, LOG10_TOLERANCE, 0},
+{750, 1114260656u, 1071792761u, 1071792761u, 0, LOG10_TOLERANCE, 0},
+{751, 1155676504u, 1079016701u, 1079016701u, 0, LOG10_TOLERANCE, 0},
+{752, 1315090496u, 1091544641u, 1091544641u, 0, LOG10_TOLERANCE, 0},
+{753, 1082919539u, 1059331952u, 1059331952u, 0, LOG10_TOLERANCE, 0},
+{754, 1335399673u, 1092311322u, 1092311322u, 0, LOG10_TOLERANCE, 0},
+{755, 1072458508u, 1049128670u, 1049128670u, 0, LOG10_TOLERANCE, 0},
+{756, 1155531601u, 1078998810u, 1078998810u, 0, LOG10_TOLERANCE, 0},
+{757, 1104656093u, 1068966936u, 1068966936u, 0, LOG10_TOLERANCE, 0},
+{758, 1321036318u, 1091778488u, 1091778488u, 0, LOG10_TOLERANCE, 0},
+{759, 1172239631u, 1081515428u, 1081515428u, 0, LOG10_TOLERANCE, 0},
+{760, 1107620519u, 1069728893u, 1069728893u, 0, LOG10_TOLERANCE, 0},
+{761, 1155477903u, 1078992135u, 1078992135u, 0, LOG10_TOLERANCE, 0},
+{762, 1126405528u, 1074638322u, 1074638322u, 0, LOG10_TOLERANCE, 0},
+{763, 1090330020u, 1063644779u, 1063644779u, 0, LOG10_TOLERANCE, 0},
+{764, 1228207362u, 1086051971u, 1086051971u, 0, LOG10_TOLERANCE, 0},
+{765, 1290175785u, 1090605316u, 1090605316u, 0, LOG10_TOLERANCE, 0},
+{766, 1214223128u, 1084981977u, 1084981977u, 0, LOG10_TOLERANCE, 0},
+{767, 1275438936u, 1089563831u, 1089563831u, 0, LOG10_TOLERANCE, 0},
+{768, 1315857601u, 1091567568u, 1091567568u, 0, LOG10_TOLERANCE, 0},
+{769, 1305742382u, 1091198584u, 1091198584u, 0, LOG10_TOLERANCE, 0},
+{770, 1078359574u, 1056679255u, 1056679255u, 0, LOG10_TOLERANCE, 0},
+{771, 1207675424u, 1084458464u, 1084458464u, 0, LOG10_TOLERANCE, 0},
+{772, 1248421894u, 1087546395u, 1087546395u, 0, LOG10_TOLERANCE, 0},
+{773, 1205768346u, 1084346548u, 1084346548u, 0, LOG10_TOLERANCE, 0},
+{774, 1076752219u, 1054756961u, 1054756961u, 0, LOG10_TOLERANCE, 0},
+{775, 1241048294u, 1086973604u, 1086973604u, 0, LOG10_TOLERANCE, 0},
+{776, 1273395082u, 1089428770u, 1089428770u, 0, LOG10_TOLERANCE, 0},
+{777, 1238104535u, 1086792336u, 1086792336u, 0, LOG10_TOLERANCE, 0},
+{778, 1294321000u, 1090770812u, 1090770812u, 0, LOG10_TOLERANCE, 0},
+{779, 1245343769u, 1087341758u, 1087341758u, 0, LOG10_TOLERANCE, 0},
+{780, 1161241793u, 1079894497u, 1079894497u, 0, LOG10_TOLERANCE, 0},
+{781, 1171318485u, 1081396814u, 1081396814u, 0, LOG10_TOLERANCE, 0},
+{782, 1243968857u, 1087233031u, 1087233031u, 0, LOG10_TOLERANCE, 0},
+{783, 1102119721u, 1068246561u, 1068246561u, 0, LOG10_TOLERANCE, 0},
+{784, 1220264047u, 1085454237u, 1085454237u, 0, LOG10_TOLERANCE, 0},
+{785, 1134728775u, 1075889794u, 1075889794u, 0, LOG10_TOLERANCE, 0},
+{786, 1204809672u, 1084284629u, 1084284629u, 0, LOG10_TOLERANCE, 0},
+{787, 1148874793u, 1077939317u, 1077939317u, 0, LOG10_TOLERANCE, 0},
+{788, 1197828352u, 1083742833u, 1083742833u, 0, LOG10_TOLERANCE, 0},
+{789, 1193026723u, 1083392420u, 1083392420u, 0, LOG10_TOLERANCE, 0},
+{790, 1127109339u, 1074754146u, 1074754146u, 0, LOG10_TOLERANCE, 0},
+{791, 1200599955u, 1083948099u, 1083948099u, 0, LOG10_TOLERANCE, 0},
+{792, 1089700228u, 1063362759u, 1063362759u, 0, LOG10_TOLERANCE, 0},
+{793, 1333109014u, 1092212490u, 1092212490u, 0, LOG10_TOLERANCE, 0},
+{794, 1155775526u, 1079028827u, 1079028827u, 0, LOG10_TOLERANCE, 0},
+{795, 1234491880u, 1086505389u, 1086505389u, 0, LOG10_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_LOG10_H multiple inclusion protection
+
+// EOF log10.h
diff --git a/packages/language/c/libm/current/tests/vectors/log1pf.c b/packages/language/c/libm/current/tests/vectors/log1pf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/log1pf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      log1pf.c
+//
+//      Test of log1pf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/log1pf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(log1pf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &log1pf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &log1pf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("log1pf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("log1pf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library log1pf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "log1pf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF log1pf.c
diff --git a/packages/language/c/libm/current/tests/vectors/log1pf.h b/packages/language/c/libm/current/tests/vectors/log1pf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/log1pf.h
@@ -0,0 +1,1360 @@
+#ifndef CYGONCE_LIBM_LOG1PFF_H
+#define CYGONCE_LIBM_LOG1PFF_H
+//===========================================================================
+//
+//      log1pf.h
+//
+//      Test vectors for testing of log1pf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/log1pf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define LOG1PF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t log1pf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1, 3214430700u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{2, 3214346813u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{3, 3214262927u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{4, 3214179041u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{5, 3214095155u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{6, 3214011269u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{7, 3213927383u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{8, 3213843497u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{9, 3213759611u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{10, 3213675725u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{11, 3213591839u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{12, 3213507953u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{13, 3213424067u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{14, 3213340180u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{15, 3213256294u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{16, 3213172408u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{17, 3213088522u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{18, 3213004636u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{19, 3212920750u, 0u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{20, 3212669092u, 0u, 3230883216u, 0, LOG1PF_TOLERANCE, 0},
+{21, 3212501320u, 0u, 3229245082u, 0, LOG1PF_TOLERANCE, 0},
+{22, 3212333548u, 0u, 3227544438u, 0, LOG1PF_TOLERANCE, 0},
+{23, 3212165775u, 0u, 3226337805u, 0, LOG1PF_TOLERANCE, 0},
+{24, 3211998003u, 0u, 3225401875u, 0, LOG1PF_TOLERANCE, 0},
+{25, 3211830231u, 0u, 3224637164u, 0, LOG1PF_TOLERANCE, 0},
+{26, 3211662459u, 0u, 3223990609u, 0, LOG1PF_TOLERANCE, 0},
+{27, 3211494687u, 0u, 3223430539u, 0, LOG1PF_TOLERANCE, 0},
+{28, 3211326915u, 0u, 3222936521u, 0, LOG1PF_TOLERANCE, 0},
+{29, 3211159142u, 0u, 3222494605u, 0, LOG1PF_TOLERANCE, 0},
+{30, 3210991370u, 0u, 3222094845u, 0, LOG1PF_TOLERANCE, 0},
+{31, 3210823598u, 0u, 3221729894u, 0, LOG1PF_TOLERANCE, 0},
+{32, 3210655826u, 0u, 3221394171u, 0, LOG1PF_TOLERANCE, 0},
+{33, 3210488054u, 0u, 3220941207u, 0, LOG1PF_TOLERANCE, 0},
+{34, 3210320282u, 0u, 3220362453u, 0, LOG1PF_TOLERANCE, 0},
+{35, 3210152509u, 0u, 3219821062u, 0, LOG1PF_TOLERANCE, 0},
+{36, 3209984737u, 0u, 3219312507u, 0, LOG1PF_TOLERANCE, 0},
+{37, 3209816965u, 0u, 3218833027u, 0, LOG1PF_TOLERANCE, 0},
+{38, 3209649193u, 0u, 3218379479u, 0, LOG1PF_TOLERANCE, 0},
+{39, 3209481421u, 0u, 3217949200u, 0, LOG1PF_TOLERANCE, 0},
+{40, 3209313649u, 0u, 3217539919u, 0, LOG1PF_TOLERANCE, 0},
+{41, 3209145876u, 0u, 3217149679u, 0, LOG1PF_TOLERANCE, 0},
+{42, 3208978104u, 0u, 3216776791u, 0, LOG1PF_TOLERANCE, 0},
+{43, 3208810332u, 0u, 3216419775u, 0, LOG1PF_TOLERANCE, 0},
+{44, 3208642560u, 0u, 3216077336u, 0, LOG1PF_TOLERANCE, 0},
+{45, 3208474788u, 0u, 3215748329u, 0, LOG1PF_TOLERANCE, 0},
+{46, 3208307016u, 0u, 3215431741u, 0, LOG1PF_TOLERANCE, 0},
+{47, 3208139244u, 0u, 3215126667u, 0, LOG1PF_TOLERANCE, 0},
+{48, 3207971471u, 0u, 3214832298u, 0, LOG1PF_TOLERANCE, 0},
+{49, 3207803699u, 0u, 3214547912u, 0, LOG1PF_TOLERANCE, 0},
+{50, 3207635927u, 0u, 3214272851u, 0, LOG1PF_TOLERANCE, 0},
+{51, 3207468155u, 0u, 3214006524u, 0, LOG1PF_TOLERANCE, 0},
+{52, 3207300383u, 0u, 3213748393u, 0, LOG1PF_TOLERANCE, 0},
+{53, 3207132611u, 0u, 3213497968u, 0, LOG1PF_TOLERANCE, 0},
+{54, 3206964838u, 0u, 3213254802u, 0, LOG1PF_TOLERANCE, 0},
+{55, 3206797066u, 0u, 3213018487u, 0, LOG1PF_TOLERANCE, 0},
+{56, 3206629294u, 0u, 3212740433u, 0, LOG1PF_TOLERANCE, 0},
+{57, 3206461522u, 0u, 3212293014u, 0, LOG1PF_TOLERANCE, 0},
+{58, 3206293750u, 0u, 3211857218u, 0, LOG1PF_TOLERANCE, 0},
+{59, 3206125978u, 0u, 3211432457u, 0, LOG1PF_TOLERANCE, 0},
+{60, 3205958205u, 0u, 3211018181u, 0, LOG1PF_TOLERANCE, 0},
+{61, 3205790433u, 0u, 3210613892u, 0, LOG1PF_TOLERANCE, 0},
+{62, 3205622661u, 0u, 3210219116u, 0, LOG1PF_TOLERANCE, 0},
+{63, 3205454889u, 0u, 3209833416u, 0, LOG1PF_TOLERANCE, 0},
+{64, 3205287117u, 0u, 3209456385u, 0, LOG1PF_TOLERANCE, 0},
+{65, 3205119345u, 0u, 3209087640u, 0, LOG1PF_TOLERANCE, 0},
+{66, 3204951572u, 0u, 3208726824u, 0, LOG1PF_TOLERANCE, 0},
+{67, 3204783800u, 0u, 3208373607u, 0, LOG1PF_TOLERANCE, 0},
+{68, 3204616028u, 0u, 3208027673u, 0, LOG1PF_TOLERANCE, 0},
+{69, 3204448256u, 0u, 3207688728u, 0, LOG1PF_TOLERANCE, 0},
+{70, 3204112712u, 0u, 3207356495u, 0, LOG1PF_TOLERANCE, 0},
+{71, 3203777167u, 0u, 3207030713u, 0, LOG1PF_TOLERANCE, 0},
+{72, 3203441623u, 0u, 3206711138u, 0, LOG1PF_TOLERANCE, 0},
+{73, 3203106079u, 0u, 3206397536u, 0, LOG1PF_TOLERANCE, 0},
+{74, 3202770534u, 0u, 3206089688u, 0, LOG1PF_TOLERANCE, 0},
+{75, 3202434990u, 0u, 3205787388u, 0, LOG1PF_TOLERANCE, 0},
+{76, 3202099446u, 0u, 3205490439u, 0, LOG1PF_TOLERANCE, 0},
+{77, 3201763901u, 0u, 3205198653u, 0, LOG1PF_TOLERANCE, 0},
+{78, 3201428357u, 0u, 3204911856u, 0, LOG1PF_TOLERANCE, 0},
+{79, 3201092813u, 0u, 3204629880u, 0, LOG1PF_TOLERANCE, 0},
+{80, 3200757268u, 0u, 3204256872u, 0, LOG1PF_TOLERANCE, 0},
+{81, 3200421724u, 0u, 3203711260u, 0, LOG1PF_TOLERANCE, 0},
+{82, 3200086180u, 0u, 3203174378u, 0, LOG1PF_TOLERANCE, 0},
+{83, 3199750636u, 0u, 3202645951u, 0, LOG1PF_TOLERANCE, 0},
+{84, 3199415091u, 0u, 3202125716u, 0, LOG1PF_TOLERANCE, 0},
+{85, 3199079547u, 0u, 3201613425u, 0, LOG1PF_TOLERANCE, 0},
+{86, 3198744003u, 0u, 3201108838u, 0, LOG1PF_TOLERANCE, 0},
+{87, 3198408458u, 0u, 3200611725u, 0, LOG1PF_TOLERANCE, 0},
+{88, 3198072914u, 0u, 3200121871u, 0, LOG1PF_TOLERANCE, 0},
+{89, 3197737370u, 0u, 3199639066u, 0, LOG1PF_TOLERANCE, 0},
+{90, 3197401825u, 0u, 3199163107u, 0, LOG1PF_TOLERANCE, 0},
+{91, 3197066281u, 0u, 3198693807u, 0, LOG1PF_TOLERANCE, 0},
+{92, 3196730737u, 0u, 3198230981u, 0, LOG1PF_TOLERANCE, 0},
+{93, 3196395192u, 0u, 3197774450u, 0, LOG1PF_TOLERANCE, 0},
+{94, 3196059648u, 0u, 3197324049u, 0, LOG1PF_TOLERANCE, 0},
+{95, 3195388559u, 0u, 3196879612u, 0, LOG1PF_TOLERANCE, 0},
+{96, 3194717471u, 0u, 3196440986u, 0, LOG1PF_TOLERANCE, 0},
+{97, 3194046382u, 0u, 3195956391u, 0, LOG1PF_TOLERANCE, 0},
+{98, 3193375293u, 0u, 3195101489u, 0, LOG1PF_TOLERANCE, 0},
+{99, 3192704205u, 0u, 3194257342u, 0, LOG1PF_TOLERANCE, 0},
+{100, 3192033116u, 0u, 3193423681u, 0, LOG1PF_TOLERANCE, 0},
+{101, 3191362028u, 0u, 3192600250u, 0, LOG1PF_TOLERANCE, 0},
+{102, 3190690939u, 0u, 3191786798u, 0, LOG1PF_TOLERANCE, 0},
+{103, 3190019850u, 0u, 3190983089u, 0, LOG1PF_TOLERANCE, 0},
+{104, 3189348762u, 0u, 3190188893u, 0, LOG1PF_TOLERANCE, 0},
+{105, 3188677673u, 0u, 3189403985u, 0, LOG1PF_TOLERANCE, 0},
+{106, 3188006584u, 0u, 3188628151u, 0, LOG1PF_TOLERANCE, 0},
+{107, 3186999951u, 0u, 3187861184u, 0, LOG1PF_TOLERANCE, 0},
+{108, 3185657774u, 0u, 3186534728u, 0, LOG1PF_TOLERANCE, 0},
+{109, 3184315597u, 0u, 3185035073u, 0, LOG1PF_TOLERANCE, 0},
+{110, 3182973420u, 0u, 3183551990u, 0, LOG1PF_TOLERANCE, 0},
+{111, 3181631242u, 0u, 3182085114u, 0, LOG1PF_TOLERANCE, 0},
+{112, 3180289065u, 0u, 3180634098u, 0, LOG1PF_TOLERANCE, 0},
+{113, 3178611343u, 0u, 3179114768u, 0, LOG1PF_TOLERANCE, 0},
+{114, 3175926989u, 0u, 3176274155u, 0, LOG1PF_TOLERANCE, 0},
+{115, 3173242634u, 0u, 3173463286u, 0, LOG1PF_TOLERANCE, 0},
+{116, 3170222735u, 0u, 3170469270u, 0, LOG1PF_TOLERANCE, 0},
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+{1200, 1064922416u, 1320485628u, 1059988285u, 0, LOG1PF_TOLERANCE, 0},
+{1201, 868114980u, 3213276361u, 868114979u, 0, LOG1PF_TOLERANCE, 0},
+{1202, 3303160152u, 3075455322u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1203, 1315090496u, 3269683237u, 1101357549u, 0, LOG1PF_TOLERANCE, 0},
+{1204, 850876090u, 3365795667u, 850876090u, 0, LOG1PF_TOLERANCE, 0},
+{1205, 3230403187u, 1322841992u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1206, 1335399673u, 974138676u, 1102240222u, 0, LOG1PF_TOLERANCE, 0},
+{1207, 1072458508u, 3372833993u, 1065741371u, 0, LOG1PF_TOLERANCE, 0},
+{1208, 3303015249u, 3015039539u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1209, 3252139741u, 1059615003u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1210, 3468519966u, 3113982619u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1211, 1006231203u, 897530770u, 1006169084u, 0, LOG1PF_TOLERANCE, 0},
+{1212, 951554138u, 1001144381u, 951553612u, 0, LOG1PF_TOLERANCE, 0},
+{1213, 942046828u, 986341002u, 942046611u, 0, LOG1PF_TOLERANCE, 0},
+{1214, 2968517146u, 951832467u, 2968517146u, 0, LOG1PF_TOLERANCE, 0},
+{1215, 3319723279u, 3414482416u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1216, 3255104167u, 928827688u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1217, 1155477903u, 3104812800u, 1089445384u, 0, LOG1PF_TOLERANCE, 0},
+{1218, 3273889176u, 980486479u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1219, 3237813668u, 3441016803u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1220, 1228207362u, 2985476579u, 1096303014u, 0, LOG1PF_TOLERANCE, 0},
+{1221, 975349337u, 1311932596u, 975346031u, 0, LOG1PF_TOLERANCE, 0},
+{1222, 2982583196u, 3132904446u, 2982583196u, 0, LOG1PF_TOLERANCE, 0},
+{1223, 1290175785u, 3008182462u, 1100276110u, 0, LOG1PF_TOLERANCE, 0},
+{1224, 981908840u, 3314038398u, 981904304u, 0, LOG1PF_TOLERANCE, 0},
+{1225, 941187647u, 1107765599u, 941187463u, 0, LOG1PF_TOLERANCE, 0},
+{1226, 1214223128u, 3225536822u, 1095071140u, 0, LOG1PF_TOLERANCE, 0},
+{1227, 3422922584u, 1086391131u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1228, 1315857601u, 3487600045u, 1101383945u, 0, LOG1PF_TOLERANCE, 0},
+{1229, 3453226030u, 3233768835u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1230, 1078359574u, 3199175230u, 1068802783u, 0, LOG1PF_TOLERANCE, 0},
+{1231, 1029557624u, 3302959071u, 1029177708u, 0, LOG1PF_TOLERANCE, 0},
+{1232, 1207675424u, 3042692550u, 1094468428u, 0, LOG1PF_TOLERANCE, 0},
+{1233, 1028355074u, 3442294040u, 1028034501u, 0, LOG1PF_TOLERANCE, 0},
+{1234, 3119299090u, 1187096397u, 3119302594u, 0, LOG1PF_TOLERANCE, 0},
+{1235, 1248421894u, 3367769132u, 1098023532u, 0, LOG1PF_TOLERANCE, 0},
+{1236, 3353251994u, 1095517730u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1237, 876926659u, 3288089977u, 876926658u, 0, LOG1PF_TOLERANCE, 0},
+{1238, 1076752219u, 876236939u, 1067979810u, 0, LOG1PF_TOLERANCE, 0},
+{1239, 3388531942u, 2988520062u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1240, 1273395082u, 3031189261u, 1099549172u, 0, LOG1PF_TOLERANCE, 0},
+{1241, 3385588183u, 3258252464u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1242, 862047095u, 829323655u, 862047095u, 0, LOG1PF_TOLERANCE, 0},
+{1243, 3192315328u, 3289489214u, 3193772998u, 0, LOG1PF_TOLERANCE, 0},
+{1244, 3441804648u, 3274638356u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1245, 837368567u, 3228474927u, 837368567u, 0, LOG1PF_TOLERANCE, 0},
+{1246, 3392827417u, 1277961150u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1247, 1161241793u, 1328003707u, 1090483808u, 0, LOG1PF_TOLERANCE, 0},
+{1248, 856495732u, 3123041418u, 856495732u, 0, LOG1PF_TOLERANCE, 0},
+{1249, 3034494183u, 3041579130u, 3034494186u, 0, LOG1PF_TOLERANCE, 0},
+{1250, 1171318485u, 3374409104u, 1091366026u, 0, LOG1PF_TOLERANCE, 0},
+{1251, 3047748143u, 831102792u, 3047748150u, 0, LOG1PF_TOLERANCE, 0},
+{1252, 1001216371u, 3052357038u, 1001186427u, 0, LOG1PF_TOLERANCE, 0},
+{1253, 2999541351u, 3085461799u, 2999541351u, 0, LOG1PF_TOLERANCE, 0},
+{1254, 912515889u, 1074635609u, 912515864u, 0, LOG1PF_TOLERANCE, 0},
+{1255, 3391452505u, 897989232u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1256, 3249603369u, 3147662248u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1257, 1220264047u, 2960450369u, 1095614849u, 0, LOG1PF_TOLERANCE, 0},
+{1258, 3169816394u, 988430929u, 3170050525u, 0, LOG1PF_TOLERANCE, 0},
+{1259, 3098997418u, 3002162688u, 3098997941u, 0, LOG1PF_TOLERANCE, 0},
+{1260, 3282212423u, 3174079140u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1261, 3352293320u, 3247843425u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1262, 3296358441u, 875645354u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1263, 1197828352u, 3245614728u, 1093644537u, 0, LOG1PF_TOLERANCE, 0},
+{1264, 3340510371u, 914930263u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1265, 1127109339u, 3368125489u, 1084577040u, 0, LOG1PF_TOLERANCE, 0},
+{1266, 816173492u, 1083268662u, 816173492u, 0, LOG1PF_TOLERANCE, 0},
+{1267, 909467381u, 1232375752u, 909467365u, 0, LOG1PF_TOLERANCE, 0},
+{1268, 1200599955u, 2981200675u, 1093880855u, 0, LOG1PF_TOLERANCE, 0},
+{1269, 962230977u, 2988248037u, 962229486u, 0, LOG1PF_TOLERANCE, 0},
+{1270, 2996667337u, 1068572835u, 2996667337u, 0, LOG1PF_TOLERANCE, 0},
+{1271, 3192887808u, 3191848339u, 3194487240u, 0, LOG1PF_TOLERANCE, 0},
+{1272, 3237183876u, 3179379969u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1273, 939285924u, 3056079386u, 939285675u, 0, LOG1PF_TOLERANCE, 0},
+{1274, 944050180u, 3452557879u, 944049877u, 0, LOG1PF_TOLERANCE, 0},
+{1275, 3058135703u, 3090284601u, 3058135722u, 0, LOG1PF_TOLERANCE, 0},
+{1276, 3480592662u, 3261728191u, 2143289344u, 0, LOG1PF_TOLERANCE, 0},
+{1277, 3061939312u, 3274418540u, 3061939328u, 0, LOG1PF_TOLERANCE, 0},
+{1278, 1003299981u, 853295521u, 1003258072u, 0, LOG1PF_TOLERANCE, 0},
+{1279, 1155775526u, 1255814444u, 1089487603u, 0, LOG1PF_TOLERANCE, 0},
+{1280, 1234491880u, 3408568717u, 1096825031u, 0, LOG1PF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_LOG1PFF_H multiple inclusion protection
+
+// EOF log1pf.h
diff --git a/packages/language/c/libm/current/tests/vectors/logbf.c b/packages/language/c/libm/current/tests/vectors/logbf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/logbf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      logbf.c
+//
+//      Test of logbf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/logbf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(logbf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &logbf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &logbf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("logbf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("logbf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library logbf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "logbf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF logbf.c
diff --git a/packages/language/c/libm/current/tests/vectors/logbf.h b/packages/language/c/libm/current/tests/vectors/logbf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/logbf.h
@@ -0,0 +1,1360 @@
+#ifndef CYGONCE_LIBM_LOGBF_H
+#define CYGONCE_LIBM_LOGBF_H
+//===========================================================================
+//
+//      logbf.h
+//
+//      Test vectors for testing of logbf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/logbf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define LOGBF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t logbf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{1, 3214430700u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{2, 3214346813u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{3, 3214262927u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{4, 3214179041u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{5, 3214095155u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{6, 3214011269u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{7, 3213927383u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{8, 3213843497u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{9, 3213759611u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{10, 3213675725u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{11, 3213591839u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{12, 3213507953u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{13, 3213424067u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{14, 3213340180u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{15, 3213256294u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{16, 3213172408u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{17, 3213088522u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{18, 3213004636u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{19, 3212920750u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{20, 3212836864u, 0u, 0u, 0, LOGBF_TOLERANCE, 0},
+{21, 3212669092u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{22, 3212501320u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{23, 3212333548u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{24, 3212165775u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{25, 3211998003u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{26, 3211830231u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{27, 3211662459u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{28, 3211494687u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{29, 3211326915u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{30, 3211159142u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{31, 3210991370u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{32, 3210823598u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{33, 3210655826u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{34, 3210488054u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{35, 3210320282u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{36, 3210152509u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{37, 3209984737u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{38, 3209816965u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{39, 3209649193u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{40, 3209481421u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{41, 3209313649u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{42, 3209145876u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{43, 3208978104u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{44, 3208810332u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{45, 3208642560u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{46, 3208474788u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{47, 3208307016u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{48, 3208139244u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{49, 3207971471u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{50, 3207803699u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{51, 3207635927u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{52, 3207468155u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{53, 3207300383u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{54, 3207132611u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{55, 3206964838u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{56, 3206797066u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{57, 3206629294u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{58, 3206461522u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{59, 3206293750u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{60, 3206125978u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{61, 3205958205u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{62, 3205790433u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{63, 3205622661u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{64, 3205454889u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{65, 3205287117u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{66, 3205119345u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{67, 3204951572u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{68, 3204783800u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{69, 3204616028u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{70, 3204448256u, 0u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{71, 3204112712u, 0u, 3221225472u, 0, LOGBF_TOLERANCE, 0},
+{72, 3203777167u, 0u, 3221225472u, 0, LOGBF_TOLERANCE, 0},
+{73, 3203441623u, 0u, 3221225472u, 0, LOGBF_TOLERANCE, 0},
+{74, 3203106079u, 0u, 3221225472u, 0, LOGBF_TOLERANCE, 0},
+{75, 3202770534u, 0u, 3221225472u, 0, LOGBF_TOLERANCE, 0},
+{76, 3202434990u, 0u, 3221225472u, 0, LOGBF_TOLERANCE, 0},
+{77, 3202099446u, 0u, 3221225472u, 0, LOGBF_TOLERANCE, 0},
+{78, 3201763901u, 0u, 3221225472u, 0, LOGBF_TOLERANCE, 0},
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+{1171, 870472127u, 3332532333u, 3250585600u, 0, LOGBF_TOLERANCE, 0},
+{1172, 3403009513u, 3381966453u, 1102053376u, 0, LOGBF_TOLERANCE, 0},
+{1173, 816825508u, 3032174124u, 3253731328u, 0, LOGBF_TOLERANCE, 0},
+{1174, 952348506u, 3377573987u, 3244294144u, 0, LOGBF_TOLERANCE, 0},
+{1175, 839544701u, 3419900937u, 3252158464u, 0, LOGBF_TOLERANCE, 0},
+{1176, 2967454456u, 3313359047u, 3253731328u, 0, LOGBF_TOLERANCE, 0},
+{1177, 1222777442u, 1125769920u, 1099956224u, 0, LOGBF_TOLERANCE, 0},
+{1178, 1325324763u, 978336043u, 1106247680u, 0, LOGBF_TOLERANCE, 0},
+{1179, 3363524213u, 3202991311u, 1099431936u, 0, LOGBF_TOLERANCE, 0},
+{1180, 1158950321u, 1073578913u, 1093664768u, 0, LOGBF_TOLERANCE, 0},
+{1181, 903129873u, 3416864271u, 3248488448u, 0, LOGBF_TOLERANCE, 0},
+{1182, 2997685349u, 1123653663u, 3251634176u, 0, LOGBF_TOLERANCE, 0},
+{1183, 3078339944u, 988173985u, 3246915584u, 0, LOGBF_TOLERANCE, 0},
+{1184, 1208345407u, 1254181270u, 1099431936u, 0, LOGBF_TOLERANCE, 0},
+{1185, 3003262042u, 1327277116u, 3251109888u, 0, LOGBF_TOLERANCE, 0},
+{1186, 1258634105u, 1247426200u, 1102577664u, 0, LOGBF_TOLERANCE, 0},
+{1187, 1248478509u, 1287895126u, 1101529088u, 0, LOGBF_TOLERANCE, 0},
+{1188, 1153863988u, 3430539165u, 1092616192u, 0, LOGBF_TOLERANCE, 0},
+{1189, 1235620969u, 866627358u, 1101004800u, 0, LOGBF_TOLERANCE, 0},
+{1190, 1097120930u, 3221726305u, 1077936128u, 0, LOGBF_TOLERANCE, 0},
+{1191, 3469778622u, 1200179013u, 1106247680u, 0, LOGBF_TOLERANCE, 0},
+{1192, 1147712200u, 931865525u, 1091567616u, 0, LOGBF_TOLERANCE, 0},
+{1193, 812694172u, 1136276190u, 3254255616u, 0, LOGBF_TOLERANCE, 0},
+{1194, 862266739u, 3139447362u, 3251109888u, 0, LOGBF_TOLERANCE, 0},
+{1195, 1124721745u, 3058969650u, 1088421888u, 0, LOGBF_TOLERANCE, 0},
+{1196, 3261744304u, 1043806501u, 1084227584u, 0, LOGBF_TOLERANCE, 0},
+{1197, 832324055u, 2954061156u, 3252682752u, 0, LOGBF_TOLERANCE, 0},
+{1198, 805759679u, 903848557u, 3254255616u, 0, LOGBF_TOLERANCE, 0},
+{1199, 2983396015u, 872299138u, 3252682752u, 0, LOGBF_TOLERANCE, 0},
+{1200, 1064922416u, 1320485628u, 3212836864u, 0, LOGBF_TOLERANCE, 0},
+{1201, 868114980u, 3213276361u, 3250585600u, 0, LOGBF_TOLERANCE, 0},
+{1202, 3303160152u, 3075455322u, 1092616192u, 0, LOGBF_TOLERANCE, 0},
+{1203, 1315090496u, 3269683237u, 1105723392u, 0, LOGBF_TOLERANCE, 0},
+{1204, 850876090u, 3365795667u, 3251634176u, 0, LOGBF_TOLERANCE, 0},
+{1205, 3230403187u, 1322841992u, 1073741824u, 0, LOGBF_TOLERANCE, 0},
+{1206, 1335399673u, 974138676u, 1107296256u, 0, LOGBF_TOLERANCE, 0},
+{1207, 1072458508u, 3372833993u, 0u, 0, LOGBF_TOLERANCE, 0},
+{1208, 3303015249u, 3015039539u, 1092616192u, 0, LOGBF_TOLERANCE, 0},
+{1209, 3252139741u, 1059615003u, 1082130432u, 0, LOGBF_TOLERANCE, 0},
+{1210, 3468519966u, 3113982619u, 1106247680u, 0, LOGBF_TOLERANCE, 0},
+{1211, 1006231203u, 897530770u, 3238002688u, 0, LOGBF_TOLERANCE, 0},
+{1212, 951554138u, 1001144381u, 3244294144u, 0, LOGBF_TOLERANCE, 0},
+{1213, 942046828u, 986341002u, 3245342720u, 0, LOGBF_TOLERANCE, 0},
+{1214, 2968517146u, 951832467u, 3253731328u, 0, LOGBF_TOLERANCE, 0},
+{1215, 3319723279u, 3414482416u, 1094713344u, 0, LOGBF_TOLERANCE, 0},
+{1216, 3255104167u, 928827688u, 1084227584u, 0, LOGBF_TOLERANCE, 0},
+{1217, 1155477903u, 3104812800u, 1092616192u, 0, LOGBF_TOLERANCE, 0},
+{1218, 3273889176u, 980486479u, 1088421888u, 0, LOGBF_TOLERANCE, 0},
+{1219, 3237813668u, 3441016803u, 1073741824u, 0, LOGBF_TOLERANCE, 0},
+{1220, 1228207362u, 2985476579u, 1100480512u, 0, LOGBF_TOLERANCE, 0},
+{1221, 975349337u, 1311932596u, 3241148416u, 0, LOGBF_TOLERANCE, 0},
+{1222, 2982583196u, 3132904446u, 3252682752u, 0, LOGBF_TOLERANCE, 0},
+{1223, 1290175785u, 3008182462u, 1104150528u, 0, LOGBF_TOLERANCE, 0},
+{1224, 981908840u, 3314038398u, 3240099840u, 0, LOGBF_TOLERANCE, 0},
+{1225, 941187647u, 1107765599u, 3245342720u, 0, LOGBF_TOLERANCE, 0},
+{1226, 1214223128u, 3225536822u, 1099431936u, 0, LOGBF_TOLERANCE, 0},
+{1227, 3422922584u, 1086391131u, 1103626240u, 0, LOGBF_TOLERANCE, 0},
+{1228, 1315857601u, 3487600045u, 1105723392u, 0, LOGBF_TOLERANCE, 0},
+{1229, 3453226030u, 3233768835u, 1105199104u, 0, LOGBF_TOLERANCE, 0},
+{1230, 1078359574u, 3199175230u, 1065353216u, 0, LOGBF_TOLERANCE, 0},
+{1231, 1029557624u, 3302959071u, 3231711232u, 0, LOGBF_TOLERANCE, 0},
+{1232, 1207675424u, 3042692550u, 1098907648u, 0, LOGBF_TOLERANCE, 0},
+{1233, 1028355074u, 3442294040u, 3231711232u, 0, LOGBF_TOLERANCE, 0},
+{1234, 3119299090u, 1187096397u, 3242196992u, 0, LOGBF_TOLERANCE, 0},
+{1235, 1248421894u, 3367769132u, 1101529088u, 0, LOGBF_TOLERANCE, 0},
+{1236, 3353251994u, 1095517730u, 1098907648u, 0, LOGBF_TOLERANCE, 0},
+{1237, 876926659u, 3288089977u, 3250061312u, 0, LOGBF_TOLERANCE, 0},
+{1238, 1076752219u, 876236939u, 1065353216u, 0, LOGBF_TOLERANCE, 0},
+{1239, 3388531942u, 2988520062u, 1101004800u, 0, LOGBF_TOLERANCE, 0},
+{1240, 1273395082u, 3031189261u, 1103101952u, 0, LOGBF_TOLERANCE, 0},
+{1241, 3385588183u, 3258252464u, 1101004800u, 0, LOGBF_TOLERANCE, 0},
+{1242, 862047095u, 829323655u, 3251109888u, 0, LOGBF_TOLERANCE, 0},
+{1243, 3192315328u, 3289489214u, 3225419776u, 0, LOGBF_TOLERANCE, 0},
+{1244, 3441804648u, 3274638356u, 1104674816u, 0, LOGBF_TOLERANCE, 0},
+{1245, 837368567u, 3228474927u, 3252682752u, 0, LOGBF_TOLERANCE, 0},
+{1246, 3392827417u, 1277961150u, 1101529088u, 0, LOGBF_TOLERANCE, 0},
+{1247, 1161241793u, 1328003707u, 1093664768u, 0, LOGBF_TOLERANCE, 0},
+{1248, 856495732u, 3123041418u, 3251109888u, 0, LOGBF_TOLERANCE, 0},
+{1249, 3034494183u, 3041579130u, 3249537024u, 0, LOGBF_TOLERANCE, 0},
+{1250, 1171318485u, 3374409104u, 1094713344u, 0, LOGBF_TOLERANCE, 0},
+{1251, 3047748143u, 831102792u, 3248488448u, 0, LOGBF_TOLERANCE, 0},
+{1252, 1001216371u, 3052357038u, 3238002688u, 0, LOGBF_TOLERANCE, 0},
+{1253, 2999541351u, 3085461799u, 3251634176u, 0, LOGBF_TOLERANCE, 0},
+{1254, 912515889u, 1074635609u, 3247964160u, 0, LOGBF_TOLERANCE, 0},
+{1255, 3391452505u, 897989232u, 1101529088u, 0, LOGBF_TOLERANCE, 0},
+{1256, 3249603369u, 3147662248u, 1082130432u, 0, LOGBF_TOLERANCE, 0},
+{1257, 1220264047u, 2960450369u, 1099956224u, 0, LOGBF_TOLERANCE, 0},
+{1258, 3169816394u, 988430929u, 3233808384u, 0, LOGBF_TOLERANCE, 0},
+{1259, 3098997418u, 3002162688u, 3244294144u, 0, LOGBF_TOLERANCE, 0},
+{1260, 3282212423u, 3174079140u, 1090519040u, 0, LOGBF_TOLERANCE, 0},
+{1261, 3352293320u, 3247843425u, 1098907648u, 0, LOGBF_TOLERANCE, 0},
+{1262, 3296358441u, 875645354u, 1091567616u, 0, LOGBF_TOLERANCE, 0},
+{1263, 1197828352u, 3245614728u, 1097859072u, 0, LOGBF_TOLERANCE, 0},
+{1264, 3340510371u, 914930263u, 1097859072u, 0, LOGBF_TOLERANCE, 0},
+{1265, 1127109339u, 3368125489u, 1088421888u, 0, LOGBF_TOLERANCE, 0},
+{1266, 816173492u, 1083268662u, 3253731328u, 0, LOGBF_TOLERANCE, 0},
+{1267, 909467381u, 1232375752u, 3247964160u, 0, LOGBF_TOLERANCE, 0},
+{1268, 1200599955u, 2981200675u, 1098907648u, 0, LOGBF_TOLERANCE, 0},
+{1269, 962230977u, 2988248037u, 3243245568u, 0, LOGBF_TOLERANCE, 0},
+{1270, 2996667337u, 1068572835u, 3251634176u, 0, LOGBF_TOLERANCE, 0},
+{1271, 3192887808u, 3191848339u, 3225419776u, 0, LOGBF_TOLERANCE, 0},
+{1272, 3237183876u, 3179379969u, 1073741824u, 0, LOGBF_TOLERANCE, 0},
+{1273, 939285924u, 3056079386u, 3246391296u, 0, LOGBF_TOLERANCE, 0},
+{1274, 944050180u, 3452557879u, 3245342720u, 0, LOGBF_TOLERANCE, 0},
+{1275, 3058135703u, 3090284601u, 3247964160u, 0, LOGBF_TOLERANCE, 0},
+{1276, 3480592662u, 3261728191u, 1106771968u, 0, LOGBF_TOLERANCE, 0},
+{1277, 3061939312u, 3274418540u, 3247439872u, 0, LOGBF_TOLERANCE, 0},
+{1278, 1003299981u, 853295521u, 3238002688u, 0, LOGBF_TOLERANCE, 0},
+{1279, 1155775526u, 1255814444u, 1092616192u, 0, LOGBF_TOLERANCE, 0},
+{1280, 1234491880u, 3408568717u, 1101004800u, 0, LOGBF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_LOGBF_H multiple inclusion protection
+
+// EOF logbf.h
diff --git a/packages/language/c/libm/current/tests/vectors/logf.c b/packages/language/c/libm/current/tests/vectors/logf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/logf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      log.c
+//
+//      Test of log() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_double_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/logf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(logf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &logf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &logf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("logf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("logf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library log() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "log() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF log.c
diff --git a/packages/language/c/libm/current/tests/vectors/logf.h b/packages/language/c/libm/current/tests/vectors/logf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/logf.h
@@ -0,0 +1,874 @@
+#ifndef CYGONCE_LIBM_LOG_H
+#define CYGONCE_LIBM_LOG_H
+//===========================================================================
+//
+//      log.h
+//
+//      Test vectors for testing of log() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/log.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define LOG_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t logf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+{0, 3214514586u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{1, 3214430700u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{2, 3214346813u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{3, 3214262927u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{4, 3214179041u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{5, 3214095155u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{6, 3214011269u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{7, 3213927383u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{8, 3213843497u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{9, 3213759611u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{10, 3213675725u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{11, 3213591839u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{12, 3213507953u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{13, 3213424067u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{14, 3213340180u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{15, 3213256294u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{16, 3213172408u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{17, 3213088522u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{18, 3213004636u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{19, 3212920750u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{20, 3212836864u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{21, 3212669092u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{22, 3212501320u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{23, 3212333548u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{24, 3212165775u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{25, 3211998003u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{26, 3211830231u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{27, 3211662459u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{28, 3211494687u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{29, 3211326915u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{30, 3211159142u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{31, 3210991370u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{32, 3210823598u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{33, 3210655826u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{34, 3210488054u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{35, 3210320282u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{36, 3210152509u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{37, 3209984737u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{38, 3209816965u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{39, 3209649193u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{40, 3209481421u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{41, 3209313649u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{42, 3209145876u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{43, 3208978104u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
+{44, 3208810332u, 1115684864u, 2143289344u, EDOM, LOG_TOLERANCE, 0},
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+{724, 1283938137u, 1099996906u, 1099996906u, 0, LOG_TOLERANCE, 0},
+{725, 1317098613u, 1101426722u, 1101426722u, 0, LOG_TOLERANCE, 0},
+{726, 1284220009u, 1100013309u, 1100013309u, 0, LOG_TOLERANCE, 0},
+{727, 1092245127u, 1074859842u, 1074859842u, 0, LOG_TOLERANCE, 0},
+{728, 1165676440u, 1090830769u, 1090830769u, 0, LOG_TOLERANCE, 0},
+{729, 1284174954u, 1100010721u, 1100010721u, 0, LOG_TOLERANCE, 0},
+{730, 1102631663u, 1078523172u, 1078523172u, 0, LOG_TOLERANCE, 0},
+{731, 1125596740u, 1084267198u, 1084267198u, 0, LOG_TOLERANCE, 0},
+{732, 1172529774u, 1091454766u, 1091454766u, 0, LOG_TOLERANCE, 0},
+{733, 1306695905u, 1100993929u, 1100993929u, 0, LOG_TOLERANCE, 0},
+{734, 1078478376u, 1066534362u, 1066534362u, 0, LOG_TOLERANCE, 0},
+{735, 1165177679u, 1090798459u, 1090798459u, 0, LOG_TOLERANCE, 0},
+{736, 1255525865u, 1098658369u, 1098658369u, 0, LOG_TOLERANCE, 0},
+{737, 1222777442u, 1095809745u, 1095809745u, 0, LOG_TOLERANCE, 0},
+{738, 1325324763u, 1101782353u, 1101782353u, 0, LOG_TOLERANCE, 0},
+{739, 1216040565u, 1095193744u, 1095193744u, 0, LOG_TOLERANCE, 0},
+{740, 1158950321u, 1090038805u, 1090038805u, 0, LOG_TOLERANCE, 0},
+{741, 1208345407u, 1094533485u, 1094533485u, 0, LOG_TOLERANCE, 0},
+{742, 1258634105u, 1098889245u, 1098889245u, 0, LOG_TOLERANCE, 0},
+{743, 1248478509u, 1098027406u, 1098027406u, 0, LOG_TOLERANCE, 0},
+{744, 1153863988u, 1089199028u, 1089199028u, 0, LOG_TOLERANCE, 0},
+{745, 1235620969u, 1096939871u, 1096939871u, 0, LOG_TOLERANCE, 0},
+{746, 1097120930u, 1076509995u, 1076509995u, 0, LOG_TOLERANCE, 0},
+{747, 1322294974u, 1101677409u, 1101677409u, 0, LOG_TOLERANCE, 0},
+{748, 1147712200u, 1088078034u, 1088078034u, 0, LOG_TOLERANCE, 0},
+{749, 1124721745u, 1084073380u, 1084073380u, 0, LOG_TOLERANCE, 0},
+{750, 1114260656u, 1082277595u, 1082277595u, 0, LOG_TOLERANCE, 0},
+{751, 1155676504u, 1089472492u, 1089472492u, 0, LOG_TOLERANCE, 0},
+{752, 1315090496u, 1101357549u, 1101357549u, 0, LOG_TOLERANCE, 0},
+{753, 1082919539u, 1069347855u, 1069347855u, 0, LOG_TOLERANCE, 0},
+{754, 1335399673u, 1102240222u, 1102240222u, 0, LOG_TOLERANCE, 0},
+{755, 1072458508u, 1058870026u, 1058870026u, 0, LOG_TOLERANCE, 0},
+{756, 1155531601u, 1089451895u, 1089451895u, 0, LOG_TOLERANCE, 0},
+{757, 1104656093u, 1079171407u, 1079171407u, 0, LOG_TOLERANCE, 0},
+{758, 1321036318u, 1101626775u, 1101626775u, 0, LOG_TOLERANCE, 0},
+{759, 1172239631u, 1091434149u, 1091434149u, 0, LOG_TOLERANCE, 0},
+{760, 1107620519u, 1080048642u, 1080048642u, 0, LOG_TOLERANCE, 0},
+{761, 1155477903u, 1089444210u, 1089444210u, 0, LOG_TOLERANCE, 0},
+{762, 1126405528u, 1084431697u, 1084431697u, 0, LOG_TOLERANCE, 0},
+{763, 1090330020u, 1074027503u, 1074027503u, 0, LOG_TOLERANCE, 0},
+{764, 1228207362u, 1096303012u, 1096303012u, 0, LOG_TOLERANCE, 0},
+{765, 1290175785u, 1100276110u, 1100276110u, 0, LOG_TOLERANCE, 0},
+{766, 1214223128u, 1095071136u, 1095071136u, 0, LOG_TOLERANCE, 0},
+{767, 1275438936u, 1099626919u, 1099626919u, 0, LOG_TOLERANCE, 0},
+{768, 1315857601u, 1101383945u, 1101383945u, 0, LOG_TOLERANCE, 0},
+{769, 1305742382u, 1100959135u, 1100959135u, 0, LOG_TOLERANCE, 0},
+{770, 1078359574u, 1066458087u, 1066458087u, 0, LOG_TOLERANCE, 0},
+{771, 1207675424u, 1094468419u, 1094468419u, 0, LOG_TOLERANCE, 0},
+{772, 1248421894u, 1098023532u, 1098023532u, 0, LOG_TOLERANCE, 0},
+{773, 1205768346u, 1094339572u, 1094339572u, 0, LOG_TOLERANCE, 0},
+{774, 1076752219u, 1065349836u, 1065349836u, 0, LOG_TOLERANCE, 0},
+{775, 1241048294u, 1097364082u, 1097364082u, 0, LOG_TOLERANCE, 0},
+{776, 1273395082u, 1099549172u, 1099549172u, 0, LOG_TOLERANCE, 0},
+{777, 1238104535u, 1097155389u, 1097155389u, 0, LOG_TOLERANCE, 0},
+{778, 1294321000u, 1100466645u, 1100466645u, 0, LOG_TOLERANCE, 0},
+{779, 1245343769u, 1097787935u, 1097787935u, 0, LOG_TOLERANCE, 0},
+{780, 1161241793u, 1090483093u, 1090483093u, 0, LOG_TOLERANCE, 0},
+{781, 1171318485u, 1091365870u, 1091365870u, 0, LOG_TOLERANCE, 0},
+{782, 1243968857u, 1097662758u, 1097662758u, 0, LOG_TOLERANCE, 0},
+{783, 1102119721u, 1078342044u, 1078342044u, 0, LOG_TOLERANCE, 0},
+{784, 1220264047u, 1095614846u, 1095614846u, 0, LOG_TOLERANCE, 0},
+{785, 1134728775u, 1085872507u, 1085872507u, 0, LOG_TOLERANCE, 0},
+{786, 1204809672u, 1094268284u, 1094268284u, 0, LOG_TOLERANCE, 0},
+{787, 1148874793u, 1088232109u, 1088232109u, 0, LOG_TOLERANCE, 0},
+{788, 1197828352u, 1093644519u, 1093644519u, 0, LOG_TOLERANCE, 0},
+{789, 1193026723u, 1093241091u, 1093241091u, 0, LOG_TOLERANCE, 0},
+{790, 1127109339u, 1084565044u, 1084565044u, 0, LOG_TOLERANCE, 0},
+{791, 1200599955u, 1093880840u, 1093880840u, 0, LOG_TOLERANCE, 0},
+{792, 1089700228u, 1073865159u, 1073865159u, 0, LOG_TOLERANCE, 0},
+{793, 1333109014u, 1102126438u, 1102126438u, 0, LOG_TOLERANCE, 0},
+{794, 1155775526u, 1089486453u, 1089486453u, 0, LOG_TOLERANCE, 0},
+{795, 1234491880u, 1096825030u, 1096825030u, 0, LOG_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_LOG_H multiple inclusion protection
+
+// EOF log.h
diff --git a/packages/language/c/libm/current/tests/vectors/modff.c b/packages/language/c/libm/current/tests/vectors/modff.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/modff.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      modff.c
+//
+//      Test of modff() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/modff.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(modff_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &modff, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_FLOAT_P, CYG_LIBM_TEST_VEC_FLOAT,
+                     &modff_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("modff() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("modff() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library modff() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "modff() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF modff.c
diff --git a/packages/language/c/libm/current/tests/vectors/modff.h b/packages/language/c/libm/current/tests/vectors/modff.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/modff.h
@@ -0,0 +1,777 @@
+#ifndef CYGONCE_LIBM_MODFF_H
+#define CYGONCE_LIBM_MODFF_H
+//===========================================================================
+//
+//      modff.h
+//
+//      Test vectors for testing of modff() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/modff.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define MODFF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t modff_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 1107800421u, 1107558400u, 1064065344u, 0, MODFF_TOLERANCE, 0},
+{1, 1203999711u, 1203999616u, 1061027840u, 0, MODFF_TOLERANCE, 0},
+{2, 896005582u, 0u, 896005582u, 0, MODFF_TOLERANCE, 0},
+{3, 3368700125u, 3368700096u, 3211264000u, 0, MODFF_TOLERANCE, 0},
+{4, 3308232444u, 3308228608u, 3211771904u, 0, MODFF_TOLERANCE, 0},
+{5, 1224242132u, 1224242112u, 1059061760u, 0, MODFF_TOLERANCE, 0},
+{6, 3221027117u, 3212836864u, 3212440154u, 0, MODFF_TOLERANCE, 0},
+{7, 1284201705u, 1284201705u, 0u, 0, MODFF_TOLERANCE, 0},
+{8, 1198712763u, 1198712576u, 1060831232u, 0, MODFF_TOLERANCE, 0},
+{9, 919636942u, 0u, 919636942u, 0, MODFF_TOLERANCE, 0},
+{10, 954173073u, 0u, 954173073u, 0, MODFF_TOLERANCE, 0},
+{11, 1035260608u, 0u, 1035260608u, 0, MODFF_TOLERANCE, 0},
+{12, 966554515u, 0u, 966554515u, 0, MODFF_TOLERANCE, 0},
+{13, 3234538174u, 3233808384u, 3199347680u, 0, MODFF_TOLERANCE, 0},
+{14, 1312607135u, 1312607135u, 0u, 0, MODFF_TOLERANCE, 0},
+{15, 1194999402u, 1194999296u, 1054081024u, 0, MODFF_TOLERANCE, 0},
+{16, 1166191415u, 1166190592u, 1053671424u, 0, MODFF_TOLERANCE, 0},
+{17, 1018661564u, 0u, 1018661564u, 0, MODFF_TOLERANCE, 0},
+{18, 1130472166u, 1130430464u, 1059251712u, 0, MODFF_TOLERANCE, 0},
+{19, 1234419246u, 1234419240u, 1061158912u, 0, MODFF_TOLERANCE, 0},
+{20, 1302107128u, 1302107128u, 0u, 0, MODFF_TOLERANCE, 0},
+{21, 3370647675u, 3370647648u, 3210215424u, 0, MODFF_TOLERANCE, 0},
+{22, 1052801068u, 0u, 1052801068u, 0, MODFF_TOLERANCE, 0},
+{23, 1060849628u, 0u, 1060849628u, 0, MODFF_TOLERANCE, 0},
+{24, 3446630737u, 3446630737u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{25, 3484320003u, 3484320003u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{26, 3305392896u, 3305390080u, 3207593984u, 0, MODFF_TOLERANCE, 0},
+{27, 882596369u, 0u, 882596369u, 0, MODFF_TOLERANCE, 0},
+{28, 1256676590u, 1256676590u, 0u, 0, MODFF_TOLERANCE, 0},
+{29, 1167223673u, 1167222784u, 1054752768u, 0, MODFF_TOLERANCE, 0},
+{30, 968192794u, 0u, 968192794u, 0, MODFF_TOLERANCE, 0},
+{31, 878547432u, 0u, 878547432u, 0, MODFF_TOLERANCE, 0},
+{32, 1111584337u, 1111490560u, 1052190848u, 0, MODFF_TOLERANCE, 0},
+{33, 1052361612u, 0u, 1052361612u, 0, MODFF_TOLERANCE, 0},
+{34, 1280025214u, 1280025214u, 0u, 0, MODFF_TOLERANCE, 0},
+{35, 906701409u, 0u, 906701409u, 0, MODFF_TOLERANCE, 0},
+{36, 3471653172u, 3471653172u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{37, 1154138102u, 1154129920u, 1065332736u, 0, MODFF_TOLERANCE, 0},
+{38, 3231467496u, 3229614080u, 3210886976u, 0, MODFF_TOLERANCE, 0},
+{39, 934336592u, 0u, 934336592u, 0, MODFF_TOLERANCE, 0},
+{40, 1341514497u, 1341514497u, 0u, 0, MODFF_TOLERANCE, 0},
+{41, 3466051188u, 3466051188u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{42, 1272351391u, 1272351391u, 0u, 0, MODFF_TOLERANCE, 0},
+{43, 3373485062u, 3373485056u, 3200253952u, 0, MODFF_TOLERANCE, 0},
+{44, 3319724992u, 3319724032u, 3203399680u, 0, MODFF_TOLERANCE, 0},
+{45, 3354615790u, 3354615680u, 3210477568u, 0, MODFF_TOLERANCE, 0},
+{46, 3266377514u, 3266314240u, 3203869184u, 0, MODFF_TOLERANCE, 0},
+{47, 917622040u, 0u, 917622040u, 0, MODFF_TOLERANCE, 0},
+{48, 1334966485u, 1334966485u, 0u, 0, MODFF_TOLERANCE, 0},
+{49, 940236348u, 0u, 940236348u, 0, MODFF_TOLERANCE, 0},
+{50, 3304072663u, 3304071168u, 3191529472u, 0, MODFF_TOLERANCE, 0},
+{51, 977028681u, 0u, 977028681u, 0, MODFF_TOLERANCE, 0},
+{52, 3251541546u, 3251109888u, 3209872704u, 0, MODFF_TOLERANCE, 0},
+{53, 3355962282u, 3355962240u, 3207069696u, 0, MODFF_TOLERANCE, 0},
+{54, 3371863479u, 3371863456u, 3208118272u, 0, MODFF_TOLERANCE, 0},
+{55, 1014861921u, 0u, 1014861921u, 0, MODFF_TOLERANCE, 0},
+{56, 966573255u, 0u, 966573255u, 0, MODFF_TOLERANCE, 0},
+{57, 1306460502u, 1306460502u, 0u, 0, MODFF_TOLERANCE, 0},
+{58, 903489435u, 0u, 903489435u, 0, MODFF_TOLERANCE, 0},
+{59, 1197542187u, 1197542144u, 1043070976u, 0, MODFF_TOLERANCE, 0},
+{60, 922888249u, 0u, 922888249u, 0, MODFF_TOLERANCE, 0},
+{61, 1139392309u, 1139376128u, 1056756736u, 0, MODFF_TOLERANCE, 0},
+{62, 1184239996u, 1184239616u, 1061027840u, 0, MODFF_TOLERANCE, 0},
+{63, 3224098462u, 3221225472u, 3207551608u, 0, MODFF_TOLERANCE, 0},
+{64, 1252490238u, 1252490238u, 0u, 0, MODFF_TOLERANCE, 0},
+{65, 1173619825u, 1173618688u, 1057890304u, 0, MODFF_TOLERANCE, 0},
+{66, 1001673627u, 0u, 1001673627u, 0, MODFF_TOLERANCE, 0},
+{67, 3462631271u, 3462631271u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{68, 976098044u, 0u, 976098044u, 0, MODFF_TOLERANCE, 0},
+{69, 1151967422u, 1151967232u, 1019084800u, 0, MODFF_TOLERANCE, 0},
+{70, 941796645u, 0u, 941796645u, 0, MODFF_TOLERANCE, 0},
+{71, 886451963u, 0u, 886451963u, 0, MODFF_TOLERANCE, 0},
+{72, 1103058486u, 1102577664u, 1063962304u, 0, MODFF_TOLERANCE, 0},
+{73, 3217259624u, 3212836864u, 3204905168u, 0, MODFF_TOLERANCE, 0},
+{74, 3287199470u, 3287187456u, 3199973376u, 0, MODFF_TOLERANCE, 0},
+{75, 893184329u, 0u, 893184329u, 0, MODFF_TOLERANCE, 0},
+{76, 1243067084u, 1243067084u, 0u, 0, MODFF_TOLERANCE, 0},
+{77, 1143233714u, 1143226368u, 1055232000u, 0, MODFF_TOLERANCE, 0},
+{78, 1007268238u, 0u, 1007268238u, 0, MODFF_TOLERANCE, 0},
+{79, 1139941253u, 1139933184u, 1048324096u, 0, MODFF_TOLERANCE, 0},
+{80, 1147688821u, 1147682816u, 1052485632u, 0, MODFF_TOLERANCE, 0},
+{81, 3234638157u, 3233808384u, 3200947408u, 0, MODFF_TOLERANCE, 0},
+{82, 3449209899u, 3449209899u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{83, 3240298487u, 3240099840u, 3191995840u, 0, MODFF_TOLERANCE, 0},
+{84, 1020260821u, 0u, 1020260821u, 0, MODFF_TOLERANCE, 0},
+{85, 1288902137u, 1288902137u, 0u, 0, MODFF_TOLERANCE, 0},
+{86, 1333134799u, 1333134799u, 0u, 0, MODFF_TOLERANCE, 0},
+{87, 1338107877u, 1338107877u, 0u, 0, MODFF_TOLERANCE, 0},
+{88, 1187847971u, 1187847680u, 1058111488u, 0, MODFF_TOLERANCE, 0},
+{89, 1317663644u, 1317663644u, 0u, 0, MODFF_TOLERANCE, 0},
+{90, 1038851706u, 0u, 1038851706u, 0, MODFF_TOLERANCE, 0},
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+{548, 3425290480u, 3425290480u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{549, 1139193797u, 1139179520u, 1054807040u, 0, MODFF_TOLERANCE, 0},
+{550, 1039917375u, 0u, 1039917375u, 0, MODFF_TOLERANCE, 0},
+{551, 1122740999u, 1122631680u, 1062568832u, 0, MODFF_TOLERANCE, 0},
+{552, 3220979495u, 3212836864u, 3212344910u, 0, MODFF_TOLERANCE, 0},
+{553, 3429223871u, 3429223871u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{554, 1311016004u, 1311016004u, 0u, 0, MODFF_TOLERANCE, 0},
+{555, 3334899880u, 3334899712u, 3198681088u, 0, MODFF_TOLERANCE, 0},
+{556, 1128016396u, 1128005632u, 1042821120u, 0, MODFF_TOLERANCE, 0},
+{557, 1105151547u, 1104674816u, 1063831392u, 0, MODFF_TOLERANCE, 0},
+{558, 3404762495u, 3404762494u, 3204448256u, 0, MODFF_TOLERANCE, 0},
+{559, 1206054701u, 1206054656u, 1051983872u, 0, MODFF_TOLERANCE, 0},
+{560, 1162227076u, 1162223616u, 1062748160u, 0, MODFF_TOLERANCE, 0},
+{561, 970745811u, 0u, 970745811u, 0, MODFF_TOLERANCE, 0},
+{562, 3313826904u, 3313825792u, 3205169152u, 0, MODFF_TOLERANCE, 0},
+{563, 1213609983u, 1213609920u, 1065091072u, 0, MODFF_TOLERANCE, 0},
+{564, 919983950u, 0u, 919983950u, 0, MODFF_TOLERANCE, 0},
+{565, 1246902946u, 1246902944u, 1056964608u, 0, MODFF_TOLERANCE, 0},
+{566, 995850843u, 0u, 995850843u, 0, MODFF_TOLERANCE, 0},
+{567, 1332031130u, 1332031130u, 0u, 0, MODFF_TOLERANCE, 0},
+{568, 3362082828u, 3362082816u, 3191865344u, 0, MODFF_TOLERANCE, 0},
+{569, 3374056268u, 3374056256u, 3208642560u, 0, MODFF_TOLERANCE, 0},
+{570, 1029480631u, 0u, 1029480631u, 0, MODFF_TOLERANCE, 0},
+{571, 3384988527u, 3384988520u, 3210739712u, 0, MODFF_TOLERANCE, 0},
+{572, 1317696241u, 1317696241u, 0u, 0, MODFF_TOLERANCE, 0},
+{573, 3235395924u, 3233808384u, 3208759968u, 0, MODFF_TOLERANCE, 0},
+{574, 1132055244u, 1132003328u, 1061866496u, 0, MODFF_TOLERANCE, 0},
+{575, 3341877624u, 3341877504u, 3203399680u, 0, MODFF_TOLERANCE, 0},
+{576, 1228636133u, 1228636128u, 1050673152u, 0, MODFF_TOLERANCE, 0},
+{577, 886552820u, 0u, 886552820u, 0, MODFF_TOLERANCE, 0},
+{578, 3335899347u, 3335899136u, 3201499136u, 0, MODFF_TOLERANCE, 0},
+{579, 3307203982u, 3307200512u, 3210272768u, 0, MODFF_TOLERANCE, 0},
+{580, 1207246237u, 1207246208u, 1047003136u, 0, MODFF_TOLERANCE, 0},
+{581, 1165476654u, 1165475840u, 1045135360u, 0, MODFF_TOLERANCE, 0},
+{582, 3350219111u, 3350219008u, 3209560064u, 0, MODFF_TOLERANCE, 0},
+{583, 1215278023u, 1215278016u, 1038090240u, 0, MODFF_TOLERANCE, 0},
+{584, 1017239798u, 0u, 1017239798u, 0, MODFF_TOLERANCE, 0},
+{585, 3438501281u, 3438501281u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{586, 1149651309u, 1149648896u, 1050071040u, 0, MODFF_TOLERANCE, 0},
+{587, 970030475u, 0u, 970030475u, 0, MODFF_TOLERANCE, 0},
+{588, 1111943722u, 1111752704u, 1060801152u, 0, MODFF_TOLERANCE, 0},
+{589, 1158358450u, 1158356992u, 1052131328u, 0, MODFF_TOLERANCE, 0},
+{590, 1189849849u, 1189849600u, 1056505856u, 0, MODFF_TOLERANCE, 0},
+{591, 3382739134u, 3382739128u, 3208642560u, 0, MODFF_TOLERANCE, 0},
+{592, 1249758327u, 1249758324u, 1061158912u, 0, MODFF_TOLERANCE, 0},
+{593, 3445282331u, 3445282331u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{594, 1168098747u, 1168097280u, 1060593664u, 0, MODFF_TOLERANCE, 0},
+{595, 1316854744u, 1316854744u, 0u, 0, MODFF_TOLERANCE, 0},
+{596, 892549317u, 0u, 892549317u, 0, MODFF_TOLERANCE, 0},
+{597, 1179637545u, 1179636736u, 1061830656u, 0, MODFF_TOLERANCE, 0},
+{598, 3301009024u, 3301007360u, 3192913920u, 0, MODFF_TOLERANCE, 0},
+{599, 3406174560u, 3406174560u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{600, 3233089227u, 3231711232u, 3207083608u, 0, MODFF_TOLERANCE, 0},
+{601, 1212652543u, 1212652480u, 1065091072u, 0, MODFF_TOLERANCE, 0},
+{602, 3218245284u, 3212836864u, 3206876488u, 0, MODFF_TOLERANCE, 0},
+{603, 1238873830u, 1238873824u, 1061158912u, 0, MODFF_TOLERANCE, 0},
+{604, 3215981890u, 3212836864u, 3200251144u, 0, MODFF_TOLERANCE, 0},
+{605, 3240474694u, 3240099840u, 3199666368u, 0, MODFF_TOLERANCE, 0},
+{606, 1266687209u, 1266687209u, 0u, 0, MODFF_TOLERANCE, 0},
+{607, 3410090781u, 3410090781u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{608, 3487959775u, 3487959775u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{609, 3331372071u, 3331372032u, 3181117440u, 0, MODFF_TOLERANCE, 0},
+{610, 943645710u, 0u, 943645710u, 0, MODFF_TOLERANCE, 0},
+{611, 3345065699u, 3345065472u, 3210936320u, 0, MODFF_TOLERANCE, 0},
+{612, 3282620725u, 3282599936u, 3206703616u, 0, MODFF_TOLERANCE, 0},
+{613, 935847271u, 0u, 935847271u, 0, MODFF_TOLERANCE, 0},
+{614, 1067255804u, 1065353216u, 1047019488u, 0, MODFF_TOLERANCE, 0},
+{615, 3410336089u, 3410336089u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{616, 1111437780u, 1111228416u, 1061975296u, 0, MODFF_TOLERANCE, 0},
+{617, 1336840432u, 1336840432u, 0u, 0, MODFF_TOLERANCE, 0},
+{618, 1141063391u, 1141047296u, 1065057280u, 0, MODFF_TOLERANCE, 0},
+{619, 1168908072u, 1168906240u, 1063583744u, 0, MODFF_TOLERANCE, 0},
+{620, 3289799763u, 3289792512u, 3202521088u, 0, MODFF_TOLERANCE, 0},
+{621, 3353679791u, 3353679744u, 3199991808u, 0, MODFF_TOLERANCE, 0},
+{622, 897158391u, 0u, 897158391u, 0, MODFF_TOLERANCE, 0},
+{623, 1001823878u, 0u, 1001823878u, 0, MODFF_TOLERANCE, 0},
+{624, 1016826861u, 0u, 1016826861u, 0, MODFF_TOLERANCE, 0},
+{625, 1009130212u, 0u, 1009130212u, 0, MODFF_TOLERANCE, 0},
+{626, 1004302940u, 0u, 1004302940u, 0, MODFF_TOLERANCE, 0},
+{627, 3367127535u, 3367127520u, 3203399680u, 0, MODFF_TOLERANCE, 0},
+{628, 943136342u, 0u, 943136342u, 0, MODFF_TOLERANCE, 0},
+{629, 1032920919u, 0u, 1032920919u, 0, MODFF_TOLERANCE, 0},
+{630, 3449126417u, 3449126417u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{631, 3281952870u, 3281944576u, 3196164096u, 0, MODFF_TOLERANCE, 0},
+{632, 1237868497u, 1237868496u, 1040187392u, 0, MODFF_TOLERANCE, 0},
+{633, 1153753924u, 1153753088u, 1037107200u, 0, MODFF_TOLERANCE, 0},
+{634, 3322269242u, 3322268672u, 3205398528u, 0, MODFF_TOLERANCE, 0},
+{635, 1120261759u, 1120141312u, 1063993216u, 0, MODFF_TOLERANCE, 0},
+{636, 892210998u, 0u, 892210998u, 0, MODFF_TOLERANCE, 0},
+{637, 3226328360u, 3225419776u, 3193819776u, 0, MODFF_TOLERANCE, 0},
+{638, 3366432856u, 3366432832u, 3208642560u, 0, MODFF_TOLERANCE, 0},
+{639, 3349595986u, 3349595904u, 3206807552u, 0, MODFF_TOLERANCE, 0},
+{640, 3251588707u, 3251109888u, 3211381856u, 0, MODFF_TOLERANCE, 0},
+{641, 3306023523u, 3306020864u, 3206950912u, 0, MODFF_TOLERANCE, 0},
+{642, 1087750238u, 1086324736u, 1059980016u, 0, MODFF_TOLERANCE, 0},
+{643, 1099325523u, 1098907648u, 1061948000u, 0, MODFF_TOLERANCE, 0},
+{644, 3359488363u, 3359488320u, 3207331840u, 0, MODFF_TOLERANCE, 0},
+{645, 1066116543u, 1065353216u, 1035623408u, 0, MODFF_TOLERANCE, 0},
+{646, 3364074347u, 3364074336u, 3199205376u, 0, MODFF_TOLERANCE, 0},
+{647, 1030612298u, 0u, 1030612298u, 0, MODFF_TOLERANCE, 0},
+{648, 3345396001u, 3345395968u, 3187933184u, 0, MODFF_TOLERANCE, 0},
+{649, 989161453u, 0u, 989161453u, 0, MODFF_TOLERANCE, 0},
+{650, 1186234578u, 1186234368u, 1053949952u, 0, MODFF_TOLERANCE, 0},
+{651, 1331680743u, 1331680743u, 0u, 0, MODFF_TOLERANCE, 0},
+{652, 1009396165u, 0u, 1009396165u, 0, MODFF_TOLERANCE, 0},
+{653, 894661023u, 0u, 894661023u, 0, MODFF_TOLERANCE, 0},
+{654, 1326067357u, 1326067357u, 0u, 0, MODFF_TOLERANCE, 0},
+{655, 887589411u, 0u, 887589411u, 0, MODFF_TOLERANCE, 0},
+{656, 1292305693u, 1292305693u, 0u, 0, MODFF_TOLERANCE, 0},
+{657, 1045232522u, 0u, 1045232522u, 0, MODFF_TOLERANCE, 0},
+{658, 3234993273u, 3233808384u, 3205538760u, 0, MODFF_TOLERANCE, 0},
+{659, 962515365u, 0u, 962515365u, 0, MODFF_TOLERANCE, 0},
+{660, 3349432725u, 3349432704u, 3190292480u, 0, MODFF_TOLERANCE, 0},
+{661, 928848003u, 0u, 928848003u, 0, MODFF_TOLERANCE, 0},
+{662, 912423027u, 0u, 912423027u, 0, MODFF_TOLERANCE, 0},
+{663, 3228795133u, 3225419776u, 3209561076u, 0, MODFF_TOLERANCE, 0},
+{664, 3273940030u, 3273916416u, 3199761408u, 0, MODFF_TOLERANCE, 0},
+{665, 3296784303u, 3296780288u, 3204116480u, 0, MODFF_TOLERANCE, 0},
+{666, 3276182352u, 3276144640u, 3205713920u, 0, MODFF_TOLERANCE, 0},
+{667, 965402291u, 0u, 965402291u, 0, MODFF_TOLERANCE, 0},
+{668, 3388153589u, 3388153584u, 3206545408u, 0, MODFF_TOLERANCE, 0},
+{669, 3426245389u, 3426245389u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{670, 1133410485u, 1133379584u, 1064397312u, 0, MODFF_TOLERANCE, 0},
+{671, 3329658993u, 3329658880u, 3185704960u, 0, MODFF_TOLERANCE, 0},
+{672, 1088652637u, 1088421888u, 1038178112u, 0, MODFF_TOLERANCE, 0},
+{673, 3369970587u, 3369970560u, 3210215424u, 0, MODFF_TOLERANCE, 0},
+{674, 959121458u, 0u, 959121458u, 0, MODFF_TOLERANCE, 0},
+{675, 1270451568u, 1270451568u, 0u, 0, MODFF_TOLERANCE, 0},
+{676, 928393353u, 0u, 928393353u, 0, MODFF_TOLERANCE, 0},
+{677, 989498922u, 0u, 989498922u, 0, MODFF_TOLERANCE, 0},
+{678, 1280215674u, 1280215674u, 0u, 0, MODFF_TOLERANCE, 0},
+{679, 1171873518u, 1171871744u, 1063108608u, 0, MODFF_TOLERANCE, 0},
+{680, 954709738u, 0u, 954709738u, 0, MODFF_TOLERANCE, 0},
+{681, 3298258100u, 3298254848u, 3200991232u, 0, MODFF_TOLERANCE, 0},
+{682, 935525182u, 0u, 935525182u, 0, MODFF_TOLERANCE, 0},
+{683, 3415208824u, 3415208824u, 2147483648u, 0, MODFF_TOLERANCE, 0},
+{684, 1001897182u, 0u, 1001897182u, 0, MODFF_TOLERANCE, 0},
+{685, 3245830463u, 3245342720u, 3203278816u, 0, MODFF_TOLERANCE, 0},
+{686, 985903305u, 0u, 985903305u, 0, MODFF_TOLERANCE, 0},
+{687, 3333087577u, 3333087232u, 3207364608u, 0, MODFF_TOLERANCE, 0},
+{688, 3357328848u, 3357328832u, 3196059648u, 0, MODFF_TOLERANCE, 0},
+{689, 982612185u, 0u, 982612185u, 0, MODFF_TOLERANCE, 0},
+{690, 923582663u, 0u, 923582663u, 0, MODFF_TOLERANCE, 0},
+{691, 3267868136u, 3267756032u, 3210408960u, 0, MODFF_TOLERANCE, 0},
+{692, 1208301947u, 1208301888u, 1064042496u, 0, MODFF_TOLERANCE, 0},
+{693, 3319048157u, 3319046144u, 3212550144u, 0, MODFF_TOLERANCE, 0},
+{694, 1172271145u, 1172271104u, 1017380864u, 0, MODFF_TOLERANCE, 0},
+{695, 1144755661u, 1144750080u, 1051617280u, 0, MODFF_TOLERANCE, 0},
+{696, 1051585760u, 0u, 1051585760u, 0, MODFF_TOLERANCE, 0},
+{697, 898467286u, 0u, 898467286u, 0, MODFF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_MODFF_H multiple inclusion protection
+
+// EOF modff.h
diff --git a/packages/language/c/libm/current/tests/vectors/nextafterf.c b/packages/language/c/libm/current/tests/vectors/nextafterf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/nextafterf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      nextafterf.c
+//
+//      Test of nextafterf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/nextafterf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(nextafterf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &nextafterf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_FLOAT, CYG_LIBM_TEST_VEC_FLOAT,
+                     &nextafterf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("nextafterf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("nextafterf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library nextafterf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "nextafterf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF nextafterf.c
diff --git a/packages/language/c/libm/current/tests/vectors/nextafterf.h b/packages/language/c/libm/current/tests/vectors/nextafterf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/nextafterf.h
@@ -0,0 +1,1126 @@
+#ifndef CYGONCE_LIBM_NEXTAFTERF_H
+#define CYGONCE_LIBM_NEXTAFTERF_H
+//===========================================================================
+//
+//      nextafterf.h
+//
+//      Test vectors for testing of nextafterf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/nextafterf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define NEXTAFTERF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t nextafterf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 0u, 3214514585u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1, 3214430700u, 0u, 3214430699u, 0, NEXTAFTERF_TOLERANCE, 0},
+{2, 3214346813u, 0u, 3214346812u, 0, NEXTAFTERF_TOLERANCE, 0},
+{3, 3214262927u, 0u, 3214262926u, 0, NEXTAFTERF_TOLERANCE, 0},
+{4, 3214179041u, 0u, 3214179040u, 0, NEXTAFTERF_TOLERANCE, 0},
+{5, 3214095155u, 0u, 3214095154u, 0, NEXTAFTERF_TOLERANCE, 0},
+{6, 3214011269u, 0u, 3214011268u, 0, NEXTAFTERF_TOLERANCE, 0},
+{7, 3213927383u, 0u, 3213927382u, 0, NEXTAFTERF_TOLERANCE, 0},
+{8, 3213843497u, 0u, 3213843496u, 0, NEXTAFTERF_TOLERANCE, 0},
+{9, 3213759611u, 0u, 3213759610u, 0, NEXTAFTERF_TOLERANCE, 0},
+{10, 3213675725u, 0u, 3213675724u, 0, NEXTAFTERF_TOLERANCE, 0},
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+{1023, 1161241793u, 1328003707u, 1161241794u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1024, 3034494183u, 3041579130u, 3034494184u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1025, 1171318485u, 3374409104u, 1171318484u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1026, 1001216371u, 3052357038u, 1001216370u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1027, 912515889u, 1074635609u, 912515890u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1028, 3391452505u, 897989232u, 3391452504u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1029, 3249603369u, 3147662248u, 3249603368u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1030, 3169816394u, 988430929u, 3169816393u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1031, 3282212423u, 3174079140u, 3282212422u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1032, 3352293320u, 3247843425u, 3352293319u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1033, 3296358441u, 875645354u, 3296358440u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1034, 1197828352u, 3245614728u, 1197828351u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1035, 3340510371u, 914930263u, 3340510370u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1036, 1127109339u, 3368125489u, 1127109338u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1037, 909467381u, 1232375752u, 909467382u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1038, 3192887808u, 3191848339u, 3192887807u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1039, 3237183876u, 3179379969u, 3237183875u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1040, 939285924u, 3056079386u, 939285923u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1041, 944050180u, 3452557879u, 944050179u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1042, 3058135703u, 3090284601u, 3058135704u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1043, 3480592662u, 3261728191u, 3480592661u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1044, 3061939312u, 3274418540u, 3061939313u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1045, 1155775526u, 1255814444u, 1155775527u, 0, NEXTAFTERF_TOLERANCE, 0},
+{1046, 1234491880u, 3408568717u, 1234491879u, 0, NEXTAFTERF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_NEXTAFTERF_H multiple inclusion protection
+
+// EOF nextafterf.h
diff --git a/packages/language/c/libm/current/tests/vectors/powf.c b/packages/language/c/libm/current/tests/vectors/powf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/powf.c
@@ -0,0 +1,114 @@
+//===========================================================================
+//
+//      pow.c
+//
+//      Test of pow() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_double_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/powf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(pow_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &powf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_FLOAT,
+                     &pow_vec[0], vec_size );
+
+    if (ret==true) {
+        CYG_TEST_PASS("powf() is stable");
+    } // if
+    else {
+        CYG_TEST_FAIL("powf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library powf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "pow() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF pow.c
diff --git a/packages/language/c/libm/current/tests/vectors/powf.h b/packages/language/c/libm/current/tests/vectors/powf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/powf.h
@@ -0,0 +1,215 @@
+#ifndef CYGONCE_LIBM_POW_H
+#define CYGONCE_LIBM_POW_H
+//===========================================================================
+//
+//      pow.h
+//
+//      Test vectors for testing of pow() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/pow.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define POW_TOLERANCE 2.0E-04
+
+static const Cyg_libm_test_float_vec_t pow_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 1198712763u, 919636942u, 1065353791u, 0, POW_TOLERANCE, 0},
+{1, 954173073u, 850531830u, 1065353213u, 0, POW_TOLERANCE, 0},
+{2, 1166191415u, 1018661564u, 1067076343u, 0, POW_TOLERANCE, 0},
+{3, 1167223673u, 846102364u, 1065353217u, 0, POW_TOLERANCE, 0},
+{4, 968192794u, 878547432u, 1065353188u, 0, POW_TOLERANCE, 0},
+{5, 1306460502u, 903489435u, 1065353488u, 0, POW_TOLERANCE, 0},
+{6, 941796645u, 886451963u, 1065353148u, 0, POW_TOLERANCE, 0},
+{7, 1143233714u, 1007268238u, 1065823341u, 0, POW_TOLERANCE, 0},
+{8, 1309289088u, 1019883016u, 1070767293u, 0, POW_TOLERANCE, 0},
+{9, 1238569473u, 873035665u, 1065353231u, 0, POW_TOLERANCE, 0},
+{10, 1142167709u, 1096445242u, 2119523639u, 0, POW_TOLERANCE, 0},
+{11, 982950501u, 982549888u, 1065228471u, 0, POW_TOLERANCE, 0},
+{12, 1142981585u, 1015602236u, 1066309943u, 0, POW_TOLERANCE, 0},
+{13, 1061834641u, 972388096u, 1065351367u, 0, POW_TOLERANCE, 0},
+{14, 1000611335u, 857599439u, 1065353213u, 0, POW_TOLERANCE, 0},
+{15, 822041816u, 898402905u, 1065352863u, 0, POW_TOLERANCE, 0},
+{16, 977281449u, 879922831u, 1065353189u, 0, POW_TOLERANCE, 0},
+{17, 1086198791u, 920125958u, 1065353312u, 0, POW_TOLERANCE, 0},
+{18, 1255152035u, 851754050u, 1065353219u, 0, POW_TOLERANCE, 0},
+{19, 1094190727u, 1056854532u, 1079464258u, 0, POW_TOLERANCE, 0},
+{20, 1294665325u, 991185677u, 1065721824u, 0, POW_TOLERANCE, 0},
+{21, 1036608591u, 805416536u, 1065353216u, 0, POW_TOLERANCE, 0},
+{22, 1325668223u, 970681762u, 1065429107u, 0, POW_TOLERANCE, 0},
+{23, 1092037607u, 1027330835u, 1066263156u, 0, POW_TOLERANCE, 0},
+{24, 1243664530u, 972879810u, 1065413269u, 0, POW_TOLERANCE, 0},
+{25, 950829092u, 929114193u, 1065351098u, 0, POW_TOLERANCE, 0},
+{26, 1030934236u, 1045139240u, 1058143257u, 0, POW_TOLERANCE, 0},
+{27, 1161858787u, 815362075u, 1065353216u, 0, POW_TOLERANCE, 0},
+{28, 1189120494u, 978961471u, 1065425061u, 0, POW_TOLERANCE, 0},
+{29, 1065798296u, 816191940u, 1065353216u, 0, POW_TOLERANCE, 0},
+{30, 1273397670u, 901308750u, 1065353415u, 0, POW_TOLERANCE, 0},
+{31, 1051773536u, 896271348u, 1065353200u, 0, POW_TOLERANCE, 0},
+{32, 1283624229u, 906796922u, 1065353533u, 0, POW_TOLERANCE, 0},
+{33, 970649315u, 1078286437u, 774321244u, 0, POW_TOLERANCE, 0},
+{34, 1279489061u, 1006049444u, 1066554775u, 0, POW_TOLERANCE, 0},
+{35, 1233171235u, 826460580u, 1065353216u, 0, POW_TOLERANCE, 0},
+{36, 1148920078u, 1007674793u, 1065878255u, 0, POW_TOLERANCE, 0},
+{37, 1000014431u, 831213088u, 1065353216u, 0, POW_TOLERANCE, 0},
+{38, 1234530539u, 1079988872u, 1656602122u, 0, POW_TOLERANCE, 0},
+{39, 1276853215u, 873199561u, 1065353235u, 0, POW_TOLERANCE, 0},
+{40, 1212717473u, 837873779u, 1065353217u, 0, POW_TOLERANCE, 0},
+{41, 1022211242u, 922124181u, 1065352780u, 0, POW_TOLERANCE, 0},
+{42, 1189421739u, 1056599002u, 1125718440u, 0, POW_TOLERANCE, 0},
+{43, 1034611395u, 882288581u, 1065353204u, 0, POW_TOLERANCE, 0},
+{44, 1314588083u, 856187848u, 1065353221u, 0, POW_TOLERANCE, 0},
+{45, 861266716u, 822172554u, 1065353215u, 0, POW_TOLERANCE, 0},
+{46, 1156767533u, 1088986462u, 1730804446u, 0, POW_TOLERANCE, 0},
+{47, 994934087u, 967678094u, 1065321222u, 0, POW_TOLERANCE, 0},
+{48, 918212457u, 1017468331u, 1061718387u, 0, POW_TOLERANCE, 0},
+{49, 959956547u, 876324728u, 1065353191u, 0, POW_TOLERANCE, 0},
+{50, 1206054701u, 826010009u, 1065353216u, 0, POW_TOLERANCE, 0},
+{51, 822524010u, 970745811u, 1065212397u, 0, POW_TOLERANCE, 0},
+{52, 1213609983u, 919983950u, 1065353874u, 0, POW_TOLERANCE, 0},
+{53, 1317696241u, 870681806u, 1065353235u, 0, POW_TOLERANCE, 0},
+{54, 1228636133u, 886552820u, 1065353262u, 0, POW_TOLERANCE, 0},
+{55, 1207246237u, 859223639u, 1065353220u, 0, POW_TOLERANCE, 0},
+{56, 1149651309u, 970030475u, 1065376643u, 0, POW_TOLERANCE, 0},
+{57, 943645710u, 852875779u, 1065353212u, 0, POW_TOLERANCE, 0},
+{58, 935847271u, 1067255804u, 906953987u, 0, POW_TOLERANCE, 0},
+{59, 1001823878u, 1016826861u, 1063778802u, 0, POW_TOLERANCE, 0},
+{60, 1009130212u, 1004302940u, 1064842908u, 0, POW_TOLERANCE, 0},
+{61, 1120261759u, 892210998u, 1065353241u, 0, POW_TOLERANCE, 0},
+{62, 1087750238u, 1099325523u, 1451348348u, 0, POW_TOLERANCE, 0},
+{63, 1186234578u, 858134374u, 1065353219u, 0, POW_TOLERANCE, 0},
+{64, 1331680743u, 1009396165u, 1067511672u, 0, POW_TOLERANCE, 0},
+{65, 847857044u, 894661023u, 1065352979u, 0, POW_TOLERANCE, 0},
+{66, 1270451568u, 928393353u, 1065355037u, 0, POW_TOLERANCE, 0},
+{67, 1171873518u, 954709738u, 1065361420u, 0, POW_TOLERANCE, 0},
+{68, 982612185u, 923582663u, 1065352258u, 0, POW_TOLERANCE, 0},
+{69, 1144755661u, 860947435u, 1065353219u, 0, POW_TOLERANCE, 0},
+{70, 840456845u, 1051585760u, 988879588u, 0, POW_TOLERANCE, 0},
+{71, 898467286u, 839254959u, 1065353214u, 0, POW_TOLERANCE, 0},
+{72, 871130681u, 905123007u, 1065352729u, 0, POW_TOLERANCE, 0},
+{73, 1153863660u, 1011991342u, 1066183352u, 0, POW_TOLERANCE, 0},
+{74, 849056171u, 910674398u, 1065352326u, 0, POW_TOLERANCE, 0},
+{75, 1250249095u, 1069023744u, 1330736323u, 0, POW_TOLERANCE, 0},
+{76, 1025404104u, 1066370251u, 1020631328u, 0, POW_TOLERANCE, 0},
+{77, 1099710167u, 887180181u, 1065353226u, 0, POW_TOLERANCE, 0},
+{78, 1253017688u, 942062372u, 1065358408u, 0, POW_TOLERANCE, 0},
+{79, 1266928623u, 811778614u, 1065353216u, 0, POW_TOLERANCE, 0},
+{80, 1152416724u, 962669179u, 1065366291u, 0, POW_TOLERANCE, 0},
+{81, 835770216u, 865469272u, 1065353194u, 0, POW_TOLERANCE, 0},
+{82, 1278946388u, 825129857u, 1065353216u, 0, POW_TOLERANCE, 0},
+{83, 1297190916u, 811863044u, 1065353216u, 0, POW_TOLERANCE, 0},
+{84, 1277649137u, 961171401u, 1065381745u, 0, POW_TOLERANCE, 0},
+{85, 1306520561u, 957302464u, 1065376134u, 0, POW_TOLERANCE, 0},
+{86, 808412264u, 941158192u, 1065340269u, 0, POW_TOLERANCE, 0},
+{87, 893449284u, 1052877339u, 1000054884u, 0, POW_TOLERANCE, 0},
+{88, 1043025031u, 987068973u, 1065304428u, 0, POW_TOLERANCE, 0},
+{89, 902318189u, 849277289u, 1065353212u, 0, POW_TOLERANCE, 0},
+{90, 1120888322u, 1086209113u, 1398810821u, 0, POW_TOLERANCE, 0},
+{91, 1040617590u, 1034835971u, 1062691293u, 0, POW_TOLERANCE, 0},
+{92, 823111402u, 877253523u, 1065353153u, 0, POW_TOLERANCE, 0},
+{93, 904255535u, 1019967545u, 1060640156u, 0, POW_TOLERANCE, 0},
+{94, 1039827284u, 1072928888u, 1016479294u, 0, POW_TOLERANCE, 0},
+{95, 1021564080u, 1064468397u, 1024039626u, 0, POW_TOLERANCE, 0},
+{96, 1133689539u, 1067460093u, 1150866472u, 0, POW_TOLERANCE, 0},
+{97, 954999730u, 969618597u, 1065294201u, 0, POW_TOLERANCE, 0},
+{98, 940437609u, 860372396u, 1065353208u, 0, POW_TOLERANCE, 0},
+{99, 1299683827u, 966031619u, 1065399368u, 0, POW_TOLERANCE, 0},
+{100, 1229268598u, 1066965677u, 1260934057u, 0, POW_TOLERANCE, 0},
+{101, 1246019790u, 850632217u, 1065353219u, 0, POW_TOLERANCE, 0},
+{102, 1015670780u, 1101217251u, 56180015u, 0, POW_TOLERANCE, 0},
+{103, 1156767169u, 1049756240u, 1091216627u, 0, POW_TOLERANCE, 0},
+{104, 1098662266u, 833740182u, 1065353216u, 0, POW_TOLERANCE, 0},
+{105, 927582555u, 947955456u, 1065341561u, 0, POW_TOLERANCE, 0},
+{106, 860108361u, 921064349u, 1065351270u, 0, POW_TOLERANCE, 0},
+{107, 1245702957u, 894348966u, 1065353313u, 0, POW_TOLERANCE, 0},
+{108, 922255363u, 958305289u, 1065323270u, 0, POW_TOLERANCE, 0},
+{109, 1113104661u, 944376032u, 1065354829u, 0, POW_TOLERANCE, 0},
+{110, 1136714348u, 828849087u, 1065353216u, 0, POW_TOLERANCE, 0},
+{111, 948856035u, 1015466475u, 1062902450u, 0, POW_TOLERANCE, 0},
+{112, 1034561811u, 1054043114u, 1052198635u, 0, POW_TOLERANCE, 0},
+{113, 853827378u, 898656161u, 1065352901u, 0, POW_TOLERANCE, 0},
+{114, 1309658335u, 1010219988u, 1067475014u, 0, POW_TOLERANCE, 0},
+{115, 1161439847u, 943449277u, 1065356223u, 0, POW_TOLERANCE, 0},
+{116, 908663107u, 939489763u, 1065346630u, 0, POW_TOLERANCE, 0},
+{117, 1084378658u, 1009650785u, 1065499167u, 0, POW_TOLERANCE, 0},
+{118, 1226473697u, 821025132u, 1065353216u, 0, POW_TOLERANCE, 0},
+{119, 916831283u, 999465787u, 1064460513u, 0, POW_TOLERANCE, 0},
+{120, 1317098613u, 949986176u, 1065366511u, 0, POW_TOLERANCE, 0},
+{121, 1063693032u, 976661408u, 1065351998u, 0, POW_TOLERANCE, 0},
+{122, 968803479u, 992989712u, 1065000552u, 0, POW_TOLERANCE, 0},
+{123, 1325324763u, 978336043u, 1065497589u, 0, POW_TOLERANCE, 0},
+{124, 1158950321u, 1073578913u, 1251181125u, 0, POW_TOLERANCE, 0},
+{125, 1235620969u, 866627358u, 1065353225u, 0, POW_TOLERANCE, 0},
+{126, 1147712200u, 931865525u, 1065354167u, 0, POW_TOLERANCE, 0},
+{127, 805759679u, 903848557u, 1065352617u, 0, POW_TOLERANCE, 0},
+{128, 1335399673u, 974138676u, 1065456997u, 0, POW_TOLERANCE, 0},
+{129, 1006231203u, 897530770u, 1065353138u, 0, POW_TOLERANCE, 0},
+{130, 951554138u, 1001144381u, 1064549096u, 0, POW_TOLERANCE, 0},
+{131, 942046828u, 986341002u, 1065092748u, 0, POW_TOLERANCE, 0},
+{132, 1076752219u, 876236939u, 1065353217u, 0, POW_TOLERANCE, 0},
+{133, 862047095u, 829323655u, 1065353215u, 0, POW_TOLERANCE, 0},
+{134, 912515889u, 1074635609u, 727565233u, 0, POW_TOLERANCE, 0},
+{135, 1003299981u, 853295521u, 1065353214u, 0, POW_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_POW_H multiple inclusion protection
+
+// EOF pow.h
diff --git a/packages/language/c/libm/current/tests/vectors/remainderf.c b/packages/language/c/libm/current/tests/vectors/remainderf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/remainderf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      remainderf.c
+//
+//      Test of remainderf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/remainderf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(remainderf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &remainderf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_FLOAT, CYG_LIBM_TEST_VEC_FLOAT,
+                     &remainderf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("remainderf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("remainderf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library remainderf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "remainderf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF remainderf.c
diff --git a/packages/language/c/libm/current/tests/vectors/remainderf.h b/packages/language/c/libm/current/tests/vectors/remainderf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/remainderf.h
@@ -0,0 +1,2441 @@
+#ifndef CYGONCE_LIBM_SCABNF_H
+#define CYGONCE_LIBM_SCABNF_H
+//===========================================================================
+//
+//      remainderf.h
+//
+//      Test vectors for testing of remainderf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/remainderf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define REMAINDERF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t remainderf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3212836864u, 3212836864u, 2147483648u, 0, REMAINDERF_TOLERANCE, 0},
+{1, 3212836864u, 3211998003u, 3175926992u, 0, REMAINDERF_TOLERANCE, 0},
+{2, 3212836864u, 3211159142u, 3184315600u, 0, REMAINDERF_TOLERANCE, 0},
+{3, 3212836864u, 3210320282u, 3189348760u, 0, REMAINDERF_TOLERANCE, 0},
+{4, 3212836864u, 3209481421u, 3192704204u, 0, REMAINDERF_TOLERANCE, 0},
+{5, 3212836864u, 3208642560u, 3196059648u, 0, REMAINDERF_TOLERANCE, 0},
+{6, 3212836864u, 3207803699u, 3197737370u, 0, REMAINDERF_TOLERANCE, 0},
+{7, 3212836864u, 3206964838u, 1050253720u, 0, REMAINDERF_TOLERANCE, 0},
+{8, 3212836864u, 3206125978u, 1045220560u, 0, REMAINDERF_TOLERANCE, 0},
+{9, 3212836864u, 3205287117u, 1036831952u, 0, REMAINDERF_TOLERANCE, 0},
+{10, 3212836864u, 3204448256u, 2147483648u, 0, REMAINDERF_TOLERANCE, 0},
+{11, 3212836864u, 3202770534u, 3184315600u, 0, REMAINDERF_TOLERANCE, 0},
+{12, 3212836864u, 3201092813u, 3192704204u, 0, REMAINDERF_TOLERANCE, 0},
+{13, 3212836864u, 3199415091u, 1028443336u, 0, REMAINDERF_TOLERANCE, 0},
+{14, 3212836864u, 3197737370u, 3184315592u, 0, REMAINDERF_TOLERANCE, 0},
+{15, 3212836864u, 3196059648u, 2147483648u, 0, REMAINDERF_TOLERANCE, 0},
+{16, 3212836864u, 3192704205u, 847249408u, 0, REMAINDERF_TOLERANCE, 0},
+{17, 3212836864u, 3189348762u, 1028443352u, 0, REMAINDERF_TOLERANCE, 0},
+{18, 3212836864u, 3184315597u, 847249408u, 0, REMAINDERF_TOLERANCE, 0},
+{19, 3212836864u, 3175926989u, 847249408u, 0, REMAINDERF_TOLERANCE, 0},
+{20, 3212836864u, 632815616u, 2751463424u, 0, REMAINDERF_TOLERANCE, 0},
+{21, 3212836864u, 1028443341u, 847249408u, 0, REMAINDERF_TOLERANCE, 0},
+{22, 3212836864u, 1036831949u, 847249408u, 0, REMAINDERF_TOLERANCE, 0},
+{23, 3212836864u, 1041865114u, 1028443352u, 0, REMAINDERF_TOLERANCE, 0},
+{24, 3212836864u, 1045220557u, 847249408u, 0, REMAINDERF_TOLERANCE, 0},
+{25, 3212836864u, 1048576000u, 2147483648u, 0, REMAINDERF_TOLERANCE, 0},
+{26, 3212836864u, 1050253722u, 3184315592u, 0, REMAINDERF_TOLERANCE, 0},
+{27, 3212836864u, 1051931443u, 1028443336u, 0, REMAINDERF_TOLERANCE, 0},
+{28, 3212836864u, 1053609165u, 3192704204u, 0, REMAINDERF_TOLERANCE, 0},
+{29, 3212836864u, 1055286886u, 3184315600u, 0, REMAINDERF_TOLERANCE, 0},
+{30, 3212836864u, 1056964608u, 2147483648u, 0, REMAINDERF_TOLERANCE, 0},
+{31, 3212836864u, 1057803469u, 1036831952u, 0, REMAINDERF_TOLERANCE, 0},
+{32, 3212836864u, 1058642330u, 1045220560u, 0, REMAINDERF_TOLERANCE, 0},
+{33, 3212836864u, 1059481190u, 1050253720u, 0, REMAINDERF_TOLERANCE, 0},
+{34, 3212836864u, 1060320051u, 3197737370u, 0, REMAINDERF_TOLERANCE, 0},
+{35, 3212836864u, 1061158912u, 3196059648u, 0, REMAINDERF_TOLERANCE, 0},
+{36, 3212836864u, 1061997773u, 3192704204u, 0, REMAINDERF_TOLERANCE, 0},
+{37, 3212836864u, 1062836634u, 3189348760u, 0, REMAINDERF_TOLERANCE, 0},
+{38, 3212836864u, 1063675494u, 3184315600u, 0, REMAINDERF_TOLERANCE, 0},
+{39, 3212836864u, 1064514355u, 3175926992u, 0, REMAINDERF_TOLERANCE, 0},
+{40, 3211998003u, 3212836864u, 1028443344u, 0, REMAINDERF_TOLERANCE, 0},
+{41, 3211998003u, 3211998003u, 2147483648u, 0, REMAINDERF_TOLERANCE, 0},
+{42, 3211998003u, 3211159142u, 3175926992u, 0, REMAINDERF_TOLERANCE, 0},
+{43, 3211998003u, 3210320282u, 3184315592u, 0, REMAINDERF_TOLERANCE, 0},
+{44, 3211998003u, 3209481421u, 3189348760u, 0, REMAINDERF_TOLERANCE, 0},
+{45, 3211998003u, 3208642560u, 3192704204u, 0, REMAINDERF_TOLERANCE, 0},
+{46, 3211998003u, 3207803699u, 3196059648u, 0, REMAINDERF_TOLERANCE, 0},
+{47, 3211998003u, 3206964838u, 3197737370u, 0, REMAINDERF_TOLERANCE, 0},
+{48, 3211998003u, 3206125978u, 1048576002u, 0, REMAINDERF_TOLERANCE, 0},
+{49, 3211998003u, 3205287117u, 1041865116u, 0, REMAINDERF_TOLERANCE, 0},
+{50, 3211998003u, 3204448256u, 1028443344u, 0, REMAINDERF_TOLERANCE, 0},
+{51, 3211998003u, 3202770534u, 3175926992u, 0, REMAINDERF_TOLERANCE, 0},
+{52, 3211998003u, 3201092813u, 3189348760u, 0, REMAINDERF_TOLERANCE, 0},
+{53, 3211998003u, 3199415091u, 1036831948u, 0, REMAINDERF_TOLERANCE, 0},
+{54, 3211998003u, 3197737370u, 3175926976u, 0, REMAINDERF_TOLERANCE, 0},
+{55, 3211998003u, 3196059648u, 1028443344u, 0, REMAINDERF_TOLERANCE, 0},
+{56, 3211998003u, 3192704205u, 1028443348u, 0, REMAINDERF_TOLERANCE, 0},
+{57, 3211998003u, 3189348762u, 3175926976u, 0, REMAINDERF_TOLERANCE, 0},
+{58, 3211998003u, 3184315597u, 3175926982u, 0, REMAINDERF_TOLERANCE, 0},
+{59, 3211998003u, 3175926989u, 853540864u, 0, REMAINDERF_TOLERANCE, 0},
+{60, 3211998003u, 632815616u, 2771386368u, 0, REMAINDERF_TOLERANCE, 0},
+{61, 3211998003u, 1028443341u, 853540864u, 0, REMAINDERF_TOLERANCE, 0},
+{62, 3211998003u, 1036831949u, 3175926982u, 0, REMAINDERF_TOLERANCE, 0},
+{63, 3211998003u, 1041865114u, 3175926976u, 0, REMAINDERF_TOLERANCE, 0},
+{64, 3211998003u, 1045220557u, 1028443348u, 0, REMAINDERF_TOLERANCE, 0},
+{65, 3211998003u, 1048576000u, 1028443344u, 0, REMAINDERF_TOLERANCE, 0},
+{66, 3211998003u, 1050253722u, 3175926976u, 0, REMAINDERF_TOLERANCE, 0},
+{67, 3211998003u, 1051931443u, 1036831948u, 0, REMAINDERF_TOLERANCE, 0},
+{68, 3211998003u, 1053609165u, 3189348760u, 0, REMAINDERF_TOLERANCE, 0},
+{69, 3211998003u, 1055286886u, 3175926992u, 0, REMAINDERF_TOLERANCE, 0},
+{70, 3211998003u, 1056964608u, 1028443344u, 0, REMAINDERF_TOLERANCE, 0},
+{71, 3211998003u, 1057803469u, 1041865116u, 0, REMAINDERF_TOLERANCE, 0},
+{72, 3211998003u, 1058642330u, 1048576002u, 0, REMAINDERF_TOLERANCE, 0},
+{73, 3211998003u, 1059481190u, 3197737370u, 0, REMAINDERF_TOLERANCE, 0},
+{74, 3211998003u, 1060320051u, 3196059648u, 0, REMAINDERF_TOLERANCE, 0},
+{75, 3211998003u, 1061158912u, 3192704204u, 0, REMAINDERF_TOLERANCE, 0},
+{76, 3211998003u, 1061997773u, 3189348760u, 0, REMAINDERF_TOLERANCE, 0},
+{77, 3211998003u, 1062836634u, 3184315592u, 0, REMAINDERF_TOLERANCE, 0},
+{78, 3211998003u, 1063675494u, 3175926992u, 0, REMAINDERF_TOLERANCE, 0},
+{79, 3211998003u, 1064514355u, 2147483648u, 0, REMAINDERF_TOLERANCE, 0},
+{80, 3211159142u, 3212836864u, 1036831952u, 0, REMAINDERF_TOLERANCE, 0},
+{81, 3211159142u, 3211998003u, 1028443344u, 0, REMAINDERF_TOLERANCE, 0},
+{82, 3211159142u, 3211159142u, 2147483648u, 0, REMAINDERF_TOLERANCE, 0},
+{83, 3211159142u, 3210320282u, 3175926976u, 0, REMAINDERF_TOLERANCE, 0},
+{84, 3211159142u, 3209481421u, 3184315592u, 0, REMAINDERF_TOLERANCE, 0},
+{85, 3211159142u, 3208642560u, 3189348760u, 0, REMAINDERF_TOLERANCE, 0},
+{86, 3211159142u, 3207803699u, 3192704204u, 0, REMAINDERF_TOLERANCE, 0},
+{87, 3211159142u, 3206964838u, 3196059648u, 0, REMAINDERF_TOLERANCE, 0},
+{88, 3211159142u, 3206125978u, 3197737368u, 0, REMAINDERF_TOLERANCE, 0},
+{89, 3211159142u, 3205287117u, 1045220560u, 0, REMAINDERF_TOLERANCE, 0},
+{90, 3211159142u, 3204448256u, 1036831952u, 0, REMAINDERF_TOLERANCE, 0},
+{91, 3211159142u, 3202770534u, 2147483648u, 0, REMAINDERF_TOLERANCE, 0},
+{92, 3211159142u, 3201092813u, 3184315592u, 0, REMAINDERF_TOLERANCE, 0},
+{93, 3211159142u, 3199415091u, 1041865114u, 0, REMAINDERF_TOLERANCE, 0},
+{94, 3211159142u, 3197737370u, 864026624u, 0, REMAINDERF_TOLERANCE, 0},
+{95, 3211159142u, 3196059648u, 1036831952u, 0, REMAINDERF_TOLERANCE, 0},
+{96, 3211159142u, 3192704205u, 3184315592u, 0, REMAINDERF_TOLERANCE, 0},
+{97, 3211159142u, 3189348762u, 864026624u, 0, REMAINDERF_TOLERANCE, 0},
+{98, 3211159142u, 3184315597u, 857735168u, 0, REMAINDERF_TOLERANCE, 0},
+{99, 3211159142u, 3175926989u, 857735168u, 0, REMAINDERF_TOLERANCE, 0},
+{100, 3211159142u, 632815616u, 608174080u, 0, REMAINDERF_TOLERANCE, 0},
+{101, 3211159142u, 1028443341u, 857735168u, 0, REMAINDERF_TOLERANCE, 0},
+{102, 3211159142u, 1036831949u, 857735168u, 0, REMAINDERF_TOLERANCE, 0},
+{103, 3211159142u, 1041865114u, 864026624u, 0, REMAINDERF_TOLERANCE, 0},
+{104, 3211159142u, 1045220557u, 3184315592u, 0, REMAINDERF_TOLERANCE, 0},
+{105, 3211159142u, 1048576000u, 1036831952u, 0, REMAINDERF_TOLERANCE, 0},
+{106, 3211159142u, 1050253722u, 864026624u, 0, REMAINDERF_TOLERANCE, 0},
+{107, 3211159142u, 1051931443u, 1041865114u, 0, REMAINDERF_TOLERANCE, 0},
+{108, 3211159142u, 1053609165u, 3184315592u, 0, REMAINDERF_TOLERANCE, 0},
+{109, 3211159142u, 1055286886u, 2147483648u, 0, REMAINDERF_TOLERANCE, 0},
+{110, 3211159142u, 1056964608u, 1036831952u, 0, REMAINDERF_TOLERANCE, 0},
+{111, 3211159142u, 1057803469u, 1045220560u, 0, REMAINDERF_TOLERANCE, 0},
+{112, 3211159142u, 1058642330u, 3197737368u, 0, REMAINDERF_TOLERANCE, 0},
+{113, 3211159142u, 1059481190u, 3196059648u, 0, REMAINDERF_TOLERANCE, 0},
+{114, 3211159142u, 1060320051u, 3192704204u, 0, REMAINDERF_TOLERANCE, 0},
+{115, 3211159142u, 1061158912u, 3189348760u, 0, REMAINDERF_TOLERANCE, 0},
+{116, 3211159142u, 1061997773u, 3184315592u, 0, REMAINDERF_TOLERANCE, 0},
+{117, 3211159142u, 1062836634u, 3175926976u, 0, REMAINDERF_TOLERANCE, 0},
+{118, 3211159142u, 1063675494u, 2147483648u, 0, REMAINDERF_TOLERANCE, 0},
+{119, 3211159142u, 1064514355u, 1028443344u, 0, REMAINDERF_TOLERANCE, 0},
+{120, 3210320282u, 3212836864u, 1041865112u, 0, REMAINDERF_TOLERANCE, 0},
+{121, 3210320282u, 3211998003u, 1036831944u, 0, REMAINDERF_TOLERANCE, 0},
+{122, 3210320282u, 3211159142u, 1028443328u, 0, REMAINDERF_TOLERANCE, 0},
+{123, 3210320282u, 3210320282u, 2147483648u, 0, REMAINDERF_TOLERANCE, 0},
+{124, 3210320282u, 3209481421u, 3175926992u, 0, REMAINDERF_TOLERANCE, 0},
+{125, 3210320282u, 3208642560u, 3184315600u, 0, REMAINDERF_TOLERANCE, 0},
+{126, 3210320282u, 3207803699u, 3189348764u, 0, REMAINDERF_TOLERANCE, 0},
+{127, 3210320282u, 3206964838u, 3192704208u, 0, REMAINDERF_TOLERANCE, 0},
+{128, 3210320282u, 3206125978u, 3196059648u, 0, REMAINDERF_TOLERANCE, 0},
+{129, 3210320282u, 3205287117u, 1048576000u, 0, REMAINDERF_TOLERANCE, 0},
+{130, 3210320282u, 3204448256u, 1041865112u, 0, REMAINDERF_TOLERANCE, 0},
+{131, 3210320282u, 3202770534u, 1028443328u, 0, REMAINDERF_TOLERANCE, 0},
+{132, 3210320282u, 3201092813u, 3175926992u, 0, REMAINDERF_TOLERANCE, 0},
+{133, 3210320282u, 3199415091u, 3189348764u, 0, REMAINDERF_TOLERANCE, 0},
+{134, 3210320282u, 3197737370u, 1028443344u, 0, REMAINDERF_TOLERANCE, 0},
+{135, 3210320282u, 3196059648u, 3184315600u, 0, REMAINDERF_TOLERANCE, 0},
+{136, 3210320282u, 3192704205u, 3175926992u, 0, REMAINDERF_TOLERANCE, 0},
+{137, 3210320282u, 3189348762u, 1028443344u, 0, REMAINDERF_TOLERANCE, 0},
+{138, 3210320282u, 3184315597u, 1028443338u, 0, REMAINDERF_TOLERANCE, 0},
+{139, 3210320282u, 3175926989u, 2990538752u, 0, REMAINDERF_TOLERANCE, 0},
+{140, 3210320282u, 632815616u, 614465536u, 0, REMAINDERF_TOLERANCE, 0},
+{141, 3210320282u, 1028443341u, 2990538752u, 0, REMAINDERF_TOLERANCE, 0},
+{142, 3210320282u, 1036831949u, 1028443338u, 0, REMAINDERF_TOLERANCE, 0},
+{143, 3210320282u, 1041865114u, 1028443344u, 0, REMAINDERF_TOLERANCE, 0},
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+{2349, 1127109339u, 3368125489u, 1127109339u, 0, REMAINDERF_TOLERANCE, 0},
+{2350, 1200599955u, 2981200675u, 817704344u, 0, REMAINDERF_TOLERANCE, 0},
+{2351, 962230977u, 2988248037u, 805535536u, 0, REMAINDERF_TOLERANCE, 0},
+{2352, 3192887808u, 3191848339u, 3162359504u, 0, REMAINDERF_TOLERANCE, 0},
+{2353, 3237183876u, 3179379969u, 3166118432u, 0, REMAINDERF_TOLERANCE, 0},
+{2354, 939285924u, 3056079386u, 855964160u, 0, REMAINDERF_TOLERANCE, 0},
+{2355, 944050180u, 3452557879u, 944050180u, 0, REMAINDERF_TOLERANCE, 0},
+{2356, 3058135703u, 3090284601u, 3058135703u, 0, REMAINDERF_TOLERANCE, 0},
+{2357, 3480592662u, 3261728191u, 3221094720u, 0, REMAINDERF_TOLERANCE, 0},
+{2358, 3061939312u, 3274418540u, 3061939312u, 0, REMAINDERF_TOLERANCE, 0},
+{2359, 1003299981u, 853295521u, 831378192u, 0, REMAINDERF_TOLERANCE, 0},
+{2360, 1155775526u, 1255814444u, 1155775526u, 0, REMAINDERF_TOLERANCE, 0},
+{2361, 1234491880u, 3408568717u, 1234491880u, 0, REMAINDERF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_SCABNF_H multiple inclusion protection
+
+// EOF remainderf.h
diff --git a/packages/language/c/libm/current/tests/vectors/rintf.c b/packages/language/c/libm/current/tests/vectors/rintf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/rintf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      rintf.c
+//
+//      Test of rintf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/rintf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(rintf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &rintf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &rintf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("rintf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("rintf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library rintf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "rintf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF rintf.c
diff --git a/packages/language/c/libm/current/tests/vectors/rintf.h b/packages/language/c/libm/current/tests/vectors/rintf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/rintf.h
@@ -0,0 +1,1004 @@
+#ifndef CYGONCE_LIBM_RINTF_H
+#define CYGONCE_LIBM_RINTF_H
+//===========================================================================
+//
+//      rintf.h
+//
+//      Test vectors for testing of rintf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/rintf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define RINTF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t rintf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{1, 3214430700u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{2, 3214346813u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{3, 3214262927u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{4, 3214179041u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{5, 3214095155u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{6, 3214011269u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{7, 3213927383u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{8, 3213843497u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{9, 3213759611u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{10, 3213675725u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{11, 3213591839u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{12, 3213507953u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{13, 3213424067u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{14, 3213340180u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{15, 3213256294u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{16, 3213172408u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{17, 3213088522u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{18, 3213004636u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{19, 3212920750u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{20, 3212836864u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{21, 3212669092u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{22, 3212501320u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{23, 3212333548u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{24, 3212165775u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{25, 3211998003u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{26, 3211830231u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{27, 3211662459u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{28, 3211494687u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{29, 3211326915u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{30, 3211159142u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{31, 3210991370u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{32, 3210823598u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{33, 3210655826u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{34, 3210488054u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{35, 3210320282u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{36, 3210152509u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{37, 3209984737u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{38, 3209816965u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{39, 3209649193u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{40, 3209481421u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{41, 3209313649u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{42, 3209145876u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{43, 3208978104u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{44, 3208810332u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{45, 3208642560u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{46, 3208474788u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{47, 3208307016u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{48, 3208139244u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{49, 3207971471u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{50, 3207803699u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{51, 3207635927u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{52, 3207468155u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{53, 3207300383u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{54, 3207132611u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{55, 3206964838u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{56, 3206797066u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{57, 3206629294u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{58, 3206461522u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{59, 3206293750u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{60, 3206125978u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{61, 3205958205u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{62, 3205790433u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{63, 3205622661u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{64, 3205454889u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{65, 3205287117u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{66, 3205119345u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{67, 3204951572u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{68, 3204783800u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{69, 3204616028u, 0u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{70, 1008981770u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{71, 1017370378u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{72, 1022739087u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{73, 1025758986u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{74, 1028443341u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{75, 1031127695u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{76, 1032805417u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{77, 1034147594u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{78, 1035489772u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{79, 1036831949u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{80, 1038174126u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{81, 1039516303u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{82, 1040522936u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{83, 1041194025u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{84, 1041865114u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{85, 1042536202u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{86, 1043207291u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{87, 1043878380u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{88, 1044549468u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{89, 1045220557u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{90, 1045891645u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{91, 1046562734u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{92, 1047233823u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{93, 1047904911u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{94, 1048576000u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{95, 1048911544u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{96, 1049247089u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{97, 1049582633u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{98, 1049918177u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{99, 1050253722u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{100, 1050589266u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{101, 1050924810u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{102, 1051260355u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{103, 1051595899u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{104, 1051931443u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{105, 1052266988u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{106, 1052602532u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{107, 1052938076u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{108, 1053273620u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{109, 1053609165u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{110, 1053944709u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{111, 1054280253u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{112, 1054615798u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{113, 1054951342u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{114, 1055286886u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{115, 1055622431u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{116, 1055957975u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{117, 1056293519u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{118, 1056629064u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{119, 1056964608u, 0u, 0u, 0, RINTF_TOLERANCE, 0},
+{120, 1057132380u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{121, 1057300152u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{122, 1057467924u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{123, 1057635697u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{124, 1057803469u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{125, 1057971241u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{126, 1058139013u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{127, 1058306785u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{128, 1058474557u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{129, 1058642330u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{130, 1058810102u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{131, 1058977874u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{132, 1059145646u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{133, 1059313418u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{134, 1059481190u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{135, 1059648963u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{136, 1059816735u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{137, 1059984507u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{138, 1060152279u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{139, 1060320051u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{140, 1060487823u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{141, 1060655596u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{142, 1060823368u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{143, 1060991140u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{144, 1061158912u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{145, 1061326684u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{146, 1061494456u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{147, 1061662228u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{148, 1061830001u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{149, 1061997773u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{150, 1062165545u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{151, 1062333317u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{152, 1062501089u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{153, 1062668861u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{154, 1062836634u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{155, 1063004406u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{156, 1063172178u, 0u, 1065353216u, 0, RINTF_TOLERANCE, 0},
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+{821, 3228793330u, 855146890u, 3229614080u, 0, RINTF_TOLERANCE, 0},
+{822, 3422194733u, 893873945u, 3422194733u, 0, RINTF_TOLERANCE, 0},
+{823, 1261940623u, 3402349985u, 1261940623u, 0, RINTF_TOLERANCE, 0},
+{824, 3400603081u, 3234396843u, 3400603080u, 0, RINTF_TOLERANCE, 0},
+{825, 1219411812u, 2961857939u, 1219411808u, 0, RINTF_TOLERANCE, 0},
+{826, 886201503u, 3272760705u, 0u, 0, RINTF_TOLERANCE, 0},
+{827, 3297366026u, 1089966380u, 3297370112u, 0, RINTF_TOLERANCE, 0},
+{828, 1218488455u, 3309646450u, 1218488448u, 0, RINTF_TOLERANCE, 0},
+{829, 1283938137u, 1196383822u, 1283938137u, 0, RINTF_TOLERANCE, 0},
+{830, 1317098613u, 949986176u, 1317098613u, 0, RINTF_TOLERANCE, 0},
+{831, 3431703657u, 3014443710u, 3431703657u, 0, RINTF_TOLERANCE, 0},
+{832, 3239728775u, 927815421u, 3240099840u, 0, RINTF_TOLERANCE, 0},
+{833, 3207141672u, 933456504u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{834, 3313160088u, 2964063309u, 3313160192u, 0, RINTF_TOLERANCE, 0},
+{835, 3207056527u, 3384206601u, 3212836864u, 0, RINTF_TOLERANCE, 0},
+{836, 1284174954u, 3436881197u, 1284174954u, 0, RINTF_TOLERANCE, 0},
+{837, 1063693032u, 976661408u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{838, 1102631663u, 3396951425u, 1102577664u, 0, RINTF_TOLERANCE, 0},
+{839, 968803479u, 992989712u, 0u, 0, RINTF_TOLERANCE, 0},
+{840, 3273080388u, 3109405906u, 3273064448u, 0, RINTF_TOLERANCE, 0},
+{841, 1172529774u, 3294550127u, 1172529152u, 0, RINTF_TOLERANCE, 0},
+{842, 1306695905u, 1292690378u, 1306695905u, 0, RINTF_TOLERANCE, 0},
+{843, 1003649752u, 1218792138u, 0u, 0, RINTF_TOLERANCE, 0},
+{844, 1078478376u, 1326246424u, 1077936128u, 0, RINTF_TOLERANCE, 0},
+{845, 1165177679u, 3276237026u, 1165176832u, 0, RINTF_TOLERANCE, 0},
+{846, 3403009513u, 3381966453u, 3403009512u, 0, RINTF_TOLERANCE, 0},
+{847, 952348506u, 3377573987u, 0u, 0, RINTF_TOLERANCE, 0},
+{848, 1222777442u, 1125769920u, 1222777440u, 0, RINTF_TOLERANCE, 0},
+{849, 1325324763u, 978336043u, 1325324763u, 0, RINTF_TOLERANCE, 0},
+{850, 3363524213u, 3202991311u, 3363524224u, 0, RINTF_TOLERANCE, 0},
+{851, 1158950321u, 1073578913u, 1158950912u, 0, RINTF_TOLERANCE, 0},
+{852, 903129873u, 3416864271u, 0u, 0, RINTF_TOLERANCE, 0},
+{853, 1208345407u, 1254181270u, 1208345408u, 0, RINTF_TOLERANCE, 0},
+{854, 1258634105u, 1247426200u, 1258634105u, 0, RINTF_TOLERANCE, 0},
+{855, 1248478509u, 1287895126u, 1248478508u, 0, RINTF_TOLERANCE, 0},
+{856, 1153863988u, 3430539165u, 1153867776u, 0, RINTF_TOLERANCE, 0},
+{857, 1235620969u, 866627358u, 1235620968u, 0, RINTF_TOLERANCE, 0},
+{858, 1097120930u, 3221726305u, 1096810496u, 0, RINTF_TOLERANCE, 0},
+{859, 3469778622u, 1200179013u, 3469778622u, 0, RINTF_TOLERANCE, 0},
+{860, 1147712200u, 931865525u, 1147715584u, 0, RINTF_TOLERANCE, 0},
+{861, 1124721745u, 3058969650u, 1124728832u, 0, RINTF_TOLERANCE, 0},
+{862, 3261744304u, 1043806501u, 3261857792u, 0, RINTF_TOLERANCE, 0},
+{863, 1064922416u, 1320485628u, 1065353216u, 0, RINTF_TOLERANCE, 0},
+{864, 3303160152u, 3075455322u, 3303161856u, 0, RINTF_TOLERANCE, 0},
+{865, 1315090496u, 3269683237u, 1315090496u, 0, RINTF_TOLERANCE, 0},
+{866, 3230403187u, 1322841992u, 3229614080u, 0, RINTF_TOLERANCE, 0},
+{867, 1335399673u, 974138676u, 1335399673u, 0, RINTF_TOLERANCE, 0},
+{868, 1072458508u, 3372833993u, 1073741824u, 0, RINTF_TOLERANCE, 0},
+{869, 3303015249u, 3015039539u, 3303014400u, 0, RINTF_TOLERANCE, 0},
+{870, 3252139741u, 1059615003u, 3252158464u, 0, RINTF_TOLERANCE, 0},
+{871, 3468519966u, 3113982619u, 3468519966u, 0, RINTF_TOLERANCE, 0},
+{872, 1006231203u, 897530770u, 0u, 0, RINTF_TOLERANCE, 0},
+{873, 951554138u, 1001144381u, 0u, 0, RINTF_TOLERANCE, 0},
+{874, 942046828u, 986341002u, 0u, 0, RINTF_TOLERANCE, 0},
+{875, 3319723279u, 3414482416u, 3319724032u, 0, RINTF_TOLERANCE, 0},
+{876, 3255104167u, 928827688u, 3255042048u, 0, RINTF_TOLERANCE, 0},
+{877, 1155477903u, 3104812800u, 1155481600u, 0, RINTF_TOLERANCE, 0},
+{878, 3273889176u, 980486479u, 3273916416u, 0, RINTF_TOLERANCE, 0},
+{879, 3237813668u, 3441016803u, 3238002688u, 0, RINTF_TOLERANCE, 0},
+{880, 1228207362u, 2985476579u, 1228207360u, 0, RINTF_TOLERANCE, 0},
+{881, 975349337u, 1311932596u, 0u, 0, RINTF_TOLERANCE, 0},
+{882, 1290175785u, 3008182462u, 1290175785u, 0, RINTF_TOLERANCE, 0},
+{883, 981908840u, 3314038398u, 0u, 0, RINTF_TOLERANCE, 0},
+{884, 941187647u, 1107765599u, 0u, 0, RINTF_TOLERANCE, 0},
+{885, 1214223128u, 3225536822u, 1214223104u, 0, RINTF_TOLERANCE, 0},
+{886, 3422922584u, 1086391131u, 3422922584u, 0, RINTF_TOLERANCE, 0},
+{887, 1315857601u, 3487600045u, 1315857601u, 0, RINTF_TOLERANCE, 0},
+{888, 3453226030u, 3233768835u, 3453226030u, 0, RINTF_TOLERANCE, 0},
+{889, 1078359574u, 3199175230u, 1077936128u, 0, RINTF_TOLERANCE, 0},
+{890, 1029557624u, 3302959071u, 0u, 0, RINTF_TOLERANCE, 0},
+{891, 1207675424u, 3042692550u, 1207675392u, 0, RINTF_TOLERANCE, 0},
+{892, 1028355074u, 3442294040u, 0u, 0, RINTF_TOLERANCE, 0},
+{893, 1248421894u, 3367769132u, 1248421896u, 0, RINTF_TOLERANCE, 0},
+{894, 3353251994u, 1095517730u, 3353251968u, 0, RINTF_TOLERANCE, 0},
+{895, 876926659u, 3288089977u, 0u, 0, RINTF_TOLERANCE, 0},
+{896, 1076752219u, 876236939u, 1077936128u, 0, RINTF_TOLERANCE, 0},
+{897, 3388531942u, 2988520062u, 3388531944u, 0, RINTF_TOLERANCE, 0},
+{898, 1273395082u, 3031189261u, 1273395082u, 0, RINTF_TOLERANCE, 0},
+{899, 3385588183u, 3258252464u, 3385588184u, 0, RINTF_TOLERANCE, 0},
+{900, 3441804648u, 3274638356u, 3441804648u, 0, RINTF_TOLERANCE, 0},
+{901, 3392827417u, 1277961150u, 3392827416u, 0, RINTF_TOLERANCE, 0},
+{902, 1161241793u, 1328003707u, 1161240576u, 0, RINTF_TOLERANCE, 0},
+{903, 1171318485u, 3374409104u, 1171318784u, 0, RINTF_TOLERANCE, 0},
+{904, 1001216371u, 3052357038u, 0u, 0, RINTF_TOLERANCE, 0},
+{905, 912515889u, 1074635609u, 0u, 0, RINTF_TOLERANCE, 0},
+{906, 3391452505u, 897989232u, 3391452504u, 0, RINTF_TOLERANCE, 0},
+{907, 3249603369u, 3147662248u, 3249537024u, 0, RINTF_TOLERANCE, 0},
+{908, 1220264047u, 2960450369u, 1220264032u, 0, RINTF_TOLERANCE, 0},
+{909, 3282212423u, 3174079140u, 3282206720u, 0, RINTF_TOLERANCE, 0},
+{910, 3352293320u, 3247843425u, 3352293376u, 0, RINTF_TOLERANCE, 0},
+{911, 3296358441u, 875645354u, 3296362496u, 0, RINTF_TOLERANCE, 0},
+{912, 1197828352u, 3245614728u, 1197828352u, 0, RINTF_TOLERANCE, 0},
+{913, 3340510371u, 914930263u, 3340510464u, 0, RINTF_TOLERANCE, 0},
+{914, 1127109339u, 3368125489u, 1127088128u, 0, RINTF_TOLERANCE, 0},
+{915, 909467381u, 1232375752u, 0u, 0, RINTF_TOLERANCE, 0},
+{916, 1200599955u, 2981200675u, 1200599936u, 0, RINTF_TOLERANCE, 0},
+{917, 962230977u, 2988248037u, 0u, 0, RINTF_TOLERANCE, 0},
+{918, 3237183876u, 3179379969u, 3238002688u, 0, RINTF_TOLERANCE, 0},
+{919, 939285924u, 3056079386u, 0u, 0, RINTF_TOLERANCE, 0},
+{920, 944050180u, 3452557879u, 0u, 0, RINTF_TOLERANCE, 0},
+{921, 3480592662u, 3261728191u, 3480592662u, 0, RINTF_TOLERANCE, 0},
+{922, 1003299981u, 853295521u, 0u, 0, RINTF_TOLERANCE, 0},
+{923, 1155775526u, 1255814444u, 1155776512u, 0, RINTF_TOLERANCE, 0},
+{924, 1234491880u, 3408568717u, 1234491880u, 0, RINTF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_RINTF_H multiple inclusion protection
+
+// EOF rintf.h
diff --git a/packages/language/c/libm/current/tests/vectors/scalbf.c b/packages/language/c/libm/current/tests/vectors/scalbf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/scalbf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      scalbf.c
+//
+//      Test of scalbf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/scalbf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(scalbf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &scalbf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_FLOAT, CYG_LIBM_TEST_VEC_FLOAT,
+                     &scalbf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("scalbf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("scalbf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library scalbf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "scalbf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF scalbf.c
diff --git a/packages/language/c/libm/current/tests/vectors/scalbf.h b/packages/language/c/libm/current/tests/vectors/scalbf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/scalbf.h
@@ -0,0 +1,221 @@
+#ifndef CYGONCE_LIBM_SCABNF_H
+#define CYGONCE_LIBM_SCABNF_H
+//===========================================================================
+//
+//      scalbf.h
+//
+//      Test vectors for testing of scalbf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/scalbf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define SCALBF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t scalbf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3212836864u, 3212836864u, 3204448256u, 0, SCALBF_TOLERANCE, 0},
+{1, 3211998003u, 3212836864u, 3203609395u, 0, SCALBF_TOLERANCE, 0},
+{2, 3211159142u, 3212836864u, 3202770534u, 0, SCALBF_TOLERANCE, 0},
+{3, 3210320282u, 3212836864u, 3201931674u, 0, SCALBF_TOLERANCE, 0},
+{4, 3209481421u, 3212836864u, 3201092813u, 0, SCALBF_TOLERANCE, 0},
+{5, 3208642560u, 3212836864u, 3200253952u, 0, SCALBF_TOLERANCE, 0},
+{6, 3207803699u, 3212836864u, 3199415091u, 0, SCALBF_TOLERANCE, 0},
+{7, 3206964838u, 3212836864u, 3198576230u, 0, SCALBF_TOLERANCE, 0},
+{8, 3206125978u, 3212836864u, 3197737370u, 0, SCALBF_TOLERANCE, 0},
+{9, 3205287117u, 3212836864u, 3196898509u, 0, SCALBF_TOLERANCE, 0},
+{10, 3204448256u, 3212836864u, 3196059648u, 0, SCALBF_TOLERANCE, 0},
+{11, 3202770534u, 3212836864u, 3194381926u, 0, SCALBF_TOLERANCE, 0},
+{12, 3201092813u, 3212836864u, 3192704205u, 0, SCALBF_TOLERANCE, 0},
+{13, 3199415091u, 3212836864u, 3191026483u, 0, SCALBF_TOLERANCE, 0},
+{14, 3197737370u, 3212836864u, 3189348762u, 0, SCALBF_TOLERANCE, 0},
+{15, 3196059648u, 3212836864u, 3187671040u, 0, SCALBF_TOLERANCE, 0},
+{16, 3192704205u, 3212836864u, 3184315597u, 0, SCALBF_TOLERANCE, 0},
+{17, 3189348762u, 3212836864u, 3180960154u, 0, SCALBF_TOLERANCE, 0},
+{18, 3184315597u, 3212836864u, 3175926989u, 0, SCALBF_TOLERANCE, 0},
+{19, 3175926989u, 3212836864u, 3167538381u, 0, SCALBF_TOLERANCE, 0},
+{20, 1028443341u, 3212836864u, 1020054733u, 0, SCALBF_TOLERANCE, 0},
+{21, 1036831949u, 3212836864u, 1028443341u, 0, SCALBF_TOLERANCE, 0},
+{22, 1041865114u, 3212836864u, 1033476506u, 0, SCALBF_TOLERANCE, 0},
+{23, 1045220557u, 3212836864u, 1036831949u, 0, SCALBF_TOLERANCE, 0},
+{24, 1048576000u, 3212836864u, 1040187392u, 0, SCALBF_TOLERANCE, 0},
+{25, 1050253722u, 3212836864u, 1041865114u, 0, SCALBF_TOLERANCE, 0},
+{26, 1051931443u, 3212836864u, 1043542835u, 0, SCALBF_TOLERANCE, 0},
+{27, 1053609165u, 3212836864u, 1045220557u, 0, SCALBF_TOLERANCE, 0},
+{28, 1055286886u, 3212836864u, 1046898278u, 0, SCALBF_TOLERANCE, 0},
+{29, 1056964608u, 3212836864u, 1048576000u, 0, SCALBF_TOLERANCE, 0},
+{30, 1057803469u, 3212836864u, 1049414861u, 0, SCALBF_TOLERANCE, 0},
+{31, 1058642330u, 3212836864u, 1050253722u, 0, SCALBF_TOLERANCE, 0},
+{32, 1059481190u, 3212836864u, 1051092582u, 0, SCALBF_TOLERANCE, 0},
+{33, 1060320051u, 3212836864u, 1051931443u, 0, SCALBF_TOLERANCE, 0},
+{34, 1061158912u, 3212836864u, 1052770304u, 0, SCALBF_TOLERANCE, 0},
+{35, 1061997773u, 3212836864u, 1053609165u, 0, SCALBF_TOLERANCE, 0},
+{36, 1062836634u, 3212836864u, 1054448026u, 0, SCALBF_TOLERANCE, 0},
+{37, 1063675494u, 3212836864u, 1055286886u, 0, SCALBF_TOLERANCE, 0},
+{38, 1064514355u, 3212836864u, 1056125747u, 0, SCALBF_TOLERANCE, 0},
+{39, 1341514497u, 3466051188u, 0u, 0, SCALBF_TOLERANCE, 0},
+{40, 1001673627u, 3462631271u, 0u, 0, SCALBF_TOLERANCE, 0},
+{41, 3048866608u, 3449209899u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{42, 1333134799u, 1338107877u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{43, 1187847971u, 1317663644u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{44, 3444653659u, 1279248024u, 4286578688u, 0, SCALBF_TOLERANCE, 0},
+{45, 974547519u, 3475164509u, 0u, 0, SCALBF_TOLERANCE, 0},
+{46, 3182301130u, 3460764044u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{47, 3417964312u, 1321337529u, 4286578688u, 0, SCALBF_TOLERANCE, 0},
+{48, 1148867223u, 1256486202u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{49, 3319315516u, 3422089012u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{50, 1134593658u, 3456812581u, 0u, 0, SCALBF_TOLERANCE, 0},
+{51, 3316278408u, 3455589207u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{52, 3131791114u, 3408392958u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{53, 881280146u, 3421884736u, 0u, 0, SCALBF_TOLERANCE, 0},
+{54, 1268194719u, 1332489410u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{55, 1133420220u, 1245770860u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{56, 3295996963u, 3453334307u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{57, 3424831780u, 1304806106u, 4286578688u, 0, SCALBF_TOLERANCE, 0},
+{58, 1257596246u, 3420832544u, 0u, 0, SCALBF_TOLERANCE, 0},
+{59, 3235326590u, 1271705594u, 4286578688u, 0, SCALBF_TOLERANCE, 0},
+{60, 1106502045u, 1290849316u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{61, 3427296372u, 3455289118u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{62, 1198917460u, 1327195159u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{63, 3114686212u, 3476082461u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{64, 1165195428u, 3390323168u, 0u, 0, SCALBF_TOLERANCE, 0},
+{65, 3275973009u, 3450721670u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{66, 3391162308u, 1291220039u, 4286578688u, 0, SCALBF_TOLERANCE, 0},
+{67, 1089986803u, 3462160118u, 0u, 0, SCALBF_TOLERANCE, 0},
+{68, 3262169538u, 1268270462u, 4286578688u, 0, SCALBF_TOLERANCE, 0},
+{69, 3404372005u, 3450484255u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{70, 999985470u, 3409354318u, 0u, 0, SCALBF_TOLERANCE, 0},
+{71, 3132541814u, 3444521949u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{72, 1164046161u, 3440635788u, 0u, 0, SCALBF_TOLERANCE, 0},
+{73, 3469748379u, 3412765608u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{74, 948775569u, 3485444126u, 0u, 0, SCALBF_TOLERANCE, 0},
+{75, 3157534378u, 3451674717u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{76, 3162548604u, 3461790298u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{77, 3424264117u, 3434026174u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{78, 1311706596u, 1254918706u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{79, 1337315179u, 3461361185u, 0u, 0, SCALBF_TOLERANCE, 0},
+{80, 3337499209u, 1226297264u, 4286578688u, 0, SCALBF_TOLERANCE, 0},
+{81, 3220979495u, 3429223871u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{82, 1017239798u, 3438501281u, 0u, 0, SCALBF_TOLERANCE, 0},
+{83, 3092982276u, 3445282331u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{84, 1168098747u, 1316854744u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{85, 3301009024u, 3406174560u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{86, 1032920919u, 3449126417u, 0u, 0, SCALBF_TOLERANCE, 0},
+{87, 3388153589u, 3426245389u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{88, 1258369714u, 3462258576u, 0u, 0, SCALBF_TOLERANCE, 0},
+{89, 3462285635u, 3444030332u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{90, 3131219358u, 3471261157u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{91, 3418753236u, 3481843070u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{92, 1277417964u, 3487506626u, 0u, 0, SCALBF_TOLERANCE, 0},
+{93, 3320923228u, 3464544249u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{94, 1337400405u, 3488844154u, 0u, 0, SCALBF_TOLERANCE, 0},
+{95, 1215968622u, 3469884568u, 0u, 0, SCALBF_TOLERANCE, 0},
+{96, 3091024506u, 3456196859u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{97, 1157186482u, 1288722647u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{98, 3477008113u, 1331845018u, 4286578688u, 0, SCALBF_TOLERANCE, 0},
+{99, 3292127294u, 3409957764u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{100, 1160162706u, 1264067367u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{101, 1096155623u, 1256423752u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{102, 3475052219u, 1284049853u, 4286578688u, 0, SCALBF_TOLERANCE, 0},
+{103, 3154720153u, 3443720494u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{104, 3108347547u, 3434003435u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{105, 3272661536u, 3461799138u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{106, 3086068902u, 3484245751u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{107, 1086717248u, 3423795374u, 0u, 0, SCALBF_TOLERANCE, 0},
+{108, 1200927971u, 1317167489u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{109, 3326858092u, 3452602832u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{110, 3316611992u, 3394732912u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{111, 3066654389u, 3443934204u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{112, 3295326432u, 1313396175u, 4286578688u, 0, SCALBF_TOLERANCE, 0},
+{113, 3455131757u, 1260217257u, 4286578688u, 0, SCALBF_TOLERANCE, 0},
+{114, 3157626955u, 3483653298u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{115, 1105291533u, 3482971524u, 0u, 0, SCALBF_TOLERANCE, 0},
+{116, 3370691006u, 1295870514u, 4286578688u, 0, SCALBF_TOLERANCE, 0},
+{117, 3335212901u, 3486414589u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{118, 3283471961u, 1260093226u, 4286578688u, 0, SCALBF_TOLERANCE, 0},
+{119, 1288901567u, 1296370667u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{120, 3100289712u, 3456334210u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{121, 3375507013u, 1306310823u, 4286578688u, 0, SCALBF_TOLERANCE, 0},
+{122, 1258114435u, 1291336083u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{123, 3445262427u, 3465211174u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{124, 1102061604u, 3424449935u, 0u, 0, SCALBF_TOLERANCE, 0},
+{125, 1284174954u, 3436881197u, 0u, 0, SCALBF_TOLERANCE, 0},
+{126, 1306695905u, 1292690378u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{127, 903129873u, 3416864271u, 0u, 0, SCALBF_TOLERANCE, 0},
+{128, 1208345407u, 1254181270u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{129, 1258634105u, 1247426200u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{130, 1248478509u, 1287895126u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{131, 1153863988u, 3430539165u, 0u, 0, SCALBF_TOLERANCE, 0},
+{132, 3319723279u, 3414482416u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{133, 3237813668u, 3441016803u, 2147483648u, 0, SCALBF_TOLERANCE, 0},
+{134, 1315857601u, 3487600045u, 0u, 0, SCALBF_TOLERANCE, 0},
+{135, 1028355074u, 3442294040u, 0u, 0, SCALBF_TOLERANCE, 0},
+{136, 3392827417u, 1277961150u, 4286578688u, 0, SCALBF_TOLERANCE, 0},
+{137, 1161241793u, 1328003707u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{138, 1171318485u, 3374409104u, 0u, 0, SCALBF_TOLERANCE, 0},
+{139, 944050180u, 3452557879u, 0u, 0, SCALBF_TOLERANCE, 0},
+{140, 1155775526u, 1255814444u, 2139095040u, 0, SCALBF_TOLERANCE, 0},
+{141, 1234491880u, 3408568717u, 0u, 0, SCALBF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_SCABNF_H multiple inclusion protection
+
+// EOF scalbf.h
diff --git a/packages/language/c/libm/current/tests/vectors/scalbnf.c b/packages/language/c/libm/current/tests/vectors/scalbnf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/scalbnf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      scalbnf.c
+//
+//      Test of scalbnf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/scalbnf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(scalbnf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &scalbnf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_INT, CYG_LIBM_TEST_VEC_FLOAT,
+                     &scalbnf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("scalbnf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("scalbnf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library scalbnf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "scalbnf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF scalbnf.c
diff --git a/packages/language/c/libm/current/tests/vectors/scalbnf.h b/packages/language/c/libm/current/tests/vectors/scalbnf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/scalbnf.h
@@ -0,0 +1,667 @@
+#ifndef CYGONCE_LIBM_SCABNF_H
+#define CYGONCE_LIBM_SCABNF_H
+//===========================================================================
+//
+//      scalbnf.h
+//
+//      Test vectors for testing of scalbnf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/scalbnf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define SCALBNF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t scalbnf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3196650934u, 0u, 3196650934u, 0, SCALBNF_TOLERANCE, 0},
+{1, 1224242132u, 0u, 1224242132u, 0, SCALBNF_TOLERANCE, 0},
+{2, 1198712763u, 0u, 1198712763u, 0, SCALBNF_TOLERANCE, 0},
+{3, 3159309973u, 0u, 3159309973u, 0, SCALBNF_TOLERANCE, 0},
+{4, 954173073u, 0u, 954173073u, 0, SCALBNF_TOLERANCE, 0},
+{5, 3090780435u, 0u, 3090780435u, 0, SCALBNF_TOLERANCE, 0},
+{6, 966554515u, 4294967290u, 916222867u, 0, SCALBNF_TOLERANCE, 0},
+{7, 1166191415u, 0u, 1166191415u, 0, SCALBNF_TOLERANCE, 0},
+{8, 1234419246u, 0u, 1234419246u, 0, SCALBNF_TOLERANCE, 0},
+{9, 1302107128u, 4294492157u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{10, 1052801068u, 0u, 1052801068u, 0, SCALBNF_TOLERANCE, 0},
+{11, 1060849628u, 0u, 1060849628u, 0, SCALBNF_TOLERANCE, 0},
+{12, 3484320003u, 0u, 3484320003u, 0, SCALBNF_TOLERANCE, 0},
+{13, 1167223673u, 0u, 1167223673u, 0, SCALBNF_TOLERANCE, 0},
+{14, 968192794u, 0u, 968192794u, 0, SCALBNF_TOLERANCE, 0},
+{15, 3122346862u, 48u, 3525000046u, 0, SCALBNF_TOLERANCE, 0},
+{16, 906701409u, 0u, 906701409u, 0, SCALBNF_TOLERANCE, 0},
+{17, 3231467496u, 0u, 3231467496u, 0, SCALBNF_TOLERANCE, 0},
+{18, 1341514497u, 3022046720u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{19, 1272351391u, 4294363968u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{20, 940236348u, 4294965375u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{21, 3251541546u, 0u, 3251541546u, 0, SCALBNF_TOLERANCE, 0},
+{22, 3110358400u, 0u, 3110358400u, 0, SCALBNF_TOLERANCE, 0},
+{23, 3371863479u, 0u, 3371863479u, 0, SCALBNF_TOLERANCE, 0},
+{24, 3204069187u, 0u, 3204069187u, 0, SCALBNF_TOLERANCE, 0},
+{25, 1306460502u, 0u, 1306460502u, 0, SCALBNF_TOLERANCE, 0},
+{26, 1197542187u, 0u, 1197542187u, 0, SCALBNF_TOLERANCE, 0},
+{27, 1184239996u, 4294967294u, 1167462780u, 0, SCALBNF_TOLERANCE, 0},
+{28, 1001673627u, 3340510784u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{29, 941796645u, 0u, 941796645u, 0, SCALBNF_TOLERANCE, 0},
+{30, 3287199470u, 0u, 3287199470u, 0, SCALBNF_TOLERANCE, 0},
+{31, 1143233714u, 0u, 1143233714u, 0, SCALBNF_TOLERANCE, 0},
+{32, 3143717025u, 4294967290u, 3093385377u, 0, SCALBNF_TOLERANCE, 0},
+{33, 3240298487u, 0u, 3240298487u, 0, SCALBNF_TOLERANCE, 0},
+{34, 1288902137u, 0u, 1288902137u, 0, SCALBNF_TOLERANCE, 0},
+{35, 3329354473u, 0u, 3329354473u, 0, SCALBNF_TOLERANCE, 0},
+{36, 1309289088u, 0u, 1309289088u, 0, SCALBNF_TOLERANCE, 0},
+{37, 3405585402u, 0u, 3405585402u, 0, SCALBNF_TOLERANCE, 0},
+{38, 3106647724u, 0u, 3106647724u, 0, SCALBNF_TOLERANCE, 0},
+{39, 1106778573u, 4294965325u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{40, 1140567947u, 0u, 1140567947u, 0, SCALBNF_TOLERANCE, 0},
+{41, 1238569473u, 0u, 1238569473u, 0, SCALBNF_TOLERANCE, 0},
+{42, 1175011025u, 0u, 1175011025u, 0, SCALBNF_TOLERANCE, 0},
+{43, 3058097085u, 0u, 3058097085u, 0, SCALBNF_TOLERANCE, 0},
+{44, 3107252546u, 1u, 3115641154u, 0, SCALBNF_TOLERANCE, 0},
+{45, 3096032662u, 0u, 3096032662u, 0, SCALBNF_TOLERANCE, 0},
+{46, 3197942144u, 0u, 3197942144u, 0, SCALBNF_TOLERANCE, 0},
+{47, 3403348556u, 0u, 3403348556u, 0, SCALBNF_TOLERANCE, 0},
+{48, 1136411063u, 82u, 1824276919u, 0, SCALBNF_TOLERANCE, 0},
+{49, 3340615780u, 0u, 3340615780u, 0, SCALBNF_TOLERANCE, 0},
+{50, 998567360u, 0u, 998567360u, 0, SCALBNF_TOLERANCE, 0},
+{51, 989687421u, 4294414202u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{52, 1152956913u, 0u, 1152956913u, 0, SCALBNF_TOLERANCE, 0},
+{53, 892922651u, 4294392467u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{54, 1307091856u, 24u, 1508418448u, 0, SCALBNF_TOLERANCE, 0},
+{55, 1142167709u, 13u, 1251219613u, 0, SCALBNF_TOLERANCE, 0},
+{56, 3426232834u, 0u, 3426232834u, 0, SCALBNF_TOLERANCE, 0},
+{57, 3368566779u, 0u, 3368566779u, 0, SCALBNF_TOLERANCE, 0},
+{58, 1138741813u, 0u, 1138741813u, 0, SCALBNF_TOLERANCE, 0},
+{59, 982950501u, 0u, 982950501u, 0, SCALBNF_TOLERANCE, 0},
+{60, 1142981585u, 0u, 1142981585u, 0, SCALBNF_TOLERANCE, 0},
+{61, 3347165962u, 0u, 3347165962u, 0, SCALBNF_TOLERANCE, 0},
+{62, 1009535440u, 4293825695u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{63, 3126820946u, 2u, 3143598162u, 0, SCALBNF_TOLERANCE, 0},
+{64, 3473956030u, 0u, 3473956030u, 0, SCALBNF_TOLERANCE, 0},
+{65, 3349098349u, 0u, 3349098349u, 0, SCALBNF_TOLERANCE, 0},
+{66, 3152729489u, 0u, 3152729489u, 0, SCALBNF_TOLERANCE, 0},
+{67, 945568720u, 4294963204u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{68, 3345489836u, 36u, 3647479724u, 0, SCALBNF_TOLERANCE, 0},
+{69, 976791751u, 4294967292u, 943237319u, 0, SCALBNF_TOLERANCE, 0},
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+{524, 3363524213u, 0u, 3363524213u, 0, SCALBNF_TOLERANCE, 0},
+{525, 1158950321u, 1u, 1167338929u, 0, SCALBNF_TOLERANCE, 0},
+{526, 903129873u, 4272788450u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{527, 3078339944u, 0u, 3078339944u, 0, SCALBNF_TOLERANCE, 0},
+{528, 1153863988u, 4229464460u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{529, 1235620969u, 0u, 1235620969u, 0, SCALBNF_TOLERANCE, 0},
+{530, 1097120930u, 4294967294u, 1080343714u, 0, SCALBNF_TOLERANCE, 0},
+{531, 1147712200u, 0u, 1147712200u, 0, SCALBNF_TOLERANCE, 0},
+{532, 1124721745u, 0u, 1124721745u, 0, SCALBNF_TOLERANCE, 0},
+{533, 3261744304u, 0u, 3261744304u, 0, SCALBNF_TOLERANCE, 0},
+{534, 3303160152u, 0u, 3303160152u, 0, SCALBNF_TOLERANCE, 0},
+{535, 1335399673u, 0u, 1335399673u, 0, SCALBNF_TOLERANCE, 0},
+{536, 1072458508u, 4294404660u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{537, 3303015249u, 0u, 3303015249u, 0, SCALBNF_TOLERANCE, 0},
+{538, 3252139741u, 0u, 3252139741u, 0, SCALBNF_TOLERANCE, 0},
+{539, 3468519966u, 0u, 3468519966u, 0, SCALBNF_TOLERANCE, 0},
+{540, 1006231203u, 0u, 1006231203u, 0, SCALBNF_TOLERANCE, 0},
+{541, 951554138u, 0u, 951554138u, 0, SCALBNF_TOLERANCE, 0},
+{542, 942046828u, 0u, 942046828u, 0, SCALBNF_TOLERANCE, 0},
+{543, 3255104167u, 0u, 3255104167u, 0, SCALBNF_TOLERANCE, 0},
+{544, 1155477903u, 0u, 1155477903u, 0, SCALBNF_TOLERANCE, 0},
+{545, 3273889176u, 0u, 3273889176u, 0, SCALBNF_TOLERANCE, 0},
+{546, 1228207362u, 0u, 1228207362u, 0, SCALBNF_TOLERANCE, 0},
+{547, 1290175785u, 0u, 1290175785u, 0, SCALBNF_TOLERANCE, 0},
+{548, 981908840u, 4294962938u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{549, 941187647u, 33u, 1218011711u, 0, SCALBNF_TOLERANCE, 0},
+{550, 1214223128u, 4294967293u, 1189057304u, 0, SCALBNF_TOLERANCE, 0},
+{551, 3422922584u, 6u, 3473254232u, 0, SCALBNF_TOLERANCE, 0},
+{552, 3453226030u, 4294967291u, 3411282990u, 0, SCALBNF_TOLERANCE, 0},
+{553, 1078359574u, 0u, 1078359574u, 0, SCALBNF_TOLERANCE, 0},
+{554, 1029557624u, 4294965511u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{555, 1207675424u, 0u, 1207675424u, 0, SCALBNF_TOLERANCE, 0},
+{556, 1028355074u, 4113313408u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{557, 1248421894u, 4294582111u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{558, 3353251994u, 12u, 3453915290u, 0, SCALBNF_TOLERANCE, 0},
+{559, 876926659u, 4294966792u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{560, 1076752219u, 0u, 1076752219u, 0, SCALBNF_TOLERANCE, 0},
+{561, 3388531942u, 0u, 3388531942u, 0, SCALBNF_TOLERANCE, 0},
+{562, 1273395082u, 0u, 1273395082u, 0, SCALBNF_TOLERANCE, 0},
+{563, 3034494183u, 0u, 3034494183u, 0, SCALBNF_TOLERANCE, 0},
+{564, 1171318485u, 4294306215u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{565, 3047748143u, 0u, 3047748143u, 0, SCALBNF_TOLERANCE, 0},
+{566, 1001216371u, 0u, 1001216371u, 0, SCALBNF_TOLERANCE, 0},
+{567, 912515889u, 2u, 929293105u, 0, SCALBNF_TOLERANCE, 0},
+{568, 3391452505u, 0u, 3391452505u, 0, SCALBNF_TOLERANCE, 0},
+{569, 3249603369u, 0u, 3249603369u, 0, SCALBNF_TOLERANCE, 0},
+{570, 1220264047u, 0u, 1220264047u, 0, SCALBNF_TOLERANCE, 0},
+{571, 3169816394u, 0u, 3169816394u, 0, SCALBNF_TOLERANCE, 0},
+{572, 3098997418u, 0u, 3098997418u, 0, SCALBNF_TOLERANCE, 0},
+{573, 3282212423u, 0u, 3282212423u, 0, SCALBNF_TOLERANCE, 0},
+{574, 3352293320u, 4294967278u, 3201298376u, 0, SCALBNF_TOLERANCE, 0},
+{575, 3296358441u, 0u, 3296358441u, 0, SCALBNF_TOLERANCE, 0},
+{576, 1197828352u, 4294967281u, 1071999232u, 0, SCALBNF_TOLERANCE, 0},
+{577, 3340510371u, 0u, 3340510371u, 0, SCALBNF_TOLERANCE, 0},
+{578, 1127109339u, 4294570975u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{579, 1200599955u, 0u, 1200599955u, 0, SCALBNF_TOLERANCE, 0},
+{580, 962230977u, 0u, 962230977u, 0, SCALBNF_TOLERANCE, 0},
+{581, 3192887808u, 0u, 3192887808u, 0, SCALBNF_TOLERANCE, 0},
+{582, 3237183876u, 0u, 3237183876u, 0, SCALBNF_TOLERANCE, 0},
+{583, 939285924u, 0u, 939285924u, 0, SCALBNF_TOLERANCE, 0},
+{584, 944050180u, 3871652128u, 0u, 0, SCALBNF_TOLERANCE, 0},
+{585, 3058135703u, 0u, 3058135703u, 0, SCALBNF_TOLERANCE, 0},
+{586, 1003299981u, 0u, 1003299981u, 0, SCALBNF_TOLERANCE, 0},
+{587, 1234491880u, 4283784819u, 0u, 0, SCALBNF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_SCABNF_H multiple inclusion protection
+
+// EOF scalbnf.h
diff --git a/packages/language/c/libm/current/tests/vectors/significandf.c b/packages/language/c/libm/current/tests/vectors/significandf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/significandf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      significandf.c
+//
+//      Test of significandf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/significandf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(significandf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &significandf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &significandf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("significandf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("significandf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library significandf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "significandf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF significandf.c
diff --git a/packages/language/c/libm/current/tests/vectors/significandf.h b/packages/language/c/libm/current/tests/vectors/significandf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/significandf.h
@@ -0,0 +1,2441 @@
+#ifndef CYGONCE_LIBM_SCABNF_H
+#define CYGONCE_LIBM_SCABNF_H
+//===========================================================================
+//
+//      significandf.h
+//
+//      Test vectors for testing of significandf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/significandf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define SIGNIFICANDF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t significandf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3212836864u, 3212836864u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{1, 3212836864u, 3211998003u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2, 3212836864u, 3211159142u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{3, 3212836864u, 3210320282u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{4, 3212836864u, 3209481421u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{5, 3212836864u, 3208642560u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{6, 3212836864u, 3207803699u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{7, 3212836864u, 3206964838u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{8, 3212836864u, 3206125978u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{9, 3212836864u, 3205287117u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{10, 3212836864u, 3204448256u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{11, 3212836864u, 3202770534u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{12, 3212836864u, 3201092813u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{13, 3212836864u, 3199415091u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{14, 3212836864u, 3197737370u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{15, 3212836864u, 3196059648u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{16, 3212836864u, 3192704205u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{17, 3212836864u, 3189348762u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{18, 3212836864u, 3184315597u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{19, 3212836864u, 3175926989u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{20, 3212836864u, 632815616u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{21, 3212836864u, 1028443341u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{22, 3212836864u, 1036831949u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{23, 3212836864u, 1041865114u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{24, 3212836864u, 1045220557u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{25, 3212836864u, 1048576000u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{26, 3212836864u, 1050253722u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{27, 3212836864u, 1051931443u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{28, 3212836864u, 1053609165u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{29, 3212836864u, 1055286886u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{30, 3212836864u, 1056964608u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{31, 3212836864u, 1057803469u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{32, 3212836864u, 1058642330u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{33, 3212836864u, 1059481190u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{34, 3212836864u, 1060320051u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{35, 3212836864u, 1061158912u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{36, 3212836864u, 1061997773u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{37, 3212836864u, 1062836634u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{38, 3212836864u, 1063675494u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{39, 3212836864u, 1064514355u, 3212836864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{40, 3211998003u, 3212836864u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{41, 3211998003u, 3211998003u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{42, 3211998003u, 3211159142u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{43, 3211998003u, 3210320282u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{44, 3211998003u, 3209481421u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{45, 3211998003u, 3208642560u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{46, 3211998003u, 3207803699u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{47, 3211998003u, 3206964838u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{48, 3211998003u, 3206125978u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{49, 3211998003u, 3205287117u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{50, 3211998003u, 3204448256u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{51, 3211998003u, 3202770534u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{52, 3211998003u, 3201092813u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{53, 3211998003u, 3199415091u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{54, 3211998003u, 3197737370u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{55, 3211998003u, 3196059648u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{56, 3211998003u, 3192704205u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{57, 3211998003u, 3189348762u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{58, 3211998003u, 3184315597u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{59, 3211998003u, 3175926989u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{60, 3211998003u, 632815616u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{61, 3211998003u, 1028443341u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{62, 3211998003u, 1036831949u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{63, 3211998003u, 1041865114u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{64, 3211998003u, 1045220557u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{65, 3211998003u, 1048576000u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{66, 3211998003u, 1050253722u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{67, 3211998003u, 1051931443u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{68, 3211998003u, 1053609165u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{69, 3211998003u, 1055286886u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{70, 3211998003u, 1056964608u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{71, 3211998003u, 1057803469u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{72, 3211998003u, 1058642330u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{73, 3211998003u, 1059481190u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{74, 3211998003u, 1060320051u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{75, 3211998003u, 1061158912u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{76, 3211998003u, 1061997773u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{77, 3211998003u, 1062836634u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{78, 3211998003u, 1063675494u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{79, 3211998003u, 1064514355u, 3220386611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{80, 3211159142u, 3212836864u, 3219547750u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{81, 3211159142u, 3211998003u, 3219547750u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{82, 3211159142u, 3211159142u, 3219547750u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{83, 3211159142u, 3210320282u, 3219547750u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{84, 3211159142u, 3209481421u, 3219547750u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{85, 3211159142u, 3208642560u, 3219547750u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{86, 3211159142u, 3207803699u, 3219547750u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{87, 3211159142u, 3206964838u, 3219547750u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{88, 3211159142u, 3206125978u, 3219547750u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{89, 3211159142u, 3205287117u, 3219547750u, 0, SIGNIFICANDF_TOLERANCE, 0},
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+{2297, 1315090496u, 3269683237u, 1071820864u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2298, 1335399673u, 974138676u, 1066964217u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2299, 1072458508u, 3372833993u, 1072458508u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2300, 3303015249u, 3015039539u, 3219129169u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2301, 3252139741u, 1059615003u, 3218585309u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2302, 3468519966u, 3113982619u, 3216861726u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2303, 1006231203u, 897530770u, 1073340067u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2304, 951554138u, 1001144381u, 1068994650u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2305, 942046828u, 986341002u, 1067875948u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2306, 3319723279u, 3414482416u, 3219059983u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2307, 3255104167u, 928827688u, 3213161127u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2308, 1155477903u, 3104812800u, 1071591823u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2309, 3273889176u, 980486479u, 3215168920u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2310, 3237813668u, 3441016803u, 3221036452u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2311, 1228207362u, 2985476579u, 1068823810u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2312, 1290175785u, 3008182462u, 1072071977u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2313, 981908840u, 3314038398u, 1065794920u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2314, 941187647u, 1107765599u, 1067016767u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2315, 1214223128u, 3225536822u, 1071616792u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2316, 3422922584u, 1086391131u, 3213207384u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2317, 1315857601u, 3487600045u, 1072587969u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2318, 3453226030u, 3233768835u, 3218345006u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2319, 1078359574u, 3199175230u, 1069970966u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2320, 1029557624u, 3302959071u, 1071500664u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2321, 1207675424u, 3042692550u, 1073457696u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2322, 1028355074u, 3442294040u, 1070298114u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2323, 1248421894u, 3367769132u, 1072261126u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2324, 3353251994u, 1095517730u, 3219034266u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2325, 876926659u, 3288089977u, 1069864643u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2326, 1076752219u, 876236939u, 1068363611u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2327, 3388531942u, 2988520062u, 3220759782u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2328, 1273395082u, 3031189261u, 1072068490u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2329, 3385588183u, 3258252464u, 3217816023u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2330, 3192315328u, 3289489214u, 3217481152u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2331, 3441804648u, 3274638356u, 3215312232u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2332, 3392827417u, 1277961150u, 3216666649u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2333, 1161241793u, 1328003707u, 1068967105u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2334, 3034494183u, 3041579130u, 3219043559u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2335, 1171318485u, 3374409104u, 1070655189u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2336, 3047748143u, 831102792u, 3215520303u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2337, 1001216371u, 3052357038u, 1068325235u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2338, 912515889u, 1074635609u, 1071899441u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2339, 3391452505u, 897989232u, 3215291737u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2340, 3249603369u, 3147662248u, 3216048937u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2341, 1220264047u, 2960450369u, 1069269103u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2342, 3169816394u, 988430929u, 3220148042u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2343, 3098997418u, 3002162688u, 3216437930u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2344, 3282212423u, 3174079140u, 3215103559u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2345, 3352293320u, 3247843425u, 3218075592u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2346, 3296358441u, 875645354u, 3220860969u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2347, 1197828352u, 3245614728u, 1071999232u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2348, 3340510371u, 914930263u, 3214681251u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2349, 1127109339u, 3368125489u, 1068389083u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2350, 1200599955u, 2981200675u, 1066382227u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2351, 962230977u, 2988248037u, 1071282881u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2352, 3192887808u, 3191848339u, 3218053632u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2353, 3237183876u, 3179379969u, 3220406660u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2354, 939285924u, 3056079386u, 1073503652u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2355, 944050180u, 3452557879u, 1069879300u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2356, 3058135703u, 3090284601u, 3217519255u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2357, 3480592662u, 3261728191u, 3220545814u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2358, 3061939312u, 3274418540u, 3212934256u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2359, 1003299981u, 853295521u, 1070408845u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2360, 1155775526u, 1255814444u, 1071889446u, 0, SIGNIFICANDF_TOLERANCE, 0},
+{2361, 1234491880u, 3408568717u, 1066719720u, 0, SIGNIFICANDF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_SCABNF_H multiple inclusion protection
+
+// EOF significandf.h
diff --git a/packages/language/c/libm/current/tests/vectors/sinf.c b/packages/language/c/libm/current/tests/vectors/sinf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/sinf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      sinf.c
+//
+//      Test of sinf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/sinf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(sinf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &sinf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &sinf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("sinf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("sinf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library sinf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "sinf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF sinf.c
diff --git a/packages/language/c/libm/current/tests/vectors/sinf.h b/packages/language/c/libm/current/tests/vectors/sinf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/sinf.h
@@ -0,0 +1,1231 @@
+#ifndef CYGONCE_LIBM_SCABNF_H
+#define CYGONCE_LIBM_SCABNF_H
+//===========================================================================
+//
+//      sinf.h
+//
+//      Test vectors for testing of sinf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/sinf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define SINF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t sinf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 0u, 3211696670u, 0, SINF_TOLERANCE, 0},
+{1, 3214430700u, 0u, 3211635095u, 0, SINF_TOLERANCE, 0},
+{2, 3214346813u, 0u, 3211571962u, 0, SINF_TOLERANCE, 0},
+{3, 3214262927u, 0u, 3211507279u, 0, SINF_TOLERANCE, 0},
+{4, 3214179041u, 0u, 3211441052u, 0, SINF_TOLERANCE, 0},
+{5, 3214095155u, 0u, 3211373285u, 0, SINF_TOLERANCE, 0},
+{6, 3214011269u, 0u, 3211303988u, 0, SINF_TOLERANCE, 0},
+{7, 3213927383u, 0u, 3211233167u, 0, SINF_TOLERANCE, 0},
+{8, 3213843497u, 0u, 3211160828u, 0, SINF_TOLERANCE, 0},
+{9, 3213759611u, 0u, 3211086979u, 0, SINF_TOLERANCE, 0},
+{10, 3213675725u, 0u, 3211011627u, 0, SINF_TOLERANCE, 0},
+{11, 3213591839u, 0u, 3210934780u, 0, SINF_TOLERANCE, 0},
+{12, 3213507953u, 0u, 3210856445u, 0, SINF_TOLERANCE, 0},
+{13, 3213424067u, 0u, 3210776631u, 0, SINF_TOLERANCE, 0},
+{14, 3213340180u, 0u, 3210695344u, 0, SINF_TOLERANCE, 0},
+{15, 3213256294u, 0u, 3210612595u, 0, SINF_TOLERANCE, 0},
+{16, 3213172408u, 0u, 3210528390u, 0, SINF_TOLERANCE, 0},
+{17, 3213088522u, 0u, 3210442738u, 0, SINF_TOLERANCE, 0},
+{18, 3213004636u, 0u, 3210355648u, 0, SINF_TOLERANCE, 0},
+{19, 3212920750u, 0u, 3210267129u, 0, SINF_TOLERANCE, 0},
+{20, 3212836864u, 0u, 3210177188u, 0, SINF_TOLERANCE, 0},
+{21, 3212669092u, 0u, 3210085836u, 0, SINF_TOLERANCE, 0},
+{22, 3212501320u, 0u, 3209993082u, 0, SINF_TOLERANCE, 0},
+{23, 3212333548u, 0u, 3209898934u, 0, SINF_TOLERANCE, 0},
+{24, 3212165775u, 0u, 3209803402u, 0, SINF_TOLERANCE, 0},
+{25, 3211998003u, 0u, 3209706495u, 0, SINF_TOLERANCE, 0},
+{26, 3211830231u, 0u, 3209608225u, 0, SINF_TOLERANCE, 0},
+{27, 3211662459u, 0u, 3209508599u, 0, SINF_TOLERANCE, 0},
+{28, 3211494687u, 0u, 3209407628u, 0, SINF_TOLERANCE, 0},
+{29, 3211326915u, 0u, 3209305323u, 0, SINF_TOLERANCE, 0},
+{30, 3211159142u, 0u, 3209201692u, 0, SINF_TOLERANCE, 0},
+{31, 3210991370u, 0u, 3209096748u, 0, SINF_TOLERANCE, 0},
+{32, 3210823598u, 0u, 3208990501u, 0, SINF_TOLERANCE, 0},
+{33, 3210655826u, 0u, 3208882960u, 0, SINF_TOLERANCE, 0},
+{34, 3210488054u, 0u, 3208774137u, 0, SINF_TOLERANCE, 0},
+{35, 3210320282u, 0u, 3208664042u, 0, SINF_TOLERANCE, 0},
+{36, 3210152509u, 0u, 3208552686u, 0, SINF_TOLERANCE, 0},
+{37, 3209984737u, 0u, 3208440082u, 0, SINF_TOLERANCE, 0},
+{38, 3209816965u, 0u, 3208326239u, 0, SINF_TOLERANCE, 0},
+{39, 3209649193u, 0u, 3208211170u, 0, SINF_TOLERANCE, 0},
+{40, 3209481421u, 0u, 3208094886u, 0, SINF_TOLERANCE, 0},
+{41, 3209313649u, 0u, 3207977399u, 0, SINF_TOLERANCE, 0},
+{42, 3209145876u, 0u, 3207858718u, 0, SINF_TOLERANCE, 0},
+{43, 3208978104u, 0u, 3207738859u, 0, SINF_TOLERANCE, 0},
+{44, 3208810332u, 0u, 3207617832u, 0, SINF_TOLERANCE, 0},
+{45, 3208642560u, 0u, 3207495649u, 0, SINF_TOLERANCE, 0},
+{46, 3208474788u, 0u, 3207372322u, 0, SINF_TOLERANCE, 0},
+{47, 3208307016u, 0u, 3207247864u, 0, SINF_TOLERANCE, 0},
+{48, 3208139244u, 0u, 3207122288u, 0, SINF_TOLERANCE, 0},
+{49, 3207971471u, 0u, 3206995604u, 0, SINF_TOLERANCE, 0},
+{50, 3207803699u, 0u, 3206867827u, 0, SINF_TOLERANCE, 0},
+{51, 3207635927u, 0u, 3206738970u, 0, SINF_TOLERANCE, 0},
+{52, 3207468155u, 0u, 3206609044u, 0, SINF_TOLERANCE, 0},
+{53, 3207300383u, 0u, 3206478064u, 0, SINF_TOLERANCE, 0},
+{54, 3207132611u, 0u, 3206346042u, 0, SINF_TOLERANCE, 0},
+{55, 3206964838u, 0u, 3206212991u, 0, SINF_TOLERANCE, 0},
+{56, 3206797066u, 0u, 3206078925u, 0, SINF_TOLERANCE, 0},
+{57, 3206629294u, 0u, 3205943857u, 0, SINF_TOLERANCE, 0},
+{58, 3206461522u, 0u, 3205807800u, 0, SINF_TOLERANCE, 0},
+{59, 3206293750u, 0u, 3205670769u, 0, SINF_TOLERANCE, 0},
+{60, 3206125978u, 0u, 3205532777u, 0, SINF_TOLERANCE, 0},
+{61, 3205958205u, 0u, 3205393837u, 0, SINF_TOLERANCE, 0},
+{62, 3205790433u, 0u, 3205253964u, 0, SINF_TOLERANCE, 0},
+{63, 3205622661u, 0u, 3205113171u, 0, SINF_TOLERANCE, 0},
+{64, 3205454889u, 0u, 3204971474u, 0, SINF_TOLERANCE, 0},
+{65, 3205287117u, 0u, 3204828885u, 0, SINF_TOLERANCE, 0},
+{66, 3205119345u, 0u, 3204685419u, 0, SINF_TOLERANCE, 0},
+{67, 3204951572u, 0u, 3204541090u, 0, SINF_TOLERANCE, 0},
+{68, 3204783800u, 0u, 3204343570u, 0, SINF_TOLERANCE, 0},
+{69, 3204616028u, 0u, 3204051550u, 0, SINF_TOLERANCE, 0},
+{70, 3204448256u, 0u, 3203757892u, 0, SINF_TOLERANCE, 0},
+{71, 3204112712u, 0u, 3203462625u, 0, SINF_TOLERANCE, 0},
+{72, 3203777167u, 0u, 3203165778u, 0, SINF_TOLERANCE, 0},
+{73, 3203441623u, 0u, 3202867382u, 0, SINF_TOLERANCE, 0},
+{74, 3203106079u, 0u, 3202567467u, 0, SINF_TOLERANCE, 0},
+{75, 3202770534u, 0u, 3202266061u, 0, SINF_TOLERANCE, 0},
+{76, 3202434990u, 0u, 3201963197u, 0, SINF_TOLERANCE, 0},
+{77, 3202099446u, 0u, 3201658903u, 0, SINF_TOLERANCE, 0},
+{78, 3201763901u, 0u, 3201353210u, 0, SINF_TOLERANCE, 0},
+{79, 3201428357u, 0u, 3201046149u, 0, SINF_TOLERANCE, 0},
+{80, 3201092813u, 0u, 3200737751u, 0, SINF_TOLERANCE, 0},
+{81, 3200757268u, 0u, 3200428046u, 0, SINF_TOLERANCE, 0},
+{82, 3200421724u, 0u, 3200117066u, 0, SINF_TOLERANCE, 0},
+{83, 3200086180u, 0u, 3199804841u, 0, SINF_TOLERANCE, 0},
+{84, 3199750636u, 0u, 3199491402u, 0, SINF_TOLERANCE, 0},
+{85, 3199415091u, 0u, 3199176781u, 0, SINF_TOLERANCE, 0},
+{86, 3199079547u, 0u, 3198861010u, 0, SINF_TOLERANCE, 0},
+{87, 3198744003u, 0u, 3198544120u, 0, SINF_TOLERANCE, 0},
+{88, 3198408458u, 0u, 3198226142u, 0, SINF_TOLERANCE, 0},
+{89, 3198072914u, 0u, 3197907109u, 0, SINF_TOLERANCE, 0},
+{90, 3197737370u, 0u, 3197587053u, 0, SINF_TOLERANCE, 0},
+{91, 3197401825u, 0u, 3197266004u, 0, SINF_TOLERANCE, 0},
+{92, 3197066281u, 0u, 3196943997u, 0, SINF_TOLERANCE, 0},
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+{1033, 3094833770u, 0u, 3094833770u, 0, SINF_TOLERANCE, 0},
+{1034, 3139250800u, 0u, 3139250790u, 0, SINF_TOLERANCE, 0},
+{1035, 886201503u, 4294967150u, 886201503u, 0, SINF_TOLERANCE, 0},
+{1036, 3297366026u, 7u, 3192470223u, 0, SINF_TOLERANCE, 0},
+{1037, 1218488455u, 4294964141u, 1045436187u, 0, SINF_TOLERANCE, 0},
+{1038, 3040358923u, 0u, 3040358923u, 0, SINF_TOLERANCE, 0},
+{1039, 1283938137u, 53086u, 3191014709u, 0, SINF_TOLERANCE, 0},
+{1040, 3182551696u, 0u, 3182537043u, 0, SINF_TOLERANCE, 0},
+{1041, 1317098613u, 0u, 3212501318u, 0, SINF_TOLERANCE, 0},
+{1042, 3116209179u, 4294965434u, 3116209179u, 0, SINF_TOLERANCE, 0},
+{1043, 3431703657u, 0u, 3206335982u, 0, SINF_TOLERANCE, 0},
+{1044, 3239728775u, 0u, 1046532122u, 0, SINF_TOLERANCE, 0},
+{1045, 3207141672u, 0u, 3206353199u, 0, SINF_TOLERANCE, 0},
+{1046, 3154378805u, 0u, 3154378711u, 0, SINF_TOLERANCE, 0},
+{1047, 3069658155u, 0u, 3069658155u, 0, SINF_TOLERANCE, 0},
+{1048, 3313160088u, 0u, 1063962697u, 0, SINF_TOLERANCE, 0},
+{1049, 3207056527u, 4293469023u, 3206285831u, 0, SINF_TOLERANCE, 0},
+{1050, 1284174954u, 4180334232u, 1064619785u, 0, SINF_TOLERANCE, 0},
+{1051, 3156081645u, 4294964338u, 3156081485u, 0, SINF_TOLERANCE, 0},
+{1052, 1063693032u, 0u, 1061728939u, 0, SINF_TOLERANCE, 0},
+{1053, 3036026175u, 4845007u, 3036026175u, 0, SINF_TOLERANCE, 0},
+{1054, 1102631663u, 4290881696u, 3211100727u, 0, SINF_TOLERANCE, 0},
+{1055, 968803479u, 0u, 968803479u, 0, SINF_TOLERANCE, 0},
+{1056, 3273080388u, 0u, 3202168628u, 0, SINF_TOLERANCE, 0},
+{1057, 1172529774u, 4294966405u, 1052481368u, 0, SINF_TOLERANCE, 0},
+{1058, 1306695905u, 147733664u, 1063024816u, 0, SINF_TOLERANCE, 0},
+{1059, 1003649752u, 338518u, 1003649657u, 0, SINF_TOLERANCE, 0},
+{1060, 1078478376u, 2364151808u, 1011462484u, 0, SINF_TOLERANCE, 0},
+{1061, 3158855023u, 0u, 3158854696u, 0, SINF_TOLERANCE, 0},
+{1062, 1165177679u, 4294967097u, 1064368675u, 0, SINF_TOLERANCE, 0},
+{1063, 3403009513u, 4293749042u, 3200332882u, 0, SINF_TOLERANCE, 0},
+{1064, 952348506u, 4294108410u, 952348506u, 0, SINF_TOLERANCE, 0},
+{1065, 1222777442u, 153u, 1061418024u, 0, SINF_TOLERANCE, 0},
+{1066, 1325324763u, 0u, 1057307338u, 0, SINF_TOLERANCE, 0},
+{1067, 3363524213u, 0u, 1057332239u, 0, SINF_TOLERANCE, 0},
+{1068, 1158950321u, 1u, 1063101660u, 0, SINF_TOLERANCE, 0},
+{1069, 903129873u, 4272788450u, 903129873u, 0, SINF_TOLERANCE, 0},
+{1070, 3078339944u, 0u, 3078339944u, 0, SINF_TOLERANCE, 0},
+{1071, 1208345407u, 6333643u, 1064552605u, 0, SINF_TOLERANCE, 0},
+{1072, 1258634105u, 3575206u, 1049625456u, 0, SINF_TOLERANCE, 0},
+{1073, 1248478509u, 102613680u, 3212835226u, 0, SINF_TOLERANCE, 0},
+{1074, 1153863988u, 4229464460u, 3211074162u, 0, SINF_TOLERANCE, 0},
+{1075, 1235620969u, 0u, 1064569301u, 0, SINF_TOLERANCE, 0},
+{1076, 1097120930u, 4294967294u, 1065141893u, 0, SINF_TOLERANCE, 0},
+{1077, 3469778622u, 70286u, 1065325367u, 0, SINF_TOLERANCE, 0},
+{1078, 1147712200u, 0u, 1061528543u, 0, SINF_TOLERANCE, 0},
+{1079, 1124721745u, 0u, 3198804551u, 0, SINF_TOLERANCE, 0},
+{1080, 3261744304u, 0u, 3211184016u, 0, SINF_TOLERANCE, 0},
+{1081, 1064922416u, 1518435840u, 1062456150u, 0, SINF_TOLERANCE, 0},
+{1082, 3303160152u, 0u, 3194883701u, 0, SINF_TOLERANCE, 0},
+{1083, 1315090496u, 4294967183u, 1027282864u, 0, SINF_TOLERANCE, 0},
+{1084, 3230403187u, 1820050432u, 1064414424u, 0, SINF_TOLERANCE, 0},
+{1085, 1335399673u, 0u, 1057037838u, 0, SINF_TOLERANCE, 0},
+{1086, 1072458508u, 4294404660u, 1064717243u, 0, SINF_TOLERANCE, 0},
+{1087, 3303015249u, 0u, 3212580702u, 0, SINF_TOLERANCE, 0},
+{1088, 3252139741u, 0u, 3212269737u, 0, SINF_TOLERANCE, 0},
+{1089, 3468519966u, 0u, 3212788099u, 0, SINF_TOLERANCE, 0},
+{1090, 1006231203u, 0u, 1006231044u, 0, SINF_TOLERANCE, 0},
+{1091, 951554138u, 0u, 951554138u, 0, SINF_TOLERANCE, 0},
+{1092, 942046828u, 0u, 942046828u, 0, SINF_TOLERANCE, 0},
+{1093, 3319723279u, 4277552160u, 1033521666u, 0, SINF_TOLERANCE, 0},
+{1094, 3255104167u, 0u, 3212314295u, 0, SINF_TOLERANCE, 0},
+{1095, 1155477903u, 0u, 1063706868u, 0, SINF_TOLERANCE, 0},
+{1096, 3273889176u, 0u, 3194027929u, 0, SINF_TOLERANCE, 0},
+{1097, 3237813668u, 4133749200u, 3212810671u, 0, SINF_TOLERANCE, 0},
+{1098, 1228207362u, 0u, 3210431030u, 0, SINF_TOLERANCE, 0},
+{1099, 975349337u, 748694784u, 975349336u, 0, SINF_TOLERANCE, 0},
+{1100, 1290175785u, 0u, 3208122918u, 0, SINF_TOLERANCE, 0},
+{1101, 981908840u, 4294962938u, 981908838u, 0, SINF_TOLERANCE, 0},
+{1102, 941187647u, 33u, 941187647u, 0, SINF_TOLERANCE, 0},
+{1103, 1214223128u, 4294967293u, 3175395280u, 0, SINF_TOLERANCE, 0},
+{1104, 3422922584u, 6u, 3202621705u, 0, SINF_TOLERANCE, 0},
+{1105, 1315857601u, 1055172096u, 1060440419u, 0, SINF_TOLERANCE, 0},
+{1106, 3453226030u, 4294967291u, 1055080459u, 0, SINF_TOLERANCE, 0},
+{1107, 1078359574u, 0u, 1025926511u, 0, SINF_TOLERANCE, 0},
+{1108, 1029557624u, 4294965511u, 1029550521u, 0, SINF_TOLERANCE, 0},
+{1109, 1207675424u, 0u, 1043330099u, 0, SINF_TOLERANCE, 0},
+{1110, 1028355074u, 4113313408u, 1028349592u, 0, SINF_TOLERANCE, 0},
+{1111, 3119299090u, 24787u, 3119299089u, 0, SINF_TOLERANCE, 0},
+{1112, 1248421894u, 4294582111u, 1059507841u, 0, SINF_TOLERANCE, 0},
+{1113, 3353251994u, 12u, 3212445556u, 0, SINF_TOLERANCE, 0},
+{1114, 876926659u, 4294966792u, 876926659u, 0, SINF_TOLERANCE, 0},
+{1115, 1076752219u, 0u, 1053987679u, 0, SINF_TOLERANCE, 0},
+{1116, 3388531942u, 0u, 3150373635u, 0, SINF_TOLERANCE, 0},
+{1117, 1273395082u, 0u, 3195827353u, 0, SINF_TOLERANCE, 0},
+{1118, 3385588183u, 4294967251u, 3212638167u, 0, SINF_TOLERANCE, 0},
+{1119, 3192315328u, 4294966714u, 3192233558u, 0, SINF_TOLERANCE, 0},
+{1120, 3441804648u, 4294967121u, 1064889844u, 0, SINF_TOLERANCE, 0},
+{1121, 3392827417u, 45125368u, 3204991638u, 0, SINF_TOLERANCE, 0},
+{1122, 1161241793u, 2814016256u, 1060713941u, 0, SINF_TOLERANCE, 0},
+{1123, 3034494183u, 0u, 3034494183u, 0, SINF_TOLERANCE, 0},
+{1124, 1171318485u, 4294306215u, 3202421859u, 0, SINF_TOLERANCE, 0},
+{1125, 3047748143u, 0u, 3047748143u, 0, SINF_TOLERANCE, 0},
+{1126, 1001216371u, 0u, 1001216318u, 0, SINF_TOLERANCE, 0},
+{1127, 912515889u, 2u, 912515889u, 0, SINF_TOLERANCE, 0},
+{1128, 3391452505u, 0u, 3205889616u, 0, SINF_TOLERANCE, 0},
+{1129, 3249603369u, 0u, 1040857218u, 0, SINF_TOLERANCE, 0},
+{1130, 1220264047u, 0u, 3194967897u, 0, SINF_TOLERANCE, 0},
+{1131, 3169816394u, 0u, 3169814156u, 0, SINF_TOLERANCE, 0},
+{1132, 3098997418u, 0u, 3098997418u, 0, SINF_TOLERANCE, 0},
+{1133, 3282212423u, 0u, 1065350123u, 0, SINF_TOLERANCE, 0},
+{1134, 3352293320u, 4294967278u, 3212086835u, 0, SINF_TOLERANCE, 0},
+{1135, 3296358441u, 0u, 3201216860u, 0, SINF_TOLERANCE, 0},
+{1136, 1197828352u, 4294967281u, 1032387171u, 0, SINF_TOLERANCE, 0},
+{1137, 3340510371u, 0u, 1062585647u, 0, SINF_TOLERANCE, 0},
+{1138, 1127109339u, 4294570975u, 3212826742u, 0, SINF_TOLERANCE, 0},
+{1139, 909467381u, 1001724u, 909467381u, 0, SINF_TOLERANCE, 0},
+{1140, 1200599955u, 0u, 3209721212u, 0, SINF_TOLERANCE, 0},
+{1141, 962230977u, 0u, 962230977u, 0, SINF_TOLERANCE, 0},
+{1142, 3192887808u, 0u, 3192794798u, 0, SINF_TOLERANCE, 0},
+{1143, 3237183876u, 0u, 3212338202u, 0, SINF_TOLERANCE, 0},
+{1144, 939285924u, 0u, 939285924u, 0, SINF_TOLERANCE, 0},
+{1145, 944050180u, 3871652128u, 944050180u, 0, SINF_TOLERANCE, 0},
+{1146, 3058135703u, 0u, 3058135703u, 0, SINF_TOLERANCE, 0},
+{1147, 3480592662u, 4294967238u, 3204456894u, 0, SINF_TOLERANCE, 0},
+{1148, 3061939312u, 4294967125u, 3061939312u, 0, SINF_TOLERANCE, 0},
+{1149, 1003299981u, 0u, 1003299893u, 0, SINF_TOLERANCE, 0},
+{1150, 1155775526u, 7150230u, 3195501537u, 0, SINF_TOLERANCE, 0},
+{1151, 1234491880u, 4283784819u, 3212387912u, 0, SINF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_SCABNF_H multiple inclusion protection
+
+// EOF sinf.h
diff --git a/packages/language/c/libm/current/tests/vectors/sinhf.c b/packages/language/c/libm/current/tests/vectors/sinhf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/sinhf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      sinhf.c
+//
+//      Test of sinhf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/sinhf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(sinhf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &sinhf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &sinhf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("sinhf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("sinhf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library sinhf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "sinhf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF sinhf.c
diff --git a/packages/language/c/libm/current/tests/vectors/sinhf.h b/packages/language/c/libm/current/tests/vectors/sinhf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/sinhf.h
@@ -0,0 +1,363 @@
+#ifndef CYGONCE_LIBM_SINHF_H
+#define CYGONCE_LIBM_SINHF_H
+//===========================================================================
+//
+//      sinhf.h
+//
+//      Test vectors for testing of sinhf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/sinhf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define SINH_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t sinhf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 3217110536u, 3217110536u, 0, SINH_TOLERANCE, 0},
+{1, 3214430700u, 3216959278u, 3216959278u, 0, SINH_TOLERANCE, 0},
+{2, 3214346813u, 3216809269u, 3216809269u, 0, SINH_TOLERANCE, 0},
+{3, 3214262927u, 3216660499u, 3216660499u, 0, SINH_TOLERANCE, 0},
+{4, 3214179041u, 3216512949u, 3216512949u, 0, SINH_TOLERANCE, 0},
+{5, 3214095155u, 3216366607u, 3216366607u, 0, SINH_TOLERANCE, 0},
+{6, 3214011269u, 3216221454u, 3216221454u, 0, SINH_TOLERANCE, 0},
+{7, 3213927383u, 3216077481u, 3216077481u, 0, SINH_TOLERANCE, 0},
+{8, 3213843497u, 3215934670u, 3215934670u, 0, SINH_TOLERANCE, 0},
+{9, 3213759611u, 3215793008u, 3215793008u, 0, SINH_TOLERANCE, 0},
+{10, 3213675725u, 3215652480u, 3215652480u, 0, SINH_TOLERANCE, 0},
+{11, 3213591839u, 3215513072u, 3215513072u, 0, SINH_TOLERANCE, 0},
+{12, 3213507953u, 3215374771u, 3215374771u, 0, SINH_TOLERANCE, 0},
+{13, 3213424067u, 3215237562u, 3215237562u, 0, SINH_TOLERANCE, 0},
+{14, 3213340180u, 3215101431u, 3215101431u, 0, SINH_TOLERANCE, 0},
+{15, 3213256294u, 3214966367u, 3214966367u, 0, SINH_TOLERANCE, 0},
+{16, 3213172408u, 3214832356u, 3214832356u, 0, SINH_TOLERANCE, 0},
+{17, 3213088522u, 3214699382u, 3214699382u, 0, SINH_TOLERANCE, 0},
+{18, 3213004636u, 3214567433u, 3214567433u, 0, SINH_TOLERANCE, 0},
+{19, 3212920750u, 3214436496u, 3214436496u, 0, SINH_TOLERANCE, 0},
+{20, 3212836864u, 3214306558u, 3214306558u, 0, SINH_TOLERANCE, 0},
+{21, 3212669092u, 3214177606u, 3214177606u, 0, SINH_TOLERANCE, 0},
+{22, 3212501320u, 3214049627u, 3214049627u, 0, SINH_TOLERANCE, 0},
+{23, 3212333548u, 3213922608u, 3213922608u, 0, SINH_TOLERANCE, 0},
+{24, 3212165775u, 3213796536u, 3213796536u, 0, SINH_TOLERANCE, 0},
+{25, 3211998003u, 3213671399u, 3213671399u, 0, SINH_TOLERANCE, 0},
+{26, 3211830231u, 3213547184u, 3213547184u, 0, SINH_TOLERANCE, 0},
+{27, 3211662459u, 3213423880u, 3213423880u, 0, SINH_TOLERANCE, 0},
+{28, 3211494687u, 3213301473u, 3213301473u, 0, SINH_TOLERANCE, 0},
+{29, 3211326915u, 3213179951u, 3213179951u, 0, SINH_TOLERANCE, 0},
+{30, 3211159142u, 3213059302u, 3213059302u, 0, SINH_TOLERANCE, 0},
+{31, 3210991370u, 3212939515u, 3212939515u, 0, SINH_TOLERANCE, 0},
+{32, 3210823598u, 3212804289u, 3212804289u, 0, SINH_TOLERANCE, 0},
+{33, 3210655826u, 3212568087u, 3212568087u, 0, SINH_TOLERANCE, 0},
+{34, 3210488054u, 3212333536u, 3212333536u, 0, SINH_TOLERANCE, 0},
+{35, 3210320282u, 3212100612u, 3212100612u, 0, SINH_TOLERANCE, 0},
+{36, 3210152509u, 3211869292u, 3211869292u, 0, SINH_TOLERANCE, 0},
+{37, 3209984737u, 3211639553u, 3211639553u, 0, SINH_TOLERANCE, 0},
+{38, 3209816965u, 3211411372u, 3211411372u, 0, SINH_TOLERANCE, 0},
+{39, 3209649193u, 3211184727u, 3211184727u, 0, SINH_TOLERANCE, 0},
+{40, 3209481421u, 3210959594u, 3210959594u, 0, SINH_TOLERANCE, 0},
+{41, 3209313649u, 3210735951u, 3210735951u, 0, SINH_TOLERANCE, 0},
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+{256, 3246601011u, 3402254137u, 3402254137u, 0, SINH_TOLERANCE, 0},
+{257, 3245028147u, 3381907410u, 3381907410u, 0, SINH_TOLERANCE, 0},
+{258, 3243245568u, 3361211828u, 3361211828u, 0, SINH_TOLERANCE, 0},
+{259, 3241462989u, 3340622545u, 3340622545u, 0, SINH_TOLERANCE, 0},
+{260, 3239680410u, 3320230690u, 3320230690u, 0, SINH_TOLERANCE, 0},
+{261, 3237792973u, 3299382405u, 3299382405u, 0, SINH_TOLERANCE, 0},
+{262, 3234227814u, 3279314841u, 3279314841u, 0, SINH_TOLERANCE, 0},
+{263, 3230662656u, 3258188566u, 3258188566u, 0, SINH_TOLERANCE, 0},
+{264, 3224580915u, 3238203928u, 3238203928u, 0, SINH_TOLERANCE, 0},
+{265, 3213675725u, 3215652480u, 3215652480u, 0, SINH_TOLERANCE, 0},
+{266, 1058642330u, 1059257275u, 1059257275u, 0, SINH_TOLERANCE, 0},
+{267, 1075000115u, 1084095382u, 1084095382u, 0, SINH_TOLERANCE, 0},
+{268, 1082130432u, 1104826815u, 1104826815u, 0, SINH_TOLERANCE, 0},
+{269, 1085695590u, 1125478038u, 1125478038u, 0, SINH_TOLERANCE, 0},
+{270, 1089260749u, 1145864059u, 1145864059u, 0, SINH_TOLERANCE, 0},
+{271, 1091672474u, 1166798129u, 1166798129u, 0, SINH_TOLERANCE, 0},
+{272, 1093455053u, 1186954451u, 1186954451u, 0, SINH_TOLERANCE, 0},
+{273, 1095237632u, 1208157740u, 1208157740u, 0, SINH_TOLERANCE, 0},
+{274, 1097020211u, 1228099076u, 1228099076u, 0, SINH_TOLERANCE, 0},
+{275, 1098802790u, 1249206348u, 1249206348u, 0, SINH_TOLERANCE, 0},
+{276, 1099746509u, 1269294498u, 1269294498u, 0, SINH_TOLERANCE, 0},
+{277, 1100637798u, 1290126283u, 1290126283u, 0, SINH_TOLERANCE, 0},
+{278, 1101529088u, 1310537485u, 1310537485u, 0, SINH_TOLERANCE, 0},
+{279, 1102420378u, 1331111329u, 1331111329u, 0, SINH_TOLERANCE, 0},
+{280, 1103311667u, 1351825023u, 1351825023u, 0, SINH_TOLERANCE, 0},
+{281, 1104202957u, 1372157288u, 1372157288u, 0, SINH_TOLERANCE, 0},
+{282, 1105094246u, 1393154230u, 1393154230u, 0, SINH_TOLERANCE, 0},
+{283, 1105985536u, 1413260339u, 1413260339u, 0, SINH_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_SINHF_H multiple inclusion protection
+
+// EOF sinhf.h
diff --git a/packages/language/c/libm/current/tests/vectors/sqrtf.c b/packages/language/c/libm/current/tests/vectors/sqrtf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/sqrtf.c
@@ -0,0 +1,127 @@
+//===========================================================================
+//
+//      sqrtf.c
+//
+//      Test of sqrtf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_double_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/sqrtf.h"
+
+// FUNCTIONS
+
+#ifdef CYGSEM_LIBM_IEEE_API_INLINE
+float Sqrtf(float x)
+{
+    return sqrtf(x);
+}
+#endif
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(sqrtf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat(
+#ifndef CYGSEM_LIBM_IEEE_API_INLINE
+                     (CYG_ADDRWORD) &sqrtf,
+#else
+                     (CYG_ADDRWORD) &Sqrtf,
+#endif
+                     CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &sqrtf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("sqrtf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("sqrtf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library sqrtf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "sqrtf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+// EOF sqrtf.c
diff --git a/packages/language/c/libm/current/tests/vectors/sqrtf.h b/packages/language/c/libm/current/tests/vectors/sqrtf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/sqrtf.h
@@ -0,0 +1,362 @@
+#ifndef CYGONCE_LIBM_SQRT_H
+#define CYGONCE_LIBM_SQRT_H
+//===========================================================================
+//
+//      sqrtf.h
+//
+//      Test vectors for testing of sqrtf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/sqrtf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define SQRT_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t sqrtf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 1090024059u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{1, 3214430700u, 1051524793u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{2, 3214346813u, 3232101343u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{3, 3214262927u, 3201242716u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{4, 3214179041u, 1100049309u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{5, 3214095155u, 1054478713u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{6, 3214011269u, 3202039382u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{7, 3213927383u, 1046089230u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{8, 3213843497u, 1045840574u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{9, 3213759611u, 1068931671u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{10, 3213675725u, 3222889559u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{11, 3213591839u, 1088899021u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{12, 3213507953u, 1066856791u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{13, 3213424067u, 1080833116u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{14, 3213340180u, 3191644264u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{15, 3213256294u, 3239903247u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{16, 3213172408u, 3198462609u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{17, 3213088522u, 3203741999u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{18, 3213004636u, 3249401130u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{19, 3212920750u, 3197817016u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{20, 3212836864u, 3231746400u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{21, 3212669092u, 1096608669u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{22, 3212501320u, 1045286891u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{23, 3212333548u, 1049342524u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{24, 3212165775u, 1078472138u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{25, 3211998003u, 1099527247u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{26, 3211830231u, 3189610016u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{27, 3211662459u, 1083791358u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{28, 3211494687u, 3214426435u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{29, 3211326915u, 1056316170u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{30, 3211159142u, 3251828686u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{31, 3210991370u, 3240257920u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{32, 3210823598u, 3237899261u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{33, 3210655826u, 3226869477u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{34, 3210488054u, 1106394906u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{35, 3210320282u, 3231581370u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{36, 3210152509u, 1061652681u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{37, 3209984737u, 3215417793u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{38, 3209816965u, 3238067573u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{39, 3209649193u, 1045917232u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{40, 3209481421u, 1066381836u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{41, 3209313649u, 1060345752u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{42, 3209145876u, 1052460275u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{43, 3208978104u, 3196647153u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{44, 3208810332u, 1081948134u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{45, 3208642560u, 3221584595u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{46, 3208474788u, 1086226574u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{47, 3208307016u, 3251401196u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{48, 3208139244u, 1083520023u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{49, 3207971471u, 1050330591u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{50, 3207803699u, 1077406406u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{51, 3207635927u, 3220729740u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{52, 3207468155u, 1046304788u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{53, 3207300383u, 1094907481u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{54, 3207132611u, 1065432625u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{55, 3206964838u, 1082985198u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{56, 3206797066u, 3222902057u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{57, 3206629294u, 3249723525u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{58, 3206461522u, 1067056698u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{59, 3206293750u, 3209056785u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{60, 3206125978u, 1106787580u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{61, 3205958205u, 1104232051u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{62, 3205790433u, 1105467109u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{63, 3205622661u, 3214251949u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{64, 3205454889u, 1103073830u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{65, 3205287117u, 1067009473u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{66, 3205119345u, 1101371955u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{67, 3204951572u, 1099430098u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{68, 3204783800u, 3188865420u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{69, 3204616028u, 1046255144u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{70, 3204448256u, 3231633258u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{71, 3204112712u, 3202219056u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{72, 3203777167u, 1048653554u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{73, 3203441623u, 3221570188u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{74, 3203106079u, 1099107978u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{75, 3202770534u, 1087299442u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{76, 3202434990u, 3197285510u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{77, 3202099446u, 1090971734u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{78, 3201763901u, 3252967851u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{79, 3201428357u, 3206610957u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{80, 3201092813u, 1073415902u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{81, 3200757268u, 3190678390u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{82, 3200421724u, 3205337291u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{83, 3200086180u, 3216653996u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{84, 3199750636u, 3240198679u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{85, 3199415091u, 3251167793u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{86, 3199079547u, 1079286273u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{87, 3198744003u, 3231412671u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{88, 3198408458u, 1048317852u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{89, 3198072914u, 3192982124u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{90, 3197737370u, 1104691287u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{91, 3197401825u, 1082507103u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{92, 3197066281u, 1096584871u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{93, 3196730737u, 1103798670u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{94, 3196395192u, 3240157452u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{95, 3196059648u, 3214382367u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{96, 3195388559u, 3240200923u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{97, 3194717471u, 1103793878u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{98, 3194046382u, 1077424413u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{99, 3193375293u, 3227593179u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{100, 3192704205u, 1076579751u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{101, 3192033116u, 1069112254u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{102, 3191362028u, 3215075200u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{103, 3190690939u, 1060430241u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{104, 3190019850u, 3237198975u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{105, 3189348762u, 3202753937u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{106, 3188677673u, 1062342831u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{107, 3188006584u, 1066474375u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{108, 3186999951u, 3239267288u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{109, 3185657774u, 3210508124u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{110, 3184315597u, 3241241441u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{111, 3182973420u, 3243941101u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{112, 3181631242u, 1074261978u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{113, 3180289065u, 1061635587u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{114, 3178611343u, 1071440059u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{115, 3175926989u, 1072073912u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{116, 3173242634u, 3232757923u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{117, 3170222735u, 1078073146u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{118, 3164854026u, 1081649113u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{119, 3156465418u, 3222407050u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{120, 646742016u, 1105124431u, 856038076u, 0, SQRT_TOLERANCE, 0},
+{121, 1008981770u, 3198136112u, 1036831949u, 0, SQRT_TOLERANCE, 0},
+{122, 1017370378u, 3215264397u, 1041289411u, 0, SQRT_TOLERANCE, 0},
+{123, 1022739087u, 1061072607u, 1043422380u, 0, SQRT_TOLERANCE, 0},
+{124, 1025758986u, 1082896196u, 1045220557u, 0, SQRT_TOLERANCE, 0},
+{125, 1028443341u, 3187675097u, 1046804782u, 0, SQRT_TOLERANCE, 0},
+{126, 1031127695u, 3234748208u, 1048237031u, 0, SQRT_TOLERANCE, 0},
+{127, 1032805417u, 1046724025u, 1049065060u, 0, SQRT_TOLERANCE, 0},
+{128, 1034147594u, 1093012318u, 1049678019u, 0, SQRT_TOLERANCE, 0},
+{129, 1035489772u, 1069733884u, 1050253722u, 0, SQRT_TOLERANCE, 0},
+{130, 1036831949u, 3204997271u, 1050798235u, 0, SQRT_TOLERANCE, 0},
+{131, 1038174126u, 3213604117u, 1051316138u, 0, SQRT_TOLERANCE, 0},
+{132, 1039516303u, 3246333414u, 1051810988u, 0, SQRT_TOLERANCE, 0},
+{133, 1040522936u, 1082858682u, 1052285615u, 0, SQRT_TOLERANCE, 0},
+{134, 1041194025u, 1083603224u, 1052742311u, 0, SQRT_TOLERANCE, 0},
+{135, 1041865114u, 3235600523u, 1053182968u, 0, SQRT_TOLERANCE, 0},
+{136, 1042536202u, 1051824459u, 1053609165u, 0, SQRT_TOLERANCE, 0},
+{137, 1043207291u, 3250673860u, 1054022239u, 0, SQRT_TOLERANCE, 0},
+{138, 1043878380u, 1049514449u, 1054423332u, 0, SQRT_TOLERANCE, 0},
+{139, 1044549468u, 1054539840u, 1054813430u, 0, SQRT_TOLERANCE, 0},
+{140, 1045220557u, 1045993352u, 1055193390u, 0, SQRT_TOLERANCE, 0},
+{141, 1045891645u, 3229182089u, 1055563964u, 0, SQRT_TOLERANCE, 0},
+{142, 1046562734u, 1071630912u, 1055925816u, 0, SQRT_TOLERANCE, 0},
+{143, 1047233823u, 1063422305u, 1056279532u, 0, SQRT_TOLERANCE, 0},
+{144, 1047904911u, 1040201163u, 1056625639u, 0, SQRT_TOLERANCE, 0},
+{145, 1048576000u, 1101553990u, 1056964608u, 0, SQRT_TOLERANCE, 0},
+{146, 1048911544u, 1042678728u, 1057130735u, 0, SQRT_TOLERANCE, 0},
+{147, 1049247089u, 1070002807u, 1057293697u, 0, SQRT_TOLERANCE, 0},
+{148, 1049582633u, 1104170406u, 1057453668u, 0, SQRT_TOLERANCE, 0},
+{149, 1049918177u, 1060859316u, 1057610807u, 0, SQRT_TOLERANCE, 0},
+{150, 1050253722u, 1067940450u, 1057765260u, 0, SQRT_TOLERANCE, 0},
+{151, 1050589266u, 3236511256u, 1057917159u, 0, SQRT_TOLERANCE, 0},
+{152, 1050924810u, 3250520938u, 1058066627u, 0, SQRT_TOLERANCE, 0},
+{153, 1051260355u, 3209806504u, 1058213777u, 0, SQRT_TOLERANCE, 0},
+{154, 1051595899u, 3202890678u, 1058358714u, 0, SQRT_TOLERANCE, 0},
+{155, 1051931443u, 3203138231u, 1058501535u, 0, SQRT_TOLERANCE, 0},
+{156, 1052266988u, 1061134072u, 1058642330u, 0, SQRT_TOLERANCE, 0},
+{157, 1052602532u, 1055663370u, 1058781182u, 0, SQRT_TOLERANCE, 0},
+{158, 1052938076u, 3199478070u, 1058918171u, 0, SQRT_TOLERANCE, 0},
+{159, 1053273620u, 3196654963u, 1059053368u, 0, SQRT_TOLERANCE, 0},
+{160, 1053609165u, 3232578253u, 1059186843u, 0, SQRT_TOLERANCE, 0},
+{161, 1053944709u, 1050082319u, 1059318660u, 0, SQRT_TOLERANCE, 0},
+{162, 1054280253u, 3253385962u, 1059448879u, 0, SQRT_TOLERANCE, 0},
+{163, 1054615798u, 1070166500u, 1059577556u, 0, SQRT_TOLERANCE, 0},
+{164, 1054951342u, 3244621407u, 1059704746u, 0, SQRT_TOLERANCE, 0},
+{165, 1055286886u, 3200798890u, 1059830499u, 0, SQRT_TOLERANCE, 0},
+{166, 1055622431u, 3223590310u, 1059954862u, 0, SQRT_TOLERANCE, 0},
+{167, 1055957975u, 1075961161u, 1060077880u, 0, SQRT_TOLERANCE, 0},
+{168, 1056293519u, 1078123323u, 1060199596u, 0, SQRT_TOLERANCE, 0},
+{169, 1056629064u, 3210844787u, 1060320051u, 0, SQRT_TOLERANCE, 0},
+{170, 1056964608u, 3246307879u, 1060439283u, 0, SQRT_TOLERANCE, 0},
+{171, 1057132380u, 3188814424u, 1060557329u, 0, SQRT_TOLERANCE, 0},
+{172, 1057300152u, 3221436876u, 1060674223u, 0, SQRT_TOLERANCE, 0},
+{173, 1057467924u, 3200554324u, 1060789998u, 0, SQRT_TOLERANCE, 0},
+{174, 1057635697u, 3239246636u, 1060904686u, 0, SQRT_TOLERANCE, 0},
+{175, 1057803469u, 3223587064u, 1061018316u, 0, SQRT_TOLERANCE, 0},
+{176, 1057971241u, 3250158026u, 1061130919u, 0, SQRT_TOLERANCE, 0},
+{177, 1058139013u, 1106085272u, 1061242520u, 0, SQRT_TOLERANCE, 0},
+{178, 1058306785u, 1095245453u, 1061353147u, 0, SQRT_TOLERANCE, 0},
+{179, 1058474557u, 1041444355u, 1061462824u, 0, SQRT_TOLERANCE, 0},
+{180, 1058642330u, 1097465301u, 1061571576u, 0, SQRT_TOLERANCE, 0},
+{181, 1058810102u, 3250239076u, 1061679425u, 0, SQRT_TOLERANCE, 0},
+{182, 1058977874u, 1084039594u, 1061786393u, 0, SQRT_TOLERANCE, 0},
+{183, 1059145646u, 1063771493u, 1061892502u, 0, SQRT_TOLERANCE, 0},
+{184, 1059313418u, 1103919063u, 1061997773u, 0, SQRT_TOLERANCE, 0},
+{185, 1059481190u, 3194616071u, 1062102224u, 0, SQRT_TOLERANCE, 0},
+{186, 1059648963u, 3221613219u, 1062205875u, 0, SQRT_TOLERANCE, 0},
+{187, 1059816735u, 3208334452u, 1062308743u, 0, SQRT_TOLERANCE, 0},
+{188, 1059984507u, 1061894279u, 1062410847u, 0, SQRT_TOLERANCE, 0},
+{189, 1060152279u, 3209762784u, 1062512202u, 0, SQRT_TOLERANCE, 0},
+{190, 1060320051u, 3206165386u, 1062612826u, 0, SQRT_TOLERANCE, 0},
+{191, 1060487823u, 1057079837u, 1062712733u, 0, SQRT_TOLERANCE, 0},
+{192, 1060655596u, 3217432469u, 1062811940u, 0, SQRT_TOLERANCE, 0},
+{193, 1060823368u, 1079368611u, 1062910460u, 0, SQRT_TOLERANCE, 0},
+{194, 1060991140u, 3243343143u, 1063008307u, 0, SQRT_TOLERANCE, 0},
+{195, 1061158912u, 1041548088u, 1063105495u, 0, SQRT_TOLERANCE, 0},
+{196, 1061326684u, 1045807374u, 1063202038u, 0, SQRT_TOLERANCE, 0},
+{197, 1061494456u, 3212131720u, 1063297947u, 0, SQRT_TOLERANCE, 0},
+{198, 1061662228u, 1052187689u, 1063393236u, 0, SQRT_TOLERANCE, 0},
+{199, 1061830001u, 1102624859u, 1063487916u, 0, SQRT_TOLERANCE, 0},
+{200, 1061997773u, 3246176356u, 1063581998u, 0, SQRT_TOLERANCE, 0},
+{201, 1062165545u, 1051558014u, 1063675494u, 0, SQRT_TOLERANCE, 0},
+{202, 1062333317u, 3207725532u, 1063768415u, 0, SQRT_TOLERANCE, 0},
+{203, 1062501089u, 3190303581u, 1063860771u, 0, SQRT_TOLERANCE, 0},
+{204, 1062668861u, 3230415151u, 1063952572u, 0, SQRT_TOLERANCE, 0},
+{205, 1062836634u, 1090646554u, 1064043829u, 0, SQRT_TOLERANCE, 0},
+{206, 1063004406u, 1046063872u, 1064134550u, 0, SQRT_TOLERANCE, 0},
+{207, 1063172178u, 3194111199u, 1064224745u, 0, SQRT_TOLERANCE, 0},
+{208, 1063339950u, 1047020885u, 1064314424u, 0, SQRT_TOLERANCE, 0},
+{209, 1063507722u, 3193450280u, 1064403594u, 0, SQRT_TOLERANCE, 0},
+{210, 1063675494u, 3235452527u, 1064492265u, 0, SQRT_TOLERANCE, 0},
+{211, 1063843267u, 3219096387u, 1064580444u, 0, SQRT_TOLERANCE, 0},
+{212, 1064011039u, 3200792376u, 1064668140u, 0, SQRT_TOLERANCE, 0},
+{213, 1064178811u, 3237045253u, 1064755361u, 0, SQRT_TOLERANCE, 0},
+{214, 1064346583u, 3206926643u, 1064842114u, 0, SQRT_TOLERANCE, 0},
+{215, 1064514355u, 1085095743u, 1064928407u, 0, SQRT_TOLERANCE, 0},
+{216, 1064682127u, 1099828675u, 1065014247u, 0, SQRT_TOLERANCE, 0},
+{217, 1064849900u, 1102759382u, 1065099641u, 0, SQRT_TOLERANCE, 0},
+{218, 1065017672u, 1091945628u, 1065184596u, 0, SQRT_TOLERANCE, 0},
+{219, 1065185444u, 1096533424u, 1065269119u, 0, SQRT_TOLERANCE, 0},
+{220, 1065353216u, 3212698915u, 1065353216u, 0, SQRT_TOLERANCE, 0},
+{221, 1065437102u, 3229111426u, 1065395055u, 0, SQRT_TOLERANCE, 0},
+{222, 1065520988u, 1089760910u, 1065436687u, 0, SQRT_TOLERANCE, 0},
+{223, 1065604874u, 1075198900u, 1065478115u, 0, SQRT_TOLERANCE, 0},
+{224, 1065688760u, 1065221325u, 1065519343u, 0, SQRT_TOLERANCE, 0},
+{225, 1065772646u, 3235313361u, 1065560373u, 0, SQRT_TOLERANCE, 0},
+{226, 1065856532u, 1042055360u, 1065601209u, 0, SQRT_TOLERANCE, 0},
+{227, 1065940419u, 3194723421u, 1065641852u, 0, SQRT_TOLERANCE, 0},
+{228, 1066024305u, 3212424262u, 1065682305u, 0, SQRT_TOLERANCE, 0},
+{229, 1066108191u, 3241512456u, 1065722572u, 0, SQRT_TOLERANCE, 0},
+{230, 1066192077u, 3211544311u, 1065762654u, 0, SQRT_TOLERANCE, 0},
+{231, 1066275963u, 1058576726u, 1065802555u, 0, SQRT_TOLERANCE, 0},
+{232, 1066359849u, 3205004060u, 1065842276u, 0, SQRT_TOLERANCE, 0},
+{233, 1066443735u, 3223356436u, 1065881821u, 0, SQRT_TOLERANCE, 0},
+{234, 1066527621u, 1098306332u, 1065921190u, 0, SQRT_TOLERANCE, 0},
+{235, 1066611507u, 1091262633u, 1065960388u, 0, SQRT_TOLERANCE, 0},
+{236, 1066695393u, 3194927008u, 1065999415u, 0, SQRT_TOLERANCE, 0},
+{237, 1066779279u, 1066368383u, 1066038275u, 0, SQRT_TOLERANCE, 0},
+{238, 1066863165u, 1098487295u, 1066076969u, 0, SQRT_TOLERANCE, 0},
+{239, 1066947052u, 1070999426u, 1066115499u, 0, SQRT_TOLERANCE, 0},
+{240, 3234402267u, 1101098363u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{241, 3231108068u, 1078368488u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{242, 3226013659u, 3230316437u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{243, 3217625051u, 1079833442u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{244, 0u, 1052873711u, 0u, 0, SQRT_TOLERANCE, 0},
+{245, 1070141403u, 1085015978u, 1067478169u, 0, SQRT_TOLERANCE, 0},
+{246, 1078530011u, 1074309900u, 1071833029u, 0, SQRT_TOLERANCE, 0},
+{247, 1083624420u, 3228615456u, 1074458227u, 0, SQRT_TOLERANCE, 0},
+{248, 3253731328u, 3230392165u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{249, 3252840038u, 3238056647u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{250, 3251948749u, 1048120593u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{251, 3251057459u, 1086112947u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{252, 3250166170u, 1100880260u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{253, 3249274880u, 3232200256u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{254, 3248383590u, 1076097908u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{255, 3247492301u, 1064816262u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{256, 3246601011u, 1065280276u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{257, 3245028147u, 1078398157u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{258, 3243245568u, 1103272172u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{259, 3241462989u, 3210023352u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{260, 3239680410u, 1085153597u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{261, 3237792973u, 1042831668u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{262, 3234227814u, 1065483445u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{263, 3230662656u, 3222430705u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{264, 3224580915u, 1084451053u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{265, 3213675725u, 1092243422u, 2143289344u, EDOM, SQRT_TOLERANCE, 0},
+{266, 1058642330u, 1071545057u, 1061571576u, 0, SQRT_TOLERANCE, 0},
+{267, 1075000115u, 3241990046u, 1069686562u, 0, SQRT_TOLERANCE, 0},
+{268, 1082130432u, 1079333374u, 1073741824u, 0, SQRT_TOLERANCE, 0},
+{269, 1085695590u, 3242081486u, 1075366980u, 0, SQRT_TOLERANCE, 0},
+{270, 1089260749u, 1043425732u, 1076762956u, 0, SQRT_TOLERANCE, 0},
+{271, 1091672474u, 3211529757u, 1078005840u, 0, SQRT_TOLERANCE, 0},
+{272, 1093455053u, 3241441539u, 1079137105u, 0, SQRT_TOLERANCE, 0},
+{273, 1095237632u, 1074522705u, 1080182320u, 0, SQRT_TOLERANCE, 0},
+{274, 1097020211u, 1088658621u, 1081158565u, 0, SQRT_TOLERANCE, 0},
+{275, 1098802790u, 3224596567u, 1082077921u, 0, SQRT_TOLERANCE, 0},
+{276, 1099746509u, 1086207177u, 1082539870u, 0, SQRT_TOLERANCE, 0},
+{277, 1100637798u, 1079361728u, 1082954983u, 0, SQRT_TOLERANCE, 0},
+{278, 1101529088u, 1090937016u, 1083352182u, 0, SQRT_TOLERANCE, 0},
+{279, 1102420378u, 1086260896u, 1083733603u, 0, SQRT_TOLERANCE, 0},
+{280, 1103311667u, 3194387916u, 1084100991u, 0, SQRT_TOLERANCE, 0},
+{281, 1104202957u, 3216442625u, 1084455788u, 0, SQRT_TOLERANCE, 0},
+{282, 1105094246u, 1063475914u, 1084799206u, 0, SQRT_TOLERANCE, 0},
+{283, 1105985536u, 3236646101u, 1085132275u, 0, SQRT_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_SQRT_H multiple inclusion protection
+
+// EOF sqrtf.h
diff --git a/packages/language/c/libm/current/tests/vectors/tanf.c b/packages/language/c/libm/current/tests/vectors/tanf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/tanf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      tanf.c
+//
+//      Test of tanf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/tanf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(tanf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &tanf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &tanf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("tanf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("tanf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library tanf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "tanf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF tanf.c
diff --git a/packages/language/c/libm/current/tests/vectors/tanf.h b/packages/language/c/libm/current/tests/vectors/tanf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/tanf.h
@@ -0,0 +1,1232 @@
+#ifndef CYGONCE_LIBM_SCABNF_H
+#define CYGONCE_LIBM_SCABNF_H
+//===========================================================================
+//
+//      tanf.h
+//
+//      Test vectors for testing of tanf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/tanf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define TANF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t tanf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 0u, 3223625251u, 0, TANF_TOLERANCE, 0},
+{1, 3214430700u, 0u, 3223313815u, 0, TANF_TOLERANCE, 0},
+{2, 3214346813u, 0u, 3223017555u, 0, TANF_TOLERANCE, 0},
+{3, 3214262927u, 0u, 3222735341u, 0, TANF_TOLERANCE, 0},
+{4, 3214179041u, 0u, 3222466140u, 0, TANF_TOLERANCE, 0},
+{5, 3214095155u, 0u, 3222209023u, 0, TANF_TOLERANCE, 0},
+{6, 3214011269u, 0u, 3221963145u, 0, TANF_TOLERANCE, 0},
+{7, 3213927383u, 0u, 3221727740u, 0, TANF_TOLERANCE, 0},
+{8, 3213843497u, 0u, 3221502108u, 0, TANF_TOLERANCE, 0},
+{9, 3213759611u, 0u, 3221285611u, 0, TANF_TOLERANCE, 0},
+{10, 3213675725u, 0u, 3220929855u, 0, TANF_TOLERANCE, 0},
+{11, 3213591839u, 0u, 3220529989u, 0, TANF_TOLERANCE, 0},
+{12, 3213507953u, 0u, 3220145165u, 0, TANF_TOLERANCE, 0},
+{13, 3213424067u, 0u, 3219774482u, 0, TANF_TOLERANCE, 0},
+{14, 3213340180u, 0u, 3219417095u, 0, TANF_TOLERANCE, 0},
+{15, 3213256294u, 0u, 3219072244u, 0, TANF_TOLERANCE, 0},
+{16, 3213172408u, 0u, 3218739210u, 0, TANF_TOLERANCE, 0},
+{17, 3213088522u, 0u, 3218417335u, 0, TANF_TOLERANCE, 0},
+{18, 3213004636u, 0u, 3218106004u, 0, TANF_TOLERANCE, 0},
+{19, 3212920750u, 0u, 3217804648u, 0, TANF_TOLERANCE, 0},
+{20, 3212836864u, 0u, 3217512739u, 0, TANF_TOLERANCE, 0},
+{21, 3212669092u, 0u, 3217229784u, 0, TANF_TOLERANCE, 0},
+{22, 3212501320u, 0u, 3216955321u, 0, TANF_TOLERANCE, 0},
+{23, 3212333548u, 0u, 3216688923u, 0, TANF_TOLERANCE, 0},
+{24, 3212165775u, 0u, 3216430186u, 0, TANF_TOLERANCE, 0},
+{25, 3211998003u, 0u, 3216178740u, 0, TANF_TOLERANCE, 0},
+{26, 3211830231u, 0u, 3215934228u, 0, TANF_TOLERANCE, 0},
+{27, 3211662459u, 0u, 3215696321u, 0, TANF_TOLERANCE, 0},
+{28, 3211494687u, 0u, 3215464711u, 0, TANF_TOLERANCE, 0},
+{29, 3211326915u, 0u, 3215239105u, 0, TANF_TOLERANCE, 0},
+{30, 3211159142u, 0u, 3215019230u, 0, TANF_TOLERANCE, 0},
+{31, 3210991370u, 0u, 3214804827u, 0, TANF_TOLERANCE, 0},
+{32, 3210823598u, 0u, 3214595654u, 0, TANF_TOLERANCE, 0},
+{33, 3210655826u, 0u, 3214391483u, 0, TANF_TOLERANCE, 0},
+{34, 3210488054u, 0u, 3214192094u, 0, TANF_TOLERANCE, 0},
+{35, 3210320282u, 0u, 3213997284u, 0, TANF_TOLERANCE, 0},
+{36, 3210152509u, 0u, 3213806858u, 0, TANF_TOLERANCE, 0},
+{37, 3209984737u, 0u, 3213620637u, 0, TANF_TOLERANCE, 0},
+{38, 3209816965u, 0u, 3213438442u, 0, TANF_TOLERANCE, 0},
+{39, 3209649193u, 0u, 3213260113u, 0, TANF_TOLERANCE, 0},
+{40, 3209481421u, 0u, 3213085491u, 0, TANF_TOLERANCE, 0},
+{41, 3209313649u, 0u, 3212914427u, 0, TANF_TOLERANCE, 0},
+{42, 3209145876u, 0u, 3212656702u, 0, TANF_TOLERANCE, 0},
+{43, 3208978104u, 0u, 3212327983u, 0, TANF_TOLERANCE, 0},
+{44, 3208810332u, 0u, 3212005577u, 0, TANF_TOLERANCE, 0},
+{45, 3208642560u, 0u, 3211689243u, 0, TANF_TOLERANCE, 0},
+{46, 3208474788u, 0u, 3211378749u, 0, TANF_TOLERANCE, 0},
+{47, 3208307016u, 0u, 3211073873u, 0, TANF_TOLERANCE, 0},
+{48, 3208139244u, 0u, 3210774407u, 0, TANF_TOLERANCE, 0},
+{49, 3207971471u, 0u, 3210480145u, 0, TANF_TOLERANCE, 0},
+{50, 3207803699u, 0u, 3210190902u, 0, TANF_TOLERANCE, 0},
+{51, 3207635927u, 0u, 3209906490u, 0, TANF_TOLERANCE, 0},
+{52, 3207468155u, 0u, 3209626734u, 0, TANF_TOLERANCE, 0},
+{53, 3207300383u, 0u, 3209351468u, 0, TANF_TOLERANCE, 0},
+{54, 3207132611u, 0u, 3209080528u, 0, TANF_TOLERANCE, 0},
+{55, 3206964838u, 0u, 3208813761u, 0, TANF_TOLERANCE, 0},
+{56, 3206797066u, 0u, 3208551021u, 0, TANF_TOLERANCE, 0},
+{57, 3206629294u, 0u, 3208292164u, 0, TANF_TOLERANCE, 0},
+{58, 3206461522u, 0u, 3208037053u, 0, TANF_TOLERANCE, 0},
+{59, 3206293750u, 0u, 3207785562u, 0, TANF_TOLERANCE, 0},
+{60, 3206125978u, 0u, 3207537560u, 0, TANF_TOLERANCE, 0},
+{61, 3205958205u, 0u, 3207292928u, 0, TANF_TOLERANCE, 0},
+{62, 3205790433u, 0u, 3207051550u, 0, TANF_TOLERANCE, 0},
+{63, 3205622661u, 0u, 3206813316u, 0, TANF_TOLERANCE, 0},
+{64, 3205454889u, 0u, 3206578116u, 0, TANF_TOLERANCE, 0},
+{65, 3205287117u, 0u, 3206345847u, 0, TANF_TOLERANCE, 0},
+{66, 3205119345u, 0u, 3206116409u, 0, TANF_TOLERANCE, 0},
+{67, 3204951572u, 0u, 3205889704u, 0, TANF_TOLERANCE, 0},
+{68, 3204783800u, 0u, 3205665640u, 0, TANF_TOLERANCE, 0},
+{69, 3204616028u, 0u, 3205444129u, 0, TANF_TOLERANCE, 0},
+{70, 3204448256u, 0u, 3205225083u, 0, TANF_TOLERANCE, 0},
+{71, 3204112712u, 0u, 3205008416u, 0, TANF_TOLERANCE, 0},
+{72, 3203777167u, 0u, 3204794048u, 0, TANF_TOLERANCE, 0},
+{73, 3203441623u, 0u, 3204581902u, 0, TANF_TOLERANCE, 0},
+{74, 3203106079u, 0u, 3204295542u, 0, TANF_TOLERANCE, 0},
+{75, 3202770534u, 0u, 3203879679u, 0, TANF_TOLERANCE, 0},
+{76, 3202434990u, 0u, 3203467813u, 0, TANF_TOLERANCE, 0},
+{77, 3202099446u, 0u, 3203059808u, 0, TANF_TOLERANCE, 0},
+{78, 3201763901u, 0u, 3202655528u, 0, TANF_TOLERANCE, 0},
+{79, 3201428357u, 0u, 3202254843u, 0, TANF_TOLERANCE, 0},
+{80, 3201092813u, 0u, 3201857626u, 0, TANF_TOLERANCE, 0},
+{81, 3200757268u, 0u, 3201463754u, 0, TANF_TOLERANCE, 0},
+{82, 3200421724u, 0u, 3201073106u, 0, TANF_TOLERANCE, 0},
+{83, 3200086180u, 0u, 3200685568u, 0, TANF_TOLERANCE, 0},
+{84, 3199750636u, 0u, 3200301024u, 0, TANF_TOLERANCE, 0},
+{85, 3199415091u, 0u, 3199919364u, 0, TANF_TOLERANCE, 0},
+{86, 3199079547u, 0u, 3199540480u, 0, TANF_TOLERANCE, 0},
+{87, 3198744003u, 0u, 3199164268u, 0, TANF_TOLERANCE, 0},
+{88, 3198408458u, 0u, 3198790623u, 0, TANF_TOLERANCE, 0},
+{89, 3198072914u, 0u, 3198419447u, 0, TANF_TOLERANCE, 0},
+{90, 3197737370u, 0u, 3198050643u, 0, TANF_TOLERANCE, 0},
+{91, 3197401825u, 0u, 3197684111u, 0, TANF_TOLERANCE, 0},
+{92, 3197066281u, 0u, 3197319762u, 0, TANF_TOLERANCE, 0},
+{93, 3196730737u, 0u, 3196957502u, 0, TANF_TOLERANCE, 0},
+{94, 3196395192u, 0u, 3196597241u, 0, TANF_TOLERANCE, 0},
+{95, 3196059648u, 0u, 3196238893u, 0, TANF_TOLERANCE, 0},
+{96, 3195388559u, 0u, 3195705092u, 0, TANF_TOLERANCE, 0},
+{97, 3194717471u, 0u, 3194995527u, 0, TANF_TOLERANCE, 0},
+{98, 3194046382u, 0u, 3194289277u, 0, TANF_TOLERANCE, 0},
+{99, 3193375293u, 0u, 3193586179u, 0, TANF_TOLERANCE, 0},
+{100, 3192704205u, 0u, 3192886073u, 0, TANF_TOLERANCE, 0},
+{101, 3192033116u, 0u, 3192188798u, 0, TANF_TOLERANCE, 0},
+{102, 3191362028u, 0u, 3191494201u, 0, TANF_TOLERANCE, 0},
+{103, 3190690939u, 0u, 3190802126u, 0, TANF_TOLERANCE, 0},
+{104, 3190019850u, 0u, 3190112424u, 0, TANF_TOLERANCE, 0},
+{105, 3189348762u, 0u, 3189424945u, 0, TANF_TOLERANCE, 0},
+{106, 3188677673u, 0u, 3188739540u, 0, TANF_TOLERANCE, 0},
+{107, 3188006584u, 0u, 3188056065u, 0, TANF_TOLERANCE, 0},
+{108, 3186999951u, 0u, 3187077709u, 0, TANF_TOLERANCE, 0},
+{109, 3185657774u, 0u, 3185717611u, 0, TANF_TOLERANCE, 0},
+{110, 3184315597u, 0u, 3184360516u, 0, TANF_TOLERANCE, 0},
+{111, 3182973420u, 0u, 3183006141u, 0, TANF_TOLERANCE, 0},
+{112, 3181631242u, 0u, 3181654207u, 0, TANF_TOLERANCE, 0},
+{113, 3180289065u, 0u, 3180304441u, 0, TANF_TOLERANCE, 0},
+{114, 3178611343u, 0u, 3178630698u, 0, TANF_TOLERANCE, 0},
+{115, 3175926989u, 0u, 3175938185u, 0, TANF_TOLERANCE, 0},
+{116, 3173242634u, 0u, 3173248365u, 0, TANF_TOLERANCE, 0},
+{117, 3170222735u, 0u, 3170227569u, 0, TANF_TOLERANCE, 0},
+{118, 3164854026u, 0u, 3164855458u, 0, TANF_TOLERANCE, 0},
+{119, 3156465418u, 0u, 3156465776u, 0, TANF_TOLERANCE, 0},
+{120, 1008981770u, 0u, 1008982128u, 0, TANF_TOLERANCE, 0},
+{121, 1017370378u, 0u, 1017371810u, 0, TANF_TOLERANCE, 0},
+{122, 1022739087u, 0u, 1022743921u, 0, TANF_TOLERANCE, 0},
+{123, 1025758986u, 0u, 1025764717u, 0, TANF_TOLERANCE, 0},
+{124, 1028443341u, 0u, 1028454537u, 0, TANF_TOLERANCE, 0},
+{125, 1031127695u, 0u, 1031147050u, 0, TANF_TOLERANCE, 0},
+{126, 1032805417u, 0u, 1032820793u, 0, TANF_TOLERANCE, 0},
+{127, 1034147594u, 0u, 1034170559u, 0, TANF_TOLERANCE, 0},
+{128, 1035489772u, 0u, 1035522493u, 0, TANF_TOLERANCE, 0},
+{129, 1036831949u, 0u, 1036876868u, 0, TANF_TOLERANCE, 0},
+{130, 1038174126u, 0u, 1038233963u, 0, TANF_TOLERANCE, 0},
+{131, 1039516303u, 0u, 1039594061u, 0, TANF_TOLERANCE, 0},
+{132, 1040522936u, 0u, 1040572417u, 0, TANF_TOLERANCE, 0},
+{133, 1041194025u, 0u, 1041255892u, 0, TANF_TOLERANCE, 0},
+{134, 1041865114u, 0u, 1041941297u, 0, TANF_TOLERANCE, 0},
+{135, 1042536202u, 0u, 1042628776u, 0, TANF_TOLERANCE, 0},
+{136, 1043207291u, 0u, 1043318478u, 0, TANF_TOLERANCE, 0},
+{137, 1043878380u, 0u, 1044010553u, 0, TANF_TOLERANCE, 0},
+{138, 1044549468u, 0u, 1044705150u, 0, TANF_TOLERANCE, 0},
+{139, 1045220557u, 0u, 1045402425u, 0, TANF_TOLERANCE, 0},
+{140, 1045891645u, 0u, 1046102531u, 0, TANF_TOLERANCE, 0},
+{141, 1046562734u, 0u, 1046805629u, 0, TANF_TOLERANCE, 0},
+{142, 1047233823u, 0u, 1047511879u, 0, TANF_TOLERANCE, 0},
+{143, 1047904911u, 0u, 1048221444u, 0, TANF_TOLERANCE, 0},
+{144, 1048576000u, 0u, 1048755245u, 0, TANF_TOLERANCE, 0},
+{145, 1048911544u, 0u, 1049113593u, 0, TANF_TOLERANCE, 0},
+{146, 1049247089u, 0u, 1049473854u, 0, TANF_TOLERANCE, 0},
+{147, 1049582633u, 0u, 1049836114u, 0, TANF_TOLERANCE, 0},
+{148, 1049918177u, 0u, 1050200463u, 0, TANF_TOLERANCE, 0},
+{149, 1050253722u, 0u, 1050566995u, 0, TANF_TOLERANCE, 0},
+{150, 1050589266u, 0u, 1050935799u, 0, TANF_TOLERANCE, 0},
+{151, 1050924810u, 0u, 1051306975u, 0, TANF_TOLERANCE, 0},
+{152, 1051260355u, 0u, 1051680620u, 0, TANF_TOLERANCE, 0},
+{153, 1051595899u, 0u, 1052056832u, 0, TANF_TOLERANCE, 0},
+{154, 1051931443u, 0u, 1052435716u, 0, TANF_TOLERANCE, 0},
+{155, 1052266988u, 0u, 1052817376u, 0, TANF_TOLERANCE, 0},
+{156, 1052602532u, 0u, 1053201920u, 0, TANF_TOLERANCE, 0},
+{157, 1052938076u, 0u, 1053589458u, 0, TANF_TOLERANCE, 0},
+{158, 1053273620u, 0u, 1053980106u, 0, TANF_TOLERANCE, 0},
+{159, 1053609165u, 0u, 1054373978u, 0, TANF_TOLERANCE, 0},
+{160, 1053944709u, 0u, 1054771195u, 0, TANF_TOLERANCE, 0},
+{161, 1054280253u, 0u, 1055171880u, 0, TANF_TOLERANCE, 0},
+{162, 1054615798u, 0u, 1055576160u, 0, TANF_TOLERANCE, 0},
+{163, 1054951342u, 0u, 1055984165u, 0, TANF_TOLERANCE, 0},
+{164, 1055286886u, 0u, 1056396031u, 0, TANF_TOLERANCE, 0},
+{165, 1055622431u, 0u, 1056811894u, 0, TANF_TOLERANCE, 0},
+{166, 1055957975u, 0u, 1057098254u, 0, TANF_TOLERANCE, 0},
+{167, 1056293519u, 0u, 1057310400u, 0, TANF_TOLERANCE, 0},
+{168, 1056629064u, 0u, 1057524768u, 0, TANF_TOLERANCE, 0},
+{169, 1056964608u, 0u, 1057741435u, 0, TANF_TOLERANCE, 0},
+{170, 1057132380u, 0u, 1057960481u, 0, TANF_TOLERANCE, 0},
+{171, 1057300152u, 0u, 1058181992u, 0, TANF_TOLERANCE, 0},
+{172, 1057467924u, 0u, 1058406056u, 0, TANF_TOLERANCE, 0},
+{173, 1057635697u, 0u, 1058632761u, 0, TANF_TOLERANCE, 0},
+{174, 1057803469u, 0u, 1058862199u, 0, TANF_TOLERANCE, 0},
+{175, 1057971241u, 0u, 1059094468u, 0, TANF_TOLERANCE, 0},
+{176, 1058139013u, 0u, 1059329668u, 0, TANF_TOLERANCE, 0},
+{177, 1058306785u, 0u, 1059567902u, 0, TANF_TOLERANCE, 0},
+{178, 1058474557u, 0u, 1059809280u, 0, TANF_TOLERANCE, 0},
+{179, 1058642330u, 0u, 1060053912u, 0, TANF_TOLERANCE, 0},
+{180, 1058810102u, 0u, 1060301914u, 0, TANF_TOLERANCE, 0},
+{181, 1058977874u, 0u, 1060553405u, 0, TANF_TOLERANCE, 0},
+{182, 1059145646u, 0u, 1060808516u, 0, TANF_TOLERANCE, 0},
+{183, 1059313418u, 0u, 1061067373u, 0, TANF_TOLERANCE, 0},
+{184, 1059481190u, 0u, 1061330113u, 0, TANF_TOLERANCE, 0},
+{185, 1059648963u, 0u, 1061596880u, 0, TANF_TOLERANCE, 0},
+{186, 1059816735u, 0u, 1061867820u, 0, TANF_TOLERANCE, 0},
+{187, 1059984507u, 0u, 1062143086u, 0, TANF_TOLERANCE, 0},
+{188, 1060152279u, 0u, 1062422842u, 0, TANF_TOLERANCE, 0},
+{189, 1060320051u, 0u, 1062707254u, 0, TANF_TOLERANCE, 0},
+{190, 1060487823u, 0u, 1062996497u, 0, TANF_TOLERANCE, 0},
+{191, 1060655596u, 0u, 1063290759u, 0, TANF_TOLERANCE, 0},
+{192, 1060823368u, 0u, 1063590225u, 0, TANF_TOLERANCE, 0},
+{193, 1060991140u, 0u, 1063895101u, 0, TANF_TOLERANCE, 0},
+{194, 1061158912u, 0u, 1064205595u, 0, TANF_TOLERANCE, 0},
+{195, 1061326684u, 0u, 1064521929u, 0, TANF_TOLERANCE, 0},
+{196, 1061494456u, 0u, 1064844335u, 0, TANF_TOLERANCE, 0},
+{197, 1061662228u, 0u, 1065173054u, 0, TANF_TOLERANCE, 0},
+{198, 1061830001u, 0u, 1065430779u, 0, TANF_TOLERANCE, 0},
+{199, 1061997773u, 0u, 1065601843u, 0, TANF_TOLERANCE, 0},
+{200, 1062165545u, 0u, 1065776465u, 0, TANF_TOLERANCE, 0},
+{201, 1062333317u, 0u, 1065954794u, 0, TANF_TOLERANCE, 0},
+{202, 1062501089u, 0u, 1066136989u, 0, TANF_TOLERANCE, 0},
+{203, 1062668861u, 0u, 1066323210u, 0, TANF_TOLERANCE, 0},
+{204, 1062836634u, 0u, 1066513636u, 0, TANF_TOLERANCE, 0},
+{205, 1063004406u, 0u, 1066708446u, 0, TANF_TOLERANCE, 0},
+{206, 1063172178u, 0u, 1066907835u, 0, TANF_TOLERANCE, 0},
+{207, 1063339950u, 0u, 1067112006u, 0, TANF_TOLERANCE, 0},
+{208, 1063507722u, 0u, 1067321179u, 0, TANF_TOLERANCE, 0},
+{209, 1063675494u, 0u, 1067535582u, 0, TANF_TOLERANCE, 0},
+{210, 1063843267u, 0u, 1067755457u, 0, TANF_TOLERANCE, 0},
+{211, 1064011039u, 0u, 1067981063u, 0, TANF_TOLERANCE, 0},
+{212, 1064178811u, 0u, 1068212673u, 0, TANF_TOLERANCE, 0},
+{213, 1064346583u, 0u, 1068450580u, 0, TANF_TOLERANCE, 0},
+{214, 1064514355u, 0u, 1068695092u, 0, TANF_TOLERANCE, 0},
+{215, 1064682127u, 0u, 1068946538u, 0, TANF_TOLERANCE, 0},
+{216, 1064849900u, 0u, 1069205275u, 0, TANF_TOLERANCE, 0},
+{217, 1065017672u, 0u, 1069471673u, 0, TANF_TOLERANCE, 0},
+{218, 1065185444u, 0u, 1069746136u, 0, TANF_TOLERANCE, 0},
+{219, 1065353216u, 0u, 1070029091u, 0, TANF_TOLERANCE, 0},
+{220, 1065437102u, 0u, 1070321000u, 0, TANF_TOLERANCE, 0},
+{221, 1065520988u, 0u, 1070622356u, 0, TANF_TOLERANCE, 0},
+{222, 1065604874u, 0u, 1070933687u, 0, TANF_TOLERANCE, 0},
+{223, 1065688760u, 0u, 1071255562u, 0, TANF_TOLERANCE, 0},
+{224, 1065772646u, 0u, 1071588596u, 0, TANF_TOLERANCE, 0},
+{225, 1065856532u, 0u, 1071933447u, 0, TANF_TOLERANCE, 0},
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+{1133, 3098997418u, 0u, 3098997418u, 0, TANF_TOLERANCE, 0},
+{1134, 3282212423u, 0u, 1112557809u, 0, TANF_TOLERANCE, 0},
+{1135, 3352293320u, 4294967278u, 3226389131u, 0, TANF_TOLERANCE, 0},
+{1136, 3296358441u, 0u, 1054993302u, 0, TANF_TOLERANCE, 0},
+{1137, 1197828352u, 4294967281u, 1032407318u, 0, TANF_TOLERANCE, 0},
+{1138, 3340510371u, 0u, 1069696271u, 0, TANF_TOLERANCE, 0},
+{1139, 1127109339u, 4294570975u, 1105605562u, 0, TANF_TOLERANCE, 0},
+{1140, 909467381u, 1001724u, 909467381u, 0, TANF_TOLERANCE, 0},
+{1141, 1200599955u, 0u, 3216216244u, 0, TANF_TOLERANCE, 0},
+{1142, 962230977u, 0u, 962230977u, 0, TANF_TOLERANCE, 0},
+{1143, 3192887808u, 0u, 3193077326u, 0, TANF_TOLERANCE, 0},
+{1144, 3237183876u, 0u, 3229633984u, 0, TANF_TOLERANCE, 0},
+{1145, 939285924u, 0u, 939285924u, 0, TANF_TOLERANCE, 0},
+{1146, 944050180u, 3871652128u, 944050180u, 0, TANF_TOLERANCE, 0},
+{1147, 3058135703u, 0u, 3058135703u, 0, TANF_TOLERANCE, 0},
+{1148, 3480592662u, 4294967238u, 1058275636u, 0, TANF_TOLERANCE, 0},
+{1149, 3061939312u, 4294967125u, 3061939312u, 0, TANF_TOLERANCE, 0},
+{1150, 1003299981u, 0u, 1003300157u, 0, TANF_TOLERANCE, 0},
+{1151, 1155775526u, 7150230u, 3195997040u, 0, TANF_TOLERANCE, 0},
+{1152, 1234491880u, 4283784819u, 3230107658u, 0, TANF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_SCABNF_H multiple inclusion protection
+
+// EOF tanf.h
diff --git a/packages/language/c/libm/current/tests/vectors/tanhf.c b/packages/language/c/libm/current/tests/vectors/tanhf.c
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/tanhf.c
@@ -0,0 +1,115 @@
+//===========================================================================
+//
+//      tanhf.c
+//
+//      Test of tanhf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+// Declarations for test system:
+//
+// TESTCASE_TYPE=CYG_TEST_MODULE
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include <cyg/infra/testcase.h>    // Test infrastructure
+#include <math.h>                  // Header for this package
+#include <sys/ieeefp.h>            // Cyg_libm_ieee_float_shape_type
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#include "vectors/tanhf.h"
+
+// FUNCTIONS
+
+static void
+test( CYG_ADDRWORD data )
+{
+    cyg_ucount32 vec_size;
+    cyg_bool ret;
+
+    vec_size = sizeof(tanhf_vec) / sizeof(Cyg_libm_test_float_vec_t);
+    ret = doTestVecFloat( (CYG_ADDRWORD) &tanhf, CYG_LIBM_TEST_VEC_FLOAT,
+                     CYG_LIBM_TEST_VEC_NONE, CYG_LIBM_TEST_VEC_FLOAT,
+                     &tanhf_vec[0], vec_size );
+
+    if (ret==true)
+    {
+        CYG_TEST_PASS("tanhf() is stable");
+    } // if
+    else
+    {
+        CYG_TEST_FAIL("tanhf() failed tests");
+    } // else
+
+    CYG_TEST_FINISH("Finished tests from testcase " __FILE__ " for Math "
+                    "library tanhf() function");
+} // test()
+
+
+int
+main(int argc, char *argv[])
+{
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Starting tests from testcase " __FILE__ " for Math library "
+                  "tanhf() function");
+
+    START_TEST( test );
+
+    CYG_TEST_PASS_FINISH("Testing is not applicable to this configuration");
+
+} // main()
+
+
+// EOF tanhf.c
diff --git a/packages/language/c/libm/current/tests/vectors/tanhf.h b/packages/language/c/libm/current/tests/vectors/tanhf.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/tanhf.h
@@ -0,0 +1,1234 @@
+#ifndef CYGONCE_LIBM_SCABNF_H
+#define CYGONCE_LIBM_SCABNF_H
+//===========================================================================
+//
+//      tanhf.h
+//
+//      Test vectors for testing of tanhf() math library function
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):
+// Contributors:  visar, ilijak
+// Date:        1998-02-13
+// Purpose:
+// Description:
+// Usage:       #include "vectors/tanhf.h"
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>   // Configuration header
+
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>    // Common type definitions and support
+#include "vectors/vector_support_float.h"// extra support for math tests
+
+#define TANHF_TOLERANCE 1.0E-04
+
+static const Cyg_libm_test_float_vec_t tanhf_vec[] = {
+
+// AUTOMATICALLY GENERATED VECTORS START
+
+{0, 3214514586u, 0u, 3210046052u, 0, TANHF_TOLERANCE, 0},
+{1, 3214430700u, 0u, 3209994449u, 0, TANHF_TOLERANCE, 0},
+{2, 3214346813u, 0u, 3209941982u, 0, TANHF_TOLERANCE, 0},
+{3, 3214262927u, 0u, 3209888640u, 0, TANHF_TOLERANCE, 0},
+{4, 3214179041u, 0u, 3209834411u, 0, TANHF_TOLERANCE, 0},
+{5, 3214095155u, 0u, 3209779285u, 0, TANHF_TOLERANCE, 0},
+{6, 3214011269u, 0u, 3209723249u, 0, TANHF_TOLERANCE, 0},
+{7, 3213927383u, 0u, 3209666293u, 0, TANHF_TOLERANCE, 0},
+{8, 3213843497u, 0u, 3209608406u, 0, TANHF_TOLERANCE, 0},
+{9, 3213759611u, 0u, 3209549577u, 0, TANHF_TOLERANCE, 0},
+{10, 3213675725u, 0u, 3209489793u, 0, TANHF_TOLERANCE, 0},
+{11, 3213591839u, 0u, 3209429045u, 0, TANHF_TOLERANCE, 0},
+{12, 3213507953u, 0u, 3209367321u, 0, TANHF_TOLERANCE, 0},
+{13, 3213424067u, 0u, 3209304610u, 0, TANHF_TOLERANCE, 0},
+{14, 3213340180u, 0u, 3209240900u, 0, TANHF_TOLERANCE, 0},
+{15, 3213256294u, 0u, 3209176182u, 0, TANHF_TOLERANCE, 0},
+{16, 3213172408u, 0u, 3209110444u, 0, TANHF_TOLERANCE, 0},
+{17, 3213088522u, 0u, 3209043675u, 0, TANHF_TOLERANCE, 0},
+{18, 3213004636u, 0u, 3208975865u, 0, TANHF_TOLERANCE, 0},
+{19, 3212920750u, 0u, 3208907003u, 0, TANHF_TOLERANCE, 0},
+{20, 3212836864u, 0u, 3208837078u, 0, TANHF_TOLERANCE, 0},
+{21, 3212669092u, 0u, 3208766079u, 0, TANHF_TOLERANCE, 0},
+{22, 3212501320u, 0u, 3208693997u, 0, TANHF_TOLERANCE, 0},
+{23, 3212333548u, 0u, 3208620822u, 0, TANHF_TOLERANCE, 0},
+{24, 3212165775u, 0u, 3208546542u, 0, TANHF_TOLERANCE, 0},
+{25, 3211998003u, 0u, 3208471148u, 0, TANHF_TOLERANCE, 0},
+{26, 3211830231u, 0u, 3208394631u, 0, TANHF_TOLERANCE, 0},
+{27, 3211662459u, 0u, 3208316980u, 0, TANHF_TOLERANCE, 0},
+{28, 3211494687u, 0u, 3208238186u, 0, TANHF_TOLERANCE, 0},
+{29, 3211326915u, 0u, 3208158240u, 0, TANHF_TOLERANCE, 0},
+{30, 3211159142u, 0u, 3208077132u, 0, TANHF_TOLERANCE, 0},
+{31, 3210991370u, 0u, 3207994854u, 0, TANHF_TOLERANCE, 0},
+{32, 3210823598u, 0u, 3207911397u, 0, TANHF_TOLERANCE, 0},
+{33, 3210655826u, 0u, 3207826753u, 0, TANHF_TOLERANCE, 0},
+{34, 3210488054u, 0u, 3207740913u, 0, TANHF_TOLERANCE, 0},
+{35, 3210320282u, 0u, 3207653870u, 0, TANHF_TOLERANCE, 0},
+{36, 3210152509u, 0u, 3207565615u, 0, TANHF_TOLERANCE, 0},
+{37, 3209984737u, 0u, 3207476141u, 0, TANHF_TOLERANCE, 0},
+{38, 3209816965u, 0u, 3207385441u, 0, TANHF_TOLERANCE, 0},
+{39, 3209649193u, 0u, 3207293508u, 0, TANHF_TOLERANCE, 0},
+{40, 3209481421u, 0u, 3207200336u, 0, TANHF_TOLERANCE, 0},
+{41, 3209313649u, 0u, 3207105919u, 0, TANHF_TOLERANCE, 0},
+{42, 3209145876u, 0u, 3207010249u, 0, TANHF_TOLERANCE, 0},
+{43, 3208978104u, 0u, 3206913323u, 0, TANHF_TOLERANCE, 0},
+{44, 3208810332u, 0u, 3206815135u, 0, TANHF_TOLERANCE, 0},
+{45, 3208642560u, 0u, 3206715679u, 0, TANHF_TOLERANCE, 0},
+{46, 3208474788u, 0u, 3206614952u, 0, TANHF_TOLERANCE, 0},
+{47, 3208307016u, 0u, 3206512950u, 0, TANHF_TOLERANCE, 0},
+{48, 3208139244u, 0u, 3206409669u, 0, TANHF_TOLERANCE, 0},
+{49, 3207971471u, 0u, 3206305105u, 0, TANHF_TOLERANCE, 0},
+{50, 3207803699u, 0u, 3206199257u, 0, TANHF_TOLERANCE, 0},
+{51, 3207635927u, 0u, 3206092121u, 0, TANHF_TOLERANCE, 0},
+{52, 3207468155u, 0u, 3205983697u, 0, TANHF_TOLERANCE, 0},
+{53, 3207300383u, 0u, 3205873982u, 0, TANHF_TOLERANCE, 0},
+{54, 3207132611u, 0u, 3205762976u, 0, TANHF_TOLERANCE, 0},
+{55, 3206964838u, 0u, 3205650678u, 0, TANHF_TOLERANCE, 0},
+{56, 3206797066u, 0u, 3205537090u, 0, TANHF_TOLERANCE, 0},
+{57, 3206629294u, 0u, 3205422211u, 0, TANHF_TOLERANCE, 0},
+{58, 3206461522u, 0u, 3205306042u, 0, TANHF_TOLERANCE, 0},
+{59, 3206293750u, 0u, 3205188586u, 0, TANHF_TOLERANCE, 0},
+{60, 3206125978u, 0u, 3205069845u, 0, TANHF_TOLERANCE, 0},
+{61, 3205958205u, 0u, 3204949821u, 0, TANHF_TOLERANCE, 0},
+{62, 3205790433u, 0u, 3204828519u, 0, TANHF_TOLERANCE, 0},
+{63, 3205622661u, 0u, 3204705942u, 0, TANHF_TOLERANCE, 0},
+{64, 3205454889u, 0u, 3204582095u, 0, TANHF_TOLERANCE, 0},
+{65, 3205287117u, 0u, 3204456984u, 0, TANHF_TOLERANCE, 0},
+{66, 3205119345u, 0u, 3204212972u, 0, TANHF_TOLERANCE, 0},
+{67, 3204951572u, 0u, 3203957726u, 0, TANHF_TOLERANCE, 0},
+{68, 3204783800u, 0u, 3203699992u, 0, TANHF_TOLERANCE, 0},
+{69, 3204616028u, 0u, 3203439784u, 0, TANHF_TOLERANCE, 0},
+{70, 3204448256u, 0u, 3203177119u, 0, TANHF_TOLERANCE, 0},
+{71, 3204112712u, 0u, 3202912015u, 0, TANHF_TOLERANCE, 0},
+{72, 3203777167u, 0u, 3202644491u, 0, TANHF_TOLERANCE, 0},
+{73, 3203441623u, 0u, 3202374569u, 0, TANHF_TOLERANCE, 0},
+{74, 3203106079u, 0u, 3202102272u, 0, TANHF_TOLERANCE, 0},
+{75, 3202770534u, 0u, 3201827621u, 0, TANHF_TOLERANCE, 0},
+{76, 3202434990u, 0u, 3201550644u, 0, TANHF_TOLERANCE, 0},
+{77, 3202099446u, 0u, 3201271366u, 0, TANHF_TOLERANCE, 0},
+{78, 3201763901u, 0u, 3200989815u, 0, TANHF_TOLERANCE, 0},
+{79, 3201428357u, 0u, 3200706020u, 0, TANHF_TOLERANCE, 0},
+{80, 3201092813u, 0u, 3200420012u, 0, TANHF_TOLERANCE, 0},
+{81, 3200757268u, 0u, 3200131821u, 0, TANHF_TOLERANCE, 0},
+{82, 3200421724u, 0u, 3199841483u, 0, TANHF_TOLERANCE, 0},
+{83, 3200086180u, 0u, 3199549031u, 0, TANHF_TOLERANCE, 0},
+{84, 3199750636u, 0u, 3199254501u, 0, TANHF_TOLERANCE, 0},
+{85, 3199415091u, 0u, 3198957930u, 0, TANHF_TOLERANCE, 0},
+{86, 3199079547u, 0u, 3198659358u, 0, TANHF_TOLERANCE, 0},
+{87, 3198744003u, 0u, 3198358824u, 0, TANHF_TOLERANCE, 0},
+{88, 3198408458u, 0u, 3198056369u, 0, TANHF_TOLERANCE, 0},
+{89, 3198072914u, 0u, 3197752036u, 0, TANHF_TOLERANCE, 0},
+{90, 3197737370u, 0u, 3197445870u, 0, TANHF_TOLERANCE, 0},
+{91, 3197401825u, 0u, 3197137913u, 0, TANHF_TOLERANCE, 0},
+{92, 3197066281u, 0u, 3196828215u, 0, TANHF_TOLERANCE, 0},
+{93, 3196730737u, 0u, 3196516822u, 0, TANHF_TOLERANCE, 0},
+{94, 3196395192u, 0u, 3196203782u, 0, TANHF_TOLERANCE, 0},
+{95, 3196059648u, 0u, 3195718645u, 0, TANHF_TOLERANCE, 0},
+{96, 3195388559u, 0u, 3195086284u, 0, TANHF_TOLERANCE, 0},
+{97, 3194717471u, 0u, 3194450938u, 0, TANHF_TOLERANCE, 0},
+{98, 3194046382u, 0u, 3193812713u, 0, TANHF_TOLERANCE, 0},
+{99, 3193375293u, 0u, 3193171718u, 0, TANHF_TOLERANCE, 0},
+{100, 3192704205u, 0u, 3192528066u, 0, TANHF_TOLERANCE, 0},
+{101, 3192033116u, 0u, 3191881866u, 0, TANHF_TOLERANCE, 0},
+{102, 3191362028u, 0u, 3191233237u, 0, TANHF_TOLERANCE, 0},
+{103, 3190690939u, 0u, 3190582293u, 0, TANHF_TOLERANCE, 0},
+{104, 3190019850u, 0u, 3189929153u, 0, TANHF_TOLERANCE, 0},
+{105, 3189348762u, 0u, 3189273938u, 0, TANHF_TOLERANCE, 0},
+{106, 3188677673u, 0u, 3188616768u, 0, TANHF_TOLERANCE, 0},
+{107, 3188006584u, 0u, 3187957768u, 0, TANHF_TOLERANCE, 0},
+{108, 3186999951u, 0u, 3186923084u, 0, TANHF_TOLERANCE, 0},
+{109, 3185657774u, 0u, 3185598513u, 0, TANHF_TOLERANCE, 0},
+{110, 3184315597u, 0u, 3184271036u, 0, TANHF_TOLERANCE, 0},
+{111, 3182973420u, 0u, 3182940910u, 0, TANHF_TOLERANCE, 0},
+{112, 3181631242u, 0u, 3181608394u, 0, TANHF_TOLERANCE, 0},
+{113, 3180289065u, 0u, 3180273749u, 0, TANHF_TOLERANCE, 0},
+{114, 3178611343u, 0u, 3178592043u, 0, TANHF_TOLERANCE, 0},
+{115, 3175926989u, 0u, 3175915815u, 0, TANHF_TOLERANCE, 0},
+{116, 3173242634u, 0u, 3173236911u, 0, TANHF_TOLERANCE, 0},
+{117, 3170222735u, 0u, 3170217905u, 0, TANHF_TOLERANCE, 0},
+{118, 3164854026u, 0u, 3164852595u, 0, TANHF_TOLERANCE, 0},
+{119, 3156465418u, 0u, 3156465060u, 0, TANHF_TOLERANCE, 0},
+{120, 1008981770u, 0u, 1008981412u, 0, TANHF_TOLERANCE, 0},
+{121, 1017370378u, 0u, 1017368947u, 0, TANHF_TOLERANCE, 0},
+{122, 1022739087u, 0u, 1022734257u, 0, TANHF_TOLERANCE, 0},
+{123, 1025758986u, 0u, 1025753263u, 0, TANHF_TOLERANCE, 0},
+{124, 1028443341u, 0u, 1028432167u, 0, TANHF_TOLERANCE, 0},
+{125, 1031127695u, 0u, 1031108395u, 0, TANHF_TOLERANCE, 0},
+{126, 1032805417u, 0u, 1032790101u, 0, TANHF_TOLERANCE, 0},
+{127, 1034147594u, 0u, 1034124746u, 0, TANHF_TOLERANCE, 0},
+{128, 1035489772u, 0u, 1035457262u, 0, TANHF_TOLERANCE, 0},
+{129, 1036831949u, 0u, 1036787388u, 0, TANHF_TOLERANCE, 0},
+{130, 1038174126u, 0u, 1038114865u, 0, TANHF_TOLERANCE, 0},
+{131, 1039516303u, 0u, 1039439436u, 0, TANHF_TOLERANCE, 0},
+{132, 1040522936u, 0u, 1040474120u, 0, TANHF_TOLERANCE, 0},
+{133, 1041194025u, 0u, 1041133120u, 0, TANHF_TOLERANCE, 0},
+{134, 1041865114u, 0u, 1041790290u, 0, TANHF_TOLERANCE, 0},
+{135, 1042536202u, 0u, 1042445505u, 0, TANHF_TOLERANCE, 0},
+{136, 1043207291u, 0u, 1043098645u, 0, TANHF_TOLERANCE, 0},
+{137, 1043878380u, 0u, 1043749589u, 0, TANHF_TOLERANCE, 0},
+{138, 1044549468u, 0u, 1044398218u, 0, TANHF_TOLERANCE, 0},
+{139, 1045220557u, 0u, 1045044418u, 0, TANHF_TOLERANCE, 0},
+{140, 1045891645u, 0u, 1045688070u, 0, TANHF_TOLERANCE, 0},
+{141, 1046562734u, 0u, 1046329065u, 0, TANHF_TOLERANCE, 0},
+{142, 1047233823u, 0u, 1046967290u, 0, TANHF_TOLERANCE, 0},
+{143, 1047904911u, 0u, 1047602636u, 0, TANHF_TOLERANCE, 0},
+{144, 1048576000u, 0u, 1048234997u, 0, TANHF_TOLERANCE, 0},
+{145, 1048911544u, 0u, 1048720134u, 0, TANHF_TOLERANCE, 0},
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+{1052, 3207056527u, 4293469023u, 3205712210u, 0, TANHF_TOLERANCE, 0},
+{1053, 1284174954u, 4180334232u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1054, 3156081645u, 4294964338u, 3156081324u, 0, TANHF_TOLERANCE, 0},
+{1055, 1063693032u, 0u, 1060602017u, 0, TANHF_TOLERANCE, 0},
+{1056, 3036026175u, 4845007u, 3036026175u, 0, TANHF_TOLERANCE, 0},
+{1057, 1102631663u, 4290881696u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1058, 968803479u, 0u, 968803478u, 0, TANHF_TOLERANCE, 0},
+{1059, 3273080388u, 0u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1060, 1172529774u, 4294966405u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1061, 1306695905u, 147733664u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1062, 1003649752u, 338518u, 1003649562u, 0, TANHF_TOLERANCE, 0},
+{1063, 1078478376u, 2364151808u, 1065289116u, 0, TANHF_TOLERANCE, 0},
+{1064, 3158855023u, 0u, 3158854369u, 0, TANHF_TOLERANCE, 0},
+{1065, 1165177679u, 4294967097u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1066, 3403009513u, 4293749042u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1067, 952348506u, 4294108410u, 952348506u, 0, TANHF_TOLERANCE, 0},
+{1068, 1222777442u, 153u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1069, 1325324763u, 0u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1070, 3363524213u, 0u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1071, 1158950321u, 1u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1072, 903129873u, 4272788450u, 903129873u, 0, TANHF_TOLERANCE, 0},
+{1073, 3078339944u, 0u, 3078339944u, 0, TANHF_TOLERANCE, 0},
+{1074, 1208345407u, 6333643u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1075, 1258634105u, 3575206u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1076, 1248478509u, 102613680u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1077, 1153863988u, 4229464460u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1078, 1235620969u, 0u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1079, 1097120930u, 4294967294u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1080, 3469778622u, 70286u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1081, 1147712200u, 0u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1082, 1124721745u, 0u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1083, 3261744304u, 0u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1084, 1064922416u, 1518435840u, 1061168937u, 0, TANHF_TOLERANCE, 0},
+{1085, 3303160152u, 0u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1086, 1315090496u, 4294967183u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1087, 3230403187u, 1820050432u, 3212831561u, 0, TANHF_TOLERANCE, 0},
+{1088, 1335399673u, 0u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1089, 1072458508u, 4294404660u, 1064538920u, 0, TANHF_TOLERANCE, 0},
+{1090, 3303015249u, 0u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1091, 3252139741u, 0u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1092, 3468519966u, 0u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1093, 1006231203u, 0u, 1006230886u, 0, TANHF_TOLERANCE, 0},
+{1094, 951554138u, 0u, 951554138u, 0, TANHF_TOLERANCE, 0},
+{1095, 942046828u, 0u, 942046828u, 0, TANHF_TOLERANCE, 0},
+{1096, 3319723279u, 4277552160u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1097, 3255104167u, 0u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1098, 1155477903u, 0u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1099, 3273889176u, 0u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1100, 3237813668u, 4133749200u, 3212836859u, 0, TANHF_TOLERANCE, 0},
+{1101, 1228207362u, 0u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1102, 975349337u, 748694784u, 975349336u, 0, TANHF_TOLERANCE, 0},
+{1103, 1290175785u, 0u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1104, 981908840u, 4294962938u, 981908837u, 0, TANHF_TOLERANCE, 0},
+{1105, 941187647u, 33u, 941187647u, 0, TANHF_TOLERANCE, 0},
+{1106, 1214223128u, 4294967293u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1107, 3422922584u, 6u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1108, 1315857601u, 1055172096u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1109, 3453226030u, 4294967291u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1110, 1078359574u, 0u, 1065285387u, 0, TANHF_TOLERANCE, 0},
+{1111, 1029557624u, 4294965511u, 1029543432u, 0, TANHF_TOLERANCE, 0},
+{1112, 1207675424u, 0u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1113, 1028355074u, 4113313408u, 1028344119u, 0, TANHF_TOLERANCE, 0},
+{1114, 3119299090u, 24787u, 3119299089u, 0, TANHF_TOLERANCE, 0},
+{1115, 1248421894u, 4294582111u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1116, 3353251994u, 12u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1117, 876926659u, 4294966792u, 876926659u, 0, TANHF_TOLERANCE, 0},
+{1118, 1076752219u, 0u, 1065207581u, 0, TANHF_TOLERANCE, 0},
+{1119, 3388531942u, 0u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1120, 1273395082u, 0u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1121, 3385588183u, 4294967251u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1122, 3192315328u, 4294966714u, 3192153914u, 0, TANHF_TOLERANCE, 0},
+{1123, 3441804648u, 4294967121u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1124, 3392827417u, 45125368u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1125, 1161241793u, 2814016256u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1126, 3034494183u, 0u, 3034494183u, 0, TANHF_TOLERANCE, 0},
+{1127, 1171318485u, 4294306215u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1128, 3047748143u, 0u, 3047748143u, 0, TANHF_TOLERANCE, 0},
+{1129, 1001216371u, 0u, 1001216265u, 0, TANHF_TOLERANCE, 0},
+{1130, 912515889u, 2u, 912515889u, 0, TANHF_TOLERANCE, 0},
+{1131, 3391452505u, 0u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1132, 3249603369u, 0u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1133, 1220264047u, 0u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1134, 3169816394u, 0u, 3169811920u, 0, TANHF_TOLERANCE, 0},
+{1135, 3098997418u, 0u, 3098997418u, 0, TANHF_TOLERANCE, 0},
+{1136, 3282212423u, 0u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1137, 3352293320u, 4294967278u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1138, 3296358441u, 0u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1139, 1197828352u, 4294967281u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1140, 3340510371u, 0u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1141, 1127109339u, 4294570975u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1142, 909467381u, 1001724u, 909467381u, 0, TANHF_TOLERANCE, 0},
+{1143, 1200599955u, 0u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1144, 962230977u, 0u, 962230977u, 0, TANHF_TOLERANCE, 0},
+{1145, 3192887808u, 0u, 3192704420u, 0, TANHF_TOLERANCE, 0},
+{1146, 3237183876u, 0u, 3212836856u, 0, TANHF_TOLERANCE, 0},
+{1147, 939285924u, 0u, 939285924u, 0, TANHF_TOLERANCE, 0},
+{1148, 944050180u, 3871652128u, 944050180u, 0, TANHF_TOLERANCE, 0},
+{1149, 3058135703u, 0u, 3058135703u, 0, TANHF_TOLERANCE, 0},
+{1150, 3480592662u, 4294967238u, 3212836864u, 0, TANHF_TOLERANCE, 0},
+{1151, 3061939312u, 4294967125u, 3061939312u, 0, TANHF_TOLERANCE, 0},
+{1152, 1003299981u, 0u, 1003299805u, 0, TANHF_TOLERANCE, 0},
+{1153, 1155775526u, 7150230u, 1065353216u, 0, TANHF_TOLERANCE, 0},
+{1154, 1234491880u, 4283784819u, 1065353216u, 0, TANHF_TOLERANCE, 0}
+
+// AUTOMATICALLY GENERATED VECTORS STOP
+
+};
+
+#endif // CYGONCE_LIBM_SCABNF_H multiple inclusion protection
+
+// EOF tanhf.h
diff --git a/packages/language/c/libm/current/tests/vectors/vector_support_float.h b/packages/language/c/libm/current/tests/vectors/vector_support_float.h
new file mode 100644
--- /dev/null
+++ b/packages/language/c/libm/current/tests/vectors/vector_support_float.h
@@ -0,0 +1,550 @@
+#ifndef CYGONCE_LIBM_VECTOR_SUPPORT_H
+#define CYGONCE_LIBM_VECTOR_SUPPORT_H
+
+//========================================================================
+//
+//      vector_support_float.h
+//
+//      Support for testing of the math library using test vectors
+//
+//========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 2012, 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     jlarmour
+// Contributors:  jlarmour, visar, ilijak
+// Date:          1999-01-21
+// Purpose:
+// Description:
+// Usage:         #include "vectors/vector_support_float.h"
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+// CONFIGURATION
+
+#include <pkgconf/libm.h>      // Configuration header
+#include <pkgconf/isoinfra.h>  // CYGINT_ISO_MAIN_STARTUP
+
+// INCLUDES
+
+#include <cyg/infra/cyg_type.h>   // Common type definitions and support
+#include <cyg/infra/testcase.h>   // Test infrastructure
+#include <math.h>                 // Header for this package
+#include <sys/ieeefp.h>           // Cyg_libm_ieee_double_shape_type
+#include <cyg/infra/diag.h>
+
+#ifndef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+# include <errno.h>                // For Cyg_ErrNo
+#else
+# ifndef EDOM
+#   define EDOM 33
+# endif
+#endif
+
+// CONSTANTS
+
+#define PROBLEM_THRESHOLD 10      // Number of test vectors allowed to fail
+                                  // before we give up completely
+
+// HOW TO START TESTS
+
+#if CYGINT_ISO_MAIN_STARTUP
+
+# define START_TEST( test ) test(0)
+
+#elif defined(CYGFUN_KERNEL_API_C)
+
+# include <cyg/hal/hal_arch.h>
+# include <cyg/kernel/kapi.h>
+
+# define STACKSIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
+
+static cyg_uint8 stack[STACKSIZE];
+static cyg_handle_t thr_handle;
+static cyg_thread thr;
+
+# define START_TEST( test ) CYG_MACRO_START \
+    cyg_thread_create( 4, &test, (cyg_addrword_t)0, "test", \
+                       &stack[0],  STACKSIZE, &thr_handle, &thr ); \
+    cyg_thread_resume( thr_handle ); \
+    cyg_scheduler_start(); \
+    CYG_MACRO_END
+
+externC int main( int, char ** );
+
+externC void
+cyg_user_start( void )
+{
+    (void) main(0, NULL);
+} // cyg_user_start()
+
+#else // !defined(CYGFUN_KERNEL_API_C)
+
+externC int main( int, char ** );
+
+externC void
+cyg_user_start( void )
+{
+    (void) main(0, NULL);
+} // cyg_user_start()
+
+# define START_TEST( test ) test(0)
+
+#endif
+
+// TYPE DEFINITIONS
+
+
+typedef enum {
+    CYG_LIBM_TEST_VEC_NONE,         // this indicates whether the "double"
+    CYG_LIBM_TEST_VEC_INT,          // is being used to store a double, an
+    CYG_LIBM_TEST_VEC_FLOAT,
+    CYG_LIBM_TEST_VEC_INT_P,        // int pointer
+    CYG_LIBM_TEST_VEC_FLOAT_P
+} Cyg_libm_test_arg_type;
+
+
+// Define a type for a test vector record
+// Define a floattype for a test vector record
+
+typedef struct {
+    cyg_ucount32 vector_num;        // id number of this test vector record
+
+    // if any of the following arguments are ints rather than doubles, then
+    // use the lsw part to store it
+
+    cyg_uint32 arg1;   // first argument
+    cyg_uint32 arg2;   // second argument
+    cyg_uint32 result; // expected return value
+
+#ifndef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+    Cyg_ErrNo errno_val;           // expected value of errno. 0==unchanged
+#else
+    cyg_uint32 errno_val;
+#endif
+
+    float tolerance;              // relative amount that it is allowed
+                                   // to vary. i.e. the value should be
+                                   // plus or minus result*tolerance
+
+    int matherr_type;              // if testing the matherr() function,
+                                   // what type should the exception be
+} Cyg_libm_test_float_vec_t;
+
+// types to cope with the different forms of function to be called by the
+// test vector
+
+typedef float (*fffn) ( float, float );
+typedef float (*fifn) ( float, int );
+typedef float (*ffn) ( float );
+typedef float (*ffpfn) ( float, float *);
+typedef float (*fipfn) ( float, int *);
+typedef float (*iffn) ( int, float );
+typedef int (*i_ffn) (float);
+
+// STATIC FUNCTIONS
+
+// equivalent of abs() for doubles. We want to be independent of fabs()
+
+static float
+my_abs_f( float x )
+{
+    Cyg_libm_ieee_float_shape_type t;
+
+    t.value = x;
+
+    t.number.sign = 0;
+
+    return t.value;
+} // my_abs_f()
+
+
+static cyg_bool
+checkErrorAcceptableFloat( Cyg_libm_ieee_float_shape_type is,
+                      Cyg_libm_ieee_float_shape_type shouldbe,
+                      float tolerance) // _relative_ amount it can vary
+{
+    Cyg_libm_ieee_float_shape_type temp_flt;
+
+    // first do a short-circuit check if its identical
+    if ( (is.asi32 == shouldbe.asi32) )
+        return false;
+
+    // now check special cases
+
+    // +0 == -0
+    if ( ((is.asi32 & 0x7fffffff) == 0) &&
+         ((shouldbe.asi32 & 0x7fffffff) == 0) )
+        return false;
+
+    // +-infinity == +-infinity
+    if ((is.number.fraction0 == 0) && (shouldbe.number.fraction0 == 0) &&
+        (is.number.exponent == 255) && (shouldbe.number.exponent == 255))
+    {
+        return (is.number.sign != shouldbe.number.sign);
+    } // if
+
+    // both NaN. Assumes isnan works, but its pretty safe
+    if ( isnanf(is.value) && isnanf(shouldbe.value) )
+        return false;
+    else if (isnanf(is.value) || isnanf(shouldbe.value) )
+        return true;
+
+    // check same sign. Even around small values close to 0 we would want
+    // it to be on the right _side_ of 0
+    if ( is.number.sign != shouldbe.number.sign )
+        return true;
+
+    // okay, now work out what tolerance means for us
+
+    // find out what the difference is in the first place
+    temp_flt.value = my_abs_f( shouldbe.value - is.value );
+
+    // Check "both ways round" to deal with both under and overflow cases
+    if ( ((temp_flt.value / tolerance) < my_abs_f(shouldbe.value)) ||
+         (temp_flt.value < (my_abs_f(shouldbe.value) * tolerance)) )
+        return false;
+    else
+        return true; // so its not close enough
+
+} // checkErrorAcceptableFloat()
+
+
+static cyg_bool
+doTestVecFloat( CYG_ADDRESS func_ptr,
+           Cyg_libm_test_arg_type arg1_type,
+           Cyg_libm_test_arg_type arg2_type,
+           Cyg_libm_test_arg_type result_type,
+           const Cyg_libm_test_float_vec_t *vectors,
+           cyg_ucount32 num_vectors )
+{
+    cyg_ucount32 problems=0;
+    cyg_ucount32 i;
+    Cyg_libm_ieee_float_shape_type arg1, arg2, result_wanted, ret;
+    cyg_ucount32 alive_count = num_vectors / 10;
+
+    if (arg1_type == CYG_LIBM_TEST_VEC_INT) {
+            iffn fn = (iffn) func_ptr;
+
+            for (i=0;
+                 (i < num_vectors) && (problems < PROBLEM_THRESHOLD);
+                 i++) {
+
+                if (0 == i % alive_count)
+                    CYG_TEST_STILL_ALIVE(i, "Still crunching, please wait...");
+
+                arg1.asi32 = vectors[i].arg1;
+                arg2.asi32 = vectors[i].arg2;
+
+                result_wanted.asi32 = vectors[i].result;
+
+                ret.value = (*fn)( (int)arg1.value, arg2.value );
+
+                if ((vectors[i].errno_val) != 0) {
+
+#ifndef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+                    // In IEEE-mode we can't check the answer if this
+                    // is an error case
+
+                    if ((cyg_libm_get_compat_mode() !=
+                        CYGNUM_LIBM_COMPAT_IEEE) &&
+                        (errno != vectors[i].errno_val)) {
+
+                        ++problems;
+                        diag_printf("Vector #%d\n", i+1);
+                        CYG_TEST_FAIL( "error not set correctly");
+
+                    } // if
+#endif
+
+                    continue; // no point checking value in an error case
+                } // if
+                if (checkErrorAcceptableFloat( ret, result_wanted,
+                                          vectors[i].tolerance) ) {
+                    ++problems;
+                    diag_printf("Vector #%d\n", i+1);
+                    CYG_TEST_FAIL( "Result out of tolerance");
+                } // if
+            } // for
+            if (problems != 0)
+                return false;
+            else
+                return true;
+    }
+    if ((arg1_type != CYG_LIBM_TEST_VEC_FLOAT) ||
+        (result_type != CYG_LIBM_TEST_VEC_FLOAT &&
+        result_type != CYG_LIBM_TEST_VEC_INT)) {
+        CYG_TEST_FAIL("Test vector arguments are not correct type!");
+        return false;
+    } // if
+
+    switch (arg2_type) {
+    case CYG_LIBM_TEST_VEC_FLOAT:
+
+        {
+            fffn fn = (fffn) func_ptr;
+
+            for (i=0;
+                 (i < num_vectors) && (problems < PROBLEM_THRESHOLD);
+                 i++) {
+
+                if (0 == i % alive_count)
+                    CYG_TEST_STILL_ALIVE(i, "Still crunching, please wait...");
+
+                arg1.asi32 = vectors[i].arg1;
+                arg2.asi32 = vectors[i].arg2;
+
+                result_wanted.asi32 = vectors[i].result;
+
+                ret.value = (*fn)( arg1.value, arg2.value );
+
+                if ((vectors[i].errno_val) != 0) {
+
+#ifndef CYGSEM_LIBM_COMPAT_IEEE_ONLY
+                    // In IEEE-mode we can't check the answer if this
+                    // is an error case
+
+                    if ((cyg_libm_get_compat_mode() !=
+                        CYGNUM_LIBM_COMPAT_IEEE) &&
+                        (errno != vectors[i].errno_val)) {
+
+                        ++problems;
+                        diag_printf("Vector #%d\n", i+1);
+                        CYG_TEST_FAIL( "error not set correctly");
+
+                    } // if
+#endif
+
+                    continue; // no point checking value in an error case
+                } // if
+                if (checkErrorAcceptableFloat( ret, result_wanted,
+                                          vectors[i].tolerance) ) {
+                    ++problems;
+                    diag_printf("Vector #%d\n", i+1);
+                    CYG_TEST_FAIL( "Result out of tolerance");
+                } // if
+            } // for
+
+        } // compound
+
+        break;
+
+    case CYG_LIBM_TEST_VEC_INT:
+
+        {
+            fifn fn = (fifn) func_ptr;
+
+            for (i=0;
+                 (i < num_vectors) && (problems < PROBLEM_THRESHOLD);
+                 i++) {
+
+                if (0 == i % alive_count)
+                    CYG_TEST_STILL_ALIVE(i, "Still crunching, please wait...");
+
+                arg1.asi32 = vectors[i].arg1;
+
+                result_wanted.asi32 = vectors[i].result;
+
+                ret.value = (*fn)( arg1.value, vectors[i].arg2 );
+
+                if (checkErrorAcceptableFloat( ret, result_wanted,
+                                          vectors[i].tolerance) ) {
+                    ++problems;
+                    diag_printf("Vector #%d\n", i+1);
+                    CYG_TEST_FAIL( "Result out of tolerance");
+                } // if
+            } // for
+
+        } // compound
+
+        break;
+
+    case CYG_LIBM_TEST_VEC_INT_P:
+
+        {
+            fipfn fn = (fipfn) func_ptr;
+            int my_int;
+            Cyg_libm_ieee_float_shape_type my_flt1, my_flt2;
+
+            for (i=0;
+                 (i < num_vectors) && (problems < PROBLEM_THRESHOLD);
+                 i++) {
+
+                if (0 == i % alive_count)
+                    CYG_TEST_STILL_ALIVE(i, "Still crunching, please wait...");
+
+                arg1.asi32 = vectors[i].arg1;
+
+                result_wanted.asi32 = vectors[i].result;
+
+                ret.value = (*fn)( arg1.value, &my_int );
+
+                if (checkErrorAcceptableFloat( ret, result_wanted,
+                                          vectors[i].tolerance) ) {
+                    ++problems;
+                    diag_printf("Vector #%d\n", i+1);
+                    CYG_TEST_FAIL( "Result out of tolerance");
+                } // if
+
+                my_flt1.value = (float) my_int;
+                my_flt2.value = (float) (signed)vectors[i].arg2;
+
+                if (checkErrorAcceptableFloat( my_flt1, my_flt2,
+                                          vectors[i].tolerance) ) {
+                    ++problems;
+                    diag_printf("Vector #%d\n", i+1);
+                    CYG_TEST_FAIL( "Integer result out of tolerance");
+                } // if
+
+
+            } // for
+
+        } // compound
+
+        break;
+
+    case CYG_LIBM_TEST_VEC_FLOAT_P:
+
+        {
+            ffpfn fn = (ffpfn) func_ptr;
+            Cyg_libm_ieee_float_shape_type my_flt1;
+
+            for (i=0;
+                 (i < num_vectors) && (problems < PROBLEM_THRESHOLD);
+                 i++) {
+
+                if (0 == i % alive_count)
+                    CYG_TEST_STILL_ALIVE(i, "Still crunching, please wait...");
+
+                arg1.asi32 = vectors[i].arg1;
+                arg2.asi32 = vectors[i].arg2;
+
+                result_wanted.asi32 = vectors[i].result;
+
+                ret.value = (*fn)( arg1.value, &my_flt1.value );
+                if (checkErrorAcceptableFloat( ret, result_wanted,
+                                          vectors[i].tolerance) ) {
+                    ++problems;
+                    diag_printf("Vector #%d\n", i+1);
+                    CYG_TEST_FAIL( "Result out of tolerance");
+                } // if
+
+                if (checkErrorAcceptableFloat( my_flt1, arg2,
+                                          vectors[i].tolerance) ) {
+                    ++problems;
+                    diag_printf("Vector #%d\n", i+1);
+                    CYG_TEST_FAIL( "Returned float result out of "
+                                   "tolerance");
+                } // if
+
+
+            } // for
+
+        } // compound
+
+        break;
+
+    case CYG_LIBM_TEST_VEC_NONE:
+
+        {
+            if (result_type == CYG_LIBM_TEST_VEC_INT) {
+                i_ffn fn = (i_ffn) func_ptr;
+
+            for (i=0;
+                 (i < num_vectors) && (problems < PROBLEM_THRESHOLD);
+                 i++) {
+
+                if (0 == i % alive_count)
+                    CYG_TEST_STILL_ALIVE(i, "Still crunching, please wait...");
+
+                arg1.asi32 = vectors[i].arg1;
+
+                result_wanted.asi32 = vectors[i].result;
+                ret.value = (*fn)( arg1.value );
+                /* Get a 32 bit int from a float.  */
+
+                if (checkErrorAcceptableFloat( ret, result_wanted,
+                                          vectors[i].tolerance) ) {
+                    ++problems;
+                    diag_printf("Vector #%d\n", i+1);
+                    CYG_TEST_FAIL( "Result out of tolerance");
+                } // if
+            } // for
+            }
+            else
+            {
+            ffn fn = (ffn) func_ptr;
+
+            for (i=0;
+                 (i < num_vectors) && (problems < PROBLEM_THRESHOLD);
+                 i++) {
+
+                if (0 == i % alive_count)
+                    CYG_TEST_STILL_ALIVE(i, "Still crunching, please wait...");
+
+                arg1.asi32 = vectors[i].arg1;
+
+                result_wanted.asi32 = vectors[i].result;
+                ret.value = (*fn)( arg1.value );
+                /* Get a 32 bit int from a float.  */
+
+                if (checkErrorAcceptableFloat( ret, result_wanted,
+                                          vectors[i].tolerance) ) {
+                    ++problems;
+                    diag_printf("Vector #%d\n", i+1);
+                    CYG_TEST_FAIL( "Result out of tolerance");
+                } // if
+            } // for
+           }
+        } // compound
+
+        break;
+
+    default:
+        CYG_TEST_FAIL("Second argument of unknown type!");
+        return false;
+    } // switch
+
+    if (problems != 0)
+        return false;
+    else
+        return true;
+
+} // doTestVecFloat()
+
+#endif // CYGONCE_LIBM_VECTOR_SUPPORT_H multiple inclusion protection
+
+// EOF vector_support_float.h
diff --git a/packages/language/cxx/ustl/current/ChangeLog b/packages/language/cxx/ustl/current/ChangeLog
--- a/packages/language/cxx/ustl/current/ChangeLog
+++ b/packages/language/cxx/ustl/current/ChangeLog
@@ -1,3 +1,35 @@
+2013-02-18  John Dallaway  <john@dallaway.org.uk>
+
+	* src/fstream.cpp: Fix processing of fstream openmode. Patch
+	from uSTL HEAD.
+	* cdl/ustl.cdl: Build interactive tests under control of a CDL
+	option. Build ROM filesystem for bvt25 test under control of a
+	CDL option.
+	* tests/bvt25.cpp: Use ROM filesystem if available.
+	* tests/bvt05.cpp, tests/bvt16.cpp: Reduce data structure sizes
+	for embedded use.	
+
+2012-03-24  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* include/*:
+	* src/*:
+	* tests/*:
+	* HISTORY:
+	* LICENSE: Updated to uSTL 1.6 sources.
+
+2011-11-21  John Dallaway  <john@dallaway.org.uk>
+
+	* include/ustl/ustring.h: Fix incorrect behaviour of iat when passed
+	offset+npos. Reported by Frank Pagliughi. Patch from uSTL HEAD.
+	[ Bugzilla 1001390 ]
+
+2010-06-25  Simon Kallweit <simon.kallweit@intefo.ch>
+
+	* include/*:
+	* tests/*:
+	* HISTORY:
+	* LICENSE: Updated to uSTL 1.4 sources.
+
 2009-10-06  Uwe Kindler <uwe_kindler@web.de>
 
 	* doc/ustl.sgml: Removed cout.flush() from example and from note.
@@ -35,7 +67,7 @@ 2009-08-20  Uwe Kindler <uwe_kindler@web
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2009 Free Software Foundation, Inc.                        
+// Copyright (C) 2009, 2010, 2011, 2013 Free Software Foundation, Inc.                        
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     
diff --git a/packages/language/cxx/ustl/current/HISTORY b/packages/language/cxx/ustl/current/HISTORY
--- a/packages/language/cxx/ustl/current/HISTORY
+++ b/packages/language/cxx/ustl/current/HISTORY
@@ -1,3 +1,30 @@
+2012-02-18 Release 1.6
+	* Fixed compilation with c++0x
+	alignof is a keyword in c++0x, so the stream version usually not needed now.
+	On the other hand, alignof can not be overloaded, so stream_align_of is the
+	new name for the old alignof. Most code should not require changes due to this.
+	* Fix iat in string, which did not handle npos argument correctly, sometimes
+	resulting in failures of other functions using it, like substr.
+
+2011-03-16 Release 1.5
+	* Updated set, map, and multimap with full set of insert, erase, and search overloads
+	* Added public lower_bound, upper_bound, and equal_range to map, as per standard
+	* Added comparator parameter to set, multiset, map, and multimap.
+	* Implemented FirstBit, Rol, Ror, and a generic NextPow2
+	* Remove memlink copy because it conflicts with string copy
+	* Operators returning a new value should be const
+	* Added char* + string operator, and a noarg erase
+	* Added --force-inline configure option
+	* Removed all references to stdc++ headers when not using libstdc++
+	* Fixed minor glitches compiling with clang++
+	* Other small fixes
+
+2010-03-21 Release 1.4
+	* Fixed crash in destructor of empty vector, introduced by 1.3
+	* Fixed list merge, which previously did not compile
+	* Some portability changes to configure so it will work with dash
+	    when escape char processing bug is fixed (Ubuntu bug #268929)
+
 2009-08-04 Release 1.3
 	* Some API changes to comply with the current C++ standard
 	    binary_search algo returns true, not the found iterator
diff --git a/packages/language/cxx/ustl/current/LICENSE b/packages/language/cxx/ustl/current/LICENSE
--- a/packages/language/cxx/ustl/current/LICENSE
+++ b/packages/language/cxx/ustl/current/LICENSE
@@ -1,24 +1,22 @@
 
 			The MIT License
 
-Copyright (C) 2005 by Mike Sharov <msharov@users.sourceforge.net>
+Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 
 Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sublicense,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
 
 The above copyright notice and this permission notice shall be included
 in all copies or substantial portions of the Software.
 
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+OTHER DEALINGS IN THE SOFTWARE.
diff --git a/packages/language/cxx/ustl/current/cdl/ustl.cdl b/packages/language/cxx/ustl/current/cdl/ustl.cdl
--- a/packages/language/cxx/ustl/current/cdl/ustl.cdl
+++ b/packages/language/cxx/ustl/current/cdl/ustl.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 2009 Free Software Foundation, Inc.
+## Copyright (C) 2009, 2013 Free Software Foundation, Inc.
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -40,7 +40,7 @@
 ######DESCRIPTIONBEGIN####
 #
 # Author(s):      Uwe Kindler
-# Contributors:   
+# Contributors:   jld
 # Date:           2009-07-28
 #
 #####DESCRIPTIONEND####
@@ -183,11 +183,62 @@ cdl_package CYGPKG_USTL {
                 the set of global flags if present."
         }
 
+        cdl_option CYGIMP_USTL_TESTS_BVT25_ROMFS {
+            display "Build ROM filesystem for bvt25 test"
+            flavor  bool
+            active_if CYGVAR_USTL_CIN_COUT_CERR
+            requires CYGPKG_FS_ROM
+            requires CYGBLD_FS_ROMFS_MK_ROMFS
+            default_value CYGBLD_FS_ROMFS_MK_ROMFS
+            description "
+                Enable this option to build a ROM filesystem for use
+                by the bvt25 test. If you disable this option, you will
+                need to provide an alternative filesystem containing
+                the file \"bvt25.std\"."
+            make {
+                <PREFIX>/include/cyg/ustl/bvt25fs_be.h : <PACKAGE>/tests/bvt25.std
+                @mkdir -p bvt25_be
+                @cp $< bvt25_be/$(<F)
+                @chmod u+w bvt25_be/$(<F)
+                @$(PREFIX)/bin/mk_romfs -b bvt25_be $(@F:.h=.tmp)
+                @mkdir -p "$(@D)"
+                tclsh $(PREFIX)/bin/file2c.tcl $(@F:.h=.tmp) $@
+                @rm -r bvt25_be $(@F:.h=.tmp)
+            }
+            make {
+                <PREFIX>/include/cyg/ustl/bvt25fs_le.h : <PACKAGE>/tests/bvt25.std
+                @mkdir -p bvt25_le
+                @cp $< bvt25_le/$(<F)
+                @chmod u+w bvt25_le/$(<F)
+                @$(PREFIX)/bin/mk_romfs bvt25_le $(@F:.h=.tmp)
+                @mkdir -p "$(@D)"
+                tclsh $(PREFIX)/bin/file2c.tcl $(@F:.h=.tmp) $@
+                @rm -r bvt25_le $(@F:.h=.tmp)
+            }
+        }
+
+        cdl_option CYGBLD_USTL_BUILD_INTERACTIVE_TESTS {
+	    display "Build interactive uSTL tests"
+            flavor  bool
+            no_define
+            active_if CYGVAR_USTL_CIN_COUT_CERR
+            default_value 0
+            description   "
+                This option enables the building of uSTL tests which
+                require user input (bvt13, bvt17). The easiest way to
+                run these tests is to build them for the synthetic
+                (linux) target and redirect standard input from file
+                at a shell prompt. For example: ./bvt13 < bvt13.cpp"
+        }
+
         cdl_option CYGPKG_USTL_TESTS {
             display "uSTL tests"
             flavor  data
             no_define
-            calculated { (CYGVAR_USTL_CIN_COUT_CERR ? "tests/bvt00 tests/bvt01 tests/bvt02 tests/bvt03 tests/bvt04 tests/bvt05 tests/bvt06 tests/bvt07 tests/bvt08 tests/bvt09 tests/bvt10 tests/bvt11 tests/bvt12 tests/bvt13 tests/bvt14 tests/bvt15 tests/bvt16 tests/bvt17 tests/bvt18 tests/bvt19 tests/bvt20 tests/bvt21 tests/bvt22 tests/bvt23 tests/bvt24 tests/bvt25 tests/bvt26 tests/bvt27" : "" )}
+            calculated { (CYGVAR_USTL_CIN_COUT_CERR ?
+                (CYGBLD_USTL_BUILD_INTERACTIVE_TESTS ?
+                    "tests/bvt00 tests/bvt01 tests/bvt02 tests/bvt03 tests/bvt04 tests/bvt05 tests/bvt06 tests/bvt07 tests/bvt08 tests/bvt09 tests/bvt10 tests/bvt11 tests/bvt12 tests/bvt13 tests/bvt14 tests/bvt15 tests/bvt16 tests/bvt17 tests/bvt18 tests/bvt19 tests/bvt20 tests/bvt21 tests/bvt22 tests/bvt23 tests/bvt24 tests/bvt25 tests/bvt26 tests/bvt27" :
+                    "tests/bvt00 tests/bvt01 tests/bvt02 tests/bvt03 tests/bvt04 tests/bvt05 tests/bvt06 tests/bvt07 tests/bvt08 tests/bvt09 tests/bvt10 tests/bvt11 tests/bvt12 tests/bvt14 tests/bvt15 tests/bvt16 tests/bvt18 tests/bvt19 tests/bvt20 tests/bvt21 tests/bvt22 tests/bvt23 tests/bvt24 tests/bvt25 tests/bvt26 tests/bvt27") : "" )}
             description   "
                 This option specifies the set of tests for the uSTL library."
         }
diff --git a/packages/language/cxx/ustl/current/include/ustl.h b/packages/language/cxx/ustl/current/include/ustl.h
--- a/packages/language/cxx/ustl/current/include/ustl.h
+++ b/packages/language/cxx/ustl/current/include/ustl.h
@@ -1,11 +1,13 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef USTL_H_6A5A10410D2CD7FC2D78FE470F045EB7
 #define USTL_H_6A5A10410D2CD7FC2D78FE470F045EB7
 
+#include <pkgconf/ustl.h>
+
 #include "ustl/uspecial.h"
 #include "ustl/umap.h"
 #include "ustl/umultimap.h"
diff --git a/packages/language/cxx/ustl/current/include/ustl/bktrace.h b/packages/language/cxx/ustl/current/include/ustl/bktrace.h
--- a/packages/language/cxx/ustl/current/include/ustl/bktrace.h
+++ b/packages/language/cxx/ustl/current/include/ustl/bktrace.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2006-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2006 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef BKTRACE_H_63ABB1E4388CEDD975DBE58B57DE474F
@@ -47,6 +47,4 @@ private:
 
 } // namespace ustl
 
-ALIGNOF(ustl::CBacktrace, sizeof(void*))
-
 #endif
diff --git a/packages/language/cxx/ustl/current/include/ustl/cmemlink.h b/packages/language/cxx/ustl/current/include/ustl/cmemlink.h
--- a/packages/language/cxx/ustl/current/include/ustl/cmemlink.h
+++ b/packages/language/cxx/ustl/current/include/ustl/cmemlink.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef CMEMLINK_H_7CFAB32C5C6732ED29B34EF00EA40A12
diff --git a/packages/language/cxx/ustl/current/include/ustl/fstream.h b/packages/language/cxx/ustl/current/include/ustl/fstream.h
--- a/packages/language/cxx/ustl/current/include/ustl/fstream.h
+++ b/packages/language/cxx/ustl/current/include/ustl/fstream.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef FSTREAM_H_056E10F70EAD416443E3B36A2D6B5FA3
diff --git a/packages/language/cxx/ustl/current/include/ustl/memblock.h b/packages/language/cxx/ustl/current/include/ustl/memblock.h
--- a/packages/language/cxx/ustl/current/include/ustl/memblock.h
+++ b/packages/language/cxx/ustl/current/include/ustl/memblock.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef MEMBLOCK_H_7ED63A891164CC43578E63664D52A196
diff --git a/packages/language/cxx/ustl/current/include/ustl/memlink.h b/packages/language/cxx/ustl/current/include/ustl/memlink.h
--- a/packages/language/cxx/ustl/current/include/ustl/memlink.h
+++ b/packages/language/cxx/ustl/current/include/ustl/memlink.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef MEMLINK_H_798D25827C8E322D2D7E734B169FF5FC
@@ -64,9 +64,6 @@ public:
     inline void		link (void* first, void* last)		{ link (first, distance (first, last)); }
     inline void		relink (const void* p, size_type n)	{ cmemlink::relink (p, n); }
     inline void		relink (void* p, size_type n)		{ cmemlink::relink (p, n); }
-    inline void		copy (const cmemlink& l)		{ copy (begin(), l.cdata(), l.size()); }
-    inline void		copy (const void* p, size_type n)	{ copy (begin(), p, n); }
-    void		copy (iterator offset, const void* p, size_type n);
     inline void		swap (memlink& l)			{ cmemlink::swap (l); }
     void		fill (iterator start, const void* p, size_type elsize, size_type elCount = 1);
     inline void		insert (iterator start, size_type size);
diff --git a/packages/language/cxx/ustl/current/include/ustl/metamac.h b/packages/language/cxx/ustl/current/include/ustl/metamac.h
--- a/packages/language/cxx/ustl/current/include/ustl/metamac.h
+++ b/packages/language/cxx/ustl/current/include/ustl/metamac.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 //
 /// \file metamac.h
diff --git a/packages/language/cxx/ustl/current/include/ustl/mistream.h b/packages/language/cxx/ustl/current/include/ustl/mistream.h
--- a/packages/language/cxx/ustl/current/include/ustl/mistream.h
+++ b/packages/language/cxx/ustl/current/include/ustl/mistream.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef MISTREAM_H_103AEF1F266C04AA1A817D38705983DA
@@ -13,7 +13,7 @@
 #include "uios.h"
 #include "config.h"
 #if WANT_STREAM_BOUNDS_CHECKING
-    #include <typeinfo>
+    #include "typeinfo.h"
 #endif
 
 namespace ustl {
@@ -257,7 +257,7 @@ inline void istream::align (streamsize g
 template <typename T>
 inline void istream::iread (T& v)
 {
-    assert (aligned (alignof (v)));
+    assert (aligned (stream_align_of (v)));
 #if WANT_STREAM_BOUNDS_CHECKING
     if (!verify_remaining ("read", USTL_TYPENAME(v), sizeof(T)))
 	return;
diff --git a/packages/language/cxx/ustl/current/include/ustl/mostream.h b/packages/language/cxx/ustl/current/include/ustl/mostream.h
--- a/packages/language/cxx/ustl/current/include/ustl/mostream.h
+++ b/packages/language/cxx/ustl/current/include/ustl/mostream.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef MOSTREAM_H_24A8C5397E0848216573E5670930FC9A
@@ -12,7 +12,7 @@
 #include "uios.h"
 #include "config.h"
 #if WANT_STREAM_BOUNDS_CHECKING
-    #include <typeinfo>
+    #include "typeinfo.h"
 #endif
 
 namespace ustl {
@@ -28,7 +28,7 @@ class string;
 /// This class contains a set of functions to write integral types into an
 /// unstructured memory block. Packing binary file data can be done this
 /// way, for instance. aligning the data is your responsibility, and can
-/// be accomplished by proper ordering of writes and by calling \ref ostream::align.
+/// be accomplished by proper ordering of writes and by calling align.
 /// Unaligned access is usually slower by orders of magnitude and,
 /// on some architectures, such as PowerPC, can cause your program to crash.
 /// Therefore, all write functions have asserts to check alignment.
@@ -253,7 +253,7 @@ inline void ostream::write (const cmemli
 template <typename T>
 inline void ostream::iwrite (const T& v)
 {
-    assert (aligned (alignof (v)));
+    assert (aligned (stream_align_of (v)));
 #if WANT_STREAM_BOUNDS_CHECKING
     if (!verify_remaining ("write", USTL_TYPENAME(v), sizeof(T)))
 	return;
diff --git a/packages/language/cxx/ustl/current/include/ustl/ofstream.h b/packages/language/cxx/ustl/current/include/ustl/ofstream.h
--- a/packages/language/cxx/ustl/current/include/ustl/ofstream.h
+++ b/packages/language/cxx/ustl/current/include/ustl/ofstream.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef FDOSTREAM_H_5E27FC3D530BF3CA04D6C73F5700EECC
diff --git a/packages/language/cxx/ustl/current/include/ustl/simd.h b/packages/language/cxx/ustl/current/include/ustl/simd.h
--- a/packages/language/cxx/ustl/current/include/ustl/simd.h
+++ b/packages/language/cxx/ustl/current/include/ustl/simd.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 //
 /// \file simd.h
@@ -54,7 +54,7 @@ inline void packop (const Ctr& op1, cons
 {
     assert (op1.size() <= op2.size() && op1.size() <= result.size());
     passign (op1, result);
-    packop (op2, result);
+    op (op2, result);
 }
 
 /// Copies \p op1 into \p result.
diff --git a/packages/language/cxx/ustl/current/include/ustl/sistream.h b/packages/language/cxx/ustl/current/include/ustl/sistream.h
--- a/packages/language/cxx/ustl/current/include/ustl/sistream.h
+++ b/packages/language/cxx/ustl/current/include/ustl/sistream.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef SISTREAM_H_0CCA102229A49F5D65EE852E62B27CE2
@@ -8,6 +8,9 @@
 
 #include "mistream.h"
 #include "ustring.h"
+#ifndef EOF
+#define EOF (-1)
+#endif
 
 namespace ustl {
 
@@ -38,7 +41,7 @@ public:
     inline string		str (void) const	{ string s; s.link (*this); return (s); }
     inline istringstream&	str (const string& s)	{ link (s); return (*this); }
     inline istringstream&	get (char& c)	{ return (read (&c, sizeof(c))); }
-    inline int			get (void)	{ char c; get(c); return (c); }
+    inline int			get (void)	{ char c = EOF; get(c); return (c); }
     istringstream&		get (char* p, size_type n, char delim = '\n');
     istringstream&		get (string& s, char delim = '\n');
     istringstream&		getline (char* p, size_type n, char delim = '\n');
@@ -137,9 +140,6 @@ ISTRSTREAM_CAST_OPERATOR (char,		int8_t)
 ISTRSTREAM_CAST_OPERATOR (uint64_t,	int64_t)
 #endif
 #if SIZE_OF_LONG == SIZE_OF_INT
-// This works only properly if stdint.h typedefs int to int32_t. If stdint.h
-// typedefs long to int32_t then this causes compiler errors. So make shure
-// that your stdint.h file typedefs int to int32_t.
 ISTRSTREAM_CAST_OPERATOR (long,		int)
 ISTRSTREAM_CAST_OPERATOR (unsigned long,int)
 #endif
diff --git a/packages/language/cxx/ustl/current/include/ustl/sostream.h b/packages/language/cxx/ustl/current/include/ustl/sostream.h
--- a/packages/language/cxx/ustl/current/include/ustl/sostream.h
+++ b/packages/language/cxx/ustl/current/include/ustl/sostream.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef SOSTREAM_H_5323DC8C26E181D43278F2F53FDCF19F
diff --git a/packages/language/cxx/ustl/current/include/ustl/strmsize.h b/packages/language/cxx/ustl/current/include/ustl/strmsize.h
--- a/packages/language/cxx/ustl/current/include/ustl/strmsize.h
+++ b/packages/language/cxx/ustl/current/include/ustl/strmsize.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 //
 /// \file strmsize.h
@@ -28,6 +28,20 @@ inline streamsize stream_size_of (const 
     return (stream_sizer_t()(v));
 }
 
+/// \brief Returns the recommended stream alignment for type \p T. Override with ALIGNOF.
+/// Because this is occasionally called with a null value, do not access the argument!
+template <typename T>
+inline size_t stream_align_of (const T&)
+{
+    if (numeric_limits<T>::is_integral)
+	return (__alignof__(T));
+    return (4);
+}
+
+#define ALIGNOF(type,grain)	\
+namespace ustl {		\
+    template <> inline size_t stream_align_of (const type&) { return (grain); } }
+
 } // namespace ustl
 
 //
diff --git a/packages/language/cxx/ustl/current/include/ustl/traits.h b/packages/language/cxx/ustl/current/include/ustl/traits.h
--- a/packages/language/cxx/ustl/current/include/ustl/traits.h
+++ b/packages/language/cxx/ustl/current/include/ustl/traits.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2007-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2007 by Mike Sharov <msharov@users.sourceforge.net>
 //
 // This implementation is adapted from the Loki library, distributed under
 // the MIT license with Copyright (c) 2001 by Andrei Alexandrescu.
diff --git a/packages/language/cxx/ustl/current/include/ustl/typeinfo.h b/packages/language/cxx/ustl/current/include/ustl/typeinfo.h
new file mode 100644
--- /dev/null
+++ b/packages/language/cxx/ustl/current/include/ustl/typeinfo.h
@@ -0,0 +1,40 @@
+// This file is part of the uSTL library, an STL implementation.
+//
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
+// This file is free software, distributed under the MIT License.
+//
+#ifndef TYPEINFO_H_E67A267F0BBB5005
+#define TYPEINFO_H_E67A267F0BBB5005
+
+#ifndef WITHOUT_LIBSTDCPP
+    #include <typeinfo>
+#else
+
+#include "uexception.h"
+
+namespace __cxxabiv1 { class __class_type_info; }
+
+namespace std {
+class type_info {
+public:
+    inline virtual	~type_info (void)			{ }
+    inline const char*	name (void) const			{ return (__name[0] == '*' ? __name + 1 : __name); }
+    inline bool		before (const type_info& v) const	{ return (__name < v.__name); }
+    inline bool		operator==(const type_info& v) const	{ return (__name == v.__name); }
+    inline bool		operator!=(const type_info& v) const	{ return (!operator==(v)); }
+    virtual bool	__is_pointer_p (void) const;
+    virtual bool	__is_function_p (void) const;
+    virtual bool	__do_catch (const type_info* __thr_type, void** __thr_obj, unsigned __outer) const;
+    virtual bool	__do_upcast (const __cxxabiv1::__class_type_info* __target, void** __obj_ptr) const;
+    explicit inline	type_info (const char* newname)		: __name(newname) { }
+private:
+    inline void		operator= (const type_info&)		{ }
+    inline		type_info (const type_info&)		{ }
+protected:
+    const char*		__name;
+};
+
+} // namespace std
+
+#endif
+#endif
diff --git a/packages/language/cxx/ustl/current/include/ustl/typelist.h b/packages/language/cxx/ustl/current/include/ustl/typelist.h
--- a/packages/language/cxx/ustl/current/include/ustl/typelist.h
+++ b/packages/language/cxx/ustl/current/include/ustl/typelist.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2007-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2007 by Mike Sharov <msharov@users.sourceforge.net>
 //
 // This implementation is adapted from the Loki library, distributed under
 // the MIT license with Copyright (c) 2001 by Andrei Alexandrescu.
diff --git a/packages/language/cxx/ustl/current/include/ustl/typet.h b/packages/language/cxx/ustl/current/include/ustl/typet.h
--- a/packages/language/cxx/ustl/current/include/ustl/typet.h
+++ b/packages/language/cxx/ustl/current/include/ustl/typet.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2007-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2007 by Mike Sharov <msharov@users.sourceforge.net>
 //
 // This implementation is adapted from the Loki library, distributed under
 // the MIT license with Copyright (c) 2001 by Andrei Alexandrescu.
@@ -38,7 +38,8 @@ struct IsSameType<T,T> { enum { value = 
 /// Conversion<T,U>::exists2Way is true if U is also convertible to T
 /// Conversion<T,U>::sameType is true if U is T
 template <typename T, typename U>
-class Conversion {
+struct Conversion {
+private:
     typedef char UT;
     typedef short TT;
     static UT Test (U);
diff --git a/packages/language/cxx/ustl/current/include/ustl/ualgo.h b/packages/language/cxx/ustl/current/include/ustl/ualgo.h
--- a/packages/language/cxx/ustl/current/include/ustl/ualgo.h
+++ b/packages/language/cxx/ustl/current/include/ustl/ualgo.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UALGO_H_711AB4214D417A51166694D47A662D6E
@@ -9,7 +9,6 @@
 #include "upair.h"
 #include "ualgobase.h"
 #include "ufunction.h"
-#include "upredalgo.h"
 #include "umemory.h"
 #include <stdlib.h>	// for rand()
 
diff --git a/packages/language/cxx/ustl/current/include/ustl/ualgobase.h b/packages/language/cxx/ustl/current/include/ustl/ualgobase.h
--- a/packages/language/cxx/ustl/current/include/ustl/ualgobase.h
+++ b/packages/language/cxx/ustl/current/include/ustl/ualgobase.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UALGOBASE_H_683A0BE77546133C4CE0E3622CFAA2EB
@@ -258,7 +258,7 @@ COPY_BACKWARD_ALIAS_FUNC(const void, voi
 #undef COPY_BACKWARD_ALIAS_FUNC
 #define FILL_ALIAS_FUNC(type, alias_type, v_type)				\
 template <> inline void fill (type* first, type* last, const v_type& value)	\
-{ fill ((alias_type*) first, (alias_type*) last, (const alias_type&) value); }
+{ fill ((alias_type*) first, (alias_type*) last, (const alias_type) value); }
 FILL_ALIAS_FUNC(void, uint8_t, char)
 FILL_ALIAS_FUNC(void, uint8_t, uint8_t)
 #if WANT_UNROLLED_COPY
@@ -298,7 +298,7 @@ COPY_N_ALIAS_FUNC(const int32_t, int32_t
 #undef COPY_N_ALIAS_FUNC
 #define FILL_N_ALIAS_FUNC(type, alias_type, v_type)				\
 template <> inline type* fill_n (type* first, size_t n, const v_type& value)	\
-{ return ((type*) fill_n ((alias_type*) first, n, (const alias_type&) value)); }
+{ return ((type*) fill_n ((alias_type*) first, n, (const alias_type) value)); }
 FILL_N_ALIAS_FUNC(void, uint8_t, char)
 FILL_N_ALIAS_FUNC(void, uint8_t, uint8_t)
 #if WANT_UNROLLED_COPY
diff --git a/packages/language/cxx/ustl/current/include/ustl/ubitset.h b/packages/language/cxx/ustl/current/include/ustl/ubitset.h
--- a/packages/language/cxx/ustl/current/include/ustl/ubitset.h
+++ b/packages/language/cxx/ustl/current/include/ustl/ubitset.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UBITSET_H_7B6450EC1400CBA45DCE0127739F82EE
@@ -38,6 +38,7 @@ public:
     typedef const_pointer	const_iterator;
     typedef size_t		difference_type;
     typedef size_t		size_type;
+    typedef const bitset<Size>&	rcself_t;
 private:
     static const size_t s_WordBits	= BitsInType (value_type);
     static const size_t	s_nWords	= Size / s_WordBits + ((Size % s_WordBits) != 0);
@@ -102,19 +103,19 @@ public:
     inline bool		any (void) const	{ value_type sum = 0; foreach (const_iterator, i, *this) sum |= *i; return (sum); }
     inline bool		none (void) const	{ return (!any()); }
     inline size_t	count (void) const	{ size_t sum = 0; foreach (const_iterator, i, *this) sum += popcount(*i); return (sum); }
-    inline bool		operator== (const bitset<Size>& v) const
+    inline bool		operator== (rcself_t v) const
 			    { return (s_nWords == 1 ? (m_Bits[0] == v.m_Bits[0]) : equal (begin(), end(), v.begin())); }
-    inline const bitset	operator& (const bitset<Size>& v)
+    inline bitset	operator& (rcself_t v) const
 			    { bitset<Size> result; transform (begin(), end(), v.begin(), result.begin(), bitwise_and<value_type>()); return (result); }
-    inline const bitset	operator| (const bitset<Size>& v)
+    inline bitset	operator| (rcself_t v) const
 			    { bitset<Size> result; transform (begin(), end(), v.begin(), result.begin(), bitwise_or<value_type>()); return (result); }
-    inline const bitset	operator^ (const bitset<Size>& v)
+    inline bitset	operator^ (rcself_t v) const
 			    { bitset<Size> result; transform (begin(), end(), v.begin(), result.begin(), bitwise_xor<value_type>()); return (result); }
-   inline const bitset&	operator&= (const bitset<Size>& v)
+    inline rcself_t	operator&= (rcself_t v)
 			    { transform (begin(), end(), v.begin(), begin(), bitwise_and<value_type>()); return (*this); }
-   inline const bitset&	operator|= (const bitset<Size>& v)
+    inline rcself_t	operator|= (rcself_t v)
 			    { transform (begin(), end(), v.begin(), begin(), bitwise_or<value_type>()); return (*this); }
-   inline const bitset&	operator^= (const bitset<Size>& v)
+    inline rcself_t	operator^= (rcself_t v)
 			    { transform (begin(), end(), v.begin(), begin(), bitwise_xor<value_type>()); return (*this); }
     inline void		read (istream& is)			{ nr_container_read (is, *this); }
     inline void		write (ostream& os) const		{ nr_container_write (os, *this); }
diff --git a/packages/language/cxx/ustl/current/include/ustl/uctralgo.h b/packages/language/cxx/ustl/current/include/ustl/uctralgo.h
--- a/packages/language/cxx/ustl/current/include/ustl/uctralgo.h
+++ b/packages/language/cxx/ustl/current/include/ustl/uctralgo.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UCTRALGO_H_0D1AEDFA74B09791489FE25B1EC644B0
diff --git a/packages/language/cxx/ustl/current/include/ustl/uctrstrm.h b/packages/language/cxx/ustl/current/include/ustl/uctrstrm.h
--- a/packages/language/cxx/ustl/current/include/ustl/uctrstrm.h
+++ b/packages/language/cxx/ustl/current/include/ustl/uctrstrm.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 //
 /// \file uctrstrm.h
@@ -16,7 +16,7 @@
 #include "mistream.h"
 #include "sostream.h"
 #include "uiosfunc.h"
-#include <typeinfo>
+#include "typeinfo.h"
 
 namespace ustl {
 
@@ -119,7 +119,7 @@ istream& container_read (istream& is, Co
     const size_t expectedSize = n * stream_size_of(value_type());
     if (!is.verify_remaining ("read", USTL_TYPENAME(v), expectedSize))
 	return (is);
-    if (alignof(NullValue<value_type>()) > alignof(n))
+    if (stream_align_of(NullValue<value_type>()) > stream_align_of(n))
 	is >> ios::talign<value_type>();
     v.resize (n);
     nr_container_read (is, v);
@@ -135,7 +135,7 @@ ostream& container_write (ostream& os, c
     typedef typename Container::written_size_type written_size_type;
     const written_size_type sz (v.size());
     os << sz;
-    if (alignof(NullValue<value_type>()) > alignof(sz))
+    if (stream_align_of(NullValue<value_type>()) > stream_align_of(sz))
 	os << ios::talign<value_type>();
     nr_container_write (os, v);
     os << ios::talign<written_size_type>();
@@ -150,9 +150,9 @@ size_t container_stream_size (const Cont
     typedef typename Container::written_size_type written_size_type;
     const written_size_type sz (v.size());
     size_t sizeSize = stream_size_of (sz);
-    if (alignof(NullValue<value_type>()) > alignof(sz))
-	sizeSize = Align (sizeSize, alignof(NullValue<value_type>()));
-    return (Align (sizeSize + nr_container_stream_size (v), alignof(sz)));
+    if (stream_align_of(NullValue<value_type>()) > stream_align_of(sz))
+	sizeSize = Align (sizeSize, stream_align_of(NullValue<value_type>()));
+    return (Align (sizeSize + nr_container_stream_size (v), stream_align_of(sz)));
 }
 
 /// \brief Writes element \p v into stream \p os as text.
diff --git a/packages/language/cxx/ustl/current/include/ustl/uexception.h b/packages/language/cxx/ustl/current/include/ustl/uexception.h
--- a/packages/language/cxx/ustl/current/include/ustl/uexception.h
+++ b/packages/language/cxx/ustl/current/include/ustl/uexception.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UEXCEPTION_H_18DE3EF55C4F00673268F0D66546AF5D
@@ -23,7 +23,7 @@ typedef void (*unexpected_handler) (void
 terminate_handler set_terminate (terminate_handler pHandler) throw();
 /// The runtime will call this function if exception handling must be
 /// abandoned for any reason.  It can also be called by the user.
-void terminate (void) __attribute__ ((__noreturn__));
+void terminate (void) throw() __attribute__ ((__noreturn__));
 /// Takes a new handler function as an argument, returns the old function.
 unexpected_handler set_unexpected (unexpected_handler pHandler) throw();
 /// The runtime will call this function if an exception is thrown which
@@ -88,8 +88,14 @@ private:
 ///
 class bad_cast : public exception {
 public:
-    inline explicit		bad_cast (void) throw() : exception() {}
-    inline virtual const char*	what (void) const throw() { return ("bad cast"); }
+    inline 			bad_cast (void) throw()		: exception() {}
+    inline virtual const char*	what (void) const throw()	{ return ("bad cast"); }
+};
+
+class bad_typeid : public exception {
+public:
+    inline			bad_typeid (void) throw()	{ }
+    inline virtual const char*	what (void) const throw()	{ return ("bad typeid"); }
 };
 
 //----------------------------------------------------------------------
diff --git a/packages/language/cxx/ustl/current/include/ustl/ufunction.h b/packages/language/cxx/ustl/current/include/ustl/ufunction.h
--- a/packages/language/cxx/ustl/current/include/ustl/ufunction.h
+++ b/packages/language/cxx/ustl/current/include/ustl/ufunction.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UFUNCTION_H_221ABA8551801799263C927234C085F3
diff --git a/packages/language/cxx/ustl/current/include/ustl/uheap.h b/packages/language/cxx/ustl/current/include/ustl/uheap.h
--- a/packages/language/cxx/ustl/current/include/ustl/uheap.h
+++ b/packages/language/cxx/ustl/current/include/ustl/uheap.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UHEAP_H_574B9EAF271A1C107190B4D575A356C5
diff --git a/packages/language/cxx/ustl/current/include/ustl/uios.h b/packages/language/cxx/ustl/current/include/ustl/uios.h
--- a/packages/language/cxx/ustl/current/include/ustl/uios.h
+++ b/packages/language/cxx/ustl/current/include/ustl/uios.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UIOS_H_630C16E316F7650E3A02E1C6611B789A
@@ -85,7 +85,7 @@ public:
     inline bool		fail (void) const		{ return (rdstate() & (badbit | failbit)); }
     inline bool		eof (void) const		{ return (rdstate() & eofbit); }
     inline bool		operator! (void) const		{ return (fail()); }
-    inline		operator void* (void) const	{ return (reinterpret_cast<void*>(!fail())); }
+    inline		operator void* (void) const	{ return ((void*)(!fail())); }
     inline void		clear (iostate v = goodbit)	{ m_State = v; }
     inline void		setstate (iostate v)		{ m_State |= v; }
     inline iostate	exceptions (void) const		{ return (m_Exceptions); }
diff --git a/packages/language/cxx/ustl/current/include/ustl/uiosfunc.h b/packages/language/cxx/ustl/current/include/ustl/uiosfunc.h
--- a/packages/language/cxx/ustl/current/include/ustl/uiosfunc.h
+++ b/packages/language/cxx/ustl/current/include/ustl/uiosfunc.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UIOSFUNC_H_730C16E316F7650E3A02E1C6611B789A
@@ -36,7 +36,7 @@ public:
     template <typename T>
     class talign : public align {
     public:
-	inline explicit		talign (void) : align (alignof (NullValue<T>())) {}
+	inline explicit		talign (void) : align (stream_align_of (NullValue<T>())) {}
     };
 
     /// \class skip uiosfunc.h ustl.h
diff --git a/packages/language/cxx/ustl/current/include/ustl/uiterator.h b/packages/language/cxx/ustl/current/include/ustl/uiterator.h
--- a/packages/language/cxx/ustl/current/include/ustl/uiterator.h
+++ b/packages/language/cxx/ustl/current/include/ustl/uiterator.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 //
 /// \file uiterator.h
@@ -125,7 +125,7 @@ public:
     				    { m_ip = m_rCtr.insert (m_ip, v); return (*this); }
     inline insert_iterator&	operator* (void)  { return (*this); }
     inline insert_iterator&	operator++ (void) { ++ m_ip; return (*this); }
-    inline insert_iterator	operator++ (int)  { insert_iterator prev (*this); ++ m_ip; return (*this); }
+    inline insert_iterator	operator++ (int)  { insert_iterator prev (*this); ++m_ip; return (prev); }
 protected:
     Container&			m_rCtr;
     iterator			m_ip;
diff --git a/packages/language/cxx/ustl/current/include/ustl/ulaalgo.h b/packages/language/cxx/ustl/current/include/ustl/ulaalgo.h
--- a/packages/language/cxx/ustl/current/include/ustl/ulaalgo.h
+++ b/packages/language/cxx/ustl/current/include/ustl/ulaalgo.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef ULAALGO_H_2E403D182E83FB596AFB800E68B255A1
@@ -204,8 +204,7 @@ static tuple<4,float> operator* (const t
 #else	// If no processor extensions, just unroll the multiplication
 
 /// Specialization for 4-component vector transform, the slow part of 3D graphics.
-template <>
-static tuple<4,float> operator* (const tuple<4,float>& t, const matrix<4,4,float>& m)
+template <> inline tuple<4,float> operator* (const tuple<4,float>& t, const matrix<4,4,float>& m)
 {
     tuple<4,float> tr;
     for (uoff_t i = 0; i < 4; ++ i)
diff --git a/packages/language/cxx/ustl/current/include/ustl/ulimits.h b/packages/language/cxx/ustl/current/include/ustl/ulimits.h
--- a/packages/language/cxx/ustl/current/include/ustl/ulimits.h
+++ b/packages/language/cxx/ustl/current/include/ustl/ulimits.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef ULIMITS_H_1C2192EA3821E0811BBAF86B0F048364
@@ -85,20 +85,6 @@ struct numeric_limits<type> {					\
 #define NUMERIC_LIMITS(type, minVal, maxVal, bSigned, bInteger, bIntegral)	\
 namespace ustl { _NUMERIC_LIMITS (type, minVal, maxVal, bSigned, bInteger, bIntegral); }
 
-/// \brief Returns the recommended stream alignment for type \p T. Override with ALIGNOF.
-/// Because this is occasionally called with a null value, do not access the argument!
-template <typename T>
-inline size_t alignof (const T&)
-{
-    if (numeric_limits<T>::is_integral)
-	return (__alignof__(T));
-    return (4);
-}
-
-#define ALIGNOF(type,grain)	\
-namespace ustl {		\
-    template <> inline size_t alignof (const type&) { return (grain); } }
-
 } // namespace ustl
 
 #endif
diff --git a/packages/language/cxx/ustl/current/include/ustl/ulist.h b/packages/language/cxx/ustl/current/include/ustl/ulist.h
--- a/packages/language/cxx/ustl/current/include/ustl/ulist.h
+++ b/packages/language/cxx/ustl/current/include/ustl/ulist.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef ULIST_H_54E3B510498982C87A0A1E1932E6729D
@@ -50,9 +50,8 @@ public:
 template <typename T>
 void list<T>::merge (list& l)
 {
-    list<T>::resize (size() + l.size());
-    iterator me = merge (begin(), end(), l.begin(), l.end(), begin());
-    list<T>::resize (distance (begin(), me));
+    insert_space (begin(), l.size());
+    ::ustl::merge (iat(l.size()), end(), l.begin(), l.end(), begin());
 }
 
 /// Moves the range [first, last) from \p l to this list at \p ip.
diff --git a/packages/language/cxx/ustl/current/include/ustl/umap.h b/packages/language/cxx/ustl/current/include/ustl/umap.h
--- a/packages/language/cxx/ustl/current/include/ustl/umap.h
+++ b/packages/language/cxx/ustl/current/include/ustl/umap.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UMAP_H_45643F516E02A87A3DCEA5024052A6F5
@@ -16,14 +16,14 @@ namespace ustl {
 ///
 /// \brief A sorted associative container of pair<K,V>
 ///
-template <typename K, typename V>
+template <typename K, typename V, typename Comp = less<K> >
 class map : public vector<pair<K,V> > {
 public:
     typedef K						key_type;
     typedef V						data_type;
     typedef const K&					const_key_ref;
     typedef const V&					const_data_ref;
-    typedef const map<K,V>&				rcself_t;
+    typedef const map<K,V,Comp>&			rcself_t;
     typedef vector<pair<K,V> >				base_class;
     typedef typename base_class::value_type		value_type;
     typedef typename base_class::size_type		size_type;
@@ -39,10 +39,10 @@ public:
     typedef pair<iterator,iterator>			range_t;
     typedef pair<iterator,bool>				insertrv_t;
 public:
-    inline			map (void)			: vector<pair<K,V> > () {}
-    explicit inline		map (size_type n)		: vector<pair<K,V> > (n) {}
-    inline			map (rcself_t v)		: vector<pair<K,V> > (v) {}
-    inline			map (const_iterator i1, const_iterator i2) : vector<pair<K,V> >() { insert (i1, i2); }
+    inline			map (void)			: base_class() {}
+    explicit inline		map (size_type n)		: base_class (n) {}
+    inline			map (rcself_t v)		: base_class (v) {}
+    inline			map (const_iterator i1, const_iterator i2) : base_class() { insert (i1, i2); }
     inline rcself_t		operator= (rcself_t v)		{ base_class::operator= (v); return (*this); }
     inline const_data_ref	operator[] (const_key_ref i) const;
     data_type&			operator[] (const_key_ref i);
@@ -56,25 +56,29 @@ public:
     inline const_iterator	find (const_key_ref k) const;
     inline iterator		find (const_key_ref k)	{ return (const_cast<iterator> (const_cast<rcself_t>(*this).find (k))); }
     inline const_iterator	find_data (const_data_ref v, const_iterator first = NULL, const_iterator last = NULL) const;
-    inline iterator		find_data (const_data_ref v, iterator first = NULL, iterator last = NULL);
+    inline iterator		find_data (const_data_ref v, iterator first = NULL, iterator last = NULL)	{ return (const_cast<iterator> (find_data (v, const_cast<const_iterator>(first), const_cast<const_iterator>(last)))); }
     insertrv_t			insert (const_reference v);
+    inline iterator		insert (iterator, const_reference v)	{ return (insert(v).first); }
     void			insert (const_iterator i1, const_iterator i2);
     inline void			erase (const_key_ref k);
     inline iterator		erase (iterator ep)	{ return (base_class::erase (ep)); }
     inline iterator		erase (iterator ep1, iterator ep2) { return (base_class::erase (ep1, ep2)); }
     inline void			clear (void)		{ base_class::clear(); }
-private:
     const_iterator		lower_bound (const_key_ref k) const;
     inline iterator		lower_bound (const_key_ref k) { return (const_cast<iterator>(const_cast<rcself_t>(*this).lower_bound (k))); }
+    const_iterator		upper_bound (const_key_ref k) const;
+    inline iterator		upper_bound (const_key_ref k) { return (const_cast<iterator>(const_cast<rcself_t>(*this).upper_bound (k))); }
+    const_range_t		equal_range (const_key_ref k) const;
+    inline range_t		equal_range (const_key_ref k) { return (const_cast<const_range_t>(const_cast<rcself_t>(*this).equal_range (k))); }
 };
 
-template <typename K, typename V>
-typename map<K,V>::const_iterator map<K,V>::lower_bound (const_key_ref k) const
+template <typename K, typename V, typename Comp>
+typename map<K,V,Comp>::const_iterator map<K,V,Comp>::lower_bound (const_key_ref k) const
 {
     const_iterator first (begin()), last (end());
     while (first != last) {
 	const_iterator mid = advance (first, distance (first,last) / 2);
-	if (mid->first < k)
+	if (Comp()(mid->first, k))
 	    first = advance (mid, 1);
 	else
 	    last = mid;
@@ -82,17 +86,41 @@ typename map<K,V>::const_iterator map<K,
     return (first);
 }
 
+template <typename K, typename V, typename Comp>
+typename map<K,V,Comp>::const_iterator map<K,V,Comp>::upper_bound (const_key_ref k) const
+{
+    const_iterator first (begin()), last (end());
+    while (first != last) {
+	const_iterator mid = advance (first, distance (first,last) / 2);
+	if (Comp()(k, mid->first))
+	    last = mid;
+	else
+	    first = mid + 1;
+    }
+    return (last);
+}
+
+template <typename K, typename V, typename Comp>
+typename map<K,V,Comp>::const_range_t map<K,V,Comp>::equal_range (const_key_ref k) const
+{
+    const_range_t rv;
+    rv.second = rv.first = lower_bound (k);
+    while (rv.second != end() && !Comp()(k, rv.second->first))
+	++rv.second;
+    return (rv);
+}
+
 /// Returns the pair<K,V> where K = \p k.
-template <typename K, typename V>
-inline typename map<K,V>::const_iterator map<K,V>::find (const_key_ref k) const
+template <typename K, typename V, typename Comp>
+inline typename map<K,V,Comp>::const_iterator map<K,V,Comp>::find (const_key_ref k) const
 {
     const_iterator i = lower_bound (k);
-    return ((i < end() && k < i->first) ? end() : i);
+    return ((i < end() && Comp()(k,i->first)) ? end() : i);
 }
 
 /// Returns the pair<K,V> where V = \p v, occuring in range [first,last).
-template <typename K, typename V>
-inline typename map<K,V>::const_iterator map<K,V>::find_data (const_data_ref v, const_iterator first, const_iterator last) const
+template <typename K, typename V, typename Comp>
+inline typename map<K,V,Comp>::const_iterator map<K,V,Comp>::find_data (const_data_ref v, const_iterator first, const_iterator last) const
 {
     if (!first) first = begin();
     if (!last) last = end();
@@ -100,55 +128,48 @@ inline typename map<K,V>::const_iterator
     return (first);
 }
 
-/// Returns the pair<K,V> where V = \p v, occuring in range [first,last).
-template <typename K, typename V>
-inline typename map<K,V>::iterator map<K,V>::find_data (const_data_ref v, iterator first, iterator last)
-{
-    return (const_cast<iterator> (find_data (v, const_cast<const_iterator>(first), const_cast<const_iterator>(last))));
-}
-
 /// Returns data associated with key \p k.
-template <typename K, typename V>
-inline const typename map<K,V>::data_type& map<K,V>::operator[] (const_key_ref k) const
+template <typename K, typename V, typename Comp>
+inline const typename map<K,V,Comp>::data_type& map<K,V,Comp>::operator[] (const_key_ref k) const
 {
     assert (find(k) != end() && "operator[] const can not insert non-existent keys");
     return (find(k)->second);
 }
 
 /// Returns data associated with key \p k.
-template <typename K, typename V>
-typename map<K,V>::data_type& map<K,V>::operator[] (const_key_ref k)
+template <typename K, typename V, typename Comp>
+typename map<K,V,Comp>::data_type& map<K,V,Comp>::operator[] (const_key_ref k)
 {
     iterator ip = lower_bound (k);
-    if (ip == end() || k < ip->first)
+    if (ip == end() || Comp()(k,ip->first))
 	ip = base_class::insert (ip, make_pair (k, V()));
     return (ip->second);
 }
 
 /// Inserts the pair into the container.
-template <typename K, typename V>
-typename map<K,V>::insertrv_t map<K,V>::insert (const_reference v)
+template <typename K, typename V, typename Comp>
+typename map<K,V,Comp>::insertrv_t map<K,V,Comp>::insert (const_reference v)
 {
     iterator ip = lower_bound (v.first);
-    bool bInserted = ip == end() || v.first < ip->first;
+    bool bInserted = ip == end() || Comp()(v.first, ip->first);
     if (bInserted)
 	ip = base_class::insert (ip, v);
     return (make_pair (ip, bInserted));
 }
 
 /// Inserts elements from range [i1,i2) into the container.
-template <typename K, typename V>
-void map<K,V>::insert (const_iterator i1, const_iterator i2)
+template <typename K, typename V, typename Comp>
+void map<K,V,Comp>::insert (const_iterator i1, const_iterator i2)
 {
     assert (i1 <= i2);
-    reserve (size() + distance (i1, i2));
+    base_class::reserve (size() + distance (i1, i2));
     for (; i1 != i2; ++i1)
 	insert (*i1);
 }
 
 /// Erases the element with key value \p k.
-template <typename K, typename V>
-inline void map<K,V>::erase (const_key_ref k)
+template <typename K, typename V, typename Comp>
+inline void map<K,V,Comp>::erase (const_key_ref k)
 {
     iterator ip = find (k);
     if (ip != end())
diff --git a/packages/language/cxx/ustl/current/include/ustl/umatrix.h b/packages/language/cxx/ustl/current/include/ustl/umatrix.h
--- a/packages/language/cxx/ustl/current/include/ustl/umatrix.h
+++ b/packages/language/cxx/ustl/current/include/ustl/umatrix.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UMATRIX_H_740EBFEF554E833645E0FD72419A8185
diff --git a/packages/language/cxx/ustl/current/include/ustl/umemory.h b/packages/language/cxx/ustl/current/include/ustl/umemory.h
--- a/packages/language/cxx/ustl/current/include/ustl/umemory.h
+++ b/packages/language/cxx/ustl/current/include/ustl/umemory.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UMEMORY_H_4AB5B0DB5BF09140541409CC47BCD17A
@@ -75,8 +75,10 @@ template <typename ForwardIterator>
 inline void construct (ForwardIterator first, ForwardIterator last)
 {
     typedef typename iterator_traits<ForwardIterator>::value_type value_type;
-    if (!numeric_limits<value_type>::is_integral && first)
-	for (--last; first <= last; ++first)
+    if (numeric_limits<value_type>::is_integral)
+	memset (first, 0, distance(first,last)*sizeof(value_type));
+    else
+	for (--last; intptr_t(first) <= intptr_t(last); ++first)
 	    construct (&*first);
 }
 
@@ -101,7 +103,7 @@ inline void destroy (T* p) throw()
 // Helper templates to not instantiate anything for integral types.
 template <typename T>
 void dtors (T first, T last) throw()
-    { for (--last; first <= last; ++first) destroy (&*first); }
+    { for (--last; intptr_t(first) <= intptr_t(last); ++first) destroy (&*first); }
 template <typename T, bool bIntegral>
 struct Sdtorsr {
     inline void operator()(T first, T last) throw() { dtors (first, last); }
diff --git a/packages/language/cxx/ustl/current/include/ustl/umultimap.h b/packages/language/cxx/ustl/current/include/ustl/umultimap.h
--- a/packages/language/cxx/ustl/current/include/ustl/umultimap.h
+++ b/packages/language/cxx/ustl/current/include/ustl/umultimap.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UMULTIMAP_H_45743F516E02A87A3FCEA5024052A6F5
@@ -16,20 +16,20 @@ namespace ustl {
 ///
 /// \brief A sorted associative container that may container multiple entries for each key.
 ///
-template <typename K, typename V>
+template <typename K, typename V, typename Comp = less<K> >
 class multimap : public vector<pair<K,V> > {
 public:
     typedef K						key_type;
     typedef V						data_type;
     typedef const K&					const_key_ref;
     typedef const V&					const_data_ref;
-    typedef const multimap<K,V>&			rcself_t;
+    typedef const multimap<K,V,Comp>&			rcself_t;
     typedef vector<pair<K,V> >				base_class;
-    typedef typename base_class::value_type	value_type;
-    typedef typename base_class::size_type	size_type;
-    typedef typename base_class::pointer	pointer;
-    typedef typename base_class::const_pointer	const_pointer;
-    typedef typename base_class::reference	reference;
+    typedef typename base_class::value_type		value_type;
+    typedef typename base_class::size_type		size_type;
+    typedef typename base_class::pointer		pointer;
+    typedef typename base_class::const_pointer		const_pointer;
+    typedef typename base_class::reference		reference;
     typedef typename base_class::const_reference	const_reference;
     typedef typename base_class::const_iterator		const_iterator;
     typedef typename base_class::iterator		iterator;
@@ -38,10 +38,10 @@ public:
     typedef pair<const_iterator,const_iterator>		const_range_t;
     typedef pair<iterator,iterator>			range_t;
 public:
-    inline			multimap (void)		: vector<pair<K,V> > () {} 
-    explicit inline		multimap (size_type n)	: vector<pair<K,V> > (n) {} 
-    inline			multimap (rcself_t v)	: vector<pair<K,V> > (v) {} 
-    inline			multimap (const_iterator i1, const_iterator i2)	: vector<pair<K,V> > () { insert (i1, i2); } 
+    inline			multimap (void)		: base_class() {}
+    explicit inline		multimap (size_type n)	: base_class (n) {}
+    inline			multimap (rcself_t v)	: base_class (v) {}
+    inline			multimap (const_iterator i1, const_iterator i2)	: base_class() { insert (i1, i2); }
     inline rcself_t		operator= (rcself_t v)	{ base_class::operator= (v); return (*this); }
     inline size_type		size (void) const	{ return (base_class::size()); }
     inline iterator		begin (void)		{ return (base_class::begin()); }
@@ -51,11 +51,15 @@ public:
     inline void			assign (const_iterator i1, const_iterator i2) { clear(); insert (i1, i2); }
     inline size_type		count (const_key_ref k) const		{ return (upper_bound(k) - lower_bound(k)); }
     inline void			push_back (const_reference v)		{ insert (v); }
+    inline const_iterator	find (const_key_ref k) const;
+    inline iterator		find (const_key_ref k)			{ return (const_cast<iterator> (const_cast<rcself_t>(*this).find (k))); }
     inline const_range_t	equal_range (const_key_ref k) const	{ return (make_pair (lower_bound(k), upper_bound(k))); }
     inline range_t		equal_range (const_key_ref k)		{ return (make_pair (const_cast<iterator>(lower_bound(k)), const_cast<iterator>(upper_bound(k)))); }
     const_iterator		lower_bound (const_key_ref k) const;
+    inline iterator		lower_bound (const_key_ref k)		{ return (const_cast<iterator> (const_cast<rcself_t>(*this).lower_bound (k))); }
     const_iterator		upper_bound (const_key_ref k) const;
-    inline iterator		insert (const_reference v);
+    inline iterator		upper_bound (const_key_ref k)		{ return (const_cast<iterator> (const_cast<rcself_t>(*this).upper_bound (k))); }
+    inline iterator		insert (const_reference v)		{ return (base_class::insert (upper_bound (v.first), v)); }
     void			insert (const_iterator i1, const_iterator i2);
     inline void			erase (const_key_ref k)			{ erase (const_cast<iterator>(lower_bound(k)), const_cast<iterator>(upper_bound(k))); }
     inline iterator		erase (iterator ep)			{ return (base_class::erase (ep)); } 
@@ -64,13 +68,13 @@ public:
 };
 
 /// Returns an iterator to the first element with key value \p k.
-template <typename K, typename V>
-typename multimap<K,V>::const_iterator multimap<K,V>::lower_bound (const_key_ref k) const
+template <typename K, typename V, typename Comp>
+typename multimap<K,V,Comp>::const_iterator multimap<K,V,Comp>::lower_bound (const_key_ref k) const
 {
     const_iterator first (begin()), last (end());
     while (first != last) {
 	const_iterator mid = advance (first, distance (first,last) / 2);
-	if (mid->first < k)
+	if (Comp()(mid->first, k))
 	    first = advance (mid, 1);
 	else
 	    last = mid;
@@ -79,13 +83,13 @@ typename multimap<K,V>::const_iterator m
 }
 
 /// Returns an iterator to the first element with key value \p k.
-template <typename K, typename V>
-typename multimap<K,V>::const_iterator multimap<K,V>::upper_bound (const_key_ref k) const
+template <typename K, typename V, typename Comp>
+typename multimap<K,V,Comp>::const_iterator multimap<K,V,Comp>::upper_bound (const_key_ref k) const
 {
     const_iterator first (begin()), last (end());
     while (first != last) {
 	const_iterator mid = advance (first, distance (first,last) / 2);
-	if (k < mid->first)
+	if (Comp()(k, mid->first))
 	    last = mid;
 	else
 	    first = advance (mid, 1);
@@ -93,20 +97,20 @@ typename multimap<K,V>::const_iterator m
     return (last);
 }
 
-/// Inserts the pair into the container.
-template <typename K, typename V>
-inline typename multimap<K,V>::iterator multimap<K,V>::insert (const_reference v)
+/// Returns the pair<K,V> where K = \p k.
+template <typename K, typename V, typename Comp>
+inline typename multimap<K,V,Comp>::const_iterator multimap<K,V,Comp>::find (const_key_ref k) const
 {
-    iterator ip = const_cast<iterator> (upper_bound (v.first));
-    return (base_class::insert (ip, v));
+    const_iterator i = lower_bound (k);
+    return ((i < end() && Comp()(k, i->first)) ? end() : i);
 }
 
 /// Inserts elements from range [i1,i2) into the container.
-template <typename K, typename V>
-void multimap<K,V>::insert (const_iterator i1, const_iterator i2)
+template <typename K, typename V, typename Comp>
+void multimap<K,V,Comp>::insert (const_iterator i1, const_iterator i2)
 {
     assert (i1 <= i2);
-    reserve (size() + distance (i1, i2));
+    base_class::reserve (size() + distance (i1, i2));
     for (; i1 != i2; ++i1)
 	insert (*i1);
 }
diff --git a/packages/language/cxx/ustl/current/include/ustl/umultiset.h b/packages/language/cxx/ustl/current/include/ustl/umultiset.h
--- a/packages/language/cxx/ustl/current/include/ustl/umultiset.h
+++ b/packages/language/cxx/ustl/current/include/ustl/umultiset.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UMULTISET_H_446AEDBB7F61C6994DC228C25D5FA3A1
@@ -17,10 +17,10 @@ namespace ustl {
 /// \brief Multiple sorted container.
 /// Unlike set, it may contain multiple copies of each element.
 ///
-template <typename T>
+template <typename T, typename Comp = less<T> >
 class multiset : public vector<T> {
 public:
-    typedef const multiset<T>&				rcself_t;
+    typedef const multiset<T,Comp>&			rcself_t;
     typedef vector<T>					base_class;
     typedef typename base_class::value_type		value_type;
     typedef typename base_class::size_type		size_type;
@@ -33,17 +33,17 @@ public:
     typedef typename base_class::reverse_iterator	reverse_iterator;
     typedef typename base_class::const_reverse_iterator	const_reverse_iterator;
 public:
-    inline			multiset (void)		: vector<T> () {}
-    explicit inline		multiset (size_type n)	: vector<T> (n) {}
-    inline			multiset (rcself_t v)	: vector<T> (v) {} 
-    inline			multiset (const_iterator i1, const_iterator i2) : vector<T> () { insert (i1, i2); }
+    inline			multiset (void)		: base_class() {}
+    explicit inline		multiset (size_type n)	: base_class (n) {}
+    inline			multiset (rcself_t v)	: base_class (v) {}
+    inline			multiset (const_iterator i1, const_iterator i2) : base_class() { insert (i1, i2); }
     inline rcself_t		operator= (rcself_t v)	{ base_class::operator= (v); return (*this); }
     inline size_type		size (void) const	{ return (base_class::size()); }
     inline iterator		begin (void)		{ return (base_class::begin()); }
     inline const_iterator	begin (void) const	{ return (base_class::begin()); }
     inline iterator		end (void)		{ return (base_class::end()); }
     inline const_iterator	end (void) const	{ return (base_class::end()); }
-    inline void			assign (const_iterator i1, const_iterator i2);
+    inline void			assign (const_iterator i1, const_iterator i2)	{ clear(); insert (i1, i2); }
     size_type			count (const_reference v) const;
     inline void			push_back (const_reference v)	{ insert (v); }
     inline iterator		insert (const_reference v);
@@ -54,45 +54,37 @@ public:
     inline void			clear (void)		{ base_class::clear(); }
 };
 
-/// Copies contents of range [i1,i2)
-template <typename T>
-inline void multiset<T>::assign (const_iterator i1, const_iterator i2)
+/// Returns the number of elements of value \p v.
+template <typename T, typename Comp>
+typename multiset<T,Comp>::size_type multiset<T,Comp>::count (const_reference v) const
 {
-    base_class::clear();
-    insert (i1, i2);
-}
-
-/// Returns the number of elements of value \p v.
-template <typename T>
-typename multiset<T>::size_type multiset<T>::count (const_reference v) const
-{
-    const pair<const_iterator,const_iterator> fr = equal_range (begin(), end(), v);
+    const pair<const_iterator,const_iterator> fr = equal_range (begin(), end(), v, Comp());
     return (distance (fr.first, fr.second));
 }
 
 /// Inserts \p v.
-template <typename T>
-inline typename multiset<T>::iterator multiset<T>::insert (const_reference v)
+template <typename T, typename Comp>
+inline typename multiset<T,Comp>::iterator multiset<T,Comp>::insert (const_reference v)
 {
-    iterator ip = upper_bound (begin(), end(), v);
+    iterator ip = upper_bound (begin(), end(), v, Comp());
     return (base_class::insert (ip, v));
 }
 
 /// Inserts all elements from range [i1,i2).
-template <typename T>
-void multiset<T>::insert (const_iterator i1, const_iterator i2)
+template <typename T, typename Comp>
+void multiset<T,Comp>::insert (const_iterator i1, const_iterator i2)
 {
     assert (i1 <= i2);
-    reserve (size() + distance (i1, i2));
+    base_class::reserve (size() + distance (i1, i2));
     for (; i1 < i2; ++i1)
 	push_back (*i1);
 }
 
 /// Erases all elements with value \p v.
-template <typename T>
-void multiset<T>::erase (const_reference v)
+template <typename T, typename Comp>
+void multiset<T,Comp>::erase (const_reference v)
 {
-    pair<iterator,iterator> epr = equal_range (begin(), end(), v);
+    pair<iterator,iterator> epr = equal_range (begin(), end(), v, Comp());
     erase (epr.first, epr.second);
 }
 
diff --git a/packages/language/cxx/ustl/current/include/ustl/unew.h b/packages/language/cxx/ustl/current/include/ustl/unew.h
--- a/packages/language/cxx/ustl/current/include/ustl/unew.h
+++ b/packages/language/cxx/ustl/current/include/ustl/unew.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UNEW_H_11D237512B324C9C05A55DAF1BF086F1
diff --git a/packages/language/cxx/ustl/current/include/ustl/unumeric.h b/packages/language/cxx/ustl/current/include/ustl/unumeric.h
--- a/packages/language/cxx/ustl/current/include/ustl/unumeric.h
+++ b/packages/language/cxx/ustl/current/include/ustl/unumeric.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UNUMERIC_H_6C99D6F6363832C644A6FFF336E84E18
diff --git a/packages/language/cxx/ustl/current/include/ustl/upair.h b/packages/language/cxx/ustl/current/include/ustl/upair.h
--- a/packages/language/cxx/ustl/current/include/ustl/upair.h
+++ b/packages/language/cxx/ustl/current/include/ustl/upair.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UPAIR_H_7DC08F1B7FECF8AE6856D84C3B617A75
diff --git a/packages/language/cxx/ustl/current/include/ustl/upredalgo.h b/packages/language/cxx/ustl/current/include/ustl/upredalgo.h
--- a/packages/language/cxx/ustl/current/include/ustl/upredalgo.h
+++ b/packages/language/cxx/ustl/current/include/ustl/upredalgo.h
@@ -1,11 +1,13 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UPREDALGO_H_2CB058AE0807A01A2F6A51BA5D5820A5
 #define UPREDALGO_H_2CB058AE0807A01A2F6A51BA5D5820A5
 
+#include "ualgo.h"
+
 namespace ustl {
 
 /// Copy_if copies elements from the range [first, last) to the range
diff --git a/packages/language/cxx/ustl/current/include/ustl/uqueue.h b/packages/language/cxx/ustl/current/include/ustl/uqueue.h
--- a/packages/language/cxx/ustl/current/include/ustl/uqueue.h
+++ b/packages/language/cxx/ustl/current/include/ustl/uqueue.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UQUEUE_H_27F01FDB0D59B75277E0E5C41ABC6B5B
diff --git a/packages/language/cxx/ustl/current/include/ustl/uset.h b/packages/language/cxx/ustl/current/include/ustl/uset.h
--- a/packages/language/cxx/ustl/current/include/ustl/uset.h
+++ b/packages/language/cxx/ustl/current/include/ustl/uset.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef USET_H_45543F516E02A87A3FCEA5024052A6F5
@@ -15,29 +15,29 @@ namespace ustl {
 ///
 /// \brief Unique sorted container. Sorted vector with all values unique.
 ///
-template <typename T>
+template <typename T, typename Comp = less<T> >
 class set : public vector<T> {
 public:
-    typedef const set<T>&			rcself_t;
-    typedef vector<T>				base_class;
+    typedef const set<T,Comp>&				rcself_t;
+    typedef vector<T>					base_class;
     typedef typename base_class::value_type		key_type;
     typedef typename base_class::value_type		data_type;
     typedef typename base_class::value_type		value_type;
     typedef typename base_class::size_type		size_type;
-    typedef typename base_class::pointer			pointer;
+    typedef typename base_class::pointer		pointer;
     typedef typename base_class::const_pointer		const_pointer;
     typedef typename base_class::reference		reference;
-    typedef typename base_class::const_reference		const_reference;
+    typedef typename base_class::const_reference	const_reference;
     typedef typename base_class::const_iterator		const_iterator;
     typedef typename base_class::iterator		iterator;
     typedef typename base_class::reverse_iterator	reverse_iterator;
     typedef typename base_class::const_reverse_iterator	const_reverse_iterator;
     typedef pair<iterator,bool>				insertrv_t;
 public:
-    inline			set (void)		: vector<T> () { }
-    explicit inline		set (size_type n)	: vector<T> (n) { }
-    inline			set (rcself_t v)	: vector<T> (v) { } 
-    inline			set (const_iterator i1, const_iterator i2) : vector<T> () { insert (i1, i2); }
+    inline			set (void)		: base_class() { }
+    explicit inline		set (size_type n)	: base_class (n) { }
+    inline			set (rcself_t v)	: base_class (v) { }
+    inline			set (const_iterator i1, const_iterator i2) : base_class() { insert (i1, i2); }
     inline rcself_t		operator= (rcself_t v)	{ base_class::operator= (v); return (*this); }
     inline size_type		size (void) const	{ return (base_class::size()); }
     inline iterator		begin (void)		{ return (base_class::begin()); }
@@ -46,46 +46,39 @@ public:
     inline const_iterator	end (void) const	{ return (base_class::end()); }
     inline void			assign (const_iterator i1, const_iterator i2)	{ clear(); insert (i1, i2); }
     inline void			push_back (const_reference v)	{ insert (v); }
-    inline const_iterator	find (const_reference v) const	{ const_iterator i = lower_bound (begin(), end(), v); return ((i != end() && *i == v) ? i : end()); }
+    inline const_iterator	find (const_reference v) const	{ const_iterator i = lower_bound (begin(), end(), v, Comp()); return ((i != end() && *i == v) ? i : end()); }
     inline iterator		find (const_reference v)	{ return (const_cast<iterator>(const_cast<rcself_t>(*this).find (v))); }
     insertrv_t			insert (const_reference v);
+    inline iterator		insert (iterator, const_reference v)	{ return (insert(v).first); }
     inline void			insert (const_iterator i1, const_iterator i2);
-    inline void			erase (const_reference v);
-    inline iterator		erase (iterator ep)	{ return (base_class::erase (ep)); }
+    inline void			erase (const_reference v)	{ iterator ip = find (v); if (ip != end()) erase (ip); }
+    inline iterator		erase (iterator ep)		{ return (base_class::erase (ep)); }
     inline iterator		erase (iterator ep1, iterator ep2) { return (base_class::erase (ep1, ep2)); }
-    inline void			clear (void)		{ base_class::clear(); }
+    inline void			clear (void)			{ base_class::clear(); }
 };
 
 /// Inserts \p v into the container, maintaining the sort order.
-template <typename T>
-typename set<T>::insertrv_t set<T>::insert (const_reference v)
+template <typename T, typename Comp>
+typename set<T,Comp>::insertrv_t set<T,Comp>::insert (const_reference v)
 {
-    iterator ip = lower_bound (begin(), end(), v);
-    bool bInserted = (ip == end() || v < *ip);
+    Comp f;
+    iterator ip = lower_bound (begin(), end(), v, f);
+    bool bInserted = (ip == end() || f(v,*ip));
     if (bInserted)
 	ip = base_class::insert (ip, v);
     return (make_pair (ip, bInserted));
 }
 
 /// Inserts the contents of range [i1,i2)
-template <typename T>
-void set<T>::insert (const_iterator i1, const_iterator i2)
+template <typename T, typename Comp>
+void set<T,Comp>::insert (const_iterator i1, const_iterator i2)
 {
     assert (i1 <= i2);
-    reserve (size() + distance (i1, i2));
+    base_class::reserve (size() + distance (i1, i2));
     for (; i1 < i2; ++i1)
 	push_back (*i1);
 }
 
-/// Erases the element with value \p v.
-template <typename T>
-inline void set<T>::erase (const_reference v)
-{
-    iterator ip = find (v);
-    if (ip != end())
-	erase (ip);
-}
-
 } // namespace ustl
 
 #endif
diff --git a/packages/language/cxx/ustl/current/include/ustl/uspecial.h b/packages/language/cxx/ustl/current/include/ustl/uspecial.h
--- a/packages/language/cxx/ustl/current/include/ustl/uspecial.h
+++ b/packages/language/cxx/ustl/current/include/ustl/uspecial.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef USPECIAL_H_947ADYOU0ARE3YOU2REALLY8ARE44CE0
@@ -46,9 +46,9 @@ template <typename T1, typename T2>
 istream& operator>> (istream& is, pair<T1,T2>& p)
 {
     is >> p.first;
-    is.align (alignof(p.second));
+    is.align (stream_align_of(p.second));
     is >> p.second;
-    is.align (alignof(p.first));
+    is.align (stream_align_of(p.first));
     return (is);
 }
 
@@ -57,9 +57,9 @@ template <typename T1, typename T2>
 ostream& operator<< (ostream& os, const pair<T1,T2>& p)
 {
     os << p.first;
-    os.align (alignof(p.second));
+    os.align (stream_align_of(p.second));
     os << p.second;
-    os.align (alignof(p.first));
+    os.align (stream_align_of(p.first));
     return (os);
 }
 
@@ -76,8 +76,8 @@ template <typename T1, typename T2>
 struct object_stream_size<pair<T1,T2> > {
     inline size_t operator()(const pair<T1,T2>& v) const
     {
-	return (Align (stream_size_of(v.first), alignof(v.second)) +
-		Align (stream_size_of(v.second), alignof(v.first)));
+	return (Align (stream_size_of(v.first), stream_align_of(v.second)) +
+		Align (stream_size_of(v.second), stream_align_of(v.first)));
     }
 };
 
@@ -111,10 +111,10 @@ unconst (const pair<typename Container::
 //----{ vector }--------------------------------------------------------
 
 template <typename T>
-inline size_t alignof (const vector<T>&)
+inline size_t stream_align_of (const vector<T>&)
 {
     typedef typename vector<T>::written_size_type written_size_type;
-    return (alignof (written_size_type()));
+    return (stream_align_of (written_size_type()));
 }
 
 //----{ bitset }--------------------------------------------------------
@@ -152,7 +152,7 @@ struct numeric_limits<tuple<N,T> > {
 };
 
 template <size_t N, typename T>
-inline size_t alignof (const tuple<N,T>&) { return (alignof (NullValue<T>())); }
+inline size_t stream_align_of (const tuple<N,T>&) { return (stream_align_of (NullValue<T>())); }
 
 template <typename T, typename IntT>
 inline ostringstream& chartype_text_write (ostringstream& os, const T& v)
@@ -257,4 +257,7 @@ CAST_STREAMABLE(bool, uint8_t)
 ALIGNOF (_long4grain, 4)
 #endif
 
+ALIGNOF(ustl::CBacktrace, sizeof(void*))
+ALIGNOF (ustl::string, stream_align_of (string::value_type()))
+
 #endif
diff --git a/packages/language/cxx/ustl/current/include/ustl/ustack.h b/packages/language/cxx/ustl/current/include/ustl/ustack.h
--- a/packages/language/cxx/ustl/current/include/ustl/ustack.h
+++ b/packages/language/cxx/ustl/current/include/ustl/ustack.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef USTACK_H_5242F5635322B2EC44A9AEE73022C6E9
diff --git a/packages/language/cxx/ustl/current/include/ustl/ustdxept.h b/packages/language/cxx/ustl/current/include/ustl/ustdxept.h
--- a/packages/language/cxx/ustl/current/include/ustl/ustdxept.h
+++ b/packages/language/cxx/ustl/current/include/ustl/ustdxept.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef USTDXEPT_H_46F7AE967738B588038F95E41158D7FF
diff --git a/packages/language/cxx/ustl/current/include/ustl/ustring.h b/packages/language/cxx/ustl/current/include/ustl/ustring.h
--- a/packages/language/cxx/ustl/current/include/ustl/ustring.h
+++ b/packages/language/cxx/ustl/current/include/ustl/ustring.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef USTRING_H_1249CB7A098A9010763AAC6D37B133CF
@@ -55,7 +55,7 @@ public:
     typedef ::ustl::reverse_iterator<iterator>		reverse_iterator;
     typedef ::ustl::reverse_iterator<const_iterator>	const_reverse_iterator;
     typedef utf8in_iterator<const_iterator>		utf8_iterator;
-    static const uoff_t npos = static_cast<uoff_t>(-1);	///< Value that means the end of string.
+    static const size_type npos = INT_MAX;		///< Value that means the end of string.
 public:
     inline			string (void)		: memblock () { relink ("",0); }
 				string (const string& s);
@@ -84,8 +84,8 @@ public:
     inline utf8_iterator	utf8_end (void) const	{ return (utf8_iterator (end())); }
     inline const_reference	at (uoff_t pos) const	{ assert (pos <= size() && begin()); return (begin()[pos]); }
     inline reference		at (uoff_t pos)		{ assert (pos <= size() && begin()); return (begin()[pos]); }
-    inline const_iterator	iat (uoff_t pos) const	{ return (begin() + min (pos, size())); }
-    inline iterator		iat (uoff_t pos)	{ return (begin() + min (pos, size())); }
+    inline const_iterator	iat (uoff_t pos) const	{ return (begin() + (__builtin_constant_p(pos) && pos >= npos ? size() : min(pos,size()))); }
+    inline iterator		iat (uoff_t pos)	{ return (const_cast<iterator>(const_cast<const string*>(this)->iat(pos))); }
     const_iterator		wiat (uoff_t i) const;
     inline iterator		wiat (uoff_t i)		{ return (const_cast<iterator>(const_cast<const string*>(this)->wiat(i))); }
     inline const_reference	back (void) const	{ return (at(size()-1)); }
@@ -142,7 +142,7 @@ public:
     inline void			insert (uoff_t ip, size_type n, value_type c)			{ insert (iat(ip), c, n); }
     inline void			insert (uoff_t ip, const string& s, uoff_t sp, size_type slen)	{ insert (iat(ip), s.iat(sp), s.iat(sp + slen)); }
     iterator			erase (iterator epo, size_type n = 1);
-    void			erase (uoff_t epo, size_type n = 1);
+    void			erase (uoff_t epo = 0, size_type n = 1);
     inline iterator		erase (iterator first, const_iterator last)	{ return (erase (first, size_type(distance(first,last)))); }
     inline void			eraser (uoff_t first, uoff_t last)		{ erase (iat(first), iat(last)); }
     inline void			push_back (const_reference c)	{ append (1, c); }
@@ -251,6 +251,8 @@ PTR_STRING_CMP (operator>,  (s2 <  s1))
 PTR_STRING_CMP (operator>=, (s2 <= s1))
 #undef PTR_STRING_CMP
 
+inline string operator+ (const char* cs, const string& ss) { string r; r.reserve (strlen(cs)+ss.size()); r += cs; r += ss; return (r); }
+
 //----------------------------------------------------------------------
 
 inline hashvalue_t hash_value (const char* first, const char* last)
@@ -262,7 +264,4 @@ inline hashvalue_t hash_value (const cha
 
 } // namespace ustl
 
-// Specialization for stream alignment
-ALIGNOF (ustl::string, alignof (string::value_type()))
-
 #endif
diff --git a/packages/language/cxx/ustl/current/include/ustl/utf8.h b/packages/language/cxx/ustl/current/include/ustl/utf8.h
--- a/packages/language/cxx/ustl/current/include/ustl/utf8.h
+++ b/packages/language/cxx/ustl/current/include/ustl/utf8.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 //
 // This file contains stream iterators that read and write UTF-8 encoded
diff --git a/packages/language/cxx/ustl/current/include/ustl/utuple.h b/packages/language/cxx/ustl/current/include/ustl/utuple.h
--- a/packages/language/cxx/ustl/current/include/ustl/utuple.h
+++ b/packages/language/cxx/ustl/current/include/ustl/utuple.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UTUPLE_H_7324ADEC49B397CA74A56F6050FD5A6B
diff --git a/packages/language/cxx/ustl/current/include/ustl/utypes.h b/packages/language/cxx/ustl/current/include/ustl/utypes.h
--- a/packages/language/cxx/ustl/current/include/ustl/utypes.h
+++ b/packages/language/cxx/ustl/current/include/ustl/utypes.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UTYPES_H_118BBB3B50B7DBF22F5460C52E515C83
diff --git a/packages/language/cxx/ustl/current/include/ustl/uutility.h b/packages/language/cxx/ustl/current/include/ustl/uutility.h
--- a/packages/language/cxx/ustl/current/include/ustl/uutility.h
+++ b/packages/language/cxx/ustl/current/include/ustl/uutility.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 //
 /// \file uutility.h
@@ -96,7 +96,7 @@ inline T* NullPointer (void)
     { return ((T*) NULL); }
 
 /// \brief Returns a non-dereferentiable value reference.
-/// This is useful for passing to alignof or the like which need a value but
+/// This is useful for passing to stream_align_of or the like which need a value but
 /// don't need to actually use it.
 template <typename T>
 inline T& NullValue (void)
@@ -145,11 +145,13 @@ UNVOID_DISTANCE(const,)
 #undef UNVOID_DISTANCE
 #endif
 
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
 // The compiler issues a warning if an unsigned type is compared to 0.
 template <typename T, bool IsSigned> struct __is_negative { inline bool operator()(const T& v) { return (v < 0); } };
 template <typename T> struct __is_negative<T,false> { inline bool operator()(const T&) { return (false); } };
 /// Warning-free way to check if \p v is negative, even if for unsigned types.
 template <typename T> inline bool is_negative (const T& v) { return (__is_negative<T,numeric_limits<T>::is_signed>()(v)); }
+#endif
 
 /// \brief Returns the absolute value of \p v
 /// Unlike the stdlib functions, this is inline and works with all types.
@@ -308,9 +310,6 @@ inline T1 DivRU (T1 n1, T2 n2)
     return ((n1 + adj) / n2);
 }
 
-#if __GNUC__ >= 3
-inline bool TestAndSet (int* pm) INLINE;
-#endif
 /// Sets the contents of \p pm to 1 and returns true if the previous value was 0.
 inline bool TestAndSet (int* pm)
 {
@@ -339,6 +338,69 @@ inline bool TestAndSet (int* pm)
 #endif
 }
 
+/// Returns the index of the first set bit in \p v or \p nbv if none.
+inline uoff_t FirstBit (uint32_t v, uoff_t nbv)
+{
+    uoff_t n = nbv;
+#if __i386__ || __x86_64__
+    if (!__builtin_constant_p(v)) asm ("bsr\t%1, %k0":"+r,r"(n):"r,m"(v)); else
+#endif
+#if __GNUC__
+    if (v) n = 31 - __builtin_clz(v);
+#else
+    if (v) for (uint32_t m = uint32_t(1)<<(n=31); !(v & m); m >>= 1) --n;
+#endif
+    return (n);
+}
+/// Returns the index of the first set bit in \p v or \p nbv if none.
+inline uoff_t FirstBit (uint64_t v, uoff_t nbv)
+{
+    uoff_t n = nbv;
+#if __x86_64__
+    if (!__builtin_constant_p(v)) asm ("bsr\t%1, %0":"+r,r"(n):"r,m"(v)); else
+#endif
+#if __GNUC__
+    if (v) n = 63 - __builtin_clzl(v);
+#else
+    if (v) for (uint64_t m = uint64_t(1)<<(n=63); !(v & m); m >>= 1) --n;
+#endif
+    return (n);
+}
+
+/// Returns the next power of 2 >= \p v.
+/// Values larger than UINT32_MAX/2 will return 2^0
+inline uint32_t NextPow2 (uint32_t v)
+{
+    uint32_t r = v-1;
+#if __i386__ || __x86_64__
+    if (!__builtin_constant_p(r)) asm("bsr\t%0, %0":"+r"(r)); else
+#endif
+    { r = FirstBit(r,r); if (r >= BitsInType(r)-1) r = uint32_t(-1); }
+    return (1<<(1+r));
+}
+
+/// Bitwise rotate value left
+template <typename T>
+inline T Rol (T v, size_t n)
+{
+#if __i386__ || __x86_64__
+    if (!(__builtin_constant_p(v) && __builtin_constant_p(n))) asm("rol\t%b1, %0":"+r,r"(v):"i,c"(n)); else
+#endif
+    v = (v << n) | (v >> (BitsInType(T)-n));
+    return (v);
+}
+
+/// Bitwise rotate value right
+template <typename T>
+inline T Ror (T v, size_t n)
+{
+#if __i386__ || __x86_64__
+    if (!(__builtin_constant_p(v) && __builtin_constant_p(n))) asm("ror\t%b1, %0":"+r,r"(v):"i,c"(n)); else
+#endif
+    v = (v >> n) | (v << (BitsInType(T)-n));
+    return (v);
+}
+
 /// \brief This template is to be used for dereferencing a type-punned pointer without a warning.
 ///
 /// When casting a local variable to an unrelated type through a pointer (for
@@ -368,7 +430,6 @@ inline DEST noalias_cast (SRC s)
 
 namespace simd {
     /// Call after you are done using SIMD algorithms for 64 bit tuples.
-    inline void reset_mmx (void) INLINE;
     #define ALL_MMX_REGS_CHANGELIST "mm0","mm1","mm2","mm3","mm4","mm5","mm6","mm7","st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)"
 #if CPU_HAS_3DNOW
     inline void reset_mmx (void) { asm ("femms":::ALL_MMX_REGS_CHANGELIST); }
diff --git a/packages/language/cxx/ustl/current/include/ustl/uvector.h b/packages/language/cxx/ustl/current/include/ustl/uvector.h
--- a/packages/language/cxx/ustl/current/include/ustl/uvector.h
+++ b/packages/language/cxx/ustl/current/include/ustl/uvector.h
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef UVECTOR_H_00BB13AF082BEB7829C031B265518169
@@ -8,6 +8,7 @@
 
 #include "memblock.h"
 #include "umemory.h"
+#include "upredalgo.h"
 
 namespace ustl {
 
@@ -98,7 +99,7 @@ public:
     inline void			write (ostream& os) const		{ container_write (os, *this); }
     inline void			text_write (ostringstream& os) const	{ container_text_write (os, *this); }
     inline size_t		stream_size (void) const		{ return (container_stream_size (*this)); }
-private:
+protected:
     inline iterator		insert_space (iterator ip, size_type n);
 private:
     memblock			m_Data;	///< Raw element data, consecutively stored.
diff --git a/packages/language/cxx/ustl/current/src/bktrace.cpp b/packages/language/cxx/ustl/current/src/bktrace.cpp
--- a/packages/language/cxx/ustl/current/src/bktrace.cpp
+++ b/packages/language/cxx/ustl/current/src/bktrace.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2006-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2006 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "bktrace.h"
@@ -109,7 +109,7 @@ void CBacktrace::text_write (ostringstre
 /// Reads the object from stream \p is.
 void CBacktrace::read (istream& is)
 {
-    assert (is.aligned (alignof (m_Addresses[0])) && "Backtrace object contains pointers and must be void* aligned");
+    assert (is.aligned (stream_align_of (m_Addresses[0])) && "Backtrace object contains pointers and must be void* aligned");
     is >> m_nFrames >> m_SymbolsSize;
     nfree (m_Symbols);
     m_Symbols = (char*) malloc (m_SymbolsSize + 1);
@@ -122,7 +122,7 @@ void CBacktrace::read (istream& is)
 /// Writes the object to stream \p os.
 void CBacktrace::write (ostream& os) const
 {
-    assert (os.aligned (alignof (m_Addresses[0])) && "Backtrace object contains pointers and must be void* aligned");
+    assert (os.aligned (stream_align_of (m_Addresses[0])) && "Backtrace object contains pointers and must be void* aligned");
     os << m_nFrames << m_SymbolsSize;
     os.write (m_Symbols, m_SymbolsSize);
     os.align();
diff --git a/packages/language/cxx/ustl/current/src/cmemlink.cpp b/packages/language/cxx/ustl/current/src/cmemlink.cpp
--- a/packages/language/cxx/ustl/current/src/cmemlink.cpp
+++ b/packages/language/cxx/ustl/current/src/cmemlink.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "cmemlink.h"
@@ -40,7 +40,7 @@ void cmemlink::write (ostream& os) const
     assert (sz == size() && "No support for writing memblocks larger than 4G");
     os << sz;
     os.write (cdata(), sz);
-    os.align (alignof (sz));
+    os.align (stream_align_of (sz));
 }
 
 /// Writes the object to stream \p os
@@ -53,7 +53,7 @@ void cmemlink::text_write (ostringstream
 cmemlink::size_type cmemlink::stream_size (void) const
 {
     const written_size_type sz (size());
-    return (Align (stream_size_of (sz) + sz, alignof(sz)));
+    return (Align (stream_size_of (sz) + sz, stream_align_of(sz)));
 }
 
 #ifdef CYGCLS_USTL_FSTREAMS
diff --git a/packages/language/cxx/ustl/current/src/fstream.cpp b/packages/language/cxx/ustl/current/src/fstream.cpp
--- a/packages/language/cxx/ustl/current/src/fstream.cpp
+++ b/packages/language/cxx/ustl/current/src/fstream.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "fstream.h"
@@ -96,7 +96,11 @@ void fstream::detach (void)
 	0,		// nocreate
 	O_NOCTTY	// noctty
     };
-    int flags = (m - 1) & O_ACCMODE;	// in and out
+    int flags;
+    if (O_RDONLY == in-1 && O_WRONLY == out-1 && O_RDWR == (in|out)-1)
+	flags = (m - 1) & O_ACCMODE;
+    else
+	flags = ((m&(in|out))==(in|out)) ? O_RDWR : ((m&out) ? O_WRONLY : O_RDONLY);
     for (uoff_t i = 0; i < VectorSize(s_OMFlags); ++ i)
 	flags |= s_OMFlags[i] & (!(m & (1 << i)) - 1);
     if (m & nocreate)
diff --git a/packages/language/cxx/ustl/current/src/memblock.cpp b/packages/language/cxx/ustl/current/src/memblock.cpp
--- a/packages/language/cxx/ustl/current/src/memblock.cpp
+++ b/packages/language/cxx/ustl/current/src/memblock.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "mistream.h"
@@ -73,7 +73,7 @@ void memblock::assign (const void* p, si
 {
     assert ((p != (const void*) cdata() || size() == n) && "Self-assignment can not resize");
     resize (n);
-    copy (p, n);
+    copy_n (pointer(p), n, begin());
 }
 
 /// \brief Reallocates internal block to hold at least \p newSize bytes.
@@ -132,7 +132,7 @@ void memblock::read (istream& is)
 	return;
     resize (n);
     is.read (data(), writable_size());
-    is.align (alignof (n));
+    is.align (stream_align_of (n));
 }
 
 #ifdef CYGCLS_USTL_FSTREAMS
diff --git a/packages/language/cxx/ustl/current/src/memlink.cpp b/packages/language/cxx/ustl/current/src/memlink.cpp
--- a/packages/language/cxx/ustl/current/src/memlink.cpp
+++ b/packages/language/cxx/ustl/current/src/memlink.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "mistream.h"
@@ -19,17 +19,7 @@ void memlink::read (istream& is)
 	USTL_THROW(length_error ("memlink can not increase the size of the linked storage for reading"));
     resize (n);
     is.read (data(), n);
-    is.align (alignof (n));
-}
-
-/// Copies data from \p p, \p n to the linked block starting at \p start.
-void memlink::copy (iterator start, const void* p, size_type n)
-{
-    assert (data() || !n);
-    assert (p || !n);
-    assert (start >= begin() && start + n <= end());
-    if (p)
-	copy_n (const_iterator(p), n, start);
+    is.align (stream_align_of (n));
 }
 
 /// Fills the linked block with the given pattern.
diff --git a/packages/language/cxx/ustl/current/src/mistream.cpp b/packages/language/cxx/ustl/current/src/mistream.cpp
--- a/packages/language/cxx/ustl/current/src/mistream.cpp
+++ b/packages/language/cxx/ustl/current/src/mistream.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "mistream.h"
diff --git a/packages/language/cxx/ustl/current/src/ofstream.cpp b/packages/language/cxx/ustl/current/src/ofstream.cpp
--- a/packages/language/cxx/ustl/current/src/ofstream.cpp
+++ b/packages/language/cxx/ustl/current/src/ofstream.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "ofstream.h"
diff --git a/packages/language/cxx/ustl/current/src/sistream.cpp b/packages/language/cxx/ustl/current/src/sistream.cpp
--- a/packages/language/cxx/ustl/current/src/sistream.cpp
+++ b/packages/language/cxx/ustl/current/src/sistream.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "sistream.h"
diff --git a/packages/language/cxx/ustl/current/src/sostream.cpp b/packages/language/cxx/ustl/current/src/sostream.cpp
--- a/packages/language/cxx/ustl/current/src/sostream.cpp
+++ b/packages/language/cxx/ustl/current/src/sostream.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "mistream.h"	// for istream_iterator, referenced in utf8.h
diff --git a/packages/language/cxx/ustl/current/src/ualgobase.cpp b/packages/language/cxx/ustl/current/src/ualgobase.cpp
--- a/packages/language/cxx/ustl/current/src/ualgobase.cpp
+++ b/packages/language/cxx/ustl/current/src/ualgobase.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #ifndef NDEBUG	// Optimized code here. asserts slow it down, and are checked elsewhere.
@@ -21,13 +21,6 @@ template <typename T> static inline void
 // Copy functions
 //----------------------------------------------------------------------
 
-#if __GNUC__ >= 3
-static inline void movsb_dir_up (void) INLINE;
-static inline void movsb_dir_down (void) INLINE;
-static inline void movsb (const void*& src, size_t nBytes, void*& dest) INLINE;
-static inline void movsd (const void*& src, size_t nWords, void*& dest) INLINE;
-#endif
-
 static inline void movsb_dir_up (void) { asm volatile ("cld"); }
 static inline void movsb_dir_down (void) { asm volatile ("std"); }
 
@@ -58,10 +51,6 @@ template <> inline void stosv (uint32_t*
 #define MMX_ALIGN	16U	// Data must be aligned on this grain
 #define MMX_BS		32U	// Assembly routines copy data this many bytes at a time.
 
-static inline void simd_block_copy (const void* src, void* dest) INLINE;
-static inline void simd_block_store (uint8_t* dest) INLINE;
-static inline void simd_block_cleanup (void) INLINE;
-
 static inline void simd_block_copy (const void* src, void* dest)
 {
     const char* csrc ((const char*) src);
diff --git a/packages/language/cxx/ustl/current/src/ubitset.cpp b/packages/language/cxx/ustl/current/src/ubitset.cpp
--- a/packages/language/cxx/ustl/current/src/ubitset.cpp
+++ b/packages/language/cxx/ustl/current/src/ubitset.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "ubitset.h"
diff --git a/packages/language/cxx/ustl/current/src/uexception.cpp b/packages/language/cxx/ustl/current/src/uexception.cpp
--- a/packages/language/cxx/ustl/current/src/uexception.cpp
+++ b/packages/language/cxx/ustl/current/src/uexception.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "uexception.h"
@@ -10,8 +10,9 @@
 #include "strmsize.h"
 #include "uspecial.h"
 #include <errno.h>
+
 #if HAVE_CXXABI_H && WANT_NAME_DEMANGLING
-    #include <cxxabi.h>
+extern "C" char* __cxa_demangle (const char* mangled_name, char* output_buffer, size_t* length, int* status);
 #endif
 
 namespace ustl {
@@ -212,7 +213,7 @@ const char* demangle_type_name (char* bu
     char dmname [256];
     size_t sz = VectorSize(dmname);
     int bFailed;
-    abi::__cxa_demangle (buf, dmname, &sz, &bFailed);
+    __cxa_demangle (buf, dmname, &sz, &bFailed);
     if (!bFailed) {
 	bl = min (strlen (dmname), bufSize - 1);
 	memcpy (buf, dmname, bl);
diff --git a/packages/language/cxx/ustl/current/src/unew.cpp b/packages/language/cxx/ustl/current/src/unew.cpp
--- a/packages/language/cxx/ustl/current/src/unew.cpp
+++ b/packages/language/cxx/ustl/current/src/unew.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "unew.h"
diff --git a/packages/language/cxx/ustl/current/src/ustdxept.cpp b/packages/language/cxx/ustl/current/src/ustdxept.cpp
--- a/packages/language/cxx/ustl/current/src/ustdxept.cpp
+++ b/packages/language/cxx/ustl/current/src/ustdxept.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "ustdxept.h"
diff --git a/packages/language/cxx/ustl/current/src/ustring.cpp b/packages/language/cxx/ustl/current/src/ustring.cpp
--- a/packages/language/cxx/ustl/current/src/ustring.cpp
+++ b/packages/language/cxx/ustl/current/src/ustring.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "ustring.h"
@@ -68,7 +68,7 @@ void string::assign (const_pointer s, si
     while (len && s[len - 1] == 0)
 	-- len;
     resize (len);
-    copy (s, len);
+    copy_n (s, len, begin());
 }
 
 /// Appends to itself the value of string \p s of length \p len.
@@ -235,7 +235,7 @@ void string::replace (iterator first, it
 uoff_t string::find (const_reference c, uoff_t pos) const
 {
     const_iterator found = ::ustl::find (iat(pos), end(), c);
-    return (found < end() ? distance(begin(),found) : npos);
+    return (found < end() ? (uoff_t) distance(begin(),found) : npos);
 }
 
 /// Returns the offset of the first occurence of substring \p s of length \p n after \p pos.
@@ -274,7 +274,7 @@ uoff_t string::rfind (const string& s, u
 	for (i = 0; size_type(i) < s.size(); ++ i)
 	    if (m[-i] != d[-i])
 		break;
-    return (d > sp ? distance (begin(), d + 2 - s.size()) : npos);
+    return (d > sp ? (uoff_t) distance (begin(), d + 2 - s.size()) : npos);
 }
 
 /// Returns the offset of the first occurence of one of characters in \p s of size \p n after \p pos.
diff --git a/packages/language/cxx/ustl/current/tests/bvt00.cpp b/packages/language/cxx/ustl/current/tests/bvt00.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt00.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt00.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt01.cpp b/packages/language/cxx/ustl/current/tests/bvt01.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt01.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt01.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
@@ -53,7 +53,7 @@ void TestML (void)
     WriteCML (a);
     a.fill (a.begin() + 5, "TEST", 4, 3); 
     WriteCML (a);
-    a.copy (cstr, VectorSize(str) - 1);
+    copy_n (cstr, VectorSize(str) - 1, a.begin());
     WriteCML (a);
 }
 
diff --git a/packages/language/cxx/ustl/current/tests/bvt02.cpp b/packages/language/cxx/ustl/current/tests/bvt02.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt02.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt02.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
@@ -49,8 +49,7 @@ void TestMB (void)
     if (a.begin() == b.begin())
 	cout << "Assignment does not copy a link\n";
     a.deallocate();
-    a.resize (strTestLen);
-    a.copy (strTest, strTestLen);
+    a.assign (strTest, strTestLen);
     WriteCML (a);
     a.insert (a.begin() + 5, 9);
     a.fill (a.begin() + 5, "-", 1, 9);
diff --git a/packages/language/cxx/ustl/current/tests/bvt03.cpp b/packages/language/cxx/ustl/current/tests/bvt03.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt03.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt03.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
@@ -29,17 +29,17 @@ void TestStreams (void)
 
     size_t totalSize = stream_size_of(c);
     totalSize += stream_size_of(uc);
-    totalSize = Align (totalSize, alignof(bv));
+    totalSize = Align (totalSize, stream_align_of(bv));
     totalSize += stream_size_of(bv);
-    totalSize = Align (totalSize, alignof(i));
+    totalSize = Align (totalSize, stream_align_of(i));
     totalSize += stream_size_of(i);
     totalSize += stream_size_of(ui);
     totalSize = Align (totalSize);
     totalSize += stream_size_of(li);
     totalSize += stream_size_of(uli);
-    totalSize = Align (totalSize, alignof(f));
+    totalSize = Align (totalSize, stream_align_of(f));
     totalSize += stream_size_of(f);
-    totalSize = Align (totalSize, alignof(d));
+    totalSize = Align (totalSize, stream_align_of(d));
     totalSize += stream_size_of(d);
     totalSize += stream_size_of(si);
     totalSize += stream_size_of(usi);
diff --git a/packages/language/cxx/ustl/current/tests/bvt04.cpp b/packages/language/cxx/ustl/current/tests/bvt04.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt04.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt04.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt05.cpp b/packages/language/cxx/ustl/current/tests/bvt05.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt05.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt05.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
@@ -158,32 +158,32 @@ static void TestAlgorithms (void)
     PrintVector (v);
     v.assign (first, last);
 
-    cout << "fill 64083 uint8_t(0x41) ";
-    TestBigFill<uint8_t> (64083, 0x41);
-    cout << "fill 64083 uint16_t(0x4142) ";
-    TestBigFill<uint16_t> (64083, 0x4142);
-    cout << "fill 64083 uint32_t(0x41424344) ";
-    TestBigFill<uint32_t> (64083, 0x41424344);
-    cout << "fill 64083 float(0.4242) ";
-    TestBigFill<float> (64083, 0x4242f);
+    cout << "fill 3207 uint8_t(0x41) ";
+    TestBigFill<uint8_t> (3207, 0x41);
+    cout << "fill 3207 uint16_t(0x4142) ";
+    TestBigFill<uint16_t> (3207, 0x4142);
+    cout << "fill 3207 uint32_t(0x41424344) ";
+    TestBigFill<uint32_t> (3207, 0x41424344);
+    cout << "fill 3207 float(0.4242) ";
+    TestBigFill<float> (3207, 0x4242f);
 #if HAVE_INT64_T
-    cout << "fill 64083 uint64_t(0x4142434445464748) ";
-    TestBigFill<uint64_t> (64083, UINT64_C(0x4142434445464748));
+    cout << "fill 3207 uint64_t(0x4142434445464748) ";
+    TestBigFill<uint64_t> (3207, UINT64_C(0x4142434445464748));
 #else
     cout << "No 64bit types available on this platform\n";
 #endif
 
-    cout << "copy 64083 uint8_t(0x41) ";
-    TestBigCopy<uint8_t> (64083, 0x41);
-    cout << "copy 64083 uint16_t(0x4142) ";
-    TestBigCopy<uint16_t> (64083, 0x4142);
-    cout << "copy 64083 uint32_t(0x41424344) ";
-    TestBigCopy<uint32_t> (64083, 0x41424344);
-    cout << "copy 64083 float(0.4242) ";
-    TestBigCopy<float> (64083, 0.4242f);
+    cout << "copy 3207 uint8_t(0x41) ";
+    TestBigCopy<uint8_t> (3207, 0x41);
+    cout << "copy 3207 uint16_t(0x4142) ";
+    TestBigCopy<uint16_t> (3207, 0x4142);
+    cout << "copy 3207 uint32_t(0x41424344) ";
+    TestBigCopy<uint32_t> (3207, 0x41424344);
+    cout << "copy 3207 float(0.4242) ";
+    TestBigCopy<float> (3207, 0.4242f);
 #if HAVE_INT64_T
-    cout << "copy 64083 uint64_t(0x4142434445464748) ";
-    TestBigCopy<uint64_t> (64083, UINT64_C(0x4142434445464748));
+    cout << "copy 3207 uint64_t(0x4142434445464748) ";
+    TestBigCopy<uint64_t> (3207, UINT64_C(0x4142434445464748));
 #else
     cout << "No 64bit types available on this platform\n";
 #endif
@@ -377,22 +377,22 @@ static void TestAlgorithms (void)
     v.resize (4);
     setEnd = set_difference (VectorRange(c_Set1), VectorRange(c_Set2), v.begin());
     PrintVector (v);
-    assert (setEnd == v.end());
+    if (setEnd != v.end()) cout << "incorrect range\n";
     cout << "set_symmetric_difference\n";
     v.resize (7);
     setEnd = set_symmetric_difference (VectorRange(c_Set1), VectorRange(c_Set2), v.begin());
     PrintVector (v);
-    assert (setEnd == v.end());
+    if (setEnd != v.end()) cout << "incorrect range\n";
     cout << "set_intersection\n";
     v.resize (2);
     setEnd = set_intersection (VectorRange(c_Set1), VectorRange(c_Set2), v.begin());
     PrintVector (v);
-    assert (setEnd == v.end());
+    if (setEnd != v.end()) cout << "incorrect range\n";
     cout << "set_union\n";
     v.resize (9);
     setEnd = set_union (VectorRange(c_Set1), VectorRange(c_Set2), v.begin());
     PrintVector (v);
-    assert (setEnd == v.end());
+    if (setEnd != v.end()) cout << "incorrect range\n";
     v.assign (first, last);
 }
 
diff --git a/packages/language/cxx/ustl/current/tests/bvt06.cpp b/packages/language/cxx/ustl/current/tests/bvt06.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt06.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt06.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt07.cpp b/packages/language/cxx/ustl/current/tests/bvt07.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt07.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt07.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
@@ -45,10 +45,7 @@ void TestString (void)
     s2 = "World";
     s3 = s1 + s2;
     cout << s3 << endl;
-    s3 = "Concatenated ";
-    s3 += s1.c_str();
-    s3 += s2;
-    s3 += " string.";
+    s3 = "Concatenated " + s1 + s2 + " string.";
     cout << s3 << endl;
 
     if (s1 < s2)
diff --git a/packages/language/cxx/ustl/current/tests/bvt08.cpp b/packages/language/cxx/ustl/current/tests/bvt08.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt08.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt08.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt09.cpp b/packages/language/cxx/ustl/current/tests/bvt09.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt09.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt09.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
@@ -72,8 +72,8 @@ void TestStringStreams (void)
     cout.format ("u_long:  %ld\n", uli);
     cout.format ("float:   %.2f\n", f);
     cout.format ("double:  %.2f\n", d);
-    cout.format ("short:   %hd\n", static_cast<int>(si));
-    cout.format ("u_short: %hd\n", static_cast<int>(usi));
+    cout.format ("short:   %d\n", static_cast<int>(si));
+    cout.format ("u_short: %d\n", static_cast<int>(usi));
     cout << endl;
 
     cout << "Dump:" << endl;
diff --git a/packages/language/cxx/ustl/current/tests/bvt10.cpp b/packages/language/cxx/ustl/current/tests/bvt10.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt10.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt10.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt11.cpp b/packages/language/cxx/ustl/current/tests/bvt11.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt11.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt11.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt12.cpp b/packages/language/cxx/ustl/current/tests/bvt12.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt12.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt12.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt13.cpp b/packages/language/cxx/ustl/current/tests/bvt13.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt13.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt13.cpp
@@ -3,7 +3,7 @@
 //
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt14.cpp b/packages/language/cxx/ustl/current/tests/bvt14.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt14.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt14.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
@@ -49,7 +49,7 @@ void TestMap (void)
     cout << endl;
 
     mcopy = months;
-    monthmap_t::iterator frob = mcopy.insert (make_pair (string("frobuary"), 42)).first;
+    monthmap_t::iterator frob = mcopy.insert (mcopy.begin(), make_pair (string("frobuary"), 42));
     cout << "After inserting " << frob->first << "," << frob->second << ":" << endl;
     for (i = mcopy.begin(); i < mcopy.end(); ++ i)
 	cout << i->first << " ";
diff --git a/packages/language/cxx/ustl/current/tests/bvt15.cpp b/packages/language/cxx/ustl/current/tests/bvt15.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt15.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt15.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
@@ -27,10 +27,10 @@ void TestMultiMap (void)
     employees.insert (make_pair (47000, string("Barbara"))); 
     employees.insert (make_pair (47000, string("Mary"))); 
 
-    cout << "As-inserted listing:" << endl;
+    cout << "As-inserted listing:\n";
     PrintEntries (employees);
 
-    cout << "Alphabetical listing:" << endl;
+    cout << "Alphabetical listing:\n";
     sort (employees);
     PrintEntries (employees);
 
@@ -41,13 +41,15 @@ void TestMultiMap (void)
 	cout << " " << i->second;
     cout << endl;
 
-    cout << "There are " << employees.count (27000) << " low-paid employees" << endl;
+    cout << employees.find(27000)->second << " makes $27000\n";
 
-    cout << "Firing all low-paid employees:" << endl;
+    cout << "There are " << employees.count (27000) << " low-paid employees\n";
+
+    cout << "Firing all low-paid employees:\n";
     employees.erase (27000);
     PrintEntries (employees);
 
-    cout << "Firing dumb employees:" << endl;
+    cout << "Firing dumb employees:\n";
     employees.erase (employees.begin(), employees.begin() + 1);
     PrintEntries (employees);
 }
diff --git a/packages/language/cxx/ustl/current/tests/bvt15.std b/packages/language/cxx/ustl/current/tests/bvt15.std
--- a/packages/language/cxx/ustl/current/tests/bvt15.std
+++ b/packages/language/cxx/ustl/current/tests/bvt15.std
@@ -15,6 +15,7 @@ Gail	- $47000
 Mary	- $47000
 BigBoss	- $99000
 Employees making $47000: Barbara Gail Mary
+Dave makes $27000
 There are 2 low-paid employees
 Firing all low-paid employees:
 Dumb	- $15000
diff --git a/packages/language/cxx/ustl/current/tests/bvt16.cpp b/packages/language/cxx/ustl/current/tests/bvt16.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt16.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt16.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
@@ -22,7 +22,7 @@ void TestUTF8 (void)
 {
     cout << "Generating Unicode characters ";
     vector<wchar_t> srcChars;
-    srcChars.resize (0xFFFF);
+    srcChars.resize (0xFFF);
     iota (srcChars.begin(), srcChars.end(), 0);
     cout.format ("%zu - %zu\n", size_t(srcChars[0]), size_t(srcChars.back()));
 
diff --git a/packages/language/cxx/ustl/current/tests/bvt17.cpp b/packages/language/cxx/ustl/current/tests/bvt17.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt17.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt17.cpp
@@ -1,7 +1,7 @@
 // 011010011001011001011000100100
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt18.cpp b/packages/language/cxx/ustl/current/tests/bvt18.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt18.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt18.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt19.cpp b/packages/language/cxx/ustl/current/tests/bvt19.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt19.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt19.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt20.cpp b/packages/language/cxx/ustl/current/tests/bvt20.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt20.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt20.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt21.cpp b/packages/language/cxx/ustl/current/tests/bvt21.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt21.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt21.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
@@ -33,6 +33,12 @@ void TestUtility (void)
     cout << "Align(17,7) = " << Align(17,7) << endl;
     cout << "Align(14,7) = " << Align(14,7) << endl;
     cout << endl;
+    cout << "NextPow2(0) = " << NextPow2(0) << endl;
+    cout << "NextPow2(1) = " << NextPow2(1) << endl;
+    cout << "NextPow2(4) = " << NextPow2(4) << endl;
+    cout << "NextPow2(3827) = " << NextPow2(3827) << endl;
+    cout << "NextPow2(0xFFFFFFF0) = " << NextPow2(0xFFFFFFF0) << endl;
+    cout << endl;
     cout << "advance(42,0) = " << advance(42,0) << endl;
     cout << "advance(42,3) = " << advance(42,3) << endl;
     const void *cvp = (const void*) 0x1234;
diff --git a/packages/language/cxx/ustl/current/tests/bvt21.std b/packages/language/cxx/ustl/current/tests/bvt21.std
--- a/packages/language/cxx/ustl/current/tests/bvt21.std
+++ b/packages/language/cxx/ustl/current/tests/bvt21.std
@@ -7,6 +7,12 @@ Align(5,2) = 6
 Align(17,7) = 21
 Align(14,7) = 14
 
+NextPow2(0) = 1
+NextPow2(1) = 2
+NextPow2(4) = 4
+NextPow2(3827) = 4096
+NextPow2(0xFFFFFFF0) = 1
+
 advance(42,0) = 42
 advance(42,3) = 45
 cvp = 1234
diff --git a/packages/language/cxx/ustl/current/tests/bvt22.cpp b/packages/language/cxx/ustl/current/tests/bvt22.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt22.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt22.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt23.cpp b/packages/language/cxx/ustl/current/tests/bvt23.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt23.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt23.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt24.cpp b/packages/language/cxx/ustl/current/tests/bvt24.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt24.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt24.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt25.cpp b/packages/language/cxx/ustl/current/tests/bvt25.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt25.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt25.cpp
@@ -1,10 +1,20 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
 
+#ifdef CYGIMP_USTL_TESTS_BVT25_ROMFS
+# include <cyg/fileio/fileio.h>
+# if (CYG_BYTEORDER == CYG_LSBFIRST)
+#  include <cyg/ustl/bvt25fs_le.h>
+# else
+#  include <cyg/ustl/bvt25fs_be.h>
+# endif
+MTAB_ENTRY(romfs_mte1, "/", "romfs", "", (CYG_ADDRWORD) &filedata[0]);
+#endif
+
 void TestFStream (void)
 {
     fstream fs ("bvt/bvt25.std", ios::in | ios::nocreate);
diff --git a/packages/language/cxx/ustl/current/tests/bvt26.cpp b/packages/language/cxx/ustl/current/tests/bvt26.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt26.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt26.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/language/cxx/ustl/current/tests/bvt27.cpp b/packages/language/cxx/ustl/current/tests/bvt27.cpp
--- a/packages/language/cxx/ustl/current/tests/bvt27.cpp
+++ b/packages/language/cxx/ustl/current/tests/bvt27.cpp
@@ -1,6 +1,6 @@
 // This file is part of the uSTL library, an STL implementation.
 //
-// Copyright (c) 2005-2009 by Mike Sharov <msharov@users.sourceforge.net>
+// Copyright (c) 2005 by Mike Sharov <msharov@users.sourceforge.net>
 // This file is free software, distributed under the MIT License.
 
 #include "stdtest.h"
diff --git a/packages/net/bsd_tcpip/current/ChangeLog b/packages/net/bsd_tcpip/current/ChangeLog
--- a/packages/net/bsd_tcpip/current/ChangeLog
+++ b/packages/net/bsd_tcpip/current/ChangeLog
@@ -1,3 +1,100 @@
+2012-03-13  Grant Edwards <grant.b.edwards@gmail.com>
+
+	* src/ecos/support.c (_dumpentry, show_network_tables): Fix
+	compiler warnings by removing variables that are set but never
+	referenced. [ Bugzilla 1001516 ]
+
+2012-03-08  Grant Edwards <grant.b.edwards@gmail.com>
+
+	* doc/freebsd.sgml: Add section on how to disable ipv6 support at
+	runtime. [ Bugzilla 1001502 ]
+
+2012-03-08  Grant Edwards <grant.b.edwards@gmail.com>
+
+	* src/sys/netinet6/icmp6.c (icmp6_redirect_input):
+	* src/sys/netinet6/in6_src.c (in6_selectroute):
+	* src/sys/netinet6/ip6_mroute.c (phyint_send, pim6_input):
+	* src/sys/netinet6/nd6.c (nd6_timer, nd6_dad_ns_input):
+	* src/sys/netinet6/nd6_rtr.c (prelist_update):
+	* src/sys/netinet6/ip6_output.c (ip6_ctloutput, ip6_raw_ctloutput):
+	* src/sys/netinet6/raw_ip6.c (rip6_ctlinput):
+	* src/sys/netinet6/ip6_input.c (ip6_hopopts_input): Fix compiler
+	warnings by removing variables that are set but never referenced,
+	or by declaring them as "unused" if they are referenced only by
+	conditionally-compiled code.
+	* src/sys/netinet6/raw_ip6.c (rip6_ctlinput):
+	* src/sys/netinet6/in6_ifattach.c (get_rand_ifid,in6_nigroup):
+	* src/sys/netinet6/ip6_output.c (ip6_insert_jumboopt):
+	* src/sys/netinet6/ip6_input.c (ip6_get_prevhdr): Fix compiler
+	warnings about signed/unsigned char mismatches.
+	* src/sys/netinet6/ip6_input.c (ip6_savecontrol): Fix
+	grouping/precedence/paren error in flag checking expression --
+	verified same fix is already in upstream.
+	[ Bugzilla 1001526 ]
+
+2012-03-08  Grant Edwards <grant.b.edwards@gmail.com>
+
+	* src/sys/net/if_ethersubr.c (ether_output, ether_resolvemulti):
+	Fix compiler warning by removing variable that was set but never
+	referenced.  Fix compiler warning about signed/unsigned pointer
+	mismatch.
+	* src/sys/netinet/tcp_input.c (tcp_input):
+	* src/sys/netinet/tcp_output.c (tcp_output):
+	* src/sys/netinet/ip_encap.c (encap6_ctlinput):
+	* src/sys/netinet/udp_usrreq.c (udp_output, udp_connect): Fix
+	compiler warnings about variables that are set but not referenced.
+	Some are removed, others that are referenced in
+	conditionally-compiled code are marked with the "unused"
+	attribute.
+	[ Bugzilla 1001525 ]
+
+2012-03-06  Grant Edwards <grant.b.edwards@gmail.com>
+	
+	* cdl/freebsd_net.cdl:
+	* src/sys/netinet/in_pcb.c: Add CDL option
+	CYGOPT_NET_FREEBSD_FORCE_DIRECTED_BROADCAST that allows you to
+	control whether or not packets sent to 255.255.255.255 get
+	redirected to the interface's subnet broadcast address.  By
+	default, this option is enabled (behavior is the same as
+	before this change). [ Bugzilla 1001508 ]
+	
+2012-03-06  Grant Edwards <grant.b.edwards@gmail.com>
+	
+	* include/sys/param.h:
+	* src/sys/netinet6/ip6_input.c:  Make ip6_init2() visible globally
+	as cyg_ip6_init2() so that it's possible to disable ipv6 support
+	at runtime by munging the net init table and replacing calls to
+	net_add_domain(&inet6domain) and ip6_init2() with calls to a noop
+	function. [ Bugzilla 1001502 ]
+
+2012-02-29  Grant Edwards <grant.b.edwards@gmail.com>
+
+	* cdl/freebsd_net.cdl:  Add -fno-strict-aliasing compiler flag to fix
+	compiler warnings from newer versions (4.6) of gcc. [ bugzilla 1001501 ]
+
+2011-05-12  John Dallaway  <john@dallaway.org.uk>
+
+	* include/sys/param.h: Fix cyg_arc4random() extern. Issue reported by
+	Marwijn Hessel. [ Bugzilla 1001227 ]
+
+2011-02-22  Kelvin Lawson  <kelvinl@users.sf.net>
+
+	* src/sys/netinet/if_ether.c: Merge fix from FreeBSD CVS r1.108.
+	Prevents creation of reciprocal ARP cache entries for hosts not on
+	local subnet.
+	* cdl/freebsd_net.cdl:
+	* include/netinet/tcp_var.c:
+	* src/sys/netinet/tcp_subr.c:
+	* src/sys/netinet/tcp_input.c: Merge fix from FreeBSD CVS. Introduces
+	a maximum size for the TCP reassembly queue to limit network buffer
+	usage associated with reassembly. Enable CYGNUM_NET_TCP_REASS_DIVISOR
+	and set it to configure the maximum number of buffers usable for TCP
+	reassembly.
+
+2010-09-18  John Dallaway  <john@dallaway.org.uk>
+
+	* doc/freebsd.sgml: No longer "recent".
+
 2009-07-22  John Dallaway  <john@dallaway.org.uk>
 
 	* include/sys/cdefs.h: Silence undefined macro warning reported
@@ -629,7 +726,7 @@ 2002-02-05  Hugo Tyson  <hmt@redhat.com>
 # ####GPLCOPYRIGHTBEGIN####                                       
 # -------------------------------------------                     
 # This file is part of eCos, the Embedded Configurable Operating System.
-# Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc.   
+# Copyright (C) 2000, 2001, 2002, 2010, 2011 Free Software Foundation, Inc.   
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
diff --git a/packages/net/bsd_tcpip/current/cdl/freebsd_net.cdl b/packages/net/bsd_tcpip/current/cdl/freebsd_net.cdl
--- a/packages/net/bsd_tcpip/current/cdl/freebsd_net.cdl
+++ b/packages/net/bsd_tcpip/current/cdl/freebsd_net.cdl
@@ -291,7 +291,7 @@ cdl_package CYGPKG_NET_FREEBSD_STACK {
         for buffers used by the networking code.  The number is an
         upper limit, with at least enough space to get the stack
         initialized. Tip: setting a breakpoint at cyg_memalloc_alloc_fail() 
-	is an especially useful tool in establishing when there is too 
+        is an especially useful tool in establishing when there is too 
         little memory for an application. "
     }
 
@@ -320,6 +320,22 @@ cdl_package CYGPKG_NET_FREEBSD_STACK {
             Clusters size."
     }
 
+    cdl_option CYGNUM_NET_TCP_REASS_DIVISOR {
+        display       "Max TCP reassembly queue fraction"
+        flavor         booldata
+        default_value 0
+        description   "
+            Enabling this option puts a maximum limit on the number of TCP
+            segments which can be queued for reassembly. The value of this
+            option gives the maximum proportion of clusters that can be used
+            for TCP reassembly. The maximum number of segments is given
+            by the total number of clusters available divided by the value of
+            this option (in other words,
+            nmbclusters / CYGNUM_NET_TCP_REASS_DIVISOR). So for example,
+            setting this option to 16 will means that no more than 1/16 of
+            the total number of clusters will be used for TCP reassembly."
+    }
+
     cdl_option CYGPKG_NET_MAXSOCKETS {
         display "Max number of open sockets"
         flavor  data
@@ -419,8 +435,8 @@ cdl_package CYGPKG_NET_FREEBSD_STACK {
             description "
                 The default is 50, which will usually mean a delay between
                 tests for 'stuck' devices of 500mS, that is half a second.
-	        The overhead only applies if no network activity occurred,
-	        so it may be acceptable to make this value very small,
+                The overhead only applies if no network activity occurred,
+                so it may be acceptable to make this value very small,
                 where high CPU load does not matter during network idle
                 periods, or very large if your application tries often to
                 send packets itself."
@@ -450,7 +466,7 @@ cdl_package CYGPKG_NET_FREEBSD_STACK {
             display "Additional compiler flags"
             flavor  data
             no_define
-            default_value { "-D_KERNEL" }
+            default_value { "-D_KERNEL -fno-strict-aliasing" }
             description   "
                 This option modifies the set of compiler flags for
                 building the networking package.
@@ -478,4 +494,29 @@ cdl_package CYGPKG_NET_FREEBSD_STACK {
             These are test specifically for the FreeBSD stack. These test features
             which only the FreeBSD stack has"
     }
+
+    cdl_option CYGOPT_NET_FREEBSD_FORCE_DIRECTED_BROADCAST {
+        display       "Convert limited broadcast addresses into directed broadcasts"
+        flavor        bool
+        default_value 1
+        description   "
+            In line with other IP stack implementations, the BSD
+            network stack has historically converted packets sent to
+            the INADDR_BROADCAST destination addresses
+            (255.255.255.255) into a more specific directed broadcast
+            address according to the address configuration of the
+            primary network interface. For example if your network
+            interface is configured as 192.168.100.33/24 and you send
+            a UDP broadcast packet to 255.255.255.255, it will
+            actually be sent with a destination IP address of
+            192.168.100.255. Over time, this behavior has been
+            criticized for various reasons.  The primary reason is
+            that it becomes impossible to send UDP packets to
+            255.255.255.255 once the primary network (broadcast)
+            interface is configured with address information. For this
+            reason, it is possible to disable this behavior with this
+            option so that packets will be sent explicitly to
+            INADDR_BROADCAST when that destination address is
+            specified."
+    }
 }
diff --git a/packages/net/bsd_tcpip/current/doc/freebsd.sgml b/packages/net/bsd_tcpip/current/doc/freebsd.sgml
--- a/packages/net/bsd_tcpip/current/doc/freebsd.sgml
+++ b/packages/net/bsd_tcpip/current/doc/freebsd.sgml
@@ -9,7 +9,7 @@
 <!-- =============================================================== -->
 <!-- ####ECOSDOCCOPYRIGHTBEGIN####                                       -->
 <!-- ===============================================================     -->
-<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. -->
+<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2010 Free Software Foundation, Inc. -->
 <!-- This material may be distributed only subject to the terms          -->
 <!-- and conditions set forth in the Open Publication License, v1.0      -->
 <!-- or later (the latest version is presently available at              -->
@@ -33,7 +33,7 @@
 <PARA>	  <productname>TCP/IP Networking for eCos</productname>
           now provides a complete
 	  TCP/IP networking stack, 
-based on a recent snapshot of the FreeBSD code, released by the
+based on a snapshot of the FreeBSD code, released by the
 KAME project.
 The networking support is
 	  fully featured and well tested within the eCos environment.
@@ -191,6 +191,97 @@ void <function>cyg_select_abort</functio
 <function>cyg_select_with_abort()</function> call
 to cease waiting and continue execution.</PARA>
 </SECT1>
-</CHAPTER>
+
+<SECT1 id="tcpip-freebsd-disabling-ipv6-at-runtime">
+<TITLE>Disabling IPv6 Support at Runtime</TITLE>
+<PARA>
+The FreeBSD stack starts up with IPv4 support in an essentially
+"disabled" state.  It requires the application to take positive actions
+to assign IPv4 address and routes before the interfaces will respond
+to packets from the outside world.
+</PARA>
+<PARA>
+This is not true of IPv6 support.  If IPv6 support was enabled in the
+eCos build, the stack will start up with link-local addresses
+assigned and interfaces listening to certain multicast addresses.  The
+stack will not only respond to IPv6 packets, it will spontaneously
+send IPv6 packets without actions from application code.
+</PARA>
+<PARA>
+If an eCos application wishes to disable IPv6 support at runtime, the
+decision has to be made very early in the boot process and actions
+taken to prevent the invocation of IPv6 startup code in the network
+stack.  This involves two rather obscure "tricks":
+<ITEMIZEDLIST>
+<LISTITEM><PARA>
+Using a dummy device driver's "init" hook as a place to execute some
+code early in the startup process
+</PARA></LISTITEM>
+<LISTITEM><PARA> Monkey-patching the network stack's table of
+initializers by looping through it and checking the function pointers
+against certain globally visible symbols and replacing the two
+IPv6-specific function pointers with pointers to a "noop" function.
+</PARA></LISTITEM>
+</ITEMIZEDLIST>
+</PARA>
+<PARA>
+The code listing below shows an example of disabling IPv6 support at
+runtime if the global variable we_want_to_disable_ipv6 is non-zero.
+The assumption is that some code in the HAL initialization or
+somewhere else has made the decision whether or not to disable IPv6
+support and set that variable accordingly.
+</PARA>
+<PROGRAMLISTING>
+// Sample code showing a method of disabling IPv6 support at runtime
 
+// Do-nothing function we can patch into the network stack's init table
+// when we want to disable one of the entries
+static void
+init_noop(void *dummy)
+{
+}
+
+// Function that loops through the network stack's init table and
+// disables the two IPv6 entries
+static void
+disable_ipv6(void)
+{
+    extern struct init_tab_entry __NET_INIT_TAB__[],
+                    __NET_INIT_TAB_END__;
+    struct init_tab_entry *init_entry;
+    extern void     cyg_net_add_domain(void *);
+    extern void     ip6_init2(void *);
+    extern char     inet6domain[];
+
+    for (init_entry = __NET_INIT_TAB__; init_entry != &__NET_INIT_TAB_END__;
+         init_entry++)
+        if ((init_entry->fun == ip6_init2)
+            || (init_entry->fun == cyg_net_add_domain
+                && init_entry->data == (void *)inet6domain))
+            init_entry->fun = init_noop;
+}
+
+// Function called early in the inintialization process via a dummy
+// device table entry
+static bool
+early_init(struct cyg_devtab_entry *tab)
+{
+    if (we_want_to_disable_ipv6)
+        disable_ipv6();
+    return 0;
+}
+
+// Dummy device driver table entry that will call the above early_init()
+// function during the startup process
+DEVTAB_ENTRY(device_master_early_init,
+             "neveruse",
+             NULL,
+             NULL,
+             early_init,
+             NULL,
+             NULL
+    );
+</PROGRAMLISTING>
+</SECT1>
+</CHAPTER>
 </PART>
diff --git a/packages/net/bsd_tcpip/current/include/netinet/tcp_var.h b/packages/net/bsd_tcpip/current/include/netinet/tcp_var.h
--- a/packages/net/bsd_tcpip/current/include/netinet/tcp_var.h
+++ b/packages/net/bsd_tcpip/current/include/netinet/tcp_var.h
@@ -67,6 +67,8 @@ struct tseg_qent {
 	struct	mbuf	*tqe_m;		/* mbuf contains packet */
 };
 LIST_HEAD(tsegqe_head, tseg_qent);
+extern int	tcp_reass_maxseg;
+extern int	tcp_reass_qsize;
 #ifdef MALLOC_DECLARE
 MALLOC_DECLARE(M_TSEGQ);
 #endif
diff --git a/packages/net/bsd_tcpip/current/include/sys/param.h b/packages/net/bsd_tcpip/current/include/sys/param.h
--- a/packages/net/bsd_tcpip/current/include/sys/param.h
+++ b/packages/net/bsd_tcpip/current/include/sys/param.h
@@ -12,7 +12,7 @@
 // and license included herein.                                 
 //
 // Portions created by the Free Software Foundation are         
-// Copyright (C) 2002 Free Software Foundation, Inc.            
+// Copyright (C) 2002, 2011 Free Software Foundation, Inc.            
 // -------------------------------------------                  
 // ####BSDCOPYRIGHTEND####                                      
 //==========================================================================
@@ -222,6 +222,7 @@
 #define ip6_get_prevhdr cyg_ip6_get_prevhdr
 #define ip6_getdstifaddr cyg_ip6_getdstifaddr
 #define ip6_init cyg_ip6_init
+#define ip6_init2 cyg_ip6_init2
 #define ip6_input cyg_ip6_input
 #define ip6_lasthdr cyg_ip6_lasthdr
 #define ip6_mforward cyg_ip6_mforward
@@ -1042,5 +1043,5 @@ if (cyg_net_log_mask & lvl)
 #endif
 
 #endif // _KERNEL
-int extern cyg_arc4random(void);
+extern int cyg_arc4random(void);
 #endif //_SYS_PARAM_H_
diff --git a/packages/net/bsd_tcpip/current/src/ecos/support.c b/packages/net/bsd_tcpip/current/src/ecos/support.c
--- a/packages/net/bsd_tcpip/current/src/ecos/support.c
+++ b/packages/net/bsd_tcpip/current/src/ecos/support.c
@@ -979,14 +979,13 @@ static int
 _dumpentry(struct radix_node *rn, void *vw)
 {
     struct rtentry *rt = (struct rtentry *)rn;
-    struct sockaddr *dst, *gate, *netmask, *genmask;
+    struct sockaddr *dst, *gate, *netmask;
     char addr[64], *cp;
     pr_fun *pr = (pr_fun *)vw;
 
     dst = rt_key(rt);
     gate = rt->rt_gateway;
     netmask = rt_mask(rt);
-    genmask = rt->rt_genmask;
     if ((rt->rt_flags & (RTF_UP | RTF_WASCLONED)) == RTF_UP) {
         _inet_ntop(dst, addr, sizeof(addr));
         (*pr)("%-15s ", addr);
@@ -1030,7 +1029,7 @@ static int
 void
 show_network_tables(pr_fun *pr)
 {
-    int i, error;
+    int i;
     struct radix_node_head *rnh;
     struct ifnet *ifp;
 
@@ -1039,7 +1038,7 @@ show_network_tables(pr_fun *pr)
     (*pr)("Destination     Gateway         Mask            Flags    Interface\n");
     for (i = 1; i <= AF_MAX; i++) {
         if ((rnh = rt_tables[i]) != NULL) {
-            error = rnh->rnh_walktree(rnh, _dumpentry, pr);
+            rnh->rnh_walktree(rnh, _dumpentry, pr);
         }
     }
 
diff --git a/packages/net/bsd_tcpip/current/src/sys/net/if_ethersubr.c b/packages/net/bsd_tcpip/current/src/sys/net/if_ethersubr.c
--- a/packages/net/bsd_tcpip/current/src/sys/net/if_ethersubr.c
+++ b/packages/net/bsd_tcpip/current/src/sys/net/if_ethersubr.c
@@ -147,7 +147,7 @@ ether_output(ifp, m, dst, rt0)
  	u_char esrc[6], edst[6];
 	register struct rtentry *rt;
 	register struct ether_header *eh;
-	int off, loop_copy = 0;
+	int loop_copy = 0;
 	int hlen;	/* link layer header lenght */
 	struct arpcom *ac = IFP2AC(ifp);
 
@@ -184,7 +184,6 @@ ether_output(ifp, m, dst, rt0)
 	case AF_INET:
 		if (!arpresolve(ac, rt, m, dst, edst, rt0))
 			return (0);	/* if not yet resolved */
-		off = m->m_pkthdr.len - m->m_len;
 		type = htons(ETHERTYPE_IP);
 		break;
 #endif
@@ -194,7 +193,6 @@ ether_output(ifp, m, dst, rt0)
 			/* Something bad happened */
 			return(0);
 		}
-		off = m->m_pkthdr.len - m->m_len;
 		type = htons(ETHERTYPE_IPV6);
 		break;
 #endif
@@ -935,7 +933,7 @@ ether_resolvemulti(ifp, llsa, sa)
 		sdl->sdl_index = ifp->if_index;
 		sdl->sdl_type = IFT_ETHER;
 		sdl->sdl_alen = ETHER_ADDR_LEN;
-		e_addr = LLADDR(sdl);
+		e_addr = (unsigned char*)LLADDR(sdl);
 		ETHER_MAP_IPV6_MULTICAST(&sin6->sin6_addr, e_addr);
 		*llsa = (struct sockaddr *)sdl;
 		return 0;
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet/if_ether.c b/packages/net/bsd_tcpip/current/src/sys/netinet/if_ether.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet/if_ether.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet/if_ether.c
@@ -807,13 +807,25 @@ arplookup(addr, create, proxy)
 		why = "could not allocate llinfo";
 	else if (rt->rt_gateway->sa_family != AF_LINK)
 		why = "gateway route is not ours";
-
-	if (why && create) {
-		log(LOG_DEBUG, "arplookup %s failed: %s\n",
-		    inet_ntoa(sin.sin_addr), why);
-		return 0;
-	} else if (why) {
-		return 0;
+	
+	if (why) {
+		if (create) {
+			log(LOG_DEBUG, "arplookup %s failed: %s\n",
+			    inet_ntoa(sin.sin_addr), why);
+			/*
+			 * If there are no references to this Layer 2 route,
+			 * and it is a cloned route, and not static, and
+			 * arplookup() is creating the route, then purge
+			 * it from the routing table as it is probably bogus.
+			 */
+			if (((rt->rt_flags & (RTF_STATIC | RTF_WASCLONED)) ==
+			    RTF_WASCLONED) && (rt->rt_refcnt == 0))
+				rtrequest(RTM_DELETE,
+				    (struct sockaddr *)rt_key(rt),
+				    rt->rt_gateway, rt_mask(rt),
+				    rt->rt_flags, 0);
+		}
+		return (0);
 	}
 	return ((struct llinfo_arp *)rt->rt_llinfo);
 }
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet/in_pcb.c b/packages/net/bsd_tcpip/current/src/sys/netinet/in_pcb.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet/in_pcb.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet/in_pcb.c
@@ -369,9 +369,11 @@ in_pcbladdr(inp, nam, plocal_sin)
 #define ifatoia(ifa)	((struct in_ifaddr *)(ifa))
 		if (sin->sin_addr.s_addr == INADDR_ANY)
 		    sin->sin_addr = IA_SIN(TAILQ_FIRST(&in_ifaddrhead))->sin_addr;
+#ifdef CYGOPT_NET_FREEBSD_FORCE_DIRECTED_BROADCAST
 		else if (sin->sin_addr.s_addr == (u_long)INADDR_BROADCAST &&
 		  (TAILQ_FIRST(&in_ifaddrhead)->ia_ifp->if_flags & IFF_BROADCAST))
 		    sin->sin_addr = satosin(&TAILQ_FIRST(&in_ifaddrhead)->ia_broadaddr)->sin_addr;
+#endif
 	}
 	if (inp->inp_laddr.s_addr == INADDR_ANY) {
 		register struct route *ro;
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet/ip_encap.c b/packages/net/bsd_tcpip/current/src/sys/netinet/ip_encap.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet/ip_encap.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet/ip_encap.c
@@ -817,12 +817,10 @@ encap6_ctlinput(cmd, sa, d0)
 	void *d0;
 {
 	void *d = d0;
-	struct ip6_hdr *ip6;
-	struct mbuf *m;
-	int off;
+	struct ip6_hdr *ip6 CYGBLD_ATTRIB_UNUSED;
+	struct mbuf *m CYGBLD_ATTRIB_UNUSED;
+	int off CYGBLD_ATTRIB_UNUSED;
 	struct ip6ctlparam *ip6cp = NULL;
-	const struct sockaddr_in6 *sa6_src = NULL;
-	void *cmdarg;
 	int nxt;
 	struct encaptab *ep;
 	const struct ip6protosw *psw;
@@ -848,14 +846,10 @@ encap6_ctlinput(cmd, sa, d0)
 		m = ip6cp->ip6c_m;
 		ip6 = ip6cp->ip6c_ip6;
 		off = ip6cp->ip6c_off;
-		cmdarg = ip6cp->ip6c_cmdarg;
-		sa6_src = ip6cp->ip6c_src;
 		nxt = ip6cp->ip6c_nxt;
 	} else {
 		m = NULL;
 		ip6 = NULL;
-		cmdarg = NULL;
-		sa6_src = &sa6_any;
 		nxt = -1;
 	}
 
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_input.c b/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_input.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_input.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_input.c
@@ -132,6 +132,26 @@ SYSCTL_INT(_net_inet_tcp, OID_AUTO, drop
     &drop_synfin, 0, "Drop TCP packets with SYN+FIN set");
 #endif
 
+#ifdef CYGNUM_NET_TCP_REASS_DIVISOR
+SYSCTL_NODE(_net_inet_tcp, OID_AUTO, reass, CTLFLAG_RW, 0,
+    "TCP Segment Reassembly Queue");
+
+int tcp_reass_maxseg = 0;
+SYSCTL_INT(_net_inet_tcp_reass, OID_AUTO, maxsegments, CTLFLAG_RD,
+    &tcp_reass_maxseg, 0,
+    "Global maximum number of TCP Segments in Reassembly Queue");
+
+int tcp_reass_qsize = 0;
+SYSCTL_INT(_net_inet_tcp_reass, OID_AUTO, cursegments, CTLFLAG_RD,
+    &tcp_reass_qsize, 0,
+    "Global number of TCP Segments currently in Reassembly Queue");
+
+static int tcp_reass_overflows = 0;
+SYSCTL_INT(_net_inet_tcp_reass, OID_AUTO, overflows, CTLFLAG_RD,
+    &tcp_reass_overflows, 0,
+    "Global number of TCP Segment Reassembly Queue Overflows");
+#endif
+
 struct inpcbhead tcb;
 #define	tcb6	tcb  /* for KAME src sync over BSD*'s */
 struct inpcbinfo tcbinfo;
@@ -185,6 +205,23 @@ tcp_reass(tp, th, tlenp, m)
 	if (th == 0)
 		goto present;
 
+	/*
+	 * Limit the number of segments in the reassembly queue to prevent
+	 * holding on to too many segments (and thus running out of mbufs).
+	 * Make sure to let the missing segment through which caused this
+	 * queue.  Always keep one global queue entry spare to be able to
+	 * process the missing segment.
+	 */
+#ifdef CYGNUM_NET_TCP_REASS_DIVISOR
+	if (th->th_seq != tp->rcv_nxt &&
+	    tcp_reass_qsize + 1 >= tcp_reass_maxseg) {
+		tcp_reass_overflows++;
+		tcpstat.tcps_rcvmemdrop++;
+		m_freem(m);
+		return (0);
+	}
+#endif
+	
 	/* Allocate a new queue entry. If we can't, just drop the pkt. XXX */
 	MALLOC(te, struct tseg_qent *, sizeof (struct tseg_qent), M_TSEGQ,
 	       M_NOWAIT);
@@ -193,6 +230,9 @@ tcp_reass(tp, th, tlenp, m)
 		m_freem(m);
 		return (0);
 	}
+#ifdef CYGNUM_NET_TCP_REASS_DIVISOR
+	tcp_reass_qsize++;
+#endif
 
 	/*
 	 * Find a segment which begins after this one does.
@@ -218,6 +258,9 @@ tcp_reass(tp, th, tlenp, m)
 				tcpstat.tcps_rcvdupbyte += *tlenp;
 				m_freem(m);
 				FREE(te, M_TSEGQ);
+#ifdef CYGNUM_NET_TCP_REASS_DIVISOR
+				tcp_reass_qsize--;
+#endif
 				/*
 				 * Try to present any queued data
 				 * at the left window edge to the user.
@@ -253,6 +296,9 @@ tcp_reass(tp, th, tlenp, m)
 		LIST_REMOVE(q, tqe_q);
 		m_freem(q->tqe_m);
 		FREE(q, M_TSEGQ);
+#ifdef CYGNUM_NET_TCP_REASS_DIVISOR
+		tcp_reass_qsize--;
+#endif
 		q = nq;
 	}
 
@@ -287,6 +333,9 @@ present:
 		else
 			sbappend(&so->so_rcv, q->tqe_m);
 		FREE(q, M_TSEGQ);
+#ifdef CYGNUM_NET_TCP_REASS_DIVISOR
+		tcp_reass_qsize--;
+#endif
 		q = nq;
 	} while (q && q->tqe_th->th_seq == tp->rcv_nxt);
 	ND6_HINT(tp);
@@ -362,7 +411,7 @@ tcp_input(m, off0)
 	struct ip6_hdr *ip6 = NULL;
 	int isipv6;
 #endif /* INET6 */
-	int rstreason; /* For badport_bandlim accounting purposes */
+	int rstreason CYGBLD_ATTRIB_UNUSED; /* For badport_bandlim accounting purposes */
 
 #ifdef INET6
 	isipv6 = (mtod(m, struct ip *)->ip_v == 6) ? 1 : 0;
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_output.c b/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_output.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_output.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_output.c
@@ -119,7 +119,6 @@ tcp_output(tp)
 	int off, flags, error;
 	register struct mbuf *m;
 	struct ip *ip = NULL;
-	register struct ipovly *ipov = NULL;
 #ifdef INET6
 	struct ip6_hdr *ip6 = NULL;
 #endif /* INET6 */
@@ -650,7 +649,6 @@ send:
 #endif /* INET6 */
       {
 	ip = mtod(m, struct ip *);
-	ipov = (struct ipovly *)ip;
 	th = (struct tcphdr *)(ip + 1);
 	/* this picks up the pseudo header (w/o the length) */
 	tcp_fillheaders(tp, ip, th);
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_subr.c b/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_subr.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_subr.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_subr.c
@@ -213,6 +213,10 @@ tcp_init()
 					&tcbinfo.porthashmask);
 	tcbinfo.ipi_zone = zinit("tcpcb", sizeof(struct inp_tp), maxsockets,
 				 ZONE_INTERRUPT, 0);
+#ifdef CYGNUM_NET_TCP_REASS_DIVISOR
+	tcp_reass_maxseg = nmbclusters / CYGNUM_NET_TCP_REASS_DIVISOR;
+#endif
+
 #ifdef INET6
 #define TCP_MINPROTOHDR (sizeof(struct ip6_hdr) + sizeof(struct tcphdr))
 #else /* INET6 */
@@ -732,6 +736,9 @@ tcp_close(tp)
 		LIST_REMOVE(q, tqe_q);
 		m_freem(q->tqe_m);
 		FREE(q, M_TSEGQ);
+#ifdef CYGNUM_NET_TCP_REASS_DIVISOR
+		tcp_reass_qsize--;
+#endif
 	}
 	inp->inp_ppcb = NULL;
 	soisdisconnected(so);
@@ -770,6 +777,9 @@ tcp_drain()
 					LIST_REMOVE(te, tqe_q);
 					m_freem(te->tqe_m);
 					FREE(te, M_TSEGQ);
+#ifdef CYGNUM_NET_TCP_REASS_DIVISOR
+					tcp_reass_qsize--;
+#endif
 				}
 			}
 		}
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_usrreq.c b/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_usrreq.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_usrreq.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet/tcp_usrreq.c
@@ -132,7 +132,7 @@ tcp_usr_attach(struct socket *so, int pr
 	int s = splnet();
 	int error;
 	struct inpcb *inp = sotoinpcb(so);
-	struct tcpcb *tp = 0;
+	struct tcpcb *tp CYGBLD_ATTRIB_UNUSED = 0;
 	TCPDEBUG0;
 
 	TCPDEBUG1();
@@ -205,7 +205,7 @@ tcp_usr_bind(struct socket *so, struct s
 	int s = splnet();
 	int error = 0;
 	struct inpcb *inp = sotoinpcb(so);
-	struct tcpcb *tp;
+	struct tcpcb *tp CYGBLD_ATTRIB_UNUSED;
 	struct sockaddr_in *sinp;
 
 	COMMON_START();
@@ -234,7 +234,7 @@ tcp6_usr_bind(struct socket *so, struct 
 	int s = splnet();
 	int error = 0;
 	struct inpcb *inp = sotoinpcb(so);
-	struct tcpcb *tp;
+	struct tcpcb *tp CYGBLD_ATTRIB_UNUSED;
 	struct sockaddr_in6 *sin6p;
 
 	COMMON_START();
@@ -429,7 +429,7 @@ tcp_usr_accept(struct socket *so, struct
 	int s = splnet();
 	int error = 0;
 	struct inpcb *inp = sotoinpcb(so);
-	struct tcpcb *tp = NULL;
+	struct tcpcb *tp CYGBLD_ATTRIB_UNUSED = NULL;
 	TCPDEBUG0;
 
 	if (so->so_state & SS_ISDISCONNECTED) {
@@ -453,7 +453,7 @@ tcp6_usr_accept(struct socket *so, struc
 	int s = splnet();
 	int error = 0;
 	struct inpcb *inp = sotoinpcb(so);
-	struct tcpcb *tp = NULL;
+	struct tcpcb *tp CYGBLD_ATTRIB_UNUSED = NULL;
 	TCPDEBUG0;
 
 	if (so->so_state & SS_ISDISCONNECTED) {
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet/udp_usrreq.c b/packages/net/bsd_tcpip/current/src/sys/netinet/udp_usrreq.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet/udp_usrreq.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet/udp_usrreq.c
@@ -667,7 +667,6 @@ udp_output(inp, m, addr, control, p)
 	register struct udpiphdr *ui;
 	register int len = m->m_pkthdr.len;
 	struct in_addr laddr;
-	struct sockaddr_in *sin;
 	int s = 0, error = 0;
 
         bzero(&laddr, sizeof(laddr));
@@ -680,7 +679,6 @@ udp_output(inp, m, addr, control, p)
 	}
 
 	if (addr) {
-		sin = (struct sockaddr_in *)addr;
 		laddr = inp->inp_laddr;
 		if (inp->inp_faddr.s_addr != INADDR_ANY) {
 			error = EISCONN;
@@ -840,7 +838,6 @@ udp_connect(struct socket *so, struct so
 {
 	struct inpcb *inp;
 	int s, error;
-	struct sockaddr_in *sin;
 
 	inp = sotoinpcb(so);
 	if (inp == 0)
@@ -850,7 +847,6 @@ udp_connect(struct socket *so, struct so
 	error = 0;
 	s = splnet();
 	if (error == 0) {
-		sin = (struct sockaddr_in *)nam;
 		error = in_pcbconnect(inp, nam, p);
 	}
 	splx(s);
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet6/icmp6.c b/packages/net/bsd_tcpip/current/src/sys/netinet6/icmp6.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet6/icmp6.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet6/icmp6.c
@@ -2536,8 +2536,6 @@ icmp6_redirect_input(m, off)
 	int icmp6len = ntohs(ip6->ip6_plen);
 	char *lladdr = NULL;
 	int lladdrlen = 0;
-	u_char *redirhdr = NULL;
-	int redirhdrlen = 0;
 	struct rtentry *rt = NULL;
 	int is_router;
 	int is_onlink;
@@ -2670,11 +2668,6 @@ icmp6_redirect_input(m, off)
 		lladdrlen = ndopts.nd_opts_tgt_lladdr->nd_opt_len << 3;
 	}
 
-	if (ndopts.nd_opts_rh) {
-		redirhdrlen = ndopts.nd_opts_rh->nd_opt_rh_len;
-		redirhdr = (u_char *)(ndopts.nd_opts_rh + 1); /* xxx */
-	}
-
 	if (lladdr && ((ifp->if_addrlen + 2 + 7) & ~7) != lladdrlen) {
 		nd6log((LOG_INFO,
 			"icmp6_redirect_input: lladdrlen mismatch for %s "
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet6/in6_ifattach.c b/packages/net/bsd_tcpip/current/src/sys/netinet6/in6_ifattach.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet6/in6_ifattach.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet6/in6_ifattach.c
@@ -209,7 +209,7 @@ get_rand_ifid(ifp, in6)
 	/* generate 8 bytes of pseudo-random value. */
 	bzero(&ctxt, sizeof(ctxt));
 	MD5Init(&ctxt);
-	MD5Update(&ctxt, hostname, hostnamelen);
+	MD5Update(&ctxt, (unsigned char*)hostname, hostnamelen);
 	MD5Final(digest, &ctxt);
 
 	/* assumes sizeof(digest) > sizeof(ifid) */
@@ -411,7 +411,7 @@ get_hw_ifid(ifp, in6)
 	return -1;
 
 found:
-	addr = LLADDR(sdl);
+	addr = (unsigned char*)LLADDR(sdl);
 	addrlen = sdl->sdl_alen;
 
 	switch (ifp->if_type) {
@@ -841,7 +841,7 @@ in6_nigroup(ifp, name, namelen, in6)
 	l = p - name;
 	strncpy(n, name, l);
 	n[(int)l] = '\0';
-	for (q = n; *q; q++) {
+	for (q = (unsigned char*)n; *q; q++) {
 		if ('A' <= *q && *q <= 'Z')
 			*q = *q - 'A' + 'a';
 	}
@@ -849,8 +849,8 @@ in6_nigroup(ifp, name, namelen, in6)
 	/* generate 8 bytes of pseudo-random value. */
 	bzero(&ctxt, sizeof(ctxt));
 	MD5Init(&ctxt);
-	MD5Update(&ctxt, &l, sizeof(l));
-	MD5Update(&ctxt, n, l);
+	MD5Update(&ctxt, (unsigned char*)&l, sizeof(l));
+	MD5Update(&ctxt, (unsigned char*)n, l);
 	MD5Final(digest, &ctxt);
 
 	bzero(in6, sizeof(*in6));
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet6/in6_src.c b/packages/net/bsd_tcpip/current/src/sys/netinet6/in6_src.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet6/in6_src.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet6/in6_src.c
@@ -716,8 +716,6 @@ in6_selectroute(dstsock, opts, mopts, ro
 	 * a new one.
 	 */
 	if (ro) {
-		int newroute = 0;
-
 		if (ro->ro_rt &&
 		    (!(ro->ro_rt->rt_flags & RTF_UP) ||
 		     !IN6_ARE_ADDR_EQUAL(&satosin6(&ro->ro_dst)->sin6_addr,
@@ -729,7 +727,6 @@ in6_selectroute(dstsock, opts, mopts, ro
 			struct sockaddr_in6 *sa6;
 
 			/* No route yet, so try to acquire one */
-			newroute = 1;
 			bzero(&ro->ro_dst, sizeof(struct sockaddr_in6));
 			sa6 = (struct sockaddr_in6 *)&ro->ro_dst;
 			sa6->sin6_family = AF_INET6;
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet6/ip6_input.c b/packages/net/bsd_tcpip/current/src/sys/netinet6/ip6_input.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet6/ip6_input.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet6/ip6_input.c
@@ -222,7 +222,7 @@ int ip6_fw_enable = 1;
 
 struct ip6stat ip6stat;
 
-static void ip6_init2 __P((void *));
+void ip6_init2 __P((void *));
 static struct mbuf *ip6_setdstifaddr __P((struct mbuf *, struct in6_ifaddr *));
 
 static int ip6_hopopts_input __P((u_int32_t *, u_int32_t *, struct mbuf **, int *));
@@ -338,7 +338,7 @@ ip6_init()
 #endif
 }
 
-static void
+void
 ip6_init2(dummy)
 	void *dummy;
 {
@@ -1362,7 +1362,6 @@ ip6_hopopts_input(plenp, rtalertp, mp, o
 	struct mbuf *m = *mp;
 	int off = *offp, hbhlen;
 	struct ip6_hbh *hbh;
-	u_int8_t *opt;
 
 	/* validation of the length of the header */
 #ifndef PULLDOWN_TEST
@@ -1389,7 +1388,6 @@ ip6_hopopts_input(plenp, rtalertp, mp, o
 #endif
 	off += hbhlen;
 	hbhlen -= sizeof(struct ip6_hbh);
-	opt = (u_int8_t *)hbh + sizeof(struct ip6_hbh);
 
 	if (ip6_process_hopopts(m, (u_int8_t *)hbh + sizeof(struct ip6_hbh),
 				hbhlen, rtalertp, plenp) < 0)
@@ -1914,7 +1912,7 @@ ip6_savecontrol(in6p, ip6, m, ctl, prevc
 				struct ip6_rthdr *prevrth = NULL;
 				int prevrhlen = 0;
 
-				if (!in6p->in6p_flags & IN6P_RTHDR)
+				if (!(in6p->in6p_flags & IN6P_RTHDR))
 					break;
 
 				if (prevctl && prevctl->rthdr) {
@@ -2274,7 +2272,7 @@ ip6_get_prevhdr(m, off)
 	struct ip6_hdr *ip6 = mtod(m, struct ip6_hdr *);
 
 	if (off == sizeof(struct ip6_hdr))
-		return(&ip6->ip6_nxt);
+		return((char*)&ip6->ip6_nxt);
 	else {
 		int len, nxt;
 		struct ip6_ext *ip6e = NULL;
@@ -2298,7 +2296,7 @@ ip6_get_prevhdr(m, off)
 			nxt = ip6e->ip6e_nxt;
 		}
 		if (ip6e)
-			return(&ip6e->ip6e_nxt);
+			return((char*)&ip6e->ip6e_nxt);
 		else
 			return NULL;
 	}
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet6/ip6_mroute.c b/packages/net/bsd_tcpip/current/src/sys/netinet6/ip6_mroute.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet6/ip6_mroute.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet6/ip6_mroute.c
@@ -1605,7 +1605,7 @@ phyint_send(ip6, mifp, m)
 {
 	struct mbuf *mb_copy;
 	struct ifnet *ifp = mifp->m6_ifp;
-	int error = 0;
+	int error CYGBLD_ATTRIB_UNUSED = 0;
 #ifdef __NetBSD__
 	int s = splsoftnet();	/* needs to protect static "ro" below. */
 #else
@@ -1896,7 +1896,6 @@ pim6_input(mp, offp, proto)
 		struct mbuf *mcp;
 		struct ip6_hdr *eip6;
 		u_int32_t *reghdr;
-		int rc;
 	
 		++pim6stat.pim6s_rcv_registers;
 
@@ -2000,15 +1999,15 @@ pim6_input(mp, offp, proto)
 
 #if defined(__FreeBSD__) && __FreeBSD__ >= 3
 #if (__FreeBSD_version >= 410000)
- 		rc = if_simloop(mif6table[reg_mif_num].m6_ifp, m,
+ 		if_simloop(mif6table[reg_mif_num].m6_ifp, m,
 				dst.sin6_family, (int)NULL);
 #else
- 		rc = if_simloop(mif6table[reg_mif_num].m6_ifp, m,
+ 		if_simloop(mif6table[reg_mif_num].m6_ifp, m,
 				(struct sockaddr *) &dst, NULL);
 
 #endif
 #else
- 		rc = looutput(mif6table[reg_mif_num].m6_ifp, m,
+ 		looutput(mif6table[reg_mif_num].m6_ifp, m,
 			      (struct sockaddr *) &dst,
 			      (struct rtentry *) NULL);
 #endif
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet6/ip6_output.c b/packages/net/bsd_tcpip/current/src/sys/netinet6/ip6_output.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet6/ip6_output.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet6/ip6_output.c
@@ -1654,7 +1654,7 @@ ip6_insert_jumboopt(exthdrs, plen)
 			n->m_len = oldoptlen + JUMBOOPTLEN;
 			bcopy(mtod(mopt, caddr_t), mtod(n, caddr_t),
 			      oldoptlen);
-			optbuf = mtod(n, caddr_t) + oldoptlen;
+			optbuf = (unsigned char*)mtod(n, caddr_t) + oldoptlen;
 			m_freem(mopt);
 			mopt = exthdrs->ip6e_hbh = n;
 		} else {
@@ -1822,7 +1822,6 @@ ip6_ctloutput(op, so, level, optname, mp
 	void *optdata;
 	struct ip6_recvpktopts *rcvopts;
 #if defined(IPSEC) && defined(__OpenBSD__)
-	struct proc *p = curproc; /* XXX */
 	struct tdb *tdb;
 	struct tdb_ident *tdbip, tdbi;
 	int s;
@@ -1832,7 +1831,6 @@ ip6_ctloutput(op, so, level, optname, mp
 	int error, optval;
 	int level, op, optname;
 	int optlen;
-	struct proc *p;
 
 	if (!sopt) {
 		panic("ip6_ctloutput: arg soopt is NULL");
@@ -1841,7 +1839,6 @@ ip6_ctloutput(op, so, level, optname, mp
         op = sopt->sopt_dir;
         optname = sopt->sopt_name;
         optlen = sopt->sopt_valsize;
-        p = sopt->sopt_p;
 #else
 #ifdef HAVE_NRL_INPCB
 	struct inpcb *inp = sotoinpcb(so);
@@ -1853,7 +1850,6 @@ ip6_ctloutput(op, so, level, optname, mp
 	int error, optval;
 	int optlen;
 #if defined(__NetBSD__) || (defined(__FreeBSD__) && __FreeBSD__ >= 3)
-	struct proc *p = curproc;	/* XXX */
 #endif
 
 	optlen = m ? m->m_len : 0;
@@ -2863,7 +2859,6 @@ ip6_raw_ctloutput(op, so, level, optname
 #endif
 #if defined(__FreeBSD__) && __FreeBSD__ >= 3
 	int level, op, optname;
-	struct proc *p;
 #else
 	struct mbuf *m = *mp;
 #endif /* FreeBSD >= 3 */
@@ -2876,7 +2871,6 @@ ip6_raw_ctloutput(op, so, level, optname
         op = sopt->sopt_dir;
         optname = sopt->sopt_name;
         optlen = sopt->sopt_valsize;
-        p = sopt->sopt_p;
 #else
 	optlen = m ? m->m_len : 0;
 #endif /* FreeBSD >= 3 */
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet6/nd6.c b/packages/net/bsd_tcpip/current/src/sys/netinet6/nd6.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet6/nd6.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet6/nd6.c
@@ -496,7 +496,6 @@ nd6_timer(ignored_arg)
 #endif
 	struct ifnet *ifp;
 	struct in6_ifaddr *ia6, *nia6;
-	struct in6_addrlifetime *lt6;
 	
 #ifdef __NetBSD__
 	s = splsoftnet();
@@ -672,7 +671,6 @@ nd6_timer(ignored_arg)
 	for (ia6 = in6_ifaddr; ia6; ia6 = nia6) {
 		nia6 = ia6->ia_next;
 		/* check address lifetime */
-		lt6 = &ia6->ia6_lifetime;
 		if (IFA6_IS_INVALID(ia6)) {
 			int regen = 0;
 
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet6/nd6_nbr.c b/packages/net/bsd_tcpip/current/src/sys/netinet6/nd6_nbr.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet6/nd6_nbr.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet6/nd6_nbr.c
@@ -1460,7 +1460,6 @@ nd6_dad_ns_input(ifa)
 	struct ifaddr *ifa;
 {
 	struct in6_ifaddr *ia;
-	struct ifnet *ifp;
 	const struct in6_addr *taddr6;
 	struct dadq *dp;
 	int duplicate;
@@ -1469,7 +1468,6 @@ nd6_dad_ns_input(ifa)
 		panic("ifa == NULL in nd6_dad_ns_input");
 
 	ia = (struct in6_ifaddr *)ifa;
-	ifp = ifa->ifa_ifp;
 	taddr6 = &ia->ia_addr.sin6_addr;
 	duplicate = 0;
 	dp = nd6_dad_find(ifa);
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet6/nd6_rtr.c b/packages/net/bsd_tcpip/current/src/sys/netinet6/nd6_rtr.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet6/nd6_rtr.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet6/nd6_rtr.c
@@ -1258,7 +1258,6 @@ prelist_update(new, dr, m)
 	int s = splnet();
 #endif
 	int error = 0;
-	int newprefix = 0;
 	int auth;
 	struct in6_addrlifetime lt6_tmp;
 
@@ -1317,8 +1316,6 @@ prelist_update(new, dr, m)
 	} else {
 		struct nd_prefix *newpr = NULL;
 
-		newprefix = 1;
-
 		if (new->ndpr_vltime == 0)
 			goto end;
 		if (new->ndpr_raf_onlink == 0 && new->ndpr_raf_auto == 0)
diff --git a/packages/net/bsd_tcpip/current/src/sys/netinet6/raw_ip6.c b/packages/net/bsd_tcpip/current/src/sys/netinet6/raw_ip6.c
--- a/packages/net/bsd_tcpip/current/src/sys/netinet6/raw_ip6.c
+++ b/packages/net/bsd_tcpip/current/src/sys/netinet6/raw_ip6.c
@@ -259,9 +259,6 @@ rip6_ctlinput(cmd, sa, d)
 	struct sockaddr *sa;
 	void *d;
 {
-	struct ip6_hdr *ip6;
-	struct mbuf *m;
-	int off = 0;
 	struct ip6ctlparam *ip6cp = NULL;
 	const struct sockaddr_in6 *sa6_src = NULL;
 	void *cmdarg;
@@ -283,14 +280,9 @@ rip6_ctlinput(cmd, sa, d)
 	/* if the parameter is from icmp6, decode it. */
 	if (d != NULL) {
 		ip6cp = (struct ip6ctlparam *)d;
-		m = ip6cp->ip6c_m;
-		ip6 = ip6cp->ip6c_ip6;
-		off = ip6cp->ip6c_off;
 		cmdarg = ip6cp->ip6c_cmdarg;
 		sa6_src = ip6cp->ip6c_src;
 	} else {
-		m = NULL;
-		ip6 = NULL;
 		cmdarg = NULL;
 		sa6_src = &sa6_any;
 	}
diff --git a/packages/net/common/current/ChangeLog b/packages/net/common/current/ChangeLog
--- a/packages/net/common/current/ChangeLog
+++ b/packages/net/common/current/ChangeLog
@@ -1,3 +1,22 @@
+2012-03-13  Grant Edwards <grant.b.edwards@gmail.com>
+
+	* src/bootp_support.c (init_net): Fix compiler warning by removing
+	'netmask' variable which is set but then never used.
+	[ Bugzilla 1001516 ]
+	
+2012-03-06  Grant Edwards <grant.b.edwards@gmail.com>
+	
+	* current/src/inet_ntop.c (inet_ntop6): Fixed compiler warnings
+	about variables possibly used before they are initialized.
+	[ Bugzilla 1001509 ]
+
+2011-03-09  Jay Foster <jay@systech.com>
+            Sergei Gavrikov <sergei.gavrikov@gmail.com>
+
+	* src/bootp_support.c (show_bootp): Fixed output for some fields.
+	* src/dhcp_prot.c (do_dhcp): Convert bp_secs field to network byte
+	order. Inspired by Kelvin Lawson. [ Bugzilla 1001170 ]
+
 2009-09-17	Jay Foster <jay@systech.com>
 
 	* src/dhcp_prot.c (do_dhcp): Fix packet parsing for DHCP servers
diff --git a/packages/net/common/current/src/bootp_support.c b/packages/net/common/current/src/bootp_support.c
--- a/packages/net/common/current/src/bootp_support.c
+++ b/packages/net/common/current/src/bootp_support.c
@@ -274,8 +274,8 @@ show_bootp(const char *intf, struct boot
     diag_printf("        hlen: %d\n", bp->bp_hlen );
     diag_printf("        hops: %d\n", bp->bp_hops );
     diag_printf("         xid: 0x%x\n", bp->bp_xid );
-    diag_printf("        secs: %d\n", bp->bp_secs );
-    diag_printf("       flags: 0x%x\n", bp->bp_flags );
+    diag_printf("        secs: %d\n", ntohs(bp->bp_secs) );
+    diag_printf("       flags: 0x%x\n", ntohs(bp->bp_flags) );
     diag_printf("       hw_addr: ");
     for (i = 0;  i < bp->bp_hlen;  i++) {
         diag_printf("%02x", bp->bp_chaddr[i]);
@@ -449,7 +449,7 @@ init_net(const char *intf, struct bootp 
     int s=-1;
     int one = 1;
     struct ecos_rtentry route;
-    struct in_addr netmask, gateway;
+    struct in_addr gateway;
     unsigned int length;
     int retcode = false;
     
@@ -481,7 +481,6 @@ init_net(const char *intf, struct bootp 
 
     length = sizeof(addrp->sin_addr);
     if (get_bootp_option(bp, TAG_SUBNET_MASK, &addrp->sin_addr,&length)) {
-        netmask = addrp->sin_addr;
         if (ioctl(s, SIOCSIFNETMASK, &ifr)) {
             perror("SIOCSIFNETMASK");
             goto out;
diff --git a/packages/net/common/current/src/dhcp_prot.c b/packages/net/common/current/src/dhcp_prot.c
--- a/packages/net/common/current/src/dhcp_prot.c
+++ b/packages/net/common/current/src/dhcp_prot.c
@@ -701,6 +701,7 @@ do_dhcp(const char *intf, struct bootp *
     unsigned int length;
     
     cyg_uint32 xid;
+    unsigned short bp_secs;
 
 #define CHECK_XID() (  /* and other details */                                  \
     received->bp_xid   != xid            || /* not the same transaction */      \
@@ -842,7 +843,8 @@ do_dhcp(const char *intf, struct bootp *
             xmit->bp_htype = HTYPE_ETHERNET;
             xmit->bp_hlen = IFHWADDRLEN;
             xmit->bp_xid = xid;
-            xmit->bp_secs = cyg_current_time() / 100;
+            bp_secs = cyg_current_time() / 100;
+            xmit->bp_secs = htons(bp_secs);
             xmit->bp_flags = htons(0x8000); // BROADCAST FLAG
             bcopy(ifr.ifr_hwaddr.sa_data, &xmit->bp_chaddr, xmit->bp_hlen);
             bcopy(mincookie, xmit->bp_vend, sizeof(mincookie));
diff --git a/packages/net/common/current/src/inet_ntop.c b/packages/net/common/current/src/inet_ntop.c
--- a/packages/net/common/current/src/inet_ntop.c
+++ b/packages/net/common/current/src/inet_ntop.c
@@ -190,7 +190,9 @@ inet_ntop6(const u_char *src, char *dst,
 	memset(words, '\0', sizeof words);
 	for (i = 0; i < IN6ADDRSZ; i++)
 		words[i / 2] |= (src[i] << ((1 - (i % 2)) << 3));
+	best.len = 0;
 	best.base = -1;
+	cur.len = 0;
 	cur.base = -1;
 	for (i = 0; i < (IN6ADDRSZ / INT16SZ); i++) {
 		if (words[i] == 0) {
diff --git a/packages/net/httpd/current/ChangeLog b/packages/net/httpd/current/ChangeLog
--- a/packages/net/httpd/current/ChangeLog
+++ b/packages/net/httpd/current/ChangeLog
@@ -1,3 +1,7 @@
+2010-09-18  John Dallaway  <john@dallaway.org.uk>
+
+	* doc/httpd.sgml: Fix GoAhead URL.
+
 2006-07-28  Jochen Gerster <JochenGerster@gmx.de>
 
 	* src/monitor.c (cyg_monitor_network): Calling the network monitor
@@ -102,8 +106,24 @@ 2002-12-06  Nick Garnett  <nickg@ecoscen
 	* cdl/httpd.cdl: 
 	Created HTTPD package.
 	
-# Copyright (C) 2002 Nick Garnett
-# All Rights Reserved.
+# ####GPLCOPYRIGHTBEGIN####                                       
+# -------------------------------------------                     
+# This file is part of eCos, the Embedded Configurable Operating System.
+# Copyright (C) 2002, 2010 Free Software Foundation, Inc.   
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 or (at your option) any
+# later version.                                                  
 #
-# Permission is granted to use, copy, modify and redistribute this
-# file.
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of      
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.                        
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the                   
+# Free Software Foundation, Inc., 51 Franklin Street,             
+# Fifth Floor, Boston, MA  02110-1301, USA.                       
+# -------------------------------------------                     
+# ####GPLCOPYRIGHTEND####                                         
diff --git a/packages/net/httpd/current/doc/httpd.sgml b/packages/net/httpd/current/doc/httpd.sgml
--- a/packages/net/httpd/current/doc/httpd.sgml
+++ b/packages/net/httpd/current/doc/httpd.sgml
@@ -8,7 +8,7 @@
 <!-- =============================================================== -->
 <!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
 <!-- =============================================================== -->
-<!-- Copyright (C) 2002 Free Software Foundation, Inc.               -->
+<!-- Copyright (C) 2002, 2010 Free Software Foundation, Inc.         -->
 <!-- This material may be distributed only subject to the terms      -->
 <!-- and conditions set forth in the Open Publication License, v1.0  -->
 <!-- or later (the latest version is presently available at          -->
@@ -40,7 +40,7 @@ content, simple forms handling and a bas
 <emphasis>not</emphasis> intended to be a general purpose server for
 delivering arbitrary web content. For these purposes a port of the
 GoAhead web server is available from <ulink
-url="www.goahead.com">www.goahead.com</ulink>.
+url="http://www.goahead.com">www.goahead.com</ulink>.
 </para>
 <para>This server is also capable of serving content using IPv6 when
 the eCos configuration contains IPv6.
diff --git a/packages/net/lwip_tcpip/current/ChangeLog b/packages/net/lwip_tcpip/current/ChangeLog
--- a/packages/net/lwip_tcpip/current/ChangeLog
+++ b/packages/net/lwip_tcpip/current/ChangeLog
@@ -1,3 +1,73 @@
+2013-03-03  Mike Jones  <mike@proclivis.com>
+
+	* src/core/snmp/msg_out.c: Applied lwip bugfix #29256.
+	ip_addr_set_hton(...) does not exist in this revision,
+	so an equivalent solution was provided. The application
+	was retested. Any application that worked around the problem by
+	using htonl(...) will need to be changed by removing it.
+	[ Bugzilla 1001789 ]
+
+2012-05-26  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* tests/nc_test_slave.c: Reduced stack sizes of IDLE, LOAD and TMAIN
+	threads as well as NUM_LOAD_THREADS to 5 (was 10) in order to fit the
+	test for targets with as low as 128KiB RAM.
+	Bug fix: MAX_BUF fixed so that in_buf[] and out_buf[] can accomodate
+	10KiB messages.
+	[ Bugzilla 1001344 ]
+
+2012-03-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+    * src/core/tcp_out.c: Fix compiler warning about unused variables.
+    [Bugzilla 1001521]
+
+2011-08-23  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* tests/nc_test_slave.c: Reduced stack sizes of IDLE, LOAD and TMAIN
+	threads as well as NUM_LOAD_THREADS to 5 (was 10) in order to fit the
+	test for targets with as low as 128KiB RAM.
+	[ Bugzilla 1001344 ]
+
+2011-08-25  John Dallaway  <john@dallaway.org.uk>
+
+	* include/lwipopts.h: Fix naming of
+	CYGNUM_LWIP_NETIF_LOOPBACK_MAX_PBUFS. Patch from Christophe Coutand.
+	[ Bugzilla 1001323 ]
+
+2011-08-23  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/lwip_net.cdl: New CDL option CYGIMP_LWIP_ENDIAN_BY_HAL.
+	* include/lwipopts.h: Add HAL override of htonl() and htons().
+	[ Bugzilla 1001275 ]
+
+2011-03-08  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/lwip_net.cdl: Require CYGPKG_ISOINFRA.
+	* include/arch/cc.h: Define ERRNO if CYGINT_ISO_ERRNO is
+	implemented. Based on patch from Will Wagner. [ Bugzilla 1001169 ]
+
+2011-01-30  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/lwip_net.cdl: New CDL option CYGSEM_LWIP_MEM_SECTION.
+	* include/lwipopts.h: Enter MEM_SECTION entity.
+	* src/mem.c, src/memp.c: Add an ability to use GCC section
+	attribute for statically allocated buffers, pbufs, and heap.
+
+2011-01-02  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/ecos/sequential.c, src/ecos/simple.c: Fixed miltiple-line
+	comment warnings.
+
+2010-12-10  Christophe Coutand  <ccoutand@stmi.com>
+
+	* include/lwipopts.h: Fix compilation error when compiling SNMP
+	code.
+
+2010-08-02  John Dallaway  <john@dallaway.org.uk>
+
+	* include/network.h: Match braces when including from C++ code.
+	Issue reported by Will Wagner.
+
 2010-02-07  John Dallaway  <john@dallaway.org.uk>
 
 	* cdl/lwip_net.cdl: Rename CFLAGS_ADD and CFLAGS_REMOVE options to
@@ -217,7 +287,7 @@ 2004-05-04  Jani Monoses <jani@iv.ro>
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2004, 2010 Free Software Foundation 
+// Copyright (C) 2004, 2010, 2011 Free Software Foundation 
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
diff --git a/packages/net/lwip_tcpip/current/cdl/lwip_net.cdl b/packages/net/lwip_tcpip/current/cdl/lwip_net.cdl
--- a/packages/net/lwip_tcpip/current/cdl/lwip_net.cdl
+++ b/packages/net/lwip_tcpip/current/cdl/lwip_net.cdl
@@ -8,7 +8,7 @@
 #####ECOSGPLCOPYRIGHTBEGIN####
 ## -------------------------------------------
 ## This file is part of eCos, the Embedded Configurable Operating System.
-## Copyright (C) 2008, 2009, 2010 Free Software Foundation
+## Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation
 ##
 ## eCos is free software; you can redistribute it and/or modify it under
 ## the terms of the GNU General Public License as published by the Free
@@ -48,6 +48,7 @@
 cdl_package CYGPKG_NET_LWIP {
     display         "lwIP networking stack"
     description     "The lightweight TCP/IP stack."
+    requires        CYGPKG_ISOINFRA
     requires        CYGINT_ISO_ERRNO_CODES
 	
     compile         core/dns.c                  \
@@ -126,6 +127,17 @@ cdl_package CYGPKG_NET_LWIP {
         compile         ecos/sio.c
     }
     
+    cdl_option CYGIMP_LWIP_ENDIAN_BY_HAL {
+        display       "HAL optimized endian functions"
+        flavor        bool
+        active_if     CYGIMP_HAL_ARCH_ENDIAN
+        default_value CYGIMP_HAL_ARCH_ENDIAN
+        description   "
+            Some architectures provide optimized functions for endian
+            manipulation (byte swapping). If utilized, they can give
+            shorter and faster code for that."
+    }
+
     cdl_component CYGPKG_LWIP_APIS {
         display         "APIs"
         flavor          none
@@ -1422,6 +1434,33 @@ cdl_package CYGPKG_NET_LWIP {
                 to accomodate single full size TCP frame in one pbuf, including
                 TCP_MSS, IP header, and link header."
         }       
+
+        cdl_component CYGOPT_LWIP_MEM_PLF_SPEC {
+            display         "Platform/application specific memory settings"
+            flavor          none
+            no_define
+            description     "
+                Platform or application specific settings such as special
+                memory section and memory constrains."
+
+            cdl_option CYGSEM_LWIP_MEM_SECTION {
+                display         "Place lwIP buffers and heap in special\
+                                        memory section."
+                flavor          bool
+                default_value   is_active(CYGDAT_LWIP_MEM_SECTION_NAME)
+                active_if       CYGDAT_LWIP_MEM_SECTION_NAME
+
+                description     "
+                    If you need lwIP buffers to appear in some special
+                    memory section (it is useful for devices with low
+                    memory footprint that is in addition fragmented
+                    in several non-contiguous blocks) the platform
+                    config file should provide the name of this section
+                    through CYGDAT_LWIP_MEM_SECTION_NAME option, if so,
+                    you can let to use the GCC section attribute for
+                    needed variables by this option."
+            }
+        }
     }
     
     cdl_component CYGPKG_LWIP_THREADS {
diff --git a/packages/net/lwip_tcpip/current/include/arch/cc.h b/packages/net/lwip_tcpip/current/include/arch/cc.h
--- a/packages/net/lwip_tcpip/current/include/arch/cc.h
+++ b/packages/net/lwip_tcpip/current/include/arch/cc.h
@@ -2,7 +2,7 @@
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2008 Free Software Foundation
+// Copyright (C) 2008, 2011 Free Software Foundation
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
@@ -34,7 +34,7 @@
 #define __LWIP_ARCH_CC_H__
 
 #include <string.h>
-#include <cyg/error/codes.h>
+#include <errno.h>
 #include <cyg/infra/cyg_type.h>
 
 typedef int sys_prot_t;
@@ -47,6 +47,11 @@ typedef int sys_prot_t;
 #define ETIME           62
 #define ENSRNOTFOUND    163
 
+// If errno support, define ERRNO used in api/sockets.c
+#if CYGINT_ISO_ERRNO > 0
+#define ERRNO
+#endif
+
 // Platform byteorder
 #if (CYG_BYTEORDER == CYG_LSBFIRST)
 #define BYTE_ORDER LITTLE_ENDIAN
diff --git a/packages/net/lwip_tcpip/current/include/lwipopts.h b/packages/net/lwip_tcpip/current/include/lwipopts.h
--- a/packages/net/lwip_tcpip/current/include/lwipopts.h
+++ b/packages/net/lwip_tcpip/current/include/lwipopts.h
@@ -4,7 +4,7 @@
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2008, 2009 Free Software Foundation
+// Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
@@ -36,6 +36,10 @@
 
 #include <cyg/hal/hal_arch.h>
 
+#if defined(CYGIMP_LWIP_ENDIAN_BY_HAL) && CYGIMP_LWIP_ENDIAN_BY_HAL
+# include <cyg/hal/hal_endian.h>
+#endif
+
 //------------------------------------------------------------------------------
 // Platform specific locking
 //------------------------------------------------------------------------------
@@ -44,6 +48,16 @@
 #define NO_SYS                      defined(CYGFUN_LWIP_MODE_SIMPLE)
 
 //------------------------------------------------------------------------------
+// Architecture specific options
+//------------------------------------------------------------------------------
+
+#if defined(CYGIMP_LWIP_ENDIAN_BY_HAL) && CYGIMP_LWIP_ENDIAN_BY_HAL
+# define LWIP_PLATFORM_BYTESWAP     1
+# define LWIP_PLATFORM_HTONS(__val) CYG_CPU_TO_BE16(__val)
+# define LWIP_PLATFORM_HTONL(__val) CYG_CPU_TO_BE32(__val)
+#endif
+
+//------------------------------------------------------------------------------
 // Memory options
 //------------------------------------------------------------------------------
 
@@ -51,6 +65,14 @@
 #define MEMP_MEM_MALLOC             defined(CYGIMP_LWIP_MEMP_MEM_MALLOC)
 #define MEM_ALIGNMENT               CYGNUM_LWIP_MEM_ALIGNMENT
 #define MEM_SIZE                    CYGNUM_LWIP_MEM_SIZE
+
+#if defined(CYGSEM_LWIP_MEM_SECTION) && CYGSEM_LWIP_MEM_SECTION
+# include <cyg/infra/cyg_type.h>
+# define MEM_SECTION CYGBLD_ATTRIB_SECTION(CYGDAT_LWIP_MEM_SECTION_NAME)
+#else
+# define MEM_SECTION
+#endif
+
 #define MEMP_OVERFLOW_CHECK         defined(CYGDBG_LWIP_MEMP_OVERFLOW_CHECK)
 #define MEMP_SANITY_CHECK           defined(CYGDBG_LWIP_MEMP_SANITY_CHECK)
 
@@ -99,7 +121,9 @@
 // IP options
 //------------------------------------------------------------------------------
 
-#define IP_FORWARD                  defined(CYGFUN_LWIP_IP_FORWARD)
+#ifdef CYGFUN_LWIP_IP_FORWARD
+# define IP_FORWARD                 1
+#endif
 #define IP_OPTIONS_ALLOWED          defined(CYGFUN_LWIP_IP_OPTIONS_ALLOWED)
 #define IP_REASSEMBLY               defined(CYGFUN_LWIP_IP_REASSEMBLY)
 #define IP_FRAG                     defined(CYGFUN_LWIP_IP_FRAG)
@@ -251,7 +275,7 @@
 #define LWIP_NETIF_LINK_CALLBACK    defined(CYGFUN_LWIP_NETIF_LINK_CALLBACK)
 #define LWIP_NETIF_HWADDRHINT       defined(CYGIMP_LWIP_NETIF_HWADDRHINT)
 #define LWIP_NETIF_LOOPBACK         defined(CYGIMP_LWIP_NETIF_LOOPBACK)
-#define LWIP_LOOPBACK_MAX_PBUFS     CYGIMP_LWIP_NETIF_LOOPBACK_MAX_PBUFS
+#define LWIP_LOOPBACK_MAX_PBUFS     CYGNUM_LWIP_NETIF_LOOPBACK_MAX_PBUFS
 //#define LWIP_NETIF_LOOPBACK_MULTITHREADING // not configurable
 //#define LWIP_NETIF_TX_SINGLE_PBUF // not configurable
 
diff --git a/packages/net/lwip_tcpip/current/include/network.h b/packages/net/lwip_tcpip/current/include/network.h
--- a/packages/net/lwip_tcpip/current/include/network.h
+++ b/packages/net/lwip_tcpip/current/include/network.h
@@ -57,5 +57,9 @@ extern "C" {
 #endif
 
 #include <lwip.h>
+
+#ifdef __cplusplus
+}
+#endif
     
 #endif // #ifndef CYGONCE_NETWORK_H
diff --git a/packages/net/lwip_tcpip/current/src/core/inet.c b/packages/net/lwip_tcpip/current/src/core/inet.c
deleted file mode 100644
--- a/packages/net/lwip_tcpip/current/src/core/inet.c
+++ /dev/null
@@ -1,525 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-
-/* inet.c
- *
- * Functions common to all TCP/IP modules, such as the Internet checksum and the
- * byte order functions.
- *
- */
-
-
-#include "lwip/opt.h"
-
-#include "lwip/arch.h"
-
-#include "lwip/def.h"
-#include "lwip/inet.h"
-
-#include "lwip/sys.h"
-
-/* This is a reference implementation of the checksum algorithm, with the
- * aim of being simple, correct and fully portable. Checksumming is the
- * first thing you would want to optimize for your platform. You will
- * need to port it to your architecture and in your sys_arch.h:
- * 
- * #define LWIP_CHKSUM <your_checksum_routine> 
-*/
-#ifndef LWIP_CHKSUM
-#define LWIP_CHKSUM lwip_standard_chksum
-
-/**
- * lwip checksum
- *
- * @param dataptr points to start of data to be summed at any boundary
- * @param len length of data to be summed
- * @return host order (!) lwip checksum (non-inverted Internet sum) 
- *
- * @note accumulator size limits summable lenght to 64k
- * @note host endianess is irrelevant (p3 RFC1071)
- */
-static u16_t
-lwip_standard_chksum(void *dataptr, u16_t len)
-{
-  u32_t acc;
-  u16_t src;
-  u8_t *octetptr;
-
-  acc = 0;
-  /* dataptr may be at odd or even addresses */
-  octetptr = (u8_t*)dataptr;
-  while (len > 1)
-  {
-    /* declare first octet as most significant
-       thus assume network order, ignoring host order */
-    src = (*octetptr) << 8;
-    octetptr++;
-    /* declare second octet as least significant */
-    src |= (*octetptr);
-    octetptr++;
-    acc += src;
-    len -= 2;
-  }
-  if (len > 0)
-  {
-    /* accumulate remaining octet */
-    src = (*octetptr) << 8;
-    acc += src;
-  }
-  /* add deferred carry bits */
-  acc = (acc >> 16) + (acc & 0x0000ffffUL);
-  if ((acc & 0xffff0000) != 0) {
-    acc = (acc >> 16) + (acc & 0x0000ffffUL);
-  }
-  /* This maybe a little confusing: reorder sum using htons()
-     instead of ntohs() since it has a little less call overhead.
-     The caller must invert bits for Internet sum ! */
-  return htons((u16_t)acc);
-}
-
-#endif
-
-#if 0
-/*
- * Curt McDowell
- * Broadcom Corp.
- * csm@broadcom.com
- *
- * IP checksum two bytes at a time with support for
- * unaligned buffer.
- * Works for len up to and including 0x20000.
- * by Curt McDowell, Broadcom Corp. 12/08/2005
- */
-
-static u16_t
-lwip_standard_chksum2(void *dataptr, int len)
-{
-  u8_t *pb = dataptr;
-  u16_t *ps, t = 0;
-  u32_t sum = 0;
-  int odd = ((u32_t)pb & 1);
-
-  /* Get aligned to u16_t */
-  if (odd && len > 0) {
-    ((u8_t *)&t)[1] = *pb++;
-    len--;
-  }
-
-  /* Add the bulk of the data */
-  ps = (u16_t *)pb;
-  while (len > 1) {
-    sum += *ps++;
-    len -= 2;
-  }
-
-  /* Consume left-over byte, if any */
-  if (len > 0)
-    ((u8_t *)&t)[0] = *(u8_t *)ps;;
-
-  /* Add end bytes */
-  sum += t;
-
-  /*  Fold 32-bit sum to 16 bits */
-  while (sum >> 16)
-    sum = (sum & 0xffff) + (sum >> 16);
-
-  /* Swap if alignment was odd */
-  if (odd)
-    sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8);
-
-  return sum;
-}
-
-/**
- * An optimized checksum routine. Basically, it uses loop-unrolling on
- * the checksum loop, treating the head and tail bytes specially, whereas
- * the inner loop acts on 8 bytes at a time. 
- *
- * @arg start of buffer to be checksummed. May be an odd byte address.
- * @len number of bytes in the buffer to be checksummed.
- * 
- * @todo First argument type conflicts with generic checksum routine.
- * 
- * by Curt McDowell, Broadcom Corp. December 8th, 2005
- */
-
-static u16_t
-lwip_standard_chksum4(u8_t *pb, int len)
-{
-  u16_t *ps, t = 0;
-  u32_t *pl;
-  u32_t sum = 0, tmp;
-  /* starts at odd byte address? */
-  int odd = ((u32_t)pb & 1);
-
-  if (odd && len > 0) {
-    ((u8_t *)&t)[1] = *pb++;
-    len--;
-  }
-
-  ps = (u16_t *)pb;
-
-  if (((u32_t)ps & 3) && len > 1) {
-    sum += *ps++;
-    len -= 2;
-  }
-
-  pl = (u32_t *)ps;
-
-  while (len > 7)  {
-    tmp = sum + *pl++;          /* ping */
-    if (tmp < sum)
-      tmp++;                    /* add back carry */
-
-    sum = tmp + *pl++;          /* pong */
-    if (sum < tmp)
-      sum++;                    /* add back carry */
-
-    len -= 8;
-  }
-
-  /* make room in upper bits */
-  sum = (sum >> 16) + (sum & 0xffff);
-
-  ps = (u16_t *)pl;
-
-  /* 16-bit aligned word remaining? */
-  while (len > 1) {
-    sum += *ps++;
-    len -= 2;
-  }
-
-  /* dangling tail byte remaining? */
-  if (len > 0)                  /* include odd byte */
-    ((u8_t *)&t)[0] = *(u8_t *)ps;
-
-  sum += t;                     /* add end bytes */
-
-  while (sum >> 16)             /* combine halves */
-    sum = (sum >> 16) + (sum & 0xffff);
-
-  if (odd)
-    sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8);
-
-  return sum;
-}
-#endif
-
-/* inet_chksum_pseudo:
- *
- * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
- */
-
-u16_t
-inet_chksum_pseudo(struct pbuf *p,
-       struct ip_addr *src, struct ip_addr *dest,
-       u8_t proto, u16_t proto_len)
-{
-  u32_t acc;
-  struct pbuf *q;
-  u8_t swapped;
-
-  acc = 0;
-  swapped = 0;
-  /* iterate through all pbuf in chain */
-  for(q = p; q != NULL; q = q->next) {
-    LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
-      (void *)q, (void *)q->next));
-    acc += LWIP_CHKSUM(q->payload, q->len);
-    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/
-    while (acc >> 16) {
-      acc = (acc & 0xffffUL) + (acc >> 16);
-    }
-    if (q->len % 2 != 0) {
-      swapped = 1 - swapped;
-      acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
-    }
-    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/
-  }
-
-  if (swapped) {
-    acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
-  }
-  acc += (src->addr & 0xffffUL);
-  acc += ((src->addr >> 16) & 0xffffUL);
-  acc += (dest->addr & 0xffffUL);
-  acc += ((dest->addr >> 16) & 0xffffUL);
-  acc += (u32_t)htons((u16_t)proto);
-  acc += (u32_t)htons(proto_len);
-
-  while (acc >> 16) {
-    acc = (acc & 0xffffUL) + (acc >> 16);
-  }
-  LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc));
-  return (u16_t)~(acc & 0xffffUL);
-}
-
-/* inet_chksum:
- *
- * Calculates the Internet checksum over a portion of memory. Used primarely for IP
- * and ICMP.
- */
-
-u16_t
-inet_chksum(void *dataptr, u16_t len)
-{
-  u32_t acc;
-
-  acc = LWIP_CHKSUM(dataptr, len);
-  while (acc >> 16) {
-    acc = (acc & 0xffff) + (acc >> 16);
-  }
-  return (u16_t)~(acc & 0xffff);
-}
-
-u16_t
-inet_chksum_pbuf(struct pbuf *p)
-{
-  u32_t acc;
-  struct pbuf *q;
-  u8_t swapped;
-
-  acc = 0;
-  swapped = 0;
-  for(q = p; q != NULL; q = q->next) {
-    acc += LWIP_CHKSUM(q->payload, q->len);
-    while (acc >> 16) {
-      acc = (acc & 0xffffUL) + (acc >> 16);
-    }
-    if (q->len % 2 != 0) {
-      swapped = 1 - swapped;
-      acc = (acc & 0x00ffUL << 8) | (acc & 0xff00UL >> 8);
-    }
-  }
-
-  if (swapped) {
-    acc = ((acc & 0x00ffUL) << 8) | ((acc & 0xff00UL) >> 8);
-  }
-  return (u16_t)~(acc & 0xffffUL);
-}
-
-/* Here for now until needed in other places in lwIP */
-#ifndef isascii
-#define in_range(c, lo, up)  ((u8_t)c >= lo && (u8_t)c <= up)
-#define isascii(c)           in_range(c, 0x20, 0x7f)
-#define isdigit(c)           in_range(c, '0', '9')
-#define isxdigit(c)          (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
-#define islower(c)           in_range(c, 'a', 'z')
-#define isspace(c)           (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v')
-#endif		
-		
-
- /*
-  * Ascii internet address interpretation routine.
-  * The value returned is in network order.
-  */
-
- /*  */
- /* inet_addr */
- u32_t inet_addr(const char *cp)
- {
-     struct in_addr val;
-
-     if (inet_aton(cp, &val)) {
-         return (val.s_addr);
-     }
-     return (INADDR_NONE);
- }
-
- /*
-  * Check whether "cp" is a valid ascii representation
-  * of an Internet address and convert to a binary address.
-  * Returns 1 if the address is valid, 0 if not.
-  * This replaces inet_addr, the return value from which
-  * cannot distinguish between failure and a local broadcast address.
-  */
- /*  */
- /* inet_aton */
- s8_t
- inet_aton(const char *cp, struct in_addr *addr)
- {
-     u32_t val;
-     s32_t base, n;
-     char c;
-     u32_t parts[4];
-     u32_t* pp = parts;
-
-     c = *cp;
-     for (;;) {
-         /*
-          * Collect number up to ``.''.
-          * Values are specified as for C:
-          * 0x=hex, 0=octal, isdigit=decimal.
-          */
-         if (!isdigit(c))
-             return (0);
-         val = 0; base = 10;
-         if (c == '0') {
-             c = *++cp;
-             if (c == 'x' || c == 'X')
-                 base = 16, c = *++cp;
-             else
-                 base = 8;
-         }
-         for (;;) {
-             if (isdigit(c)) {
-                 val = (val * base) + (s16_t)(c - '0');
-                 c = *++cp;
-             } else if (base == 16 && isxdigit(c)) {
-                 val = (val << 4) |
-                     (s16_t)(c + 10 - (islower(c) ? 'a' : 'A'));
-                 c = *++cp;
-             } else
-             break;
-         }
-         if (c == '.') {
-             /*
-              * Internet format:
-              *  a.b.c.d
-              *  a.b.c   (with c treated as 16 bits)
-              *  a.b (with b treated as 24 bits)
-              */
-             if (pp >= parts + 3)
-                 return (0);
-             *pp++ = val;
-             c = *++cp;
-         } else
-             break;
-     }
-     /*
-      * Check for trailing characters.
-      */
-     if (c != '\0' && (!isascii(c) || !isspace(c)))
-         return (0);
-     /*
-      * Concoct the address according to
-      * the number of parts specified.
-      */
-     n = pp - parts + 1;
-     switch (n) {
-
-     case 0:
-         return (0);     /* initial nondigit */
-
-     case 1:             /* a -- 32 bits */
-         break;
-
-     case 2:             /* a.b -- 8.24 bits */
-         if (val > 0xffffff)
-             return (0);
-         val |= parts[0] << 24;
-         break;
-
-     case 3:             /* a.b.c -- 8.8.16 bits */
-         if (val > 0xffff)
-             return (0);
-         val |= (parts[0] << 24) | (parts[1] << 16);
-         break;
-
-     case 4:             /* a.b.c.d -- 8.8.8.8 bits */
-         if (val > 0xff)
-             return (0);
-         val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
-         break;
-     }
-     if (addr)
-         addr->s_addr = htonl(val);
-     return (1);
- }
-
-/* Convert numeric IP address into decimal dotted ASCII representation.
- * returns ptr to static buffer; not reentrant!
- */
-char *inet_ntoa(struct in_addr addr)
-{
-  static char str[16];
-  u32_t s_addr = addr.s_addr;
-  char inv[3];
-  char *rp;
-  u8_t *ap;
-  u8_t rem;
-  u8_t n;
-  u8_t i;
-
-  rp = str;
-  ap = (u8_t *)&s_addr;
-  for(n = 0; n < 4; n++) {
-    i = 0;
-    do {
-      rem = *ap % (u8_t)10;
-      *ap /= (u8_t)10;
-      inv[i++] = '0' + rem;
-    } while(*ap);
-    while(i--)
-      *rp++ = inv[i];
-    *rp++ = '.';
-    ap++;
-  }
-  *--rp = 0;
-  return str;
-}
-
-
-#ifndef BYTE_ORDER
-#error BYTE_ORDER is not defined
-#endif
-#if BYTE_ORDER == LITTLE_ENDIAN
-
-u16_t
-htons(u16_t n)
-{
-  return ((n & 0xff) << 8) | ((n & 0xff00) >> 8);
-}
-
-u16_t
-ntohs(u16_t n)
-{
-  return htons(n);
-}
-
-u32_t
-htonl(u32_t n)
-{
-  return ((n & 0xff) << 24) |
-    ((n & 0xff00) << 8) |
-    ((n & 0xff0000) >> 8) |
-    ((n & 0xff000000) >> 24);
-}
-
-u32_t
-ntohl(u32_t n)
-{
-  return htonl(n);
-}
-
-#endif /* BYTE_ORDER == LITTLE_ENDIAN */
diff --git a/packages/net/lwip_tcpip/current/src/core/mem.c b/packages/net/lwip_tcpip/current/src/core/mem.c
--- a/packages/net/lwip_tcpip/current/src/core/mem.c
+++ b/packages/net/lwip_tcpip/current/src/core/mem.c
@@ -172,7 +172,7 @@ struct mem {
 #define MEM_SIZE_ALIGNED     LWIP_MEM_ALIGN_SIZE(MEM_SIZE)
 
 /** the heap. we need one struct mem at the end and some room for alignment */
-static u8_t ram_heap[MEM_SIZE_ALIGNED + (2*SIZEOF_STRUCT_MEM) + MEM_ALIGNMENT];
+static u8_t ram_heap[MEM_SIZE_ALIGNED + (2*SIZEOF_STRUCT_MEM) + MEM_ALIGNMENT] MEM_SECTION;
 /** pointer to the heap (ram_heap): for alignment, ram is now a pointer instead of an array */
 static u8_t *ram;
 /** the last entry, always unused! */
diff --git a/packages/net/lwip_tcpip/current/src/core/memp.c b/packages/net/lwip_tcpip/current/src/core/memp.c
--- a/packages/net/lwip_tcpip/current/src/core/memp.c
+++ b/packages/net/lwip_tcpip/current/src/core/memp.c
@@ -146,7 +146,7 @@ static const char *memp_desc[MEMP_MAX] =
 static u8_t memp_memory[MEM_ALIGNMENT - 1 
 #define LWIP_MEMPOOL(name,num,size,desc) + ( (num) * (MEMP_SIZE + MEMP_ALIGN_SIZE(size) ) )
 #include "lwip/memp_std.h"
-];
+] MEM_SECTION;
 
 #if MEMP_SANITY_CHECK
 /**
diff --git a/packages/net/lwip_tcpip/current/src/core/snmp/msg_out.c b/packages/net/lwip_tcpip/current/src/core/snmp/msg_out.c
--- a/packages/net/lwip_tcpip/current/src/core/snmp/msg_out.c
+++ b/packages/net/lwip_tcpip/current/src/core/snmp/msg_out.c
@@ -96,7 +96,7 @@ snmp_trap_dst_ip_set(u8_t dst_idx, struc
 {
   if (dst_idx < SNMP_TRAP_DESTINATIONS)
   {
-    trap_dst[dst_idx].dip.addr = htonl(dst->addr);
+    trap_dst[dst_idx].dip.addr = dst->addr;
   }
 }
 
@@ -269,11 +269,8 @@ snmp_send_trap(s8_t generic_trap, struct
         snmp_inc_snmpouttraps();
         snmp_inc_snmpoutpkts();
 
-        /** connect to the TRAP destination */
-        udp_connect(trap_msg.pcb, &trap_msg.dip, SNMP_TRAP_PORT);
-        udp_send(trap_msg.pcb, p);
-        /** disassociate remote address and port with this pcb */
-        udp_disconnect(trap_msg.pcb);
+        /** send to the TRAP destination */
+        udp_sendto(trap_msg.pcb, p, &trap_msg.dip, SNMP_TRAP_PORT);
 
         pbuf_free(p);
       }
diff --git a/packages/net/lwip_tcpip/current/src/core/tcp_out.c b/packages/net/lwip_tcpip/current/src/core/tcp_out.c
--- a/packages/net/lwip_tcpip/current/src/core/tcp_out.c
+++ b/packages/net/lwip_tcpip/current/src/core/tcp_out.c
@@ -462,7 +462,9 @@ err_t
 tcp_send_empty_ack(struct tcp_pcb *pcb)
 {
   struct pbuf *p;
+#if LWIP_TCP_TIMESTAMPS || CHECKSUM_GEN_TCP
   struct tcp_hdr *tcphdr;
+#endif
   u8_t optlen = 0;
 
 #if LWIP_TCP_TIMESTAMPS
@@ -479,8 +481,10 @@ tcp_send_empty_ack(struct tcp_pcb *pcb)
               ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt));
   /* remove ACK flags from the PCB, as we send an empty ACK now */
   pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
-
-  tcphdr = tcp_output_set_header(pcb, p, optlen, htonl(pcb->snd_nxt));
+#if LWIP_TCP_TIMESTAMPS || CHECKSUM_GEN_TCP
+  tcphdr =
+#endif
+  tcp_output_set_header(pcb, p, optlen, htonl(pcb->snd_nxt));
 
   /* NB. MSS option is only sent on SYNs, so ignore it here */
 #if LWIP_TCP_TIMESTAMPS
@@ -932,8 +936,9 @@ void
 tcp_keepalive(struct tcp_pcb *pcb)
 {
   struct pbuf *p;
+#if CHECKSUM_GEN_TCP
   struct tcp_hdr *tcphdr;
-
+#endif
   LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
                           ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
                           ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
@@ -950,8 +955,10 @@ tcp_keepalive(struct tcp_pcb *pcb)
   }
   LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
               (p->len >= sizeof(struct tcp_hdr)));
-
-  tcphdr = tcp_output_set_header(pcb, p, 0, htonl(pcb->snd_nxt - 1));
+#if CHECKSUM_GEN_TCP
+  tcphdr =
+#endif
+  tcp_output_set_header(pcb, p, 0, htonl(pcb->snd_nxt - 1));
 
 #if CHECKSUM_GEN_TCP
   tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip,
diff --git a/packages/net/lwip_tcpip/current/src/ecos/init.c b/packages/net/lwip_tcpip/current/src/ecos/init.c
deleted file mode 100644
--- a/packages/net/lwip_tcpip/current/src/ecos/init.c
+++ /dev/null
@@ -1,325 +0,0 @@
-//==========================================================================
-// ####ECOSGPLCOPYRIGHTBEGIN####                                            
-// -------------------------------------------                              
-// This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2004 Free Software Foundation, Inc.                        
-//
-// eCos is free software; you can redistribute it and/or modify it under    
-// the terms of the GNU General Public License as published by the Free     
-// Software Foundation; either version 2 or (at your option) any later      
-// version.                                                                 
-//
-// eCos is distributed in the hope that it will be useful, but WITHOUT      
-// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
-// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
-// for more details.                                                        
-//
-// You should have received a copy of the GNU General Public License        
-// along with eCos; if not, write to the Free Software Foundation, Inc.,    
-// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
-//
-// As a special exception, if other files instantiate templates or use      
-// macros or inline functions from this file, or you compile this file      
-// and link it with other works to produce a work based on this file,       
-// this file does not by itself cause the resulting work to be covered by   
-// the GNU General Public License. However the source code for this file    
-// must still be made available in accordance with section (3) of the GNU   
-// General Public License v2.                                               
-//
-// This exception does not invalidate any other reasons why a work based    
-// on this file might be covered by the GNU General Public License.         
-// -------------------------------------------                              
-// ####ECOSGPLCOPYRIGHTEND####                                              
-//==========================================================================
-
-/*
- * init.c - misc lwip ecos glue functions 
- */
-#include <pkgconf/system.h>
-#include <pkgconf/net_lwip.h>
-#include "lwip/opt.h"
-#include "lwip/sys.h"
-#include "lwip/memp.h"
-#include "lwip/tcpip.h"
-#include "lwip/ip_addr.h"
-
-#if LWIP_DHCP
-#include "lwip/dhcp.h"
-#endif
-
-#if LWIP_SLIP
-#include "netif/slipif.h"
-#endif
-
-#if PPP_SUPPORT
-#include "netif/ppp/ppp.h"
-#endif
-
-#include "netif/loopif.h"
-#include <cyg/hal/hal_if.h>
-#include <cyg/infra/diag.h>
-
-#ifdef CYGPKG_LWIP_ETH
-#include "netif/etharp.h"
-
-#include <cyg/io/eth/eth_drv.h>
-#include <cyg/io/eth/netdev.h>
-
-
-// Define table boundaries
-CYG_HAL_TABLE_BEGIN(__NETDEVTAB__, netdev);
-CYG_HAL_TABLE_END(__NETDEVTAB_END__, netdev);
-static void ecosglue_init(void);
-#endif
-
-void inline IP_ADDR(struct ip_addr *ipaddr, char a, char b, char c, char d)
-{
-	IP4_ADDR(ipaddr,a,b,c,d);
-}
-
-
-struct netif mynetif, loopif;
-void lwip_set_addr(struct netif *netif);
-#if PPP_SUPPORT
-#define PPP_USER "pppuser"
-#define PPP_PASS "ppppass"
-
-void 
-pppMyCallback(void *a , int e, void * arg)
-{
-	diag_printf("callback %d \n",e);
-}
-
-/* These temporarily here */
-unsigned long
-sys_jiffies(void)
-{
-   return cyg_current_time();
-}
-
-void 
-ppp_trace(int level, const char *format,...)
-{
-    va_list args;
-
-    (void)level;
-    va_start(args, format);
-    diag_vprintf(format, args);
-    va_end(args);
-}	
-#endif
-
-#if LWIP_HAVE_LOOPIF
-struct netif ecos_loopif;
-#endif
-
-#ifdef CYGPKG_LWIP_ETH
-static void
-arp_timer(void *arg)
-{
-  etharp_tmr();
-  sys_timeout(ARP_TMR_INTERVAL, (sys_timeout_handler) arp_timer, NULL);
-}
-#endif
-
-#if LWIP_DHCP
-static void lwip_dhcp_fine_tmr(void *arg)
-{
-    dhcp_fine_tmr();
-    sys_timeout(500, (sys_timeout_handler) lwip_dhcp_fine_tmr, NULL);
-}
-
-static void lwip_dhcp_coarse_tmr(void *arg)
-{
-    dhcp_coarse_tmr();
-    sys_timeout(60000, (sys_timeout_handler) lwip_dhcp_coarse_tmr, NULL);
-}
-#endif
-
-
-//
-// This function is called when tcpip thread finished initialisation.
-// We start several timers here - these timers are all handled in the
-// tcpip thread. That means that also the DHCP stuff is handled in the
-// TCPIP thread. If this causes any trouble than it may be necessaray to
-// use an own DHCP thread insted.
-//
-void tcpip_init_done(void * arg)
-{
-#ifdef CYGPKG_LWIP_ETH
-    sys_timeout(ARP_TMR_INTERVAL, (sys_timeout_handler) arp_timer, NULL);
-#endif
-#ifdef CYGOPT_LWIP_DHCP_MANAGEMENT
-	sys_timeout(500, (sys_timeout_handler) lwip_dhcp_fine_tmr, NULL);
-	sys_timeout(60000, (sys_timeout_handler) lwip_dhcp_coarse_tmr, NULL);
-#endif
-	sys_sem_t *sem = arg;
-	sys_sem_signal(*sem);
-}
-
-
-/*
- * Called by the eCos application at startup
- * wraps various init calls
- */
-int
-lwip_init(void)
-{
-#if LWIP_HAVE_LOOPIF
-	struct ip_addr ipaddr, netmask, gw;
-#endif
-	static int inited = 0;
-	sys_sem_t sem;
-	if (inited)
-		return 1;
-	inited++;
-	
-	sys_init();	/* eCos specific initialization */
-	mem_init();	/* heap based memory allocator */
-	memp_init();	/* pool based memory allocator */
-	pbuf_init();	/* packet buffer allocator */
-	netif_init();	/* netif layer */
-	
-	/* Start the stack.It will spawn a new dedicated thread */
-	sem = sys_sem_new(0);
-	tcpip_init(tcpip_init_done,&sem);
-	sys_sem_wait(sem);
-	sys_sem_free(sem);
-
-#if LWIP_HAVE_LOOPIF
-	IP4_ADDR(&gw, 127,0,0,1);
-	IP4_ADDR(&ipaddr, 127,0,0,1);
-	IP4_ADDR(&netmask, 255,0,0,0);
-  
-	netif_add(&ecos_loopif, &ipaddr, &netmask, &gw, NULL, loopif_init,
-	    tcpip_input);
-#endif
-	
-#if LWIP_SLIP	
-	lwip_set_addr(&mynetif);
-	slipif_init(&mynetif);
-	netif_set_default(&mynetif);
-#elif PPP_SUPPORT
-	pppInit();
-#if PAP_SUPPORT || CHAP_SUPPORT
-	pppSetAuth(PPPAUTHTYPE_PAP, PPP_USER, PPP_PASS);
-#endif
-	pppOpen(sio_open(2), pppMyCallback, NULL);
-#else	
-	ecosglue_init();		
-#endif	
-	return 0;
-}
-
-
-err_t lwip_dummy_netif_init(struct netif *netif)
-{
-    return ERR_OK; 
-}
-
-
-void
-lwip_set_addr(struct netif *netif)
-{
-	struct ip_addr ipaddr, netmask, gw;
-  
-#if LWIP_DHCP
-    IP4_ADDR(&gw, 0,0,0,0);
-    IP4_ADDR(&ipaddr, 0,0,0,0);
-    IP4_ADDR(&netmask, 0,0,0,0);
-
-    netif_add(netif, &ipaddr, &netmask, &gw, netif->state, lwip_dummy_netif_init, tcpip_input);
-    netif_set_default(netif);
-    netif_set_up(netif);        // new step from lwip 1.0.0
-#else
-	IP_ADDR(&gw, CYGDAT_LWIP_SERV_ADDR);
-	IP_ADDR(&ipaddr, CYGDAT_LWIP_MY_ADDR);
-	IP_ADDR(&netmask, CYGDAT_LWIP_NETMASK);
-
-	netif_add(netif, &ipaddr, &netmask, &gw, netif->state, lwip_dummy_netif_init, tcpip_input);
-    netif_set_default(netif); 
-    netif_set_up(netif);        // new step from lwip 1.0.0
-#endif 
-}
-
-void lwip_dhcp_init(struct netif *netif)
-{
-#ifdef CYGOPT_LWIP_DHCP_MANAGEMENT
-    dhcp_start(netif);
-#endif
-}
-
-
-#ifdef CYGPKG_LWIP_ETH
-//io eth stuff
-
-cyg_sem_t delivery;
-
-void
-lwip_dsr_stuff(void)
-{
-  cyg_semaphore_post(&delivery);
-}
-
-//Input thread signalled by DSR calls deliver() on low level drivers
-static void
-input_thread(void *arg)
-{
-  cyg_netdevtab_entry_t *t;
-
-  for (;;) {
-    cyg_semaphore_wait(&delivery);
-
-    for (t = &__NETDEVTAB__[0]; t != &__NETDEVTAB_END__; t++) {
-      struct eth_drv_sc *sc = (struct eth_drv_sc *)t->device_instance;
-      if (sc->state & ETH_DRV_NEEDS_DELIVERY) {
-#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
-        cyg_bool was_ctrlc_int;
-#endif
-	sc->state &= ~ETH_DRV_NEEDS_DELIVERY;
-#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
-        was_ctrlc_int = HAL_CTRLC_CHECK((*sc->funs->int_vector)(sc), (int)sc);
-          if (!was_ctrlc_int) // Fall through and run normal code
-		  
-#endif
-	(sc->funs->deliver) (sc);
-      }
-    }
-  }
-
-}
-
-
-// Initialize all network devices
-static void
-init_hw_drivers(void)
-{
-  cyg_netdevtab_entry_t *t;
-
-  for (t = &__NETDEVTAB__[0]; t != &__NETDEVTAB_END__; t++) {
-    if (t->init(t)) {
-      t->status = CYG_NETDEVTAB_STATUS_AVAIL;
-    } else {
-      // What to do if device init fails?
-      t->status = 0;		// Device not [currently] available
-    }
-  }
-}
-
-extern struct netif *netif_default;
-
-static void
-ecosglue_init(void)
-{
-    etharp_init();
-    cyg_semaphore_init(&delivery, 0);
-    //
-    // start input thread before hardware drivers are initialized because
-    // init_hw_drivers() calls dhcp_init() if DHCP support is configured 
-    // and dhcp_init() requires a running input thread
-    //
-    sys_thread_new(input_thread, (void*)0, CYGNUM_LWIP_ETH_THREAD_PRIORITY);
-    init_hw_drivers();
-}
-
-#endif //CYGPKG_LWIP_ETH
diff --git a/packages/net/lwip_tcpip/current/src/ecos/sequential.c b/packages/net/lwip_tcpip/current/src/ecos/sequential.c
--- a/packages/net/lwip_tcpip/current/src/ecos/sequential.c
+++ b/packages/net/lwip_tcpip/current/src/ecos/sequential.c
@@ -115,8 +115,8 @@ set_ip_addr(struct ip_addr *addr, u8_t a
     IP4_ADDR(addr, a, b, c, d);
 }
 
-#endif // (LWIP_HAVE_LOOPIF && defined(CYGIMP_LWIP_LOOPIF_INSTANCE)) || \
-          (LWIP_HAVE_SLIPIF && defined(CYGIMP_LWIP_SLIPIF_INSTANCE))
+#endif // (LWIP_HAVE_LOOPIF && defined(CYGIMP_LWIP_LOOPIF_INSTANCE)) ||
+       // (LWIP_HAVE_SLIPIF && defined(CYGIMP_LWIP_SLIPIF_INSTANCE))
 
 #ifdef CYGFUN_LWIP_SHOW_NETIF_CONFIG
 
diff --git a/packages/net/lwip_tcpip/current/src/ecos/simple.c b/packages/net/lwip_tcpip/current/src/ecos/simple.c
--- a/packages/net/lwip_tcpip/current/src/ecos/simple.c
+++ b/packages/net/lwip_tcpip/current/src/ecos/simple.c
@@ -187,8 +187,8 @@ simple_input(struct pbuf *p, struct neti
     return ERR_OK;
 }
 
-#endif // (LWIP_HAVE_LOOPIF && defined(CYGIMP_LWIP_LOOPIF_INSTANCE)) || \
-          (LWIP_HAVE_SLIPIF && defined(CYGIMP_LWIP_SLIPIF_INSTANCE))
+#endif // (LWIP_HAVE_LOOPIF && defined(CYGIMP_LWIP_LOOPIF_INSTANCE)) ||
+       // (LWIP_HAVE_SLIPIF && defined(CYGIMP_LWIP_SLIPIF_INSTANCE))
 
 #ifdef CYGFUN_LWIP_SHOW_NETIF_CONFIG
 
diff --git a/packages/net/lwip_tcpip/current/src/netif/ppp/ppp.h b/packages/net/lwip_tcpip/current/src/netif/ppp/ppp.h
deleted file mode 100644
--- a/packages/net/lwip_tcpip/current/src/netif/ppp/ppp.h
+++ /dev/null
@@ -1,446 +0,0 @@
-/*****************************************************************************
-* ppp.h - Network Point to Point Protocol header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher <marc@mbsi.ca>
-*   Ported to lwIP.
-* 97-11-05 Guy Lancaster <glanca@gesn.com>, Global Election Systems Inc.
-*	Original derived from BSD codes.
-*****************************************************************************/
-
-#ifndef PPP_H
-#define PPP_H
-
-#include "lwip/opt.h"
-
-#if PPP_SUPPORT > 0
-#include "lwip/sio.h"
-#include "lwip/api.h"
-#include "lwip/sockets.h"
-#include "lwip/stats.h"
-#include "lwip/mem.h"
-#include "lwip/tcpip.h"
-#include "lwip/netif.h"
-
-/*
- * pppd.h - PPP daemon global declarations.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- */
-/*
- * ppp_defs.h - PPP definitions.
- *
- * Copyright (c) 1994 The Australian National University.
- * All rights reserved.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, provided that the above copyright
- * notice appears in all copies.  This software is provided without any
- * warranty, express or implied. The Australian National University
- * makes no representations about the suitability of this software for
- * any purpose.
- *
- * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
- * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
- * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
- * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
- * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
- * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
- * OR MODIFICATIONS.
- */
-
-#define TIMEOUT(f, a, t)    sys_untimeout((f), (a)), sys_timeout((t)*1000, (f), (a))
-#define UNTIMEOUT(f, a)     sys_untimeout((f), (a))
-
-
-# ifndef __u_char_defined
-
-/* Type definitions for BSD code. */
-typedef unsigned long u_long;
-typedef unsigned int u_int;
-typedef unsigned short u_short;
-typedef unsigned char u_char;
-
-#endif
-
-/*
- * Constants and structures defined by the internet system,
- * Per RFC 790, September 1981, and numerous additions.
- */
-
-/*
- * The basic PPP frame.
- */
-#define PPP_HDRLEN  4       /* octets for standard ppp header */
-#define PPP_FCSLEN  2       /* octets for FCS */
-
-
-/*
- * Significant octet values.
- */
-#define PPP_ALLSTATIONS 0xff    /* All-Stations broadcast address */
-#define PPP_UI          0x03    /* Unnumbered Information */
-#define PPP_FLAG        0x7e    /* Flag Sequence */
-#define PPP_ESCAPE      0x7d    /* Asynchronous Control Escape */
-#define PPP_TRANS       0x20    /* Asynchronous transparency modifier */
-
-/*
- * Protocol field values.
- */
-#define PPP_IP          0x21    /* Internet Protocol */
-#define PPP_AT          0x29    /* AppleTalk Protocol */
-#define PPP_VJC_COMP    0x2d    /* VJ compressed TCP */
-#define PPP_VJC_UNCOMP  0x2f    /* VJ uncompressed TCP */
-#define PPP_COMP        0xfd    /* compressed packet */
-#define PPP_IPCP        0x8021  /* IP Control Protocol */
-#define PPP_ATCP        0x8029  /* AppleTalk Control Protocol */
-#define PPP_CCP         0x80fd  /* Compression Control Protocol */
-#define PPP_LCP         0xc021  /* Link Control Protocol */
-#define PPP_PAP         0xc023  /* Password Authentication Protocol */
-#define PPP_LQR         0xc025  /* Link Quality Report protocol */
-#define PPP_CHAP        0xc223  /* Cryptographic Handshake Auth. Protocol */
-#define PPP_CBCP        0xc029  /* Callback Control Protocol */
-
-/*
- * Values for FCS calculations.
- */
-#define PPP_INITFCS 0xffff  /* Initial FCS value */
-#define PPP_GOODFCS 0xf0b8  /* Good final FCS value */
-#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
-
-/*
- * Extended asyncmap - allows any character to be escaped.
- */
-typedef u_char  ext_accm[32];
-
-/*
- * What to do with network protocol (NP) packets.
- */
-enum NPmode {
-    NPMODE_PASS,        /* pass the packet through */
-    NPMODE_DROP,        /* silently drop the packet */
-    NPMODE_ERROR,       /* return an error */
-    NPMODE_QUEUE        /* save it up for later. */
-};
-
-/*
- * Inline versions of get/put char/short/long.
- * Pointer is advanced; we assume that both arguments
- * are lvalues and will already be in registers.
- * cp MUST be u_char *.
- */
-#define GETCHAR(c, cp) { \
-    (c) = *(cp)++; \
-}
-#define PUTCHAR(c, cp) { \
-    *(cp)++ = (u_char) (c); \
-}
-
-
-#define GETSHORT(s, cp) { \
-    (s) = *(cp)++ << 8; \
-    (s) |= *(cp)++; \
-}
-#define PUTSHORT(s, cp) { \
-    *(cp)++ = (u_char) ((s) >> 8); \
-    *(cp)++ = (u_char) (s); \
-}
-
-#define GETLONG(l, cp) { \
-    (l) = *(cp)++ << 8; \
-    (l) |= *(cp)++; (l) <<= 8; \
-    (l) |= *(cp)++; (l) <<= 8; \
-    (l) |= *(cp)++; \
-}
-#define PUTLONG(l, cp) { \
-    *(cp)++ = (u_char) ((l) >> 24); \
-    *(cp)++ = (u_char) ((l) >> 16); \
-    *(cp)++ = (u_char) ((l) >> 8); \
-    *(cp)++ = (u_char) (l); \
-}
-
-
-#define INCPTR(n, cp)   ((cp) += (n))
-#define DECPTR(n, cp)   ((cp) -= (n))
-
-#define BCMP(s0, s1, l)     memcmp((u_char *)(s0), (u_char *)(s1), (l))
-#define BCOPY(s, d, l)      memcpy((d), (s), (l))
-#define BZERO(s, n)         memset(s, 0, n)
-#if PPP_DEBUG
-#define PRINTMSG(m, l)  { m[l] = '\0'; ppp_trace(LOG_INFO, "Remote message: %s\n", m); }
-#else
-#define PRINTMSG(m, l)
-#endif
-
-/*
- * MAKEHEADER - Add PPP Header fields to a packet.
- */
-#define MAKEHEADER(p, t) { \
-    PUTCHAR(PPP_ALLSTATIONS, p); \
-    PUTCHAR(PPP_UI, p); \
-    PUTSHORT(t, p); }
-
-/*************************
-*** PUBLIC DEFINITIONS ***
-*************************/
-
-/* Error codes. */
-#define PPPERR_NONE 0				/* No error. */
-#define PPPERR_PARAM -1				/* Invalid parameter. */
-#define PPPERR_OPEN -2				/* Unable to open PPP session. */
-#define PPPERR_DEVICE -3			/* Invalid I/O device for PPP. */
-#define PPPERR_ALLOC -4				/* Unable to allocate resources. */
-#define PPPERR_USER -5				/* User interrupt. */
-#define PPPERR_CONNECT -6			/* Connection lost. */
-#define PPPERR_AUTHFAIL -7			/* Failed authentication challenge. */
-#define PPPERR_PROTOCOL -8			/* Failed to meet protocol. */
-
-/*
- * PPP IOCTL commands.
- */
-/*
- * Get the up status - 0 for down, non-zero for up.  The argument must
- * point to an int.
- */
-#define PPPCTLG_UPSTATUS 100	/* Get the up status - 0 down else up */
-#define PPPCTLS_ERRCODE 101		/* Set the error code */
-#define PPPCTLG_ERRCODE 102		/* Get the error code */
-#define	PPPCTLG_FD		103		/* Get the fd associated with the ppp */
-
-/************************
-*** PUBLIC DATA TYPES ***
-************************/
-
-/*
- * The following struct gives the addresses of procedures to call
- * for a particular protocol.
- */
-struct protent {
-    u_short protocol;       /* PPP protocol number */
-    /* Initialization procedure */
-    void (*init) (int unit);
-    /* Process a received packet */
-    void (*input) (int unit, u_char *pkt, int len);
-    /* Process a received protocol-reject */
-    void (*protrej) (int unit);
-    /* Lower layer has come up */
-    void (*lowerup) (int unit);
-    /* Lower layer has gone down */
-    void (*lowerdown) (int unit);
-    /* Open the protocol */
-    void (*open) (int unit);
-    /* Close the protocol */
-    void (*close) (int unit, char *reason);
-#if 0
-    /* Print a packet in readable form */
-    int  (*printpkt) (u_char *pkt, int len,
-              void (*printer) (void *, char *, ...),
-              void *arg);
-    /* Process a received data packet */
-    void (*datainput) (int unit, u_char *pkt, int len);
-#endif
-    int  enabled_flag;      /* 0 iff protocol is disabled */
-    char *name;         /* Text name of protocol */
-#if 0
-    /* Check requested options, assign defaults */
-    void (*check_options) (u_long);
-    /* Configure interface for demand-dial */
-    int  (*demand_conf) (int unit);
-    /* Say whether to bring up link for this pkt */
-    int  (*active_pkt) (u_char *pkt, int len);
-#endif
-};
-
-/*
- * The following structure records the time in seconds since
- * the last NP packet was sent or received.
- */
-struct ppp_idle {
-    u_short xmit_idle;      /* seconds since last NP packet sent */
-    u_short recv_idle;      /* seconds since last NP packet received */
-};
-
-struct ppp_settings {
-
-	u_int  disable_defaultip : 1;   /* Don't use hostname for default IP addrs */
-	u_int  auth_required : 1;      /* Peer is required to authenticate */
-	u_int  explicit_remote : 1;    /* remote_name specified with remotename opt */
-	u_int  refuse_pap : 1;         /* Don't wanna auth. ourselves with PAP */
-	u_int  refuse_chap : 1;        /* Don't wanna auth. ourselves with CHAP */
-	u_int  usehostname : 1;        /* Use hostname for our_name */
-	u_int  usepeerdns : 1;         /* Ask peer for DNS adds */
-
-	u_short idle_time_limit; /* Shut down link if idle for this long */
-	int  maxconnect;         /* Maximum connect time (seconds) */
-
-	char user[MAXNAMELEN + 1];/* Username for PAP */
-	char passwd[MAXSECRETLEN + 1];           /* Password for PAP, secret for CHAP */
-	char our_name[MAXNAMELEN + 1];         /* Our name for authentication purposes */
-	char remote_name[MAXNAMELEN + 1];      /* Peer's name for authentication */
-};
-
-struct ppp_addrs {
-    struct ip_addr our_ipaddr, his_ipaddr, netmask, dns1, dns2;
-};
-
-/*****************************
-*** PUBLIC DATA STRUCTURES ***
-*****************************/
-/* Buffers for outgoing packets. */
-extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];
-
-extern struct ppp_settings ppp_settings;
-
-extern struct protent *ppp_protocols[];/* Table of pointers to supported protocols */
-
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-
-/* Initialize the PPP subsystem. */
-void pppInit(void);
-
-/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
- * RFC 1994 says:
- *
- * In practice, within or associated with each PPP server, there is a
- * database which associates "user" names with authentication
- * information ("secrets").  It is not anticipated that a particular
- * named user would be authenticated by multiple methods.  This would
- * make the user vulnerable to attacks which negotiate the least secure
- * method from among a set (such as PAP rather than CHAP).  If the same
- * secret was used, PAP would reveal the secret to be used later with
- * CHAP.
- *
- * Instead, for each user name there should be an indication of exactly
- * one method used to authenticate that user name.  If a user needs to
- * make use of different authentication methods under different
- * circumstances, then distinct user names SHOULD be employed, each of
- * which identifies exactly one authentication method.
- *
- */
-enum pppAuthType {
-    PPPAUTHTYPE_NONE,
-    PPPAUTHTYPE_ANY,
-    PPPAUTHTYPE_PAP,
-    PPPAUTHTYPE_CHAP
-};
-
-void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd);
-
-/*
- * Open a new PPP connection using the given I/O device.
- * This initializes the PPP control block but does not
- * attempt to negotiate the LCP session.
- * Return a new PPP connection descriptor on success or
- * an error code (negative) on failure. 
- */
-int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx);
-
-/*
- * Close a PPP connection and release the descriptor. 
- * Any outstanding packets in the queues are dropped.
- * Return 0 on success, an error code on failure. 
- */
-int pppClose(int pd);
-
-/*
- * Indicate to the PPP process that the line has disconnected.
- */
-void pppSigHUP(int pd);
-
-/*
- * Get and set parameters for the given connection.
- * Return 0 on success, an error code on failure. 
- */
-int  pppIOCtl(int pd, int cmd, void *arg);
-
-/*
- * Return the Maximum Transmission Unit for the given PPP connection.
- */
-u_int pppMTU(int pd);
-
-/*
- * Write n characters to a ppp link.
- *	RETURN: >= 0 Number of characters written
- *		 	 -1 Failed to write to device
- */
-int pppWrite(int pd, const u_char *s, int n);
-
-void pppMainWakeup(int pd);
-
-/* Configure i/f transmit parameters */
-void ppp_send_config (int, int, u32_t, int, int);
-/* Set extended transmit ACCM */
-void ppp_set_xaccm (int, ext_accm *);
-/* Configure i/f receive parameters */
-void ppp_recv_config (int, int, u32_t, int, int);
-/* Find out how long link has been idle */
-int  get_idle_time (int, struct ppp_idle *);
-
-/* Configure VJ TCP header compression */
-int  sifvjcomp (int, int, int, int);
-/* Configure i/f down (for IP) */
-int  sifup (int);		
-/* Set mode for handling packets for proto */
-int  sifnpmode (int u, int proto, enum NPmode mode);
-/* Configure i/f down (for IP) */
-int  sifdown (int);	
-/* Configure IP addresses for i/f */
-int  sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t);
-/* Reset i/f IP addresses */
-int  cifaddr (int, u32_t, u32_t);
-/* Create default route through i/f */
-int  sifdefaultroute (int, u32_t, u32_t);
-/* Delete default route through i/f */
-int  cifdefaultroute (int, u32_t, u32_t);
-
-/* Get appropriate netmask for address */
-u32_t GetMask (u32_t); 
-
-#endif /* PPP_SUPPORT */
-
-#endif /* PPP_H */
diff --git a/packages/net/lwip_tcpip/current/tests/httpd.c b/packages/net/lwip_tcpip/current/tests/httpd.c
deleted file mode 100644
--- a/packages/net/lwip_tcpip/current/tests/httpd.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * Copyright (c) 2001, Swedish Institute of Computer Science.
- * All rights reserved. 
- *
- * Redistribution and use in source and binary forms, with or without 
- * modification, are permitted provided that the following conditions 
- * are met: 
- * 1. Redistributions of source code must retain the above copyright 
- *    notice, this list of conditions and the following disclaimer. 
- * 2. Redistributions in binary form must reproduce the above copyright 
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the distribution. 
- * 3. Neither the name of the Institute nor the names of its contributors 
- *    may be used to endorse or promote products derived from this software 
- *    without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-#include "lwip/debug.h"
-#include "lwip/stats.h"
-#include "lwip/tcp.h"
-#include <cyg/infra/testcase.h>
-
-#ifdef CYGPKG_LWIP_TCP
-
-struct http_state {
-  const char *file;
-  u32_t left;
-  u8_t retries;
-};
-
-/* Stack smashing arch-independent shellcode: will brick your target :-) */
-static const char sdata[] __attribute__ ((aligned)) = {
-	0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 
-	0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x43, 0x6f, 0x6e, 
-	0x74, 0x65, 0x6e, 0x74, 0x2d, 0x54, 0x79, 0x70, 0x65, 0x3a, 
-	0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 
-	0xd, 0xa, 0xd, 0xa, 0x49, 0x74, 0x20, 0x77, 0x6f, 0x72, 
-	0x6b, 0x65, 0x64, 0x2e, 0xa, };
-
-
-
-
-/*-----------------------------------------------------------------------------------*/
-static void
-conn_err(void *arg, err_t err)
-{
-  struct http_state *hs;
-
-  hs = arg;
-  mem_free(hs);
-}
-/*-----------------------------------------------------------------------------------*/
-static void
-close_conn(struct tcp_pcb *pcb, struct http_state *hs)
-{
-  tcp_arg(pcb, NULL);
-  tcp_sent(pcb, NULL);
-  tcp_recv(pcb, NULL);
-  mem_free(hs);
-  tcp_close(pcb);
-}
-/*-----------------------------------------------------------------------------------*/
-static void
-send_data(struct tcp_pcb *pcb, struct http_state *hs)
-{
-  err_t err;
-  u16_t len;
-
-  /* We cannot send more data than space available in the send
-     buffer. */     
-  if(tcp_sndbuf(pcb) < hs->left) {
-    len = tcp_sndbuf(pcb);
-  } else {
-    len = hs->left;
-  }
-
-  do {
-    err = tcp_write(pcb, hs->file, len, 0);
-    if(err == ERR_MEM) {
-      len /= 2;
-    }
-  } while(err == ERR_MEM && len > 1);  
-  
-  if(err == ERR_OK) {
-    hs->file += len;
-    hs->left -= len;
-  }
-}
-/*-----------------------------------------------------------------------------------*/
-static err_t
-http_poll(void *arg, struct tcp_pcb *pcb)
-{
-  struct http_state *hs;
-
-  hs = arg;
-  
-  /*  printf("Polll\n");*/
-  if(hs == NULL) {
-    /*    printf("Null, close\n");*/
-    tcp_abort(pcb);
-    return ERR_ABRT;
-  } else {
-    ++hs->retries;
-    if(hs->retries == 4) {
-      tcp_abort(pcb);
-      return ERR_ABRT;
-    }
-    send_data(pcb, hs);
-  }
-
-  return ERR_OK;
-}
-/*-----------------------------------------------------------------------------------*/
-static err_t
-http_sent(void *arg, struct tcp_pcb *pcb, u16_t len)
-{
-  struct http_state *hs;
-
-  hs = arg;
-
-  hs->retries = 0;
-  
-  if(hs->left > 0) {    
-    send_data(pcb, hs);
-  } else {
-    close_conn(pcb, hs);
-  }
-
-  return ERR_OK;
-}
-/*-----------------------------------------------------------------------------------*/
-static err_t
-http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
-{
-  int i;
-  char *data;
-  struct http_state *hs;
-
-  hs = arg;
-
-  if(err == ERR_OK && p != NULL) {
-
-    /* Inform TCP that we have taken the data. */
-    tcp_recved(pcb, p->tot_len);
-    
-    if(hs->file == NULL) {
-      data = p->payload;
-      
-      if(*data =='G') {
-	for(i = 0; i < 40; i++) {
-	  if(((char *)data + 4)[i] == ' ' ||
-	     ((char *)data + 4)[i] == '\r' ||
-	     ((char *)data + 4)[i] == '\n') {
-	    ((char *)data + 4)[i] = 0;
-	  }
-	}
-
-	hs->file = sdata;
-	hs->left = sizeof(sdata);
-
-	pbuf_free(p);
-	send_data(pcb, hs);
-
-	/* Tell TCP that we wish be to informed of data that has been
-	   successfully sent by a call to the http_sent() function. */
-	tcp_sent(pcb, http_sent);
-      } else {
-	pbuf_free(p);
-	close_conn(pcb, hs);
-      }
-    } else {
-      pbuf_free(p);
-    }
-  }
-
-  if(err == ERR_OK && p == NULL) {
-    close_conn(pcb, hs);
-  }
-  return ERR_OK;
-}
-/*-----------------------------------------------------------------------------------*/
-static err_t
-http_accept(void *arg, struct tcp_pcb *pcb, err_t err)
-{
-  struct http_state *hs;
-
-  tcp_setprio(pcb, TCP_PRIO_MIN);
-  
-  /* Allocate memory for the structure that holds the state of the
-     connection. */
-  hs = mem_malloc(sizeof(struct http_state));
-
-  if(hs == NULL) {
-    return ERR_MEM;
-  }
-  
-  /* Initialize the structure. */
-  hs->file = NULL;
-  hs->left = 0;
-  hs->retries = 0;
-  
-  /* Tell TCP that this is the structure we wish to be passed for our
-     callbacks. */
-  tcp_arg(pcb, hs);
-
-  /* Tell TCP that we wish to be informed of incoming data by a call
-     to the http_recv() function. */
-  tcp_recv(pcb, http_recv);
-
-  tcp_err(pcb, conn_err);
-  
-  tcp_poll(pcb, http_poll, 4);
-  return ERR_OK;
-}
-
-/*-----------------------------------------------------------------------------------*/
-void
-httpd_init(void *arg)
-{
-  struct tcp_pcb *pcb;
-
-  pcb = tcp_new();
-  tcp_bind(pcb, IP_ADDR_ANY, 80);
-  pcb = tcp_listen(pcb);
-  tcp_accept(pcb, http_accept);
-  while(1)
-	  cyg_thread_delay(1000);
-}
-
-void
-tmain(cyg_addrword_t p)
-{
-  lwip_init();	
-  sys_thread_new(httpd_init, (void*)"httpd",7);  
-}
-
-#define STACK_SIZE 0x1000
-static char stack[STACK_SIZE];
-static cyg_thread thread_data;
-static cyg_handle_t thread_handle;
-
-void
-httpd_main(void)
-{
-    CYG_TEST_INIT();
-    // Create a main thread, so we can run the scheduler and have time 'pass'
-    cyg_thread_create(10,                // Priority - just a number
-                      tmain,          // entry
-                      0,                 // entry parameter
-                      "thread",        // Name
-                      &stack[0],         // Stack
-                      STACK_SIZE,        // Size
-                      &thread_handle,    // Handle
-                      &thread_data       // Thread data structure
-            );
-    cyg_thread_resume(thread_handle);  // Start it
-    cyg_scheduler_start();
-    CYG_TEST_FAIL_FINISH("Not reached");
-}
-
-externC void
-cyg_start( void )
-{
-    httpd_main();
-}
-
-#else // def CYGPKG_LWIP_TCP
-#define N_A_MSG "TCP support disabled"
-#endif // def CYGFUN_KERNEL_API_C
-
-#ifdef N_A_MSG
-externC void
-cyg_start( void )
-{
-    CYG_TEST_INIT();
-    CYG_TEST_NA(N_A_MSG);
-}
-#endif // N_A_MSG
-
diff --git a/packages/net/lwip_tcpip/current/tests/nc_test_slave.c b/packages/net/lwip_tcpip/current/tests/nc_test_slave.c
--- a/packages/net/lwip_tcpip/current/tests/nc_test_slave.c
+++ b/packages/net/lwip_tcpip/current/tests/nc_test_slave.c
@@ -57,7 +57,8 @@
 #include "nc_test_framework.h"
 
 
-#define STACK_SIZE               (CYGNUM_HAL_STACK_SIZE_TYPICAL + 0x1000)
+#define STACK_SIZE               (CYGNUM_HAL_STACK_SIZE_MINIMUM + \
+                                  4*CYGNUM_HAL_STACK_FRAME_SIZE)
 #define MAX_LOAD_THREAD_LEVEL    20
 #define MIN_LOAD_THREAD_LEVEL    0
 #define NUM_LOAD_THREADS         10
@@ -90,7 +91,7 @@ static void do_some_random_computation(i
 extern void show_net_times(void);
 #endif
 
-#define MAX_BUF 8192
+#define MAX_BUF (sizeof(struct nc_test_data)+10240)
 static unsigned char in_buf[MAX_BUF], out_buf[MAX_BUF];
 
 extern void
@@ -186,13 +187,13 @@ do_udp_test(int s1, struct nc_request *r
                 if ((ntohl(tdp->key1) == NC_TEST_DATA_KEY1) &&
                     (ntohl(tdp->key2) == NC_TEST_DATA_KEY2)) {
                     if (ntohl(tdp->seq) != seq) {
-                        test_printf("Packets out of sequence - recvd: %lu, expected: %d\n",
+                        test_printf("Packets out of sequence - recvd: %u, expected: %d\n",
                                     ntohl(tdp->seq), seq);
                         seq = ntohl(tdp->seq);
                         seq_errors++;
                     }
                 } else {
-                    test_printf("Bad data packet - key: %lx/%lx, seq: %lu\n",
+                    test_printf("Bad data packet - key: %x/%x, seq: %u\n",
                                 ntohl(tdp->key1), ntohl(tdp->key2),
                                 ntohl(tdp->seq));
                 }
@@ -362,13 +363,13 @@ do_tcp_test(int s1, struct nc_request *r
                 if ((ntohl(tdp->key1) == NC_TEST_DATA_KEY1) &&
                     (ntohl(tdp->key2) == NC_TEST_DATA_KEY2)) {
                     if (ntohl(tdp->seq) != seq) {
-                        test_printf("Packets out of sequence - recvd: %lu, expected: %d\n",
+                        test_printf("Packets out of sequence - recvd: %u, expected: %d\n",
                                     ntohl(tdp->seq), seq);
                         seq = ntohl(tdp->seq);
                         seq_errors++;
                     }
                 } else {
-                    test_printf("Bad data packet - key: %lx/%lx, seq: %lu\n",
+                    test_printf("Bad data packet - key: %x/%x, seq: %u\n",
                                 ntohl(tdp->key1), ntohl(tdp->key2),
                                 ntohl(tdp->seq));
                 }
@@ -446,7 +447,7 @@ nc_slave(test_param_t param)
         if (recvfrom(s, &req, sizeof(req), 0, (struct sockaddr *)&master, &masterlen) < 0) {
             pexit("recvfrom");
         }
-        test_printf("Request %lu from %s:%d\n", ntohl(req.type), 
+        test_printf("Request %u from %s:%d\n", ntohl(req.type), 
                     inet_ntoa(master.sin_addr), ntohs(master.sin_port));
         reply.response = htonl(NC_REPLY_ACK);
         reply.seq = req.seq;
@@ -455,22 +456,22 @@ nc_slave(test_param_t param)
             done = true;
             break;
         case NC_REQUEST_UDP_SEND:
-            test_printf("UDP send - %lu buffers, %lu bytes\n", ntohl(req.nbufs), ntohl(req.buflen));
+            test_printf("UDP send - %u buffers, %u bytes\n", ntohl(req.nbufs), ntohl(req.buflen));
             break;
         case NC_REQUEST_UDP_RECV:
-            test_printf("UDP recv - %lu buffers, %lu bytes\n", ntohl(req.nbufs), ntohl(req.buflen));
+            test_printf("UDP recv - %u buffers, %u bytes\n", ntohl(req.nbufs), ntohl(req.buflen));
             break;
         case NC_REQUEST_UDP_ECHO:
-            test_printf("UDP echo - %lu buffers, %lu bytes\n", ntohl(req.nbufs), ntohl(req.buflen));
+            test_printf("UDP echo - %u buffers, %u bytes\n", ntohl(req.nbufs), ntohl(req.buflen));
             break;
         case NC_REQUEST_TCP_SEND:
-            test_printf("TCP send - %lu buffers, %lu bytes\n", ntohl(req.nbufs), ntohl(req.buflen));
+            test_printf("TCP send - %u buffers, %u bytes\n", ntohl(req.nbufs), ntohl(req.buflen));
             break;
         case NC_REQUEST_TCP_RECV:
-            test_printf("TCP recv - %lu buffers, %lu bytes\n", ntohl(req.nbufs), ntohl(req.buflen));
+            test_printf("TCP recv - %u buffers, %u bytes\n", ntohl(req.nbufs), ntohl(req.buflen));
             break;
         case NC_REQUEST_TCP_ECHO:
-            test_printf("TCP echo - %lu buffers, %lu bytes\n", ntohl(req.nbufs), ntohl(req.buflen));
+            test_printf("TCP echo - %u buffers, %u bytes\n", ntohl(req.nbufs), ntohl(req.buflen));
             break;
         case NC_REQUEST_SET_LOAD:
             start_load(ntohl(req.nbufs));
@@ -490,7 +491,7 @@ nc_slave(test_param_t param)
             reply.misc.idle_results.count[1] = htonl((long)idle_thread_count);
             break;
         default:
-            test_printf("Unrecognized request: %lu\n", ntohl(req.type));
+            test_printf("Unrecognized request: %u\n", ntohl(req.type));
             reply.response = htonl(NC_REPLY_NAK);
             reply.reason = htonl(NC_REPLY_NAK_UNKNOWN_REQUEST);
             break;
@@ -678,7 +679,7 @@ static void
 do_some_random_computation(int p)
 {
     // Just something that might be "hard"
-    volatile double x;
+    volatile double x CYGBLD_ATTRIB_UNUSED;
     x = ((p * 10) * 3.14159) / 180.0;  // radians
 }
 
diff --git a/packages/net/ns/dns/current/ChangeLog b/packages/net/ns/dns/current/ChangeLog
--- a/packages/net/ns/dns/current/ChangeLog
+++ b/packages/net/ns/dns/current/ChangeLog
@@ -1,3 +1,8 @@
+2010-09-29  Kelvin Lawson  <kelvinl@users.sf.net>
+
+	* src/dns.c: Remove spurious mutex unlock in cyg_res_getaddrinfo()
+	when name lookup string is too long.
+
 2008-08-12  Jonathan Larmour  <jifl@eCosCentric.com>
 
 	* src/dns.c: id global should be unsigned, in line with DNS header.
diff --git a/packages/net/ns/dns/current/src/dns.c b/packages/net/ns/dns/current/src/dns.c
--- a/packages/net/ns/dns/current/src/dns.c
+++ b/packages/net/ns/dns/current/src/dns.c
@@ -593,7 +593,6 @@ cyg_dns_getaddrinfo(const char * hostnam
     
     if (domainname) {
         if ((strlen(hostname) + strlen(domainname)) > 254) {
-            cyg_drv_mutex_unlock(&dns_mutex);
             CYG_REPORT_RETVAL( -EAI_FAIL );
             return -EAI_FAIL;
         }
diff --git a/packages/net/tcpip/current/ChangeLog b/packages/net/tcpip/current/ChangeLog
--- a/packages/net/tcpip/current/ChangeLog
+++ b/packages/net/tcpip/current/ChangeLog
@@ -1,3 +1,7 @@
+2010-09-18  John Dallaway  <john@dallaway.org.uk>
+
+	* doc/openbsd.sgml: No longer "recent".
+
 2009-09-10  John Dallaway  <john@dallaway.org.uk>
 
 	* src/sys/netinet/tcp_input.c, src/sys/netinet/tcp_timer.c: Remove
@@ -1735,7 +1739,7 @@ 2000-02-08  John Dallaway  <jld@cygnus.c
 # ####GPLCOPYRIGHTBEGIN####                                       
 # -------------------------------------------                     
 # This file is part of eCos, the Embedded Configurable Operating System.
-# Copyright (C) 2000, 2001, 2002, 2009 Free Software Foundation, Inc.   
+# Copyright (C) 2000, 2001, 2002, 2009, 2010 Free Software Foundation, Inc.   
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
diff --git a/packages/net/tcpip/current/doc/openbsd.sgml b/packages/net/tcpip/current/doc/openbsd.sgml
--- a/packages/net/tcpip/current/doc/openbsd.sgml
+++ b/packages/net/tcpip/current/doc/openbsd.sgml
@@ -9,7 +9,7 @@
 <!-- =============================================================== -->
 <!-- ####ECOSDOCCOPYRIGHTBEGIN####                                       -->
 <!-- ===============================================================     -->
-<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. -->
+<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2010 Free Software Foundation, Inc. -->
 <!-- This material may be distributed only subject to the terms          -->
 <!-- and conditions set forth in the Open Publication License, v1.0      -->
 <!-- or later (the latest version is presently available at              -->
@@ -32,7 +32,7 @@
 <PARTINTRO>
 <PARA>	  <productname>TCP/IP Networking for eCos</productname>
           now provides a complete
-	  TCP/IP networking stack, which is derived from a recent
+	  TCP/IP networking stack, which is derived from a
 	  stable release of OpenBSD. The networking support is
 	  fully featured and well tested within the eCos environment.
 	</PARA>
diff --git a/packages/redboot/current/ChangeLog b/packages/redboot/current/ChangeLog
--- a/packages/redboot/current/ChangeLog
+++ b/packages/redboot/current/ChangeLog
@@ -1,3 +1,25 @@
+2012-03-06  Grant Edwards  <grant.b.edwards@gmail.com>
+
+	* src/net/net_io.c:
+	* cdl/redboot.cdl: Added new CDL option
+	CYGPKG_REDBOOT_NETWORKING_BOOTP to control whether BOOTP/DHCP
+	support is built into Redboot.  Moved "DEFAULT_NO_BOOTP" option
+	into the new package.
+	[ Bugzilla 1001177 ]
+
+	* src/net/bootp.c:
+	* cdl/redboot.cdl: Re-wrote BOOTP/DHCP client code to fix retry
+	mechanism and to fix race conditions that were corrupting the
+	received IP configuration data.  Added verbose BOOTP/DHCP output
+	CDL option.
+	[ Bugzilla 1001177 ]
+
+
+2011-12-02  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/redboot.cdl: Fix typographical error. Issue reported by
+	Keith Smith. [ Bugzilla 1001403 ]
+
 2010-04-23  John Dallaway  <john@dallaway.org.uk>
 
 	* src/net/dns.c: Initialise DNS domain with an empty string to
diff --git a/packages/redboot/current/cdl/redboot.cdl b/packages/redboot/current/cdl/redboot.cdl
--- a/packages/redboot/current/cdl/redboot.cdl
+++ b/packages/redboot/current/cdl/redboot.cdl
@@ -251,6 +251,7 @@ cdl_package CYGPKG_REDBOOT {
             display       "Include POSIX checksum command"
             doc           ref/cksum-command.html
             default_value 1
+            requires      CYGPKG_CRC
             compile -library=libextras.a cksum.c
         }
 
@@ -339,7 +340,7 @@ cdl_package CYGPKG_REDBOOT {
             active_if     CYGPKG_IO_ETH_DRIVERS
             default_value 1
             implements    CYGINT_REDBOOT_LOAD_METHOD
-            compile net/bootp.c net/udp.c net/ip.c net/pktbuf.c net/cksum.c
+            compile net/udp.c net/ip.c net/pktbuf.c net/cksum.c
             compile net/enet.c net/icmp.c net/tcp.c net/timers.c net/arp.c
             compile net/inet_addr.c
             compile -library=libextras.a net/ping.c net/net_io.c 
@@ -389,17 +390,6 @@ cdl_package CYGPKG_REDBOOT {
                     an IP address is configured into the Flash
                     configuration, that will be used in preference."
     
-                cdl_option CYGSEM_REDBOOT_DEFAULT_NO_BOOTP {
-                     display          "Do not try to use BOOTP"
-                     flavor           bool
-                     default_value    0
-                     description      "
-                         By default Redboot tries to use BOOTP to get an IP
-                         address. If there's no BOOTP server on your network
-                         use this option to avoid to wait until the
-                         timeout. This option is overriden by the
-                         configuration stored in flash."
-                }
                 cdl_option CYGDAT_REDBOOT_DEFAULT_BOOTP_SERVER_IP_ADDR {
                      display           "Default bootp server"
                      flavor            booldata
@@ -415,21 +405,54 @@ cdl_package CYGPKG_REDBOOT {
                           preference."
                 }
             }
-    
-            cdl_component CYGSEM_REDBOOT_NETWORKING_DHCP {
-                display          "Use DHCP to get IP information"
+
+            cdl_component CYGPKG_REDBOOT_NETWORKING_BOOTP {
+                display          "Enable BOOTP/DHCP support"
                 flavor           bool
                 default_value    1
+                compile          net/bootp.c
                 description      "
-                    Use DHCP protocol to obtain pertinent IP addresses, such 
-                    as the client, server, gateway, etc."
+                    Use BOOTP/DHCP protocol to obtain pertinent IP
+                    addresses, such as the client, server, gateway,
+                    etc."
+                
+                cdl_component CYGSEM_REDBOOT_NETWORKING_DHCP {
+                    display          "Enable DHCP in addition to BOOTP support"
+                    flavor           bool
+                    default_value    1
+                    description      "
+                    Enables DHCP protocol in addition to BOOTP.  If not enabled,
+                    only BOOTP will be suported."
+                }
+
+                cdl_component CYGSEM_REDBOOT_NETWORKING_BOOTP_VERBOSE {
+                    display          "Enable verbose output from BOOTP/DHCP code"
+                    flavor           bool
+                    default_value    0
+                    description      "
+                    Enable more verbose output from BOOTP/DHCP that logs rx/tx
+                    packet types and state-machine transitions."
+                }
+
+                cdl_option CYGSEM_REDBOOT_DEFAULT_NO_BOOTP {
+                    display          "Do not try to use BOOTP/DHCP"
+                    flavor           bool
+                    default_value    0
+                    description      "
+                         By default Redboot tries to use BOOTP/DHCP to
+                         get an IP address when BOOTP/DHCP support is
+                         present in Redboot. If there's no BOOTP/DHCP
+                         server on your network use this option to
+                         avoid waiting for the BOOTP/DHCP timeouts and
+                         retries. This option is overriden by the
+                         configuration stored in flash."
+                }
             }
-    
+
             cdl_component CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY {
                 display          "Use a gateway for non-local IP traffic"
                 flavor           bool
                 default_value    1
-                requires         CYGSEM_REDBOOT_NETWORKING_DHCP
                 description      "
                   Enabling this option will allow the RedBoot networking
                 stack to use a \[single\] gateway to reach a non-local
@@ -932,6 +955,7 @@ cdl_package CYGPKG_REDBOOT {
                 display       "Use CRC checksums on FIS images."
                 flavor        bool
                 default_value 1
+                requires      CYGPKG_CRC
                 description "
                   When this option is enabled, RedBoot will use CRC checksums
                   when reading and writing flash images."
diff --git a/packages/redboot/current/include/redboot.h b/packages/redboot/current/include/redboot.h
--- a/packages/redboot/current/include/redboot.h
+++ b/packages/redboot/current/include/redboot.h
@@ -67,8 +67,10 @@
 #include <net/net.h>
 #include <net/bootp.h>
 // Determine an IP address for this node, using BOOTP
+#ifdef CYGPKG_REDBOOT_NETWORKING_BOOTP
 extern int __bootp_find_local_ip(bootp_header_t *info);
 #endif
+#endif
 
 #ifdef DEFINE_VARS
 #define EXTERN
diff --git a/packages/redboot/current/src/net/bootp.c b/packages/redboot/current/src/net/bootp.c
--- a/packages/redboot/current/src/net/bootp.c
+++ b/packages/redboot/current/src/net/bootp.c
@@ -40,11 +40,13 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):    gthomas
+//               grant edwards
 // Contributors: gthomas
-// Date:         2000-07-14
-// Purpose:      
-// Description:  
-//              
+//               grant edwards
+// Date:         2011-03-18
+// Purpose:
+// Description:
+//
 // This code is part of RedBoot (tm).
 //
 //####DESCRIPTIONEND####
@@ -55,299 +57,341 @@
 #include <net/net.h>
 #include <net/bootp.h>
 
-#define SHOULD_BE_RANDOM  0x12345555
+#define RETRY_TIME_MS  2000
+#define MAX_RETRIES    4
 
-/* How many milliseconds to wait before retrying the request */
-#define RETRY_TIME  2000
-#define MAX_RETRIES    8
-
+static unsigned xid;                   // transaction ID,  should be random/unique
+static const ip_route_t broadcast = { {255, 255, 255, 255},
+                                      {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
 static bootp_header_t *bp_info;
-  
+
 #ifdef CYGSEM_REDBOOT_NETWORKING_DHCP
-static const unsigned char dhcpCookie[] = {99,130,83,99};
-static const unsigned char dhcpEnd[] = {255};
-static const unsigned char dhcpDiscover[] = {53,1,1};
-static const unsigned char dhcpRequest[] = {53,1,3};
-static const unsigned char dhcpRequestIP[] = {50,4};
-static const unsigned char dhcpParamRequestList[] = {55,3,1,3,6};
+static const unsigned char dhcpCookie[] =           { 99, 130, 83, 99 };
+static const unsigned char dhcpDiscover[] =         { 53, 1, 1 };
+static const unsigned char dhcpRequest[] =          { 53, 1, 3 };
+static const unsigned char dhcpRequestIP[] =        { 50, 4 };
+static const unsigned char dhcpParamRequestList[] = { 55, 3, 1, 3, 6 };
+static const unsigned char dhcpEnd[] =              { 255 };
+#endif
+
+// FSM states -- only NONE and DONE are used in BOOTP mode
 static enum {
     DHCP_NONE = 0,
-    DHCP_DISCOVER,
-    DHCP_OFFER,
-    DHCP_REQUEST,
-    DHCP_ACK
+    DHCP_WAITING_FOR_OFFER,
+    DHCP_WAITING_FOR_ACK,
+    DHCP_DONE,
+    DHCP_FAILED
 } dhcpState;
+
+#if !defined(CYGSEM_REDBOOT_NETWORKING_BOOTP_VERBOSE)
+# define debug_printf(format, ...)     /* noop */
+#else
+# define debug_printf(format, ...)  diag_printf(format, ##__VA_ARGS__)
+static const char *dhcpStateString[] =  { "NONE", "WAITING_FOR_OFFER", "WAITING_FOR_ACK", "DONE", "FAILED" };
+# ifdef CYGSEM_REDBOOT_NETWORKING_DHCP
+static const char *dhcpTypeString[] =  { "0x00", "DISCOVER", "OFFER", "REQUEST", "0x04", "ACK", "NAK", "0x07" };
+# endif
+#endif
+
+// parse network configuration from a DHCP ACK packet or BOOTP REPLY
+static void
+parseConfig(bootp_header_t *bp, int len)
+{
+#ifdef CYGSEM_REDBOOT_NETWORKING_DHCP
+    unsigned char  *end,
+                   *p;
+    int             optlen;
+#endif
+    memcpy(__local_ip_addr, &bp->bp_yiaddr, sizeof __local_ip_addr);
+#ifdef CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY
+    memcpy(__local_ip_gate, &bp->bp_giaddr, sizeof __local_ip_gate);
 #endif
 
+#ifdef CYGSEM_REDBOOT_NETWORKING_DHCP
+
+    // are there option fields to parse?
+    if (memcmp(bp->bp_vend, dhcpCookie, sizeof dhcpCookie))
+        return;
+
+    p = bp->bp_vend + 4;
+    end = (unsigned char *)bp + len;
+    while (p < end) {
+        unsigned char tag = *p;
+        if (tag == TAG_END)
+            break;
+        if (tag == TAG_PAD)
+            optlen = 1;
+        else {
+            optlen = p[1];
+            p += 2;
+            switch (tag) {
+# ifdef CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY
+            case TAG_SUBNET_MASK:
+                memcpy(__local_ip_mask, p, sizeof __local_ip_mask);
+                break;
+            case TAG_GATEWAY:
+                memcpy(__local_ip_gate, p, sizeof __local_ip_gate);
+                break;
+# endif
+# ifdef CYGPKG_REDBOOT_NETWORKING_DNS
+            case TAG_DOMAIN_SERVER:
+                memcpy(&__bootp_dns_addr, p, sizeof __bootp_dns_addr);
+                __bootp_dns_set = 1;
+                break;
+# endif
+            default:
+                break;
+            }
+        }
+        p += optlen;
+    }
+#endif
+}
+
+// functions used to prepare BOOTP/DHCP tx packets
+
+// basic BOOTP request
 static void
-bootp_handler(udp_socket_t *skt, char *buf, int len,
-	      ip_route_t *src_route, word src_port)
+prep_bootp_request(bootp_header_t *b)
+{
+    memset(b, 0, sizeof *b);
+    b->bp_op = BOOTREQUEST;
+    b->bp_htype = HTYPE_ETHERNET;
+    b->bp_hlen = sizeof __local_enet_addr;
+    b->bp_xid = xid;
+    memcpy(b->bp_chaddr, __local_enet_addr, sizeof b->bp_chaddr);
+}
+
+#ifdef CYGSEM_REDBOOT_NETWORKING_DHCP
+
+# define AddOption(p,d) do {memcpy(p,d,sizeof d); p += sizeof d;} while (0)
+
+// add DHCP DISCOVER fields to a basic BOOTP request
+static int
+prep_dhcp_discover(bootp_header_t *b)
+{
+    unsigned char  *p = b->bp_vend;
+    AddOption(p, dhcpCookie);
+    AddOption(p, dhcpDiscover);
+    AddOption(p, dhcpParamRequestList);
+    AddOption(p, dhcpEnd);
+    if (p < &b->bp_vend[BP_MIN_VEND_SIZE])
+        p = &b->bp_vend[BP_MIN_VEND_SIZE];
+    return p - (unsigned char *)b;
+}
+
+// add DHCP REQUEST fields to a basic BOOTP request using data from supplied DHCP OFFER
+static int
+prep_dhcp_request(bootp_header_t *b, bootp_header_t *offer)
+{
+    unsigned char  *p = b->bp_vend;
+    AddOption(p, dhcpCookie);
+    AddOption(p, dhcpRequest);
+    AddOption(p, dhcpRequestIP);
+    memcpy(p, &offer->bp_yiaddr, dhcpRequestIP[1]);
+    p += dhcpRequestIP[1];                            // Ask for the address just given
+    AddOption(p, dhcpParamRequestList);
+    AddOption(p, dhcpEnd);
+    if (p < &b->bp_vend[BP_MIN_VEND_SIZE])
+        p = &b->bp_vend[BP_MIN_VEND_SIZE];
+    return p - (unsigned char *)b;
+}
+#endif
+
+// Macro used to change state of BOOTP/DHCP state machine
+#define NewDhcpState(state)  do {dhcpState = state; debug_printf("DHCP state: %s\n",dhcpStateString[state]);}while(0)
+
+// send BOOTP REQUEST or DHCP DISCOVER
+static void
+bootp_start(void)
+{
+    int             txSize;
+    bootp_header_t  b;
+    // send out a BOOTP request or DHCP DISCOVER
+    prep_bootp_request(&b);            // basic BOOTP request
+#ifdef CYGSEM_REDBOOT_NETWORKING_DHCP
+    debug_printf("DHCP  send: DISCOVER\n");
+    NewDhcpState(DHCP_WAITING_FOR_OFFER);
+    txSize = prep_dhcp_discover(&b);   // make it into DHCP DISCOVER
+#else
+    debug_printf("BOOTP send: REQUEST\n");
+    txSize = sizeof(b);
+#endif
+    __udp_send((char *)&b, txSize, (ip_route_t*)&broadcast, IPPORT_BOOTPS, IPPORT_BOOTPC);
+}
+
+// save packet for use by other commands
+static void
+save_packet(void *b, int len)
+{
+    memset(bp_info, 0, sizeof *bp_info);
+    if ((unsigned)len > sizeof *bp_info)
+        len = sizeof *bp_info;
+    memcpy(bp_info, b, len);
+}
+
+// Handler for received BOOTP/DHCP packets
+static void
+bootp_handler(udp_socket_t *skt, char *buf, int len, ip_route_t *src_route,
+              word src_port)
 {
     bootp_header_t *b;
 #ifdef CYGSEM_REDBOOT_NETWORKING_DHCP
-    unsigned char *p, expected = 0;
+    int             txSize;
+    int             type;
+    bootp_header_t  txpkt;
+    unsigned        expected = 0;
 #endif
 
-    b = (bootp_header_t *)buf;
-    if (bp_info) {
-        memset(bp_info,0,sizeof *bp_info);
-        if (len > sizeof *bp_info)
-            len = sizeof *bp_info;
-        memcpy(bp_info, b, len);
+    b = (bootp_header_t *) buf;
+
+    // only accept BOOTP REPLY responses
+    if (b->bp_op != BOOTREPLY)
+        return;
+
+    // must be sent to me
+    if (memcmp(b->bp_chaddr, __local_enet_addr, b->bp_hlen))
+        return;
+
+    // verify XID
+    if (b->bp_xid != xid)
+        return;
+
+#if !defined(CYGSEM_REDBOOT_NETWORKING_DHCP)
+    // simple BOOTP - this is all there is!
+    debug_printf("BOOTP recv: REPLY\n");
+    if (dhcpState != DHCP_DONE) {
+        save_packet(b, len);
+        parseConfig(b, len);
+        NewDhcpState(DHCP_DONE);
+    }
+#else
+    // DHCP support is enabled...
+
+    // Check to see that it's a DHCP packet with a DHCP type field
+
+    type = -1;
+    if (!memcmp(b->bp_vend, dhcpCookie, sizeof dhcpCookie)) {
+        unsigned char *p = b->bp_vend + 4;
+        while (p < (unsigned char *)b + len) {
+            if (*p == TAG_DHCP_MESS_TYPE) {
+                type = p[2];
+                break;
+            }
+            p += p[1] + 2;
+        }
     }
 
-    // Only accept pure REPLY responses
-    if (b->bp_op != BOOTREPLY)
-      return;
-    
-    // Must be sent to me, as well!
-    if (memcmp(b->bp_chaddr, __local_enet_addr, 6))
-      return;
+    if (type == -1) {
+        // apparently we have a BOOTP (but not not DHCP) server
+        debug_printf("DHCP  recv: BOOTP-REPLY -- falling back to BOOTP mode\n");
+        if (dhcpState != DHCP_DONE) {
+            save_packet(b, len);
+            parseConfig(b, len);
+            NewDhcpState(DHCP_DONE);
+        }
+        return;
+    }
         
-#ifdef CYGSEM_REDBOOT_NETWORKING_DHCP
-    p = b->bp_vend;
-    if (memcmp(p, dhcpCookie, sizeof(dhcpCookie)))
-      return;
-    p += 4;
-
-    // Find the DHCP Message Type tag
-    while (*p != TAG_DHCP_MESS_TYPE) {
-        p += p[1] + 2;
-        if (p >= (unsigned char*)b + sizeof(*bp_info))
-            return;
-    }
-
-    p += 2;
+    // it's a real DHCP packet
+    debug_printf("DHCP  recv: %s [%d]\n", dhcpTypeString[type], type);
 
     switch (dhcpState) {
-    case DHCP_DISCOVER:
-        // The discover message has been sent, only accept an offer reply
-        if (*p == DHCP_MESS_TYPE_OFFER) {
-            dhcpState = DHCP_OFFER;
+    case DHCP_WAITING_FOR_OFFER:
+        if (type == (expected = DHCP_MESS_TYPE_OFFER)) {
+            prep_bootp_request(&txpkt);
+            txSize = prep_dhcp_request(&txpkt, b);
+            debug_printf("DHCP  send: REQUEST\n");
+            NewDhcpState(DHCP_WAITING_FOR_ACK);
+            __udp_send((char *)&txpkt, txSize, (ip_route_t *)&broadcast, IPPORT_BOOTPS, IPPORT_BOOTPC);
             return;
-        } else {
-            expected = DHCP_MESS_TYPE_OFFER;
         }
         break;
-    case DHCP_REQUEST:
-        // The request message has been sent, only accept an ack reply
-        if (*p == DHCP_MESS_TYPE_ACK) {
-            dhcpState = DHCP_ACK;
+
+    case DHCP_WAITING_FOR_ACK:
+        if (type == (expected = DHCP_MESS_TYPE_ACK)) {
+            save_packet(b, len);
+            parseConfig(b, len);
+            NewDhcpState(DHCP_DONE);
             return;
-        } else {
-            expected = DHCP_MESS_TYPE_ACK;
         }
         break;
-    case DHCP_NONE:
-    case DHCP_OFFER:
-    case DHCP_ACK:
-        // Quitely ignore these - they indicate repeated message from server
+
+    default:
+        debug_printf("DHCP packet ignored\n");
         return;
     }
-    // See if we've been NAK'd - if so, give up and try again
-    if (*p == DHCP_MESS_TYPE_NAK) {
-        dhcpState = DHCP_NONE;
+
+    if (type == DHCP_MESS_TYPE_NAK && dhcpState != DHCP_DONE) {
+        NewDhcpState(DHCP_FAILED);
         return;
     }
-    diag_printf("DHCP reply: %d, not %d\n", (int)*p, (int)expected);
-    return;
-#else
-    // Simple BOOTP - this is all there is!
-    memcpy(__local_ip_addr, &b->bp_yiaddr, 4);
+
+    debug_printf("DHCP packet ignored -- expected %d[%s]\n", expected, dhcpTypeString[expected]);
 #endif
 }
 
-#define AddOption(p,d) do {memcpy(p,d,sizeof d); p += sizeof d;} while (0)
 
-/*
- * Find our IP address and copy to __local_ip_addr.
- * Return zero if successful, -1 if not.
- */
+// Request IP configuration via BOOTP/DHCP.
+// Return zero if successful, -1 if not.
+
 int
 __bootp_find_local_ip(bootp_header_t *info)
 {
-    udp_socket_t udp_skt;
-    bootp_header_t b;
-    ip_route_t     r;
-    int            retry;
-    unsigned long  start;
-    ip_addr_t saved_ip_addr;
-#ifdef CYGSEM_REDBOOT_NETWORKING_DHCP
-    unsigned char *p;
-    int oldState;
-#endif
-    int txSize;
-    bool abort = false;
-    static int xid = SHOULD_BE_RANDOM;
+    udp_socket_t    udp_skt;
+    int             retry;
+    unsigned long   start;
+    ip_addr_t       saved_ip_addr;
 
-#ifdef CYGSEM_REDBOOT_NETWORKING_DHCP
-    dhcpState = DHCP_NONE;
-#endif
+    bp_info = info;
+
+    diag_printf("\nRequesting IP conf via BOOTP/DHCP...\n");
 
-    // Where we want the results saved
-    bp_info = info;
-    // Preserve any IP address we currently have, just in case
-    memcpy(saved_ip_addr, __local_ip_addr, sizeof(__local_ip_addr));
+    memcpy(&xid, __local_enet_addr, sizeof xid);
+    xid ^= (__local_enet_addr[4]<<16) + __local_enet_addr[5];
+    xid ^= (unsigned)&retry + (unsigned)&__bootp_find_local_ip;
 
-    // fill out route for a broadcast
-    r.ip_addr[0] = 255;
-    r.ip_addr[1] = 255;
-    r.ip_addr[2] = 255;
-    r.ip_addr[3] = 255;
-    r.enet_addr[0] = 255;
-    r.enet_addr[1] = 255;
-    r.enet_addr[2] = 255;
-    r.enet_addr[3] = 255;
-    r.enet_addr[4] = 255;
-    r.enet_addr[5] = 255;
+    debug_printf("XID: %08x\n",xid);
 
-    // setup a socket listener for bootp replies
+    memcpy(saved_ip_addr, __local_ip_addr, sizeof __local_ip_addr);    // save our IP in case of failure
+
+    NewDhcpState(DHCP_NONE);
+
     __udp_install_listener(&udp_skt, IPPORT_BOOTPC, bootp_handler);
 
-    retry = MAX_RETRIES;  
-    do {
-	start = MS_TICKS();
+    retry = MAX_RETRIES;
 
-        // Build up the BOOTP/DHCP request
-        memset(&b, 0, sizeof(b));
-        b.bp_op = BOOTREQUEST;
-        b.bp_htype = HTYPE_ETHERNET;
-        b.bp_hlen = 6;
-        b.bp_xid = xid++;
-        memcpy(b.bp_chaddr, __local_enet_addr, 6);
+    while (retry > 0) {
+        start = MS_TICKS();
         memset(__local_ip_addr, 0, sizeof(__local_ip_addr));
-         
-#ifdef CYGSEM_REDBOOT_NETWORKING_DHCP
-        p = b.bp_vend;
-        switch (dhcpState) {
-        case DHCP_NONE:
-        case DHCP_DISCOVER:
-            AddOption(p,dhcpCookie);
-            AddOption(p,dhcpDiscover);
-            AddOption(p,dhcpParamRequestList);
-            AddOption(p,dhcpEnd);
-            dhcpState = DHCP_DISCOVER;
-            break;
-        case DHCP_OFFER:
-            retry = MAX_RETRIES;
-        case DHCP_REQUEST:
-            b.bp_xid = bp_info->bp_xid;  // Match what server sent
-            AddOption(p,dhcpCookie);
-            AddOption(p,dhcpRequest);
-            AddOption(p,dhcpRequestIP);
-            memcpy(p, &bp_info->bp_yiaddr, 4);  p += 4;  // Ask for the address just given
-            AddOption(p,dhcpParamRequestList);
-            AddOption(p,dhcpEnd);
-            dhcpState = DHCP_REQUEST;
-            memset(&b.bp_yiaddr, 0xFF, 4);
-            memset(&b.bp_siaddr, 0xFF, 4);
-            memset(&b.bp_yiaddr, 0x00, 4);
-            memset(&b.bp_siaddr, 0x00, 4);
-            break;
-        case DHCP_ACK:
-            // Ignore these states (they won't happen)
-            break;
-        }
-     
-        // Some servers insist on a minimum amount of "vendor" data
-        if (p < &b.bp_vend[BP_MIN_VEND_SIZE]) p = &b.bp_vend[BP_MIN_VEND_SIZE];
-        txSize = p - (unsigned char*)&b;
-        oldState = dhcpState;
-#else
-        txSize = sizeof(b);
-#endif
 
-	__udp_send((char *)&b, txSize, &r, IPPORT_BOOTPS, IPPORT_BOOTPC);
-
-        // If we're retrying, inform the user
-        if (retry == (MAX_RETRIES-1))
-            diag_printf("... waiting for BOOTP information\n");
+        // send bootp REQUEST or dhcp DISCOVER
+        bootp_start();
 
-	do {
-	    __enet_poll();
-#ifdef CYGSEM_REDBOOT_NETWORKING_DHCP
-            if (dhcpState != oldState) {
-                if (dhcpState == DHCP_ACK) {
-                    unsigned char *end;
-                    int optlen;
-                    // Address information has now arrived!
-                    memcpy(__local_ip_addr, &bp_info->bp_yiaddr, 4);
-#ifdef CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY
-                    memcpy(__local_ip_gate, &bp_info->bp_giaddr, 4);
-#endif
-                    p = bp_info->bp_vend+4;
-                    end = (unsigned char *)bp_info+sizeof(*bp_info);
-                    while (p < end) {
-                        unsigned char tag = *p;
-                        if (tag == TAG_END)
-                            break;
-                        if (tag == TAG_PAD)
-                            optlen = 1;
-                        else {
-                            optlen = p[1];
-                            p += 2;
-                            switch (tag) {
-#ifdef CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY
-                            case TAG_SUBNET_MASK:  // subnet mask
-                                memcpy(__local_ip_mask,p,4); 
-                                break;
-                            case TAG_GATEWAY:  // router
-                                memcpy(__local_ip_gate,p,4); 
-                                break;
-#endif
-#ifdef CYGPKG_REDBOOT_NETWORKING_DNS
-			    case TAG_DOMAIN_SERVER:
-//				diag_printf(" DNS server found!\n");
-				memcpy(&__bootp_dns_addr, p, 4);
-				__bootp_dns_set = 1;
-				break;
-#ifdef CYGPKG_REDBOOT_NETWORKING_DNS_DHCP_DOMAIN
-                            case TAG_DOMAIN_NAME:
-                                if(optlen < sizeof(__bootp_dns_domain)) {
-                                    memcpy(__bootp_dns_domain, p, optlen);
-                                    __bootp_dns_domain[optlen] = '\0';
-                                    __bootp_dns_domain_set = 1;
-                                } else {
-                                  diag_printf("DNS domain name too long\n");
-                                }
-                                break;
-#endif //CYGPKG_REDBOOT_NETWORKING_DNS_DHCP_DOMAIN
-#endif //CYGPKG_REDBOOT_NETWORKING_DNS
-                            default:
-                                break;
-                            }
-                        }
-                        p += optlen;
-                    }
-                    __udp_remove_listener(IPPORT_BOOTPC);
-                    return 0;
-                } else {
-                    break;  // State changed, handle it
-                }
-            }
-#else
-            // All done, if address response has arrived
-	    if (__local_ip_addr[0] || __local_ip_addr[1] ||
-		__local_ip_addr[2] || __local_ip_addr[3]) {
-		/* success */
-		__udp_remove_listener(IPPORT_BOOTPC);
-		return 0;
-	    }
-#endif
-            if (_rb_break(1)) {
-                // The user typed ^C on the console
-                abort = true;
+        // wait for timeout, user-abort, or for receive packet handler to fail/succeed
+        while ((MS_TICKS_DELAY() - start) < RETRY_TIME_MS) {
+            __enet_poll();
+            if (dhcpState == DHCP_FAILED)
                 break;
-            }
-            MS_TICKS_DELAY();  // Count for ^C test
-	} while ((MS_TICKS_DELAY() - start) < RETRY_TIME);
-    } while (!abort && (retry-- > 0));
+            if (dhcpState == DHCP_DONE)
+                goto done;
+            if (_rb_break(1))          // did user hit ^C?
+                goto failed;
+            MS_TICKS_DELAY();
+        }
+        --retry;
+        ++xid;
+        diag_printf("TIMEOUT%s\n", retry ? ", retrying..." : "");
+    }
 
-    // timed out
+failed:
+    diag_printf("FAIL\n");
     __udp_remove_listener(IPPORT_BOOTPC);
-    // Restore any previous IP address
-    memcpy(__local_ip_addr, saved_ip_addr, sizeof(__local_ip_addr));
+    memcpy(__local_ip_addr, saved_ip_addr, sizeof __local_ip_addr);    // restore prev IP
     return -1;
+
+done:
+    diag_printf("OK\n");
+    __udp_remove_listener(IPPORT_BOOTPC);
+    return 0;
 }
-
-
diff --git a/packages/redboot/current/src/net/net_io.c b/packages/redboot/current/src/net/net_io.c
--- a/packages/redboot/current/src/net/net_io.c
+++ b/packages/redboot/current/src/net/net_io.c
@@ -59,6 +59,10 @@
 #include <cyg/hal/hal_intr.h>
 #include <cyg/infra/cyg_ass.h>         // assertion macros
 
+#ifndef CYGSEM_REDBOOT_DEFAULT_NO_BOOTP
+#define CYGSEM_REDBOOT_DEFAULT_NO_BOOTP 0
+#endif
+
 #ifdef CYGSEM_REDBOOT_FLASH_CONFIG
 #include <flash_config.h>
 
@@ -90,15 +94,14 @@ RedBoot_config_option("Default network d
 // negated (if false, the others apply) which makes the names even more
 // confusing.
 
-#ifndef CYGSEM_REDBOOT_DEFAULT_NO_BOOTP
-#define CYGSEM_REDBOOT_DEFAULT_NO_BOOTP 0
-#endif
+#ifdef CYGPKG_REDBOOT_NETWORKING_BOOTP
 RedBoot_config_option("Use BOOTP for network configuration",
                       bootp, 
                       ALWAYS_ENABLED, true,
                       CONFIG_BOOL,
                       !CYGSEM_REDBOOT_DEFAULT_NO_BOOTP
     );
+#endif
 RedBoot_config_option("Local IP address",
                       bootp_my_ip,
                       "bootp", false,
@@ -689,10 +692,10 @@ net_init(void)
 #endif
 
     // Set defaults as appropriate
-#ifdef CYGSEM_REDBOOT_DEFAULT_NO_BOOTP
+#if defined(CYGPKG_REDBOOT_NETWORKING_BOOTP) && !CYGSEM_REDBOOT_DEFAULT_NO_BOOTP
+    use_bootp = true;
+#else
     use_bootp = false;
-#else
-    use_bootp = true;
 #endif
 #ifdef CYGDBG_REDBOOT_NET_DEBUG
     net_debug = true;
@@ -707,7 +710,9 @@ net_init(void)
 #endif
     flash_get_config("net_debug", &net_debug, CONFIG_BOOL);
     flash_get_config("gdb_port", &gdb_port, CONFIG_INT);
+#ifdef CYGPKG_REDBOOT_NETWORKING_BOOTP
     flash_get_config("bootp", &use_bootp, CONFIG_BOOL);
+#endif
     if (!use_bootp) {
         flash_get_IP("bootp_my_ip", &__local_ip_addr);
 #ifdef CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY
@@ -767,6 +772,7 @@ net_init(void)
         return;
     }    
     // Initialize the network [if present]
+#ifdef CYGPKG_REDBOOT_NETWORKING_BOOTP
     if (use_bootp) {
         if (__bootp_find_local_ip(&my_bootp_info) == 0) {
             have_net = true;
@@ -781,7 +787,9 @@ net_init(void)
                 have_net = true;
             }
         }
-    } else {
+    }
+#endif
+    if (!use_bootp) {
         if (__local_ip_addr[0] == 0 && __local_ip_addr[1] == 0 &&
             __local_ip_addr[2] == 0 && __local_ip_addr[3] == 0) {
             show_eth_info();
@@ -813,7 +821,11 @@ net_init(void)
     }
 }
 
-static char usage[] = "[-b] [-l <local_ip_address>[/<mask_len>]] [-h <server_address>]"
+static char usage[] = ""
+#ifdef CYGPKG_REDBOOT_NETWORKING_BOOTP
+       " [-b]"
+#endif
+       " [-l <local_ip_address>[/<mask_len>]] [-h <server_address>]"
 #ifdef CYGPKG_REDBOOT_NETWORKING_DNS
 	" [-d <dns_server_address>]"
 #ifdef CYGPKG_REDBOOT_NETWORKING_DNS_FCONFIG_DOMAIN                                                  
@@ -836,7 +848,9 @@ do_ip_addr(int argc, char *argv[])
     struct option_info opts[5];
     char *ip_addr, *host_addr;
     bool ip_addr_set, host_addr_set;
+#ifdef CYGPKG_REDBOOT_NETWORKING_BOOTP
     bool do_bootp = false;
+#endif
     struct sockaddr_in host;
 #ifdef CYGPKG_REDBOOT_NETWORKING_DNS
     char *dns_addr;
@@ -857,9 +871,12 @@ do_ip_addr(int argc, char *argv[])
               (void *)&ip_addr, (bool *)&ip_addr_set, "local IP address");
     init_opts(&opts[1], 'h', true, OPTION_ARG_TYPE_STR, 
               (void *)&host_addr, (bool *)&host_addr_set, "default server address");
+    num_opts = 2;
+#ifdef CYGPKG_REDBOOT_NETWORKING_BOOTP
     init_opts(&opts[2], 'b', false, OPTION_ARG_TYPE_FLG,
               &do_bootp, 0, "use BOOTP");
-    num_opts = 3;
+    num_opts++;
+#endif
 #ifdef CYGPKG_REDBOOT_NETWORKING_DNS
     init_opts(&opts[num_opts], 'd', true, OPTION_ARG_TYPE_STR, 
               (void *)&dns_addr, (bool *)&dns_addr_set, "DNS server address");
@@ -875,11 +892,13 @@ do_ip_addr(int argc, char *argv[])
     if (!scan_opts(argc, argv, 1, opts, num_opts, 0, 0, "")) {
         return;
     }
+#ifdef CYGPKG_REDBOOT_NETWORKING_BOOTP
     if (do_bootp) {
         if (__bootp_find_local_ip(&my_bootp_info) != 0) {
             diag_printf("Failed to get BOOTP address\n");
         }
     }
+#endif
     if (ip_addr_set) {
 #ifdef CYGSEM_REDBOOT_NETWORKING_USE_GATEWAY
         char *slash_pos;
diff --git a/packages/services/curses/pdcurses/current/ChangeLog b/packages/services/curses/pdcurses/current/ChangeLog
--- a/packages/services/curses/pdcurses/current/ChangeLog
+++ b/packages/services/curses/pdcurses/current/ChangeLog
@@ -1,3 +1,14 @@
+2012-03-26  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* examples/*: Removed an odd skeleton of PDcurses application.
+	NOTE: PDCurses is not thread-safe. [ Bugilla 1001544 ]
+
+2012-03-24  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* src/drivers/serial.c (PDC_check_key): Refactored to fix new compiler
+	warnings (dereferencing type-punned pointer will break strict-aliasing
+	rules).
+
 2009-03-26  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
 
 	* cdl/pdcurses.cdl:
diff --git a/packages/services/curses/pdcurses/current/examples/Makefile b/packages/services/curses/pdcurses/current/examples/Makefile
deleted file mode 100644
--- a/packages/services/curses/pdcurses/current/examples/Makefile
+++ /dev/null
@@ -1,29 +0,0 @@
-#
-# Makefile for PDCurses eCos Application
-#
-
-.PHONY: all clean
-
-# Platform specific setups
-include Make.params
-
-# Simple build rules
-
-%.o: %.c
-	$(CC) -c $*.c $(ACTUAL_CFLAGS) -I$(PREFIX)/include -o $@
-
-# PDCurses CFLAGS
-ACTUAL_CFLAGS := $(subst , -D__ECOS__,$(ACTUAL_CFLAGS))
-ACTUAL_CFLAGS := $(subst , -D_LP64=0,$(ACTUAL_CFLAGS))
-
-OBJS           = pdcecos_app.o pdcecos_init.o pdcecos_thread.o 
-DST            = pdcecos_app
-
-all: ${DST}
-
-clean:
-	-rm -f ${DST} ${OBJS}
-
-${DST}: ${OBJS}
-	$(CC) $(ACTUAL_LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o $@ $^
-
diff --git a/packages/services/curses/pdcurses/current/examples/README b/packages/services/curses/pdcurses/current/examples/README
deleted file mode 100644
--- a/packages/services/curses/pdcurses/current/examples/README
+++ /dev/null
@@ -1,65 +0,0 @@
-* PDCurses + eCos Application
-  ---------------------------
-
-It is possible to run a curses program in a separate eCos thread. Look
-at the pdcecos_app.h, pdcecos_app.c, pdcecos_init.c, pdcecos_thread.c
-sources for details.
-
-As you can see you should put own curses code inside a pdcecos_main()
-function instead of traditional main() entry. In such a build you have
-to link your executable with a pdcecos_app.o object file, and a curses
-program must look as
-
-    #include <curses.h>
-    ...
-
-    int
-    pdcecos_main(int argc, char *argv[])
-    {
-        initscr();
-        ...
-    }
-
-The pdcecos_app.c has cyg_user_start() entry where a startup_thread()
-creates and resumes itself there.  The startup_tread() creates and
-invokes a set of threads are defined in a __PDC_APP_TAB__. By default
-only alone thread is registered in the table, it is pdcecos_thread(),
-but you can expand the table. When the pdcecos_thread() is started, it
-invokes the pdcecos_main() function -- your curses program.
-
-The "PDCECOS" thread uses a separate stack as well, you can change its
-size by default is ( CYGNUM_HAL_STACK_SIZE_TYPICAL * 2 ).
-
-To build a PDCurses+eCos demo application, first generate a Make.params
-file using the build_Make.params script which is placed under the eCos
-`examples' directory and then just type 'make'.
-
-There is an example of running the pdcecos_app demo in GDB the below. As
-you can see the "PDCECOS" thread starts and invokes pdcecos_main() then.
-
-    (gdb) break pdcecos_main
-    Breakpoint 1 at 0x100111b: pdcecos_thread.c, line 93.
-    (gdb) continue
-    Starting program: pdcecos_app
-    SYSTEM INITIALIZATION in progress
-    data index = 4
-    Creating system threads
-    Creating PDCECOS thread
-    Starting threads
-    Starting PDCECOS
-    SYSTEM THREADS STARTED!
-
-    Breakpoint 1, pdcecos_main (argc=0, argv=0x0)
-        at pdcecos_thread.c:93
-        88          initscr();
-        Current language:  auto; currently c
-    (gdb) continue
-
-Then you should see a message
-
-    Hello PDCurses+eCos World!
-    
-in a terminal program (minicom, hyperterm, etc.).
-
-
-------------------------------------------------------------------------
diff --git a/packages/services/curses/pdcurses/current/examples/pdcecos_app.c b/packages/services/curses/pdcurses/current/examples/pdcecos_app.c
deleted file mode 100644
--- a/packages/services/curses/pdcurses/current/examples/pdcecos_app.c
+++ /dev/null
@@ -1,170 +0,0 @@
-// ==========================================================================
-// 
-//      pdcecos_app.c
-// 
-//      Public Domain Curses for eCos
-// 
-// ===========================================================================
-// ####ECOSGPLCOPYRIGHTBEGIN####                                            
-// -------------------------------------------                              
-// This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2009 Free Software Foundation, Inc.
-//
-// eCos is free software; you can redistribute it and/or modify it under    
-// the terms of the GNU General Public License as published by the Free     
-// Software Foundation; either version 2 or (at your option) any later      
-// version.                                                                 
-//
-// eCos is distributed in the hope that it will be useful, but WITHOUT      
-// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
-// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
-// for more details.                                                        
-//
-// You should have received a copy of the GNU General Public License        
-// along with eCos; if not, write to the Free Software Foundation, Inc.,    
-// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
-//
-// As a special exception, if other files instantiate templates or use      
-// macros or inline functions from this file, or you compile this file      
-// and link it with other works to produce a work based on this file,       
-// this file does not by itself cause the resulting work to be covered by   
-// the GNU General Public License. However the source code for this file    
-// must still be made available in accordance with section (3) of the GNU   
-// General Public License v2.                                               
-//
-// This exception does not invalidate any other reasons why a work based    
-// on this file might be covered by the GNU General Public License.         
-// -------------------------------------------                              
-// ####ECOSGPLCOPYRIGHTEND####                                              
-// ===========================================================================
-// ===========================================================================
-// #####DESCRIPTIONBEGIN####
-// 
-// Author(s):    Sergei Gavrikov
-// Contributors: Sergei Gavrikov
-// Date:         2009-03-26
-// Purpose:      Early startup for PDCurses stuff
-// Description:
-// 
-// ####DESCRIPTIONEND####
-// 
-// ========================================================================*/
-
-// ---------------------------------------------------------------------------
-// CONFIGURATION CHECKS 
-// 
-
-#include <pkgconf/system.h>            // which packages are enabled/disabled
-#ifdef CYGPKG_KERNEL
-# include <pkgconf/kernel.h>
-#endif
-#ifdef CYGPKG_LIBC
-# include <pkgconf/libc.h>
-#endif
-#ifdef CYGPKG_IO_SERIAL
-# include <pkgconf/io_serial.h>
-#endif
-#ifdef CYGPKG_FS_JFFS2
-# include <pkgconf/io_flash.h>
-#define USE_JFFS2
-#endif
-
-#ifndef CYGFUN_KERNEL_API_C
-# error Kernel API must be enabled to build this application
-#endif
-
-#ifndef CYGPKG_LIBC_STDIO
-# error C library standard I/O must be enabled to build this application
-#endif
-
-#ifndef CYGPKG_IO_SERIAL_HALDIAG
-# error I/O HALDIAG pseudo-device driver must be enabled to build this application
-#endif
-
-#include <pkgconf/pdcurses.h>
-
-// ---------------------------------------------------------------------------
-// INCLUDES 
-// 
-
-#include <stdio.h>                     // printf
-#include <stdlib.h>                    // printf
-
-#include <cyg/kernel/kapi.h>           // All the kernel specific stuff
-#include <cyg/hal/hal_arch.h>          // CYGNUM_HAL_STACK_SIZE_TYPICAL
-
-#include "pdcecos_app.h"
-
-// Define table boundaries
-CYG_HAL_TABLE_BEGIN(__PDC_APP_TAB__, _pdc_apps);
-CYG_HAL_TABLE_END(__PDC_APP_TAB_END__, _pdc_apps);
-extern struct _pdc_app_entry __PDC_APP_TAB__[],
-                __PDC_APP_TAB_END__;
-
-// ---------------------------------------------------------------------------
-// PDCurses startup thread. 
-// 
-static char     startup_stack[STACKSIZE];
-cyg_handle_t    startup_thread;
-cyg_thread      startup_thread_obj;
-
-static void
-startup(CYG_ADDRESS data)
-{
-    cyg_ucount32    pdc_data_index;
-    struct _pdc_app_entry *pdc;
-
-    printf("SYSTEM INITIALIZATION in progress\n");
-
-#ifdef USE_JFFS2
-    {
-        int             res;
-        printf("... Mounting JFFS2 on \"/\"\n");
-        res = mount(CYGDAT_IO_FLASH_BLOCK_DEVICE_NAME_1, "/", "jffs2");
-        if (res < 0) {
-            printf("Mount \"/\" failed - res: %d\n", res);
-        }
-        chdir("/");
-    }
-#endif
-
-    pdc_data_index = cyg_thread_new_data_index();
-    printf("data index = %d\n", pdc_data_index);
-
-    printf("Creating system threads\n");
-    for (pdc = __PDC_APP_TAB__; pdc != &__PDC_APP_TAB_END__; pdc++) {
-        printf("Creating %s thread\n", pdc->name);
-        cyg_thread_create(pdc->prio,
-                          pdc->entry,
-                          (cyg_addrword_t) pdc_data_index,
-                          pdc->name,
-                          (void *) pdc->stack, STACKSIZE,
-                          &pdc->t, &pdc->t_obj);
-    }
-    printf("Starting threads\n");
-    for (pdc = __PDC_APP_TAB__; pdc != &__PDC_APP_TAB_END__; pdc++) {
-        printf("Starting %s\n", pdc->name);
-        cyg_thread_resume(pdc->t);
-        if (pdc->init) {
-            (pdc->init) (pdc_data_index);
-        }
-    }
-
-    printf("SYSTEM THREADS STARTED!\n");
-}
-
-void
-cyg_user_start(void)
-{
-    // Create the initial thread and start it up
-    cyg_thread_create(PDC_ECOS_STARTUP_PRIORITY,
-                      startup,
-                      (cyg_addrword_t) 0,
-                      "System startup",
-                      (void *) startup_stack, STACKSIZE,
-                      &startup_thread, &startup_thread_obj);
-    cyg_thread_resume(startup_thread);
-}
-
-// ---------------------------------------------------------------------------
-// EOF pdcecos_app.c
diff --git a/packages/services/curses/pdcurses/current/examples/pdcecos_app.h b/packages/services/curses/pdcurses/current/examples/pdcecos_app.h
deleted file mode 100644
--- a/packages/services/curses/pdcurses/current/examples/pdcecos_app.h
+++ /dev/null
@@ -1,94 +0,0 @@
-#ifndef CYGONCE_PDCECOS_APP_H
-#define CYGONCE_PDCECOS_APP_H
-// ==========================================================================
-// 
-//      pdcecos_app.h
-// 
-//      Public Domain Curses for eCos
-// 
-// ===========================================================================
-// ####ECOSGPLCOPYRIGHTBEGIN####                                            
-// -------------------------------------------                              
-// This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2009 Free Software Foundation, Inc.
-//
-// eCos is free software; you can redistribute it and/or modify it under    
-// the terms of the GNU General Public License as published by the Free     
-// Software Foundation; either version 2 or (at your option) any later      
-// version.                                                                 
-//
-// eCos is distributed in the hope that it will be useful, but WITHOUT      
-// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
-// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
-// for more details.                                                        
-//
-// You should have received a copy of the GNU General Public License        
-// along with eCos; if not, write to the Free Software Foundation, Inc.,    
-// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
-//
-// As a special exception, if other files instantiate templates or use      
-// macros or inline functions from this file, or you compile this file      
-// and link it with other works to produce a work based on this file,       
-// this file does not by itself cause the resulting work to be covered by   
-// the GNU General Public License. However the source code for this file    
-// must still be made available in accordance with section (3) of the GNU   
-// General Public License v2.                                               
-//
-// This exception does not invalidate any other reasons why a work based    
-// on this file might be covered by the GNU General Public License.         
-// -------------------------------------------                              
-// ####ECOSGPLCOPYRIGHTEND####                                              
-// ===========================================================================
-// ===========================================================================
-// #####DESCRIPTIONBEGIN####
-// 
-// Author(s):    Sergei Gavrikov
-// Contributors: Sergei Gavrikov
-// Date:         2009-03-26
-// Purpose:      Definitions for PDCECOS thread
-// Description:
-// Usage:        #include "pdcecos_app.h"
-// 
-// ####DESCRIPTIONEND####
-// 
-// ========================================================================*/
-
-#include <cyg/kernel/kapi.h>
-#include <cyg/infra/cyg_type.h>
-#include <cyg/hal/hal_tables.h>
-#include <cyg/hal/hal_arch.h>          // CYGNUM_HAL_STACK_SIZE_TYPICAL
-
-#include <pkgconf/pdcurses.h>
-
-#define STACKSIZE ( CYGNUM_HAL_STACK_SIZE_TYPICAL * 2 )
-
-typedef void    fun(CYG_ADDRWORD);
-struct _pdc_app_entry {
-    char           *name;
-    fun            *entry;
-    int             prio;
-    fun            *init;
-    cyg_handle_t    t;
-    cyg_thread      t_obj;
-    char            stack[STACKSIZE];
-} CYG_HAL_TABLE_TYPE;
-
-#define _pdc_app(_name_,_id_,_pri_,_init_)              \
-externC void _id_##_thread(CYG_ADDRWORD data);          \
-struct _pdc_app_entry _pdc_app_##_pri_##_##_id_         \
-   CYG_HAL_TABLE_QUALIFIED_ENTRY(_pdc_apps,_pri_) =     \
-     { _name_, _id_##_thread, _pri_, _init_};
-
-
-#define INIT_PER_THREAD_DATA()
-
-#define PDC_ECOS_STARTUP_PRIORITY 11
-#define PDC_ECOS_CORE_PRIORITY    (PDC_ECOS_STARTUP_PRIORITY+3)
-
-int
-pdcecos_main(int argc, char **argv)
-    CYGBLD_ATTRIB_WEAK;
-#endif
-
-// ---------------------------------------------------------------------
-// EOF pdcecos_app.h
diff --git a/packages/services/curses/pdcurses/current/examples/pdcecos_init.c b/packages/services/curses/pdcurses/current/examples/pdcecos_init.c
deleted file mode 100644
--- a/packages/services/curses/pdcurses/current/examples/pdcecos_init.c
+++ /dev/null
@@ -1,66 +0,0 @@
-// ==========================================================================
-// 
-//      pdcecos_init.c
-// 
-//      Public Domain Curses for eCos
-// 
-// ===========================================================================
-// ####ECOSGPLCOPYRIGHTBEGIN####                                            
-// -------------------------------------------                              
-// This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2009 Free Software Foundation, Inc.
-//
-// eCos is free software; you can redistribute it and/or modify it under    
-// the terms of the GNU General Public License as published by the Free     
-// Software Foundation; either version 2 or (at your option) any later      
-// version.                                                                 
-//
-// eCos is distributed in the hope that it will be useful, but WITHOUT      
-// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
-// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
-// for more details.                                                        
-//
-// You should have received a copy of the GNU General Public License        
-// along with eCos; if not, write to the Free Software Foundation, Inc.,    
-// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
-//
-// As a special exception, if other files instantiate templates or use      
-// macros or inline functions from this file, or you compile this file      
-// and link it with other works to produce a work based on this file,       
-// this file does not by itself cause the resulting work to be covered by   
-// the GNU General Public License. However the source code for this file    
-// must still be made available in accordance with section (3) of the GNU   
-// General Public License v2.                                               
-//
-// This exception does not invalidate any other reasons why a work based    
-// on this file might be covered by the GNU General Public License.         
-// -------------------------------------------                              
-// ####ECOSGPLCOPYRIGHTEND####                                              
-// ===========================================================================
-// ===========================================================================
-// #####DESCRIPTIONBEGIN####
-// 
-// Author(s):    Sergei Gavrikov
-// Contributors: Sergei Gavrikov
-// Date:         2009-03-26
-// Purpose:
-// Description:
-// 
-// ####DESCRIPTIONEND####
-// 
-// ========================================================================*/
-
-#include <cyg/infra/cyg_type.h>
-
-// ---------------------------------------------------------------------------
-// pdcecos_init --
-//
-void
-pdcecos_init(CYG_ADDRWORD data)
-{
-    // Currently, it does nothing.
-    CYG_UNUSED_PARAM(CYG_ADDRWORD, data);
-}
-
-// ---------------------------------------------------------------------------
-// EOF pdcecos_init.c
diff --git a/packages/services/curses/pdcurses/current/examples/pdcecos_thread.c b/packages/services/curses/pdcurses/current/examples/pdcecos_thread.c
deleted file mode 100644
--- a/packages/services/curses/pdcurses/current/examples/pdcecos_thread.c
+++ /dev/null
@@ -1,129 +0,0 @@
-// ==========================================================================
-// 
-//      pdcecos_thread.c
-// 
-//      Public Domain Curses for eCos
-// 
-// ===========================================================================
-// ####ECOSGPLCOPYRIGHTBEGIN####                                            
-// -------------------------------------------                              
-// This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2009 Free Software Foundation, Inc.
-//
-// eCos is free software; you can redistribute it and/or modify it under    
-// the terms of the GNU General Public License as published by the Free     
-// Software Foundation; either version 2 or (at your option) any later      
-// version.                                                                 
-//
-// eCos is distributed in the hope that it will be useful, but WITHOUT      
-// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
-// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
-// for more details.                                                        
-//
-// You should have received a copy of the GNU General Public License        
-// along with eCos; if not, write to the Free Software Foundation, Inc.,    
-// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
-//
-// As a special exception, if other files instantiate templates or use      
-// macros or inline functions from this file, or you compile this file      
-// and link it with other works to produce a work based on this file,       
-// this file does not by itself cause the resulting work to be covered by   
-// the GNU General Public License. However the source code for this file    
-// must still be made available in accordance with section (3) of the GNU   
-// General Public License v2.                                               
-//
-// This exception does not invalidate any other reasons why a work based    
-// on this file might be covered by the GNU General Public License.         
-// -------------------------------------------                              
-// ####ECOSGPLCOPYRIGHTEND####                                              
-// ===========================================================================
-// ===========================================================================
-// #####DESCRIPTIONBEGIN####
-// 
-// Author(s):    Sergei Gavrikov
-// Contributors: Sergei Gavrikov
-// Date:         2009-03-26
-// Purpose:      Used to run PDCurses program as eCos thread.
-// Description:
-// 
-// ####DESCRIPTIONEND####
-// 
-// ========================================================================*/
-
-#include <pkgconf/system.h>            // which packages are enabled/disabled
-#ifdef CYGPKG_KERNEL
-# include <pkgconf/kernel.h>
-#endif
-#ifdef CYGPKG_LIBC
-# include <pkgconf/libc.h>
-#endif
-#ifdef CYGPKG_IO_SERIAL
-# include <pkgconf/io_serial.h>
-#endif
-
-#ifndef CYGFUN_KERNEL_API_C
-# error Kernel API must be enabled to build this application
-#endif
-
-#ifndef CYGPKG_LIBC_STDIO
-# error C library standard I/O must be enabled to build this application
-#endif
-
-#ifndef CYGPKG_IO_SERIAL_HALDIAG
-# error I/O HALDIAG pseudo-device driver must be enabled to build this application
-#endif
-
-// --------------------------------------------------------------------------
-// INCLUDES
-// 
-
-#include <cyg/kernel/kapi.h>           // All the kernel specific stuff
-#include <cyg/infra/diag.h>
-
-#include <pkgconf/pdcurses.h>
-#include <curses.h>
-
-#include "pdcecos_app.h"
-
-extern void     pdcecos_init(CYG_ADDRWORD data);
-_pdc_app("PDCECOS", pdcecos, PDC_ECOS_CORE_PRIORITY, pdcecos_init);
-
-// --------------------------------------------------------------------------
-// Component interfaces
-// 
-
-// --------------------------------------------------------------------------
-// pdcecos_main --
-// 
-// Note: the pdcecos_main() is declared as a weaked function, Look at the
-//       "pdcecos_app.h". So, you can have own one in a user space.
-int
-pdcecos_main(int argc, char **argv)
-{
-    initscr();
-    printw("Hello PDCurses+eCos World!");
-    refresh();
-    getch();
-    endwin();
-
-    return 0;
-}
-
-// --------------------------------------------------------------------------
-// pdcecos_thread --
-// 
-void
-pdcecos_thread(CYG_ADDRWORD data)
-{
-    int             argc = 0;
-    char          **argv = NULL;
-
-    CYG_UNUSED_PARAM(CYG_ADDRWORD, data);
-
-    INIT_PER_THREAD_DATA();
-
-    pdcecos_main(argc, argv);
-}
-
-// ---------------------------------------------------------------------------
-// EOF pdcecos_thread.c
diff --git a/packages/services/curses/pdcurses/current/src/drivers/serial.c b/packages/services/curses/pdcurses/current/src/drivers/serial.c
--- a/packages/services/curses/pdcurses/current/src/drivers/serial.c
+++ b/packages/services/curses/pdcurses/current/src/drivers/serial.c
@@ -293,15 +293,18 @@ PDC_get_rows(void)
 // ---------------------------------------------------------------------------
 
 static int      key_code = ERR;
-static unsigned char keystroke[4] = { '\0', '\0', '\0', '\0' };
+static union {
+    cyg_uint32      key;
+    cyg_uint8       seq[4];
+} kk = {0};
 
-#define _FLSH_KEY() *(unsigned int *) &keystroke[0] = 0;
+#define SYM kk.seq
+#define FLUSH() kk.key=0
+
 #if (CYG_BYTEORDER == CYG_LSBFIRST)
-// Little endian
-# define _UNGET_KEY(_n_)  *(unsigned int *) &keystroke[0] >>= 8*(_n_)
-#elif (CYG_BYTEORDER == CYG_MSBFIRST)
-// Big endian
-# define _UNGET_KEY(_n_)  *(unsigned int *) &keystroke[0] <<= 8*(_n_)
+# define POP(x) kk.key>>=8*(x)
+#else
+# define POP(x) kk.key<<=8*(x)
 #endif
 
 bool
@@ -319,73 +322,73 @@ PDC_check_key(void)
     return (dev_buf_conf.rx_count > 0);
 #else
     if ((count = dev_buf_conf.rx_count) > 0) {
-        if (keystroke[0] == '\0') {
+        if (SYM[0] == '\0') {
             count = min(count, 4);
-            cyg_io_read(handle, &keystroke[0], &count);
-        } else if (keystroke[1] == '\0') {
+            cyg_io_read(handle, &SYM[0], &count);
+        } else if (SYM[1] == '\0') {
             count = min(count, 3);
-            cyg_io_read(handle, &keystroke[1], &count);
-        } else if (keystroke[2] == '\0') {
+            cyg_io_read(handle, &SYM[1], &count);
+        } else if (SYM[2] == '\0') {
             count = min(count, 2);
-            cyg_io_read(handle, &keystroke[2], &count);
-        } else if (keystroke[3] == '\0') {
+            cyg_io_read(handle, &SYM[2], &count);
+        } else if (SYM[3] == '\0') {
             count = min(count, 1);
-            cyg_io_read(handle, &keystroke[3], &count);
+            cyg_io_read(handle, &SYM[3], &count);
         }
     }
-    if (keystroke[0] == '\0')
+    if (SYM[0] == '\0')
         return FALSE;
-    switch (keystroke[0]) {
+    switch (SYM[0]) {
     case '\x1b':
-        switch (keystroke[1]) {
+        switch (SYM[1]) {
         case '[':
-            switch (keystroke[2]) {
+            switch (SYM[2]) {
                 // ^[[A -- KEY_UP
             case 'A':
                 key_code = KEY_UP;
-                _UNGET_KEY(3);
+                POP(3);
                 return TRUE;
                 // ^[[B -- KEY_DOWN
             case 'B':
                 key_code = KEY_DOWN;
-                _UNGET_KEY(3);
+                POP(3);
                 return TRUE;
                 // ^[[C -- KEY_RIGHT
             case 'C':
                 key_code = KEY_RIGHT;
-                _UNGET_KEY(3);
+                POP(3);
                 return TRUE;
                 // ^[[D -- KEY_LEFT
             case 'D':
                 key_code = KEY_LEFT;
-                _UNGET_KEY(3);
+                POP(3);
                 return TRUE;
             case '1':
             case '4':
             case '5':
             case '6':
-                switch (keystroke[3]) {
+                switch (SYM[3]) {
                 case '~':
-                    switch (keystroke[2]) {
+                    switch (SYM[2]) {
                         // ^[[1~ -- KEY_HOME
                     case '1':
                         key_code = KEY_HOME;
-                        _FLSH_KEY();
+                        FLUSH();
                         return TRUE;
                         // ^[[4~ -- KEY_END
                     case '4':
                         key_code = KEY_END;
-                        _FLSH_KEY();
+                        FLUSH();
                         return TRUE;
                         // ^[[5~ -- KEY_PPAGE
                     case '5':
                         key_code = KEY_PPAGE;
-                        _FLSH_KEY();
+                        FLUSH();
                         return TRUE;
                         // ^[[6~ -- KEY_NPAGE
                     case '6':
                         key_code = KEY_NPAGE;
-                        _FLSH_KEY();
+                        FLUSH();
                         return TRUE;
                     }
                 default:
@@ -395,16 +398,16 @@ PDC_check_key(void)
                 break;
             }
         case 'O':
-            switch (keystroke[2]) {
+            switch (SYM[2]) {
                 // ^[OF -- KEY_END
             case 'F':
                 key_code = KEY_END;
-                _UNGET_KEY(3);
+                POP(3);
                 return TRUE;
                 // ^[OH -- KEY_HOME
             case 'H':
                 key_code = KEY_HOME;
-                _UNGET_KEY(3);
+                POP(3);
                 return TRUE;
             default:
                 break;
@@ -415,8 +418,8 @@ PDC_check_key(void)
     default:
         break;
     }
-    key_code = keystroke[0];
-    _UNGET_KEY(1);
+    key_code = SYM[0];
+    POP(1);
     return TRUE;
 #endif                          // ENABLE_KEYPAD
 }
@@ -435,7 +438,7 @@ PDC_flushinp(void)
     cyg_io_get_config(handle, CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH, NULL,
                       NULL);
 #ifdef ENABLE_KEYPAD
-    _FLSH_KEY();
+    FLUSH();
 #endif
 }
 
diff --git a/packages/services/memalloc/common/current/ChangeLog b/packages/services/memalloc/common/current/ChangeLog
--- a/packages/services/memalloc/common/current/ChangeLog
+++ b/packages/services/memalloc/common/current/ChangeLog
@@ -1,3 +1,15 @@
+2012-06-07  Bernard Fouché <bernard.fouche@kuantic.com>
+
+	* include/memjoin.inl: Fix compiler warning about variable that
+	is set but never referenced when CYG_ASSERT isn't used.
+
+2012-03-06  Grant Edwards <grant.b.edwards@gmail.com>
+
+	* src/malloc.cxx (free):
+	* src/kapi.cxx (cyg_mempool_var_free, cyg_mempool_fix_free): Fix
+	compiler warnings about variables that are set but never
+	referenced. [ Bugzilla 1001511 ]
+
 2009-09-01  Bart Veer  <bartv@ecoscentric.com>
 
 	* src/heapgen.tcl (tcl_path): use the makefile's HOST instead of
diff --git a/packages/services/memalloc/common/current/include/memjoin.inl b/packages/services/memalloc/common/current/include/memjoin.inl
--- a/packages/services/memalloc/common/current/include/memjoin.inl
+++ b/packages/services/memalloc/common/current/include/memjoin.inl
@@ -149,7 +149,7 @@ Cyg_Mempool_Joined<T>::~Cyg_Mempool_Join
     CYG_REPORT_FUNCTION();
     CYG_REPORT_FUNCARGVOID();
 
-    cyg_bool freestat;
+    cyg_bool freestat CYGBLD_ATTRIB_UNUSED;
     
     freestat = free( (cyg_uint8 *)pools, poolcount * sizeof(struct pooldesc) );
     CYG_ASSERT( freestat, "free failed!");
diff --git a/packages/services/memalloc/common/current/src/kapi.cxx b/packages/services/memalloc/common/current/src/kapi.cxx
--- a/packages/services/memalloc/common/current/src/kapi.cxx
+++ b/packages/services/memalloc/common/current/src/kapi.cxx
@@ -166,7 +166,7 @@ externC void *cyg_mempool_var_try_alloc(
 /* Frees memory back into variable size pool. */
 externC void cyg_mempool_var_free(cyg_handle_t varpool, void *p) __THROW
 {
-    cyg_bool b;
+    cyg_bool b CYGBLD_ATTRIB_UNUSED;
     b = ((Cyg_Mempool_Variable *)varpool)->free((cyg_uint8 *)p, 0);
     CYG_ASSERT( b, "Bad free");
 }
@@ -267,7 +267,7 @@ externC void *cyg_mempool_fix_try_alloc(
 /* Frees memory back into fixed size pool. */
 externC void cyg_mempool_fix_free(cyg_handle_t fixpool, void *p) __THROW
 {
-    cyg_bool b;
+    cyg_bool b CYGBLD_ATTRIB_UNUSED;
     b = ((Cyg_Mempool_Fixed *)fixpool)->free((cyg_uint8 *)p);
     CYG_ASSERT( b, "Bad free");
 }
diff --git a/packages/services/memalloc/common/current/src/malloc.cxx b/packages/services/memalloc/common/current/src/malloc.cxx
--- a/packages/services/memalloc/common/current/src/malloc.cxx
+++ b/packages/services/memalloc/common/current/src/malloc.cxx
@@ -155,7 +155,7 @@ malloc( size_t size )
 void
 free( void *ptr )
 {
-    cyg_bool freeret;
+    cyg_bool freeret CYGBLD_ATTRIB_UNUSED;
 
     CYG_REPORT_FUNCNAME( "free");
     
diff --git a/packages/services/objloader/current/ChangeLog b/packages/services/objloader/current/ChangeLog
--- a/packages/services/objloader/current/ChangeLog
+++ b/packages/services/objloader/current/ChangeLog
@@ -1,3 +1,8 @@
+2011-06-14  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* src/objelf.c:cyg_ldr_relocate_section(): Conditional block did
+	shadow the return of error code. Fixed.
+
 2010-03-03  Stanislav Karpenko  <s.o.karpenko@gmail.com>
 
 	* include/objelf.h: Add missed entry to CYG_LDR_TABLE_KAPI_MUTEX
diff --git a/packages/services/objloader/current/src/objelf.c b/packages/services/objloader/current/src/objelf.c
--- a/packages/services/objloader/current/src/objelf.c
+++ b/packages/services/objloader/current/src/objelf.c
@@ -369,8 +369,8 @@ cyg_ldr_relocate_section(PELF_OBJECT p, 
 #if CYGPKG_SERVICES_OBJLOADER_DEBUG_LEVEL > 1
             diag_printf("Error while relocating symbol: %s\n",
                         p_strtab + p_symtab[sym_index].st_name);
+#endif
             return -1;
-#endif
         }    
     }