# HG changeset patch
# User gthomas
# Date 1050509061 0
# Node ID 83ca3aef4a9297eb6235e36ea7bc06c7963f9e52
# Parent  cf8d8ca2ed1dcc1e8a273f190908815978509d17
Adjust configuration for MPC852T platforms

diff --git a/packages/hal/powerpc/adder/current/ChangeLog b/packages/hal/powerpc/adder/current/ChangeLog
--- a/packages/hal/powerpc/adder/current/ChangeLog
+++ b/packages/hal/powerpc/adder/current/ChangeLog
@@ -1,3 +1,8 @@
+2003-04-16  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/hal_aux.c (hal_platform_init): Set up GPIO bits according
+	to platform type.
+
 2003-03-31  Gary Thomas  <gary@mlbassoc.com>
 
 	* cdl/hal_powerpc_adder.cdl: Enable use of SCC3 on AdderII.
diff --git a/packages/hal/powerpc/adder/current/src/hal_aux.c b/packages/hal/powerpc/adder/current/src/hal_aux.c
--- a/packages/hal/powerpc/adder/current/src/hal_aux.c
+++ b/packages/hal/powerpc/adder/current/src/hal_aux.c
@@ -86,9 +86,17 @@ hal_platform_init(void)
     eppc->cpmi_cicr &= ~0xFF0000;  // Routing bits
     eppc->cpmi_cicr |= 0x240000;   // SCC2, SCC3 on "normal" bit positions
 
+#if defined(CYGHWR_HAL_POWERPC_ADDER_I)
     eppc->pip_pbpar &= ~0x0000400E;   // PB29..30 AS GPIO
     eppc->pip_pbdir |=  0x0000400E;
     eppc->pip_pbdat  =  0x00004000;
+#endif
+
+#if defined(CYGHWR_HAL_POWERPC_ADDER_II)  
+    eppc->pip_pbpar &= ~0x00000007;   // PB29..31 AS GPIO for LEDS
+    eppc->pip_pbdir |=  0x00000007;
+    eppc->pip_pbdat |=  0x00000007;
+#endif
 
     hal_if_init();
 
diff --git a/packages/hal/powerpc/mpc8xx/current/ChangeLog b/packages/hal/powerpc/mpc8xx/current/ChangeLog
--- a/packages/hal/powerpc/mpc8xx/current/ChangeLog
+++ b/packages/hal/powerpc/mpc8xx/current/ChangeLog
@@ -1,3 +1,7 @@
+2003-04-16  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/var_misc.c (hal_variant_init): Errata setup for MPC852T
+
 2003-03-23  Gary Thomas  <gary@mlbassoc.com>
 
 	* src/var_intr.c: 
diff --git a/packages/hal/powerpc/mpc8xx/current/src/var_misc.c b/packages/hal/powerpc/mpc8xx/current/src/var_misc.c
--- a/packages/hal/powerpc/mpc8xx/current/src/var_misc.c
+++ b/packages/hal/powerpc/mpc8xx/current/src/var_misc.c
@@ -56,6 +56,7 @@
 
 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
 #include <cyg/hal/ppc_regs.h>
+#include <cyg/hal/quicc/ppc8xx.h>
 #include <cyg/infra/cyg_type.h>         // types
 #include <cyg/infra/diag.h>             // diag_printf
 
@@ -65,6 +66,9 @@
 void
 hal_variant_init(void)
 {
+#if defined(CYGHWR_HAL_POWERPC_MPC8XX_852T)
+    volatile EPPC *eppc = (volatile EPPC *)eppc_base();
+#endif
     // Disable serialization
     {
         cyg_uint32 ictrl;
@@ -73,6 +77,19 @@ hal_variant_init(void)
         CYGARC_MTSPR (ICTRL, ictrl);
     }
 
+#if defined(CYGHWR_HAL_POWERPC_MPC8XX_852T)
+    // Special settings - according to manual errata
+    eppc->pio_papar &= ~0xffffffff;   // PA manatory settings
+    eppc->pio_padir |=  0xffffffff;
+
+    eppc->pip_pbpar &= ~0x0003ff07;   // PB29..31 AS GPIO
+    eppc->pip_pbdir |=  0x0003ff07;
+    eppc->pip_pbdat  =  0x00010007;
+    
+    eppc->pio_pcpar &= ~0xffffffff;   // PC manatory settings
+    eppc->pio_pcdir |=  0xffffffff;
+#endif
+
 #ifndef CYGSEM_HAL_USE_ROM_MONITOR
     // Reset CPM
     _mpc8xx_reset_cpm();