# HG changeset patch
# User asl
# Date 1164128083 0
# Node ID 8f44705956b20ed12162323c3b03dda08985a5a2
# Parent  6d4c075d293909827ff8c3720e1c5b7958b5985b
 * cdl/flash_intel_28fxxx.cdl, include/flash_28fxxx_parts.inl:
        Add Intel 28F128K3, 28F128P30 and 28F128J3 parts.

diff --git a/packages/devs/flash/intel/28fxxx/current/ChangeLog b/packages/devs/flash/intel/28fxxx/current/ChangeLog
--- a/packages/devs/flash/intel/28fxxx/current/ChangeLog
+++ b/packages/devs/flash/intel/28fxxx/current/ChangeLog
@@ -1,3 +1,8 @@
+2006-11-21  Alexander Neundorf <alexander.neundorf@jenoptik.com>
+
+	* cdl/flash_intel_28fxxx.cdl, include/flash_28fxxx_parts.inl:
+	Add Intel 28F128K3, 28F128P30 and 28F128J3 parts.
+
 2006-11-17  Alexander Neundorf <alexander.neundorf@jenoptik.com>
 
 	* cdl/flash_intel_28fxxx.cdl, include/flash_28fxxx.inl: 
diff --git a/packages/devs/flash/intel/28fxxx/current/cdl/flash_intel_28fxxx.cdl b/packages/devs/flash/intel/28fxxx/current/cdl/flash_intel_28fxxx.cdl
--- a/packages/devs/flash/intel/28fxxx/current/cdl/flash_intel_28fxxx.cdl
+++ b/packages/devs/flash/intel/28fxxx/current/cdl/flash_intel_28fxxx.cdl
@@ -139,6 +139,40 @@ cdl_package CYGPKG_DEVS_FLASH_INTEL_28FX
             part in the family."
     }
 
+    cdl_option CYGHWR_DEVS_FLASH_INTEL_28F128K3 {
+        display       "Intel 28F128K3 flash memory support"
+        default_value 0
+        implements    CYGHWR_IO_FLASH_BLOCK_LOCKING
+        implements    CYGINT_DEVS_FLASH_INTEL_VARIANTS
+        description   "
+            When this option is enabled, the Intel flash driver will be
+            able to recognize and handle the 28F128K3
+            part in the family."
+    }
+
+   cdl_option CYGHWR_DEVS_FLASH_INTEL_28F128P30 {
+        display       "Intel 28F128P30 flash memory support"
+        default_value 0
+        implements    CYGHWR_IO_FLASH_BLOCK_LOCKING
+        implements    CYGINT_DEVS_FLASH_INTEL_VARIANTS
+        implements    CYGHWR_DEVS_FLASH_INTEL_BUFFERED_WRITES
+        description   "
+            When this option is enabled, the Intel flash driver will be
+            able to recognize and handle the 28F128P30
+            part in the family."
+    }
+
+    cdl_option CYGHWR_DEVS_FLASH_INTEL_28F128J3 {
+        display       "Intel 28F128J3 flash memory support"
+        default_value 0
+        implements    CYGHWR_IO_FLASH_BLOCK_LOCKING
+        implements    CYGINT_DEVS_FLASH_INTEL_VARIANTS
+        description   "
+            When this option is enabled, the Intel flash driver will be
+            able to recognize and handle the 28F128J3
+            part in the family."
+    }
+
     cdl_option CYGHWR_DEVS_FLASH_INTEL_28F800B5 {
         display       "Intel 28F800B5 flash memory support"
         default_value 0
diff --git a/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx_parts.inl b/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx_parts.inl
--- a/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx_parts.inl
+++ b/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx_parts.inl
@@ -194,6 +194,48 @@
     },
 #endif
 	
+#ifdef CYGHWR_DEVS_FLASH_INTEL_28F128K3
+    {   
+        device_id  : FLASHWORD(0x8802),
+        block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
+        block_count: 128,
+        device_size: 0x1000000 * CYGNUM_FLASH_INTERLEAVE,
+        base_mask  : ~(0x1000000 * CYGNUM_FLASH_INTERLEAVE - 1),
+        locking    : true,
+        buffered_w : true,
+        bootblock  : false,
+        banked     : false
+    },
+#endif
+
+#ifdef CYGHWR_DEVS_FLASH_INTEL_28F128P30
+    {   
+        device_id  : FLASHWORD(0x8818),
+        block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
+        block_count: 128,
+        device_size: 0x1000000 * CYGNUM_FLASH_INTERLEAVE,
+        base_mask  : ~(0x1000000 * CYGNUM_FLASH_INTERLEAVE - 1),
+        locking    : true,
+        buffered_w : true,
+        bootblock  : false,
+        banked     : false
+    },
+#endif
+
+#ifdef CYGHWR_DEVS_FLASH_INTEL_28F128J3
+    {   
+        device_id  : FLASHWORD(0x18),
+        block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
+        block_count: 128,
+        device_size: 0x1000000 * CYGNUM_FLASH_INTERLEAVE,
+        base_mask  : ~(0x1000000 * CYGNUM_FLASH_INTERLEAVE - 1),
+        locking    : true,
+        buffered_w : true,
+        bootblock  : false,
+        banked     : false
+    },
+#endif
+
 #ifdef CYGHWR_DEVS_FLASH_INTEL_28F160S5
     {   // 28F160S5
         device_id  : FLASHWORD(0x00d0),