# HG changeset patch
# User vae
# Date 1352037116 0
# Node ID be10f73f67e24232d820c0d213ad8ef9ba04fe5c
# Parent  ea482849d62076b56c3dfca0af00e93917860791
Recognize 256 Bytes space for virtual vectors in sram. Recognize 256 Bytes space for virtual vectors in sram.

diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog b/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog
@@ -1,3 +1,12 @@
+2012-11-04  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
+	* twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi:
+	Recognize 256 Bytes space for virtual vectors in sram.
+
+	* twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
+	Add settings for Kinetis internal flash.  [Bugzilla 1001561]
+
 2012-09-28  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl
@@ -9,7 +18,7 @@ 2012-09-28  Ilija Kocho  <ilijak@siva.co
 	* twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
 	* twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h
 	* twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi
-	* twr_k70f120m/current/src/twr_k70f120m_misc.c
+	* twr_k70f120m/current/src/twr_k70f120m_misc.c:
 	Synchronized with Kinetis variant changes to SDRAM controller support.
 	Memory layouts adapted to separate data and code cacing partitions.
 	                                            [Bugzilla 1001606]
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl b/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl
@@ -62,6 +62,10 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T
     requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 70 }
     requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME == "1M0" }
     requires      { CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 }
+    requires      { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies
+                    CYGNUM_DEVS_KINETIS_FLASH_BLOCK_SIZE == 0x1000 }
+    requires      { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies
+                    CYGNUM_DEVS_KINETIS_FLASH_LONGWORD_SIZE == 8 }
 
     implements    CYGINT_IO_SERIAL_FREESCALE_UART2
 
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
@@ -16,7 +16,7 @@ MEMORY
 SECTIONS
 {
     SECTIONS_BEGIN
-    USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA)
+    USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA)
     SECTION_sram (sram, 0x20000000, LMA_EQ_VMA)
     SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LMA_EQ_VMA)
     SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA)
diff --git a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
+++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
@@ -16,7 +16,7 @@ MEMORY
 SECTIONS
 {
     SECTIONS_BEGIN
-    SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA)
     SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LMA_EQ_VMA)
     SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA)
     SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA)
@@ -36,6 +36,5 @@ SECTIONS
 
 hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
 hal_virtual_vector_table = hal_vsr_table + 128*4;
-//hal_startup_stack = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE + CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE;
 hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;