# HG changeset patch
# User jlarmour
# Date 1056436359 0
# Node ID c27fc1b75136ea18dcb856545c5a4ae120db2c3c
# Parent  9d0f5c9517ddc0095a2135d709aa1cae7c68a160
	* src/at91_misc.c (hal_hardware_init): Make sure the AIC internal
	priority level stack is flushed.
	(hal_IRQ_handler): Calculate active interrupt by dummy read from
	the IVR, which has the side-effect of updating ISR with the
	current interrupt source number.
	(hal_interrupt_acknowledge): Write to ICCR is not needed, as
	interrupt deassertion is taken care of by read of IVR in
	hal_IRQ_handler.

diff --git a/packages/hal/arm/at91/var/current/ChangeLog b/packages/hal/arm/at91/var/current/ChangeLog
--- a/packages/hal/arm/at91/var/current/ChangeLog
+++ b/packages/hal/arm/at91/var/current/ChangeLog
@@ -1,3 +1,14 @@
+2003-06-04  Daniel Néri  <daniel.neri@sigicom.se>
+
+	* src/at91_misc.c (hal_hardware_init): Make sure the AIC internal
+	priority level stack is flushed.
+	(hal_IRQ_handler): Calculate active interrupt by dummy read from
+	the IVR, which has the side-effect of updating ISR with the
+	current interrupt source number.
+	(hal_interrupt_acknowledge): Write to ICCR is not needed, as
+	interrupt deassertion is taken care of by read of IVR in
+	hal_IRQ_handler.
+
 2003-05-27  Daniel Néri  <daniel.neri@sigicom.se>
 
 	* include/var_io.h: Add missing USART register defines.
diff --git a/packages/hal/arm/at91/var/current/src/at91_misc.c b/packages/hal/arm/at91/var/current/src/at91_misc.c
--- a/packages/hal/arm/at91/var/current/src/at91_misc.c
+++ b/packages/hal/arm/at91/var/current/src/at91_misc.c
@@ -159,14 +159,17 @@ void hal_delay_us(cyg_int32 usecs)
 
 void hal_hardware_init(void)
 {
+    unsigned i;
+
     // Set up eCos/ROM interfaces
     hal_if_init();
 
     // Reset all interrupts
     HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IDCR, 0xFFFFFFFF);  
 
-    // Make sure interrupt controller is happy
-    HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_EOI, 0xFFFFFFFF);  
+    // Flush internal priority level stack
+    for (i = 0; i < 8; ++i)
+        HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_EOI, 0xFFFFFFFF);
 }
 
 // -------------------------------------------------------------------------
@@ -176,16 +179,12 @@ void hal_hardware_init(void)
 int hal_IRQ_handler(void)
 {
     cyg_uint32 irq_num;
-    cyg_uint32 ipr, imr;
+    cyg_uint32 ivr;
     
-//    HAL_READ_UINT32(AT91_AIC+AT91_AIC_ISR, irq_num);
+    // Calculate active interrupt (updates ISR)
+    HAL_READ_UINT32(AT91_AIC+AT91_AIC_IVR, ivr);
 
-    HAL_READ_UINT32(AT91_AIC+AT91_AIC_IPR, ipr);        
-    HAL_READ_UINT32(AT91_AIC+AT91_AIC_IMR, imr);        
-
-    ipr &= imr;
-
-    HAL_LSBIT_INDEX( irq_num, ipr );
+    HAL_READ_UINT32(AT91_AIC+AT91_AIC_ISR, irq_num);
     
     return irq_num;
 }
@@ -215,9 +214,6 @@ void hal_interrupt_acknowledge(int vecto
     CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
                vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
 
-    HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_ICCR, (1<<vector));
-
-    // FIXME - This isn't 100% correct
     HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_EOI, 0xFFFFFFFF);  
 }