Mercurial > nand-ecoscentric
changeset 3266:068fbe2304f1
Separate data and code caches, as well as text indentation suggested by Jifl. Fixes to cache and SDRAM CDL and functions Improved SDRAM controller support due to better manufacturer documentation: Configurable pad control. [Bugzilla 1001606]
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--- a/packages/hal/cortexm/kinetis/var/current/ChangeLog +++ b/packages/hal/cortexm/kinetis/var/current/ChangeLog @@ -1,3 +1,18 @@ +2012-09-28 Ilija Kocho <ilijak@siva.com.mk> + + * var/current/cdl/hal_cortexm_kinetis.cdl + * var/current/cdl/kinetis_clocking.cdl + * var/current/doc/kinetis.sgml + * var/current/include/hal_cache.h + * var/current/include/var_io_ddrmc.h + * var/current/include/var_io_lmem.h + * var/current/src/kinetis_ddram.c + * var/current/src/kinetis_misc.c + Separate data and code caches, as well as text indentation suggested by Jifl. + Fixes to cache and SDRAM CDL and functions Improved SDRAM controller + support due to better manufacturer documentation: Configurable pad control. + [Bugzilla 1001606] + 2012-08-01 Ilija Kocho <ilijak@siva.com.mk> * include/var_io.h, src/kinetis_misc.c: Add functions and macros
--- a/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl +++ b/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl @@ -73,8 +73,8 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { } cdl_component CYGHWR_HAL_CORTEXM_KINETIS { - display "Kinetis part" - flavor data + display "Kinetis part" + flavor data calculated { "MK" . CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM . (CYGHWR_HAL_CORTEXM_KINETIS_FPU ? "F" : "D") . (CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM ? "X" : "N") . @@ -101,7 +101,7 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FPU { display "Floating Point Unit option" flavor bool - default_value 0 + default_value 0 description "Select whether the chip has Floating Point Unit." } @@ -124,16 +124,16 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { cdl_option CYGHWR_HAL_CORTEXM_KINETIS_REV { display "Kinetis revision" - flavor data - legal_values 1 2 + flavor data + legal_values { 1 2 } default_value 1 description "Revision" } } cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS { - display "CPU exception priority level bits" - flavor data + display "CPU exception priority level bits" + flavor data default_value 4 description " This option defines the number of bits used to encode the @@ -142,15 +142,15 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { } cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING { - display "Clocking" - flavor data + display "Clocking" + flavor data no_define - calculated CYGHWR_HAL_CORTEXM_KINETIS_MCG + calculated CYGHWR_HAL_CORTEXM_KINETIS_MCG description "Configure system clock and subsystem clocking." cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP { - display "System frequency clock setpoint" - flavor data + display "System frequency clock setpoint" + flavor data legal_values 32768 to 220000000 default_value { CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP ? CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP : 96000000 } @@ -158,13 +158,13 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { } cdl_option CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP { - display "Auxiliary clock frequency setpoint" - flavor data - active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 + display "Auxiliary clock frequency setpoint" + flavor data + active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 legal_values 32768 to 220000000 default_value { CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP ? - CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP : 96000000 } - description "Desired auxiliary clock frequency" + CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP : 96000000 } + description "Desired auxiliary clock frequency" } script kinetis_clocking.cdl @@ -173,7 +173,7 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY { display "Clock interrupt ISR priority" flavor data - calculated CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP + calculated CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP description "Set clock ISR priority. Default setting is lowest priority." } @@ -204,39 +204,36 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { } cdl_option CYG_HAL_STARTUP_VAR { - display "By variant" + display "By variant" flavor data - parent CYG_HAL_STARTUP_ENV - default_value { - (CYG_HAL_STARTUP_PLF) && (CYG_HAL_STARTUP_PLF!="ByVariant") ? - "ByPlatform" : "ROM" } + parent CYG_HAL_STARTUP_ENV + default_value { (CYG_HAL_STARTUP_PLF) && (CYG_HAL_STARTUP_PLF!="ByVariant") ? + "ByPlatform" : "ROM" } legal_values { "ROM" "SRAM" } - active_if ((!CYG_HAL_STARTUP_PLF) || (CYG_HAL_STARTUP_PLF=="ByVariant")) + active_if ((!CYG_HAL_STARTUP_PLF) || (CYG_HAL_STARTUP_PLF=="ByVariant")) description " - 'ROM' startup builds a stand-alone application which will - be placed into flash. SRAM startup builds application - intended for loading in on-chip SRAM by means of JTAG/SWD. - Note: Variant Startup Type can be overriden/overloaded by - Platform Startup Type." + 'ROM' startup builds a stand-alone application which will + be placed into flash. SRAM startup builds application + intended for loading in on-chip SRAM by means of JTAG/SWD. + Note: Variant Startup Type can be overriden/overloaded by + Platform Startup Type." } - cdl_component CYG_HAL_STARTUP { - display "Startup type calculator" - flavor data - parent CYG_HAL_STARTUP_ENV - calculated { - (CYG_HAL_STARTUP_PLF && (CYG_HAL_STARTUP_PLF!="ByVariant")) ? - CYG_HAL_STARTUP_PLF : CYG_HAL_STARTUP_VAR - } - no_define - define -file system.h CYG_HAL_STARTUP - description " + cdl_component CYG_HAL_STARTUP { + display "Startup type calculator" + flavor data + parent CYG_HAL_STARTUP_ENV + calculated { (CYG_HAL_STARTUP_PLF && (CYG_HAL_STARTUP_PLF!="ByVariant")) ? + CYG_HAL_STARTUP_PLF : CYG_HAL_STARTUP_VAR} + no_define + define -file system.h CYG_HAL_STARTUP + description " Startup type defines what type of application shall be built. Startup type can be defined by variant (CYG_HAL_STARTUP_VAR) or platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF is defined and not equal to 'ByVariant' then it shall override CYG_HAL_STARTUP_VAR." - } + } cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_CONF { display "FlexNVM configuration" @@ -250,19 +247,19 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { cdl_component CYGHWR_HAL_CORTEXM_KINETIS_EEE { display "Enhanced EEPROM (EEE)" - flavor bool; + flavor bool; cdl_option CYGHWR_HAL_KINETIS_EEE_SIZE { - display "EEE Size \[Bytes\]" - flavor data - legal_values { 32 64 128 256 512 1024 2048 4096 } + display "EEE Size \[Bytes\]" + flavor data + legal_values { 32 64 128 256 512 1024 2048 4096 } default_value 4096 } cdl_component CYGHWR_HAL_KINETIS_EEE_SPLIT { - display "EEE Split ratio" + display "EEE Split ratio" flavor data - legal_values { 0 2 4 8 } + legal_values { 0 2 4 8 } default_value 0 description " Enhanced EEPROM is split in two partitions that are @@ -367,7 +364,7 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED { display "Unified on chip SRAM region" - flavor bool + flavor bool default_value { 1 } description " Kinetis have two equal SRAM banks SRAM_L and SRAM_U that @@ -472,141 +469,147 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { } cdl_option CYGHWR_HAL_KINETIS_FLEXNVM_FLASH_SIZE { - display "Kinetis on chip FLASH size" + display "Kinetis on chip FlexNVM FLASH size" flavor data calculated { (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB - CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB)* 0x400 } } - cdl_option CYGHWR_HAL_KINETIS_FLEXNVM_FLEXRAM_SIZE { - display "Kinetis on chip FlexRAM size" + cdl_option CYGHWR_HAL_KINETIS_FLEXNVM_FLEXRAM_SIZE { + display "Kinetis on chip FlexRAM size" + flavor data + active_if { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM & + !CYGHWR_HAL_CORTEXM_KINETIS_EEE } + calculated { 4096 } + } + } + + cdl_interface CYGINT_HAL_CACHE { + display "Platform has cache" + flavor bool + } + + cdl_interface CYGINT_HAL_HAS_NONCACHEABLE { + display "Platform has non-cacheable regions" + flavor bool + } + + cdl_component CYGPKG_HAL_KINETIS_CACHE { + display "Cache memory" + flavor bool + + default_value CYGINT_HAL_CACHE + active_if (CYGINT_HAL_CACHE) + + cdl_component CYGHWR_HAL_NON_CACHABLE { + display "Non cacheable RAM memory regions" + flavor data + active_if CYGINT_HAL_HAS_NONCACHEABLE + legal_values { "\".sram\"" "\".noncache\"" } + default_value { "\".noncache\"" } + description " + Non cacheable memory sections may be usful for storage that + is unsuitable for caching, such as sharing buffers between + the CPU and other bus masters such as DMA, ENET, etc. + The \".sram\" section is located in the internal SRAM, + which is is always present and never cached. + Additionaly, as an option, a partition of external memory: + DDRAM or FlexRAM, if one is present, can be configured + non-cachable and accommodate \".noncache\" section." + + cdl_option CYGHWR_HAL_ENET_TCD_SECTION { + display "Ethernet buffer descriptor memory section" flavor data - active_if { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM & - !CYGHWR_HAL_CORTEXM_KINETIS_EEE } - calculated { 4096 } + legal_values { "\".sram\"" "\".noncache\"" } + default_value { "\".sram\"" } + + description "Ethernet is a bus master so buffers/buffer + descriptos must reside in non-cacheable memory" } - cdl_interface CYGINT_HAL_CACHE { - display "Platform has cache" - flavor bool + cdl_option CYGHWR_HAL_ENET_BUF_SECTION { + display "Ethernet buffer memory section" + flavor data + legal_values { "\".sram\"" "\".noncache\"" } + default_value { "\".noncache\"" } + + description "Ethernet is a bus master so buffers/buffer + descriptos must reside in non-cacheable memory" } - cdl_interface CYGINT_HAL_HAS_NONCACHEABLE { - display "Platform has non-cacheable regions" - flavor bool + cdl_option CYGHWR_HAL_EDMA_TCD_SECTION { + display "eDMA transfer control descriptor memory section" + flavor data + legal_values { "\".sram\"" "\".noncache\"" } + default_value { "\".sram\"" } + + description "eDMA is a bus master so buffers/buffer + descriptos must reside in non-cacheable memory" + } + + cdl_option CYGHWR_HAL_EDMA_BUF_SECTION { + display "eDMA buffer memory section" + flavor data + legal_values { "\".sram\"" "\".noncache\"" } + default_value { "\".noncache\"" } + + description "eDMA is a bus master so buffers/buffer + descriptos must reside in non-cacheable memory" } } - - cdl_component CYGPKG_HAL_KINETIS_CACHE { - display "Cache memory" - flavor bool - - default_value CYGINT_HAL_CACHE - active_if (CYGINT_HAL_CACHE) + } - cdl_component CYGHWR_HAL_NON_CACHABLE { - display "Non cacheable RAM memory regions" - flavor data - active_if CYGINT_HAL_HAS_NONCACHEABLE - legal_values { "\".sram\"" "\".noncache\"" } - default_value { "\".noncache\"" } - description " - Non cacheable memory sections may be used as shared memory - between CPU and other bus masters such as DMA, ENET, etc." + cdl_interface CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS { + display "Platform uses FlexBus" + flavor bool + description " + This interface will be implemented if the specific + controller being used provides FlexBus and if FlexBus is + used on target hardware" + } - cdl_option CYGHWR_HAL_ENET_TCD_SECTION { - display "Ethernet buffer descriptor memory section" - flavor data - legal_values { "\".sram\"" "\".noncache\"" } - default_value { "\".sram\"" } + cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS { + display "FlexBus" + flavor bool + active_if CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS + default_value CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS + description "FlexBus provides access for external memory." - description "Ethernet is a bus master so buffers/buffer - descriptos must reside in non-cacheable memory" - } + for { set ::chipsel 0 } { $::chipsel < 6 } { incr ::chipsel } { - cdl_option CYGHWR_HAL_ENET_BUF_SECTION { - display "Ethernet buffer memory section" - flavor data - legal_values { "\".sram\"" "\".noncache\"" } - default_value { "\".noncache\"" } - - description "Ethernet is a bus master so buffers/buffer - descriptos must reside in non-cacheable memory" - } + cdl_interface CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] { + display "Platform uses Chip select [set ::chipsel]" + flavor bool + description " + This interface will be implemented if the specific + controller being used provides chip select [set ::chipsel], and if + that chip select is used on target hardware." + } - cdl_option CYGHWR_HAL_EDMA_TCD_SECTION { - display "eDMA transfer control descriptor memory section" - flavor data - legal_values { "\".sram\"" "\".noncache\"" } - default_value { "\".sram\"" } + cdl_component CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel] { + display "Chip select [set ::chipsel]" + flavor bool + active_if CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] + default_value CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] + description " + This option includes initialization data for + chip select [set ::chipsel]." - description "eDMA is a bus master so buffers/buffer - descriptos must reside in non-cacheable memory" - } - - cdl_option CYGHWR_HAL_EDMA_BUF_SECTION { - display "eDMA buffer memory section" - flavor data - legal_values { "\".sram\"" "\".noncache\"" } - default_value { "\".noncache\"" } - - description "eDMA is a bus master so buffers/buffer - descriptos must reside in non-cacheable memory" + cdl_option CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PS { + display "Port size (encoded)" + flavor data + calculated ( \ + CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 32 ? 0 : \ + CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 8 ? 1 : \ + CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 16 ? 2 : 3) } } } - - cdl_interface CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS { - display "Platform uses FlexBus" - flavor bool - description " - This interface will be implemented if the specific - controller being used provides FlexBus and if FlexBus is - used on target hardware" - } - - cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS { - display "FlexBus" - flavor bool - active_if CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS - default_value CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS - description "FlexBus provides access for external memory." - - for { set ::chipsel 0 } { $::chipsel < 6 } { incr ::chipsel } { + } - cdl_interface CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] { - display "Platform uses Chip select [set ::chipsel]" - flavor bool - description " - This interface will be implemented if the specific - controller being used provides chip select [set ::chipsel], and if - that chip select is used on target hardware." - } - - cdl_component CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel] { - display "Chip select [set ::chipsel]" - flavor bool - active_if CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] - default_value CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] - description " - This option includes initialization data for - chip select [set ::chipsel]." - - cdl_option CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PS { - display "Port size (encoded)" - flavor data - calculated ( \ - CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 32 ? 0 : \ - CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 8 ? 1 : \ - CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 16 ? 2 : 3) - } - } - } - } - - cdl_component CYGHWR_HAL_KINETIS_FLASH_CONF { + cdl_component CYGHWR_HAL_KINETIS_FLASH_CONF { display "Flash configuration field" - flavor none + flavor none no_define active_if { CYG_HAL_STARTUP == "ROM" } @@ -664,104 +667,226 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { } cdl_interface CYGINT_HAL_CORTEXM_KINETIS_DDRAM { - display "Platform uses SDRAM" + display "Platform uses DDRAM" flavor bool description " - This interface will be implemented if the specific - controller being used provides FlexBus and if FlexBus is - used on target hardware" + This interface will be implemented if the specific + controller being used provides FlexBus and if FlexBus is + used on target hardware" } cdl_component CYGPKG_HAL_CORTEXM_KINETIS_DDRMC { - display "SDRAM" + display "DDRAM" flavor bool active_if CYGINT_HAL_CORTEXM_KINETIS_DDRAM default_value CYGINT_HAL_CORTEXM_KINETIS_DDRAM - description "SDRAM external RAM." + description "DDRAM on Kinetis is mirrored at several address ranges. + Each mirror has its own caching options that may include: + non-cachable, write-through and write-back. + By eCos configuration, DDRAM is partitioned in two partitions: + Cachable and Non-Cachable. + Cachable partition is intended for general purpose main memory, + while non-cachable partition is convenient for sharing + buffers with other bus masters such as Ethernet controller, + DMA, etc." - requires CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 - compile kinetis_ddram.c + requires CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 + compile kinetis_ddram.c - cdl_option CYGHWR_HAL_KINETIS_DDR_CACHE_TYPE { - display "DDR cache type" + cdl_component CYGHWR_HAL_KINETIS_DDR_CACHED_MIRROR { + display "Cached DDRAM mirror base" flavor data - calculated CYGSEM_HAL_DCACHE_STARTUP_MODE + no_define + legal_values { 0x70000000 0x80000000 } + default_value { 0x70000000 } + description "According to Kinetis Reference Manual rev. 2, + the DDRAM mirror mapped at 0x80000000 (able only for write-thru caching) + is not accesible by ENET, SDH and some other bus masters, and that the mirror + at 0x70000000 (able for copy-back caching) is accessible by them. + The practical tests prove that it is the opposite, (actually as it should be). + Until this discrepancy is removed, this option selects the default (non)cached + mirror and provides the user with possibilty for manual override. + Note: The behavior may change in future. + " } - cdl_option CYGHWR_HAL_KINETIS_DDR_BASE { - display "Cacheable DDRAM base address" - flavor data - default_value 0x70000000 + cdl_option CYGHWR_HAL_KINETIS_DDR_NON_NON_CACHED_MIRROR { + display "Non-cached DDRAM mirror base" + flavor data + no_define + calculated { CYGHWR_HAL_KINETIS_DDR_CACHED_MIRROR == 0x70000000 ? + 0x80000000 : 0x70000000 } } - cdl_option CYGHWR_HAL_KINETIS_DDR_SIZE_MIB { - display "DDRAM size \[MiB\]" - flavor data + cdl_component CYGHWR_HAL_KINETIS_DDR_SIZE_MIB { + display "DDRAM size \[MiB\]" + flavor data default_value 128 + + cdl_option CYGHWR_HAL_KINETIS_DDR_SIZE { + display "DDRAM size \[Bytes\]" + flavor data + calculated { CYGHWR_HAL_KINETIS_DDR_SIZE_MIB * (1024 * 1024) * 0x1 } + } } - cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB { - display "Non-cacheable DDRAM size \[MiB\]" - requires { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB <= - CYGHWR_HAL_KINETIS_DDR_SIZE_MIB } - flavor data + cdl_component CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB { + display "Non-cacheable DDRAM partition \[MiB\]" + requires { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB <= + CYGHWR_HAL_KINETIS_DDR_SIZE_MIB } + flavor data - implements CYGINT_HAL_HAS_NONCACHEABLE + implements CYGINT_HAL_HAS_NONCACHEABLE + + legal_values { 1 to (CYGHWR_HAL_KINETIS_DDR_SIZE_MIB - 8) } + + default_value 8 - default_value 16 - } + description " + Non-cachable DDRAM partition, intended for sharing + buffers with other bus masters such as Ethernet controller, + DMA, etc." - cdl_option CYGHWR_HAL_KINETIS_DDR_SIZE { - display "DDRAM size \[MiB\]" - flavor data - calculated { CYGHWR_HAL_KINETIS_DDR_SIZE_MIB * (1024 * 1024) * 0x1 } + cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE { + display "Non-cacheable DDRAM size \[Bytes\]" + flavor data + calculated { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB + * (1024 * 1024) * 0x1 } + } + + cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE { + display "Non-cacheable DDRAM base address" + flavor data + + calculated { CYGHWR_HAL_KINETIS_DDR_NON_NON_CACHED_MIRROR + + CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE + + CYGHWR_HAL_KINETIS_DDR_CODE_SIZE } + } } - cdl_option CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE_MIB { - display "Cacheable DDRAM size \[MiB\]" - flavor data - calculated { CYGHWR_HAL_KINETIS_DDR_SIZE_MIB - - CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB} + cdl_component CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB { + display "DDRAM code partition \[MiB\]" + requires { CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB <= + CYGHWR_HAL_KINETIS_DDR_SIZE_MIB } + flavor data + + legal_values { 1 to (CYGHWR_HAL_KINETIS_DDR_SIZE_MIB - 8) } + + default_value 8 + + description " + DDRAM code partition" + + cdl_option CYGHWR_HAL_KINETIS_DDR_CODE_SIZE { + display "DDRAM code partition size \[Bytes\]" + flavor data + calculated { CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB + * (1024 * 1024) * 0x1 } + } + + cdl_option CYGHWR_HAL_KINETIS_DDR_CODE_BASE { + display "DDRAM code partition base address" + flavor data + + calculated { 0x08000000 } + } } - cdl_option CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE { - display "Cacheable DDRAM size \[Bytes\]" - flavor data - calculated { (CYGHWR_HAL_KINETIS_DDR_SIZE - - CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE) * 0x1 } - } + cdl_component CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE_MIB { + display "Cacheable DDRAM partition \[MiB\]" + flavor data + requires { CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE_MIB >= 8 } + calculated { CYGHWR_HAL_KINETIS_DDR_SIZE_MIB - + CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB - + CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB } + + description "Cachable DDRAM partition - for general use as main memory." - cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE { - display "Non-cacheable DDRAM base address" - flavor data + cdl_option CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE { + display "Cacheable DDRAM size \[Bytes\]" + flavor data + calculated { (CYGHWR_HAL_KINETIS_DDR_SIZE - + CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE - + CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) * 0x1 } + } - calculated { 0x80000000 + CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE } - } + cdl_option CYGHWR_HAL_KINETIS_DDR_CACHED_BASE { + display "Cacheable DDRAM base address" + flavor data + calculated { CYGHWR_HAL_KINETIS_DDR_CACHED_MIRROR + + CYGHWR_HAL_KINETIS_DDR_CODE_SIZE } + } - cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE { - display "Non-cacheable DDRAM size \[Bytes\]" - flavor data - calculated { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB - * (1024 * 1024) * 0x1 } + cdl_option CYGHWR_HAL_KINETIS_DDR_CACHE_TYPE { + display "DDRAM cache type" + flavor data + calculated CYGSEM_HAL_DCACHE_STARTUP_MODE + description "DDRAM cache type is determined by general cache setting" + } } cdl_option CYGHWR_HAL_DDR_SYNC_MODE { - display "Synchronous mode" - flavor bool - requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" } + display "Use synchronous mode" + flavor bool + requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" } default_value { 1 } } cdl_option CYGHWR_HAL_KINETIS_SIM_MCR_DDRBUS { - display "DDR bus configuration" - flavor data - legal_values 0 1 2 3 6 + display "DDRAM bus configuration" + flavor data + legal_values 0 1 2 3 6 default_value 6 description " DDRAM configuration: 0 - LPDDR Half Strength, 1 - LPDDR Full Strength, 2 - DDR2 Half Strength, 3 - DDR1, 6 - DDR2 Full Strength" } + + cdl_component CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL { + display "Pad control" + flavor data + + calculated { + (CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_ODT << 24) | + CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_SPARE_DLY_CTRL | + 0x00000200 + } + + cdl_option CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_ODT { + display "On Die Termination" + flavor data + legal_values { 0 1 2 3 } + default_value 1 + + description "On Die Termination \[Ohm\]: 0 - Off, 1 - 75, + 2 - 150, 3 - 50" + } + + cdl_option CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_SPARE_DLY_CTRL { + display "Delay chains in spare logic" + flavor data + legal_values { 0 1 2 3 } + default_value 3 + + description "Delay chains in spare logic: 0 - No buffer, 1 - 4 buffers, + 2 - 7 buffers, 11 - 10 buffers" + } + } + } + + cdl_option CYGNUM_HAL_KINETIS_MEM_SEGMENTS { + display "RAM memory segments" + flavor data + no_define + active_if is_active(CYGBLD_REDBOOT_MAX_MEM_SEGMENTS) + requires { CYGBLD_REDBOOT_MAX_MEM_SEGMENTS >= CYGNUM_HAL_KINETIS_MEM_SEGMENTS } + + calculated { + ((CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED ? 1 : 2) + + (CYGPKG_HAL_CORTEXM_KINETIS_DDRMC ? 2 : 0) + + (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE ? 1 : 0)) + } } for { set ::channel 0 } { $::channel < 6 } { incr ::channel } { @@ -786,8 +911,8 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { } cdl_interface CYGINT_HAL_DMA { - display "Platform uses DMA" - flavor bool + display "Platform uses DMA" + flavor bool description " This interface will be implemented if the specific controller being used provides DMA and if DMA is @@ -795,26 +920,26 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { } cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR { - display "Variant IRQ priority defaults" + display "Variant IRQ priority defaults" no_define - flavor none - parent CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME + flavor none + parent CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME description " Interrupt priorities defined by Kinetis variant" script kinetis_irq_scheme.cdl } cdl_component CYGPKG_HAL_CORTEXM_KINETIS_OPTIONS { - display "Build options" - flavor none + display "Build options" + flavor none no_define description " Package specific build options including control over compiler flags used only in building this package." cdl_option CYGPKG_HAL_CORTEXM_KINETIS_CFLAGS_ADD { - display "Additional compiler flags" - flavor data + display "Additional compiler flags" + flavor data no_define default_value { "" } description " @@ -824,8 +949,8 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { } cdl_option CYGPKG_HAL_CORTEXM_KINETIS_CFLAGS_REMOVE { - display "Suppressed compiler flags" - flavor data + display "Suppressed compiler flags" + flavor data no_define default_value { "" } description "
--- a/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl +++ b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl @@ -822,6 +822,7 @@ } cdl_interface CYGINT_HAL_CORTEXM_KINETIS_RTC { + display "System uses Real Time Clock" } cdl_component CYGHWR_HAL_CORTEXM_KINETIS_RTC {
--- a/packages/hal/cortexm/kinetis/var/current/doc/kinetis.sgml +++ b/packages/hal/cortexm/kinetis/var/current/doc/kinetis.sgml @@ -78,7 +78,7 @@ controller naming scheme (see respective Freescale Kinetis product brief(s) and reference manual(s)). The Kinetis part builder <literal>CYGHWR_HAL_CORTEXM_KINETIS</literal>, respects this naming scheme and enables the user to interactively configure eCos for the desired part by selecting - the requested part's name segments. + the requested part name segments. Based on user input, the CDL computes the part-specific eCos configuration. This includes calculation of on-chip FLASH and SRAM layout as well as the activation/deactivation of options such as FPU and Ethernet. @@ -230,15 +230,18 @@ <refsect3 id="kinetis-var-memory-cache"><title>Cache</title> <para> Kinetis members with operating frequencies of 120 MHz and 150 MHz are equipped with cache memory. - Due to the Harvard architecture, there are two unified cache memories connected to code - - <emphasis>PC</emphasis> and system - <emphasis>PS</emphasis> buses respectively. One of the - issues with caching is operation with bus masters such as DMA, Ethernet controller, etc. - In order to keep shared data such - as buffers and transfer descriptors synchronous, a part of cached data may have to be flushed - and/or invalidated. In some cases, an alternative can be the usage of non-cacheable memory - regions. <literal>CYGHWR_HAL_NON_CACHABLE</literal> provides for the configuration of non-cacheable - memory. If some bus masters have provision for non-cacheable memory, such configuration options - can be parented by <literal>CYGHWR_HAL_NON_CACHABLE</literal>. + Due to the Harvard architecture, there are two cache memories connected to code + - <emphasis>PC</emphasis> and system - <emphasis>PS</emphasis> buses respectively. + Although both modules can cache both instructions and data (unified caches), with the provided + memory they act as instruction (<emphasis>PC</emphasis>) and data (<emphasis>PS</emphasis>) caches. + </para> + <para> + A common caching issue is sharing memory resources with bus masters such as DMA, Ethernet controller, etc. + In order to keep shared data such as buffers and transfer control descriptors consistent, + cached data have to be flushed and/or invalidated. An alternative approach, used here is usage of + non-cachable memory for shared data. <literal>CYGHWR_HAL_NON_CACHABLE</literal> provides for + the configuration of non-cachable memory. If some bus masters have provision for non-cache able memory, + such configuration options can be parenthed by <literal>CYGHWR_HAL_NON_CACHABLE</literal>. </para> </refsect3> </refsect2>
--- a/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h +++ b/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h @@ -64,58 +64,91 @@ #ifdef CYGINT_HAL_CACHE // Data cache -#define HAL_DCACHE_SIZE (8192*2) // Size of data cache in bytes -#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line -#define HAL_DCACHE_WAYS (2*2) // Associativity of the cache +#define HAL_DCACHE_SIZE 8192 // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line +#define HAL_DCACHE_WAYS 2 // Associativity of the cache // Instruction cache -#define HAL_ICACHE_SIZE (8192*2) // Size of cache in bytes -#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line -#define HAL_ICACHE_WAYS (2*2) // Associativity of the cache +#define HAL_ICACHE_SIZE 8192 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line +#define HAL_ICACHE_WAYS 2 // Associativity of the cache #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) +#include <cyg/hal/var_io.h> #include <cyg/hal/var_io_lmem.h> //----------------------------------------------------------------------------- // Global control of data cache // Enable the data cache -#define HAL_DCACHE_ENABLE() \ - HAL_CORTEXM_KINETIS_CACHE_PS_ENABLE(); \ - HAL_CORTEXM_KINETIS_CACHE_PC_ENABLE() +#define HAL_DCACHE_ENABLE() HAL_CORTEXM_KINETIS_CACHE_PS_ENABLE() // Disable the data cache -#define HAL_DCACHE_DISABLE() \ - HAL_CORTEXM_KINETIS_CACHE_PS_DISABLE(); \ - HAL_CORTEXM_KINETIS_CACHE_PC_DISABLE() +#define HAL_DCACHE_DISABLE() HAL_CORTEXM_KINETIS_CACHE_PS_DISABLE() // Invalidate the entire cache -#define HAL_DCACHE_INVALIDATE_ALL() \ - HAL_CORTEXM_KINETIS_CACHE_PS_INVALL(); \ - HAL_CORTEXM_KINETIS_CACHE_PC_INVALL() +#define HAL_DCACHE_INVALIDATE_ALL() HAL_CORTEXM_KINETIS_CACHE_PS_INVALL() // Synchronize the contents of the cache with memory. -#define HAL_DCACHE_SYNC() \ - HAL_CORTEXM_KINETIS_CACHE_PS_SYNC(); \ - HAL_CORTEXM_KINETIS_CACHE_PC_SYNC() +#define HAL_DCACHE_SYNC() HAL_CORTEXM_KINETIS_CACHE_PS_SYNC() // Purge contents of data cache -#define HAL_DCACHE_PURGE_ALL() \ - HAL_CORTEXM_KINETIS_CACHE_PS_CLEAR(); \ - HAL_CORTEXM_KINETIS_CACHE_PC_CLEAR() +#define HAL_DCACHE_PURGE_ALL() HAL_CORTEXM_KINETIS_CACHE_PS_CLEAR() // Query the state of the data cache (does not affect the caching) -#define HAL_DCACHE_IS_ENABLED(_state_) \ - CYG_MACRO_START \ - (_state_) = (HAL_CORTEXM_KINETIS_CACHE_PS_IS_ENABLED() && \ - HAL_CORTEXM_KINETIS_CACHE_PC_IS_ENABLED()); \ +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = HAL_CORTEXM_KINETIS_CACHE_PS_IS_ENABLED(); \ CYG_MACRO_END // Invalidate cache lines in the given range without writing to memory. -#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \ - HAL_CORTEXM_KINETIS_CACHE_PS_INVALIDATE(_base_, _size_); \ +#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \ + HAL_CORTEXM_KINETIS_CACHE_PS_INVALIDATE(_base_, _size_) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() HAL_CORTEXM_KINETIS_CACHE_PC_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() HAL_CORTEXM_KINETIS_CACHE_PC_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() HAL_CORTEXM_KINETIS_CACHE_PC_INVALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() HAL_CORTEXM_KINETIS_CACHE_PC_SYNC() + +// Purge contents of data cache +#define HAL_ICACHE_PURGE_ALL() HAL_CORTEXM_KINETIS_CACHE_PC_CLEAR() + +// Query the state of the instruction cache (does not affect the caching) +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = HAL_CORTEXM_KINETIS_CACHE_PC_IS_ENABLED(); \ + CYG_MACRO_END + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) \ HAL_CORTEXM_KINETIS_CACHE_PC_INVALIDATE(_base_, _size_) #else // CYGINT_HAL_CACHE @@ -146,9 +179,9 @@ #define HAL_DCACHE_PURGE_ALL() // Query the state of the data cache (does not affect the caching) -#define HAL_DCACHE_IS_ENABLED(_state_) \ - CYG_MACRO_START \ - (_state_) = 0; \ +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ CYG_MACRO_END // Set the data cache refill burst size @@ -198,25 +231,27 @@ // Allocate and zero the cache lines associated with the given range. //#define HAL_DCACHE_ZERO( _base_ , _size_ ) -#endif // CYGINT_HAL_CACHE //----------------------------------------------------------------------------- // Global control of Instruction cache // Enable the instruction cache -#define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE() +#define HAL_ICACHE_ENABLE() // Disable the instruction cache -#define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE() +#define HAL_ICACHE_DISABLE() // Invalidate the entire cache -#define HAL_ICACHE_INVALIDATE_ALL() HAL_DCACHE_INVALIDATE_ALL() +#define HAL_ICACHE_INVALIDATE_ALL() // Synchronize the contents of the cache with memory. -#define HAL_ICACHE_SYNC() HAL_DCACHE_SYNC() +#define HAL_ICACHE_SYNC() // Query the state of the instruction cache (does not affect the caching) -#define HAL_ICACHE_IS_ENABLED(_state_) HAL_DCACHE_IS_ENABLED(_state_) +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END // Set the instruction cache refill burst size //#define HAL_ICACHE_BURST_SIZE(_size_) @@ -235,46 +270,9 @@ // Instruction cache line control // Invalidate cache lines in the given range without writing to memory. -#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) HAL_DCACHE_INVALIDATE( _base_ , _size_ ) - -//----------------------------------------------------------------------------- -// Global control of Instruction cache - -// Enable the instruction cache -#define HAL_UCACHE_ENABLE() HAL_DCACHE_ENABLE() - -// Disable the instruction cache -#define HAL_UCACHE_DISABLE() HAL_DCACHE_DISABLE() - -// Invalidate the entire cache -#define HAL_UCACHE_INVALIDATE_ALL() HAL_DCACHE_INVALIDATE_ALL() - -// Synchronize the contents of the cache with memory. -#define HAL_UCACHE_SYNC() HAL_DCACHE_SYNC() - -// Query the state of the instruction cache (does not affect the caching) -#define HAL_UCACHE_IS_ENABLED(_state_) HAL_DCACHE_IS_ENABLED(_state_) +#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) -// Set the instruction cache refill burst size -//#define HAL_UCACHE_BURST_SIZE(_size_) - -// Load the contents of the given address range into the instruction cache -// and then lock the cache so that it stays there. -//#define HAL_UCACHE_LOCK(_base_, _size_) - -// Undo a previous lock operation -//#define HAL_UCACHE_UNLOCK(_base_, _size_) +#endif // CYGINT_HAL_CACHE -// Unlock entire cache -//#define HAL_UCACHE_UNLOCK_ALL() - -//----------------------------------------------------------------------------- -// Instruction cache line control - -// Invalidate cache lines in the given range without writing to memory. -#define HAL_UCACHE_INVALIDATE( _base_ , _size_ ) HAL_DCACHE_INVALIDATE( _base_ , _size_ ) - +// End of hal_cache.h #endif // CYGONCE_HAL_CACHE_H - -//----------------------------------------------------------------------------- -// End of hal_cache.h
--- a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi @@ -32,14 +32,14 @@ SECTIONS SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) - USER_SECTION (code_sram, sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE (NOLOAD), LMA_EQ_VMA) - SECTION_data (ram, 0x20000400, FOLLOWING (.got)) + USER_SECTION (code_sram, sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA) + SECTION_data (ram, 0x20000000, FOLLOWING (.got)) SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data)) SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); SECTIONS_END } -hal_vsr_table = (0x20000000); +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); hal_virtual_vector_table = hal_vsr_table + 128*4; hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
--- a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi @@ -5,31 +5,31 @@ MEMORY { - sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE - sram_u : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + sram_u : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE } SECTIONS { SECTIONS_BEGIN - SECTION_rom_vectors (sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA) + SECTION_rom_vectors (sram_l, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA) SECTION_RELOCS (sram_l, ALIGN (0x8), LMA_EQ_VMA) SECTION_text (sram_l, ALIGN (0x8), LMA_EQ_VMA) SECTION_fini (sram_l, ALIGN (0x8), LMA_EQ_VMA) - SECTION_rodata (sram_l, ALIGN (0x8), LMA_EQ_VMA) - SECTION_rodata1 (sram_l, ALIGN (0x8), LMA_EQ_VMA) - SECTION_fixup (sram_l, ALIGN (0x8), LMA_EQ_VMA) - SECTION_gcc_except_table (sram_l, ALIGN (0x8), LMA_EQ_VMA) - SECTION_eh_frame (sram_l, ALIGN (0x8), LMA_EQ_VMA) - SECTION_got (sram_l, ALIGN (0x8), LMA_EQ_VMA) - SECTION_data (sram_u, 0x20000000 + 0x400, FOLLOWING (.got)) - SECTION_sram (sram_u, ALIGN (0x8), FOLLOWING (.data)) + SECTION_rodata (sram_u, 0x20000000, LMA_EQ_VMA) + SECTION_rodata1 (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram_u, ALIGN (0x8), LMA_EQ_VMA) SECTION_bss (sram_u, ALIGN (0x8), LMA_EQ_VMA) CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); SECTIONS_END } -hal_vsr_table = (0x20000000); +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); hal_virtual_vector_table = hal_vsr_table + 128*4; hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
--- a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi @@ -43,7 +43,7 @@ SECTIONS SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) - USER_SECTION (code_sram, sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE (NOLOAD), LMA_EQ_VMA) + USER_SECTION (code_sram, sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA) #ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE USER_SECTION(d_flash, flexnvm, 0x10000000 (NOLOAD), LMA_EQ_VMA) #endif @@ -55,13 +55,13 @@ SECTIONS #else USER_SECTION(flex_ram, flexram, 0x14000000 (NOLOAD), LMA_EQ_VMA) #endif - SECTION_data (ram, 0x20000400, FOLLOWING (.got)) + SECTION_data (ram, 0x20000000, FOLLOWING (.got)) SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data)) SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); SECTIONS_END } -hal_vsr_table = (0x20000000); +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); hal_virtual_vector_table = hal_vsr_table + 128*4; hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
--- a/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi @@ -5,31 +5,31 @@ MEMORY { - sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE - sram_u : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + sram_u : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE } SECTIONS { SECTIONS_BEGIN - SECTION_rom_vectors (sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA) + SECTION_rom_vectors (sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, LMA_EQ_VMA) SECTION_RELOCS (sram_l, ALIGN (0x8), LMA_EQ_VMA) SECTION_text (sram_l, ALIGN (0x8), LMA_EQ_VMA) SECTION_fini (sram_l, ALIGN (0x8), LMA_EQ_VMA) - SECTION_rodata (sram_l, ALIGN (0x8), LMA_EQ_VMA) - SECTION_rodata1 (sram_l, ALIGN (0x8), LMA_EQ_VMA) - SECTION_fixup (sram_l, ALIGN (0x8), LMA_EQ_VMA) - SECTION_gcc_except_table (sram_l, ALIGN (0x8), LMA_EQ_VMA) - SECTION_eh_frame (sram_l, ALIGN (0x8), LMA_EQ_VMA) - SECTION_got (sram_l, ALIGN (0x8), LMA_EQ_VMA) - SECTION_data (sram_u, 0x20000000 + 0x400, FOLLOWING (.got)) - SECTION_sram (sram_u, ALIGN (0x8), FOLLOWING (.data)) + SECTION_rodata (sram_u, 0x20000000 , LMA_EQ_VMA) + SECTION_rodata1 (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (sram_u, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram_u, ALIGN (0x8), LMA_EQ_VMA) SECTION_bss (sram_u, ALIGN (0x8), LMA_EQ_VMA) CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); SECTIONS_END } -hal_vsr_table = (0x20000000); +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); hal_virtual_vector_table = hal_vsr_table + 128*4; hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
--- a/packages/hal/cortexm/kinetis/var/current/include/var_io.h +++ b/packages/hal/cortexm/kinetis/var/current/include/var_io.h @@ -63,12 +63,8 @@ //--------------------------------------------------------------------------- // VTOR - Vector Table Offset Register #ifndef CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM -# ifdef CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED -# define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM (BIT_(29) - \ - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) -# else -# define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM BIT_(29) -# endif +#define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM (BIT_(29) - \ + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) #endif //============================================================================= @@ -147,7 +143,7 @@ typedef volatile struct cyghwr_hal_kinet cyg_uint8 atcvl; // MCG Auto Trim Compare Value Low Register #if CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 cyg_uint8 c7; // MCG Control 7 Register - cyg_uint8 c8; // MCG Control 8 Register + cyg_uint8 c8; // MCG Control 8 Register #endif #if CYGINT_HAL_CORTEXM_KINETIS_150 cyg_uint8 c10; // MCG Control 10 Register @@ -155,7 +151,7 @@ typedef volatile struct cyghwr_hal_kinet cyg_uint8 c11; // MCG Control 11 Register cyg_uint8 c12; // MCG Control 12 Register cyg_uint8 s2; // MCG Status 2 Register -#endif //CYGINT_HAL_CORTEXM_KINETIS_150 +#endif //CYGINT_HAL_CORTEXM_KINETIS_150 } cyghwr_hal_kinetis_mcg_t; #define CYGHWR_HAL_KINETIS_MCG_P ((cyghwr_hal_kinetis_mcg_t *)0x40064000) @@ -545,7 +541,7 @@ typedef volatile struct cyghwr_hal_kinet cyg_uint32 uidmh; // Unique Identification Register Mid-High cyg_uint32 uidml; // Unique Identification Register Mid Low cyg_uint32 uidl; // Unique Identification Register Low - + cyg_uint32 clkdiv3; // System Clock Divider Register 3 cyg_uint32 clkdiv4; // System Clock Divider Register 4 cyg_uint32 mcr; // Misc control register @@ -954,7 +950,7 @@ typedef volatile struct cyghwr_hal_kinet // The following encodes the control register and clock bit number // into 16 bit descriptor. -#define CYGHWR_HAL_CLOCK( __reg, __bit ) (((__reg-1)&0xF) + ((__bit<<8)&0x1F00)) +#define CYGHWR_HAL_CLOCK( __reg, __bit ) ((((__reg)-1)&0xF) + (((__bit)<<8)&0x1F00)) // Macros to extract encoded values. #define CYGHWR_HAL_CLOCK_REG( __desc ) ((__desc)&0xF) @@ -968,6 +964,67 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_CLOCK_ENABLE( __desc ) hal_clock_enable( __desc ) #define CYGHWR_HAL_CLOCK_DISABLE( __desc ) hal_clock_disable( __desc ) +//-------------------------------------------------------------------------- +// AXBS - Crossbar switch + +#define CYGHWR_HAL_KINETIS_AXBS_SLAVES_K 7 +#define CYGHWR_HAL_KINETIS_AXBS_MASTERS_K 8 + +typedef volatile struct cyghwr_hal_kinetis_axbs_s { + volatile struct cyghwr_hal_kinetis_axbs_slave_s { + cyg_uint32 prs; + cyg_uint32 res0[3]; + cyg_uint32 crs; + cyg_uint32 res1[59]; + } slave[8]; + volatile struct cyghwr_hal_kinetis_axbs_master_s { + cyg_uint32 res0[64]; + cyg_uint32 mgprc; + } master[8]; +} cyghwr_hal_kinetis_axbs_t; + +#define CYGHWR_HAL_KINETIS_AXBS_P ((cyghwr_hal_kinetis_axbs_t *) 0x40004000) + +// PRS Fields +#define CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(_master_) ((_master_) * 4) +#define CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(_master_) \ + (0x7 << CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(_master_)) + +#define CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_PRIO(_master_,_prs) \ + (((_prs) & CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(_master_)) >> \ + CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(_master_)) +// CRS Fields +#define CYGHWR_HAL_KINETIS_AXBS_CRS_PARK_M 0x7 + +#define CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_M 0x30 +#define CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_S 4 +#define CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL(_x_) (((_x_) << CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_S) & \ + CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_M) +#define CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_M 0x300 +#define CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_S 8 +#define CYGHWR_HAL_KINETIS_AXBS_CRS_ARB(_x_) (((_x_) << CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_S) & \ + CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_M) +#define CYGHWR_HAL_KINETIS_AXBS_CRS_HLP_M 0x40000000 +#define CYGHWR_HAL_KINETIS_AXBS_CRS_RO_M 0x80000000 + +#define CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB(_slave_i,_arb) \ +CYG_MACRO_START \ + cyg_uint32 regval; \ + cyghwr_hal_kinetis_axbs_t* _axbs_p = CYGHWR_HAL_KINETIS_AXBS_P; \ + regval = _axbs_p->slave[_slave_i].crs; \ + regval &= ~CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_M; \ + regval |= CYGHWR_HAL_KINETIS_AXBS_CRS_ARB(_arb); \ + _axbs_p->slave[_slave_i].crs = regval; \ +CYG_MACRO_END + +#define CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB_RR(_slave_i) \ + CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB((_slave_i), 1) + +#define CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB_FIX(_slave_i) \ + CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB((_slave_i), 0) + +// MGPCR Bit Fields +#define CYGHWR_HAL_KINETIS_AXBS_CRS_AXBS_MGPCR_AULB_M 0x7 //--------------------------------------------------------------------------- // PORT - Peripheral register structure @@ -1028,12 +1085,12 @@ enum { #define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_GPIO 1 #define CYGHWR_HAL_KINETIS_PIN(__port, __bit, __mux, __cnf) \ - ((CYGHWR_HAL_KINETIS_PORT##__port << 20) | (__bit << 27) \ - | CYGHWR_HAL_KINETIS_PORT_PCR_MUX(__mux) | __cnf) + ((CYGHWR_HAL_KINETIS_PORT##__port << 20) | ((__bit) << 27) \ + | CYGHWR_HAL_KINETIS_PORT_PCR_MUX(__mux) | (__cnf)) -#define CYGHWR_HAL_KINETIS_PIN_PORT(__pin) ((__pin >> 20) & 0x7) -#define CYGHWR_HAL_KINETIS_PIN_BIT(__pin) ((__pin >> 27 ) & 0x1f) -#define CYGHWR_HAL_KINETIS_PIN_FUNC(__pin) (__pin & 0x010f8777) +#define CYGHWR_HAL_KINETIS_PIN_PORT(__pin) (((__pin) >> 20) & 0x7) +#define CYGHWR_HAL_KINETIS_PIN_BIT(__pin) (((__pin) >> 27 ) & 0x1f) +#define CYGHWR_HAL_KINETIS_PIN_FUNC(__pin) ((__pin) & 0x010f8777) #define CYGHWR_HAL_KINETIS_PIN_NONE (0xffffffff) // GPCLR Bit Fields @@ -1105,7 +1162,7 @@ typedef volatile struct cyghwr_hal_kinet // LVDSC1 Bit Fields #define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV_M 0x3 #define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV(__val) \ - (__val & CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV_M) + ((__val) & CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV_M) #define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDRE_M 0x10 #define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDRE_S 4 #define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDIE_M 0x20 @@ -1117,7 +1174,7 @@ typedef volatile struct cyghwr_hal_kinet // LVDSC2 Bit Fields #define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV_M 0x3 #define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV(__val) \ - (__val & CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV_M) + ((__val) & CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV_M) #define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWIE_M 0x20 #define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWIE_S 5 #define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWACK_M 0x40 @@ -1163,13 +1220,13 @@ enum { }; #define CYGHWR_HAL_KINETIS_FMC_TAG(__way,__side) \ - (CYGHWR_HAL_KINETIS_FMC_BASE + 0x100 + __way*0x20 + __side*4) + (CYGHWR_HAL_KINETIS_FMC_BASE + 0x100 + (__way)*0x20 + (__side)*4) #define CYGHWR_HAL_KINETIS_FMC_DATA_U(__way,side) \ - (CYGHWR_HAL_KINETIS_FMC_BASE + 0x200 + --way*0x20 + __side*8) + (CYGHWR_HAL_KINETIS_FMC_BASE + 0x200 + (__way)*0x20 + (__side)*8) #define CYGHWR_HAL_KINETIS_FMC_DATA_L(__way,side) \ - (CYGHWR_HAL_KINETIS_FMC_BASE + 0x204 + --way*0x40 + __side*8) + (CYGHWR_HAL_KINETIS_FMC_BASE + 0x204 + (__way)*0x40 + (__side)*8) -#define CYGHWR_HAL_KINETIS_FMC_PFAPR_MPFD_M(__master) (1 << (__master + 16)) +#define CYGHWR_HAL_KINETIS_FMC_PFAPR_MPFD_M(__master) (1 << ((__master) + 16)) enum { CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_NO_ACCESS, CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_RO, @@ -1177,18 +1234,18 @@ enum { CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_RW }; #define CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP(__master, __access) \ - (__access <<(2 * __master)) + ((__access) <<(2 * (__master))) #define CYGHWR_HAL_KINETIS_FMC_PFBCR_RWSC_M (0xf0000000) -#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(__way) ((1 << __way) << 24) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(__way) ((1 << (__way)) << 24) #define CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_ALL \ CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W0) | \ CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W1) | \ CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W2) | \ CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W3) -#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(__way) ((1 << __way) << 20) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(__way) ((1 << (__way)) << 20) #define CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_ALL \ CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W0) | \ CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W1) | \ @@ -1205,7 +1262,7 @@ enum{ CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_IND_LRUW02ID3D }; #define CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC (__cache_repl_con) \ - (__cache_repl_con << 5) + ((__cache_repl_con) << 5) #define CYGHWR_HAL_KINETIS_FMC_PFBCR_BDCE (0x10) #define CYGHWR_HAL_KINETIS_FMC_PFBCR_BICE (0x08)
--- a/packages/hal/cortexm/kinetis/var/current/include/var_io_ddrmc.h +++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_ddrmc.h @@ -101,9 +101,9 @@ typedef volatile struct cyghwr_hal_kinet (CYGHWR_HAL_KINETIS_SIM_MCR_DDRSREN_M * 0 )) # endif -__externC void hal_cortexm_kinetis_ddrmc_init(const cyg_uint32 src[], cyg_uint32 num); +__externC void hal_cortexm_kinetis_ddrmc_init(const cyg_uint32 src[]); # define HAL_CORTEXM_KINETIS_DDRMC_INIT(__inidat) \ - hal_cortexm_kinetis_ddrmc_init(__inidat, ((sizeof(__inidat)/2)/sizeof(__inidat[0]))) + hal_cortexm_kinetis_ddrmc_init(__inidat) __externC void hal_cortexm_kinetis_ddrmc_diag(void); //-----------------------------------------------------------------------------
--- a/packages/hal/cortexm/kinetis/var/current/include/var_io_lmem.h +++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_lmem.h @@ -80,7 +80,7 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_M 0xFFC #define CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_S 2 #define CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR(_ca_) \ - (_ca_ << CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_S) + ((_ca_) << CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_S) #define CYGHWR_HAL_KINETIS_LMEM_CLCR_WSEL_M 0x4000 #define CYGHWR_HAL_KINETIS_LMEM_CLCR_TDSEL_M 0x10000 #define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCIVB_M 0x100000 @@ -88,7 +88,7 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCWAY_M 0x400000 #define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_S 24 #define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD(_cmd_) \ - (_cmd_ << CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_S) + ((_cmd_) << CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_S) #define CYGHWR_HAL_KINETIS_LMEM_CLCR_LADSEL_M 0x4000000 #define CYGHWR_HAL_KINETIS_LMEM_CLCR_LACC_M 0x8000000 @@ -97,7 +97,7 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_M 0xFFFFFFFC #define CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_S 2 #define CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR(_adr_) \ - (_adr_ << CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_S) + ((_adr_) << CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_S) // CCVR Bit Fields #define CYGHWR_HAL_KINETIS_LMEM_CCVR_DATA_M 0xFFFFFFFF @@ -106,24 +106,23 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_M 0x3 #define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION(_region_,_mask_) \ - (_mask_ << ((15 - _region_) * 2)) + ((_mask_) << ((15 - (_region_)) * 2)) #define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M 0 #define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WT_M 2 #define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WB_M 3 -#define CYGHWR_HAL_KINETIS_LMEM_R_FLASH_0000 0 -#define CYGHWR_HAL_KINETIS_LMEM_R_DRAM_0800 1 -#define CYGHWR_HAL_KINETIS_LMEM_R_FLEXNVM_1000 2 -#define CYGHWR_HAL_KINETIS_LMEM_R_FLEXBUS_1800 3 -#define CYGHWR_HAL_KINETIS_LMEM_R_SRAM_L 4 -#define CYGHWR_HAL_KINETIS_LMEM_R_SRAM_U 5 +#define CYGHWR_HAL_KINETIS_LMEM_FLASH_0000 0 +#define CYGHWR_HAL_KINETIS_LMEM_DRAM_0800 1 +#define CYGHWR_HAL_KINETIS_LMEM_FLEXNVM_1000 2 +#define CYGHWR_HAL_KINETIS_LMEM_FLEXBUS_1800 3 +#define CYGHWR_HAL_KINETIS_LMEM_SRAM_L 4 +#define CYGHWR_HAL_KINETIS_LMEM_SRAM_U 5 #define CYGHWR_HAL_KINETIS_LMEM_FLEXBUS_6000 6 #define CYGHWR_HAL_KINETIS_LMEM_DRAM_7000 7 #define CYGHWR_HAL_KINETIS_LMEM_DRAM_8000 8 #define CYGHWR_HAL_KINETIS_LMEM_FLEXBUS_9000 9 - #define HAL_CORTEXM_KINETIS_CACHE_PC_ENABLE() \ hal_cortexm_kinetis_cache_enable(CYGHWR_HAL_KINETIS_LMEM_PC_P) @@ -166,24 +165,49 @@ typedef volatile struct cyghwr_hal_kinet #define HAL_CORTEXM_KINETIS_CACHE_PC_INVALIDATE(_base, _size_) \ hal_cortexm_kinetis_cache_invalidate(CYGHWR_HAL_KINETIS_LMEM_PC_P, _base, _size_) +#if defined CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK && defined CYG_HAL_STARTUP_RAM + +#define CYGHWR_HAL_KINETIS_CACHE_WAIT(_lmem_p) \ +CYG_MACRO_START \ + cyg_uint32 prs_tmp, prs_save; \ + cyg_uint32 m0, m1; \ + cyghwr_hal_kinetis_axbs_t* _axbs_p = CYGHWR_HAL_KINETIS_AXBS_P; \ + prs_save = prs_tmp = _axbs_p->slave[5].prs; \ + m0 = CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_PRIO(0, prs_tmp); \ + m1 = CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_PRIO(1, prs_tmp); \ + if(m1 > m0) { \ + prs_tmp &= ~(CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(0) | \ + CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(1)); \ + prs_tmp |= (m0 << CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(1)) | m1; \ + _axbs_p->slave[5].prs = prs_tmp; \ + } \ + while((_lmem_p)->ccr & CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M); \ + _axbs_p->slave[5].prs = prs_save; \ +CYG_MACRO_END + +#else // CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK + +#define CYGHWR_HAL_KINETIS_CACHE_WAIT(_lmem_p) \ + while((_lmem_p)->ccr & CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M) + +#endif // CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK + __externC void inline hal_cortexm_kinetis_cache_enable(cyghwr_hal_kinetis_lmem_t* lmem_p) { - lmem_p->ccr = (CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M | - CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M | - CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M | - CYGHWR_HAL_KINETIS_LMEM_CCR_ENCACHE_M | - CYGHWR_HAL_KINETIS_LMEM_CCR_ENWRBUF_M - ); + lmem_p->ccr = ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_ENCACHE_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_ENWRBUF_M + ); + CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p); } __externC void inline hal_cortexm_kinetis_cache_disable(cyghwr_hal_kinetis_lmem_t* lmem_p) { - lmem_p->ccr = (CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M | - CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M | - CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M - ); + lmem_p->ccr = 0; } __externC void inline @@ -193,26 +217,29 @@ hal_cortexm_kinetis_cache_inval(cyghwr_h CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M | CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M ); + CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p); } __externC void inline hal_cortexm_kinetis_cache_sync(cyghwr_hal_kinetis_lmem_t* lmem_p) { lmem_p->ccr |= ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M | - CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M | - CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M - ); + CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M + ); + CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p); } __externC void inline hal_cortexm_kinetis_cache_clear(cyghwr_hal_kinetis_lmem_t* lmem_p) { lmem_p->ccr |= ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M | - CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M | - CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M | - CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M | - CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M - ); + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M + ); + CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p); } __externC bool inline @@ -227,20 +254,16 @@ hal_cortexm_kinetis_cache_invalidate(cyg cyg_uint8* addr_p, cyg_uint32 size) { size = (((cyg_uint32)addr_p & 0xf) + size)/HAL_DCACHE_LINE_SIZE + 1; + lmem_p->clcr = CYGHWR_HAL_KINETIS_LMEM_CLCR_LADSEL_M | + CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD(1); while(size--){ - lmem_p->csar = addr_p; - lmem_p->clcr = CYGHWR_HAL_KINETIS_LMEM_CLCR_LADSEL_M | - CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD(1) | - CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M; + lmem_p->csar = (cyg_uint8*)(((cyg_uint32) addr_p & 0xfffffffc) | + CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M); addr_p += HAL_DCACHE_LINE_SIZE; - while(lmem_p->clcr & CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M); + while(lmem_p->clcr & CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M); } } -# define HAL_CORTEXM_KINETIS_DDRMC_INIT(__inidat) \ - hal_cortexm_kinetis_ddrmc_init(__inidat, ((sizeof(__inidat)/2)/sizeof(__inidat[0]))) -__externC void hal_cortexm_kinetis_ddrmc_diag(void); - //----------------------------------------------------------------------------- -// end of var_io_ddrmc.h +// end of var_io_lmem.h #endif // CYGONCE_HAL_VAR_IO_LMEM_H
--- a/packages/hal/cortexm/kinetis/var/current/src/kinetis_ddram.c +++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_ddram.c @@ -64,18 +64,29 @@ #include <cyg/hal/hal_intr.h> // HAL header #include <cyg/hal/hal_if.h> // HAL header - - // DDRAM Controller #ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC + +// DDRAM controller register indices. +const cyg_uint8 const kinetis_ddr_reg_ix[] = { + 0, + 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 20, 21, 22, 23, + 25, 26, 27, 28, 29, 30, + 34, + 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, + 52, 53, 54, 55, 56, 57 +}; + // Initialize DDRAM controller. // inidat[] is an array of ordered pairs: (register-index, register-value). void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR -hal_cortexm_kinetis_ddrmc_init(const cyg_uint32 inidat[], cyg_uint32 num) +hal_cortexm_kinetis_ddrmc_init(const cyg_uint32 inidat[]) { cyghwr_hal_kinetis_ddrmc_t* ddrmc_p = CYGHWR_HAL_KINETIS_DDRMC_P; cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; volatile cyg_uint32* cr_p; + cyg_uint32 cr_ix; cyg_uint32 cr_i; cyg_uint32 regval; @@ -85,12 +96,12 @@ hal_cortexm_kinetis_ddrmc_init(const cyg sim_p->mcr = regval | CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP; ddrmc_p->rcr |= CYGHWR_HAL_KINETIS_DDRMC_RCR_RST_M; - ddrmc_p->pad_ctrl = 0x01030203; + ddrmc_p->pad_ctrl = CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL; cr_p = ddrmc_p->cr; - do { - cr_i = *inidat++; + for(cr_ix = 0; cr_ix < sizeof(kinetis_ddr_reg_ix); cr_ix++) { + cr_i = kinetis_ddr_reg_ix[cr_ix]; cr_p[cr_i] = *inidat++; - } while(--num); + }; __asm__ volatile ("nop\n"); ddrmc_p->cr[0] |= CYGHWR_HAL_KINETIS_DDRMC_CR00_START; while(!(ddrmc_p->cr[30] & CYGHWR_HAL_KINETIS_DDRMC_CR30_DRAM_INIT_CPL));
--- a/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c +++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c @@ -70,16 +70,7 @@ void sst25xx_freescale_dspi_reg(void); -#ifdef CYGPKG_HAL_KINETIS_CACHE -# if defined CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP || \ - defined CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP - -# define ENABLE_CACHE_ON_STARTUP - -# endif -#endif // defined CYGPKG_HAL_KINETIS_CACHE - -#ifdef CYG_HAL_STARTUP_ROM +#if defined CYG_HAL_STARTUP_ROM && !defined CYG_HAL_STARTUP_RAM //=========================================================================== // KINETIS FLASH configuration field @@ -107,13 +98,12 @@ hal_kinetis_flash_conf_p( void ) return &CYGHWR_HAL_KINETIS_FLASH_CONF_FIELD; } -#endif // CYG_HAL_STARTUP_ROM +#endif // defined CYG_HAL_STARTUP_ROM && !defined CYG_HAL_STARTUP_RAM //=== KINETIS FLASH security configuration END. ============================ #if defined CYGPKG_HAL_KINETIS_CACHE -# ifndef CYG_HAL_STARTUP_RAM // Function for demotion of caching memory regions static void hal_cortexm_kinetis_conf_cache_regions(cyghwr_hal_kinetis_lmem_t* lmem_p, @@ -134,9 +124,22 @@ hal_cortexm_kinetis_conf_cache_regions(c } lmem_p->rmr = regval; } -# endif // ndef CYG_HAL_STARTUP_RAM + +const cyg_uint32 cache_reg_modes_pc[] = { + (CYGHWR_HAL_KINETIS_LMEM_DRAM_7000 << 16) | + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M, -const cyg_uint32 cache_reg_modes[] = { + (CYGHWR_HAL_KINETIS_LMEM_DRAM_8000 << 16) | + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M +}; + +const cyg_uint32 cache_reg_modes_ps[] = { + (CYGHWR_HAL_KINETIS_LMEM_FLASH_0000 << 16) | + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M, + + (CYGHWR_HAL_KINETIS_LMEM_DRAM_0800 << 16) | + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M, + (CYGHWR_HAL_KINETIS_LMEM_DRAM_7000 << 16) | #if defined CYGSEM_HAL_DCACHE_STARTUP_MODE_WRITETHRU CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WT_M, @@ -158,21 +161,40 @@ const cyg_uint32 cache_reg_modes[] = { void hal_variant_init( void ) { +#if defined CYGPKG_HAL_KINETIS_CACHE +# if defined CYG_HAL_STARTUP_RAM + register CYG_INTERRUPT_STATE oldints; +# endif +#endif + hal_update_clock_var(); + #if defined CYGPKG_HAL_KINETIS_CACHE -# ifndef CYG_HAL_STARTUP_RAM +# if defined CYG_HAL_STARTUP_RAM + HAL_DISABLE_INTERRUPTS(oldints); + HAL_DCACHE_SYNC(); + HAL_DCACHE_DISABLE(); + HAL_DCACHE_PURGE_ALL(); + HAL_ICACHE_DISABLE(); + HAL_ICACHE_INVALIDATE_ALL(); +# endif // defined CYG_HAL_STARTUP_RAM hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PS_P, - sizeof(cache_reg_modes)/sizeof(cache_reg_modes[0]), - cache_reg_modes); + sizeof(cache_reg_modes_ps)/sizeof(cache_reg_modes_ps[0]), + cache_reg_modes_ps); hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PC_P, - sizeof(cache_reg_modes)/sizeof(cache_reg_modes[0]), - cache_reg_modes); + sizeof(cache_reg_modes_pc)/sizeof(cache_reg_modes_pc[0]), + cache_reg_modes_pc); +# if defined CYG_HAL_STARTUP_RAM + HAL_RESTORE_INTERRUPTS(oldints); # endif -# ifdef ENABLE_CACHE_ON_STARTUP - HAL_DCACHE_ENABLE(); +# ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP HAL_ICACHE_ENABLE(); # endif +# ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP + HAL_DCACHE_ENABLE(); +# endif #endif // defined CYGPKG_HAL_KINETIS_CACHE + #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT hal_if_init(); #endif @@ -259,22 +281,22 @@ void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTI hal_clock_enable(cyg_uint32 desc) { volatile cyg_uint32 *scgc_p; - + if(desc != CYGHWR_HAL_KINETIS_CLOCK_NONE) { scgc_p = &CYGHWR_HAL_KINETIS_SIM_P->scgc1 + CYGHWR_HAL_CLOCK_REG(desc); *scgc_p |= 1 << CYGHWR_HAL_CLOCK_BIT(desc); - } + } } void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR hal_clock_disable(cyg_uint32 desc) { volatile cyg_uint32 *scgc_p; - + if(desc != CYGHWR_HAL_KINETIS_CLOCK_NONE) { scgc_p = &CYGHWR_HAL_KINETIS_SIM_P->scgc1 + CYGHWR_HAL_CLOCK_REG(desc); *scgc_p &= ~(1 << CYGHWR_HAL_CLOCK_BIT(desc)); - } + } } //==========================================================================