Mercurial > nand-ecoscentric
changeset 3198:70cc85a5623a
New package -- Actel Smartfusion A2F200 EVAL board HAL. [Bugzilla 1001291]
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new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/ChangeLog @@ -0,0 +1,45 @@ +2011-01-18 Christophe Coutand <ecos@hotmail.co.uk> + + * cdl/hal_cortexm_a2f200_eval.cdl: + * doc/a2f200e.sgml + * src/a2f200_eval_misc.c: + * src/platform_i2c.c: + * host/memory-map.xml: + * host/softconsole_flash_init.txt: + * host/softconsole_sram_init.txt: + * include/plf_arch.h: + * include/plf_intr.h: + * include/plf_io.h: + * include/pkgconf/mlt_cortexm_a2f200_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_a2f200_eval_rom.h: + * include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.ldi: + * include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.h: + * include/pkgconf/mlt_cortexm_a2f200_eval_sram.ldi: + * include/pkgconf/mlt_cortexm_a2f200_eval_sram.h: + New package -- Actel Smartfusion A2F200 EVAL board HAL. + [Bugzilla 1001291] + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/cdl/hal_cortexm_a2f200_eval.cdl @@ -0,0 +1,328 @@ +##========================================================================== +## +## hal_cortexm_a2f200_eval.cdl +## +## Actel Smartfusion A2F200 EVAL platform HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): ccoutand +## Date: 2011-02-13 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_A2F200_EVAL { + display "Actel Smartfusion Development Board HAL" + doc ref/hal-cortexm-a2fxxx-a2f200-eval.html + parent CYGPKG_HAL_CORTEXM_A2FXXX + define_header hal_cortexm_a2f200_eval.h + include_dir cyg/hal + hardware + description " + The Actel Smartfusion HAL package provides the support needed to run + eCos on the Actel Smartfusion A2F200 EVAL board." + + compile a2f200_eval_misc.c platform_i2c.c + + requires { is_active(CYGPKG_DEVS_ETH_PHY) implies + (1 == CYGHWR_DEVS_ETH_PHY_DP8384X) } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_cortexm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_cortexm_a2fxxx.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_a2f200_eval.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M3\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Smartfusion A2F200 EVAL\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME { + display "Interrupt priority scheme" + flavor none + description "Consolidated interrupt priority scheme setting." + } + + cdl_option CYGNUM_DEVS_FLASH_SPI_AT25XXX_DEV0_MAP_ADDR { + display "Base address of the SPI flash device" + flavor data + default_value 0x10000000 + description " + Specifies the base address of the Atmel AT95DFxxx SPI flash." + } + + cdl_component CYG_HAL_STARTUP { + display "Architecture Startup type" + flavor data + legal_values { "SRAM" "ROM" } + calculated { CYG_HAL_PLF_STARTUP == "SRAM" ? "SRAM" : "ROM" } + description " + Mapping of CYG_HAL_PLF_STARTUP to CYG_HAL_STARTUP" + define -file system.h CYG_HAL_STARTUP + } + + cdl_component CYG_HAL_PLF_STARTUP { + display "Platform Startup type" + flavor data + default_value {"ROM"} + legal_values {"SRAM" "ROM" "ROM_SOFTCONSOLE"} + description " + When targeting the Smartfusion A2F200 EVAL board it is possible + to build the system for either SRAM bootstrap or ROM bootstrap. + Select 'SRAM' when building programs to load into SRAM using + on-board debug software such as RedBoot or eCos GDB stubs or via + a JTAG debugger. + Select 'ROM' when building a stand-alone application which will + be put into ROM. The 'ROM_SOFTCONSOLE' type allows programs to be + loaded (to 'ROM') and debug using the SoftConsole IDE." + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { (CYG_HAL_PLF_STARTUP == "SRAM" ) ? "cortexm_a2f200_eval_sram" : + (CYG_HAL_PLF_STARTUP == "ROM" ) ? "cortexm_a2f200_eval_rom" : + (CYG_HAL_PLF_STARTUP == "ROM_SOFTCONSOLE" ) ? "cortexm_a2f200_eval_rom_sc" : + "undefined" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" } + } + + } + + # Both UARTs 0 and 1 are available for diagnostic/debug use. + implements CYGINT_HAL_A2FXXX_UART0 + + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The Actel Smartfusion EVAL board has two serial ports. This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The Actel Smartfusion EVAL has two serial ports. This option + chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Console serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + console connection. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + GDB connection. + Note: this should match the value chosen for the console port if the + console and GDB port are the same." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + requires { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + requires { CYGNUM_REDBOOT_FLASH_BASE == 0x60000000 } + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary images" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to binary image formats suitable for ROM programming." + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } + } + + cdl_component CYGBLD_HAL_CORTEXM_A2FXXX_EVAL_GDB_STUBS { + display "Create StubROM SREC and binary files" + active_if CYGBLD_BUILD_COMMON_GDB_STUBS + no_define + calculated 1 + requires { CYG_HAL_STARTUP == "ROM" } + + make -priority 325 { + <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec $< $@ + } + make -priority 325 { + <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + + description "This component causes the ELF image generated by the + build process to be converted to S-Record and binary + files." + } + +}
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/doc/a2f200e.sgml @@ -0,0 +1,814 @@ +<!-- DOCTYPE reference PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- a2f200e.sgml --> +<!-- --> +<!-- Actel Smartfusion Board Support. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2011 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): ccoutand --> +<!-- Contact(s): --> +<!-- Date: 2011/06/04 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> +<part id="hal-cortexm-a2fxxx-a2f200-eval"><title>Actel Smartfusion Board Support</title> + + <!-- {{{ Actel Smartfusion Board Support --> + <chapter id="a2f200-eval-chapter"> + + <title>Actel Smartfusion Board Support</title> + + <!-- {{{ Overview --> + <refentry id="a2f200-over"> + + <refmeta> + <refentrytitle>Overview</refentrytitle> + </refmeta> + + <refnamediv> + <refname>Overview</refname> + <refpurpose>Actel Smartfusion Board Support</refpurpose> + </refnamediv> + + <refsect1 id="a2f200-eval-overview"><title>Overview</title> + + <para> + The Actel Smartfusion evaluation kit uses the A2F200 microcontroller from the + Actel smartfusion family. The SmartFusion devices are a mix of programmable + logic around a ARM cortex-M3 based processor. The SmartFusion has 3 variants: + A2F060, A2F200, A2F500. The main difference between parts are the amount of + RAM, FLASH as well as programmable logic. In addition, the A2F060 does not + include the Ethernet controller peripheral. + The A2F200 device includes 256KB of internal FLASH (also called Embedded + Non-volatile Memory, ENVM) and 64KB of internal SRAM. + The device has various peripherals such as UART, I2C, SPI, Ethernet MAC, ADC or + DAC as well as the FPGA fabric. + The kit features an OLED graphical display and UART0 is accessible via the + on-board USB to UART converter. The kit also includes a serial flash, the Atmel + AT25DF641 part (8MB memory). + The FPGA fabric uses a non-volatile technology thus removing the + need of additional flash memory for storing the FPGA programming matrix. + </para> + + <para> + The eCos port targets standalone ROM application. The eCos device drivers include + support for the I2C and SPI buses as well as UART and Ethernet Controller. No + device driver is currently available for the ADC/DAC or the In-Application + Programming feature that allows the application to re-program the FLASH or the + FPGA fabric. + The Smartfusion (A2Fxxx) HAL includes a timer test application and the A2F200 evaluation + board flash device package includes a test application for the SPI serial flash. + </para> + </refsect1> + <!-- }}} --> + + <!-- {{{ Tools --> + <refsect1 id="a2f200-eval-tools"><title>Tools</title> + + <para> + For compilation, the official eCos ARM toolchain is required (gcc version 4.3.2). + For debugging, while the board offers a JTAG interface, the HAL was developed using + the SoftConsole IDE supplied from Actel. SoftConsole is an Eclipse based IDE + installed along with the CodeSourcery ARM compiler / debugger. The ARM GDB and Sprite + utilities from CodeSourcery are used to debug the target. The target includes an on-board + debugger and is connected to the host via a USB cable. GDB interfaces the + on-board debugger through the Actel flashpro driver. Detailed example of a debugging + session is described later in this chapter. + </para> + + </refsect1> + <!-- }}} --> + </refentry> + + + <!-- {{{ HAL port --> + <refentry id="a2f200-eval-hal"> + <refmeta> + <refentrytitle>HAL and Device Drivers</refentrytitle> + </refmeta> + + <refnamediv> + <refname>HAL</refname> + <refpurpose>Actel HAL and Device Drivers</refpurpose> + </refnamediv> + + <!-- {{{ Clocking --> + <refsect1 id="a2f200-eval-hal-clock"><title>Clocking</title> + + <para> + The internal clock network of the Smarfusion devices includes a large amount of possible + configuration combination. The network has 3 different input clocks (CLKA, CLKB and CLKC), + each of them can be connected to a different clock source such as the main oscillator, the + RC oscillator, the FPGA fabric or the dedicated single-ended or differential IO. The clock + network has an internal PLL and 3 global output clocks (CLKGA, CLKGB and CLKGC). The cortex-M3, + digital and analog peripherals clocks are derived either from CLKGA or CLKGC through the + NGMUX. + Due to the large amount of configuration parameters, it is recommended to use the Actel MSS + configuration tool to setup the clock network and let the system boot handle the configuration. + However, the eCos HAL includes all the required options to setup the clock network. Note that + only a limited subset of combinations have been tested. + </para> + + </refsect1> + <!-- }}} --> + + <!-- {{{ SPI Bus --> + <refsect1 id="a2f200-eval-hal-spi"><title>SPI bus</title> + + <para> + The Actel AF2xxx microcontroller family has 2 SPI buses available. Each SPI bus has + a certain number of slave select line (called SPI_x_SSx) that are directly driven by + the SPI controller. + The first SPI bus has 4 slave select lines available (SPI_0_SS0 to SPI_0_SS3) while the + second bus has 8 of them (SPI_1_SS0 to SPI_1_SS7). In addition, the eCos SPI driver allows + using the GPIO of the microcontroller as slave select lines which is in some cases required. + In the rest of this chapter, the former case is called SPI controlled slave select while + the later is called GPIO controlled slave select + </para> + + <para> + NOTE: The SPI_x_SSx microcontroller dedicated pins can be used as GPIO, thus, it is possible + to use SPI_0_SS0 as slave select either in SPI or GPIO controlled mode. This is true for all + SPI_x_SSx pins. + </para> + + <para> + New SPI devices are instantiated using the following macro: + </para> + <programlisting width=80> + #include <filename class="headerfile"><cyg/io/spi.h></filename> + #include <filename class="headerfile"><cyg/io/spi_a2fxxx.h></filename> + + #define CYG_DEVS_SPI_CORTEXM_A2FXXX_DEVICE( \ + _name_, _bus_, _csnum_, _csgpio_, _proto_, _clpol_, \ + _clpha_, _brate_, _csup_dly_, _csdw_dly_, _trbt_dly_) + + + _name_ is the name of the SPI device. This will be used to + reference a data structure of type cyg_spi_device + which can be passed to the SPI driver API without + needing a cast. + _bus_ is the bus number to which this device is attached + (1 or 2). + _csgpio_ when set to false: + - the device slave select line is controlled by the + SPI controller. + when set to true: + - the device slave select line is a GPIO of the + processor controlled by the SPI driver. + _csnum_ when _csgpio_ is set to false : + - is the slave select line used for this device, + numbered from 0. + when _csgpio_ is set to true : + - is the GPIO number used to drive the device slave + select line. + _proto_ is the SPI bus protocol: + 0 -> Motorola SPI Mode (_clpol_ and _clpha_ are + valid in this mode) + 1 -> National Semiconductor MICROWIRE Mode + 2 -> Texas Instruments (TI) Synchronous Serial Mode + _clpol_ is the SPI bus clock polarity used by the device + (valid only for Motorola SPI Protocol). + _clpha_ is the SPI bus clock phase used by the device + (valid only for Motorola SPI Protocol). + _brate_ is the SPI bus clock baud rate used by the device, + measured in Hz. + _csup_dly_ is the minimum delay between slave select assert and + transfer start, measured in microseconds. + _csdw_dly_ is the minimum delay between transfer end and slave + select deassert, measured in microseconds. + _trbt_dly_ is the minimum delay between consecutive transfers. + </programlisting> + + <para> + NOTE: _csup_dly_ and _csdw_dly_ are only valid when GPIOs are configured to drive the + slave select line. When the SPI controller drives the slave select line itself, the user + has no control over the exact timing. + </para> + + <para> + The Actel Smartfusion board features a SPI serial flash (AT25DF641) attached + to the first SPI bus. The SPI flash is connected to the SPI_0_SS0 line, however, to suit + eCos SPI transaction, the line is configured as a general purpose IO and controlled by the + SPI driver. + </para> + + <para> + The following section describes how the SPI serial flash is declared. The code is located + in devs/fash/cortexm/a2fxxx/a2f200_eval/flash_a2f200_eval.c. The required includes are: + </para> + + <programlisting width=80> + #include <filename class="headerfile"><cyg/io/spi.h></filename> + #include <filename class="headerfile"><cyg/io/at25dfxxx.h></filename> + #include <filename class="headerfile"><cyg/io/spi_a2fxxx.h></filename> + </programlisting> + + <para> + The device is defined to be connected on SPI bus 1, using GPIO 19 for slave select. + The Motorola protocol (mode 0) is selected with a bus clock speed of 25MHz. + </para> + + <programlisting width=80> + CYG_DEVS_SPI_CORTEXM_A2FXXX_DEVICE ( + at25dfxxx_spi_device, 1, 19, true, A2FXXX_SPI_MOTOROLA, 0, 0, 25000000, 1, 1, 1 + ); + + _bus_ = 1 + _csgpio_ = true -> use GPIO + _csgpio_ = 19 -> GPIO19 also SPI_0_SS0 + _proto_ = Motorola Protocol + _clpol_ = 0 + _clpha_ = 0 + _brate_ = 25MHz + _csup_dly = 1us + _csdw_dly_ = 1us + _trbt_dly_ = 1us + </programlisting> + + <para> + From the default CDL, SPI bus 1 uses the DMA channel 0 for outbound and channel 1 for inbound + transfer. SPI bus 2 uses DMA channel 2 and 3 respectively. The DMA channel number are selected + with: + </para> + + <programlisting width=80> + CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS1_TX_DMA + CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS1_RX_DMA + and + CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS2_TX_DMA + CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS2_RX_DMA + </programlisting> + + </refsect1> + <!-- }}} --> + + <!-- {{{ I2C Bus --> + <refsect1 id="a2f200-eval-hal-i2c"><title>I2C bus</title> + + <para> + The Actel microcontroller family has 2 I2C buses available and the Smartfusion evaluation kit + feature an OLED display connected to the first I2C bus with address 0x3C. + The I2C driver is tested using the OLED display, however, the OLED driver is not part of the + eCos HAL. A new I2C bus is instantiated using the following macro: + </para> + + <programlisting width=80> + #define CYG_A2FXXX_I2C_BUS( \ + _name_, \ + _init_fn_, \ + _base_, \ + _base_bb_, \ + _periph_, \ + _isr_vec_, \ + _isr_pri_) \ + + _name_ is the name of the SPI device. + _init_fn_ is the I2C initialization function to be called by the C constructor. + _base_ is the base address of the I2C peripheral. + _base_bb_ is the Bit-Band base address of the I2C peripheral. + _periph_ is the peripheral bit identifier for reset/release operation. + _isr_vec_ is the peripheral interrupt vector number. + _isr_pri_ is the interrupt priority. + </programlisting> + + <para> + The following section describes how the I2C bus 0 is declared. The code is located in + hal/cortexm/a2fxxx/a2f200_eval/current/src/platform_i2c.c. The required includes are: + </para> + + <programlisting width=80> + #include <filename class="headerfile"><cyg/io/i2c.h></filename> + #include <filename class="headerfile"><cyg/io/i2c_a2fxxx.h></filename> + </programlisting> + + <para> + The first part declares the I2C bus 0 and the second part attached a I2C device with address + 0x3C to the bus. + </para> + + <programlisting width=80> + CYG_A2FXXX_I2C_BUS(hal_a2fxxx_i2c0_bus, + a2fxxx_i2c0_init, + CYGHWR_HAL_A2FXXX_I2C0, + CYGHWR_HAL_A2FXXX_I2C0_BB, + CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_I2C0, + CYGNUM_HAL_INTERRUPT_I2C0_0, + 0x60); + + _name_ = hal_a2fxxx_i2c0_bus + _init_fn_ = a2fxxx_i2c0_init + _base_ = CYGHWR_HAL_A2FXXX_I2C0 // Base address + _base_bb_ = CYGHWR_HAL_A2FXXX_I2C0_BB // for bit-band access + _periph_ = CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_I2C0 + _isr_vec_ = CYGNUM_HAL_INTERRUPT_I2C0_0 + _isr_pri_ = 0x60 + + CYG_I2C_DEVICE(i2c_a2fxxx_oled, + &hal_a2fxxx_i2c0_bus, + 0x3c, + 0, + CYG_I2C_DEFAULT_DELAY); + </programlisting> + + </refsect1> + <!-- }}} --> + + <!-- {{{ Ethernet Controller --> + <refsect1 id="a2f200-eval-hal-eth"><title>Ethernet Controller</title> + + <para> + The Ethernet MAC layer of the Actel device is compliant with the RMII 10/100Mbps specification. + The development kit interface the DP83848 PHY from National Semiconductor. + </para> + <para> + NOTE: To use the Ethernet interface of the evaluation kit, the FPGA fabric must be programmed. + The Ethernet PHY input clock (50MHz) is connected to an IO only accessible from the fabric. It + is therefore required to route the MAC_CLK from the clock network to the IO (T6). + </para> + <para> + Some of the driver configuration parameters accessible from the CDL file are: + </para> + + <variablelist> + <varlistentry> + <term>CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_CHATTER</term> + <listitem> + <para> + Selecting this option will cause the Ethernet driver to print status + messages as various Ethernet operations are undertaken. This is option + is designed to help debugging the Ethernet driver. + </para> + </listitem> + </varlistentry> + + <varlistentry> + <term>CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_PROMISCUOUS</term> + <listitem> + <para> + Selecting this option will set the Ethernet MAC in promiscuous mode, all Ethernet + packets will be delivered to the application layer whether or not destinated to the + device. + </para> + </listitem> + </varlistentry> + + <varlistentry> + <term>CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_BUFSIZE_TX</term> + <listitem> + <para> + This option specifies the size of the internal transmit buffers used + for the Ethernet device. + </para> + </listitem> + </varlistentry> + + <varlistentry> + <term>CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_BUFSIZE_RX</term> + <listitem> + <para> + This option specifies the size of the internal receive buffers used + for the Ethernet device. + </para> + </listitem> + </varlistentry> + + <varlistentry> + <term>CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_TxNUM</term> + <listitem> + <para> + This option specifies the number of output buffer packets + to be used for the Ethernet device. + </para> + </listitem> + </varlistentry> + + <varlistentry> + <term>CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_RxNUM</term> + <listitem> + <para> + This option specifies the number of input buffer packets + to be used for the Ethernet device. + </para> + </listitem> + </varlistentry> + + <varlistentry> + <term>CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_STATS</term> + <listitem> + <para> + Selecting this option will cause the Ethernet driver to accumulate statistics + provided from the MAC layer. + </para> + </listitem> + </varlistentry> + </variablelist> + + </refsect1> + <!-- }}} --> + + <!-- {{{ Serial --> + <refsect1 id="a2f200-eval-hal-serial"><title>Serial</title> + + <para> + The Actel A2Fxxx uses the 16x5x generic serial device driver. The driver is instantiaced through + the CYGPKG_IO_SERIAL_CORTEXM_A2FXXX serial package. + </para> + + </refsect1> + <!-- }}} --> + + <!-- {{{ DMA --> + <refsect1 id="a2f200-eval-hal-dma"><title>DMA</title> + + <para> + The eCos HAL offers some basics routines to configure and use the 8 DMA channels + available in the Smartfusion chips. It must be noted that all channels are sharing + the same interrupt. The current implementation limits the transfer size to byte + tranfer ( field TRANSFER_SIZE from the CHANNEL_x_CONTROL register ). + Currently only the SPI driver makes use of the DMA interface. + </para> + + <para> + DMA channels are registered / released with <literal>a2fxxx_dma_ch_attach</literal> and + <literal>a2fxxx_dma_ch_detach</literal> respectively: + </para> + + <programlisting width=80> + cyg_uint32 + a2fxxx_dma_ch_attach(cyg_uint8 ch, cyg_ISR_t *isr, cyg_DSR_t *dsr, cyg_addrword_t data) + + ch specify the DMA channel numbered from 0. + isr specify the interrupt ISR to call for this channel. + dsr specify the interrupt DSR to call for this channel. + data data argument passed to the ISR and DSR routine. + </programlisting> + + <programlisting width=80> + void + a2fxxx_dma_ch_detach (cyg_uint8 ch) + + ch specify the DMA channel number from 0 to 7 + </programlisting> + + + <para> + DMA channels are configured with <literal>a2fxxx_dma_ch_setup</literal> : + </para> + + <programlisting width=80> + cyg_uint32 + a2fxxx_dma_ch_setup(cyg_uint8 ch, cyg_uint8 type, cyg_bool outbound, + cyg_uint8 src_incr, cyg_uint8 dst_incr, cyg_bool pri, cyg_uint8 wr_adj) + + ch is the DMA channel numbered from 0. + type is the transfer type to be performed. For valid + values, check CYGHWR_HAL_A2FXXX_DMA_XFER(_x) in var_io.h. + outbound set to true for transfer out of memory, false for transfer + to memory + src_incr is the memory address increment step for the source. Valid + values are 0, 1, 2 and 4 byte(s). 0 can be used for DMA + transfer from peripheral FIFO for instance. + dst_incr is the memory address increment step for the destination. + Valid values are 0, 1, 2 and 4 byte(s). 0 can be used for + DMA transfer to peripheral FIFO for instance. + pri is the DMA channel priority (true = high , false = low) + wr_adj indicates the number of FCLK periods which the PDMA must wait + after completion of a read or write access to a peripheral + before evaluating the out-of-band status signals from that + peripheral for another transfer. + </programlisting> + + <para> + DMA transfer are initiated using <literal>a2fxxx_dma_xfer</literal> : + </para> + + <programlisting width=80> + cyg_uint32 + a2fxxx_dma_xfer (cyg_uint8 ch, cyg_bool polled, cyg_uint32 len, cyg_uint8 *src, + cyg_uint8 *dst) + + ch is the DMA channel numbered from 0. + polled set to true to use the DMA channel in polling mode ( no + end of tranfer interrupt are raised ). + len select the length of the transfer ( in number of byte + transfered ). + src is the start address from which data is to be read during + the next DMA transfer cycle. + dst is the start address from which data is to be written during + the next DMA transfer cycle. + </programlisting> + + <para> + DMA interrupts are cleared with <literal>a2fxxx_dma_clear_interrupt</literal> and + status of the transaction is retreived with <literal>a2fxxx_dma_get_comp_flag</literal> : + </para> + + <programlisting width=80> + void + a2fxxx_dma_clear_interrupt (cyg_uint8 ch) + + cyg_uint8 + a2fxxx_dma_get_comp_flag (cyg_uint8 ch) + + ch is the DMA channel numbered from 0. + </programlisting> + + </refsect1> + <!-- }}} --> + + </refentry> + <!-- }}} --> + + + <!-- {{{ Configuration --> + <refentry id="a2f200-eval-conf"> + <refmeta> + <refentrytitle>Configuration</refentrytitle> + </refmeta> + <refnamediv> + <refname>Configuration</refname> + <refpurpose>Configure, compile and debug the application</refpurpose> + </refnamediv> + + <refsect1 id="a2f200-eval-conf-ov"> + <title><!-- <index></index> -->Overview</title> + <para> + For compilation of the application, the official eCos ARM toolchain is required + (gcc version 4.3.2). + For debugging, it is needed to install the FlashPro utility from Actel as well + as SoftConsole. SoftConsole is an Eclipse based IDE from Microsemi that installs + along with the CodeSourcery ARM toolchain. Both are freely available and require + a Windows OS based host workstation. + To use some peripherals such as the Ethernet controller, the FPGA fabric must be + configured to route the Ethernet PHY clock from the MAC_CLK. It is recommended to + restore the factory image provided from Actel as a starting point in case the user + has already experimented with the fabric. + </para> + </refsect1> + <!-- }}} --> + + <refsect1 id="a2f200-eval-conf-build"> + <title><!-- <index></index> -->Building the application</title> + + <para> + The steps needed to build the HAL library for the Smartfusion evaluation board are: + </para> + <screen> + $ mkdir a2f200_eval + $ cd a2f200_eval + $ ecosconfig new smartfusion kernel + $ ecosconfig resolve + $ ecosconfig tree + $ make + </screen> + <para> + At the end of the build the <filename + class="directory">install/lib</filename> subdirectory should contain the library and linker script and the <filename + class="directory">install/include</filename> subdirectory the necessary includes to compile the application. + </para> + + <para> + The differents startup type available for this platforme are: + </para> + + <informaltable frame="all"> + <tgroup cols="2" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration (HAL_PLF_STARTUP_TYPE)</entry> + <entry>Description</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>Application running from the board's internal flash, LMA = 0x60000000 and VMA = 0x60000000</entry> + </row> + <row> + <entry>SRAM</entry> + <entry>Application running from the board's internal RAM, LMA = 0x20000000 and VMA = 0x20000000</entry> + </row> + <row> + <entry>ROM_SOFTCONSOLE</entry> + <entry>Application running from the board's internal flash, LMA = 0x60000000 and VMA = 0x00000000</entry> + </row> + </tbody> + </tgroup> + </informaltable> + + </refsect1> + <!-- }}} --> + + <refsect1 id="a2f200-eval-conf-sys"> + <title><!-- <index></index> -->System Boot</title> + + <para> + The Smartfusion devices boot process is not entirely controlled by the user. The + Embedded Non-volatile Memory contains spare pages that are reserved to store + specific data such as the factory boot code, the manufacturing parameters, the + system boot code or other data such as the Analog block or MSS configuration. + </para> + + <para> + As described in the device user manual, the device first boots from factory boot + code before jumping to the system boot and eventually giving the hand to the user + code, in this case, the eCos ROM application. + </para> + + <para> + The Actel MSS configuration tool can be used to alter the system boot and the + configuration pages. The ENVM spare pages can then be re-programmed using the + Actel FlashPro utility. The FlashPro utility can also be used to program the + FPGA fabric if required. + </para> + + <informaltable frame="all"> + <tgroup cols="2" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Spare page content</entry> + <entry>Address</entry> + </row> + </thead> + <tbody> + <row> + <entry>Manufacturing parameters</entry> + <entry>0x60080000</entry> + </row> + <row> + <entry>Factory boot</entry> + <entry>0x60080400</entry> + </row> + <row> + <entry>System Boot</entry> + <entry>0x60080800</entry> + </row> + <row> + <entry>Analog block configuration</entry> + <entry>0x60081600</entry> + </row> + <row> + <entry>MSS configuration</entry> + <entry>0x60081E80</entry> + </row> + </tbody> + </tgroup> + </informaltable> + + </refsect1> + <!-- }}} --> + + <refsect1 id="a2f200-eval-conf-dbg"> + <title><!-- <index></index> -->Debugging from console</title> + + <para> + Loading of the application to internal FLASH or RAM of the target is done either + using the SoftConsole IDE supplied from Actel or GDB from command line. The later + case is described in this paragraph. + </para> + + <para> + To debug ROM based application, while configuring eCos, select the ROM_SOFTCONSOLE + startup type. The ROM_SOFTCONSOLE startup type is equivalent to a ROM startup but + while the application is loaded at address 0x60000000 (FLASH), it runs and is debugged + from address 0x00000000. This is done by setting the load address (LMA) to 0x60000000 + and the virtual address (VMA) to 0x00000000 in the eCos memory layout file. In this + example, the timers test application from the eCos Smartfusion HAL is compiled: + </para> + + <screen> + $ mkdir a2f200_eval + $ cd a2f200_eval + $ ecosconfig new smartfusion kernel + -> Select ROM_SOFTCONSOLE statup type + $ ecosconfig resolve + $ ecosconfig tree + $ make + $ make -s tests IGNORE_LINK_ERRORS=y + </screen> + + <para> + Once the application is compiled, from a Windows command interpreter, start the + actel-keepalive utility: + </para> + + <screen> + c:> start actel-keepalive actel-keepalive + </screen> + + <para> + The GDB initialisation sequence located in a2fxxx/a2f200_eval/current/host/softconsole_flash_init.txt + is an example of initialisation sequence to use for debugging application located in + ROM. For RAM based application, the initialisation sequence from + a2fxxx/a2f200_eval/current/host/softconsole_sram_init.txt shall be used. + Make sure to replace the path to the debugger toolchain and the eCos repository first. The GDB + initialisation sequence without in-line comments is: + </para> + + <screen> + set arm fallback-mode thumb + target remote | "C:/Program Files (x86)/Microsemi/SoftConsole v3.3/Sourcery-G++/b- + in/arm-none-eabi-sprite" flashpro:?cpu=Cortex-M3 "C:/wrk/ecos/packages/hal/cortex- + m/a2fxxx/a2f200_eval/current/host" + set mem inaccessible-by-default off + set *0x40006010 = 0x4C6E55FA + set *0xE0042000 = 0 + set *0xE0042008 = 1 + set *0xE0042040 = 0x00207FFD + set *0xE004203C = 0x00000001 + set *0xE0042030 = *0xE0042030 & 0xFFFFFFF7 + set *0xE000ED08 = 0x00000000 + load + set $sp = *0x60080000 + set $pc = *0x60080004 - 1 + </screen> + + <para> + Start the GDB session to debug the timers test example: + </para> + + <screen> + C:\root\a2f200_eval>arm-none-eabi-gdb install\tests\hal\cortexm\a2fxxx\var\curren- + t\tests\timers + GNU gdb (Sourcery G++ Lite Sourcery G++ Lite 2010q1-188 + Actel 1.2) 7.0.50.20100- + 218-cvs + Copyright (C) 2010 Free Software Foundation, Inc. + License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> + This is free software: you are free to change and redistribute it. + There is NO WARRANTY, to the extent permitted by law. Type "show copying" + and "show warranty" for details. + This GDB was configured as "--host=i686-mingw32 --target=arm-none-eabi". + For bug reporting instructions, please see: + <https://support.codesourcery.com/GNUToolchain/>... + Reading symbols from c:\root\a2f200_eval\install\tests\hal\cortexm\a2fxxx\var\curren- + t\tests\timers...done. + (gdb) + </screen> + + <para> + A typical log from the GDB initialisation sequence is shown here: + </para> + + <screen> + Remote debugging using | "C:/Program Files (x86)/Microsemi/SoftConsole v3.3/Sourc- + ery-G++/bin/arm-none-eabi-sprite" flashpro:?cpu=Cortex-M3 "C:/wrk/ecos/packages/h- + al/cortexm/a2fxxx/a2f200_eval/current/host" + arm-none-eabi-sprite: Using memory map C:/wrk/ecos/packages/hal/cortexm/a2fxxx/a2f- + 200_eval/current/host/memory-map.xml + arm-none-eabi-sprite: Target reset + arm-none-eabi-sprite: Transferring memory map (may cause a delay) + 0x6008051c in ?? () + Loading section .rom_vectors, size 0x8 lma 0x60000000 + Loading section .ARM.exidx, size 0x10 lma 0x60000008 + Loading section .text, size 0x3340 lma 0x60000018 + Loading section .rodata, size 0x4dc lma 0x60003358 + Loading section .data, size 0x318 lma 0x6000383c + arm-none-eabi-sprite: Using host routines for flash programming + arm-none-eabi-sprite: Start of flash programming + arm-none-eabi-sprite: Comparing flash memory contents of actel-smartfusion-envm @- + 0x60000000 + arm-none-eabi-sprite: Program 0x60000000 sector [0x0,+0x80) unchanged + arm-none-eabi-sprite: Program 0x60000000 sector [0x80,+0x80) unchanged + arm-none-eabi-sprite: Program 0x60000000 sector [0x100,+0x80) unchanged + .... + arm-none-eabi-sprite: Program 0x60000000 sector [0x3b00,+0x80) unchanged + arm-none-eabi-sprite: End of programming + Start address 0x18, load size 15180 + Transfer rate: 8 KB/sec, 62 bytes/write. + </screen> + + </refsect1> + <!-- }}} --> + + </refentry> + <!-- }}} --> + + </chapter> + <!-- }}} --> + +</part> + +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/memory-map.xml @@ -0,0 +1,16 @@ +<board> + <properties> + <property name="system-v6-m"/> + </properties> + <memory-map> + <memory-device address="0x60000000" size="256k" type="flash" device="actel-smartfusion-envm"> + <description>Flash</description> + </memory-device> + <memory-device address="0x00000000" size="256k" type="rom"> + <description>ROM</description> + </memory-device> + <memory-device address="0x20000000" size="64k" type="ram"> + <description>SRAM</description> + </memory-device> + </memory-map> +</board>
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/softconsole_flash_init.txt @@ -0,0 +1,53 @@ + +# GDB initialization sequence provided from SoftConsole IDE with slight modification +# for eCos + +# [1] Targeting SmartFusion embedded NVM (envm) @ 0x60000000. +# Loads at 0x60000000 but runs/debugs at 0x00000000 (i.e. ld LMA=0x60000000, VMA=0x00000000) + +# Make sure 16-bit Thumb mode breakpoint requests are always used. +set arm fallback-mode thumb + +# Invoke debug sprite in Cortex-M3 mode +# +# PATH to the arm-none-eabi-sprite utility and eCos repository must be +# updated according to a particular setup +target remote | "C:/Program Files (x86)/Microsemi/SoftConsole v3.3/Sourcery-G++/bin/arm-none-eabi-sprite" flashpro:?cpu=Cortex-M3 "C:/wrk/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host" + +# Don't restrict memory access to just regions defined in linker script +set mem inaccessible-by-default off + +# Disable the watchdog +set *0x40006010 = 0x4C6E55FA + +# Ensure that eSRAM IS NOT mapped to 0x00000000 +# Clear ESRAM_CONFIG system register bit 0 (COM_ESRAMFWREMAP) +set *0xE0042000 = 0 +# Ensure that eNVM @ 0x60000000 IS mapped to 0x00000000 +# Set ENVM_REMAP_BASE register COM_ENVMREMAPBASE field to 1 +set *0xE0042008 = 1 + +# Configure external memory controller to access external RAM. + +# Program EMC_CONFIG_0_REG +set *0xE0042040 = 0x00207FFD +# Program EMC_MUX_CONFIG_REG +set *0xE004203C = 0x00000001 +# Program SOFT_RESET_REG +set *0xE0042030 = *0xE0042030 & 0xFFFFFFF7 + +#set *0xE0042004 = 0x00000001 + +# Set temporary breakpoint on main (must be h/w BP for eNVM) +thb cyg_usert_start + +# Specify user application vector table (remapped/mirrored address) +set *0xE000ED08 = 0x00000000 + +# Load the program +load + +# Ensure chip boot code runs before transferring control to user application +# Initialize SP & PC from chip boot vector table +set $sp = *0x60080000 +set $pc = *0x60080004 - 1 \ No newline at end of file
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/softconsole_sram_init.txt @@ -0,0 +1,42 @@ + +# GDB initialization sequence provided from SoftConsole IDE with slight modification +# for eCos + +# [1] Targeting SmartFusion embedded SRAM (esram) @ 0x20000000. +# Loads and debugs at 0x20000000 (i.e. ld LMA=VMA=0x20000000). + +# Make sure 16-bit Thumb mode breakpoint requests are always used. +set arm fallback-mode thumb + +# PATH to the arm-none-eabi-sprite utility and eCos repository must be +# updated according to a particular setup +target remote | "C:/Program Files (x86)/Microsemi/SoftConsole v3.3/Sourcery-G++/bin/arm-none-eabi-sprite" flashpro:?cpu=Cortex-M3 "C:/wrk/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host" + +# Don't restrict memory access to just regions defined in linker script +set mem inaccessible-by-default off + +# Disable the watchdog +set *0x40006010 = 0x4C6E55FA + +# Configure external memory controller to access external RAM. + +# Program EMC_CONFIG_0_REG +set *0xE0042040 = 0x00207FFD +# Program EMC_MUX_CONFIG_REG +set *0xE004203C = 0x00000001 +# Program SOFT_RESET_REG +set *0xE0042030 = *0xE0042030 & 0xFFFFFFF7 + +# Set temporary breakpoint on main (must be s/w BP - Cortex-M3 h/w BPs only below 0x20000000) +thb cyg_usert_start + +# Specify user application vector table +set *0xE000ED08 = 0x20000400 + +# Load the program +load + +# Ensure chip boot code runs before transferring control to user application +# Initialize SP & PC from chip boot vector table +set $sp = *0x60080000 +set $pc = *0x60080004 - 1 \ No newline at end of file
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom.h @@ -0,0 +1,25 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +// Only to get Redboot to compile.. +#define CYGMEM_REGION_ram (CYGMEM_REGION_sram) +#define CYGMEM_REGION_ram_SIZE (CYGMEM_REGION_sram_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_sram_ATTR) + +#define CYGMEM_REGION_flash (0x60000000) +#define CYGMEM_REGION_flash_SIZE (0x00040000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram_SIZE+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom.ldi @@ -0,0 +1,36 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x60000000, LENGTH = 0x00040000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x60000000, LMA_EQ_VMA) + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000400, FOLLOWING (.got)) + SECTION_data (sram, ALIGN (0x8), FOLLOWING (.sram)) + SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = 0x20000000; +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + 1024*64; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.h @@ -0,0 +1,25 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +// Only to get Redboot to compile.. +#define CYGMEM_REGION_ram (CYGMEM_REGION_sram) +#define CYGMEM_REGION_ram_SIZE (CYGMEM_REGION_sram_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_sram_ATTR) + +#define CYGMEM_REGION_flash (0x60000000) +#define CYGMEM_REGION_flash_SIZE (0x00040000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram_SIZE+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.ldi @@ -0,0 +1,39 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +#define PLF_FOLLOWING(_section_) FOLLOWING_ALIGNED(_section_, 8) + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x60000000, LENGTH = 0x00040000 + /* flash mirrored to 0x00000000 */ + flashm : ORIGIN = 0x00000000, LENGTH = 0x00040000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flashm, 0x00000000, AT (0x60000000)) + SECTION_text (flashm, ALIGN (0x8), PLF_FOLLOWING (.rom_vectors)) + SECTION_fini (flashm, ALIGN (0x8), PLF_FOLLOWING (.text)) + SECTION_rodata (flashm, ALIGN (0x8), PLF_FOLLOWING (.fini)) + SECTION_rodata1 (flashm, ALIGN (0x8), PLF_FOLLOWING (.rodata)) + SECTION_fixup (flashm, ALIGN (0x8), PLF_FOLLOWING (.rodata1)) + SECTION_gcc_except_table (flashm, ALIGN (0x8), PLF_FOLLOWING (.fixup)) + SECTION_eh_frame (flashm, ALIGN (0x8), PLF_FOLLOWING (.gcc_except_table)) + SECTION_got (flashm, ALIGN (0x8), PLF_FOLLOWING (.eh_frame)) + SECTION_sram (sram, 0x20000400, PLF_FOLLOWING (.got)) + SECTION_data (sram, ALIGN (0x8), PLF_FOLLOWING (.sram)) + SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = 0x20000000; +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + 1024*64; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_sram.h @@ -0,0 +1,25 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGMEM_REGION_sram) +#define CYGMEM_REGION_ram_SIZE (CYGMEM_REGION_sram_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_sram_ATTR) + +#define CYGMEM_REGION_flash (0x60000000) +#define CYGMEM_REGION_flash_SIZE (0x00040000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_sram.ldi @@ -0,0 +1,34 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x60000000, LENGTH = 0x00040000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (sram, 0x20000400, LMA_EQ_VMA) + SECTION_RELOCS (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (sram, ALIGN(0x8), LMA_EQ_VMA) + SECTION_rodata1 (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = 0x20000000; +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20010000;
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_arch.h @@ -0,0 +1,63 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H +//============================================================================= +// +// plf_arch.h +// +// Platform specific architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Original: nickg (STM32 HAL) +// Date: 2011-04-03 +// Purpose: Actel Smartfusion A2F200 EVAL board specific architecture overrides +// Description: +// Usage: #include <cyg/hal/plf_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_a2f200_eval.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_arch.h +#endif // CYGONCE_HAL_PLF_ARCH_H
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_intr.h @@ -0,0 +1,63 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H +//============================================================================= +// +// plf_intr.h +// +// Platform specific interrupt overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Original: nickg (STM32 HAL) +// Date: 2011-04-03 +// Purpose: Actel Smartfusion A2F200 EVAL board specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_intr.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_a2f200_eval.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_intr.h +#endif // CYGONCE_HAL_PLF_INTR_H
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_io.h @@ -0,0 +1,74 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Platform specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Original: nickg (STM32 HAL) +// Date: 2011-04-03 +// Purpose: Actel Smartfusion A2F200 EVAL board specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_a2f200_eval.h> + +//============================================================================= +// Memory access checks. +// +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. These macros allow the GDB stubs to avoid making +// accidental accesses to these areas. + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ); + +#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +//----------------------------------------------------------------------------- +// end of plf_io.h + +#endif // CYGONCE_HAL_PLF_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/src/a2f200_eval_misc.c @@ -0,0 +1,160 @@ +/*========================================================================== +// +// a2f200_eval_misc.c +// +// Cortex-M3 A2F200 EVAL HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Original: nickg (STM32 HAL) +// Date: 2011-04-03 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_a2fxxx.h> +#include <pkgconf/hal_cortexm_a2f200_eval.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header + +#define TEST_IO 0 + +//========================================================================== +// System init +// +// This is run to set up the basic system, including GPIO setting, +// clock feeds, power supply, and memory initialization. This code +// runs before the DATA is copied from ROM and the BSS cleared, hence +// it cannot make use of static variables or data tables. + + +__externC void +hal_system_init( void ) +{ +} + +cyg_uint32 led[7] = { + CYGHWR_HAL_A2FXXX_GPIO( 24, OUT, NONE, DISABLE ), + CYGHWR_HAL_A2FXXX_GPIO( 25, OUT, NONE, DISABLE ), + CYGHWR_HAL_A2FXXX_GPIO( 26, OUT, NONE, DISABLE ), + CYGHWR_HAL_A2FXXX_GPIO( 27, OUT, NONE, DISABLE ), +}; + + +//========================================================================== + +__externC void +hal_platform_init( void ) +{ +#if TEST_IO + cyg_uint8 i; +#endif + +#if TEST_IO + for(i = 0; i < 4; i++) + { + CYGHWR_HAL_A2FXXX_GPIO_SET( led[i] ); + CYGHWR_HAL_A2FXXX_GPIO_OUT( led[i], 1); + } +#endif + +} + +//========================================================================== + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. +// +// The following table defines the memory areas that GDB is allowed to +// touch. All others are disallowed. +// This table needs to be kept up to date with the set of memory areas +// that are available on the board. + +static struct +{ + CYG_ADDRESS start; // Region start address + CYG_ADDRESS end; // End address (last byte) +} hal_data_access[] = +{ +#ifdef CYGMEM_REGION_sram // On-chip SRAM + { + CYGMEM_REGION_sram, CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE - 1}, +#endif +#ifdef CYGMEM_REGION_flash // On-chip flash + { + CYGMEM_REGION_flash, + CYGMEM_REGION_flash + CYGMEM_REGION_flash_SIZE - 1}, +#endif + { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals + { 0x40000000, 0x60000000-1 }, // Smartfusion peripherals +}; + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ) +{ + int i; + for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) + { + if( (addr >= hal_data_access[i].start) && + (addr+count) <= hal_data_access[i].end) + return true; + } + return false; +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + + +//========================================================================== +// EOF a2f200_eval_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/a2fxxx/a2f200_eval/current/src/platform_i2c.c @@ -0,0 +1,179 @@ +//========================================================================== +// +// platform_i2c.c +// +// Optional I2C support for Cortex-M3 Actel Smartfusion +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Contributors: +// Date: 2011-04-08 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + + +//============================================================================= +// INCLUDES +//============================================================================= +#include <pkgconf/system.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_io.h> +#include <cyg/infra/cyg_ass.h> +#include <cyg/hal/hal_endian.h> +#include <cyg/hal/hal_intr.h> + +#ifdef CYGPKG_DEVS_I2C_CORTEXM_A2FXXX + +#include <cyg/io/i2c.h> +#include <cyg/io/i2c_a2fxxx.h> + +//============================================================================= +// Setup I2C bus 0 +// +static void +a2fxxx_i2c0_init( struct cyg_i2c_bus *bus ) +{ + cyg_uint32 scl_io = CYGHWR_HAL_A2FXXX_I2C0_SCL; + cyg_uint32 sda_io = CYGHWR_HAL_A2FXXX_I2C0_SDA; + + // + // We only need to setup the pins here and + // leave the I2C driver to take care of the rest. + // + CYGHWR_HAL_A2FXXX_GPIO_SET( scl_io ); + CYGHWR_HAL_A2FXXX_GPIO_SET( sda_io ); + + a2fxxx_i2c_init( bus ); +} + + +//----------------------------------------------------------------------------- +// I2C bus 0 +// +CYG_A2FXXX_I2C_BUS(hal_a2fxxx_i2c0_bus, + &a2fxxx_i2c0_init, + CYGHWR_HAL_A2FXXX_I2C0, // Base address + CYGHWR_HAL_A2FXXX_I2C0_BB, // Bit-band base address + CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_I2C0, + CYGNUM_HAL_INTERRUPT_I2C0_0, + CYGNUM_DEVS_I2C_CORTEXM_A2FXXX_I2C0_ISR_PRIORITY); + + +//----------------------------------------------------------------------------- +// OLED +// +CYG_I2C_DEVICE(i2c_a2fxxx_oled, + &hal_a2fxxx_i2c0_bus, + 0x3c, + 0, + CYG_I2C_DEFAULT_DELAY); + + +#define DELAY 1 + +// Wrapper to OLED driver + +externC cyg_uint32 +a2fxxx_oled_write_first( cyg_uint8 byte ) +{ + cyg_uint32 result; + + cyg_i2c_transaction_begin( &i2c_a2fxxx_oled ); + + result = cyg_i2c_transaction_tx( &i2c_a2fxxx_oled, + true, ( cyg_uint8 * )&byte, 1, false ); + +#ifdef CYGPKG_KERNEL + cyg_thread_delay( DELAY ); +#endif + + return result; +} + +externC cyg_uint32 +a2fxxx_oled_write_byte( cyg_uint8 byte ) +{ + cyg_uint32 result; + + result = cyg_i2c_transaction_tx( &i2c_a2fxxx_oled, + false, ( cyg_uint8 * )&byte, 1, false ); + +#ifdef CYGPKG_KERNEL + cyg_thread_delay( DELAY ); +#endif + + return result; +} + + +externC cyg_uint32 +a2fxxx_oled_write_array( const cyg_uint8 *array, cyg_uint32 count ) +{ + cyg_uint32 result; + + result = cyg_i2c_transaction_tx( &i2c_a2fxxx_oled, + false, array, count, false ); + + return result; +} + + +externC cyg_uint32 +a2fxxx_oled_write_final( cyg_uint8 byte ) +{ + cyg_uint32 result; + + result = cyg_i2c_transaction_tx( &i2c_a2fxxx_oled, + false, ( cyg_uint8 * )&byte, 1, true ); +#ifdef CYGPKG_KERNEL + cyg_thread_delay( DELAY ); +#endif + + cyg_i2c_transaction_end( &i2c_a2fxxx_oled ); + + return result; +} + +#endif // #ifdef CYGPKG_DEVS_I2C_CORTEXM_A2FXXX + +//----------------------------------------------------------------------------- +// EOF platform_i2c.c