--- a/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog
@@ -1,3 +1,11 @@
+2012-01-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512.cdl:
+	* include/plf_io.h:
+	* src/twr_k60n512_misc.c:
+	Add entry for DMA, Add CYG_HAL_STARTUP_ENV. Add DSPI pins for SPI1 bus.
+	Updated for early clock start.  [Bugzilla 1001450]
+
 2011-03-26  Ilija Kocho  <ilijak@siva.com.mk>
 
 	* cdl/hal_cortexm_kinetis_twr_k60n512.cdl:

--- a/packages/hal/cortexm/kinetis/twr_k60n512/current/cdl/hal_cortexm_kinetis_twr_k60n512.cdl
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/cdl/hal_cortexm_kinetis_twr_k60n512.cdl
@@ -71,6 +71,9 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T
 
     requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
         (1 == CYGHWR_DEVS_ETH_PHY_KSZ8041) }
+    requires      { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies
+        (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) }
+
     define_proc {
         puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k60n512.h>"
         puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
@@ -78,6 +81,23 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T
         puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
     }
 
+    cdl_component CYG_HAL_STARTUP_ENV {
+        display "Startup type"
+        flavor data
+        no_define
+        calculated {
+            !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP :
+            ((CYG_HAL_STARTUP_PLF == "ByVariant") ?
+            (CYG_HAL_STARTUP . "(Variant)") :
+            (CYG_HAL_STARTUP . "(Platform)"))
+        }
+        description "
+            Startup type configuration defines the system memory layout.
+            Startup type  can be defined by the variant (CYG_HAL_STARTUP_VAR)
+            or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
 
     cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ {
         display "Platform Clock Frequency"
@@ -184,6 +204,30 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T
             Digital I/O provided by HAL for ENET IEEE 1588 timers."
     }
 
+    cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS {
+        display "MMC Disk SPI bus"
+        flavor data
+        parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+        calculated 1
+
+        requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1
+        implements CYGINT_DEVS_SPI_FREESCALE_DSPI1
+        implements CYGINT_FREESCALE_DSPI1_HAS_MASS
+
+        cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS {
+            display "Device number (CS)"
+            flavor data
+            calculated 0
+            implements CYGINT_FREESCALE_DSPI1_CS0
+        }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
     cdl_component CYGBLD_GLOBAL_OPTIONS {
         display "Global build options"
         flavor  none

--- a/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_io.h
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_io.h
@@ -108,6 +108,24 @@
 # define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(C, 18, 4, 0)
 # define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(C, 19, 4, 0)
 #endif
+
+
+// DSPI
+// DSPI Pins
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN  CYGHWR_HAL_KINETIS_PIN(E, 3, 2, KINETIS_PIN_SPI1_IN_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 1, 2, KINETIS_PIN_SPI1_OUT_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK  CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_OUT_OPT)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0  CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1  CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2  CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3  CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4  CYGHWR_HAL_KINETIS_PIN_NONE
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5  CYGHWR_HAL_KINETIS_PIN_NONE
+
+
+
 //=============================================================================
 // Memory access checks.
 //

--- a/packages/hal/cortexm/kinetis/twr_k60n512/current/src/twr_k60n512_misc.c
+++ b/packages/hal/cortexm/kinetis/twr_k60n512/current/src/twr_k60n512_misc.c
@@ -76,7 +76,6 @@ static inline void hal_gpio_init(void);
 __externC cyg_uint32 __bss_start;
 __externC cyg_uint32 __bss_end;
 
-
 //==========================================================================
 // System init
 //
@@ -91,6 +90,7 @@ hal_system_init( void )
 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
     hal_wdog_disable();
     hal_gpio_init();
+    hal_start_clocks();
 #endif
 #if defined(CYG_HAL_STARTUP_SRAM) && !defined(CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED)
     // Note: For CYG_HAL_STARTUP_SRAM, the SRAM_L bank simulates ROM
@@ -136,8 +136,6 @@ hal_gpio_init(void)
     mpu_p->cesr = 0;
 }
 
-
-
 //==========================================================================
 
 __externC void hal_platform_init( void )
@@ -224,6 +222,5 @@ cyg_plf_memory_segment(int seg, unsigned
 
 #endif // CYGPKG_REDBOOT
 
-
 //==========================================================================
 // EOF twr_k60n512_misc.c