Mercurial > nand-ecoscentric
changeset 3238:952b5540550c
* src/stm3210e_eval_eth_enc424j600.c: New file, initialization
of optional enc424j600 ethernet over SPI.
* include/plf_io.h: Add macro for initialization of optional
enc424j600 ethernet over SPI.
* cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Add component
enc424j600 ethernet over SPI.
| author | jlarmour |
|---|---|
| date | Thu, 03 May 2012 18:49:39 +0000 |
| parents | 3c619144e8af |
| children | 7ca4d3009445 |
| files | packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.h packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.ldi packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_eth_enc424j600.c |
| diffstat | 6 files changed, 341 insertions(+), 7 deletions(-) [+] |
line wrap: on
line diff
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog @@ -1,3 +1,14 @@ +2012-04-20 Ilija Stanislevik <ilijas@siva.mk> + + * src/stm3210e_eval_eth_enc424j600.c: New file, initialization + of optional enc424j600 ethernet over SPI. + + * include/plf_io.h: Add macro for initialization of optional + enc424j600 ethernet over SPI. + + * cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Add component + enc424j600 ethernet over SPI. + 2012-03-23 James Smith <jsmith@ecoscentric.com> * include/plf_io.h: Update GPIO pin definitions to use new PIN
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl @@ -8,7 +8,7 @@ ## ####ECOSGPLCOPYRIGHTBEGIN#### ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. -## Copyright (C) 2008 Free Software Foundation, Inc. +## Copyright (C) 2008, 2012 Free Software Foundation, Inc. ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -86,16 +86,34 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM JTAG debugger such as a BDI3000 or PEEDI. The 'SRAM' type allows programs to be downloaded via a JTAG debugger into on-chip SRAM." } - + cdl_component CYGHWR_MEMORY_LAYOUT { display "Memory layout" flavor data no_define - calculated { (CYG_HAL_STARTUP == "RAM" ) ? "cortexm_stm3210e_eval_ram" : - (CYG_HAL_STARTUP == "SRAM" ) ? "cortexm_stm3210e_eval_sram" : - (CYG_HAL_STARTUP == "ROM" ) ? "cortexm_stm3210e_eval_rom" : - (CYG_HAL_STARTUP == "JTAG" ) ? "cortexm_stm3210e_eval_jtag" : - "undefined" } + calculated { (CYG_HAL_STARTUP == "RAM" ) ? + (CYGMEM_HAL_CORTEXM_STM32_STM3210E_EXTRA_BASE_RAM ? + "cortexm_stm3210e_eval_extrabaseram" : "cortexm_stm3210e_eval_ram") : + (CYG_HAL_STARTUP == "SRAM") ? "cortexm_stm3210e_eval_sram" : + (CYG_HAL_STARTUP == "ROM" ) ? "cortexm_stm3210e_eval_rom" : + (CYG_HAL_STARTUP == "JTAG") ? "cortexm_stm3210e_eval_jtag" : + "undefined" } + + cdl_option CYGMEM_HAL_CORTEXM_STM32_STM3210E_EXTRA_BASE_RAM { + display "Additional reserved space at base of RAM" + flavor booldata + default_value 0 + active_if {CYG_HAL_STARTUP == "RAM"} + legal_values 0 to 0x80000 + description " + If you are using a RedBoot with additional components enabled, + such as networking, RedBoot may be occupying additional RAM. + In such cases, an eCos application loaded by RedBoot must + reserve additional space at the base of RAM to accommodate + RedBoot's extra RAM requirements. This option, specified in + bytes, allows the amount of extra reserved space to be + increased beyond the default." + } cdl_option CYGHWR_MEMORY_LAYOUT_LDI { display "Memory layout linker script fragment" @@ -218,6 +236,95 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM console and GDB port are the same." } + cdl_component CYGHWR_HAL_CORTEXM_STM32_SPIETH_CONTROLLER { + display "STM3210E HAL resources" + parent CYGPKG_DEVS_ETH_ENC424J600 + active_if CYGPKG_DEVS_ETH_ENC424J600 + compile stm3210e_eval_eth_enc424j600.c + flavor none + no_define + + description " + Support for ENC424J600 with STM3210E EVAL board." + + cdl_option CYGNUM_ETH_SPIETH_HAL_INTERRUPT_VECTOR { + display "Interrupt vector calculated from pin" + parent CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_VECTOR + flavor data + no_define + calculated { "CYGNUM_HAL_INTERRUPT_EXTI" . CYGHWR_HAL_SPIETH_INTERRUPT_PIN } + active_if CYGINT_IO_ETH_INT_SUPPORT_REQUIRED + description " + Interrupt vector corresponding with external interrupt line used for + enc424j600. + This value is automatically calculated from CYGHWR_HAL_SPIETH_INTERRUPT_PIN. + " + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS { + display "SPI bus" + flavor data + requires { (CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS == 1) implies CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1 } + requires { (CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS == 2) implies CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2 } + requires { (CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS == 3) implies CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3 } + requires (CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE==50) + legal_values { 1 2 3 } + default_value 1 + description " + Select which SPI bus of the STM32 the SPI Ethernet controller + is connected to." + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_CS { + display "Chip select index" + flavor data + default_value 0 + legal_values 0 to 99 + description " + Enter the index into the array of chip selects to be used as + the chip select for the external Ethernet + controller connected to the SPI bus. The list of possible chip + selects for the selected SPI bus is defined in the STM32 SPI + driver's configuration, for example for SPI bus 1: + CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1_CS_GPIOS." + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_SPIETH_INTERRUPT_PORT { + display "Interrupt pin port" + active_if CYGINT_IO_ETH_INT_SUPPORT_REQUIRED + flavor data + legal_values { "\'A\'" "\'B\'" "\'C\'" "\'D\'" "\'E\'" "\'F\'" "\'G\'" } + default_value {"\'G\'"} + description " + This selects the GPIO port associated with the interrupt pin + connected to the external Ethernet controller." + } + + cdl_option CYGHWR_HAL_SPIETH_INTERRUPT_PIN { + display "Interrupt pin number" + active_if CYGINT_IO_ETH_INT_SUPPORT_REQUIRED + flavor data + legal_values 0 to 15 + default_value 15 + description " + This selects the pin number within the GPIO port associated with + the interrupt pin connected to the external Ethernet controller." + } + + cdl_option CYGNUM_HAL_SPIETH_INTERRUPT_PRIORITY { + display "Interrupt priority" + active_if CYGINT_IO_ETH_INT_SUPPORT_REQUIRED + flavor data + legal_values { 0xe0 0xd0 0xc0 0xb0 0xa0 0x90 0x80 + 0x70 0x60 0x50 0x40 0x30 0x20 0x10 0x00} + default_value 0xe0 + description " + Enter the interrupt priority used for the interrupt + connected to the external Ethernet controller. A + lower number means a higher priority." + } + } + cdl_component CYGBLD_GLOBAL_OPTIONS { display "Global build options" flavor none
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.h @@ -0,0 +1,21 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00010000) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (0x68000000) +#define CYGMEM_REGION_ram_SIZE (0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.ldi @@ -0,0 +1,36 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00010000 + flash : ORIGIN = 0x08000000, LENGTH = 0x00080000 + rom : ORIGIN = 0x64000000, LENGTH = 0x01000000 + ram : ORIGIN = 0x68000000, LENGTH = 0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_sram (sram, 0x20000400, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x68008000+CYGMEM_HAL_CORTEXM_STM32_STM3210E_EXTRA_BASE_RAM, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = 0x20000000; +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x68100000;
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h @@ -149,6 +149,17 @@ #define CYGHWR_HAL_STM32_SPI3_DMA_RX CYGHWR_HAL_STM32_DMA( 2, 1, 0, P2M ) +//============================================================================= +// Optional enc424j600 Ethernet over SPI + +#ifdef CYGPKG_DEVS_ETH_ENC424J600 +struct cyg_netdevtab_entry; +__externC void cyg_devs_cortexm_stm3210e_enc424j600_init( struct cyg_netdevtab_entry * ); +#define CYG_DEVS_ETH_ENC424J600_PLF_INIT( _tab_ ) \ + cyg_devs_cortexm_stm3210e_enc424j600_init( _tab_ ) + +#endif + //----------------------------------------------------------------------------- // end of plf_io.h #endif // CYGONCE_HAL_PLF_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_eth_enc424j600.c @@ -0,0 +1,148 @@ +/*========================================================================== +// +// stm3210e_eval_eth_enc424j600.c +// +// Setup for optional enc424j600 Ethernet over SPI +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Stanislevik +// Date: 2012-04-05 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <cyg/hal/hal_io.h> + +#include <cyg/io/spi.h> +#include <cyg/io/spi_stm32.h> +#include <cyg/io/eth/netdev.h> +#include <cyg/io/eth/eth_drv.h> +#include <cyg/io/eth/enc424j600_eth.h> + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_ass.h> // assertion macros + +// Set to: 1 for diagnostic printouts; 0 for no diagnostic printouts. +#define DEBUG_ENC424J600_PLATFORM_INIT 0 + +// SPI device for communication with enc424j600 Ethernet chip +#define TRANS8B false +#define CLK_IDLE_LOW 0 +#define CLK_PHASE_RISING 0 + +#define AUX_SPI_CORTEXM_STM32_DEVICE(_name_, _bus_) \ + CYG_DEVS_SPI_CORTEXM_STM32_DEVICE( \ + _name_##_spi, \ + _bus_, \ + CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_CS, \ + TRANS8B, \ + CLK_IDLE_LOW, \ + CLK_PHASE_RISING, \ + 14000000, \ + 1, \ + 1, \ + 1 \ + ) + +AUX_SPI_CORTEXM_STM32_DEVICE +( + CYGDAT_IO_ETH_ENC424J600_NAME, + CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS +); + +// Code to initialize enc424j600 driver data structure. + +void cyg_devs_cortexm_stm3210e_enc424j600_init( struct cyg_netdevtab_entry * netdevtab_entry) +{ + struct eth_drv_sc *eth_inst = NULL; // pointer to device instance + enc424j600_priv_data_t *eth_inst_pd = NULL; // device's private data +#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED + cyg_uint32 cr; + cyg_uint32 backupr; +#endif + +// Assign SPI device to Ethernet device. + eth_inst = netdevtab_entry->device_instance; + eth_inst_pd = (enc424j600_priv_data_t *)eth_inst->driver_private; + +#if DEBUG_ENC424J600_PLATFORM_INIT & 1 + diag_printf("%s(): Assigning SPI device to Ethernet device %s.\n",__FUNCTION__, netdevtab_entry->name); +#endif + eth_inst_pd->spi_service_device = (cyg_spi_device *) &CYGDAT_IO_ETH_ENC424J600_NAME_spi_stm32; + +#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED + +// Interrupt output from enc424j600 is connected to one of the pins from ports A-G. +// Here this pin is marshaled to External Interrupt Controller (EXTI). + +#define ENC424J600_INTERRUPT_SOURCE_PIN CYGHWR_HAL_SPIETH_INTERRUPT_PIN +#define ENC424J600_EXTICR ((ENC424J600_INTERRUPT_SOURCE_PIN / 4) * 4 + 8) +#define ENC424J600_SHIFT_VALUE ((ENC424J600_INTERRUPT_SOURCE_PIN % 4) * 4) + +#if DEBUG_ENC424J600_PLATFORM_INIT & 1 + diag_printf("%s(): Mapping external interrupt from P%c%d.\n",__FUNCTION__, + CYGHWR_HAL_CORTEXM_STM32_SPIETH_INTERRUPT_PORT, + ENC424J600_INTERRUPT_SOURCE_PIN); +#endif + + // Is AFIO clock enabled? + HAL_READ_UINT32(CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB2ENR , backupr ); + if (0 == (backupr & BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_AFIO))) + { + CYGHWR_HAL_STM32_CLOCK_ENABLE(CYGHWR_HAL_STM32_CLOCK(APB2,AFIO)); + } + + // Modify External Interrupt Control Register + HAL_READ_UINT32(CYGHWR_HAL_STM32_AFIO + ENC424J600_EXTICR , cr ); + cr |= ((cyg_uint32)0xf << ENC424J600_SHIFT_VALUE); + cr &= (((cyg_uint32)(CYGHWR_HAL_CORTEXM_STM32_SPIETH_INTERRUPT_PORT - 'A') + << ENC424J600_SHIFT_VALUE) & 0xffff); + HAL_WRITE_UINT32(CYGHWR_HAL_STM32_AFIO + ENC424J600_EXTICR , cr ); + + // Restore AFIO clock + if (0 == (backupr & BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_AFIO))) + { + CYGHWR_HAL_STM32_CLOCK_DISABLE(CYGHWR_HAL_STM32_CLOCK(APB2,AFIO)); + } + +#endif // #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED +} + +//========================================================================== +// EOF stm3210e_eval_eth_enc424j600.c