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changeset 3234:abf5be1b8582

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Whitespace cleanup
author vae
date Mon, 23 Apr 2012 19:03:36 +0000
parents e07f3346a350
children c40674be6da8
files packages/hal/cortexm/arch/current/ChangeLog packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl packages/hal/cortexm/arch/current/include/basetype.h packages/hal/cortexm/arch/current/include/cortexm_stub.h packages/hal/cortexm/arch/current/include/hal_arch.h packages/hal/cortexm/arch/current/include/hal_intr.h packages/hal/cortexm/arch/current/include/hal_io.h packages/hal/cortexm/arch/current/src/context.S packages/hal/cortexm/arch/current/src/cortexm_stub.c packages/hal/cortexm/arch/current/src/hal_misc.c packages/hal/cortexm/arch/current/src/vectors.S
diffstat 11 files changed, 143 insertions(+), 123 deletions(-) [+]
line wrap: on
line diff
--- a/packages/hal/cortexm/arch/current/ChangeLog
+++ b/packages/hal/cortexm/arch/current/ChangeLog
@@ -1,3 +1,17 @@
+2012-04-23  Ilija Kocho  <ilijak@siva.com.mk>
+
+    * cdl/hal_cortexm.cdl:
+    * include/basetype.h:
+    * include/cortexm_stub.h:
+    * include/hal_arch.h:
+    * include/hal_intr.h:
+    * include/hal_io.h:
+    * src/context.S:
+    * src/cortexm_stub.c:
+    * src/hal_misc.c:
+    * src/vectors.S:
+    Whitespace cleanup [Bugzilla 1001569]
+
 2012-03-06  Ilija Kocho  <ilijak@siva.com.mk>
 
     * include/hal_intr.h: Fix compiler warning about unused variables.
--- a/packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl
+++ b/packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl
@@ -151,11 +151,11 @@ cdl_package CYGPKG_HAL_CORTEXM {
              Calculate the maximum exception priority that can be set by interrupts.
              Higher priorities are reserved for the DEBUG and SVC traps."
     }
-    
+
     cdl_option CYGBLD_LINKER_SCRIPT {
         display "Linker script"
         flavor data
-	no_define
+        no_define
         calculated  { "src/cortexm.ld" }
     }
 
@@ -165,7 +165,7 @@ cdl_package CYGPKG_HAL_CORTEXM {
             default_value 8
             description   "
                 This option determines the number of breakpoints supported by the HAL."
-    }    
+    }
 }
 
 # EOF hal_cortexm.cdl
--- a/packages/hal/cortexm/arch/current/include/basetype.h
+++ b/packages/hal/cortexm/arch/current/include/basetype.h
@@ -47,7 +47,8 @@
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 #define CYG_BYTEORDER           CYG_LSBFIRST    // Little endian
 #define CYG_DOUBLE_BYTEORDER    CYG_LSBFIRST
@@ -68,4 +69,3 @@
 //==========================================================================
 #endif // CYGONCE_HAL_BASETYPE_H
 // End of basetype.h
-
--- a/packages/hal/cortexm/arch/current/include/cortexm_stub.h
+++ b/packages/hal/cortexm/arch/current/include/cortexm_stub.h
@@ -46,7 +46,8 @@
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 
 #ifdef __cplusplus
@@ -74,9 +75,9 @@ typedef unsigned long target_register_t;
 #endif
 
 enum regnames {
-    R0, R1, R2, R3, R4, R5, R6, R7, 
+    R0, R1, R2, R3, R4, R5, R6, R7,
     R8, R9, R10, FP, IP, SP, LR, PC,
-    F0, F1, F2, F3, F4, F5, F6, F7, 
+    F0, F1, F2, F3, F4, F5, F6, F7,
     FPS, PS
 };
 
@@ -91,7 +92,7 @@ enum regnames {
 typedef enum regnames regnames_t;
 
 //------------------------------------------------------------------------
-    
+
 /* Given a trap value TRAP, return the corresponding signal. */
 extern int __computeSignal (unsigned int trap_number);
 
--- a/packages/hal/cortexm/arch/current/include/hal_arch.h
+++ b/packages/hal/cortexm/arch/current/include/hal_arch.h
@@ -47,7 +47,8 @@
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 #include <pkgconf/system.h>
 #include <pkgconf/hal.h>
@@ -63,7 +64,7 @@
 // for each context. This makes the GDB state get/put slightly more
 // complex, but that is a suitable compromise.
 
-typedef struct 
+typedef struct
 {
     union
     {
@@ -83,10 +84,10 @@ typedef struct
             cyg_uint32          type;           // State type
             cyg_uint32          vector;         // Exception vector number
             cyg_uint32          basepri;        // BASEPRI
-            
+
             cyg_uint32          r4_11[8];       // Remaining CPU registers
             cyg_uint32          xlr;            // Exception return LR
-            
+
             // The following are saved and restored automatically by the CPU
             // for exceptions or interrupts.
 
@@ -103,7 +104,7 @@ typedef struct
         struct
         {
             cyg_uint32          type;           // State type
-            
+
             // The following are saved and restored automatically by the CPU
             // for exceptions or interrupts.
 
@@ -115,7 +116,7 @@ typedef struct
             cyg_uint32          lr;
             cyg_uint32          pc;
             cyg_uint32          psr;
-            
+
         } interrupt;
     } u;
 
@@ -220,7 +221,7 @@ externC void cyg_hal_deliver_exception( 
 // Breakpoint support
 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen
 // if executed.
-// HAL_BREAKINST is the value of the breakpoint instruction and 
+// HAL_BREAKINST is the value of the breakpoint instruction and
 // HAL_BREAKINST_SIZE is its size in bytes.
 
 #define HAL_BREAKINST           0xbebe         // BKPT
@@ -342,4 +343,3 @@ typedef cyg_uint32 hal_jmp_buf[CYGARC_JM
 
 //==========================================================================
 #endif //CYGONCE_HAL_ARCH_H
-
--- a/packages/hal/cortexm/arch/current/include/hal_intr.h
+++ b/packages/hal/cortexm/arch/current/include/hal_intr.h
@@ -47,7 +47,8 @@
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 #include <pkgconf/system.h>
 #include <pkgconf/hal.h>
@@ -71,7 +72,7 @@
 #define CYGNUM_HAL_VECTOR_MEMORY_MAN     4      // Memory management (M3)
 #define CYGNUM_HAL_VECTOR_BUS_FAULT      5      // Bus Fault
 #define CYGNUM_HAL_VECTOR_USAGE_FAULT    6      // Usage Fault
-#define CYGNUM_HAL_VECTOR_RESERVED_07    7      
+#define CYGNUM_HAL_VECTOR_RESERVED_07    7
 #define CYGNUM_HAL_VECTOR_RESERVED_08    8
 #define CYGNUM_HAL_VECTOR_RESERVED_09    9
 #define CYGNUM_HAL_VECTOR_RESERVED_10   10
@@ -168,7 +169,7 @@ CYG_MACRO_END
 //
 // Interrupt handler/data/object tables plus functions and macros to
 // manipulate them.
- 
+
 __externC volatile CYG_ADDRESS   hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
 __externC volatile CYG_ADDRWORD  hal_interrupt_data    [CYGNUM_HAL_ISR_COUNT];
 __externC volatile CYG_ADDRESS   hal_interrupt_objects [CYGNUM_HAL_ISR_COUNT];
@@ -396,4 +397,3 @@ typedef cyg_uint32  CYG_INTERRUPT_STATE;
 
 //==========================================================================
 #endif //CYGONCE_HAL_INTR_H
-
--- a/packages/hal/cortexm/arch/current/include/hal_io.h
+++ b/packages/hal/cortexm/arch/current/include/hal_io.h
@@ -47,7 +47,8 @@
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 #include <pkgconf/system.h>
 #include <pkgconf/hal.h>
@@ -318,7 +319,7 @@ typedef volatile CYG_ADDRWORD HAL_IO_REG
 //-----------------------------------------------------------------------------
 // 16 bit access.
 // Individual and vectorized access to 16 bit registers.
-    
+
 
 #define HAL_READ_UINT16( _register_, _value_ ) \
         ((_value_) = *((volatile CYG_WORD16 *)(_register_)))
@@ -397,7 +398,7 @@ typedef volatile CYG_ADDRWORD HAL_IO_REG
 
 #endif // !HAL_IO_MACROS_DEFINED
 
-// Enforce a flow "barrier" to prevent optimizing compiler from reordering 
+// Enforce a flow "barrier" to prevent optimizing compiler from reordering
 // operations.
 #define HAL_IO_BARRIER()
 
--- a/packages/hal/cortexm/arch/current/src/context.S
+++ b/packages/hal/cortexm/arch/current/src/context.S
@@ -45,7 +45,8 @@
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 #include <pkgconf/system.h>
 #include <pkgconf/hal.h>
@@ -59,13 +60,13 @@
         .syntax unified
         .thumb
         .text
-        
+
 //==========================================================================
 // Context switch
 //
 // R0 contains a pointer to the SP of the thread to load, R1 contains
-// a pointer to the SP of the current thread.        
-        
+// a pointer to the SP of the current thread.
+
         .globl  hal_thread_switch_context
         .thumb
         .thumb_func
@@ -77,11 +78,11 @@ hal_thread_switch_context:
         mrs     r3,basepri              // Get priority base register
         mov     r4,sp                   // Get SP (for info only)
         push    {r2-r4}                 // Push them
-        
+
         str     sp,[r1]                 // Save SP
 
         // Fall through
-        
+
 //--------------------------------------------------------------------------
 // Load context
 //
@@ -99,16 +100,16 @@ hal_thread_load_context:
         msr     basepri,r3              // Set BASEPRI
         pop     {r0-r12,pc}             // Pop all register and return
 
-//==========================================================================        
+//==========================================================================
 //  HAL longjmp, setjmp implementations
-//        
+//
 //  hal_setjmp saves only to callee save registers R4-14
 //  and LR into buffer supplied in r0[arg0].
 
         .globl  hal_setjmp
         .thumb
         .thumb_func
-        .type   hal_setjmp, %function        
+        .type   hal_setjmp, %function
 hal_setjmp:
         mov     r3,sp
         stmea   r0,{r3-r12,r14}
@@ -116,7 +117,7 @@ hal_setjmp:
         bx      lr
 
 //  hal_longjmp loads state from r0[arg0] and returns
-        
+
         .globl  hal_longjmp
         .thumb
         .thumb_func
--- a/packages/hal/cortexm/arch/current/src/cortexm_stub.c
+++ b/packages/hal/cortexm/arch/current/src/cortexm_stub.c
@@ -44,7 +44,8 @@
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 #include <stddef.h>
 
@@ -118,17 +119,17 @@ reg_offset(regnames_t reg)
     int base_offset;
 
     if (reg < F0)
-	return reg * 4;
+        return reg * 4;
 
     base_offset = 16 * 4;
 
     if (reg < FPS)
-	return base_offset + ((reg - F0) * 12);
+        return base_offset + ((reg - F0) * 12);
 
     base_offset += (8 * 12);
 
     if (reg <= PS)
-	return base_offset + ((reg - FPS) * 4);
+        return base_offset + ((reg - FPS) * 4);
 
     return -1;  // Should never happen!
 }
@@ -138,14 +139,14 @@ reg_offset(regnames_t reg)
 // Return the currently-saved value corresponding to register REG of
 // the exception context.
 
-target_register_t 
+target_register_t
 get_register (regnames_t reg)
 {
     target_register_t val;
     int offset = reg_offset(reg);
 
     if (REGSIZE(reg) > sizeof(target_register_t) || offset == -1)
-	return -1;
+        return -1;
 
     val = _registers[offset/sizeof(target_register_t)];
 
@@ -156,13 +157,13 @@ get_register (regnames_t reg)
 // Store VALUE in the register corresponding to WHICH in the exception
 // context.
 
-void 
+void
 put_register (regnames_t which, target_register_t value)
 {
     int offset = reg_offset(which);
 
     if (REGSIZE(which) > sizeof(target_register_t) || offset == -1)
-	return;
+        return;
 
     _registers[offset/sizeof(target_register_t)] = value;
 }
@@ -178,8 +179,8 @@ get_register_as_bytes (regnames_t which,
     int offset = reg_offset(which);
 
     if (offset != -1) {
-	memcpy (value, (char *)_registers + offset, REGSIZE(which));
-	return 1;
+        memcpy (value, (char *)_registers + offset, REGSIZE(which));
+        return 1;
     }
     return 0;
 }
@@ -195,8 +196,8 @@ put_register_as_bytes (regnames_t which,
     int offset = reg_offset(which);
 
     if (offset != -1) {
-	memcpy ((char *)_registers + offset, value, REGSIZE(which));
-	return 1;
+        memcpy ((char *)_registers + offset, value, REGSIZE(which));
+        return 1;
     }
     return 0;
 }
@@ -229,8 +230,8 @@ void __single_step (void)
 
     // Clear any bits set in DFSR
     base = CYGARC_REG_NVIC_BASE;
-    HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_DFSR, 0xFFFFFFFF );    
-    
+    HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_DFSR, 0xFFFFFFFF );
+
 }
 
 //==========================================================================
@@ -251,7 +252,7 @@ void __clear_single_step (void)
 
     // Clear any bits set in DFSR
     base = CYGARC_REG_NVIC_BASE;
-    HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_DFSR, 0xFFFFFFFF );        
+    HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_DFSR, 0xFFFFFFFF );
 }
 
 //==========================================================================
--- a/packages/hal/cortexm/arch/current/src/hal_misc.c
+++ b/packages/hal/cortexm/arch/current/src/hal_misc.c
@@ -44,7 +44,8 @@
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 #include <pkgconf/hal.h>
 #include <pkgconf/hal_cortexm.h>
@@ -128,9 +129,9 @@ void hal_reset_vsr( void )
     // usually supplied by the platform HAL. Calls to
     // hal_variant_init() and hal_platform_init() later will perform
     // the main initialization.
-    
+
     hal_system_init();
-    
+
     // Initialize vector table in base of SRAM.
     {
         register int i;
@@ -140,13 +141,13 @@ void hal_reset_vsr( void )
         // Only install the exception vectors for non-RAM startup. For
         // RAM startup we want these to continue to point to the original
         // VSRs, which will belong to RedBoot or GDB stubs.
-        
+
         for( i = 2; i < 15; i++ )
             hal_vsr_table[i] = (CYG_ADDRESS)hal_default_exception_vsr;
 
 #endif
         // Always point SVC and PENDSVC vectors to our local versions
-        
+
         hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr;
         hal_vsr_table[CYGNUM_HAL_VECTOR_PENDSV] = (CYG_ADDRESS)hal_pendable_svc_vsr;
 
@@ -167,11 +168,11 @@ void hal_reset_vsr( void )
 
     // On M3 and M4 parts, the NVIC contains a vector table base register.
     // We program this to relocate the vector table base to the base of SRAM.
-    
+
     HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_VTOR,
                       CYGARC_REG_NVIC_VTOR_TBLOFF(0)|
                       CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM );
-    
+
 # else
 
 #  error Unknown SRAM/VECTAB remap mechanism
@@ -182,14 +183,14 @@ void hal_reset_vsr( void )
     // We don't need to do this for RAM startup since the ROM code
     // will have already done it.
 
-    hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_switch_state_vsr;    
+    hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_switch_state_vsr;
 
     __asm__ volatile( "swi 0" );
 
     hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr;
-    
+
 #endif // !defined(CYG_HAL_STARTUP_RAM)
-    
+
 #if defined(CYG_HAL_STARTUP_ROM)
     // Relocate data from ROM to RAM
     {
@@ -223,13 +224,13 @@ void hal_reset_vsr( void )
     // PendSVC which are lowest priority.
     {
         register int i;
-        
+
         HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR0, 0x00000000 );
         HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR1, 0xFF000000 );
         HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, 0x00FF0000 );
-        
+
         hal_interrupt_handlers[CYGNUM_HAL_INTERRUPT_SYS_TICK] = (CYG_ADDRESS)hal_default_isr;
-        
+
         for( i = 1; i < CYGNUM_HAL_ISR_COUNT; i++ )
         {
             hal_interrupt_handlers[i] = (CYG_ADDRESS)hal_default_isr;
@@ -251,7 +252,7 @@ void hal_reset_vsr( void )
     }
 #endif
 
-#if !defined(CYG_HAL_STARTUP_RAM)    
+#if !defined(CYG_HAL_STARTUP_RAM)
     // Enable Usage, Bus and Mem fault handlers. Do this for ROM and
     // JTAG startups. For RAM startups, this will have already been
     // done by the ROM monitor.
@@ -266,25 +267,25 @@ void hal_reset_vsr( void )
         HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_SHCSR, shcsr );
     }
 #endif
-    
+
     // Call variant and platform init routines
     hal_variant_init();
     hal_platform_init();
 
     // Start up the system clock
     HAL_CLOCK_INITIALIZE( CYGNUM_HAL_RTC_PERIOD );
-            
+
 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
-    
+
     initialize_stub();
-    
+
 #endif
 
 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) || \
     defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
-    
+
     hal_ctrlc_isr_init();
-    
+
 #endif
 
     // Run through static constructors
@@ -319,7 +320,7 @@ void hal_deliver_exception( HAL_SavedReg
     if (__mem_fault_handler )
     {
         regs->u.exception.pc = (unsigned long)__mem_fault_handler;
-        return; // Caught an exception inside stubs        
+        return; // Caught an exception inside stubs
     }
 #endif
 
@@ -335,8 +336,8 @@ void hal_deliver_exception( HAL_SavedReg
 #else
 
     CYG_FAIL("Exception!!!");
-    
-#endif    
+
+#endif
 }
 
 //==========================================================================
@@ -356,14 +357,14 @@ void hal_deliver_interrupt( cyg_uint32 v
     register cyg_uint32 isr_result;
     register cyg_isr *isr;
     cyg_bool pendsvc = false;
-    
+
 #if defined(CYGPKG_KERNEL_INSTRUMENT) && \
     defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
     CYG_INSTRUMENT_INTR(RAISE, vector, 0);
 #endif
 
     isr = (cyg_isr *)hal_interrupt_handlers[vector];
-    
+
     // Call the ISR
     isr_result = isr( vector, hal_interrupt_data[vector] );
 
@@ -413,10 +414,10 @@ void hal_deliver_interrupt( cyg_uint32 v
 
 __externC void hal_interrupt_end( void )
 {
-#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT    
+#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
     cyg_scheduler_sched_lock++;
 #endif
-    
+
    interrupt_end(0,0,0);
 }
 
@@ -521,7 +522,7 @@ void hal_deliver_interrupt( cyg_uint32 v
         if( t1 < t0 )
             us -= (t1 + CYGNUM_HAL_RTC_PERIOD - t0);
         else
-        	us -= t1 - t0;
+            us -= t1 - t0;
         t0 = t1;
     }
 }
@@ -546,7 +547,7 @@ cyg_hal_invoke_constructors (void)
 {
 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
     static pfunc *p = &CONSTRUCTORS_START;
-    
+
     cyg_hal_stop_constructors = 0;
     for (; p != CONSTRUCTORS_END; NEXT_CONSTRUCTOR(p)) {
         (*p)();
@@ -586,7 +587,7 @@ hal_arch_default_isr(CYG_ADDRWORD vector
 {
     int i;
     cyg_uint32 *p = gdbreg->f0;
-    
+
     switch( regs->u.type )
     {
     case HAL_SAVEDREGISTERS_THREAD:
@@ -597,7 +598,7 @@ hal_arch_default_isr(CYG_ADDRWORD vector
         gdbreg->gpr[15] = regs->u.thread.pc;
         gdbreg->ps = 0x01000000;
         break;
-            
+
     case HAL_SAVEDREGISTERS_EXCEPTION:
         gdbreg->gpr[0] = regs->u.exception.r0;
         gdbreg->gpr[1] = regs->u.exception.r1;
@@ -611,7 +612,7 @@ hal_arch_default_isr(CYG_ADDRWORD vector
         gdbreg->gpr[15] = regs->u.exception.pc;
         gdbreg->ps = regs->u.exception.psr;
         break;
-                
+
     case HAL_SAVEDREGISTERS_INTERRUPT:
         gdbreg->gpr[0] = regs->u.interrupt.r0;
         gdbreg->gpr[1] = regs->u.interrupt.r1;
@@ -628,13 +629,13 @@ hal_arch_default_isr(CYG_ADDRWORD vector
     // Clear FP state, which we don't use
     for( i = 0; i < (8*3+1); i++ )
         p[i] = 0;
-    
+
 }
 
 __externC void hal_set_gdb_registers( HAL_CORTEXM_GDB_Registers *gdbreg, HAL_SavedRegisters *regs )
 {
     int i;
-    
+
     switch( regs->u.type )
     {
     case HAL_SAVEDREGISTERS_THREAD:
@@ -644,7 +645,7 @@ hal_arch_default_isr(CYG_ADDRWORD vector
         regs->u.thread.pc = gdbreg->gpr[14];
         regs->u.thread.pc = gdbreg->gpr[15];
         break;
-            
+
     case HAL_SAVEDREGISTERS_EXCEPTION:
         regs->u.exception.r0 = gdbreg->gpr[0];
         regs->u.exception.r1 = gdbreg->gpr[1];
@@ -657,7 +658,7 @@ hal_arch_default_isr(CYG_ADDRWORD vector
         regs->u.exception.pc = gdbreg->gpr[15];
         regs->u.exception.psr = gdbreg->ps;
         break;
-                
+
     case HAL_SAVEDREGISTERS_INTERRUPT:
         regs->u.interrupt.r0 = gdbreg->gpr[0];
         regs->u.interrupt.r1 = gdbreg->gpr[1];
--- a/packages/hal/cortexm/arch/current/src/vectors.S
+++ b/packages/hal/cortexm/arch/current/src/vectors.S
@@ -48,7 +48,8 @@
 //
 //####DESCRIPTIONEND####
 //
-//========================================================================*/
+//========================================================================
+*/
 
 #include <pkgconf/hal.h>
 #include <pkgconf/hal_cortexm.h>
@@ -78,10 +79,10 @@ hal_vsr_table_init:
         .long           hal_reset_vsr                   //  1 Reset entry
 
 //==========================================================================
-        
+
         .text
         .thumb
-        
+
 //==========================================================================
 // Fake entry point.
 //
@@ -89,7 +90,7 @@ hal_vsr_table_init:
 // via RedBoot/Stubs or via JTAG the PC will be set to this address.
 // The code here sets up the SP and branches to the reset VSR in
 // emulation of the hardware reset behaviour.
-        
+
         .align  2
         .global reset_vector
         .thumb
@@ -102,7 +103,7 @@ reset_vector:
 
         .pool
 
-#if !defined(CYG_HAL_STARTUP_RAM)        
+#if !defined(CYG_HAL_STARTUP_RAM)
 //==========================================================================
 // State switch VSR
 //
@@ -115,8 +116,8 @@ reset_vector:
 // throw exceptions without corrupting the execution stack. This is
 // only necessary for non-kernel configurations (e.g. RedBoot, Stubs)
 // since kernel configurations will switch to a thread stack before
-// they should throw an exception.        
-        
+// they should throw an exception.
+
         .global hal_switch_state_vsr
         .thumb
         .thumb_func
@@ -125,23 +126,23 @@ hal_switch_state_vsr:
 
         mov     r0,#CYGNUM_HAL_CORTEXM_PRIORITY_MAX
         msr     basepri,r0
-        
+
         mov     r0,#2                   // Set CONTROL register to 2
         msr     control,r0
         isb                             // Insert a barrier
-        
+
         mov     r0,sp
         msr     psp,r0                  // Copy SP to PSP
 
 #if !defined(CYGPKG_KERNEL)
         sub     sp,#(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE/2)
-#endif        
-        
+#endif
+
         orr     lr,#0xD                 // Adjust return link
         bx      lr                      // Return to init code on PSP now
 
 #endif
-        
+
 //==========================================================================
 // Default exception VSR
 //
@@ -153,7 +154,7 @@ hal_switch_state_vsr:
 // switch elsewhere. However, I know of no code that does anything
 // like this. If there is then this may need treating in the same way
 // as the interrupt end code.
-        
+
         .global hal_default_exception_vsr
         .thumb
         .thumb_func
@@ -163,11 +164,11 @@ hal_default_exception_vsr:
         mrs     r0,psp                  // Get process stack
         sub     r1,r0,#(4*12)           // Make space for saved state
         msr     psp,r1                  // Ensure PSP is up to date
-        
+
         mov     r1,#1                   // R1 = exception state type
         mrs     r2,ipsr                 // R2 = vector number
         mrs     r3,basepri              // R3 = basepri
-        stmfd   r0!,{r1-r11,lr}         // Push type, vector, basepri, r4-11 
+        stmfd   r0!,{r1-r11,lr}         // Push type, vector, basepri, r4-11
 
         mov     r4,r0                   // R4 = saved state pointer
 
@@ -177,9 +178,9 @@ hal_default_exception_vsr:
         ldmfd   r0!,{r1-r11,lr}         // Pop type, vec, basepri, registers and LR
         msr     psp,r0                  // Restore PSP
         msr     basepri,r3              // Restore basepri
-        
+
         bx      lr                      // Return
-        
+
         .pool
 
 //==========================================================================
@@ -188,7 +189,7 @@ hal_default_exception_vsr:
 // This is a trampoline that translates from the hardware defined entry point
 // to the ISR defined by eCos. The CPU will switch automatically to the main
 // (interrupt) stack with the process state saved on the process stack. Apart
-// from saving a pointer to the interrupt state for Ctrl-C support, and fetching        
+// from saving a pointer to the interrupt state for Ctrl-C support, and fetching
 // the vector number, most of the work is actually done in hal_deliver_interrupt().
 
 
@@ -200,7 +201,7 @@ hal_default_interrupt_vsr:
 
         push    {lr}                    // Save return link
         sub     sp,#4                   // Realign SP to 8 bytes
-        
+
 #if CYGINT_HAL_COMMON_SAVED_INTERRUPT_STATE_REQUIRED > 0
         // If we are supporting Ctrl-C interrupts from GDB, we must squirrel
         // away a pointer to the saved interrupt state here so that we can
@@ -208,12 +209,12 @@ hal_default_interrupt_vsr:
 
        .extern  hal_saved_interrupt_state
         mrs     r1,psp                  // Get PSP
-        mov     r0,#3                   // Interrupt state type        
+        mov     r0,#3                   // Interrupt state type
         stmfd   r1!,{r0}                // Push interrupt type
         ldr     r12,=hal_saved_interrupt_state
         str     r1,[r12]
 #endif
-        
+
         mrs     r0,ipsr                 // R0 = arg0 = vector number
         sub     r0,#15                  // Adjust to interrupt range
 
@@ -221,7 +222,7 @@ hal_default_interrupt_vsr:
 
         add     sp,#4                   // pop alignment padding
         pop     {pc}                    // Pop LR and return
-        
+
         .pool
 
 //==========================================================================
@@ -233,9 +234,9 @@ hal_default_interrupt_vsr:
 // a fake exception frame onto the PSP which will take us to hal_interrupt_end(),
 // which will make the call. The return link loaded by that frame takes us
 // back to hal_interrupt_end_done which will unwind the real exception
-// frame that is still on the PSP.        
+// frame that is still on the PSP.
 
-        
+
         .global hal_pendable_svc_vsr
         .thumb
         .thumb_func
@@ -245,18 +246,18 @@ hal_pendable_svc_vsr:
         mrs     r12,psp                 // R12 = thread's PSP
         sub     r0,r12,#0x20            // Make space for frame
         msr     psp,r0                  // Put it back
-        
+
         ldr     r3,=0x01000000          // R3 = PSR = thumb bit set
         ldr     r2,=hal_interrupt_end   // R2 = PC = interrupt end entry point
         ldr     r1,=hal_interrupt_end_done // R1 = LR = restore code
         stmfd   r12!,{r0-r3}            // Save fake R12, LR, PC, PSR
         stmfd   r12!,{r0-r3}            // Save fake R0-R3
-        
+
         bx      lr                      // Return to hal_interrupt_end
 
         .pool
-        
-//==========================================================================                        
+
+//==========================================================================
 // Interrupt end done
 //
 // After calling interrupt end a thread returns here to unstack the
@@ -265,7 +266,7 @@ hal_pendable_svc_vsr:
 // from handler mode, so we use a SWI which will discard its own
 // frame and restore the saved one.
 
-        
+
         .global hal_interrupt_end_done
         .thumb
         .thumb_func
@@ -274,21 +275,21 @@ hal_interrupt_end_done:
 
         ldr     r3,=hal_interrupt_end_vsr
         swi 0
-        
-//==========================================================================        
+
+//==========================================================================
 // Interrupt end VSR
 //
 // This is the SVC VSR invoked by hal_interrupt_end_done to restore the
 // original exception frame from a pendable SVC entry. It does this
 // by discarding its own frame and using the one below it on the
 // stack to return.
-        
+
         .global hal_interrupt_end_vsr
         .thumb
         .thumb_func
         .type   hal_interrupt_end_vsr, %function
-hal_interrupt_end_vsr: 
-        
+hal_interrupt_end_vsr:
+
         mrs     r12,psp                 // R12 = thread's PSP
         add     r12,#32                 // Skip our saved state
         msr     psp,r12                 // Restore thread's PSP
@@ -307,7 +308,7 @@ hal_interrupt_end_vsr:
         .thumb
         .thumb_func
         .type   hal_call_dsrs_vsr, %function
-        
+
 hal_call_dsrs_vsr:
 
         .extern cyg_interrupt_call_pending_DSRs
@@ -320,7 +321,7 @@ hal_call_dsrs_vsr:
 // in handler mode. R3 contains the address of a piece of code to run,
 // R0-R2 contain any arguments. Once entered the code is responsible for
 // handling the system state and returning to thread mode.
-//        
+//
 // Note that R0-R3 must be explicitly restored from their stacked
 // copies since a late arriving interrupt can preempt the SVC entry
 // and corrupt these registers before we get here.
@@ -336,6 +337,6 @@ hal_default_svc_vsr:
         bx      r3                      // Jump to routine in R3
 
         .pool
-        
-//==========================================================================        
+
+//==========================================================================
 // end of vectors.S