Mercurial > nand-ecoscentric
changeset 6:d376b777e2ce ecos-sw-1999-05-14
Merge from eCos master repository on 1999-05-14-19:27:43-BST
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--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -1,3 +1,23 @@ +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The following changes were made in a branch and imported to the + main trunk at a later date: + + + 1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * packages: Reorder IO & HAL packages to allow ConfigTool to + handle rearranged hierarchy. + + 1999-04-14 John Dallaway <jld@cygnus.co.uk> + + * packages: Place architecture package description strings in + alphabetic order. + +1999-05-13 Jesper Skov <jskov@cygnus.co.uk> + PR 17809 + * targets: Use -msoft-float instead of defining _SOFT_FLOAT. + 1999-05-10 Bart Veer <bartv@cygnus.co.uk> * pkgconf.tcl:
--- a/packages/compat/uitron/current/ChangeLog +++ b/packages/compat/uitron/current/ChangeLog @@ -1,3 +1,9 @@ +1999-05-14 Hugo Tyson <hmt@masala.cygnus.co.uk> + + * include/uit_objs.hxx: object array declaration macro now + contains constructor priority ordering rune; if 0'd out pending + 99r1 compiler cutover. + 1999-04-23 Hugo Tyson <hmt@cygnus.co.uk> * tests/testcx7.cxx: T2_MALLOC definition; only make it smaller
--- a/packages/compat/uitron/current/include/uit_objs.hxx +++ b/packages/compat/uitron/current/include/uit_objs.hxx @@ -73,8 +73,15 @@ // Macro to declare static uitron static objects; uses the appropriate // config define for the number of them to have. +#if 0 +#define CYG_UITRON_OBJS_INIT_PRIORITY CYG_INIT_PRIORITY( COMPAT ) +#else +#define CYG_UITRON_OBJS_INIT_PRIORITY // nothing +#endif + #define CYG_UITRON_DECL( _which_ ) \ - CYG_UITRON_OBJS( _which_ ) [ CYG_UITRON_NUM( _which_ ) ] + CYG_UITRON_OBJS( _which_ ) [ CYG_UITRON_NUM( _which_ ) ] \ + CYG_UITRON_OBJS_INIT_PRIORITY // and the array of pointers to them for those with dynamic existence: #define CYG_UITRON_DECL_PTRS( _which_ ) \
--- a/packages/hal/arm/arch/current/ChangeLog +++ b/packages/hal/arm/arch/current/ChangeLog @@ -1,3 +1,12 @@ +1999-05-13 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_arch.h (HAL_THREAD_INIT_CONTEXT): Align stack + (rather conservatively) before use. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/vectors.S: No separate interrupt stack if no kernel. + 1999-05-10 Gary Thomas <gthomas@cygnus.co.uk> * src/vectors.S:
--- a/packages/hal/arm/arch/current/include/hal_arch.h +++ b/packages/hal/arm/arch/current/include/hal_arch.h @@ -124,7 +124,7 @@ externC int hal_msbindex(int); #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ CYG_MACRO_START \ - register CYG_WORD _sp_ = ((CYG_WORD)_sparg_); \ + register CYG_WORD _sp_ = ((CYG_WORD)_sparg_) &~15; \ register HAL_SavedRegisters *_regs_; \ int _i_; \ _regs_ = (HAL_SavedRegisters *)((_sp_) - sizeof(HAL_SavedRegisters)); \
--- a/packages/hal/arm/arch/current/include/hal_mmu.h +++ b/packages/hal/arm/arch/current/include/hal_mmu.h @@ -80,6 +80,10 @@ #define MMU_InvalidateCache c7 // Invalidate cache data #define MMU_TLB c8 // Translation Lookaside Buffer +// These seem to be 710 specific +#define MMU_FlushTLB c5 +#define MMU_FlushIDC c7 + #define MMU_Control_M 0x001 // Enable MMU #define MMU_Control_A 0x002 // Enable address alignment faults #define MMU_Control_C 0x004 // Enable cache @@ -90,7 +94,7 @@ #define MMU_Control_B 0x080 // Enable Big-Endian #define MMU_Control_S 0x100 // Enable system protection #define MMU_Control_R 0x200 // Enable ROM protection -#define MMU_Control_Init (MMU_Control_M|MMU_Control_P|MMU_Control_D) +#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L) //-----------------------------------------------------------------------------
--- a/packages/hal/arm/arch/current/src/vectors.S +++ b/packages/hal/arm/arch/current/src/vectors.S @@ -48,6 +48,7 @@ #include <pkgconf/kernel.h> #else # undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT +# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK #endif #include <cyg/hal/hal_platform_setup.h> @@ -216,8 +217,7 @@ 2: mov r0,#0 cmp r1,r2 beq 2f - sub r1,r1,#4 -1: str r0,[r1,#4]! +1: str r0,[r1],#4 cmp r1,r2 bne 1b 2:
--- a/packages/hal/common/current/ChangeLog +++ b/packages/hal/common/current/ChangeLog @@ -1,3 +1,33 @@ +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The following changes were all made on a branch and imported into + the main trunk later. + + 1999-05-11 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/hal.h: + tidied up all MIPS targets to include CYGBLD_HAL_TARGET_H. This + will eventually apply to all configurations. + + 1999-05-06 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak (COMPILE): Added dbg-threads-syscall.c. + + * include/dbg-thread-syscall.h: + * src/dbg-threads-syscall.c: + Files added to enable support for thread-awareness in GDB stub + ROMs. The .h file has been moved from kernel/src/debug. + + 1999-04-28 Nick Garnett <nickg@cygnus.co.uk> + + * src/hal_stub.c (__build_t_packet): Changed sp variable to a + non-pointer type to force it to be installed in the T packet with + the right size. + + * src/drv_api.c: Added cyg_interrupt_call_pending_DSRs() to keep + HAL happy in non-kernel configurations. + + 1999-04-28 Bart Veer <bartv@cygnus.co.uk> * src/PKGconf.mak:
new file mode 100644 --- /dev/null +++ b/packages/hal/common/current/include/dbg-thread-syscall.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 1998,1999 Cygnus Solutions + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +/* This file should be included only by + thread-syscall-relay.c and + dbg-thread-demux.c + */ + + + +enum dbg_syscall_ids + { + dbg_null_func , + dbg_capabilities_func, + dbg_currthread_func, + dbg_threadlist_func, + dbg_threadinfo_func, + dbg_getthreadreg_func, + dbg_setthreadreg_func, + dbg_scheduler_func, + } ; + + +union dbg_thread_syscall_parms +{ + struct + { + struct dbg_capabilities * abilities ; + } cap_parms ; + + struct + { + threadref * ref ; + } currthread_parms ; + + struct + { + int startflag ; + threadref * lastid ; + threadref * nextthreadid ; + } threadlist_parms ; + + struct + { + threadref * ref ; + struct cygmon_thread_debug_info * info ; + } info_parms ; + + struct + { + threadref * thread ; + int regcount ; + void * registers ; + } reg_parms ; + struct + { + threadref * thread ; /* 64-bit thread identifier */ + int lock; /* 0 == unlock, 1 == lock */ + int mode; /* 0 == short (step), 1 == continue */ + } scheduler_parms ; +} ; + + +typedef int (*dbg_syscall_func) (enum dbg_syscall_ids id, + union dbg_thread_syscall_parms * p ) ;
--- a/packages/hal/common/current/include/pkgconf/hal.h +++ b/packages/hal/common/current/include/pkgconf/hal.h @@ -313,7 +313,7 @@ parent CYGPKG_HAL_DEBUG requires !CYGPKG_HAL_POWERPC_SIM requires !CYGPKG_HAL_MN10300_SIM - requires !CYGPKG_HAL_TX39_SIM + requires !CYGPKG_HAL_MIPS_SIM requires !CYGPKG_HAL_I386_LINUX requires !CYGPKG_HAL_SPARCLITE description " @@ -329,7 +329,7 @@ display "Include GDB external break support" parent CYGPKG_HAL_DEBUG requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS - requires !CYGPKG_HAL_TX39_JMR3904 + requires !CYGPKG_HAL_MIPS_TX39_JMR3904 requires !CYGPKG_HAL_POWERPC_FADS description " This option causes the GDB stub to add a serial interrupt handler @@ -381,7 +381,7 @@ //#define CYG_HAL_USE_ROM_MONITOR -#if defined(CYG_HAL_TX39_JMR3904) && defined(CYG_HAL_STARTUP_RAM) +#if defined(CYG_HAL_MIPS_TX39_JMR3904) && defined(CYG_HAL_STARTUP_RAM) #define CYG_HAL_USE_ROM_MONITOR #define CYG_HAL_USE_ROM_MONITOR_CYGMON #endif @@ -395,6 +395,7 @@ //#define CYG_HAL_USE_ROM_MONITOR_SLOAD //#define CYG_HAL_USE_ROM_MONITOR_GDB_STUBS //#define CYG_HAL_USE_ROM_MONITOR_CYGMON +//#define CYG_HAL_USE_ROM_MONITOR_PMON #endif @@ -432,19 +433,8 @@ # define CYG_HAL_POWERPC_MPC603 #endif -#ifdef CYG_HAL_TX39_JMR3904 -# define CYG_HAL_MIPS -# define CYG_HAL_MIPS_TX39 -# define CYG_HAL_MIPS_TX3904 -# define CYG_HAL_MIPS_JMR3904 -#endif -#ifdef CYG_HAL_TX39_SIM -# define CYG_HAL_MIPS -# define CYG_HAL_MIPS_TX39 -# define CYG_HAL_MIPS_SIM -#endif -#ifdef CYG_HAL_MIPS_TX39 -#include <pkgconf/hal_tx39.h> +#ifdef CYGPKG_HAL_MIPS +#include CYGBLD_HAL_TARGET_H #endif /* -------------------------------------------------------------------*/
--- a/packages/hal/common/current/src/PKGconf.mak +++ b/packages/hal/common/current/src/PKGconf.mak @@ -32,7 +32,7 @@ PACKAGE := hal include ../../../../pkgconf/pkgconf.mak LIBRARY := libtarget.a -COMPILE := generic-stub.c thread-packets.c hal_stub.c drv_api.c +COMPILE := generic-stub.c thread-packets.c hal_stub.c drv_api.c dbg-threads-syscall.c EXTRAS_COMPILE := dummy.c OTHER_OBJS :=
new file mode 100644 --- /dev/null +++ b/packages/hal/common/current/src/dbg-threads-syscall.c @@ -0,0 +1,187 @@ + +/* pseudo system calls to bind system specific multithread debug support + with a ROM monitor, cygmon. + We call it Cygmon, but the feature lives in libstub. + */ + +/* + * Copyright (c) 1998, 1999 Cygnus Solutions + * + * The contents of this file are subject to the Cygnus eCos Public + * License Version 1.0 (the "License"); you may not use this file + * except in compliance with the License. You may obtain a copy of + * the License at http://sourceware.cygnus.com/ecos/ + * + * Software distributed under the License is distributed on an + * "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or + * implied. See the License for the specific language governing rights + * and limitations under the License. + * + * The Original Code is eCos - Embedded Cygnus Operating System, + * released September 30, 1998. The Initial Developer of the Original + * Code is Cygnus. Portions created by Cygnus are Copyright (C) 1998 + * Cygnus Solutions. All Rights Reserved. + */ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#if !defined(CYGPKG_KERNEL) && defined(CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT) + +/* Only include this code if we do not have a kernel. Otherwise the kernel + * supplies these functions for the app we are linked with. + */ + +#include <cyg/hal/dbg-threads-api.h> +#include <cyg/hal/dbg-thread-syscall.h> + + +static dbg_syscall_func * dbg_syscall_ptr ; + +static union dbg_thread_syscall_parms tcall ; + +/* ----- INIT_THREADS_SYSCALL --------------------------------------- */ +/* Some external bing and configuration logic knows how to setup + the ststem calls. In the first implementation, we have used a vector + in the secondary vector table. This functions allows us to isolate that + sort of system specific detail. Similarly, we do not export the + specific detail of a dbg_syscall_func. + */ + + +void init_threads_syscall(void * vector) +{ + dbg_syscall_ptr = vector ; /* AH, the easy compatability of the + void pointer*/ +} /* init_threads_syscall */ + +/* All forms of failure return 0 */ +/* Whether non support, incomplete initialization, unknown thread */ +static __inline__ int dbg_thread_syscall( + enum dbg_syscall_ids id) +{ + dbg_syscall_func f ; /* double indirect via */ + if (0 ==(f = *dbg_syscall_ptr)) return 0 ; /* no pointer to vector */ + if (0 == *f) return 0 ; /* vector not initialized */ + return (*f)(id,&tcall); +} + + + + +/* ------- INIT_THREAD_SYSCALL ------------------------------------------- */ +/* Received the address of the entry in the secondary interrupt vector table */ +/* This table is the interchange between the O.S. and Cygmon/libstub */ +/* This could get more complex so, I am doing it with a function + rather than exposing the internals. + */ +void init_thread_syscall(void * vector) +{ + dbg_syscall_ptr = vector ; +} + +int dbg_thread_capabilities(struct dbg_capabilities * cbp) +{ +#if 0 + tcall.cap_parms.abilities = cbp ; + return dbg_thread_syscall(dbg_capabilities_func) ; +#else + cbp->mask1 = has_thread_current | + has_thread_registers | + has_thread_reg_change | + has_thread_list | + has_thread_info ; + return 1 ; +#endif +} + +int dbg_currthread(threadref * varparm) +{ + tcall.currthread_parms.ref = varparm ; + return dbg_thread_syscall(dbg_currthread_func) ; +} + + +int dbg_threadlist( + int startflag, + threadref * lastthreadid, + threadref * next_thread + ) +{ + tcall.threadlist_parms.startflag = startflag ; + tcall.threadlist_parms.lastid = lastthreadid ; + tcall.threadlist_parms.nextthreadid = next_thread ; + return dbg_thread_syscall(dbg_threadlist_func) ; +} + +int dbg_threadinfo( + threadref * threadid, + struct cygmon_thread_debug_info * info) +{ + tcall.info_parms.ref = threadid ; + tcall.info_parms.info = info ; + return dbg_thread_syscall(dbg_threadinfo_func) ; +} + +int dbg_getthreadreg( + threadref * osthreadid, + int regcount, /* count of registers in the array */ + void * regval) /* fillin this array */ +{ + tcall.reg_parms.thread = osthreadid ; + tcall.reg_parms.regcount = regcount ; + tcall.reg_parms.registers = regval ; + return dbg_thread_syscall(dbg_getthreadreg_func) ; +} + +int dbg_setthreadreg( + threadref * osthreadid, + int regcount , /* number of registers */ + void * regval) +{ + tcall.reg_parms.thread = osthreadid ; + tcall.reg_parms.regcount = regcount ; + tcall.reg_parms.registers = regval ; + return dbg_thread_syscall(dbg_setthreadreg_func) ; +} /* dbg_setthreadreg */ + +int dbg_scheduler(threadref *thread_id, int lock, int mode) +{ + tcall.scheduler_parms.thread = thread_id; + tcall.scheduler_parms.lock = lock ; + tcall.scheduler_parms.mode = mode ; + + return dbg_thread_syscall(dbg_scheduler_func) ; +} + + + +#if (CYG_BYTEORDER == CYG_LSBFIRST) + +unsigned long swap32(unsigned long x) +{ + unsigned long r = 0; + + r |= (x>>24)&0xFF; + r |= ((x>>16)&0xFF)<<8; + r |= ((x>>8)&0xFF)<<16; + r |= ((x)&0xFF)<<24; + + return r; +} + +#else + +#define swap32(x) ((unsigned long)(x)) + +#endif + +int dbg_currthread_id(void) +{ + threadref ref; + dbg_currthread( &ref ); + + return (cyg_uint16)swap32(((unsigned long *)ref)[1]); +} + +#endif
--- a/packages/hal/common/current/src/drv_api.c +++ b/packages/hal/common/current/src/drv_api.c @@ -122,6 +122,16 @@ static void call_dsrs(void) } //-------------------------------------------------------------------------- +// This is referenced from the HAL, although it does not actually get called. + +externC void +cyg_interrupt_call_pending_DSRs(void) +{ + call_dsrs(); +} + + +//-------------------------------------------------------------------------- // Interrupt end function called from HAL VSR to tidy up. This is where // DSRs will be called if necessary.
--- a/packages/hal/common/current/src/hal_stub.c +++ b/packages/hal/common/current/src/hal_stub.c @@ -317,9 +317,9 @@ void { target_register_t addr; char *ptr = buf; - target_register_t *sp; + target_register_t sp; - sp = (target_register_t *) get_register (SP); + sp = (target_register_t) get_register (SP); *ptr++ = 'T'; *ptr++ = __tohex (sigval >> 4);
--- a/packages/hal/i386/arch/current/ChangeLog +++ b/packages/hal/i386/arch/current/ChangeLog @@ -1,3 +1,13 @@ +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + PR 18956 + * src/i386.ld: Fixed problem with rel_got. + Encode . in section name as __. + +1999-05-13 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_arch.h (HAL_THREAD_INIT_CONTEXT): Align stack + (rather conservatively) before use. + 1999-04-28 Bart Veer <bartv@cygnus.co.uk> * src/PKGconf.mak:
--- a/packages/hal/i386/arch/current/include/hal_arch.h +++ b/packages/hal/i386/arch/current/include/hal_arch.h @@ -88,7 +88,7 @@ externC cyg_uint32 hal_msbit_index(cyg_u #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ CYG_MACRO_START \ - register CYG_WORD* _sp_ = ((CYG_WORD*)_sparg_); \ + register CYG_WORD* _sp_ = ((CYG_WORD*)((_sparg_) &~15)); \ register HAL_SavedRegisters *_regs_; \ \ /* The 'ret' executed at the end of hal_thread_load_context will */ \
--- a/packages/hal/i386/arch/current/src/i386.ld +++ b/packages/hal/i386/arch/current/src/i386.ld @@ -90,10 +90,10 @@ GROUP(libtarget.a libgcc.a) _EXCEPT_END_ = ABSOLUTE(.);} \ > _region_ +// Note: The __ in the name is an encoding of the . #define SECTION_rel__got(_region_, _vma_, _lma_) \ .rel.got _vma_ : _lma_ \ - { FORCE_OUTPUT; \ - *(.rel.got) } \ + { *(.rel.got) } \ > _region_ #define SECTION_data(_region_, _vma_, _lma_) \
--- a/packages/hal/i386/linux/current/ChangeLog +++ b/packages/hal/i386/linux/current/ChangeLog @@ -1,3 +1,10 @@ +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + PR 18956 + * include/pkgconf/mlt_i386_linux_ram.mlt: + * include/pkgconf/mlt_i386_linux_ram.ldi: + Fixed problem with rel_got. + Encode . in section name as __. + 1999-04-08 John Dallaway <jld@cygnus.co.uk> * include/pkgconf/mlt_*.*: Use double underscore substitution
--- a/packages/hal/i386/linux/current/include/pkgconf/mlt_i386_linux_ram.ldi +++ b/packages/hal/i386/linux/current/include/pkgconf/mlt_i386_linux_ram.ldi @@ -31,11 +31,6 @@ MEMORY ram : ORIGIN = 0x00000000, LENGTH = 0x800000 } -// The rel__got section doesn't result in any output but the linker -// complains if it is not present. It is necessary when compiling -// with CYGIMP_LIBC_MALLOC_CXX_DELETE_CALLS_FREE=true but causes -// problems with BFD when this option is false. - SECTIONS { SECTIONS_BEGIN @@ -46,7 +41,7 @@ SECTIONS SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) -// SECTION_rel__got (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rel__got (ram, ALIGN (0x1), LMA_EQ_VMA) SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA) SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
--- a/packages/hal/i386/linux/current/include/pkgconf/mlt_i386_linux_ram.mlt +++ b/packages/hal/i386/linux/current/include/pkgconf/mlt_i386_linux_ram.mlt @@ -6,7 +6,8 @@ section fini 0 4 0 1 0 1 0 1 rodata1 rod section rodata1 0 8 0 1 0 1 0 1 rodata rodata ! section rodata 0 8 0 1 0 1 0 1 fixup fixup ! section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! -section gcc_except_table 0 1 0 1 0 1 0 1 data data ! +section gcc_except_table 0 1 0 1 0 1 0 1 rel__got rel__got ! +section rel__got 0 1 0 1 0 1 0 1 data data ! section data 0 8 0 1 0 1 0 1 sbss sbss ! section sbss 0 4 0 1 0 1 0 1 bss bss ! section bss 0 10 0 1 0 0 0 0 !
--- a/packages/hal/mips/arch/current/ChangeLog +++ b/packages/hal/mips/arch/current/ChangeLog @@ -1,3 +1,141 @@ +1999-05-12 Nick Garnett <nickg@cygnus.co.uk> + + The following have been merged from a branch: + + (1999-05-11 Nick Garnett <nickg@cygnus.co.uk>) + + * include/hal_arch.h: + * include/hal_intr.h: + * include/hal_cache.h: + * include/arch.inc: + Changed references to "imp" and "implementation" to "var" and + "variant" respectively. These are better names for these files and + functions. + + * src/vectors.S: + Removed or disabled some development/debug code. + Same imp->var changes as above. + + (1999-05-06 Nick Garnett <nickg@cygnus.co.uk>) + + * src/vectors.S: Added call to hal_cpu_except_enable in + __default_exception_vsr to re-enable nested exceptions. + + * src/mips-stub.c: Use _registers[X] rather that register[X] for + accessing CPU registers, since the former may point to per-thread + register sets while the latter only refers to the current trap + register set. + + * include/arch.inc: Added hal_cpu_except_enable macro to + (re-)enable exception processing and disable interrupts. This is + necessary if we are to allow nested exceptions (like breakpoints + in exception handlers). + + (1999-04-29 Nick Garnett <nickg@cygnus.co.uk>) + + * src/vectors.S: Reenable interrupts while processing exceptions. + Several temporary kludges to permit us to test ROM code from RAM + under PMON. + + * include/mips.inc: Extended list of CP0 register aliases. + + + * include/arch.inc: Added generic version of hal_cache_init to + disable kseg0 caching in config0 register. + + * include/hal_cache.h: Moved dummy addresses used in index + operations to 0x80000000, zero caused MMU exceptions. + Fixed looping bugs in all macros that use them. + + (1999-04-28 Gary Thomas <gthomas@cygnus.co.uk>) + + [v1_2_2_beta branch] + * src/vectors.S: Add dummy "__gccmain()" + + (1999-04-27 Gary Thomas <gthomas@cygnus.co.uk>) + + * include/hal_arch.h: Make minimum stack sizes more realistic. + Also fix size of interrupt stack frame when FPU present. + + (1999-04-23 Nick Garnett <nickg@cygnus.co.uk>) + + * src/vectors.S: Added support for floating point register save + and restore. Fixed hal_interrupt_stack_call_pending_DSRs to use + hal_cpu_int_merge macro. + + * src/context.S: Added support for floating point register save + and restore. Started some preparations for 64 bit processor + support. + + * include/mips.inc: Added floating point register aliases. Moved + saved state to arch.inc. + + * include/hal_arch.h: Completed support for floating point state + save and restore. Parameterized GDB support macros a little to + enable GDB to work properly. + + * include/arch.inc: Added support for floating point state save + and restore. Moved assembler version of saved state layout here + from mips.inc. + + (1999-04-22 Nick Garnett <nickg@cygnus.co.uk>) + + * src/context.S (hal_thread_load_context): Substituted explicit + code to reload the interrupt enable state with a macro. + + * include/hal_cache.h: Removed default implementations of + HAL_[D/I]CACHE_[EN/DIS]ABLE since these were actually TX39 + specific. There is aparrently no standard way of implementing + these function in the MIPS architecture. + + * include/mips.inc: Added a comment to point out a TX39-only + register. + + * src/vectors.S: Modified hal_interrupt_stack_call_pending_DSRs() + to also call DSRs with interrupts enabled. Returns interrupt state + to original value when finished. + Use hal_cpu_int_ensable macro in place of explicit code in + hal_interrupt_stack_call_pending_DSRs(). + + (1999-04-21 Nick Garnett <nickg@cygnus.co.uk>) + + * include/arch.inc: Ifdeffed definition of hal_intc_init macro to + allow it to be defined elsewhere. Added default versions of diag + macros. + + * src/vectors.S: Added some low-level diagnostic macros to show + HAL events if there is adequate hardware (such as leds). + Removed interrupt enable/disables in interrupt processing since we + can now go through a thread switch with interrupts disabled. + Ifdeffed ISR tables so they can be defined elsewhere. + Added implementation of hal_interrupt_stack_call_pending_DSRs. + Added calls to implementation and platform init routines. + + * src/hal_misc.c: Many changes to hal_idle_thread_action() to + print or instrument various CPU registers. Left with code to + wiggle an led in the idle loop. + Stripped out TX39 specific code and moved it to plf_misc.c. + + * src/context.S: Added code to save and restore the interrupt mask + state in thread contexts. + + * include/hal_intr.h: + Renamed default interrupts to match the hardware more closely. + Added ifdef around HAL_TRANSLATE_VECTOR() so it can be made + platform/variant specific. Added implementation of + HAL_INTERRUPT_ACKNOWLEDGE(). + + * include/hal_arch.h (HAL_THREAD_INIT_CONTEXT): Aligned the + intitial stack pointer to 16 byte boundary, added an initial value + for the status register. + + * include/arch.inc: Added some nops to eret macros. + + (1999-04-13 John Dallaway <jld@cygnus.co.uk>) + + * src/mips.ld: Migrate global MIPS linker script to individual + MIPS variant directories + 1999-04-30 Hugo Tyson <hmt@cygnus.co.uk> Merge the following changes from the 1.2.1 release branch,
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/arch/current/include/arch.inc @@ -0,0 +1,551 @@ +#ifndef CYGONCE_HAL_ARCH_INC +#define CYGONCE_HAL_ARCH_INC +##============================================================================= +## +## arch.inc +## +## MIPS assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors: nickg +## Date: 1997-10-16 +## Purpose: Architecture definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the MIPS CPU family. +## Usage: +## #include <cyg/hal/arch.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <cyg/hal/mips.inc> + +#include <cyg/hal/variant.inc> + +##----------------------------------------------------------------------------- +## Set up the value for the initial status register + +#ifndef INITIAL_SR + +#if defined(CYG_HAL_STARTUP_RAM) +# if defined(CYG_HAL_MIPS_SIM) || !defined(CYG_HAL_USE_ROM_MONITOR) +# define INITIAL_SR 0x1000ff00 /* CP0 usable, Ints enabled */ +# else +# define INITIAL_SR 0x1040ff00 /* as above + ROM vectors used */ +# endif +#elif defined(CYG_HAL_STARTUP_ROM) +# define INITIAL_SR 0x1040ff00 /* as above + ROM vectors used */ +#endif + +#endif + +##----------------------------------------------------------------------------- +## MIPS thread and interrupt saved state. This must match the layout of the +## HAL_SavedRegisters in hal_arch.h. Do not change this without changing the +## layout there, or viceversa. + +#ifdef CYGHWR_HAL_MIPS_64BIT +# define mips_regsize 8 +#else +# define mips_regsize 4 +#endif + +#if defined(CYGHWR_HAL_MIPS_FPU) +# if defined(CYGHWR_HAL_MIPS_FPU_64BIT) +# define mips_fpuregsize 8 +# elif defined(CYGHWR_HAL_MIPS_FPU_32BIT) +# define mips_fpuregsize 4 +# else +# error MIPS FPU register size not defined +# endif +#endif + + +#define mipsreg_regs 0 +#define mipsreg_hi (mips_regsize*32) +#define mipsreg_lo (mipsreg_hi+mips_regsize) +#ifdef CYGHWR_HAL_MIPS_FPU +# define mipsreg_fpureg (mipsreg_lo+mips_regsize) +# define mipsreg_fcr31 (mipsreg_fpureg+(mips_fpuregsize*32)) +# define mipsreg_fppad (mipsreg_fcr31+mips_regsize) +# define mipsreg_vector (mipsreg_fppad+mips_regsize) +#else +# define mipsreg_vector (mipsreg_lo+mips_regsize) +#endif +#define mipsreg_pc (mipsreg_vector+mips_regsize) +#define mipsreg_sr (mipsreg_pc+mips_regsize) +#define mipsreg_cache (mipsreg_sr+mips_regsize) +#define mipsreg_cause (mipsreg_cache+mips_regsize) +#define mipsreg_badvr (mipsreg_cause+mips_regsize) +#define mipsreg_prid (mipsreg_badvr+mips_regsize) +#define mipsreg_config (mipsreg_prid+mips_regsize) +#define mipsreg_size (mipsreg_config+mips_regsize) + +#define mips_exception_decrement (mipsreg_size*2) + +##----------------------------------------------------------------------------- +## Minimal stack frame size uses to call functions from asm. + +#define mips_stack_frame_size 32 // 4 (64 bit) args worth + + +##----------------------------------------------------------------------------- +## CPU specific macros. These provide a common assembler interface to +## operations that may have CPU specific implementations on different +## variants of the architecture. + + # Initialize CPU + .macro hal_cpu_init + mtc0 zero,cause # zero cause reg + nop + la v0,INITIAL_SR # initialize status register + mtc0 v0,status + nop + nop + nop + + .endm + + # Enable interrupts +#ifdef CYG_HAL_MIPS_R3900 + .macro hal_cpu_int_enable + mfc0 v0,status + nop + nop + ori v0,v0,0x0001 # set IE bit + mtc0 v0,status + nop + nop + nop + .endm +#else + .macro hal_cpu_int_enable + mfc0 v0,status + la v1,0xFFFFFFF9 + and v0,v0,v1 # clear EXL and ERL bits + ori v0,v0,0x0001 # set IE bit + mtc0 v0,status + nop + nop + nop + .endm +#endif + + + # Disable interrupts + .macro hal_cpu_int_disable + mfc0 v0,status + la v1,0xFFFFFFFE + and v0,v0,v1 + mtc0 v0,status + nop + nop + nop + .endm + + # Merge the interrupt enable state of the status register in + # \sr with the current sr. +#ifdef CYG_HAL_MIPS_R3900 +#define HAL_SR_INT_MASK 0x00000001 // IEc only +#else +#define HAL_SR_INT_MASK 0x00000007 // IE, EXL, ERL +#endif + .macro hal_cpu_int_merge sr + mfc0 v0,status # V0 = current SR + la v1,HAL_SR_INT_MASK # V1 = SR interrupt bits mask + and \sr,\sr,v1 # Isolate interrupt bits of \sr + nor v1,v1,zero # Invert mask + and v0,v0,v1 # V0 = current SR except int bits + or v0,v0,\sr # V0 = New SR + mtc0 v0,status # Return to SR + .endm + + # Enable further exception processing, and disable + # interrupt processing. +#ifdef CYG_HAL_MIPS_R3900 + .macro hal_cpu_except_enable + hal_cpu_int_disable + .endm +#else + .macro hal_cpu_except_enable + mfc0 v0,status + la v1,0xFFFFFFF0 + and v0,v0,v1 # clear EXL, ERL and IE bits + mtc0 v0,status + nop + nop + nop + .endm +#endif + + # Return from exception. +#ifdef CYG_HAL_MIPS_R3900 + .macro hal_cpu_eret pc,sr + mtc0 \sr,status # Load status register + nop + nop + nop + sync # settle things down + jr \pc # jump back to interrupted code + rfe # restore state (delay slot) + .endm +#else + .macro hal_cpu_eret pc,sr + mtc0 \pc,epc # put PC in EPC + nop + nop + nop + mtc0 \sr,status # put SR back + nop + nop + nop + sync # settle things down + eret # return + nop # just to be safe + .endm +#endif + +##----------------------------------------------------------------------------- +# Default MIPS interrupt decoding macros. This uses the basic interrupt +# support provided by CP0 in the cause and status registers. If there is +# a more complex external interrupt controller, or the default stuff is +# interpreted differently (as in the TX3904) then these macros will be +# overridden and CYGPKG_HAL_MIPS_INTC_DEFINED will be defined. + +#ifndef CYGPKG_HAL_MIPS_INTC_DEFINED + +#ifndef CYGPKG_HAL_MIPS_INTC_INIT_DEFINED + # initialize all interrupts to disabled + .macro hal_intc_init + mfc0 v0,status + nop + lui v1,0xFFFF + ori v1,v1,0x00FF + and v0,v0,v1 # clear the IntMask bits + mtc0 v0,status + nop + nop + nop + .endm +#endif + + .macro hal_intc_decode vnum + mfc0 v0,cause # get cause register + nop # delay slot + srl v0,v0,10 # shift interrupt bits down + andi v0,v0,0x7f # isolate 6 interrupt bits + la v1,hal_intc_translation_table + add v0,v0,v1 # index into table + lb \vnum,0(v0) # pick up vector number + .endm + + .macro hal_intc_decode_data +hal_intc_translation_table: + .byte 0, 0, 1, 0 + .byte 2, 0, 1, 0 + .byte 3, 0, 1, 0 + .byte 2, 0, 1, 0 + .byte 4, 0, 1, 0 + .byte 2, 0, 1, 0 + .byte 3, 0, 1, 0 + .byte 2, 0, 1, 0 + .byte 5, 0, 1, 0 + .byte 2, 0, 1, 0 + .byte 3, 0, 1, 0 + .byte 2, 0, 1, 0 + .byte 4, 0, 1, 0 + .byte 2, 0, 1, 0 + .byte 3, 0, 1, 0 + .byte 2, 0, 1, 0 + .endm +#endif + +#------------------------------------------------------------------------------ +# FPU macros. +# The MIPS floating point unit essentially operates in two modes. In the first +# it supplies 32 32bit FP registers that may be paired into 16 64 bit registers. +# In the second it supplies 32 64bit registers. Which mode is to be used depends +# not only on the specific implementation in use, but also on the setting of the +# FR bit in the status register (if it is implemented) and on the expectations of +# the toolchain. + +#ifndef CYGPKG_HAL_MIPS_FPU_DEFINED + +#ifdef CYGHWR_HAL_MIPS_FPU + +#if defined(CYGHWR_HAL_MIPS_FPU_64BIT) +#define sfpr sdc1 +#define lfpr ldc1 +#define CYG_HAL_MIPS_FPU_SR_INIT 0x24000000 +#elif defined(CYGHWR_HAL_MIPS_FPU_32BIT) +#define sfpr swc1 +#define lfpr lwc1 +#define CYG_HAL_MIPS_FPU_SR_INIT 0x20000000 +#else +#error MIPS FPU register size not defined +#endif + + .macro hal_fpu_init + mfc0 v0,status # Get sr + la v1,0xDBFFFFFF # Clear bits to be changed + and v0,v0,v1 + la v1,CYG_HAL_MIPS_FPU_SR_INIT # Set the bits we want + or v0,v0,v1 # Set sr to required value + mtc0 v0,status # return to sr + nop + nop + nop + ctc1 zero,$31 # clear Fp control reg + nop + .endm + + # Save the caller-saved registers as defined by the ABI. + # These only really need saving during interrupts. + .macro hal_fpu_save_caller regs + sfpr f0,(mipsreg_fpureg+0*mips_fpuregsize)(\regs) + sfpr f1,(mipsreg_fpureg+1*mips_fpuregsize)(\regs) + sfpr f2,(mipsreg_fpureg+2*mips_fpuregsize)(\regs) + sfpr f3,(mipsreg_fpureg+3*mips_fpuregsize)(\regs) + sfpr f4,(mipsreg_fpureg+4*mips_fpuregsize)(\regs) + sfpr f5,(mipsreg_fpureg+5*mips_fpuregsize)(\regs) + sfpr f6,(mipsreg_fpureg+6*mips_fpuregsize)(\regs) + sfpr f7,(mipsreg_fpureg+7*mips_fpuregsize)(\regs) + sfpr f8,(mipsreg_fpureg+8*mips_fpuregsize)(\regs) + sfpr f9,(mipsreg_fpureg+9*mips_fpuregsize)(\regs) + sfpr f10,(mipsreg_fpureg+10*mips_fpuregsize)(\regs) + sfpr f11,(mipsreg_fpureg+11*mips_fpuregsize)(\regs) + sfpr f12,(mipsreg_fpureg+12*mips_fpuregsize)(\regs) + sfpr f13,(mipsreg_fpureg+13*mips_fpuregsize)(\regs) + sfpr f14,(mipsreg_fpureg+14*mips_fpuregsize)(\regs) + sfpr f15,(mipsreg_fpureg+15*mips_fpuregsize)(\regs) + sfpr f16,(mipsreg_fpureg+16*mips_fpuregsize)(\regs) + sfpr f17,(mipsreg_fpureg+17*mips_fpuregsize)(\regs) + sfpr f18,(mipsreg_fpureg+18*mips_fpuregsize)(\regs) + sfpr f19,(mipsreg_fpureg+19*mips_fpuregsize)(\regs) + sfpr f31,(mipsreg_fpureg+31*mips_fpuregsize)(\regs) + cfc1 v0,$31 + sw v0,mipsreg_fcr31(\regs) + .endm + + # Save the callee-saved registers as defined by the ABI. + # These are the only registers that need to be saved + # across thread switches. + .macro hal_fpu_save_callee regs + sfpr f20,(mipsreg_fpureg+20*mips_fpuregsize)(\regs) + sfpr f21,(mipsreg_fpureg+21*mips_fpuregsize)(\regs) + sfpr f22,(mipsreg_fpureg+22*mips_fpuregsize)(\regs) + sfpr f23,(mipsreg_fpureg+23*mips_fpuregsize)(\regs) + sfpr f24,(mipsreg_fpureg+24*mips_fpuregsize)(\regs) + sfpr f25,(mipsreg_fpureg+25*mips_fpuregsize)(\regs) + sfpr f26,(mipsreg_fpureg+26*mips_fpuregsize)(\regs) + sfpr f27,(mipsreg_fpureg+27*mips_fpuregsize)(\regs) + sfpr f28,(mipsreg_fpureg+28*mips_fpuregsize)(\regs) + sfpr f29,(mipsreg_fpureg+29*mips_fpuregsize)(\regs) + sfpr f30,(mipsreg_fpureg+30*mips_fpuregsize)(\regs) + .endm + + # General macro to save everything + .macro hal_fpu_save regs + hal_fpu_save_callee \regs + hal_fpu_save_caller \regs + .endm + + # Reload the caller-saved registers. + .macro hal_fpu_load_caller regs + lw v0,mipsreg_fcr31(\regs) + ctc1 v0,$31 + lfpr f0,(mipsreg_fpureg+0*mips_fpuregsize)(\regs) + lfpr f1,(mipsreg_fpureg+1*mips_fpuregsize)(\regs) + lfpr f2,(mipsreg_fpureg+2*mips_fpuregsize)(\regs) + lfpr f3,(mipsreg_fpureg+3*mips_fpuregsize)(\regs) + lfpr f4,(mipsreg_fpureg+4*mips_fpuregsize)(\regs) + lfpr f5,(mipsreg_fpureg+5*mips_fpuregsize)(\regs) + lfpr f6,(mipsreg_fpureg+6*mips_fpuregsize)(\regs) + lfpr f7,(mipsreg_fpureg+7*mips_fpuregsize)(\regs) + lfpr f8,(mipsreg_fpureg+8*mips_fpuregsize)(\regs) + lfpr f9,(mipsreg_fpureg+9*mips_fpuregsize)(\regs) + lfpr f10,(mipsreg_fpureg+10*mips_fpuregsize)(\regs) + lfpr f11,(mipsreg_fpureg+11*mips_fpuregsize)(\regs) + lfpr f12,(mipsreg_fpureg+12*mips_fpuregsize)(\regs) + lfpr f13,(mipsreg_fpureg+13*mips_fpuregsize)(\regs) + lfpr f14,(mipsreg_fpureg+14*mips_fpuregsize)(\regs) + lfpr f15,(mipsreg_fpureg+15*mips_fpuregsize)(\regs) + lfpr f16,(mipsreg_fpureg+16*mips_fpuregsize)(\regs) + lfpr f17,(mipsreg_fpureg+17*mips_fpuregsize)(\regs) + lfpr f18,(mipsreg_fpureg+18*mips_fpuregsize)(\regs) + lfpr f19,(mipsreg_fpureg+19*mips_fpuregsize)(\regs) + lfpr f31,(mipsreg_fpureg+31*mips_fpuregsize)(\regs) + .endm + + # Reload the callee-saved registers. + .macro hal_fpu_load_callee regs + lfpr f20,(mipsreg_fpureg+20*mips_fpuregsize)(\regs) + lfpr f21,(mipsreg_fpureg+21*mips_fpuregsize)(\regs) + lfpr f22,(mipsreg_fpureg+22*mips_fpuregsize)(\regs) + lfpr f23,(mipsreg_fpureg+23*mips_fpuregsize)(\regs) + lfpr f24,(mipsreg_fpureg+24*mips_fpuregsize)(\regs) + lfpr f25,(mipsreg_fpureg+25*mips_fpuregsize)(\regs) + lfpr f26,(mipsreg_fpureg+26*mips_fpuregsize)(\regs) + lfpr f27,(mipsreg_fpureg+27*mips_fpuregsize)(\regs) + lfpr f28,(mipsreg_fpureg+28*mips_fpuregsize)(\regs) + lfpr f29,(mipsreg_fpureg+29*mips_fpuregsize)(\regs) + lfpr f30,(mipsreg_fpureg+30*mips_fpuregsize)(\regs) + .endm + + # Reload everything. + .macro hal_fpu_load regs + hal_fpu_load_caller \regs + hal_fpu_load_callee \regs + .endm +#else + + # Default macros for non-fpu implementations + + .macro hal_fpu_init + .endm + + .macro hal_fpu_save regs + .endm + + .macro hal_fpu_save_caller regs + .endm + + .macro hal_fpu_save_callee regs + .endm + + .macro hal_fpu_load_caller regs + .endm + + .macro hal_fpu_load_callee regs + .endm + + .macro hal_fpu_load regs + .endm + +#endif + +#endif + +#------------------------------------------------------------------------------ +# MMU macros. + +#ifndef CYGPKG_HAL_MIPS_MMU_DEFINED + + .macro hal_mmu_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# MEMC macros. + +#ifndef CYGPKG_HAL_MIPS_MEMC_DEFINED + + .macro hal_memc_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# Cache macros. + +#ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED + +#ifdef CYG_HAL_MIPS_R3900 + .macro hal_cache_init + mfc0 v0,config # disable cache in config register + nop + nop + la v1,0xffffffcf + and v0,v0,v1 + mtc0 v0,config + nop + nop + nop + .endm +#else + .macro hal_cache_init + mfc0 v0,config0 # disable Kseg0 caching in config0 register + nop + nop + la v1,0xfffffff8 + and v0,v0,v1 + ori v0,v0,2 + mtc0 v0,config0 + nop + nop + nop + .endm +#endif + +#endif + +#------------------------------------------------------------------------------ +# Diagnostics macros. + +#ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED + + .macro hal_diag_init + .endm + + .macro hal_diag_excpt_start + .endm + + .macro hal_diag_intr_start + .endm + + .macro hal_diag_restore + .endm +#endif + +#------------------------------------------------------------------------------ +# Timer initialization. + +#ifndef CYGPKG_HAL_MIPS_TIMER_DEFINED + + .macro hal_timer_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# Monitor initialization. + +#ifndef CYGPKG_HAL_MIPS_MON_DEFINED + + .macro hal_mon_init + .endm + +#endif + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_ARCH_INC +# end of arch.inc
--- a/packages/hal/mips/arch/current/include/basetype.h +++ b/packages/hal/mips/arch/current/include/basetype.h @@ -41,10 +41,15 @@ //####DESCRIPTIONEND#### // +#include <pkgconf/hal.h> + //----------------------------------------------------------------------------- // Characterize the architecture -#define CYG_BYTEORDER CYG_MSBFIRST // Big endian +#if 0 +#else +# define CYG_BYTEORDER CYG_MSBFIRST // Big endian +#endif //----------------------------------------------------------------------------- // MIPS does not usually use labels with undersores. Some labels generated
--- a/packages/hal/mips/arch/current/include/hal_arch.h +++ b/packages/hal/mips/arch/current/include/hal_arch.h @@ -45,31 +45,50 @@ #include <pkgconf/hal.h> #include <cyg/infra/cyg_type.h> +#include <cyg/hal/var_arch.h> + //-------------------------------------------------------------------------- // Processor saved states: // The layout of this structure is also defined in "mips.inc", for assembly // code. Do not change this without changing that (or vice versa). +#if defined(CYGHWR_HAL_MIPS_FPU) +# if defined(CYGHWR_HAL_MIPS_FPU_64BIT) +# define CYG_HAL_FPU_REG CYG_WORD64 +# elif defined(CYGHWR_HAL_MIPS_FPU_32BIT) +# define CYG_HAL_FPU_REG CYG_WORD32 +# else +# error MIPS FPU register size not defined +# endif +#endif + typedef struct { // These are common to all saved states - cyg_uint32 d[32]; /* Data regs */ - cyg_uint32 hi; /* hi word of mpy/div reg */ - cyg_uint32 lo; /* lo word of mpy/div reg */ - + CYG_ADDRWORD d[32]; /* Data regs */ + CYG_ADDRWORD hi; /* hi word of mpy/div reg */ + CYG_ADDRWORD lo; /* lo word of mpy/div reg */ +#ifdef CYGHWR_HAL_MIPS_FPU + CYG_HAL_FPU_REG f[32]; /* FPU registers */ + CYG_ADDRWORD fcr31; /* FPU control/status register */ + CYG_ADDRWORD fppad; /* Dummy location to make this */ + /* structure a multiple of 8 */ + /* bytes long. */ +#endif + // These are only saved for exceptions and interrupts - cyg_uint32 vector; /* Vector number */ - cyg_uint32 pc; /* Program Counter */ - cyg_uint32 sr; /* Status Reg */ - cyg_uint32 cache; /* Cache control register */ + CYG_ADDRWORD vector; /* Vector number */ + CYG_ADDRWORD pc; /* Program Counter */ + CYG_ADDRWORD sr; /* Status Reg */ + CYG_ADDRWORD cache; /* Cache control register */ // These are only saved for exceptions, and are not restored // when continued. - cyg_uint32 cause; /* Exception cause register */ - cyg_uint32 badvr; /* Bad virtual address reg */ - cyg_uint32 prid; /* Processor Version */ - cyg_uint32 config; /* Config register */ + CYG_ADDRWORD cause; /* Exception cause register */ + CYG_ADDRWORD badvr; /* Bad virtual address reg */ + CYG_ADDRWORD prid; /* Processor Version */ + CYG_ADDRWORD config; /* Config register */ } HAL_SavedRegisters; //-------------------------------------------------------------------------- @@ -93,20 +112,35 @@ externC cyg_uint32 hal_msbit_index(cyg_u //-------------------------------------------------------------------------- // Context Initialization + + +// Optional FPU context initialization +#ifdef CYGHWR_HAL_MIPS_FPU +#define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ ) \ +{ \ + for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->f[_i_] = (_id_)|_i_; \ + (_regs_)->fcr31 = 0; \ +} +#else +#define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ ) +#endif + + // Initialize the context of a thread. // Arguments: // _sparg_ name of variable containing current sp, will be written with new sp // _thread_ thread object address, passed as argument to entry point // _entry_ entry point address. // _id_ bit pattern used in initializing registers, for debugging. - #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ { \ register CYG_WORD _sp_ = ((CYG_WORD)_sparg_)-56; \ register HAL_SavedRegisters *_regs_; \ int _i_; \ - _regs_ = (HAL_SavedRegisters *)((_sp_) - sizeof(HAL_SavedRegisters)); \ + _sp_ = _sp_ & 0xFFFFFFF0; \ + _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters))&0xFFFFFFF0); \ for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->d[_i_] = (_id_)|_i_; \ + HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ ); \ (_regs_)->d[29] = (CYG_WORD)(_sp_); /* SP = top of stack */ \ (_regs_)->d[04] = (CYG_WORD)(_thread_); /* R4 = arg1 = thread ptr */ \ (_regs_)->lo = 0; /* LO = 0 */ \ @@ -114,6 +148,7 @@ externC cyg_uint32 hal_msbit_index(cyg_u (_regs_)->d[30] = (CYG_WORD)(_sp_); /* FP = top of stack */ \ (_regs_)->d[31] = (CYG_WORD)(_entry_); /* LR(d[31]) = entry point*/ \ (_regs_)->pc = (CYG_WORD)(_entry_); /* PC = entry point */ \ + (_regs_)->sr = 0x00000001; /* SR = ls 3 bits only */ \ _sparg_ = (CYG_ADDRESS)_regs_; \ } @@ -151,31 +186,11 @@ externC void hal_thread_load_context( CY // HAL_BREAKINST is the value of the breakpoint instruction and // HAL_BREAKINST_SIZE is its size in bytes. -#ifdef CYG_HAL_MIPS_SIM -#define HAL_BREAKPOINT(_label_) \ - /* This code causes a fake breakpoint. */ \ - asm volatile ( \ - "lui $24,0x0000;" \ - "ori $24,0x0024;" \ - "mtc0 $24,$13;" \ - "lui $25,%%hi(1f);" \ - "ori $25,$25,%%lo(1f);" \ - "j other_vector;" \ - "nop;" \ - ".global " #_label_ ";" \ - #_label_":" \ - "1: nop;" \ - : \ - : \ - : "t8", "t9" \ - ); -#else #define HAL_BREAKPOINT(_label_) \ asm volatile (" .globl " #_label_ ";" \ #_label_":" \ " break 5" \ ); -#endif // CYG_HAL_MIPS_SIM #define HAL_BREAKINST 0x0005000d @@ -184,33 +199,38 @@ asm volatile (" .globl " #_label_ ";" //-------------------------------------------------------------------------- // Thread register state manipulation for GDB support. +// Default to a 32 bit register size for GDB register dumps. +#ifndef CYG_HAL_GDB_REG +#define CYG_HAL_GDB_REG CYG_WORD32 +#endif + // Translate a stack pointer as saved by the thread context macros above into // a pointer to a HAL_SavedRegisters structure. -#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ +#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ (_regs_) = (HAL_SavedRegisters *)(_sp_) // Copy a set of registers from a HAL_SavedRegisters structure into a // GDB ordered array. -#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \ -{ \ - CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ - int _i_; \ - \ - for( _i_ = 0; _i_ < 32; _i_++ ) \ - _regval_[_i_] = (_regs_)->d[_i_]; \ - \ - _regval_[32] = (_regs_)->sr; \ - _regval_[33] = (_regs_)->lo; \ - _regval_[34] = (_regs_)->hi; \ - _regval_[35] = (_regs_)->badvr; \ - _regval_[36] = (_regs_)->cause; \ - _regval_[37] = (_regs_)->pc; \ +#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \ +{ \ + CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \ + int _i_; \ + \ + for( _i_ = 0; _i_ < 32; _i_++ ) \ + _regval_[_i_] = (_regs_)->d[_i_]; \ + \ + _regval_[32] = (_regs_)->sr; \ + _regval_[33] = (_regs_)->lo; \ + _regval_[34] = (_regs_)->hi; \ + _regval_[35] = (_regs_)->badvr; \ + _regval_[36] = (_regs_)->cause; \ + _regval_[37] = (_regs_)->pc; \ } // Copy a GDB ordered array into a HAL_SavedRegisters structure. #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ { \ - CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ + CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \ int _i_; \ \ for( _i_ = 0; _i_ < 32; _i_++ ) \ @@ -276,11 +296,23 @@ externC void hal_idle_thread_action(cyg_ // This is not a config option because it should not be adjusted except // under "enough rope" sort of disclaimers. -// Worst case stack frame size: return link + 5 pushed registers. -#define CYGNUM_HAL_STACK_FRAME_SIZE (24) +// Typical case stack frame size: return link + 4 pushed registers + some locals. +#define CYGNUM_HAL_STACK_FRAME_SIZE (48) // Stack needed for a context switch: -#define CYGNUM_HAL_STACK_CONTEXT_SIZE (42*4) +#if defined(CYGHWR_HAL_MIPS_FPU) +# if defined(CYGHWR_HAL_MIPS_FPU_64BIT) +#define CYGNUM_HAL_STACK_CONTEXT_SIZE (((32+12)*4)+(32*8)) +# elif defined(CYGHWR_HAL_MIPS_FPU_32BIT) +#define CYGNUM_HAL_STACK_CONTEXT_SIZE (((32+12)*4)+(32*4)) +# else +# error MIPS FPU register size not defined +# endif +#else +#define CYGNUM_HAL_STACK_CONTEXT_SIZE ((32+10)*4) +#endif + + // Interrupt + call to ISR, interrupt_end() and the DSR #define CYGNUM_HAL_STACK_INTERRUPT_SIZE (4+2*CYGNUM_HAL_STACK_CONTEXT_SIZE) @@ -293,7 +325,7 @@ externC void hal_idle_thread_action(cyg_ #define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+ \ CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+ \ - CYGNUM_HAL_STACK_FRAME_SIZE*4) + CYGNUM_HAL_STACK_FRAME_SIZE*8) #define CYGNUM_HAL_STACK_SIZE_TYPICAL (2048) #else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
--- a/packages/hal/mips/arch/current/include/hal_cache.h +++ b/packages/hal/mips/arch/current/include/hal_cache.h @@ -50,13 +50,19 @@ #include <pkgconf/hal.h> #include <cyg/infra/cyg_type.h> +#include <cyg/hal/var_cache.h> + //============================================================================= -// MIPS simulator - -#ifdef CYG_HAL_MIPS_SIM +// Default Implementation. This uses the standard MIPS CP0 registers and +// cache instructions. Note that not all variants will have all of the +// functionality defined here. //----------------------------------------------------------------------------- -// Cache dimensions +// Cache dimensions. +// These really should be defined in var_cache.h. If they are not, then provide +// a set of numbers that are typical of many variants. + +#ifndef HAL_DCACHE_SIZE // Data cache #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes @@ -71,20 +77,46 @@ #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) +#endif + //----------------------------------------------------------------------------- // Global control of data cache // Enable the data cache +// There is no default mechanism for enabling or disabling the caches. +#ifndef HAL_DCACHE_ENABLE_DEFINED #define HAL_DCACHE_ENABLE() +#endif // Disable the data cache +#ifndef HAL_DCACHE_DISABLE_DEFINED #define HAL_DCACHE_DISABLE() +#endif // Invalidate the entire cache -#define HAL_DCACHE_INVALIDATE_ALL() +// We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this +// is not quite what we want, but there is no index-invalidate operation +// available. +#ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED +#define HAL_DCACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC() +#endif // Synchronize the contents of the cache with memory. -#define HAL_DCACHE_SYNC() +// This uses the index-writeback-invalidate operation. +#ifndef HAL_DCACHE_SYNC_DEFINED +#define HAL_DCACHE_SYNC() \ +{ \ + register CYG_ADDRESS _baddr_ = 0x80000000; \ + register CYG_ADDRESS _addr_ = 0x80000000; \ + register CYG_WORD _size_ = HAL_DCACHE_SIZE; \ + HAL_DCACHE_DISABLE(); \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { \ + asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); \ + } \ + HAL_DCACHE_ENABLE(); \ +} +#endif // Set the data cache refill burst size //#define HAL_DCACHE_BURST_SIZE(_size_) @@ -97,13 +129,34 @@ // Load the contents of the given address range into the data cache // and then lock the cache so that it stays there. -//#define HAL_DCACHE_LOCK(_base_, _size_) +// This uses the fetch-and-lock cache operation. +#ifndef HAL_DCACHE_LOCK_DEFINED +#define HAL_DCACHE_LOCK(_base_, _asize_) \ +CYG_MACRO_START \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + HAL_DCACHE_DISABLE(); \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { \ + asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); \ + } \ + HAL_DCACHE_ENABLE(); \ +CYG_MACRO_END +#endif -// Undo a previous lock operation -//#define HAL_DCACHE_UNLOCK(_base_, _size_) +// Undo a previous lock operation. +// Do this by flushing the cache, which is defined to clear the lock bit. +#ifndef HAL_DCACHE_UNLOCK_DEFINED +#define HAL_DCACHE_UNLOCK(_base_, _size_) \ + HAL_DCACHE_FLUSH( _base_, _size_ ) +#endif // Unlock entire cache -//#define HAL_DCACHE_UNLOCK_ALL() +#ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED +#define HAL_DCACHE_UNLOCK_ALL() \ + HAL_DCACHE_INVALIDATE_ALL() +#endif //----------------------------------------------------------------------------- // Data cache line control @@ -114,13 +167,55 @@ // Write dirty cache lines to memory and invalidate the cache entries // for the given address range. -//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) +// This uses the hit-writeback-invalidate cache operation. +#ifndef HAL_DCACHE_FLUSH_DEFINED +#define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \ +{ \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + HAL_DCACHE_DISABLE(); \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { \ + asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); \ + } \ + HAL_DCACHE_ENABLE(); \ +} +#endif // Invalidate cache lines in the given range without writing to memory. -//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) +// This uses the hit-invalidate cache operation. +#ifndef HAL_DCACHE_INVALIDATE_DEFINED +#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \ +{ \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + HAL_DCACHE_DISABLE(); \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { \ + asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); \ + } \ + HAL_DCACHE_ENABLE(); \ +} +#endif // Write dirty cache lines to memory for the given address range. -//#define HAL_DCACHE_STORE( _base_ , _size_ ) +// This uses the hit-writeback cache operation. +#ifndef HAL_DCACHE_STORE_DEFINED +#define HAL_DCACHE_STORE( _base_ , _asize_ ) \ +{ \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + HAL_DCACHE_DISABLE(); \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { \ + asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); \ + } \ + HAL_DCACHE_ENABLE(); \ +} +#endif // Preread the given range into the cache with the intention of reading // from it later. @@ -137,26 +232,65 @@ // Global control of Instruction cache // Enable the instruction cache +// There is no default mechanism for enabling or disabling the caches. +#ifndef HAL_ICACHE_ENABLE_DEFINED #define HAL_ICACHE_ENABLE() +#endif // Disable the instruction cache +#ifndef HAL_ICACHE_DISABLE_DEFINED #define HAL_ICACHE_DISABLE() +#endif // Invalidate the entire cache -#define HAL_ICACHE_INVALIDATE_ALL() +// This uses the index-invalidate cache operation. +#ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED +#define HAL_ICACHE_INVALIDATE_ALL() \ +{ \ + register CYG_ADDRESS _baddr_ = 0x80000000; \ + register CYG_ADDRESS _addr_ = 0x80000000; \ + HAL_ICACHE_DISABLE(); \ + for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ + { \ + asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \ + } \ + HAL_ICACHE_ENABLE(); \ +} +#endif // Synchronize the contents of the cache with memory. -#define HAL_ICACHE_SYNC() +// Simply force the cache to reload. +#ifndef HAL_ICACHE_SYNC_DEFINED +#define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL() +#endif // Set the instruction cache refill burst size //#define HAL_ICACHE_BURST_SIZE(_size_) // Load the contents of the given address range into the instruction cache // and then lock the cache so that it stays there. -//#define HAL_ICACHE_LOCK(_base_, _size_) +// This uses the fetch-and-lock cache operation. +#ifndef HAL_ICACHE_LOCK_DEFINED +#define HAL_ICACHE_LOCK(_base_, _asize_) \ +CYG_MACRO_START \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + HAL_DCACHE_DISABLE(); \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { \ + asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); \ + } \ + HAL_DCACHE_ENABLE(); \ +CYG_MACRO_END +#endif -// Undo a previous lock operation -//#define HAL_ICACHE_UNLOCK(_base_, _size_) +// Undo a previous lock operation. +// Do this by invalidating the cache, which is defined to clear the lock bit. +#ifndef HAL_ICACHE_UNLOCK_DEFINED +#define HAL_ICACHE_UNLOCK(_base_, _size_) \ + HAL_ICACHE_INVALIDATE( _base_, _size_ ) +#endif // Unlock entire cache //#define HAL_ICACHE_UNLOCK_ALL() @@ -165,252 +299,20 @@ // Instruction cache line control // Invalidate cache lines in the given range without writing to memory. -//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) - -#endif - - -//============================================================================= -// Toshiba TX3904 - -#ifdef CYG_HAL_MIPS_TX3904 - -//----------------------------------------------------------------------------- -// Cache dimensions - -// Data cache -#define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes -#define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line -#define HAL_DCACHE_WAYS 2 // Associativity of the cache - -// Instruction cache -#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes -#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line -#define HAL_ICACHE_WAYS 1 // Associativity of the cache - -#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) -#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) - -//----------------------------------------------------------------------------- -// Global control of data cache - -// Enable the data cache -#define HAL_DCACHE_ENABLE() \ -{ \ - asm volatile ("mfc0 $2,$3;" \ - "ori $2,$2,0x0010;" \ - "mtc0 $2,$3;" \ - : \ - : \ - : "$2" \ - ); \ - \ -} - -// Disable the data cache -#define HAL_DCACHE_DISABLE() \ -{ \ - asm volatile ("mfc0 $2,$3;" \ - "la $3,0xFFFFFFEF;" \ - "and $2,$2,$3;" \ - "mtc0 $2,$3;" \ - : \ - : \ - : "$2", "$3" \ - ); \ - \ -} - -// Invalidate the entire cache -// The TX39 only has hit-invalidate on the DCACHE, not -// index-invalidate, so we cannot just empty the cache out without -// knowing what is in it. This is annoying. So, the best we can do is -// fill the cache with data that is unlikely to be there -// otherwise. Hence we read bytes from the ROM space since this is -// most likely to be code, and will not get out of sync even if it is not. -#define HAL_DCACHE_INVALIDATE_ALL() \ -{ \ - CYG_BYTE volatile *addr = (CYG_BYTE *)(0x9fc00000); \ - CYG_BYTE volatile tmp = 0; \ - int i; \ - for( i = 0; i < (HAL_DCACHE_SIZE*2); i += HAL_DCACHE_LINE_SIZE ) \ - { \ - tmp = addr[i]; \ - } \ -} - -// Synchronize the contents of the cache with memory. -#define HAL_DCACHE_SYNC() HAL_DCACHE_INVALIDATE_ALL() - -// Set the data cache refill burst size -//#define HAL_DCACHE_BURST_SIZE(_size_) - -// Set the data cache write mode -//#define HAL_DCACHE_WRITE_MODE( _mode_ ) - -//#define HAL_DCACHE_WRITETHRU_MODE 0 -//#define HAL_DCACHE_WRITEBACK_MODE 1 - -// Load the contents of the given address range into the data cache -// and then lock the cache so that it stays there. -#define HAL_DCACHE_LOCK(_base_, _size_) \ -{ \ - asm volatile ("mfc0 $2,$7;" \ - "ori $2,$2,0x0100;" \ - "mtc0 $2,$7;" \ - : \ - : \ - : "$2" \ - ); \ -} - -// Undo a previous lock operation -#define HAL_DCACHE_UNLOCK(_base_, _size_) \ -{ \ - asm volatile ("mfc0 $2,$7;" \ - "la $3,0xFFFFFEFF;" \ - "and $2,$2,$3;" \ - "mtc0 $2,$7;" \ - : \ - : \ - : "$2", "$3" \ - ); \ -} - -// Unlock entire cache -#define HAL_DCACHE_UNLOCK_ALL() - -//----------------------------------------------------------------------------- -// Data cache line control - -// Allocate cache lines for the given address range without reading its -// contents from memory. -//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) - -// Write dirty cache lines to memory and invalidate the cache entries -// for the given address range. -//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) - -// Invalidate cache lines in the given range without writing to memory. -#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \ +// This uses the hit-invalidate cache operation. +#ifndef HAL_ICACHE_INVALIDATE_DEFINED +#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ { \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ register CYG_WORD _size_ = (_asize_); \ HAL_DCACHE_DISABLE(); \ - for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ { \ - asm volatile ("cache 17,0(%0)" : : "r"(_addr_) ); \ + asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); \ } \ HAL_DCACHE_ENABLE(); \ } - -// Write dirty cache lines to memory for the given address range. -//#define HAL_DCACHE_STORE( _base_ , _size_ ) - -// Preread the given range into the cache with the intention of reading -// from it later. -//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) - -// Preread the given range into the cache with the intention of writing -// to it later. -//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) - -// Allocate and zero the cache lines associated with the given range. -//#define HAL_DCACHE_ZERO( _base_ , _size_ ) - -//----------------------------------------------------------------------------- -// Global control of Instruction cache - -// Enable the instruction cache -#define HAL_ICACHE_ENABLE() \ -{ \ - asm volatile ("mfc0 $2,$3;" \ - "ori $2,$2,0x0020;" \ - "mtc0 $2,$3;" \ - : \ - : \ - : "$2" \ - ); \ - \ -} - -// Disable the instruction cache -#define HAL_ICACHE_DISABLE() \ -{ \ - asm volatile ("mfc0 $2,$3;" \ - "la $3,0xFFFFFFDF;" \ - "and $2,$2,$3;" \ - "mtc0 $2,$3;" \ - : \ - : \ - : "$2", "$3" \ - ); \ - \ -} - -// Invalidate the entire cache -#define HAL_ICACHE_INVALIDATE_ALL() \ -{ \ - register CYG_ADDRESS _addr_; \ - HAL_ICACHE_DISABLE(); \ - for( _addr_ = 0; _addr_ < HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \ - } \ - HAL_ICACHE_ENABLE(); \ -} - -// Synchronize the contents of the cache with memory. -#define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL() - -// Set the instruction cache refill burst size -//#define HAL_ICACHE_BURST_SIZE(_size_) - -// Load the contents of the given address range into the instruction cache -// and then lock the cache so that it stays there. -#define HAL_ICACHE_LOCK(_base_, _size_) \ -{ \ - asm volatile ("mfc0 $2,$7;" \ - "ori $2,$2,0x0200;" \ - "mtc0 $2,$7;" \ - : \ - : \ - : "$2" \ - ); \ -} - -// Undo a previous lock operation -#define HAL_ICACHE_UNLOCK(_base_, _size_) \ -{ \ - asm volatile ("mfc0 $2,$7;" \ - "la $3,0xFFFFFDFF;" \ - "and $2,$2,$3;" \ - "mtc0 $2,$7;" \ - : \ - : \ - : "$2", "$3" \ - ); \ -} - -// Unlock entire cache -#define HAL_ICACHE_UNLOCK_ALL() - -//----------------------------------------------------------------------------- -// Instruction cache line control - -// Invalidate cache lines in the given range without writing to memory. -#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ -{ \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - HAL_ICACHE_DISABLE(); \ - for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ - { \ - asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \ - } \ - HAL_ICACHE_ENABLE(); \ -} - #endif //-----------------------------------------------------------------------------
--- a/packages/hal/mips/arch/current/include/hal_intr.h +++ b/packages/hal/mips/arch/current/include/hal_intr.h @@ -54,6 +54,8 @@ #include <cyg/infra/cyg_type.h> #include <cyg/hal/hal_io.h> +#include <cyg/hal/var_intr.h> + //-------------------------------------------------------------------------- // MIPS vectors. @@ -88,12 +90,14 @@ #define CYGNUM_HAL_VECTOR_OVERFLOW 12 // Reserved #define CYGNUM_HAL_VECTOR_RESERVED_13 13 -// Floating point exception - not applicable yet -// #define CYGNUM_HAL_VECTOR_FPE 15 +// Floating point exception +#ifdef CYGHWR_HAL_MIPS_FPU +#define CYGNUM_HAL_VECTOR_FPE 15 +#endif #define CYGNUM_HAL_VSR_MIN 0 -#define CYGNUM_HAL_VSR_MAX 13 -#define CYGNUM_HAL_VSR_COUNT 14 +#define CYGNUM_HAL_VSR_MAX 15 +#define CYGNUM_HAL_VSR_COUNT 16 // Exception vectors. These are the values used when passed out to an // external exception handler using cyg_hal_deliver_exception() @@ -121,38 +125,33 @@ #define CYGNUM_HAL_EXCEPTION_MAX 13 #define CYGNUM_HAL_EXCEPTION_COUNT 13 -// Interrupt vectors. + +#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED -#if defined(CYG_HAL_MIPS_TX3904) || defined(CYG_HAL_MIPS_SIM) - -// These are decoded via the IP bits of the cause -// register when an external interrupt is delivered. +// the default for all MIPS variants is to use the 6 bits +// in the cause register. -#define CYGNUM_HAL_INTERRUPT_1 0 -#define CYGNUM_HAL_INTERRUPT_2 1 -#define CYGNUM_HAL_INTERRUPT_3 2 -#define CYGNUM_HAL_INTERRUPT_4 3 -#define CYGNUM_HAL_INTERRUPT_5 4 -#define CYGNUM_HAL_INTERRUPT_6 5 -#define CYGNUM_HAL_INTERRUPT_7 6 -#define CYGNUM_HAL_INTERRUPT_DMAC1_CH3 7 -#define CYGNUM_HAL_INTERRUPT_DMAC1_CH2 8 -#define CYGNUM_HAL_INTERRUPT_DMAC0_CH1 9 -#define CYGNUM_HAL_INTERRUPT_DMAC0_CH0 10 -#define CYGNUM_HAL_INTERRUPT_SIO_0 11 -#define CYGNUM_HAL_INTERRUPT_SIO_1 12 -#define CYGNUM_HAL_INTERRUPT_TMR_0 13 -#define CYGNUM_HAL_INTERRUPT_TMR_1 14 -#define CYGNUM_HAL_INTERRUPT_TMR_2 15 -#define CYGNUM_HAL_INTERRUPT_0 16 +#define CYGNUM_HAL_INTERRUPT_0 0 +#define CYGNUM_HAL_INTERRUPT_1 1 +#define CYGNUM_HAL_INTERRUPT_2 2 +#define CYGNUM_HAL_INTERRUPT_3 3 +#define CYGNUM_HAL_INTERRUPT_4 4 +#define CYGNUM_HAL_INTERRUPT_5 5 // Min/Max ISR numbers and how many there are #define CYGNUM_HAL_ISR_MIN 0 -#define CYGNUM_HAL_ISR_MAX 16 -#define CYGNUM_HAL_ISR_COUNT 17 +#define CYGNUM_HAL_ISR_MAX 5 +#define CYGNUM_HAL_ISR_COUNT 6 -// The vector used by the Real time clock -#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TMR_0 +// The vector used by the Real time clock. The default here is to use +// interrupt 5, which is connected to the counter/comparator registers +// in many MIPS variants. + +#ifndef CYGNUM_HAL_INTERRUPT_RTC +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_5 +#endif + +#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED #endif @@ -179,8 +178,9 @@ typedef cyg_uint32 CYG_INTERRUPT_STATE; //-------------------------------------------------------------------------- // Interrupt control macros -// Beware of the nops in this code. These fill load/store delay slots to -// prevent following code being run in the wrong state. +// Beware of nops in this code. They fill delay slots and avoid CP0 hazards +// that might otherwise cause following code to run in the wrong state or +// cause a resource conflict. #define HAL_DISABLE_INTERRUPTS(_old_) \ { \ @@ -240,6 +240,8 @@ typedef cyg_uint32 CYG_INTERRUPT_STATE; // For chained interrupts we only have a single vector though which all // are passed. For unchained interrupts we have a vector per interrupt. +#ifndef HAL_TRANSLATE_VECTOR + #if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN) #define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0 @@ -250,6 +252,8 @@ typedef cyg_uint32 CYG_INTERRUPT_STATE; #endif +#endif + //-------------------------------------------------------------------------- // Interrupt and VSR attachment macros @@ -318,173 +322,122 @@ CYG_MACRO_END //-------------------------------------------------------------------------- // Interrupt controller access - -#if defined(CYG_HAL_MIPS_TX3904) || defined(CYG_HAL_MIPS_SIM) +// The default code here simply uses the fields present in the CP0 status +// and cause registers to implement this functionality. +// Beware of nops in this code. They fill delay slots and avoid CP0 hazards +// that might otherwise cause following code to run in the wrong state or +// cause a resource conflict. -#define CYG_HAL_MIPS_TX3904_ILR0 0xFFFFC010 -#define CYG_HAL_MIPS_TX3904_CConR 0xFFFFE000 - -// Array which stores the configured priority levels for the configured -// interrupts. -externC volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT]; - +#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED -#define HAL_INTERRUPT_MASK( _vector_ ) \ -{ \ - HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \ - CYG_WORD32 _ilr_; \ - _reg_ += (_vector_)&0xC; \ - HAL_READ_UINT32( _reg_, _ilr_ ); \ - _ilr_ &= ~(7 << (((_vector_)&0x3)<<3)); \ - HAL_WRITE_UINT32( _reg_, _ilr_ ); \ -} - -#define HAL_INTERRUPT_UNMASK( _vector_ ) \ -{ \ - HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \ - CYG_WORD32 _ilr_; \ - _reg_ += (_vector_)&0xC; \ - HAL_READ_UINT32( _reg_, _ilr_ ); \ - _ilr_ |= hal_interrupt_level[_vector_] << (((_vector_)&0x3)<<3); \ - HAL_WRITE_UINT32( _reg_, _ilr_ ); \ -} +#define HAL_INTERRUPT_MASK( _vector_ ) \ +CYG_MACRO_START \ + asm volatile ( \ + "mfc0 $3,$12\n" \ + "la $2,0x00000400\n" \ + "sllv $2,$2,%0\n" \ + "nor $2,$2,$0\n" \ + "and $3,$3,$2\n" \ + "mtc0 $3,$12\n" \ + "nop; nop; nop\n" \ + : \ + : "r"(_vector_) \ + : "$2", "$3" \ + ); \ +CYG_MACRO_END -#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ -{ \ - if( _vector_ <= CYGNUM_HAL_INTERRUPT_7 || \ - _vector_ == CYGNUM_HAL_INTERRUPT_0 ) \ - { \ - cyg_uint32 _val_ = _vector_ + 1; \ - if( _val_ == CYGNUM_HAL_INTERRUPT_0 + 1 ) _val_ = 0; \ - HAL_WRITE_UINT8( CYG_HAL_MIPS_TX3904_CConR+1, _val_); \ - } \ -} +#define HAL_INTERRUPT_UNMASK( _vector_ ) \ +CYG_MACRO_START \ + asm volatile ( \ + "mfc0 $3,$12\n" \ + "la $2,0x00000400\n" \ + "sllv $2,$2,%0\n" \ + "or $3,$3,$2\n" \ + "mtc0 $3,$12\n" \ + "nop; nop; nop\n" \ + : \ + : "r"(_vector_) \ + : "$2", "$3" \ + ); \ +CYG_MACRO_END -#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ -{ \ - if( _vector_ <= CYGNUM_HAL_INTERRUPT_7 || \ - _vector_ == CYGNUM_HAL_INTERRUPT_0 ) \ - { \ - cyg_uint32 _val_ = 0; \ - if( _up_ ) _val_ |= 1; \ - if( !(_level_) ) _val_ |= 2; \ - HAL_WRITE_UINT16( CYG_HAL_MIPS_TX3904_CConR+2, _val_ ); \ - } \ -} +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ +CYG_MACRO_START \ + asm volatile ( \ + "mfc0 $3,$13\n" \ + "la $2,0x00000400\n" \ + "sllv $2,$2,%0\n" \ + "nor $2,$2,$0\n" \ + "and $3,$3,$2\n" \ + "mtc0 $3,$13\n" \ + "nop; nop; nop\n" \ + : \ + : "r"(_vector_) \ + : "$2", "$3" \ + ); \ +CYG_MACRO_END -#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ -{ \ - HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \ - CYG_WORD32 _ilr_; \ - _reg_ += (_vector_)&0xC; \ - HAL_READ_UINT32( _reg_, _ilr_ ); \ - _ilr_ |= (_level_) << (((_vector_)&0x3)<<3); \ - HAL_WRITE_UINT32( _reg_, _ilr_ ); \ - hal_interrupt_level[_vector_] = _level_; \ -} +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) -#else +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) -#error Unspecified platform for MIPS +#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED #endif //-------------------------------------------------------------------------- -// Clock control - -#if defined(CYG_HAL_MIPS_TX3904) || defined(CYG_HAL_MIPS_SIM) +// Clock control. +// This code uses the count and compare registers that are present in many +// MIPS variants. +// Beware of nops in this code. They fill delay slots and avoid CP0 hazards +// that might otherwise cause following code to run in the wrong state or +// cause a resource conflict. -#define CYG_HAL_MIPS_TX3904_TIMER_BASE 0xFFFFF000 -#define CYG_HAL_MIPS_TX3904_TIMER_CR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x00) -#define CYG_HAL_MIPS_TX3904_TIMER_SR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x04) -#define CYG_HAL_MIPS_TX3904_TIMER_CPR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x08) -#define CYG_HAL_MIPS_TX3904_TIMER_IMR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x10) -#define CYG_HAL_MIPS_TX3904_TIMER_DR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x20) -#define CYG_HAL_MIPS_TX3904_TIMER_RR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0xF0) - -#define HAL_CLOCK_INITIALIZE( _period_ ) \ -{ \ - HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_DR, 0x00000003 ); \ - HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_CPR, _period_ ); \ - HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_SR, 0x00000000 ); \ - HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_IMR, 0x00008001 ); \ - HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_CR, 0x000000C0 ); \ -} +#ifndef CYGHWR_HAL_CLOCK_CONTROL_DEFINED -#define HAL_CLOCK_RESET( _vector_, _period_ ) \ -{ \ - HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_SR, 0x00000000 ); \ -} - -#if defined(CYGHWR_HAL_MIPS_TX3904_TRR_REQUIRES_SYNC) && \ - !defined(CYG_HAL_MIPS_SIM) - -// We need to sync and check the coprocessor 0 condition - this indicates -// whether data is present in the write buffer. We need to wait until -// that data to be written is flushed out. This works around a tx39 bug. -// gcc will insert a NOP after the asm insns. - -# define HAL_CLOCK_READ( _pvalue_ ) \ -CYG_MACRO_START \ - asm volatile ( \ - "sync; nop; 1: ; bc0f 1b" \ - : \ - : \ - : "$0" \ - ); \ - HAL_READ_UINT32( CYG_HAL_MIPS_TX3904_TIMER_RR, *(_pvalue_) ); \ +#define HAL_CLOCK_INITIALIZE( _period_ ) \ +CYG_MACRO_START \ + asm volatile ( \ + "mtc0 $0,$9\n" \ + "nop; nop; nop\n" \ + "mtc0 %0,$11\n" \ + "nop; nop; nop\n" \ + : \ + : "r"(_period_) \ + ); \ CYG_MACRO_END -#else +#define HAL_CLOCK_RESET( _vector_, _period_ ) \ +CYG_MACRO_START \ + asm volatile ( \ + "mtc0 $0,$9\n" \ + "nop; nop; nop\n" \ + "mtc0 %0,$11\n" \ + "nop; nop; nop\n" \ + : \ + : "r"(_period_) \ + ); \ +CYG_MACRO_END -# define HAL_CLOCK_READ( _pvalue_ ) \ -CYG_MACRO_START \ - HAL_READ_UINT32( CYG_HAL_MIPS_TX3904_TIMER_RR, *(_pvalue_) ); \ +#define HAL_CLOCK_READ( _pvalue_ ) \ +CYG_MACRO_START \ + register CYG_WORD32 result; \ + asm volatile ( \ + "mfc0 %0,$9\n" \ + : "=r"(result) \ + ); \ + *(_pvalue_) = result; \ CYG_MACRO_END +#define CYGHWR_HAL_CLOCK_CONTROL_DEFINED + #endif -#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY +#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \ + !defined(HAL_CLOCK_LATENCY) #define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_) #endif -#else - -#error Unspecified platform for MIPS - -#endif - -//-------------------------------------------------------------------------- -// Timeout exception support. This is only enabled on the real TX39 hardware. - -#if defined(CYG_HAL_MIPS_TX3904) - -#define HAL_TX39_DEBUG_TOE_ENABLE() \ -{ \ - HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_CConR; \ - CYG_WORD32 _cconr_; \ - HAL_READ_UINT32( _reg_, _cconr_); \ - _cconr_ |= 0x04000000; \ - HAL_WRITE_UINT32( _reg_, _cconr_); \ -} - -#define HAL_TX39_DEBUG_TOE_DISABLE() \ -{ \ - HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_CConR; \ - CYG_WORD32 _cconr_; \ - HAL_READ_UINT32( _reg_, _cconr_); \ - _cconr_ &= 0xFBFFFFFF; \ - HAL_WRITE_UINT32( _reg_, _cconr_); \ -} - -#else - -#define HAL_TX39_DEBUG_TOE_ENABLE() - -#define HAL_TX39_DEBUG_TOE_DISABLE() - -#endif - //-------------------------------------------------------------------------- #endif // ifndef CYGONCE_HAL_HAL_INTR_H // End of hal_intr.h
--- a/packages/hal/mips/arch/current/include/mips-stub.h +++ b/packages/hal/mips/arch/current/include/mips-stub.h @@ -16,9 +16,11 @@ * they apply. */ +#include <pkgconf/system.h> + #define NUMREGS 90 -#ifdef __mips64 +#if defined(__mips64) #define REGSIZE(X) 8 typedef unsigned long long target_register_t; #else
--- a/packages/hal/mips/arch/current/include/mips.inc +++ b/packages/hal/mips/arch/current/include/mips.inc @@ -1,3 +1,6 @@ +#ifndef CYGONCE_HAL_MIPS_INC +#define CYGONCE_HAL_MIPS_INC + ##============================================================================= ## ## mips.inc @@ -81,33 +84,73 @@ #define ra $31 /* return address */ #define pc $pc /* pc, used on mips16 */ -#define config $3 // Configuration register -#define cache $7 // Cache control -#define badvr $8 // Bad virtual address -#define sr $12 // Status register -#define cause $13 // Exception cause -#define epc $14 // Exception pc value -#define prid $15 // processor ID +#define f0 $f0 +#define f1 $f1 +#define f2 $f2 +#define f3 $f3 +#define f4 $f4 +#define f5 $f5 +#define f6 $f6 +#define f7 $f7 +#define f8 $f8 +#define f9 $f9 +#define f10 $f10 +#define f11 $f11 +#define f12 $f12 +#define f13 $f13 +#define f14 $f14 +#define f15 $f15 +#define f16 $f16 +#define f17 $f17 +#define f18 $f18 +#define f19 $f19 +#define f20 $f20 +#define f21 $f21 +#define f22 $f22 +#define f23 $f23 +#define f24 $f24 +#define f25 $f25 +#define f26 $f26 +#define f27 $f27 +#define f28 $f28 +#define f29 $f29 +#define f30 $f30 +#define f31 $f31 -##----------------------------------------------------------------------------- -## MIPS saved state - -#define mipsreg_regs 0 -#define mipsreg_hi (4*32) -#define mipsreg_lo (mipsreg_hi+4) -#define mipsreg_vector (mipsreg_lo+4) -#define mipsreg_pc (mipsreg_vector+4) -#define mipsreg_sr (mipsreg_pc+4) -#define mipsreg_cache (mipsreg_sr+4) -#define mipsreg_cause (mipsreg_cache+4) -#define mipsreg_badvr (mipsreg_cause+4) -#define mipsreg_prid (mipsreg_badvr+4) -#define mipsreg_config (mipsreg_prid+4) -#define mipsreg_size (mipsreg_config+4) +// Coprocessor 0 registers -#define mips_exception_decrement (mipsreg_size*2) +#define index $0 // TLB entry index register +#define random $1 // TLB random index register +#define tlblo0 $2 // TLB even page entry register +#define tlblo1 $3 // TLB odd page entry register +#define config $3 // Configuration register (TX39 only) +#define context $4 // TLB context register +#define pagemask $5 // TLB page size mask +#define wired $6 // TLB wired boundary +#define cache $7 // Cache control +#define badvr $8 // Bad virtual address +#define count $9 // Timer cycle count register +#define tlbhi $10 // TLB virtual address match register +#define compare $11 // Timer compare register +#define status $12 // Status register +#define cause $13 // Exception cause +#define epc $14 // Exception pc value +#define prid $15 // processor ID +#define config0 $16 // Config register 0 -#define mips_stack_frame_size 24 // 3 (64 bit) args worth #------------------------------------------------------------------------------ + +#define FUNC_START(name) \ + .type name,@function; \ + .globl name; \ + .ent name; \ +name: + +#define FUNC_END(name) \ +name##_end: \ + .end name \ + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_MIPS_INC # end of mips.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/arch/current/include/pkgconf/hal_mips.h @@ -0,0 +1,85 @@ +#ifndef CYGONCE_PKGCONF_HAL_MIPS_H +#define CYGONCE_PKGCONF_HAL_MIPS_H +// ==================================================================== +// +// pkgconf/hal_mips.h +// +// HAL configuration file +// +// ==================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Contributors: bartv +// Date: 1998-09-02 +// Purpose: To allow the user to edit HAL configuration options. +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + + +/* --------------------------------------------------------------------- + {{CFG_DATA + + cdl_package CYGPKG_HAL_MIPS { + display "MIPS architecture" + type radio + parent CYGPKG_HAL + description " + The MIPS architecture HAL package provides generic support + for this processor architecture. It is also necessary to + select a CPU variant and a specific target platform HAL + package." + } + + cdl_component CYGFUN_HAL_MIPS_VARIANTS { + display "MIPS variants" + type dummy + parent CYGPKG_HAL_MIPS + description " + A number MIPS variants are supported." + } + + cdl_option CYGHWR_HAL_MIPS_CPU_FREQ { + display "CPU frequency" + type count + legal_values 0 to 1000000 + parent CYGPKG_HAL_MIPS + description " + This option contains the frequency of the CPU in MegaHertz. + Choose the frequency to match the processor you have. This + may affect thing like serial device, interval clock and + memory access speed settings." + } + + }}CFG_DATA */ + +#define CYGHWR_HAL_MIPS_CPU_FREQ 50 + +/* -------------------------------------------------------------------*/ +#endif /* CYGONCE_PKGCONF_HAL_MIPS_H */ +/* EOF hal_mips.h */
deleted file mode 100644 --- a/packages/hal/mips/arch/current/include/pkgconf/hal_tx39.h +++ /dev/null @@ -1,103 +0,0 @@ -#ifndef CYGONCE_PKGCONF_HAL_TX39_H -#define CYGONCE_PKGCONF_HAL_TX39_H -// ==================================================================== -// -// pkgconf/hal_tx39.h -// -// HAL configuration file -// -// ==================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Cygnus eCos Public License -// Version 1.0 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://sourceware.cygnus.com/ecos -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Cygnus Operating System, released -// September 30, 1998. -// -// The Initial Developer of the Original Code is Cygnus. Portions created -// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -// ==================================================================== -//#####DESCRIPTIONBEGIN#### -// -// Author(s): bartv -// Contributors: bartv -// Date: 1998-09-02 -// Purpose: To allow the user to edit HAL configuration options. -// Description: -// -//####DESCRIPTIONEND#### -// -// ==================================================================== - - -/* --------------------------------------------------------------------- - {{CFG_DATA - - cdl_package CYGPKG_HAL_TX39 { - display "TX39 architecture" - type radio - parent CYGPKG_HAL - target tx39 - description " - The TX39 architecture HAL package provides generic support - for this processor architecture. It is also necessary to - select a specific target platform HAL package." - } - - cdl_option CYGHWR_HAL_MIPS_CPU_FREQ { - display "CPU frequency" - type count - legal_values 0 to 1000000 - parent CYGPKG_HAL_TX39 - description " - This option contains the frequency of the CPU in MegaHertz. - Choose the frequency to match the processor you have. This - may affect thing like serial device, interval clock and - memory access speed settings." - } - - }}CFG_DATA */ - - -#define CYGHWR_HAL_MIPS_CPU_FREQ 50 - -/* NO CDL for this because we want it enabled always. */ -#define CYGDBG_HAL_MIPS_INSTALL_CTRL_C_ISR - -/* -------------------------------------------------------------------*/ -/* Workaround for TX3904 Timer TRR register problem */ -/* */ -/* We do it conditionally so that it is possible to override it on */ -/* the command line, for example, for a simulator build */ -#ifndef CYGARC_TX39_PR19846 -# define CYGHWR_HAL_MIPS_TX3904_TRR_REQUIRES_SYNC -#endif - - -/* -------------------------------------------------------------------*/ -/* translate the user defined CPU frequency into a the real number of */ -/* cycles. */ - -#if (CYGHWR_HAL_MIPS_CPU_FREQ == 50) -#define CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL 49152000 -#elif (CYGHWR_HAL_MIPS_CPU_FREQ == 66) -#define CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL 66355200 -#else -#error Unsupported TX39 CPU frequency -#endif - -/* -------------------------------------------------------------------*/ -#endif /* CYGONCE_PKGCONF_HAL_TX39_H */ -/* EOF hal_tx39.h */
--- a/packages/hal/mips/arch/current/src/PKGconf.mak +++ b/packages/hal/mips/arch/current/src/PKGconf.mak @@ -28,15 +28,15 @@ #####COPYRIGHTEND#### #============================================================================== -PACKAGE := hal_tx39 +PACKAGE := hal_mips include ../../../../../pkgconf/pkgconf.mak LIBRARY := libtarget.a COMPILE := hal_misc.c context.S mips-stub.c OTHER_OBJS := -OTHER_TARGETS := vectors.stamp ldscript.stamp -OTHER_DEPS := $(PACKAGE)_vectors.d ldscript.d -OTHER_CLEAN := vectors.clean ldscript.clean +OTHER_TARGETS := vectors.stamp +OTHER_DEPS := $(PACKAGE)_vectors.d +OTHER_CLEAN := vectors.clean include $(COMPONENT_REPOSITORY)/pkgconf/makrules.src @@ -50,17 +50,3 @@ vectors.clean: $(PACKAGE)_vectors.o: $(BUILD_TREE)/pkgconf/pkgconf.mak \ $(BUILD_TREE)/pkgconf/makevars $(PACKAGE_RULES_FILE) - -.PHONY: ldscript.clean - -ldscript.stamp: tx39.ld - $(CC) -E -P -Wp,-MD,ldscript.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $(PREFIX)/lib/target.ld $< - @echo > ldscript.d - @echo $@ ':' $< '\' >> ldscript.d - @tail +2 ldscript.tmp >> ldscript.d - @rm ldscript.tmp - $(TOUCH) $@ - -ldscript.clean: - $(RM) -f $(PREFIX)/lib/target.ld - $(RM) -f ldscript.stamp
--- a/packages/hal/mips/arch/current/src/context.S +++ b/packages/hal/mips/arch/current/src/context.S @@ -42,7 +42,7 @@ #include <pkgconf/hal.h> -#include <cyg/hal/mips.inc> +#include <cyg/hal/arch.inc> .set noat @@ -59,39 +59,39 @@ hal_thread_switch_context: # store GPRs #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM - sw $0,(mipsreg_regs+0*4)(sp) - sw $1,(mipsreg_regs+1*4)(sp) - sw $2,(mipsreg_regs+2*4)(sp) - sw $3,(mipsreg_regs+3*4)(sp) - sw $4,(mipsreg_regs+4*4)(sp) - sw $5,(mipsreg_regs+5*4)(sp) - sw $6,(mipsreg_regs+6*4)(sp) - sw $7,(mipsreg_regs+7*4)(sp) - sw $8,(mipsreg_regs+8*4)(sp) - sw $9,(mipsreg_regs+9*4)(sp) - sw $10,(mipsreg_regs+10*4)(sp) - sw $11,(mipsreg_regs+11*4)(sp) - sw $12,(mipsreg_regs+12*4)(sp) - sw $13,(mipsreg_regs+13*4)(sp) - sw $14,(mipsreg_regs+14*4)(sp) - sw $15,(mipsreg_regs+15*4)(sp) - sw $24,(mipsreg_regs+24*4)(sp) - sw $25,(mipsreg_regs+25*4)(sp) - sw $28,(mipsreg_regs+28*4)(sp) # == GP + sw $0,(mipsreg_regs+0*mips_regsize)(sp) + sw $1,(mipsreg_regs+1*mips_regsize)(sp) + sw $2,(mipsreg_regs+2*mips_regsize)(sp) + sw $3,(mipsreg_regs+3*mips_regsize)(sp) + sw $4,(mipsreg_regs+4*mips_regsize)(sp) + sw $5,(mipsreg_regs+5*mips_regsize)(sp) + sw $6,(mipsreg_regs+6*mips_regsize)(sp) + sw $7,(mipsreg_regs+7*mips_regsize)(sp) + sw $8,(mipsreg_regs+8*mips_regsize)(sp) + sw $9,(mipsreg_regs+9*mips_regsize)(sp) + sw $10,(mipsreg_regs+10*mips_regsize)(sp) + sw $11,(mipsreg_regs+11*mips_regsize)(sp) + sw $12,(mipsreg_regs+12*mips_regsize)(sp) + sw $13,(mipsreg_regs+13*mips_regsize)(sp) + sw $14,(mipsreg_regs+14*mips_regsize)(sp) + sw $15,(mipsreg_regs+15*mips_regsize)(sp) + sw $24,(mipsreg_regs+24*mips_regsize)(sp) + sw $25,(mipsreg_regs+25*mips_regsize)(sp) + sw $28,(mipsreg_regs+28*mips_regsize)(sp) # == GP #endif - sw $16,(mipsreg_regs+16*4)(sp) - sw $17,(mipsreg_regs+17*4)(sp) - sw $18,(mipsreg_regs+18*4)(sp) - sw $19,(mipsreg_regs+19*4)(sp) - sw $20,(mipsreg_regs+20*4)(sp) - sw $21,(mipsreg_regs+21*4)(sp) - sw $22,(mipsreg_regs+22*4)(sp) - sw $23,(mipsreg_regs+23*4)(sp) -# sw $26,(mipsreg_regs+26*4)(sp) # == K0 -# sw $27,(mipsreg_regs+27*4)(sp) # == K1 -# sw $29,(mipsreg_regs+29*4)(sp) # == SP - sw $30,(mipsreg_regs+30*4)(sp) # == FP - sw $31,(mipsreg_regs+31*4)(sp) # == RA + sw $16,(mipsreg_regs+16*mips_regsize)(sp) + sw $17,(mipsreg_regs+17*mips_regsize)(sp) + sw $18,(mipsreg_regs+18*mips_regsize)(sp) + sw $19,(mipsreg_regs+19*mips_regsize)(sp) + sw $20,(mipsreg_regs+20*mips_regsize)(sp) + sw $21,(mipsreg_regs+21*mips_regsize)(sp) + sw $22,(mipsreg_regs+22*mips_regsize)(sp) + sw $23,(mipsreg_regs+23*mips_regsize)(sp) +# sw $26,(mipsreg_regs+26*mips_regsize)(sp) # == K0 +# sw $27,(mipsreg_regs+27*mips_regsize)(sp) # == K1 +# sw $29,(mipsreg_regs+29*mips_regsize)(sp) # == SP + sw $30,(mipsreg_regs+30*mips_regsize)(sp) # == FP + sw $31,(mipsreg_regs+31*mips_regsize)(sp) # == RA sw $31,(mipsreg_pc)(sp) # == PC (to help with debugging) #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM @@ -103,9 +103,20 @@ hal_thread_switch_context: #endif + hal_fpu_save_callee sp + +#ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + + hal_fpu_save_caller sp + +#endif + addi t0,sp,mipsreg_size # save SP in reg dump - sw t0,(mipsreg_regs+29*4)(sp) + sw t0,(mipsreg_regs+29*mips_regsize)(sp) + mfc0 t1,status # Save status register + sw t1,mipsreg_sr(sp) + sw sp,0(a1) # save sp in save loc # Now load the destination thread by dropping through @@ -124,6 +135,14 @@ hal_thread_load_context: lw sp,0(a0) # load new SP directly #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + + hal_fpu_load_caller sp + +#endif + + hal_fpu_load_callee sp + +#ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM lw t0,mipsreg_hi(sp) # load HI and LO regs lw t1,mipsreg_lo(sp) @@ -131,47 +150,48 @@ hal_thread_load_context: mtlo t1 #endif - + # load GPRs -# lw $0,(mipsreg_regs+0*4)(sp) - lw $4,(mipsreg_regs+4*4)(sp) # A0, must load for thread startup +# lw $0,(mipsreg_regs+0*mips_regsize)(sp) + lw $4,(mipsreg_regs+4*mips_regsize)(sp) # A0, must load for thread startup #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM - lw $1,(mipsreg_regs+1*4)(sp) - lw $2,(mipsreg_regs+2*4)(sp) - lw $3,(mipsreg_regs+3*4)(sp) - lw $5,(mipsreg_regs+5*4)(sp) - lw $6,(mipsreg_regs+6*4)(sp) - lw $7,(mipsreg_regs+7*4)(sp) - lw $8,(mipsreg_regs+8*4)(sp) - lw $9,(mipsreg_regs+9*4)(sp) - lw $10,(mipsreg_regs+10*4)(sp) - lw $11,(mipsreg_regs+11*4)(sp) - lw $12,(mipsreg_regs+12*4)(sp) - lw $13,(mipsreg_regs+13*4)(sp) - lw $14,(mipsreg_regs+14*4)(sp) - lw $15,(mipsreg_regs+15*4)(sp) - lw $24,(mipsreg_regs+24*4)(sp) - lw $25,(mipsreg_regs+25*4)(sp) + lw $1,(mipsreg_regs+1*mips_regsize)(sp) + lw $2,(mipsreg_regs+2*mips_regsize)(sp) + lw $3,(mipsreg_regs+3*mips_regsize)(sp) + lw $5,(mipsreg_regs+5*mips_regsize)(sp) + lw $6,(mipsreg_regs+6*mips_regsize)(sp) + lw $7,(mipsreg_regs+7*mips_regsize)(sp) + lw $8,(mipsreg_regs+8*mips_regsize)(sp) + lw $9,(mipsreg_regs+9*mips_regsize)(sp) + lw $10,(mipsreg_regs+10*mips_regsize)(sp) + lw $11,(mipsreg_regs+11*mips_regsize)(sp) + lw $12,(mipsreg_regs+12*mips_regsize)(sp) + lw $13,(mipsreg_regs+13*mips_regsize)(sp) + lw $14,(mipsreg_regs+14*mips_regsize)(sp) + lw $15,(mipsreg_regs+15*mips_regsize)(sp) + lw $24,(mipsreg_regs+24*mips_regsize)(sp) + lw $25,(mipsreg_regs+25*mips_regsize)(sp) #endif - lw $16,(mipsreg_regs+16*4)(sp) - lw $17,(mipsreg_regs+17*4)(sp) - lw $18,(mipsreg_regs+18*4)(sp) - lw $19,(mipsreg_regs+19*4)(sp) - lw $20,(mipsreg_regs+20*4)(sp) - lw $21,(mipsreg_regs+21*4)(sp) - lw $22,(mipsreg_regs+22*4)(sp) - lw $23,(mipsreg_regs+23*4)(sp) -# lw $26,(mipsreg_regs+26*4)(sp) # == K0 -# lw $27,(mipsreg_regs+27*4)(sp) # == K1 -# lw $28,(mipsreg_regs+28*4)(sp) # == GP -# lw $29,(mipsreg_regs+29*4)(sp) # == SP - lw $30,(mipsreg_regs+30*4)(sp) # == FP - lw $31,(mipsreg_regs+31*4)(sp) # == RA + lw $16,(mipsreg_regs+16*mips_regsize)(sp) + lw $17,(mipsreg_regs+17*mips_regsize)(sp) + lw $18,(mipsreg_regs+18*mips_regsize)(sp) + lw $19,(mipsreg_regs+19*mips_regsize)(sp) + lw $20,(mipsreg_regs+20*mips_regsize)(sp) + lw $21,(mipsreg_regs+21*mips_regsize)(sp) + lw $22,(mipsreg_regs+22*mips_regsize)(sp) + lw $23,(mipsreg_regs+23*mips_regsize)(sp) +# lw $26,(mipsreg_regs+26*mips_regsize)(sp) # == K0 +# lw $27,(mipsreg_regs+27*mips_regsize)(sp) # == K1 +# lw $28,(mipsreg_regs+28*mips_regsize)(sp) # == GP +# lw $29,(mipsreg_regs+29*mips_regsize)(sp) # == SP + lw $30,(mipsreg_regs+30*mips_regsize)(sp) # == FP + lw $31,(mipsreg_regs+31*mips_regsize)(sp) # == RA - # Note that the following lw must go here and not - # in the jr delay slot, since it has a delay slot - # of its own. - lw sp,(mipsreg_regs+29*4)(sp) # load SP + lw a2,mipsreg_sr(sp) # A2 = saved SR + lw sp,(mipsreg_regs+29*mips_regsize)(sp) # SP = saved SP + + hal_cpu_int_merge a2 # Merge with current SR + jr ra # return via ra nop # delay slot - must be nop @@ -200,18 +220,18 @@ hal_thread_load_context: .globl hal_setjmp .ent hal_setjmp hal_setjmp: - sw $31,CYGARC_JMP_BUF_R31*4(a0) # ra (link) - sw $30,CYGARC_JMP_BUF_R30*4(a0) - sw $28,CYGARC_JMP_BUF_R28*4(a0) # gp, optimize out? - sw $23,CYGARC_JMP_BUF_R23*4(a0) - sw $22,CYGARC_JMP_BUF_R22*4(a0) - sw $21,CYGARC_JMP_BUF_R21*4(a0) - sw $20,CYGARC_JMP_BUF_R20*4(a0) - sw $19,CYGARC_JMP_BUF_R19*4(a0) - sw $18,CYGARC_JMP_BUF_R18*4(a0) - sw $17,CYGARC_JMP_BUF_R17*4(a0) - sw $16,CYGARC_JMP_BUF_R16*4(a0) - sw sp,CYGARC_JMP_BUF_SP*4(a0) # $29 + sw $31,CYGARC_JMP_BUF_R31*mips_regsize(a0) # ra (link) + sw $30,CYGARC_JMP_BUF_R30*mips_regsize(a0) + sw $28,CYGARC_JMP_BUF_R28*mips_regsize(a0) # gp, optimize out? + sw $23,CYGARC_JMP_BUF_R23*mips_regsize(a0) + sw $22,CYGARC_JMP_BUF_R22*mips_regsize(a0) + sw $21,CYGARC_JMP_BUF_R21*mips_regsize(a0) + sw $20,CYGARC_JMP_BUF_R20*mips_regsize(a0) + sw $19,CYGARC_JMP_BUF_R19*mips_regsize(a0) + sw $18,CYGARC_JMP_BUF_R18*mips_regsize(a0) + sw $17,CYGARC_JMP_BUF_R17*mips_regsize(a0) + sw $16,CYGARC_JMP_BUF_R16*mips_regsize(a0) + sw sp,CYGARC_JMP_BUF_SP*mips_regsize(a0) # $29 li v0,0 jr ra nop # delay slot @@ -220,18 +240,18 @@ hal_setjmp: .globl hal_longjmp .ent hal_longjmp hal_longjmp: - lw $31,CYGARC_JMP_BUF_R31*4(a0) # ra (link) - lw $30,CYGARC_JMP_BUF_R30*4(a0) - lw $28,CYGARC_JMP_BUF_R28*4(a0) # gp, optimize out? - lw $23,CYGARC_JMP_BUF_R23*4(a0) - lw $22,CYGARC_JMP_BUF_R22*4(a0) - lw $21,CYGARC_JMP_BUF_R21*4(a0) - lw $20,CYGARC_JMP_BUF_R20*4(a0) - lw $19,CYGARC_JMP_BUF_R19*4(a0) - lw $18,CYGARC_JMP_BUF_R18*4(a0) - lw $17,CYGARC_JMP_BUF_R17*4(a0) - lw $16,CYGARC_JMP_BUF_R16*4(a0) - lw sp,CYGARC_JMP_BUF_SP*4(a0) # $29 + lw $31,CYGARC_JMP_BUF_R31*mips_regsize(a0) # ra (link) + lw $30,CYGARC_JMP_BUF_R30*mips_regsize(a0) + lw $28,CYGARC_JMP_BUF_R28*mips_regsize(a0) # gp, optimize out? + lw $23,CYGARC_JMP_BUF_R23*mips_regsize(a0) + lw $22,CYGARC_JMP_BUF_R22*mips_regsize(a0) + lw $21,CYGARC_JMP_BUF_R21*mips_regsize(a0) + lw $20,CYGARC_JMP_BUF_R20*mips_regsize(a0) + lw $19,CYGARC_JMP_BUF_R19*mips_regsize(a0) + lw $18,CYGARC_JMP_BUF_R18*mips_regsize(a0) + lw $17,CYGARC_JMP_BUF_R17*mips_regsize(a0) + lw $16,CYGARC_JMP_BUF_R16*mips_regsize(a0) + lw sp,CYGARC_JMP_BUF_SP*mips_regsize(a0) # $29 move v0,a1 jr ra nop # delay slot
--- a/packages/hal/mips/arch/current/src/hal_misc.c +++ b/packages/hal/mips/arch/current/src/hal_misc.c @@ -135,11 +135,14 @@ cyg_bool cyg_hal_stop_constructors; typedef void (*pfunc) (void); extern pfunc __CTOR_LIST__[]; -extern void patch_dbg_syscalls(void * vector); void cyg_hal_invoke_constructors(void) { +#if 0 + +#else + pfunc p; #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG @@ -165,67 +168,10 @@ cyg_hal_invoke_constructors(void) p (); } #endif -} // cyg_hal_invoke_constructors() -void -cyg_hal_enable_caches(void) -{ -#ifdef CYG_HAL_MIPS_TX3904 - - // On the real hardware we also enable the cache. - // doing this here is a temporary measure until we - // have a proper platform specific place to do it. +#endif -#if !defined(CYGHWR_HAL_TX39_JMR3904_ENABLE_TOE) - - HAL_ICACHE_INVALIDATE_ALL(); - HAL_ICACHE_ENABLE(); - HAL_DCACHE_INVALIDATE_ALL(); - HAL_DCACHE_ENABLE(); - - HAL_TX39_DEBUG_TOE_DISABLE(); - -#else - - // If TOE is enabled, caches are disabled by default - // until spurious Bus Timeout problem is fixed. - - HAL_ICACHE_INVALIDATE_ALL(); - HAL_ICACHE_DISABLE(); - HAL_DCACHE_INVALIDATE_ALL(); - HAL_DCACHE_DISABLE(); - - HAL_TX39_DEBUG_TOE_ENABLE(); - -#endif - -#endif -} // cyg_hal_enable_caches() - -void -cyg_hal_debug_init(void) -{ -#ifdef CYGDBG_HAL_MIPS_INSTALL_CTRL_C_ISR -#if defined(CYG_HAL_USE_ROM_MONITOR) && \ - !defined(CYGDBG_INFRA_DIAG_USE_DEVICE) && \ - defined(CYG_HAL_TX39_JMR3904) - - { - static void hal_init_ctrlc_intr(void); - hal_init_ctrlc_intr(); - } - -#endif -#endif // CYGDBG_HAL_MIPS_INSTALL_CTRL_C_ISR - -#if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ - defined(CYG_HAL_USE_ROM_MONITOR) && \ - defined(CYG_HAL_USE_ROM_MONITOR_CYGMON) - { - patch_dbg_syscalls( (void *)(&hal_vsr_table[0]) ); - } -#endif -} // cyg_hal_debug_init() +} // cyg_hal_invoke_constructors() /*------------------------------------------------------------------------*/ /* Determine the index of the ls bit of the supplied mask. */ @@ -276,6 +222,8 @@ cyg_uint32 hal_msbit_index(cyg_uint32 ma /*------------------------------------------------------------------------*/ /* Idle thread action */ +#include <cyg/infra/diag.h> + void hal_idle_thread_action( cyg_uint32 count ) { #if 0 //def CYG_HAL_MIPS_SIM @@ -298,9 +246,10 @@ void hal_idle_thread_action( cyg_uint32 #endif #if 0 //def CYG_HAL_MIPS_JMR3904 + if( (count % 100000 ) == 0 ) { // cyg_uint32 tval, isr, imr, ilr; - cyg_uint32 sr, cr; + cyg_uint32 sr = 0, cr = 0, ctr = 0, cpr = 0; // HAL_CLOCK_READ( &tval ); // HAL_READ_UINT32( 0xFFFFC000, isr ); // HAL_READ_UINT32( 0xFFFFC004, imr ); @@ -308,14 +257,85 @@ void hal_idle_thread_action( cyg_uint32 // CYG_TRACE2(1, "Timer value, ISR ",tval, isr); // CYG_TRACE2(1, "IMR ILR0 ", imr, ilr); +// asm volatile ( +// "mfc0 %0,$12;" +// "nop; nop; nop;" +// "mfc0 %1,$13;" +// "nop; nop; nop;" +// "mfc0 %2,$9;" +// "nop; nop; nop;" +// "mfc0 %3,$11;" +// "nop; nop; nop;" +// : "=r"(sr), "=r"(cr), "=r"(ctr), "=r"(cpr) +// ); + + +// diag_printf("Status %08x ", sr ); +// diag_printf("Cause %08x ", cr ); +// diag_printf("Counter %08x ", ctr ); +// diag_printf("Compare %08x\n", cpr); + +#if 0 asm volatile ( "mfc0 %0,$12;" - "mfc0 %1,$13;" - : "=r"(sr), "=r"(cr) + "nop; nop; nop;" + : "=r"(sr) + ); + diag_write_string("Status "); diag_write_hex( sr ); + + asm volatile ( + "mfc0 %0,$13;" + "nop; nop; nop;" + : "=r"(cr) + ); + diag_write_string(" Cause "); diag_write_hex( cr ); + + asm volatile ( + "mfc0 %0,$9;" + "nop; nop; nop;" + : "=r"(ctr) + ); + diag_write_string(" Counter "); diag_write_hex( ctr ); + + asm volatile ( + "mfc0 %0,$11;" + "nop; nop; nop;" + : "=r"(cpr) + ); + diag_write_string(" Compare "); diag_write_hex( cpr ); + diag_write_string( "\n" ); + +#endif +#if 1 + asm volatile ( + "mfc0 %0,$12;" + "nop; nop; nop;" + : "=r"(sr) ); - CYG_TRACE2(1, "Status Cause ", sr, cr); + asm volatile ( + "mfc0 %0,$13;" + "nop; nop; nop;" + : "=r"(cr) + ); + + CYG_INSTRUMENT_USER( 1, sr, cr ); + asm volatile ( + "mfc0 %0,$9;" + "nop; nop; nop;" + : "=r"(ctr) + ); + + asm volatile ( + "mfc0 %0,$11;" + "nop; nop; nop;" + : "=r"(cpr) + ); + + CYG_INSTRUMENT_USER( 2, ctr, cpr ); +#endif + // if( count == 4 ) // { // HAL_ENABLE_INTERRUPTS(); @@ -328,123 +348,4 @@ void hal_idle_thread_action( cyg_uint32 } /*------------------------------------------------------------------------*/ -/* Functions to support the detection and execution of a user provoked */ -/* program break. These are usually called from interrupt routines. */ - -cyg_bool cyg_hal_is_break(char *buf, int size) -{ - while( size ) - if( buf[--size] == 0x03 ) return true; - - return false; -} - -void cyg_hal_user_break( CYG_ADDRWORD *regs ) -{ -#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) - - // Ctrl-C: breakpoint. - extern void breakpoint(void); - breakpoint(); - -#elif defined(CYG_HAL_USE_ROM_MONITOR) && defined(CYG_HAL_USE_ROM_MONITOR_GDB_STUBS) - - // Ctrl-C: breakpoint. - typedef void bpt_fn(void); - bpt_fn *bfn = ((bpt_fn **)0x80000100)[61]; - bfn(); - -#elif defined(CYG_HAL_USE_ROM_MONITOR) && defined(CYG_HAL_USE_ROM_MONITOR_CYGMON) - - // Ctrl-C: breakpoint. - typedef void install_bpt_fn(void *epc); - HAL_SavedRegisters *sreg = (HAL_SavedRegisters *)regs; - install_bpt_fn *ibp = (install_bpt_fn *)hal_vsr_table[35]; - if( ibp != NULL ) ibp((void *)sreg->pc); - -#endif - -} - -/*------------------------------------------------------------------------*/ -/* This code installs an interrupt handler to capture Ctrl-C. */ -/* It's here for lack of anywhere more suitable to put it. */ - -#ifdef CYGDBG_HAL_MIPS_INSTALL_CTRL_C_ISR -#if defined(CYG_HAL_USE_ROM_MONITOR) && \ - !defined(CYGDBG_INFRA_DIAG_USE_DEVICE) && \ - defined(CYG_HAL_TX39_JMR3904) - -#define DIAG_BASE 0xfffff300 -#define DIAG_SLCR (DIAG_BASE+0x00) -#define DIAG_SLSR (DIAG_BASE+0x04) -#define DIAG_SLDICR (DIAG_BASE+0x08) -#define DIAG_SLDISR (DIAG_BASE+0x0C) -#define DIAG_SFCR (DIAG_BASE+0x10) -#define DIAG_SBRG (DIAG_BASE+0x14) -#define DIAG_TFIFO (DIAG_BASE+0x20) -#define DIAG_RFIFO (DIAG_BASE+0x30) - -#define BRG_T0 0x0000 -#define BRG_T2 0x0100 -#define BRG_T4 0x0200 -#define BRG_T5 0x0300 - -typedef cyg_uint32 (*original_isr_ptr_t)(CYG_ADDRWORD vector, CYG_ADDRWORD data); -static original_isr_ptr_t original_isr_ptr; -static CYG_ADDRWORD original_data, original_object; - -static cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data, CYG_ADDRWORD* regs) -{ - char c; - CYG_WORD16 disr; - - HAL_READ_UINT16( DIAG_SLDISR , disr ); - - if( disr & 0x0001 ) - { - - disr = disr & ~0x0001; - - HAL_READ_UINT8( DIAG_RFIFO, c ); - - HAL_WRITE_UINT16( DIAG_SLDISR , disr ); - - if( cyg_hal_is_break( &c , 1 ) ) - cyg_hal_user_break( regs ); - return 0; - } - /* else */ - return (*original_isr_ptr)(vector, data); -} - - -static void hal_init_ctrlc_intr(void) -{ - CYG_WORD16 dicr; - - cyg_uint32 index; - HAL_TRANSLATE_VECTOR(CYGNUM_HAL_INTERRUPT_SIO_0, index); - - original_data = hal_interrupt_data[index]; - original_object = hal_interrupt_objects[index]; - original_isr_ptr = (original_isr_ptr_t) hal_interrupt_handlers[index]; - - hal_interrupt_handlers[index] = - (CYG_ADDRESS)hal_default_isr; - - HAL_INTERRUPT_ATTACH( CYGNUM_HAL_INTERRUPT_SIO_0, hal_ctrlc_isr, original_data, - original_object ); - - HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_SIO_0 ); - - HAL_READ_UINT16( DIAG_SLDICR , dicr ); - dicr = 0x0001; - HAL_WRITE_UINT16( DIAG_SLDICR , dicr ); -} - -#endif -#endif // CYGDBG_HAL_MIPS_INSTALL_CTRL_C_ISR - -/*------------------------------------------------------------------------*/ /* End of hal_misc.c */
deleted file mode 100644 --- a/packages/hal/mips/arch/current/src/tx39.ld +++ /dev/null @@ -1,161 +0,0 @@ -//=========================================================================== -// -// MLT linker script for TX39 -// adapted from packages\hal\mips\jmr3904\v1_1\src\jmr3904.ld -// -//=========================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Cygnus eCos Public License -// Version 1.0 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://sourceware.cygnus.com/ecos -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Cygnus Operating System, released -// September 30, 1998. -// -// The Initial Developer of the Original Code is Cygnus. Portions created -// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//=========================================================================== - -#include <pkgconf/system.h> - -STARTUP(vectors.o) -ENTRY(reset_vector) -#ifdef EXTRAS -INPUT(extras.o) -#endif -GROUP(libtarget.a libgcc.a) - -#define ALIGN_LMA 8 -#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1)) -#define LMA_EQ_VMA -#define FORCE_OUTPUT . = . - -#define SECTIONS_BEGIN - -#if defined(CYG_HAL_STARTUP_RAM) - -/* this version for RAM startup */ -#define SECTION_rom_vectors(_region_, _vma_, _lma_) \ - .rom_vectors _vma_ : _lma_ \ - { KEEP (*(.utlb_vector)) \ - . = ALIGN(0x80); KEEP(*(.other_vector)) \ - /* debug and reset vector not used in RAM version */ \ - KEEP(*(.debug_vector)) \ - KEEP (*(.reset_vector)) } \ - > _region_ - -#elif defined(CYG_HAL_STARTUP_ROM) - -/* this version for ROM startup */ -#define SECTION_rom_vectors(_region_, _vma_, _lma_) \ - .rom_vectors _vma_ : _lma_ \ - { KEEP (*(.reset_vector)) \ - . = ALIGN(0x100); KEEP (*(.utlb_vector)) \ - . = ALIGN(0x80); KEEP(*(.other_vector)) \ - . = ALIGN(0x100); KEEP(*(.debug_vector)) } \ - > _region_ - -#endif /* ROM startup version of ROM vectors */ - -#define SECTION_text(_region_, _vma_, _lma_) \ - .text _vma_ : _lma_ \ - { _stext = ABSOLUTE(.); \ - *(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) } \ - > _region_ \ - _etext = .; PROVIDE (etext = .); - -#define SECTION_fini(_region_, _vma_, _lma_) \ - .fini _vma_ : _lma_ \ - { FORCE_OUTPUT; *(.fini) } \ - > _region_ - -#define SECTION_rodata(_region_, _vma_, _lma_) \ - .rodata _vma_ : _lma_ \ - { FORCE_OUTPUT; *(.rodata*) } \ - > _region_ - -#define SECTION_vsr_table(_region_, _vma_, _lma_) \ - .vsr_table _vma_ : _lma_ \ - { FORCE_OUTPUT; *(.vsr_table) } \ - > _region_ - -#define SECTION_rodata1(_region_, _vma_, _lma_) \ - .rodata1 _vma_ : _lma_ \ - { FORCE_OUTPUT; *(.rodata1) } \ - > _region_ - -#define SECTION_fixup(_region_, _vma_, _lma_) \ - .fixup _vma_ : _lma_ \ - { FORCE_OUTPUT; *(.fixup) } \ - > _region_ - -#define SECTION_rel__dyn(_region_, _vma_, _lma_) \ - .rel.dyn _vma_ : _lma_ \ - { FORCE_OUTPUT; *(.rel.dyn) } \ - > _region_ - -#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \ - .gcc_except_table _vma_ : _lma_ \ - { FORCE_OUTPUT; *(.gcc_except_table) } \ - > _region_ - -#define SECTION_data(_region_, _vma_, _lma_) \ - .data _vma_ : _lma_ \ - { __ram_data_start = ABSOLUTE (.); \ - *(.data*) *(.data1) \ - _GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \ - _GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \ - . = ALIGN (8); \ - SORT (CONSTRUCTORS) *(.ctors*) *(.dtors*) \ - . = ALIGN (8); \ - __DEVTAB__ = ABSOLUTE (.); KEEP (*(SORT (.devtab*))) __DEVTAB_END__ = ABSOLUTE (.); \ - . = ALIGN (8); \ - _GOT_START = ABSOLUTE (.); _gp = ABSOLUTE (.); __global = _gp; _GLOBAL_OFFSET_TABLE_ = ABSOLUTE (.); _SDA_BASE_ = ABSOLUTE (.); \ - *(.got.plt) *(.got) _GOT_END_ = ABSOLUTE (.); \ - *(.dynamic) *(.sdata*) *(.sbss*) *(.eh_frame) } \ - > _region_ \ - __rom_data_start = LOADADDR (.data); \ - __ram_data_end = .; PROVIDE (__ram_data_end = .); _edata = .; PROVIDE (edata = .); - -#define SECTION_bss(_region_, _vma_, _lma_) \ - .bss _vma_ : _lma_ \ - { __bss_start = ABSOLUTE (.); \ - *(.scommon) *(.dynbss) *(.bss) *(COMMON) \ - __bss_end = ABSOLUTE (.); } \ - > _region_ - -#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); \ - .debug 0 : { *(.debug) } \ - .line 0 : { *(.line) } \ - .debug_srcinfo 0 : { *(.debug_srcinfo) } \ - .debug_sfnames 0 : { *(.debug_sfnames) } \ - .debug_aranges 0 : { *(.debug_aranges) } \ - .debug_pubnames 0 : { *(.debug_pubnames) } \ - .debug_info 0 : { *(.debug_info) } \ - .debug_abbrev 0 : { *(.debug_abbrev) } \ - .debug_line 0 : { *(.debug_line) } \ - .debug_frame 0 : { *(.debug_frame) } \ - .debug_str 0 : { *(.debug_str) } \ - .debug_loc 0 : { *(.debug_loc) } \ - .debug_macinfo 0 : { *(.debug_macinfo) } \ - .debug_weaknames 0 : { *(.debug_weaknames) } \ - .debug_funcnames 0 : { *(.debug_funcnames) } \ - .debug_typenames 0 : { *(.debug_typenames) } \ - .debug_varnames 0 : { *(.debug_varnames) } - -#include CYGHWR_MEMORY_LAYOUT_LDI - -#ifndef CYGPKG_HAL_TX39_SIM -hal_vsr_table = 0x80000100; -#endif
--- a/packages/hal/mips/arch/current/src/vectors.S +++ b/packages/hal/mips/arch/current/src/vectors.S @@ -42,8 +42,6 @@ ## ##============================================================================= -# .file "vectors.S" - #include <pkgconf/system.h> #include <pkgconf/hal.h> @@ -51,47 +49,9 @@ # include <pkgconf/kernel.h> #endif -#include <cyg/hal/mips.inc> - - .extern cyg_instrument - -##----------------------------------------------------------------------------- - -#define MAX_SAVE_REG 31 +#include <cyg/hal/arch.inc> -#if defined(CYG_HAL_STARTUP_RAM) -# if defined(CYG_HAL_MIPS_SIM) || !defined(CYG_HAL_USE_ROM_MONITOR) -# define INITIAL_SR 0x1000ff00 /* CP0 usable, Ints enabled */ -//#define INITIAL_SR 0x10000000 /* CP0 usable, Ints disabled */ -# else -# define INITIAL_SR 0x1040ff00 /* as above + ROM vectors used */ -# endif -#elif defined(CYG_HAL_STARTUP_ROM) -# define INITIAL_SR 0x1040ff00 /* as above + ROM vectors used */ -#endif - -## ROM timing characteristics dependent on the clock speed. - -#if (CYGHWR_HAL_MIPS_CPU_FREQ == 50) -#define ROM_CCR0_INIT 0x00000420 -#define DRAM_DREFC_INIT 0x00000180 -#elif (CYGHWR_HAL_MIPS_CPU_FREQ == 66) -#define ROM_CCR0_INIT 0x00000520 -#define DRAM_DREFC_INIT 0x00000200 -#else -#error Unsupported clock frequency -#endif - -## DRAM configuration dependent on the DRAM device used. - ## for 16MByte (4MBit (x4bit) x 8) 0x08024030 - ## for 4MByte (1MBit (x4bit) x 8) 0x08013020 - ## for 8MByte (1MBit (x4bit) x 8 x 2 banks) 0x08013020 - -#if defined CYGHWR_HAL_TX39_JMR3904_DRAM_CONFIG_INIT -#define DRAM_CONFIG_INIT CYGHWR_HAL_TX39_JMR3904_DRAM_CONFIG_INIT -#else -#define DRAM_CONFIG_INIT 0x08024030 -#endif + .extern cyg_instrument ##----------------------------------------------------------------------------- ## Hardware supplied vectors @@ -103,30 +63,29 @@ # Reset vector at 0xBFC00000 - .globl reset_vector -reset_vector: +FUNC_START(reset_vector) la v0,_start # jump to start jr v0 nop # (delay slot) - +FUNC_END(reset_vector) + .section ".debug_vector","ax" # Debug vector at 0xBFC00200 - .globl debug_vector -debug_vector: +FUNC_START(debug_vector) la k0,32 la k1,hal_vsr_table # Get VSR table lw k1,32*4(k1) # load debug vector jr k1 # go there nop # (delay slot) +FUNC_END(debug_vector) .section ".other_vector","ax" # Common vector at 0x80000080 or 0xBFC00180 - .globl other_vector -other_vector: +FUNC_START(other_vector) mfc0 k0,cause # K0 = exception cause nop andi k0,k0,0x7F # isolate exception code @@ -135,119 +94,36 @@ other_vector: lw k1,0(k1) # k1 = pointer to VSR jr k1 # go there nop # (delay slot) - +FUNC_END(other_vector) + .section ".utlb_vector","ax" - .globl utlb_vector -utlb_vector: +FUNC_START(utlb_vector) la k0,33 la k1,hal_vsr_table # Get VSR table lw k1,33*4(k1) # load utlb vector jr k1 # go there nop # (delay slot) +FUNC_END(utlb_vector) - ##----------------------------------------------------------------------------- ## Startup code .text - .globl _start - .ent _start -_start: - # init CPU registers - mtc0 zero,cause # zero cause reg - la v0,INITIAL_SR - mtc0 v0,sr - mfc0 v0,config - nop - .set at - and v0,v0,0xffffffcf -# la v0,0 - .set noat - mtc0 v0,config +FUNC_START(_start) - # Initialize hardware -#ifdef CYG_HAL_MIPS_JMR3904 - - # These mappings need to be set up before we - # can use the stack and make calls to other - # functions - - # If we have been started from Cygmon, it should have - # already done a lot of this, but it should do no harm - # to reinitialize the following registers. - - # SCS0,1 base addr of ISA & PCI - la a0,0xffffe010 - la a1,0x20201410 - sw a1,0(a0) - - la a0,0xffffe014 - la a1,0xfffffcfc - sw a1,0(a0) - - # ROM configuration - .set at - la a0,0xffff9000 - lw a1,0(a0) - and a1,a1,0xffff0004 # keep hardware defaults - or a1,ROM_CCR0_INIT # install our values - sw a1,0(a0) - .set noat - - # SRAM config - la a0,0xffff9100 - la a1,0x00000000 - sw a1,0(a0) - - # ISA bus setup - la a0,0xb2100000 - la a1,4 - sb a1,0(a0) - - # Clear IMR (to cope with JMON) - la a0,0xffffc004 - la a1,0x00000000 - sw a1,0(a0) - -#if defined(CYG_HAL_STARTUP_ROM) - - # Only do this in ROM configurations. - - # DRAM Configuration - la a0, 0xffff8000 - la a1, DRAM_CONFIG_INIT - sw a1, 0(a0) - - # DBMR0 - la a0, 0xffff8004 - la a1, 0x00000000 - sw a1, 0(a0) - - # DWR0 - la a0, 0xffff8008 - la a1, 0x00000000 - sw a1, 0(a0) - - # DREFC - Depends on clock requency - la a0, 0xffff8800 - la a1, DRAM_DREFC_INIT - sw a1, 0(a0) - -#endif - - # Set up PIO0 for output - la a0,0xfffff500 - la a1,0xff - sb a1,0(a0) - la a1,0 - sb a1,4(a0) - -#endif - + hal_cpu_init + hal_mmu_init + hal_fpu_init + hal_memc_init + hal_intc_init + hal_cache_init + hal_diag_init + hal_timer_init + # Load Global Pointer register. la gp,_gp @@ -255,71 +131,15 @@ utlb_vector: la a0,__interrupt_stack move sp,a0 -#if defined(CYG_HAL_STARTUP_ROM) || \ - (defined(CYG_HAL_STARTUP_RAM) && !defined(CYG_HAL_USE_ROM_MONITOR)) - - # If we are starting up from ROM, or we are starting in - # RAM and NOT using a ROM monitor, initialize the VSR table. - - la a0,__default_interrupt_vsr - la a1,__default_exception_vsr - la a3,hal_vsr_table - sw a0,0(a3) - sw a1,1*4(a3) - sw a1,2*4(a3) - sw a1,3*4(a3) - sw a1,4*4(a3) - sw a1,5*4(a3) - sw a1,6*4(a3) - sw a1,7*4(a3) - sw a1,8*4(a3) - sw a1,9*4(a3) - sw a1,10*4(a3) - sw a1,11*4(a3) - sw a1,12*4(a3) - sw a1,13*4(a3) - sw a1,14*4(a3) - sw a1,15*4(a3) - - sw a1,32*4(a3) - sw a1,33*4(a3) - -#ifdef CYG_HAL_ROM_MONITOR - - # Install vectors to debug read and write functions - - .extern hal_diag_write_char - .extern hal_diag_read_char - .extern breakpoint - - la a0,hal_diag_write_char - sw a0,63*4(a3) - la a1,hal_diag_read_char - sw a1,62*4(a3) - la a0,breakpoint - sw a0,61*4(a3) - -#endif + hal_mon_init -#endif -#if defined(CYG_HAL_STARTUP_RAM) && defined(CYG_HAL_USE_ROM_MONITOR) - - # initialize the VSR table - # We only take control of the interrupt vector, - # the rest are left to the ROM for now... - - la a0,__default_interrupt_vsr - la a3,hal_vsr_table - sw a0,0(a3) - -#endif - #ifdef CYG_HAL_STARTUP_ROM # Copy data from ROM to RAM .extern hal_copy_data jal hal_copy_data nop + #endif # Zero BSS @@ -328,18 +148,20 @@ utlb_vector: jal hal_zero_bss nop - # Call constructors + # Cal variant and platform HAL + # initialization routines. - .extern cyg_hal_invoke_constructors - jal cyg_hal_invoke_constructors + .extern hal_variant_init + jal hal_variant_init nop - .extern cyg_hal_enable_caches - jal cyg_hal_enable_caches + .extern hal_platform_init + jal hal_platform_init nop - - .extern cyg_hal_debug_init - jal cyg_hal_debug_init + + # Call constructors + .extern cyg_hal_invoke_constructors + jal cyg_hal_invoke_constructors nop #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS @@ -354,34 +176,35 @@ utlb_vector: jal cyg_start nop -9: - j 9b # Loop if we return +9: j 9b # Loop if we return nop # (delay slot) - .end _start +FUNC_END(_start ) ##----------------------------------------------------------------------------- ## Default exception VSR. ## Saves machine state and calls external handling code. - .globl __default_exception_vsr - .ent __default_exception_vsr -__default_exception_vsr: +FUNC_START(__default_exception_vsr) # We enter here with all of the CPU state still # in its registers except: # K0 = vector index # K1 = address of this function + + move k1,sp # K1 = original SP + #ifdef CYG_HAL_ROM_MONITOR # Switch to interrupt stack to handle exception - move k1,sp la sp,__interrupt_stack #endif addi sp,sp,-mips_exception_decrement # space for registers + safety margin + mfc0 k0,cause + andi k0,k0,0x7F # isolate exception code sw k0,mipsreg_vector(sp) # store vector .set noat @@ -424,28 +247,17 @@ 9: sw a0,mipsreg_hi(sp) sw a1,mipsreg_lo(sp) -#ifdef CYG_HAL_ROM_MONITOR # K1 contains original SP sw k1,(mipsreg_regs+29*4)(sp) # store in reg dump -#else - # synthesize original SP value - move a2,sp # a2 = sp - addi a2,a2,mips_exception_decrement # a2 = original sp - sw a2,(mipsreg_regs+29*4)(sp) # store in reg dump -#endif # save remaining machine state registers mfc0 t0,cause - mfc0 t1,sr -# mfc0 t2,cache + mfc0 t1,status + mfc0 t2,cache mfc0 t3,badvr mfc0 t4,config mfc0 t5,prid mfc0 t6,epc - -#ifndef CYG_HAL_MIPS_SIM - mfc0 t2,cache -#endif sw t0,mipsreg_cause(sp) sw t1,mipsreg_sr(sp) @@ -455,9 +267,12 @@ 9: sw t5,mipsreg_prid(sp) sw t6,mipsreg_pc(sp) + hal_fpu_save sp # The machine state is now all saved on the stack. + hal_diag_excpt_start + # Load Global Pointer register. la gp,_gp @@ -468,7 +283,9 @@ 9: # Need to set up back pointers etc. ??? la ra,restore_state # load return address - + + hal_cpu_except_enable # reenable exceptions + .extern exception_handler j exception_handler # call C code move a0,s0 # arg0 = register dump (delay slot) @@ -476,16 +293,14 @@ 9: # When the exception handler returns, it will # go back to restore_state, below. - .end __default_exception_vsr +FUNC_END(__default_exception_vsr) ##------------------------------------------------------------------------------ ## Default interrupt VSR. ## Saves machine state and calls appropriate ISR. When done, calls ## interrupt_end() to finish up and possibly reschedule. - .globl __default_interrupt_vsr - .ent __default_interrupt_vsr -__default_interrupt_vsr: +FUNC_START(__default_interrupt_vsr) # We enter here with all of the CPU state still @@ -493,6 +308,8 @@ 9: # K0 = vector index # K1 = address of this function + move k1,sp # K1 = original SP + addi sp,sp,-mips_exception_decrement # space for registers + safety margin @@ -537,23 +354,23 @@ 9: sw a0,mipsreg_hi(sp) sw a1,mipsreg_lo(sp) - # synthesize original SP value - move a2,sp # a2 = sp - addi a2,a2,mips_exception_decrement # a2 = original sp - sw a2,(mipsreg_regs+29*4)(sp) # store in reg dump - - mfc0 t1,sr + # K1 contains original SP + sw k1,(mipsreg_regs+29*4)(sp) # store in reg dump + + mfc0 t1,status + mfc0 t2,cache mfc0 t3,epc -#ifndef CYG_HAL_MIPS_SIM - mfc0 t2,cache -#endif sw t1,mipsreg_sr(sp) sw t2,mipsreg_cache(sp) sw t3,mipsreg_pc(sp) + hal_fpu_save sp + # The machine state is now all saved on the stack. + hal_diag_intr_start + # Load Global Pointer register. la gp,_gp @@ -591,14 +408,8 @@ 8: # Decode external interrupt via interrupt controller - mfc0 a1,cause # get cause register - nop - srl a1,a1,10 # shift IP bits to ls bits - andi a1,a1,0x7F # isolate IP bits - la t0,interrupt_translation_table # address of translation table - add t0,t0,a1 # offset of index byte - lb s2,0(t0) # load it - + hal_intc_decode s2 + #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN move s1,zero # Just vector zero is supported #else @@ -672,11 +483,6 @@ 8: move a2,s0 # arg3 = saved register dump - # interrupt_end() must be called with interrupts enabled. - - rfe # restore previous status bits - # this may enable interrupts - .extern interrupt_end jal interrupt_end # call into C to finish off nop # (delay slot) @@ -688,25 +494,21 @@ restore_state: # All done, restore CPU state and continue addi sp,sp,mips_stack_frame_size # retrieve CPU state ptr - - # Load status register and cache control register. - # This will put the interrupt, mode and cache control - # bits back to their post-exception values, so we will - # need to do another RFE before we finish. - - lw t1,mipsreg_sr(sp) - lw t2,mipsreg_cache(sp) + + # Disable interrupts again while we restore state. + + hal_diag_restore - mtc0 t1,sr -#ifndef CYG_HAL_MIPS_SIM - mtc0 t2,cache -#endif - - lw a0,mipsreg_hi(sp) - lw a1,mipsreg_lo(sp) - mthi a0 - mtlo a1 + hal_fpu_load sp + lw t0,mipsreg_cache(sp) + lw t1,mipsreg_hi(sp) + lw t2,mipsreg_lo(sp) + + mtc0 t0,cache + mthi t1 + mtlo t2 + # load GPRs # lw $0,(mipsreg_regs+0*4)(sp) lw $1,(mipsreg_regs+1*4)(sp) @@ -742,21 +544,60 @@ restore_state: lw $31,(mipsreg_regs+31*4)(sp) # == RA lw k0,mipsreg_pc(sp) # K0 = return PC + lw k1,mipsreg_sr(sp) # K1 = saved SR lw sp,(mipsreg_regs+29*4)(sp) # load SP - sync - jr k0 # jump back to interrupted code - rfe # restore state (delay slot) + + # Invoke CPU specific mechanism for returning from this + # exception + + hal_cpu_eret k0,k1 - .end __default_interrupt_vsr +FUNC_END(__default_interrupt_vsr) + + hal_intc_decode_data + +##----------------------------------------------------------------------------- +## Execute pending DSRs on the interrupt stack with interrupts enabled. +## Note: this can only be called from code running on a thread stack + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + .extern cyg_interrupt_call_pending_DSRs -# This table translates from the 6 bit value supplied in the IP bits -# of the cause register into a 0..16 offset into the ISR tables. -interrupt_translation_table: - .byte 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - .byte 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - .byte 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 - .byte 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 - +FUNC_START(hal_interrupt_stack_call_pending_DSRs) + mfc0 t0,status # get status register value + la v0,__interrupt_stack # v0 = interrupt stack + move v1,sp # v1 = original stack ptr + move sp,v0 # sp = interrupt stack + addi sp,sp,-32 # make a null frame + sw v1,16(sp) # save old sp + sw ra,20(sp) # save old ra + sw t0,24(sp) # save old sr + + hal_cpu_int_enable + + jal cyg_interrupt_call_pending_DSRs # call back to kernel + nop + + lw a0,24(sp) # get status reg + + hal_cpu_int_merge a0 # merge with current SR + + lw ra,20(sp) # restore ra + lw sp,16(sp) # restore sp + + jr ra # go back + nop # delay slot + +FUNC_END(hal_interrupt_stack_call_pending_DSRs) +#endif + + +// Short circuit in case any code tries to use "__gccmain()" +FUNC_START(__gccmain) + jr ra +FUNC_END(__gccmain) + + ##----------------------------------------------------------------------------- ## Interrupt Stack. ## Used during intialization and for executing ISRs. @@ -780,12 +621,11 @@ interrupt_translation_table: ## This is only used for simulated targets, on real targets a fixed location VSR ## table is now allocated at 0x80000100. -#if defined(CYG_HAL_MIPS_SIM) || \ - ( defined(CYG_HAL_MIPS_TX3904) && \ - defined(CYG_HAL_STARTUP_RAM) && \ - !defined(CYG_HAL_USE_ROM_MONITOR) \ - ) - .section ".vsr_table","a" +#ifndef CYG_HAL_MIPS_VSR_TABLE_DEFINED + +## .section ".vsr_table","a" + + .data .globl hal_vsr_table @@ -803,8 +643,12 @@ hal_vsr_table: # interrupts to user code. # hal_interrupt_level contains the interrupt level set by # HAL_INTERRUPT_CONFIGURE(). +# This is a default set that provide support only for the 6 external +# interrupts in the status/cause registers. Platforms or boards are expected +# to define their own versions of these if they have their own interrupt mappings. + +#ifndef CYG_HAL_MIPS_ISR_TABLES_DEFINED - .extern hal_default_isr .data @@ -817,35 +661,23 @@ hal_interrupt_handlers: .long hal_default_isr .long hal_default_isr .long hal_default_isr - .long hal_default_isr - .long hal_default_isr - .long hal_default_isr - .long hal_default_isr - .long hal_default_isr - .long hal_default_isr - .long hal_default_isr - .long hal_default_isr - .long hal_default_isr - .long hal_default_isr - .long hal_default_isr + .globl hal_interrupt_data hal_interrupt_data: - .rept 17 + .rept 6 .long 0 .endr .globl hal_interrupt_objects hal_interrupt_objects: - .rept 17 + .rept 6 .long 0 .endr - .globl hal_interrupt_level -hal_interrupt_level: - .rept 17 - .byte 7 - .endr - +#endif + ##----------------------------------------------------------------------------- ## end of vectors.S + +
--- a/packages/hal/mips/jmr3904/current/ChangeLog +++ b/packages/hal/mips/jmr3904/current/ChangeLog @@ -1,3 +1,35 @@ +1999-05-14 Nick Garnett <nickg@cygnus.co.uk> + + * src/platform.S: Moved ISR tables out to variant directory. + + * include/platform.inc: Moved definition of + CYG_HAL_MIPS_ISR_TABLES_DEFINED out to variant.inc. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The following changes were made on a branch and merged: + + 1999-05-11 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/hal_tx39_jmr3904.h: + * include/pkgconf/hal_mips_tx39_jmr3904.h: + File hal_tx39_jmr3904.h renamed to match name synthesized by + pkgconf.tcl. + + 1999-04-21 Nick Garnett <nickg@cygnus.co.uk> + + * src/plf_misc.c: Added this file. it contains all of the TX39 + specific code that was in hal_misc.c. + + * src/platform.S: Added this file. It contains platform specific + code and data, specifically the ISR tables. + + * src/PKGconf.mak (COMPILE): Substituted platform.S for jmr3904.S. + Added plf_misc.c. + + * include/platform.inc: Added CYG_HAL_MIPS_ISR_TABLES_DEFINED to + indicate that the tables are defined in platform.S. + 1999-04-30 Hugo Tyson <hmt@cygnus.co.uk> Merge the following changes from the 1.2.1 release branch.
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/jmr3904/current/include/pkgconf/hal_mips_tx39_jmr3904.h @@ -0,0 +1,108 @@ +#ifndef CYGONCE_PKGCONF_HAL_TX39_JMR3904_H +#define CYGONCE_PKGCONF_HAL_TX39_JMR3904_H +// ==================================================================== +// +// pkgconf/hal_tx39_jmr3904.h +// +// HAL configuration file +// +// ==================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Contributors: bartv +// Date: 1998-09-02 +// Purpose: To allow the user to edit HAL configuration options. +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + + +/* --------------------------------------------------------------------- + {{CFG_DATA + + cdl_package CYGPKG_HAL_MIPS_TX39_JMR3904 { + display "JMR3904 evaluation board" + type radio + parent CYGPKG_HAL_MIPS + requires CYGPKG_HAL_MIPS_TX39 + platform jmr3904 + description " + The JMR3904 HAL package should be used when targetting the + actual hardware. The same package can also be used when + running on the full simulator, since this provides an + accurate simulation of the hardware including I/O devices. + To use the simulator in this mode the command + `target sim --board=jmr3904' should be used from inside gdb." + } + + cdl_option CYGHWR_HAL_MIPS_TX39_JMR3904_STARTUP { + display "Startup type" + parent CYGPKG_HAL_MIPS_TX39_JMR3904 + #type count + type enum + legal_values ram rom + startup + description " + When targetting the JMR3904 board it is possible to build + the system for either RAM bootstrap or ROM bootstrap. The + former generally requires that the board is equipped with + ROMs containing the Cygmon ROM monitor or equivalent + software that allows gdb to download the eCos application + on to the board. The latter typically requires that the + eCos application be blown into EPROMs or equivalent + technology." + } + + }}CFG_DATA */ + +#define CYGHWR_HAL_MIPS_TX39_JMR3904_STARTUP ram + +/* -------------------------------------------------------------------*/ +/* Manually edited configuration option, these should only be touched */ +/* by experts who understand the consequences. */ + +/* DRAM Configuration */ +/* for 16MByte (4MBit (x4bit) x 8) 0x08024030 */ +/* for 4MByte (1MBit (x4bit) x 8) 0x08013020 */ +/* for 8MByte (1MBit (x4bit) x 8 x 2 banks) 0x08013020 */ + +#define CYGHWR_HAL_MIPS_TX39_JMR3904_DRAM_CONFIG_INIT 0x08024030 // 16MByte +//#define CYGHWR_HAL_MIPS_TX39_JMR3904_DRAM_CONFIG_INIT 0x08013020 // 4 or 8MByte + +/* Bus Timeout Detection */ + +/* Note: If you enable this option the caches are disabled by default. + * If you enable caches in your code, Spurious Bus Time Outs might + * fire. + */ + +// #define CYGHWR_HAL_MIPS_TX39_JMR3904_ENABLE_TOE + +/* -------------------------------------------------------------------*/ +#endif /* CYGONCE_PKGCONF_HAL_TX39_JMR3904_H */ +/* EOF hal_tx39_jmr3904.h */
deleted file mode 100644 --- a/packages/hal/mips/jmr3904/current/include/pkgconf/hal_tx39_jmr3904.h +++ /dev/null @@ -1,107 +0,0 @@ -#ifndef CYGONCE_PKGCONF_HAL_TX39_JMR3904_H -#define CYGONCE_PKGCONF_HAL_TX39_JMR3904_H -// ==================================================================== -// -// pkgconf/hal_tx39_jmr3904.h -// -// HAL configuration file -// -// ==================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Cygnus eCos Public License -// Version 1.0 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://sourceware.cygnus.com/ecos -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Cygnus Operating System, released -// September 30, 1998. -// -// The Initial Developer of the Original Code is Cygnus. Portions created -// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -// ==================================================================== -//#####DESCRIPTIONBEGIN#### -// -// Author(s): bartv -// Contributors: bartv -// Date: 1998-09-02 -// Purpose: To allow the user to edit HAL configuration options. -// Description: -// -//####DESCRIPTIONEND#### -// -// ==================================================================== - - -/* --------------------------------------------------------------------- - {{CFG_DATA - - cdl_package CYGPKG_HAL_TX39_JMR3904 { - display "JMR3904 evaluation board" - type radio - parent CYGPKG_HAL_TX39 - platform jmr3904 - description " - The JMR3904 HAL package should be used when targetting the - actual hardware. The same package can also be used when - running on the full simulator, since this provides an - accurate simulation of the hardware including I/O devices. - To use the simulator in this mode the command - `target sim --board=jmr3904' should be used from inside gdb." - } - - cdl_option CYGHWR_HAL_TX39_JMR3904_STARTUP { - display "Startup type" - parent CYGPKG_HAL_TX39_JMR3904 - #type count - type enum - legal_values ram rom - startup - description " - When targetting the JMR3904 board it is possible to build - the system for either RAM bootstrap or ROM bootstrap. The - former generally requires that the board is equipped with - ROMs containing the Cygmon ROM monitor or equivalent - software that allows gdb to download the eCos application - on to the board. The latter typically requires that the - eCos application be blown into EPROMs or equivalent - technology." - } - - }}CFG_DATA */ - -#define CYGHWR_HAL_TX39_JMR3904_STARTUP ram - -/* -------------------------------------------------------------------*/ -/* Manually edited configuration option, these should only be touched */ -/* by experts who understand the consequences. */ - -/* DRAM Configuration */ -/* for 16MByte (4MBit (x4bit) x 8) 0x08024030 */ -/* for 4MByte (1MBit (x4bit) x 8) 0x08013020 */ -/* for 8MByte (1MBit (x4bit) x 8 x 2 banks) 0x08013020 */ - -#define CYGHWR_HAL_TX39_JMR3904_DRAM_CONFIG_INIT 0x08024030 // 16MByte -//#define CYGHWR_HAL_TX39_JMR3904_DRAM_CONFIG_INIT 0x08013020 // 4 or 8MByte - -/* Bus Timeout Detection */ - -/* Note: If you enable this option the caches are disabled by default. - * If you enable caches in your code, Spurious Bus Time Outs might - * fire. - */ - -// #define CYGHWR_HAL_TX39_JMR3904_ENABLE_TOE - -/* -------------------------------------------------------------------*/ -#endif /* CYGONCE_PKGCONF_HAL_TX39_JMR3904_H */ -/* EOF hal_tx39_jmr3904.h */
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/jmr3904/current/include/pkgconf/mlt_mips_tx39_jmr3904_ram.ldi @@ -0,0 +1,48 @@ +//=========================================================================== +// +// MLT linker script export - Wed Jan 13 17:05:29 1999 +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +MEMORY +{ + ram : ORIGIN = 0x80008000, LENGTH = 0x78000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0x80008000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rel__dyn (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/jmr3904/current/include/pkgconf/mlt_mips_tx39_jmr3904_ram.mlt @@ -0,0 +1,12 @@ +version 0 +region ram 80008000 78000 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 80008000 80008000 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 1 0 1 0 1 0 1 rodata rodata ! +section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! +section fixup 0 1 0 1 0 1 0 1 rel.dyn rel.dyn ! +section rel.dyn 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 1 0 1 data data ! +section data 0 8 0 1 0 1 0 1 bss bss ! +section bss 0 4 0 1 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/jmr3904/current/include/pkgconf/mlt_mips_tx39_jmr3904_rom.ldi @@ -0,0 +1,49 @@ +//=========================================================================== +// +// MLT linker script export - Wed Jan 13 10:44:34 1999 +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +MEMORY +{ + ram : ORIGIN = 0x80000200, LENGTH = 0x7fe00 + rom : ORIGIN = 0xbfc00000, LENGTH = 0x80000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0xbfc00000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rel__dyn (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, 0x80000200, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/jmr3904/current/include/pkgconf/mlt_mips_tx39_jmr3904_rom.mlt @@ -0,0 +1,13 @@ +version 0 +region ram 80000200 7fe00 0 ! +region rom bfc00000 80000 1 ! +section data 0 1 1 1 1 1 0 0 80000200 bss ! +section bss 0 4 0 1 0 0 0 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 bfc00000 bfc00000 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 1 0 1 0 1 0 1 rodata rodata ! +section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! +section fixup 0 1 0 1 0 1 0 1 rel.dyn rel.dyn ! +section rel.dyn 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 0 0 1 data !
deleted file mode 100644 --- a/packages/hal/mips/jmr3904/current/include/pkgconf/mlt_tx39_jmr3904_ram.ldi +++ /dev/null @@ -1,48 +0,0 @@ -//=========================================================================== -// -// MLT linker script export - Wed Jan 13 17:05:29 1999 -// -//=========================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Cygnus eCos Public License -// Version 1.0 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://sourceware.cygnus.com/ecos -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Cygnus Operating System, released -// September 30, 1998. -// -// The Initial Developer of the Original Code is Cygnus. Portions created -// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//=========================================================================== - -MEMORY -{ - ram : ORIGIN = 0x80008000, LENGTH = 0x78000 -} - -SECTIONS -{ - SECTIONS_BEGIN - SECTION_rom_vectors (ram, 0x80008000, LMA_EQ_VMA) - SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_rel__dyn (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) - SECTIONS_END -}
deleted file mode 100644 --- a/packages/hal/mips/jmr3904/current/include/pkgconf/mlt_tx39_jmr3904_ram.mlt +++ /dev/null @@ -1,12 +0,0 @@ -version 0 -region ram 80008000 78000 0 ! -section rom_vectors 0 1 0 1 1 1 1 1 80008000 80008000 text text ! -section text 0 1 0 1 0 1 0 1 fini fini ! -section fini 0 1 0 1 0 1 0 1 rodata rodata ! -section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! -section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! -section fixup 0 1 0 1 0 1 0 1 rel.dyn rel.dyn ! -section rel.dyn 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! -section gcc_except_table 0 1 0 1 0 1 0 1 data data ! -section data 0 8 0 1 0 1 0 1 bss bss ! -section bss 0 4 0 1 0 0 0 0 !
deleted file mode 100644 --- a/packages/hal/mips/jmr3904/current/include/pkgconf/mlt_tx39_jmr3904_rom.ldi +++ /dev/null @@ -1,49 +0,0 @@ -//=========================================================================== -// -// MLT linker script export - Wed Jan 13 10:44:34 1999 -// -//=========================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Cygnus eCos Public License -// Version 1.0 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://sourceware.cygnus.com/ecos -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Cygnus Operating System, released -// September 30, 1998. -// -// The Initial Developer of the Original Code is Cygnus. Portions created -// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//=========================================================================== - -MEMORY -{ - ram : ORIGIN = 0x80000200, LENGTH = 0x7fe00 - rom : ORIGIN = 0xbfc00000, LENGTH = 0x80000 -} - -SECTIONS -{ - SECTIONS_BEGIN - SECTION_rom_vectors (rom, 0xbfc00000, LMA_EQ_VMA) - SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_fini (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_rodata (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_rodata1 (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_fixup (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_rel__dyn (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_data (ram, 0x80000200, FOLLOWING (.gcc_except_table)) - SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) - SECTIONS_END -}
deleted file mode 100644 --- a/packages/hal/mips/jmr3904/current/include/pkgconf/mlt_tx39_jmr3904_rom.mlt +++ /dev/null @@ -1,13 +0,0 @@ -version 0 -region ram 80000200 7fe00 0 ! -region rom bfc00000 80000 1 ! -section data 0 1 1 1 1 1 0 0 80000200 bss ! -section bss 0 4 0 1 0 0 0 0 ! -section rom_vectors 0 1 0 1 1 1 1 1 bfc00000 bfc00000 text text ! -section text 0 1 0 1 0 1 0 1 fini fini ! -section fini 0 1 0 1 0 1 0 1 rodata rodata ! -section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! -section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! -section fixup 0 1 0 1 0 1 0 1 rel.dyn rel.dyn ! -section rel.dyn 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! -section gcc_except_table 0 1 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/jmr3904/current/include/platform.inc @@ -0,0 +1,127 @@ +#ifndef CYGONCE_HAL_PLATFORM_INC +#define CYGONCE_HAL_PLATFORM_INC +##============================================================================= +## +## platform.inc +## +## JMR-TX3904 board assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors: nickg +## Date: 1999-04-06 +## Purpose: JMR-TX3904 board definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the JMR-TX3904 board. +## Usage: +## #include <cyg/hal/platform.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <cyg/hal/mips.inc> + +#------------------------------------------------------------------------------ +# Monitor initialization. + +#ifndef CYGPKG_HAL_MIPS_MON_DEFINED + + .macro hal_mon_init +#if defined(CYG_HAL_STARTUP_ROM) || \ + ( defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYG_HAL_USE_ROM_MONITOR)) + + # If we are starting up from ROM, or we are starting in + # RAM and NOT using a ROM monitor, initialize the VSR table. + + la a0,__default_interrupt_vsr + la a1,__default_exception_vsr + la a3,hal_vsr_table + sw a0,0(a3) + sw a1,1*4(a3) + sw a1,2*4(a3) + sw a1,3*4(a3) + sw a1,4*4(a3) + sw a1,5*4(a3) + sw a1,6*4(a3) + sw a1,7*4(a3) + sw a1,8*4(a3) + sw a1,9*4(a3) + sw a1,10*4(a3) + sw a1,11*4(a3) + sw a1,12*4(a3) + sw a1,13*4(a3) + sw a1,14*4(a3) + sw a1,15*4(a3) + + sw a1,32*4(a3) + sw a1,33*4(a3) + +#endif + +#if defined(CYG_HAL_STARTUP_RAM) && defined(CYG_HAL_USE_ROM_MONITOR) + + # Initialize the VSR table entries + # We only take control of the interrupt vector, + # the rest are left to the ROM for now... + + la a0,__default_interrupt_vsr + la a3,hal_vsr_table + sw a0,0(a3) + +#endif + + .endm + +#define CYGPKG_HAL_MIPS_MON_DEFINED + +#endif + +#------------------------------------------------------------------------------ +# Decide whether the VSR table is defined externally, or is to be defined +# here. + +#if defined(CYG_HAL_MIPS_SIM) || \ + ( defined(CYG_HAL_MIPS_TX3904) && \ + defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYG_HAL_USE_ROM_MONITOR) \ + ) + +## VSR table defined in linker script + +#else + +#define CYG_HAL_MIPS_VSR_TABLE_DEFINED + +#endif + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_PLATFORM_INC +# end of platform.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/jmr3904/current/include/plf_cache.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_PLF_CACHE_H +#define CYGONCE_PLF_CACHE_H + +//============================================================================= +// +// plf_cache.h +// +// HAL cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1998-02-17 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/plf_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/plf_cache.h> + +//============================================================================= + +// Nothing here at present. + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PLF_CACHE_H +// End of plf_cache.h +
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/jmr3904/current/include/plf_intr.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// JMR3904 Interrupt and clock support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jskov, +// gthomas, jlarmour +// Date: 1999-02-16 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for the JMR3904 board. +// +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +//-------------------------------------------------------------------------- + +// No platform specific stuff at present. + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +// End of plf_intr.h
--- a/packages/hal/mips/jmr3904/current/src/PKGconf.mak +++ b/packages/hal/mips/jmr3904/current/src/PKGconf.mak @@ -28,11 +28,11 @@ #####COPYRIGHTEND#### #============================================================================== -PACKAGE := hal_tx39_jmr3904 +PACKAGE := hal_mips_tx39_jmr3904 include ../../../../../pkgconf/pkgconf.mak LIBRARY := libtarget.a -COMPILE := hal_diag.c jmr3904.S plf_stub.c +COMPILE := platform.S plf_misc.c plf_stub.c OTHER_OBJS := OTHER_TARGETS := OTHER_CLEAN :=
deleted file mode 100644 --- a/packages/hal/mips/jmr3904/current/src/hal_diag.c +++ /dev/null @@ -1,527 +0,0 @@ -/*============================================================================= -// -// hal_diag.c -// -// HAL diagnostic output code -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Cygnus eCos Public License -// Version 1.0 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://sourceware.cygnus.com/ecos -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Cygnus Operating System, released -// September 30, 1998. -// -// The Initial Developer of the Original Code is Cygnus. Portions created -// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): nickg -// Contributors: nickg -// Date: 1998-03-02 -// Purpose: HAL diagnostic output -// Description: Implementations of HAL diagnostic output support. -// -//####DESCRIPTIONEND#### -// -//===========================================================================*/ - -#include <pkgconf/hal.h> - -#include <cyg/infra/cyg_type.h> // base types -#include <cyg/infra/cyg_trac.h> // tracing macros -#include <cyg/infra/cyg_ass.h> // assertion macros - -#include <cyg/hal/hal_arch.h> -#include <cyg/hal/hal_diag.h> - -#include <cyg/hal/hal_intr.h> - -#include <cyg/hal/hal_io.h> - -/*---------------------------------------------------------------------------*/ - -//#define CYG_KERNEL_DIAG_LCD -#define CYG_KERNEL_DIAG_SERIAL0 - -#if defined(CYG_HAL_USE_ROM_MONITOR) - -#define CYG_KERNEL_DIAG_GDB - -#endif - -/*---------------------------------------------------------------------------*/ - -static cyg_uint8 leds = 0; - -void hal_diag_led(int x) -{ -// return; - leds ^= x; - - HAL_WRITE_UINT8( 0xfffff504, leds); - -#if 0 - { - int i; - - for( i = 0; i < 0x00020000; i++ ); - } -#endif -} - -/*---------------------------------------------------------------------------*/ - -#ifdef CYG_KERNEL_DIAG_SERIAL0 - -#define DIAG_BASE 0xfffff300 -#define DIAG_SLCR (DIAG_BASE+0x00) -#define DIAG_SLSR (DIAG_BASE+0x04) -#define DIAG_SLDICR (DIAG_BASE+0x08) -#define DIAG_SLDISR (DIAG_BASE+0x0C) -#define DIAG_SFCR (DIAG_BASE+0x10) -#define DIAG_SBRG (DIAG_BASE+0x14) -#define DIAG_TFIFO (DIAG_BASE+0x20) -#define DIAG_RFIFO (DIAG_BASE+0x30) - -#define BRG_T0 0x0000 -#define BRG_T2 0x0100 -#define BRG_T4 0x0200 -#define BRG_T5 0x0300 - - -void hal_diag_init() -{ -#if defined(CYG_HAL_USE_ROM_MONITOR) -// If we are using the ROM monitor, it has already -// initialized the serial line. -#else -//hal_diag_led(0x10); - HAL_WRITE_UINT16( DIAG_SLCR , 0x0020 ); - - HAL_WRITE_UINT16( DIAG_SLDICR , 0x0000 ); - - HAL_WRITE_UINT16( DIAG_SFCR , 0x0000 ); - -#if CYGHWR_HAL_MIPS_CPU_FREQ == 50 -// HAL_WRITE_UINT16( DIAG_SBRG , BRG_T2 | 20 ); // 9600 bps -// HAL_WRITE_UINT16( DIAG_SBRG , BRG_T2 | 10 ); // 19200 bps - HAL_WRITE_UINT16( DIAG_SBRG , BRG_T2 | 5 ); // 38400 bps -#elif CYGHWR_HAL_MIPS_CPU_FREQ == 66 -// HAL_WRITE_UINT16( DIAG_SBRG , BRG_T2 | 27 ); // 9600 bps -// HAL_WRITE_UINT16( DIAG_SBRG , BRG_T0 | 54 ); // 19200 bps - HAL_WRITE_UINT16( DIAG_SBRG , BRG_T0 | 27 ); // 38400 bps -#else -#error Unsupported CPU frequency -#endif -//hal_diag_led(0x10); -#endif -} - -void hal_diag_write_char_serial0( char c) -{ - CYG_WORD16 disr; - -//hal_diag_led(0x20); - - for(;;) - { - HAL_READ_UINT16( DIAG_SLDISR , disr ); - - if( disr & 0x0002 ) break; - } - - disr = disr & ~0x0002; - - HAL_WRITE_UINT8( DIAG_TFIFO, c ); - - HAL_WRITE_UINT16( DIAG_SLDISR , disr ); - -//hal_diag_led(0x20); -} - -void hal_diag_drain_serial0(void) -{ - CYG_WORD16 disr; - - for(;;) - { - HAL_READ_UINT16( DIAG_SLDISR , disr ); - - if( disr & 0x0002 ) break; - } - - disr = disr & ~0x0002; - - HAL_WRITE_UINT16( DIAG_SLDISR , disr ); -} - -void hal_diag_read_char_serial0(char *c) -{ - CYG_WORD16 disr; - -//hal_diag_led(0x40); - for(;;) - { - - HAL_READ_UINT16( DIAG_SLDISR , disr ); - - if( disr & 0x0001 ) break; - } - - disr = disr & ~0x0001; - - HAL_READ_UINT8( DIAG_RFIFO, *c ); - - HAL_WRITE_UINT16( DIAG_SLDISR , disr ); - -//hal_diag_led(0x40); -} - - -void hal_diag_write_char(char c) -{ -#ifdef CYG_KERNEL_DIAG_GDB -#if 0 //defined(CYG_HAL_USE_ROM_MONITOR) - - typedef void rom_write_fn(char c); - rom_write_fn *fn = ((rom_write_fn **)0x80000100)[63]; - - fn(c); - -#else - static char line[100]; - static int pos = 0; -// register volatile cyg_uint16 *volatile tty_status = SERIAL1_SR; - - // No need to send CRs - if( c == '\r' ) return; - - line[pos++] = c; - - if( c == '\n' || pos == sizeof(line) ) - { - - // Disable interrupts. This prevents GDB trying to interrupt us - // while we are in the middle of sending a packet. The serial - // receive interrupt will be seen when we re-enable interrupts - // later. - CYG_INTERRUPT_STATE oldstate; - HAL_DISABLE_INTERRUPTS(oldstate); - - while(1) - { - static char hex[] = "0123456789ABCDEF"; - cyg_uint8 csum = 0; - int i; - char c1; - - hal_diag_write_char_serial0('$'); - hal_diag_write_char_serial0('O'); - csum += 'O'; - for( i = 0; i < pos; i++ ) - { - char ch = line[i]; - char h = hex[(ch>>4)&0xF]; - char l = hex[ch&0xF]; - hal_diag_write_char_serial0(h); - hal_diag_write_char_serial0(l); - csum += h; - csum += l; - } - hal_diag_write_char_serial0('#'); - hal_diag_write_char_serial0(hex[(csum>>4)&0xF]); - hal_diag_write_char_serial0(hex[csum&0xF]); - -#ifndef CYGDBG_HAL_MIPS_INSTALL_CTRL_C_ISR - hal_diag_read_char_serial0( &c1 ); - - if( c1 == '+' ) break; - - // FIXME: Need to make the following use - // cyg_hal_is_break() and cyg_hal_user_break(). - - if( c1 == 3 ) - HAL_BREAKPOINT(_breakinst); -#endif // ! CYGDBG_HAL_MIPS_INSTALL_CTRL_C_ISR -#if 0 - - // We must ack the interrupt caused by that read to avoid - // confusing the GDB stub ROM. -// HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_SIO_0 ); - - if( c1 == '+' ) break; - -#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) - if( c1 == 3 ) - { - // Ctrl-C: breakpoint. - extern void breakpoint(); - breakpoint(); - break; - } -#elif defined(CYG_HAL_USE_ROM_MONITOR) && defined(CYG_HAL_USE_ROM_MONITOR_GDB_STUBS) - if( c1 == 3 ) - { - // Ctrl-C: breakpoint. -// HAL_BREAKPOINT(_breakinst); - typedef void bpt_fn(); - bpt_fn *bfn = ((bpt_fn **)0x80000100)[61]; - - bfn(); - - break; - } -#elif defined(CYG_HAL_USE_ROM_MONITOR) && defined(CYG_HAL_USE_ROM_MONITOR_CYGMON) - if( c1 == 3 ) - { - // Ctrl-C: breakpoint. - HAL_BREAKPOINT(_breakinst); - - break; - } -#endif - -#else - break; -#endif - } - - pos = 0; - - // Wait for all data from serial line to drain - // and clear ready-to-send indication. - hal_diag_drain_serial0(); - - // And re-enable interrupts - HAL_RESTORE_INTERRUPTS( oldstate ); - - } -#endif -#else - hal_diag_write_char_serial0(c); -#endif -} - -void hal_diag_read_char(char *c) -{ - for(;;) - { -#if defined(CYG_KERNEL_DIAG_GDB) && defined(CYG_HAL_USE_ROM_MONITOR) - - typedef void rom_read_fn(char *c); - rom_read_fn *fn = ((rom_read_fn **)0x80000100)[62]; - - fn(c); - -#else - hal_diag_read_char_serial0(c); - -#endif - -#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) - if( *c == 3 ) - { - // Ctrl-C: breakpoint. - extern void breakpoint(void); - breakpoint(); - continue; - } -#elif defined(CYG_HAL_USE_ROM_MONITOR) - if( *c == 3 ) - { - // Ctrl-C: breakpoint. - -// HAL_BREAKPOINT(_breakinst); - typedef void bpt_fn(void); - bpt_fn *bfn = ((bpt_fn **)0x80000100)[61]; - - bfn(); - continue; - } -#endif - - break; - } -} - -#endif - -/*---------------------------------------------------------------------------*/ - -#ifdef CYG_KERNEL_DIAG_LCD - -/* ----------------------------------------------------------- */ -#define ISA_BASE 0xA0000000 -#define LCD_DATA *(volatile unsigned char*)(0x13400000+ISA_BASE) -#define LCD_CMD *(volatile unsigned char*)(0x13000000+ISA_BASE) - -#define DISPCLR 0x01 /* Display Clear */ -#define ECURINC 0x06 /* Cursor Increment */ -#define DISPCONT 0x08 /* Display Control */ -#define BLINK 0x01 /* Blink */ -#define CURON 0x02 /* Cursor ON */ -#define DISPON 0x04 /* Display ON */ -#define INITCMD 0x38 /* Initial Command */ -#define DDRAM 0x80 /* DDRAM address */ -#define LCDBUSY 0x80 /* Busy */ - -/* ----------------------------------------------------------- */ - -/* */ -/* JMZ-LCD202 LCD Display Unit */ -/* - Sample Program (for JMR-TX3904) - */ -/* */ - -static void readyLCD(){ - while(LCD_CMD & LCDBUSY); -} - -static void outLCD(unsigned char d){ - readyLCD(); - LCD_DATA = d; -} - -static void outLCD_CMD(unsigned char d){ - readyLCD(); - LCD_CMD = d; -} - -static void INIT_LCD(){ - outLCD_CMD(INITCMD); - outLCD_CMD(DISPCONT); - outLCD_CMD(DISPCLR); - outLCD_CMD(ECURINC); - outLCD_CMD(DISPCONT|BLINK|CURON|DISPON); -} - -#if 0 -static void MAIN(){ - int i; - static char c[]="JMZ-LCD202 LCD UNIT"; - static char d[]="Display Test Sample"; - - INIT_LCD(); - outLCD_CMD(DDRAM); - for (i=0;i<20;i++) outLCD(c[i]); - outLCD_CMD(DDRAM+0x40); - for (i=0;i<20;i++) outLCD(d[i]); -} -#endif - -#define LCD_LINE0 0x00 -#define LCD_LINE1 0x40 - -#define LCD_LINE_LENGTH 20 - -static char lcd_line0[LCD_LINE_LENGTH+1]; -static char lcd_line1[LCD_LINE_LENGTH+1]; -static char *lcd_line[2] = { lcd_line0, lcd_line1 }; -static int lcd_curline = 0; -static int lcd_linepos = 0; - -static void lcd_dis(int add, char *string); - -void hal_diag_init() -{ - int i; -//hal_diag_led(0x10); - - INIT_LCD(); - - lcd_curline = 0; - lcd_linepos = 0; - - for( i = 0; i < LCD_LINE_LENGTH; i++ ) - lcd_line[0][i] = lcd_line[1][i] = ' '; - - lcd_line[0][LCD_LINE_LENGTH] = lcd_line[1][LCD_LINE_LENGTH] = 0; - - lcd_dis( LCD_LINE0, lcd_line[0] ); - lcd_dis( LCD_LINE1, lcd_line[1] ); - -#if 0 - { - int i; - static char c[]="JMZ-LCD202 LCD UNIT"; - static char d[]="Display Test Sample"; - - outLCD_CMD(DDRAM); - for (i=0;i<20;i++) outLCD(c[i]); - outLCD_CMD(DDRAM+0x40); - for (i=0;i<20;i++) outLCD(d[i]); - } -#endif - -//hal_diag_led(0x10); -} - -/* this routine writes the string to the LCD */ -/* display after setting the address to add */ -static void lcd_dis(int add, char *string) -{ - int i; - - outLCD_CMD(DDRAM+add); - - for (i=0 ; i<LCD_LINE_LENGTH ; i++) outLCD(string[i]); -} - -void hal_diag_write_char( char c) -{ - int i; - -//hal_diag_led(0x20); - - // Truncate long lines - if( lcd_linepos >= LCD_LINE_LENGTH ) return; - - // ignore CR - if( c == '\r' ) return; - - if( c == '\n' ) - { - lcd_dis( LCD_LINE0, &lcd_line[lcd_curline^1][0] ); - lcd_dis( LCD_LINE1, &lcd_line[lcd_curline][0] ); - - // Do a line feed - lcd_curline ^= 1; - lcd_linepos = 0; - - for( i = 0; i < LCD_LINE_LENGTH; i++ ) - lcd_line[lcd_curline][i] = ' '; - - return; - } - - lcd_line[lcd_curline][lcd_linepos++] = c; - -//hal_diag_led(0x20); -} - -void hal_diag_read_char(char *c) -{ -//hal_diag_led(0x40); - -//hal_diag_led(0x40); -} - - -#endif - - -/*---------------------------------------------------------------------------*/ -/* End of hal_diag.c */
deleted file mode 100644 --- a/packages/hal/mips/jmr3904/current/src/jmr3904.S +++ /dev/null @@ -1,55 +0,0 @@ -##============================================================================= -## -## sim.S -## -## Simulator hardware setup -## -##============================================================================= -#####COPYRIGHTBEGIN#### -# -# ------------------------------------------- -# The contents of this file are subject to the Cygnus eCos Public License -# Version 1.0 (the "License"); you may not use this file except in -# compliance with the License. You may obtain a copy of the License at -# http://sourceware.cygnus.com/ecos -# -# Software distributed under the License is distributed on an "AS IS" -# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -# License for the specific language governing rights and limitations under -# the License. -# -# The Original Code is eCos - Embedded Cygnus Operating System, released -# September 30, 1998. -# -# The Initial Developer of the Original Code is Cygnus. Portions created -# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. -# ------------------------------------------- -# -#####COPYRIGHTEND#### -##============================================================================= -#######DESCRIPTIONBEGIN#### -## -## Author(s): nickg -## Contributors: nickg -## Date: 1998-02-05 -## Purpose: Simulator hardware setup -## Description: This file contains any code needed to initialize the -## hardware on the MIPS simulator. -## -######DESCRIPTIONEND#### -## -##============================================================================= - -#include <pkgconf/hal.h> - -##include <cyg/hal/mips.inc> - -#------------------------------------------------------------------------------ - - .globl hal_hardware_init -hal_hardware_init: - - jr $31 - -#------------------------------------------------------------------------------ -# end of sim.S \ No newline at end of file
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/jmr3904/current/src/platform.S @@ -0,0 +1,60 @@ +##============================================================================= +## +## platform.S +## +## MIPS JMR-TX3904 platform code +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors: nickg +## Date: 1999-04-20 +## Purpose: MIPS JMR-TX3904 platform code +## Description: Platform specific code for JMR-TX3904 board. +## +## +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +#endif + +#include <cyg/hal/arch.inc> + +##----------------------------------------------------------------------------- + +## nothing here at present. + +##----------------------------------------------------------------------------- +## end of platform.S + \ No newline at end of file
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/jmr3904/current/src/plf_misc.c @@ -0,0 +1,217 @@ +//========================================================================== +// +// plf_misc.c +// +// HAL platform miscellaneous functions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jlarmour +// Date: 1999-01-21 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // Base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // architectural definitions + +#include <cyg/hal/hal_intr.h> // Interrupt handling + +#include <cyg/hal/hal_cache.h> // Cache handling + +/*------------------------------------------------------------------------*/ + +extern void patch_dbg_syscalls(void * vector); + +/*------------------------------------------------------------------------*/ + +void hal_platform_init(void) +{ + // On the real hardware we also enable the cache. + // doing this here is a temporary measure until we + // have a proper platform specific place to do it. + +#if !defined(CYGHWR_HAL_TX39_JMR3904_ENABLE_TOE) + + HAL_ICACHE_INVALIDATE_ALL(); + HAL_ICACHE_ENABLE(); + HAL_DCACHE_INVALIDATE_ALL(); + HAL_DCACHE_ENABLE(); + + HAL_TX39_DEBUG_TOE_DISABLE(); + +#else + + // If TOE is enabled, caches are disabled by default + // until spurious Bus Timeout problem is fixed. + + HAL_ICACHE_INVALIDATE_ALL(); + HAL_ICACHE_DISABLE(); + HAL_DCACHE_INVALIDATE_ALL(); + HAL_DCACHE_DISABLE(); + + HAL_TX39_DEBUG_TOE_ENABLE(); + +#endif + +#if 0 +#if defined(CYG_HAL_USE_ROM_MONITOR) && \ + !defined(CYGDBG_INFRA_DIAG_USE_DEVICE) && \ + defined(CYG_HAL_TX39_JMR3904) + + { + static void hal_init_ctrlc_intr(void); + hal_init_ctrlc_intr(); + } + +#endif +#endif + +#if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ + defined(CYG_HAL_USE_ROM_MONITOR) && \ + defined(CYG_HAL_USE_ROM_MONITOR_CYGMON) + { + patch_dbg_syscalls( (void *)(&hal_vsr_table[0]) ); + } +#endif + +} + +/*------------------------------------------------------------------------*/ +/* Functions to support the detection and execution of a user provoked */ +/* program break. These are usually called from interrupt routines. */ + +cyg_bool cyg_hal_is_break(char *buf, int size) +{ + while( size ) + if( buf[--size] == 0x03 ) return true; + + return false; +} + +void cyg_hal_user_break( CYG_ADDRWORD *regs ) +{ +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) + + // Ctrl-C: breakpoint. + extern void breakpoint(void); + breakpoint(); + +#elif defined(CYG_HAL_USE_ROM_MONITOR) && defined(CYG_HAL_USE_ROM_MONITOR_GDB_STUBS) + + // Ctrl-C: breakpoint. + typedef void bpt_fn(void); + bpt_fn *bfn = ((bpt_fn **)0x80000100)[61]; + bfn(); + +#elif defined(CYG_HAL_USE_ROM_MONITOR) && defined(CYG_HAL_USE_ROM_MONITOR_CYGMON) + + // Ctrl-C: breakpoint. + typedef void install_bpt_fn(void *epc); + HAL_SavedRegisters *sreg = (HAL_SavedRegisters *)regs; + install_bpt_fn *ibp = (install_bpt_fn *)hal_vsr_table[35]; + if( ibp != NULL ) ibp((void *)sreg->pc); + +#endif + +} + +/*------------------------------------------------------------------------*/ +/* This code installs an interrupt handler to capture Ctrl-C. */ + +#if 0 +#if defined(CYG_HAL_USE_ROM_MONITOR) && \ + !defined(CYGDBG_INFRA_DIAG_USE_DEVICE) && \ + defined(CYG_HAL_TX39_JMR3904) + +#define DIAG_BASE 0xfffff300 +#define DIAG_SLCR (DIAG_BASE+0x00) +#define DIAG_SLSR (DIAG_BASE+0x04) +#define DIAG_SLDICR (DIAG_BASE+0x08) +#define DIAG_SLDISR (DIAG_BASE+0x0C) +#define DIAG_SFCR (DIAG_BASE+0x10) +#define DIAG_SBRG (DIAG_BASE+0x14) +#define DIAG_TFIFO (DIAG_BASE+0x20) +#define DIAG_RFIFO (DIAG_BASE+0x30) + +#define BRG_T0 0x0000 +#define BRG_T2 0x0100 +#define BRG_T4 0x0200 +#define BRG_T5 0x0300 + +static cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data, CYG_ADDRWORD regs) +{ + char c; + CYG_WORD16 disr; + + HAL_READ_UINT16( DIAG_SLDISR , disr ); + + if( disr & 0x0001 ) + { + + disr = disr & ~0x0001; + + HAL_READ_UINT8( DIAG_RFIFO, c ); + + HAL_WRITE_UINT16( DIAG_SLDISR , disr ); + + if( cyg_hal_is_break( &c , 1 ) ) + cyg_hal_user_break( regs ); + } + + return 0; +} + + +static void hal_init_ctrlc_intr(void) +{ + CYG_WORD16 dicr; + + HAL_INTERRUPT_ATTACH( CYGNUM_HAL_INTERRUPT_SIO_0, hal_ctrlc_isr, NULL, + NULL ); + + HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_SIO_0 ); + + HAL_READ_UINT16( DIAG_SLDICR , dicr ); + dicr = 0x0001; + HAL_WRITE_UINT16( DIAG_SLDICR , dicr ); +} + +#endif +#endif + +/*------------------------------------------------------------------------*/ +/* End of plf_misc.c */
--- a/packages/hal/mips/sim/current/ChangeLog +++ b/packages/hal/mips/sim/current/ChangeLog @@ -1,3 +1,22 @@ +1999-05-14 Nick Garnett <nickg@cygnus.co.uk> + + * src/plf_misc.c: + * src/platform.S: + * src/sim.S: + * src/PKGconf.mak (COMPILE): Added platform.S and plf_misc.c and + removed sim.S. + + * include/plf_intr.h: + * include/plf_cache.h: + * include/platform.inc: + Added these files to complete support for TX39 sim builds using + new HAL organization. + +1999-05-14 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/hal_mips_tx39_sim.h: New file to include + the common MIPS simulator configuration header file. + 1999-04-08 John Dallaway <jld@cygnus.co.uk> * include/pkgconf/mlt_*.*: Use double underscore substitution
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/sim/current/include/pkgconf/hal_mips_sim.h @@ -0,0 +1,67 @@ +#ifndef CYGONCE_PKGCONF_HAL_MIPS_SIM_H +#define CYGONCE_PKGCONF_HAL_MIPS_SIM_H +// ==================================================================== +// +// pkgconf/hal_mips_sim.h +// +// HAL configuration file +// +// ==================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Contributors: bartv +// Date: 1998-09-02 +// Purpose: To allow the user to edit HAL configuration options. +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + + +/* --------------------------------------------------------------------- + {{CFG_DATA + + cdl_package CYGPKG_HAL_MIPS_SIM { + display "Minimal simulator" + type radio + parent CYGPKG_HAL_MIPS + platform sim + description " + The minimal simulator HAL package is provided for when only + a simple simulation of the processor architecture is + desired, as opposed to detailed simulation of any specific + board. To use this minimal simulator the command + `target sim --board=jmr3904pal' should be used from inside + gdb. It is not possible to use any of the eCos device + drivers when the simulator is running in this mode" + } + + }}CFG_DATA */ + +/* -------------------------------------------------------------------*/ +#endif /* CYGONCE_PKGCONF_HAL_MIPS_SIM_H */ +/* EOF hal_mips_sim.h */
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/sim/current/include/pkgconf/hal_mips_tx39_sim.h @@ -0,0 +1,1 @@ +#include <pkgconf/hal_mips_sim.h>
deleted file mode 100644 --- a/packages/hal/mips/sim/current/include/pkgconf/hal_tx39_sim.h +++ /dev/null @@ -1,67 +0,0 @@ -#ifndef CYGONCE_PKGCONF_HAL_TX39_SIM_H -#define CYGONCE_PKGCONF_HAL_TX39_SIM_H -// ==================================================================== -// -// pkgconf/hal_tx39_sim.h -// -// HAL configuration file -// -// ==================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Cygnus eCos Public License -// Version 1.0 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://sourceware.cygnus.com/ecos -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Cygnus Operating System, released -// September 30, 1998. -// -// The Initial Developer of the Original Code is Cygnus. Portions created -// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -// ==================================================================== -//#####DESCRIPTIONBEGIN#### -// -// Author(s): bartv -// Contributors: bartv -// Date: 1998-09-02 -// Purpose: To allow the user to edit HAL configuration options. -// Description: -// -//####DESCRIPTIONEND#### -// -// ==================================================================== - - -/* --------------------------------------------------------------------- - {{CFG_DATA - - cdl_package CYGPKG_HAL_TX39_SIM { - display "Minimal simulator" - type radio - parent CYGPKG_HAL_TX39 - platform sim - description " - The minimal simulator HAL package is provided for when only - a simple simulation of the processor architecture is - desired, as opposed to detailed simulation of any specific - board. To use this minimal simulator the command - `target sim --board=jmr3904pal' should be used from inside - gdb. It is not possible to use any of the eCos device - drivers when the simulator is running in this mode" - } - - }}CFG_DATA */ - -/* -------------------------------------------------------------------*/ -#endif /* CYGONCE_PKGCONF_HAL_TX39_SIM_H */ -/* EOF hal_tx39_sim.h */
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/sim/current/include/pkgconf/mlt_mips_tx39_sim_ram.ldi @@ -0,0 +1,49 @@ +//=========================================================================== +// +// MLT linker script export - Wed Jan 13 10:41:43 1999 +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +MEMORY +{ + ram : ORIGIN = 0x80000000, LENGTH = 0x80000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0x80000000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_vsr_table (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rel__dyn (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/sim/current/include/pkgconf/mlt_mips_tx39_sim_ram.mlt @@ -0,0 +1,13 @@ +version 0 +region ram 80000000 80000 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 80000000 80000000 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 1 0 1 0 1 0 1 rodata rodata ! +section rodata 0 1 0 1 0 1 0 1 vsr_table vsr_table ! +section vsr_table 0 1 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! +section fixup 0 1 0 1 0 1 0 1 rel.dyn rel.dyn ! +section rel.dyn 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 1 0 1 data data ! +section data 0 8 0 1 0 1 0 1 bss bss ! +section bss 0 4 0 1 0 0 0 0 !
deleted file mode 100644 --- a/packages/hal/mips/sim/current/include/pkgconf/mlt_tx39_sim_ram.ldi +++ /dev/null @@ -1,49 +0,0 @@ -//=========================================================================== -// -// MLT linker script export - Wed Jan 13 10:41:43 1999 -// -//=========================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Cygnus eCos Public License -// Version 1.0 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://sourceware.cygnus.com/ecos -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Cygnus Operating System, released -// September 30, 1998. -// -// The Initial Developer of the Original Code is Cygnus. Portions created -// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//=========================================================================== - -MEMORY -{ - ram : ORIGIN = 0x80000000, LENGTH = 0x80000 -} - -SECTIONS -{ - SECTIONS_BEGIN - SECTION_rom_vectors (ram, 0x80000000, LMA_EQ_VMA) - SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_vsr_table (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_rel__dyn (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) - SECTIONS_END -}
deleted file mode 100644 --- a/packages/hal/mips/sim/current/include/pkgconf/mlt_tx39_sim_ram.mlt +++ /dev/null @@ -1,13 +0,0 @@ -version 0 -region ram 80000000 80000 0 ! -section rom_vectors 0 1 0 1 1 1 1 1 80000000 80000000 text text ! -section text 0 1 0 1 0 1 0 1 fini fini ! -section fini 0 1 0 1 0 1 0 1 rodata rodata ! -section rodata 0 1 0 1 0 1 0 1 vsr_table vsr_table ! -section vsr_table 0 1 0 1 0 1 0 1 rodata1 rodata1 ! -section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! -section fixup 0 1 0 1 0 1 0 1 rel.dyn rel.dyn ! -section rel.dyn 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! -section gcc_except_table 0 1 0 1 0 1 0 1 data data ! -section data 0 8 0 1 0 1 0 1 bss bss ! -section bss 0 4 0 1 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/sim/current/include/platform.inc @@ -0,0 +1,57 @@ +#ifndef CYGONCE_HAL_PLATFORM_INC +#define CYGONCE_HAL_PLATFORM_INC +##============================================================================= +## +## platform.inc +## +## JMR-TX3904 board assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors: nickg +## Date: 1999-04-06 +## Purpose: JMR-TX3904 board definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the JMR-TX3904 board. +## Usage: +## #include <cyg/hal/platform.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <cyg/hal/mips.inc> + +#------------------------------------------------------------------------------ + +# Nothing to define here + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_PLATFORM_INC +# end of platform.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/sim/current/include/plf_cache.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_PLF_CACHE_H +#define CYGONCE_PLF_CACHE_H + +//============================================================================= +// +// plf_cache.h +// +// HAL cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1998-02-17 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/plf_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/plf_cache.h> + +//============================================================================= + +// Nothing here at present. + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PLF_CACHE_H +// End of plf_cache.h +
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/sim/current/include/plf_intr.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// Sim Interrupt and clock support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jskov, +// gthomas, jlarmour +// Date: 1999-02-16 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for the JMR3904 board. +// +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +//-------------------------------------------------------------------------- + +// No platform specific stuff at present. + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +// End of plf_intr.h
--- a/packages/hal/mips/sim/current/src/PKGconf.mak +++ b/packages/hal/mips/sim/current/src/PKGconf.mak @@ -28,11 +28,11 @@ #####COPYRIGHTEND#### #============================================================================== -PACKAGE := hal_tx39_sim +PACKAGE := hal_mips_sim include ../../../../../pkgconf/pkgconf.mak LIBRARY := libtarget.a -COMPILE := hal_diag.c sim.S +COMPILE := hal_diag.c platform.S plf_misc.c OTHER_OBJS := OTHER_TARGETS := OTHER_CLEAN :=
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/sim/current/src/platform.S @@ -0,0 +1,54 @@ +##============================================================================= +## +## platform.S +## +## MIPS Sim platform code +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors: nickg +## Date: 1999-04-20 +## Purpose: MIPS Sim platform code +## Description: Platform specific code for Simulated target board. +## +## +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +##----------------------------------------------------------------------------- + +## Nothing to define here at present. + +##----------------------------------------------------------------------------- +## end of platform.S + \ No newline at end of file
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/sim/current/src/plf_misc.c @@ -0,0 +1,56 @@ +//========================================================================== +// +// plf_misc.c +// +// HAL platform miscellaneous functions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jlarmour +// Date: 1999-01-21 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // Base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +/*------------------------------------------------------------------------*/ + +void hal_platform_init(void) +{ +} + +/*------------------------------------------------------------------------*/ +/* End of plf_misc.c */
deleted file mode 100644 --- a/packages/hal/mips/sim/current/src/sim.S +++ /dev/null @@ -1,55 +0,0 @@ -##============================================================================= -## -## sim.S -## -## Simulator hardware setup -## -##============================================================================= -#####COPYRIGHTBEGIN#### -# -# ------------------------------------------- -# The contents of this file are subject to the Cygnus eCos Public License -# Version 1.0 (the "License"); you may not use this file except in -# compliance with the License. You may obtain a copy of the License at -# http://sourceware.cygnus.com/ecos -# -# Software distributed under the License is distributed on an "AS IS" -# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -# License for the specific language governing rights and limitations under -# the License. -# -# The Original Code is eCos - Embedded Cygnus Operating System, released -# September 30, 1998. -# -# The Initial Developer of the Original Code is Cygnus. Portions created -# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. -# ------------------------------------------- -# -#####COPYRIGHTEND#### -##============================================================================= -#######DESCRIPTIONBEGIN#### -## -## Author(s): nickg -## Contributors: nickg -## Date: 1998-02-05 -## Purpose: Simulator hardware setup -## Description: This file contains any code needed to initialize the -## hardware on the MIPS simulator. -## -######DESCRIPTIONEND#### -## -##============================================================================= - -#include <pkgconf/hal.h> - -##include <cyg/hal/mips.inc> - -#------------------------------------------------------------------------------ - - .globl hal_hardware_init -hal_hardware_init: - - jr $31 - -#------------------------------------------------------------------------------ -# end of sim.S \ No newline at end of file
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx39/current/ChangeLog @@ -0,0 +1,52 @@ +1999-05-14 Nick Garnett <nickg@cygnus.co.uk> + + * src/var_misc.c: Added definition of hal_interrupt_level[]. + + * include/variant.inc: + * src/variant.S: + Added these files. They contain stuff that was previously in the + jmr3904 platform files. + + * src/PKGconf.mak (COMPILE): Added variant.S + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + Imported whole directory tree into main trunk of repository. + +1999-05-11 Nick Garnett <nickg@cygnus.co.uk> + + * include/imp_cache.h + * include/imp_intr.h + * include/impl.h + * src/imp_misc.c: + * include/var_cache.h + * include/var_intr.h + * include/variant.inc + * src/var_misc.c: + Changed references to "imp" and "implementation" to "var" and + "variant" respectively. + + * include/var_arch.h + File added. + + * include/pkgconf/hal_tx39.h: + * include/pkgconf/hal_mips_tx39.h: + File hal_tx39.h renamed to match name synthesized by pkgconf.tcl. + +1999-04-22 Nick Garnett <nickg@cygnus.co.uk> + + * include/imp_cache.h: Move cache enables and disables here from + hal_cache.h since they are tx39 specific. + +1999-04-21 Nick Garnett <nickg@cygnus.co.uk> + + * src/imp_misc.c: Added this file to contain + hal_implementation_init(). + + * src/PKGconf.mak (COMPILE): Added imp_misc.c. + +1999-04-13 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/hal_tx39.h: Removed superfluous variant level + from configuration data. +
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx39/current/include/pkgconf/hal_mips_tx39.h @@ -0,0 +1,106 @@ +#ifndef CYGONCE_PKGCONF_HAL_TX39_H +#define CYGONCE_PKGCONF_HAL_TX39_H +// ==================================================================== +// +// pkgconf/hal_tx39.h +// +// HAL configuration file +// +// ==================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1999-04-06 +// Purpose: To allow the user to edit HAL configuration options. +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +#include <pkgconf/hal_mips.h> +#include CYGBLD_HAL_PLATFORM_H + +/* ------------------------------------------------------------------- + * Decide which variant of the MIPS family we have. + + {{CFG_DATA + + cdl_package CYGPKG_HAL_MIPS_TX39 { + display "TX39 variant" + type radio + parent CYGFUN_HAL_MIPS_VARIANTS + target mips_tx39 + description " + The TX39 architecture HAL package provides generic support + for this processor architecture. It is also necessary to + select a specific target platform HAL package." + } + + cdl_option CYGPKG_HAL_MIPS_TX3904 { + display "TX3904 microprocessor" + parent CYGPKG_HAL_MIPS_TX39 + type radio + description " + The TMPR3904F microprocessor. This is an emedded part that in + addition to the TX39 processor core has built in peripherals + such as memory controllers, DMA controllers, serial ports and + timers/counters." + } + + }}CFG_DATA */ + +#define CYGPKG_HAL_MIPS_TX3904 + +/* -------------------------------------------------------------------*/ +/* Workaround for TX3904 Timer TRR register problem */ +/* */ +/* We do it conditionally so that it is possible to override it on */ +/* the command line, for example, for a simulator build */ + +#ifndef CYGARC_TX39_PR19846 +//# define CYGHWR_HAL_MIPS_TX3904_TRR_REQUIRES_SYNC +#endif + +/* -------------------------------------------------------------------*/ +/* Translate the user defined CPU frequency into a the real number of */ +/* cycles. */ + +#ifdef CYGPKG_HAL_MIPS_TX3904 + +#if (CYGHWR_HAL_MIPS_CPU_FREQ == 50) +#define CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL 49152000 +#elif (CYGHWR_HAL_MIPS_CPU_FREQ == 66) +#define CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL 66355200 +#else +#error Unsupported TX3904 CPU frequency +#endif + +#endif + +/* -------------------------------------------------------------------*/ +#endif /* CYGONCE_PKGCONF_HAL_TX39_H */ +/* EOF hal_tx39.h */
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx39/current/include/var_arch.h @@ -0,0 +1,52 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H + +//========================================================================== +// +// var_arch.h +// +// Architecture specific abstractions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1999-02-17 +// Purpose: Define architecture abstractions +// Description: This file contains any extra or modified definitions for +// this variant of the architecture. +// Usage: #include <cyg/hal/var_arch.h> +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +//-------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_ARCH_H +// End of var_arch.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx39/current/include/var_cache.h @@ -0,0 +1,279 @@ +#ifndef CYGONCE_IMP_CACHE_H +#define CYGONCE_IMP_CACHE_H + +//============================================================================= +// +// imp_cache.h +// +// HAL cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1998-02-17 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/imp_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/plf_cache.h> + +//============================================================================= +// Toshiba TX3904 + +#ifdef CYGPKG_HAL_MIPS_TX3904 + +//----------------------------------------------------------------------------- +// Cache dimensions + +// Data cache +#define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line +#define HAL_DCACHE_WAYS 2 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line +#define HAL_ICACHE_WAYS 1 // Associativity of the cache + +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +// This uses a bit in the config register, which is TX39 specific. +#define HAL_DCACHE_ENABLE_DEFINED +#define HAL_DCACHE_ENABLE() \ +{ \ + asm volatile ("mfc0 $2,$3;" \ + "ori $2,$2,0x0010;" \ + "mtc0 $2,$3;" \ + : \ + : \ + : "$2" \ + ); \ + \ +} + +// Disable the data cache +#define HAL_DCACHE_DISABLE_DEFINED +#define HAL_DCACHE_DISABLE() \ +{ \ + asm volatile ("mfc0 $2,$3;" \ + "la $3,0xFFFFFFEF;" \ + "and $2,$2,$3;" \ + "mtc0 $2,$3;" \ + : \ + : \ + : "$2", "$3" \ + ); \ + \ +} + + +// Invalidate the entire cache +// The TX39 only has hit-invalidate on the DCACHE, not +// index-invalidate, so we cannot just empty the cache out without +// knowing what is in it. This is annoying. So, the best we can do is +// fill the cache with data that is unlikely to be there +// otherwise. Hence we read bytes from the ROM space since this is +// most likely to be code, and will not get out of sync even if it is not. +#define HAL_DCACHE_INVALIDATE_ALL_DEFINED +#define HAL_DCACHE_INVALIDATE_ALL() \ +{ \ + CYG_BYTE volatile *addr = (CYG_BYTE *)(0x9fc00000); \ + CYG_BYTE volatile tmp = 0; \ + int i; \ + for( i = 0; i < (HAL_DCACHE_SIZE*2); i += HAL_DCACHE_LINE_SIZE ) \ + { \ + tmp = addr[i]; \ + } \ +} + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC_DEFINED +#define HAL_DCACHE_SYNC() HAL_DCACHE_INVALIDATE_ALL() + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +#define HAL_DCACHE_LOCK_DEFINED +#define HAL_DCACHE_LOCK(_base_, _size_) \ +{ \ + asm volatile ("mfc0 $2,$7;" \ + "ori $2,$2,0x0100;" \ + "mtc0 $2,$7;" \ + : \ + : \ + : "$2" \ + ); \ +} + +// Undo a previous lock operation +#define HAL_DCACHE_UNLOCK_DEFINED +#define HAL_DCACHE_UNLOCK(_base_, _size_) \ +{ \ + asm volatile ("mfc0 $2,$7;" \ + "la $3,0xFFFFFEFF;" \ + "and $2,$2,$3;" \ + "mtc0 $2,$7;" \ + : \ + : \ + : "$2", "$3" \ + ); \ +} + +// Unlock entire cache +#define HAL_DCACHE_UNLOCK_ALL_DEFINED +#define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE) + + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) +#define HAL_DCACHE_FLUSH_DEFINED // Ensure no default definition + +// Write dirty cache lines to memory for the given address range. +//#define HAL_DCACHE_STORE( _base_ , _size_ ) +#define HAL_DCACHE_STORE_DEFINED // Disable default definition + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +// This uses a bit in the config register, which is TX39 specific. +#define HAL_ICACHE_ENABLE_DEFINED +#define HAL_ICACHE_ENABLE() \ +{ \ + asm volatile ("mfc0 $2,$3;" \ + "ori $2,$2,0x0020;" \ + "mtc0 $2,$3;" \ + : \ + : \ + : "$2" \ + ); \ + \ +} + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE_DEFINED +#define HAL_ICACHE_DISABLE() \ +{ \ + asm volatile ("mfc0 $2,$3;" \ + "la $3,0xFFFFFFDF;" \ + "and $2,$2,$3;" \ + "mtc0 $2,$3;" \ + : \ + : \ + : "$2", "$3" \ + ); \ + \ +} + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +#define HAL_ICACHE_LOCK_DEFINED +#define HAL_ICACHE_LOCK(_base_, _size_) \ +{ \ + asm volatile ("mfc0 $2,$7;" \ + "ori $2,$2,0x0200;" \ + "mtc0 $2,$7;" \ + : \ + : \ + : "$2" \ + ); \ +} + +// Undo a previous lock operation +#define HAL_ICACHE_UNLOCK_DEFINED +#define HAL_ICACHE_UNLOCK(_base_, _size_) \ +{ \ + asm volatile ("mfc0 $2,$7;" \ + "la $3,0xFFFFFDFF;" \ + "and $2,$2,$3;" \ + "mtc0 $2,$7;" \ + : \ + : \ + : "$2", "$3" \ + ); \ +} + +// Unlock entire cache +#define HAL_ICACHE_UNLOCK_ALL_DEFINED +#define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0, HAL_ICACHE_SIZE) + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +// This uses the index-invalidate cache operation since the TX39 does not +// have hit-invalidate on the instruction cache. +#define HAL_ICACHE_INVALIDATE_DEFINED +#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ +{ \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + HAL_ICACHE_DISABLE(); \ + for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ + { \ + asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \ + } \ + HAL_ICACHE_ENABLE(); \ +} + +#endif + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_IMP_CACHE_H +// End of imp_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx39/current/include/var_intr.h @@ -0,0 +1,277 @@ +#ifndef CYGONCE_HAL_IMP_INTR_H +#define CYGONCE_HAL_IMP_INTR_H + +//========================================================================== +// +// imp_intr.h +// +// TX39 Interrupt and clock support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jskov, +// gthomas, jlarmour +// Date: 1999-02-16 +// Purpose: TX39 Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for variants of the TX39 MIPS +// architecture. +// +// Usage: +// #include <cyg/hal/imp_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/plf_intr.h> + +//-------------------------------------------------------------------------- +// Interrupt vectors. + +#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED + +// These are decoded via the IP bits of the cause +// register when an external interrupt is delivered. + +#define CYGNUM_HAL_INTERRUPT_1 0 +#define CYGNUM_HAL_INTERRUPT_2 1 +#define CYGNUM_HAL_INTERRUPT_3 2 +#define CYGNUM_HAL_INTERRUPT_4 3 +#define CYGNUM_HAL_INTERRUPT_5 4 +#define CYGNUM_HAL_INTERRUPT_6 5 +#define CYGNUM_HAL_INTERRUPT_7 6 +#define CYGNUM_HAL_INTERRUPT_DMAC1_CH3 7 +#define CYGNUM_HAL_INTERRUPT_DMAC1_CH2 8 +#define CYGNUM_HAL_INTERRUPT_DMAC0_CH1 9 +#define CYGNUM_HAL_INTERRUPT_DMAC0_CH0 10 +#define CYGNUM_HAL_INTERRUPT_SIO_0 11 +#define CYGNUM_HAL_INTERRUPT_SIO_1 12 +#define CYGNUM_HAL_INTERRUPT_TMR_0 13 +#define CYGNUM_HAL_INTERRUPT_TMR_1 14 +#define CYGNUM_HAL_INTERRUPT_TMR_2 15 +#define CYGNUM_HAL_INTERRUPT_0 16 + +// Min/Max ISR numbers and how many there are +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX 16 +#define CYGNUM_HAL_ISR_COUNT 17 + +// The vector used by the Real time clock +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TMR_0 + +#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED + +#endif + +//-------------------------------------------------------------------------- +// Interrupt controller access. + +#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED + +#if defined(CYGPKG_HAL_MIPS_TX3904) + +#define CYG_HAL_MIPS_TX3904_ILR0 0xFFFFC010 +#define CYG_HAL_MIPS_TX3904_CConR 0xFFFFE000 + +// Array which stores the configured priority levels for the configured +// interrupts. +externC volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT]; + + +#define HAL_INTERRUPT_MASK( _vector_ ) \ +{ \ + HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \ + CYG_WORD32 _ilr_; \ + _reg_ += (_vector_)&0xC; \ + HAL_READ_UINT32( _reg_, _ilr_ ); \ + _ilr_ &= ~(7 << (((_vector_)&0x3)<<3)); \ + HAL_WRITE_UINT32( _reg_, _ilr_ ); \ +} + +#define HAL_INTERRUPT_UNMASK( _vector_ ) \ +{ \ + HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \ + CYG_WORD32 _ilr_; \ + _reg_ += (_vector_)&0xC; \ + HAL_READ_UINT32( _reg_, _ilr_ ); \ + _ilr_ |= hal_interrupt_level[_vector_] << (((_vector_)&0x3)<<3); \ + HAL_WRITE_UINT32( _reg_, _ilr_ ); \ +} + +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ +{ \ + if( _vector_ <= CYGNUM_HAL_INTERRUPT_7 || \ + _vector_ == CYGNUM_HAL_INTERRUPT_0 ) \ + { \ + cyg_uint32 _val_ = _vector_ + 1; \ + if( _val_ == CYGNUM_HAL_INTERRUPT_0 + 1 ) _val_ = 0; \ + HAL_WRITE_UINT8( CYG_HAL_MIPS_TX3904_CConR+1, _val_); \ + } \ +} + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ +{ \ + if( _vector_ <= CYGNUM_HAL_INTERRUPT_7 || \ + _vector_ == CYGNUM_HAL_INTERRUPT_0 ) \ + { \ + cyg_uint32 _val_ = 0; \ + if( _up_ ) _val_ |= 1; \ + if( !(_level_) ) _val_ |= 2; \ + HAL_WRITE_UINT16( CYG_HAL_MIPS_TX3904_CConR+2, _val_ ); \ + } \ +} + +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ +{ \ + HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \ + CYG_WORD32 _ilr_; \ + _reg_ += (_vector_)&0xC; \ + HAL_READ_UINT32( _reg_, _ilr_ ); \ + _ilr_ |= (_level_) << (((_vector_)&0x3)<<3); \ + HAL_WRITE_UINT32( _reg_, _ilr_ ); \ + hal_interrupt_level[_vector_] = _level_; \ +} + +#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED + +#else + +#error Unspecified TX39 variant + +#endif + +#endif + +//-------------------------------------------------------------------------- +// Clock control + +#ifndef CYGHWR_HAL_CLOCK_CONTROL_DEFINED + +#if defined(CYGPKG_HAL_MIPS_TX3904) + +#define CYG_HAL_MIPS_TX3904_TIMER_BASE 0xFFFFF000 +#define CYG_HAL_MIPS_TX3904_TIMER_CR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x00) +#define CYG_HAL_MIPS_TX3904_TIMER_SR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x04) +#define CYG_HAL_MIPS_TX3904_TIMER_CPR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x08) +#define CYG_HAL_MIPS_TX3904_TIMER_IMR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x10) +#define CYG_HAL_MIPS_TX3904_TIMER_DR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x20) +#define CYG_HAL_MIPS_TX3904_TIMER_RR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0xF0) + +#define HAL_CLOCK_INITIALIZE( _period_ ) \ +{ \ + HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_DR, 0x00000003 ); \ + HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_CPR, _period_ ); \ + HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_SR, 0x00000000 ); \ + HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_IMR, 0x00008001 ); \ + HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_CR, 0x000000C0 ); \ +} + +#define HAL_CLOCK_RESET( _vector_, _period_ ) \ +{ \ + HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_SR, 0x00000000 ); \ +} + +#if defined(CYGHWR_HAL_MIPS_TX3904_TRR_REQUIRES_SYNC) && \ + !defined(CYG_HAL_MIPS_SIM) + +// We need to sync and check the coprocessor 0 condition - this +// indicates whether data is present in the write buffer. We need to +// wait until the data to be written is flushed out. This works +// around a tx39 bug. gcc will insert a NOP after the asm insns. + +# define HAL_CLOCK_READ( _pvalue_ ) \ +CYG_MACRO_START \ + asm volatile ( \ + "sync; nop; 1: ; bc0f 1b" \ + : \ + : \ + : "$0" \ + ); \ + HAL_READ_UINT32( CYG_HAL_MIPS_TX3904_TIMER_RR, *(_pvalue_) ); \ +CYG_MACRO_END + +#else + +# define HAL_CLOCK_READ( _pvalue_ ) \ +CYG_MACRO_START \ + HAL_READ_UINT32( CYG_HAL_MIPS_TX3904_TIMER_RR, *(_pvalue_) ); \ +CYG_MACRO_END + +#endif + +#define CYGHWR_HAL_CLOCK_CONTROL_DEFINED + +#else + +#error Unspecified TX39 variant + +#endif + +#endif + +//-------------------------------------------------------------------------- +// Timeout exception support. This is TX39 specific. + +#if defined(CYGPKG_HAL_MIPS_TX3904) + +#define HAL_TX39_DEBUG_TOE_ENABLE() \ +{ \ + HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_CConR; \ + CYG_WORD32 _cconr_; \ + HAL_READ_UINT32( _reg_, _cconr_); \ + _cconr_ |= 0x04000000; \ + HAL_WRITE_UINT32( _reg_, _cconr_); \ +} + +#define HAL_TX39_DEBUG_TOE_DISABLE() \ +{ \ + HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_CConR; \ + CYG_WORD32 _cconr_; \ + HAL_READ_UINT32( _reg_, _cconr_); \ + _cconr_ &= 0xFBFFFFFF; \ + HAL_WRITE_UINT32( _reg_, _cconr_); \ +} + +#else + +#define HAL_TX39_DEBUG_TOE_ENABLE() + +#define HAL_TX39_DEBUG_TOE_DISABLE() + +#endif + + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_IMP_INTR_H +// End of imp_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx39/current/include/variant.inc @@ -0,0 +1,239 @@ +#ifndef CYGONCE_HAL_IMPL_INC +#define CYGONCE_HAL_IMPL_INC +##============================================================================= +## +## impl.inc +## +## TX39 family assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors: nickg +## Date: 1999-04-06 +## Purpose: TX39 family definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the TX39 CPU family. +## Usage: +## #include <cyg/hal/impl.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <cyg/hal/mips.inc> + +#include <cyg/hal/platform.inc> + +#include <pkgconf/hal.h> + +##----------------------------------------------------------------------------- +## Define CPU variant for architecture HAL. + +#define CYG_HAL_MIPS_R3000A +#define CYG_HAL_MIPS_R3900 + +##----------------------------------------------------------------------------- +## Indicate that the ISR tables are defined in variant.S + +#define CYG_HAL_MIPS_ISR_TABLES_DEFINED + +##----------------------------------------------------------------------------- +## TX39 Memory controller. + +#ifndef CYGPKG_HAL_MIPS_MEMC_DEFINED + +## ROM timing characteristics are dependent on the clock speed. + +#if (CYGHWR_HAL_MIPS_CPU_FREQ == 50) +#define ROM_CCR0_INIT 0x00000420 +#define DRAM_DREFC_INIT 0x00000180 +#elif (CYGHWR_HAL_MIPS_CPU_FREQ == 66) +#define ROM_CCR0_INIT 0x00000520 +#define DRAM_DREFC_INIT 0x00000200 +#else +#error Unsupported clock frequency +#endif + +## DRAM configuration is dependent on the DRAM device used. +## for 16MByte (4MBit (x4bit) x 8) 0x08024030 +## for 4MByte (1MBit (x4bit) x 8) 0x08013020 +## for 8MByte (1MBit (x4bit) x 8 x 2 banks) 0x08013020 + +#if defined CYGHWR_HAL_TX39_JMR3904_DRAM_CONFIG_INIT +#define DRAM_CONFIG_INIT CYGHWR_HAL_TX39_JMR3904_DRAM_CONFIG_INIT +#else +#define DRAM_CONFIG_INIT 0x08024030 +#endif + +#ifdef CYG_HAL_MIPS_JMR3904 + .macro hal_memc_init + + # These mappings need to be set up before we + # can use the stack and make calls to other + # functions + + # If we have been started from Cygmon, it should have + # already done a lot of this, but it should do no harm + # to reinitialize the following registers. + + # SCS0,1 base addr of ISA & PCI + la v0,0xffffe010 + la v1,0x20201410 + sw v1,0(v0) + + la v0,0xffffe014 + la v1,0xfffffcfc + sw v1,0(v0) + + # ROM configuration + .set at + la v0,0xffff9000 + lw v1,0(v0) + and v1,v1,0xffff0004 # keep hardware defaults + or v1,ROM_CCR0_INIT # install our values + sw v1,0(v0) + .set noat + + # SRAM config + la v0,0xffff9100 + la v1,0x00000000 + sw v1,0(v0) + + # ISA bus setup + la v0,0xb2100000 + la v1,4 + sb v1,0(v0) + + # Clear IMR (to cope with JMON) + la v0,0xffffc004 + la v1,0x00000000 + sw v1,0(v0) + +#if defined(CYG_HAL_STARTUP_ROM) + + # Only do this in ROM configurations. + + # DRAM Configuration + la v0, 0xffff8000 + la v1, DRAM_CONFIG_INIT + sw v1, 0(v0) + + # DBMR0 + la v0, 0xffff8004 + la v1, 0x00000000 + sw v1, 0(v0) + + # DWR0 + la v0, 0xffff8008 + la v1, 0x00000000 + sw v1, 0(v0) + + # DREFC - Depends on clock requency + la v0, 0xffff8800 + la v1, DRAM_DREFC_INIT + sw v1, 0(v0) + +#endif + + .endm +#endif + +#endif + +##----------------------------------------------------------------------------- +## TX39 interrupt handling. + +#ifndef CYGPKG_HAL_MIPS_INTC_DEFINED + +#ifdef CYGPKG_HAL_MIPS_TX3904 + + # Set all ILRX registers to 0, masking all external interrupts. + .macro hal_intc_init + la v0,0xFFFFC010 + move v1,zero + sw v1,0(v0) + sw v1,4(v0) + sw v1,8(v0) + sw v1,12(v0) + .endm + + .macro hal_intc_decode vnum + mfc0 v1,cause # get cause register + nop + srl v1,v1,10 # shift IP bits to ls bits + andi v1,v1,0x7F # isolate IP bits + la v0,hal_intc_translation_table # address of translation table + add v0,v0,v1 # offset of index byte + lb \vnum,0(v0) # load it + .endm + + +# This table translates from the 6 bit value supplied in the IP bits +# of the cause register into a 0..16 offset into the ISR tables. + .macro hal_intc_decode_data +hal_intc_translation_table: + .byte 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + .byte 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + .byte 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + .byte 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + .endm + +#define CYGPKG_HAL_MIPS_INTC_DEFINED + +#else + +#error Unknown TX39 variant + +#endif + +#endif + +#------------------------------------------------------------------------------ +# Diagnostics macros. + +#if 0 +#ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED + + # Set up PIO0 for debugging output + .macro hal_diag_init + la v0,0xfffff500 + la v1,0xff + sb v1,0(v0) + la v1,0 + sb v1,4(v0) + .endm + +#define CYGPKG_HAL_MIPS_DIAG_DEFINED + +#endif +#endif + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_IMPL_INC +# end of impl.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx39/current/src/PKGconf.mak @@ -0,0 +1,62 @@ +#============================================================================== +# +# makefile +# +# hal/mips/tx39/src +# +#============================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +#============================================================================== + +PACKAGE := hal_mips_tx39 +include ../../../../../pkgconf/pkgconf.mak + +LIBRARY := libtarget.a +COMPILE := hal_diag.c var_misc.c variant.S +OTHER_OBJS := +OTHER_TARGETS := ldscript.stamp +OTHER_CLEAN := ldscript.clean +OTHER_DEPS := ldscript.d + +include $(COMPONENT_REPOSITORY)/pkgconf/makrules.src + +.PHONY: ldscript.clean + +EXTRAS = $(wildcard $(PREFIX)/lib/libextras.a) + +ldscript.stamp: mips_tx39.ld $(EXTRAS) +ifneq ($(EXTRAS),) + $(LD) --whole-archive $(PREFIX)/lib/libextras.a -r -o $(PREFIX)/lib/extras.o + $(CC) -E -P -Wp,-MD,ldscript.tmp -DEXTRAS=$(EXTRAS) -xc $(INCLUDE_PATH) $(CFLAGS) -o $(PREFIX)/lib/target.ld $< +else + $(CC) -E -P -Wp,-MD,ldscript.tmp -xc $(INCLUDE_PATH) $(CFLAGS) -o $(PREFIX)/lib/target.ld $< +endif + @echo > ldscript.d + @echo $@ ':' $< '\' >> ldscript.d + @tail -n +2 ldscript.tmp >> ldscript.d + @rm ldscript.tmp + $(TOUCH) $@ + +ldscript.clean: + $(RM) -f $(PREFIX)/lib/target.ld + $(RM) -f ldscript.stamp
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx39/current/src/hal_diag.c @@ -0,0 +1,527 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1998-03-02 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_diag.h> + +#include <cyg/hal/hal_intr.h> + +#include <cyg/hal/hal_io.h> + +/*---------------------------------------------------------------------------*/ + +//#define CYG_KERNEL_DIAG_LCD +#define CYG_KERNEL_DIAG_SERIAL0 + +#if defined(CYG_HAL_USE_ROM_MONITOR) + +#define CYG_KERNEL_DIAG_GDB + +#endif + +/*---------------------------------------------------------------------------*/ + +static cyg_uint8 leds = 0; + +void hal_diag_led(int x) +{ +// return; + leds ^= x; + + HAL_WRITE_UINT8( 0xfffff504, leds); + +#if 0 + { + int i; + + for( i = 0; i < 0x00020000; i++ ); + } +#endif +} + +/*---------------------------------------------------------------------------*/ + +#ifdef CYG_KERNEL_DIAG_SERIAL0 + +#define DIAG_BASE 0xfffff300 +#define DIAG_SLCR (DIAG_BASE+0x00) +#define DIAG_SLSR (DIAG_BASE+0x04) +#define DIAG_SLDICR (DIAG_BASE+0x08) +#define DIAG_SLDISR (DIAG_BASE+0x0C) +#define DIAG_SFCR (DIAG_BASE+0x10) +#define DIAG_SBRG (DIAG_BASE+0x14) +#define DIAG_TFIFO (DIAG_BASE+0x20) +#define DIAG_RFIFO (DIAG_BASE+0x30) + +#define BRG_T0 0x0000 +#define BRG_T2 0x0100 +#define BRG_T4 0x0200 +#define BRG_T5 0x0300 + + +void hal_diag_init() +{ +#if defined(CYG_HAL_USE_ROM_MONITOR) +// If we are using the ROM monitor, it has already +// initialized the serial line. +#else +//hal_diag_led(0x10); + HAL_WRITE_UINT16( DIAG_SLCR , 0x0020 ); + + HAL_WRITE_UINT16( DIAG_SLDICR , 0x0000 ); + + HAL_WRITE_UINT16( DIAG_SFCR , 0x0000 ); + +#if CYGHWR_HAL_MIPS_CPU_FREQ == 50 +// HAL_WRITE_UINT16( DIAG_SBRG , BRG_T2 | 20 ); // 9600 bps +// HAL_WRITE_UINT16( DIAG_SBRG , BRG_T2 | 10 ); // 19200 bps + HAL_WRITE_UINT16( DIAG_SBRG , BRG_T2 | 5 ); // 38400 bps +#elif CYGHWR_HAL_MIPS_CPU_FREQ == 66 +// HAL_WRITE_UINT16( DIAG_SBRG , BRG_T2 | 27 ); // 9600 bps +// HAL_WRITE_UINT16( DIAG_SBRG , BRG_T0 | 54 ); // 19200 bps + HAL_WRITE_UINT16( DIAG_SBRG , BRG_T0 | 27 ); // 38400 bps +#else +#error Unsupported CPU frequency +#endif +//hal_diag_led(0x10); +#endif +} + +void hal_diag_write_char_serial0( char c) +{ + CYG_WORD16 disr; + +//hal_diag_led(0x20); + + for(;;) + { + HAL_READ_UINT16( DIAG_SLDISR , disr ); + + if( disr & 0x0002 ) break; + } + + disr = disr & ~0x0002; + + HAL_WRITE_UINT8( DIAG_TFIFO, c ); + + HAL_WRITE_UINT16( DIAG_SLDISR , disr ); + +//hal_diag_led(0x20); +} + +void hal_diag_drain_serial0(void) +{ + CYG_WORD16 disr; + + for(;;) + { + HAL_READ_UINT16( DIAG_SLDISR , disr ); + + if( disr & 0x0002 ) break; + } + + disr = disr & ~0x0002; + + HAL_WRITE_UINT16( DIAG_SLDISR , disr ); +} + +void hal_diag_read_char_serial0(char *c) +{ + CYG_WORD16 disr; + +//hal_diag_led(0x40); + for(;;) + { + + HAL_READ_UINT16( DIAG_SLDISR , disr ); + + if( disr & 0x0001 ) break; + } + + disr = disr & ~0x0001; + + HAL_READ_UINT8( DIAG_RFIFO, *c ); + + HAL_WRITE_UINT16( DIAG_SLDISR , disr ); + +//hal_diag_led(0x40); +} + + +void hal_diag_write_char(char c) +{ +#ifdef CYG_KERNEL_DIAG_GDB +#if 0 //defined(CYG_HAL_USE_ROM_MONITOR) + + typedef void rom_write_fn(char c); + rom_write_fn *fn = ((rom_write_fn **)0x80000100)[63]; + + fn(c); + +#else + static char line[100]; + static int pos = 0; +// register volatile cyg_uint16 *volatile tty_status = SERIAL1_SR; + + // No need to send CRs + if( c == '\r' ) return; + + line[pos++] = c; + + if( c == '\n' || pos == sizeof(line) ) + { + + // Disable interrupts. This prevents GDB trying to interrupt us + // while we are in the middle of sending a packet. The serial + // receive interrupt will be seen when we re-enable interrupts + // later. + CYG_INTERRUPT_STATE oldstate; + HAL_DISABLE_INTERRUPTS(oldstate); + + while(1) + { + static char hex[] = "0123456789ABCDEF"; + cyg_uint8 csum = 0; + int i; + char c1; + + hal_diag_write_char_serial0('$'); + hal_diag_write_char_serial0('O'); + csum += 'O'; + for( i = 0; i < pos; i++ ) + { + char ch = line[i]; + char h = hex[(ch>>4)&0xF]; + char l = hex[ch&0xF]; + hal_diag_write_char_serial0(h); + hal_diag_write_char_serial0(l); + csum += h; + csum += l; + } + hal_diag_write_char_serial0('#'); + hal_diag_write_char_serial0(hex[(csum>>4)&0xF]); + hal_diag_write_char_serial0(hex[csum&0xF]); + +#if 1 + hal_diag_read_char_serial0( &c1 ); + + if( c1 == '+' ) break; + + // FIXME: Need to make the following use + // cyg_hal_is_break() and cyg_hal_user_break(). + + if( c1 == 3 ) + HAL_BREAKPOINT(_breakinst); +#endif +#if 0 + + // We must ack the interrupt caused by that read to avoid + // confusing the GDB stub ROM. +// HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_SIO_0 ); + + if( c1 == '+' ) break; + +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) + if( c1 == 3 ) + { + // Ctrl-C: breakpoint. + extern void breakpoint(); + breakpoint(); + break; + } +#elif defined(CYG_HAL_USE_ROM_MONITOR) && defined(CYG_HAL_USE_ROM_MONITOR_GDB_STUBS) + if( c1 == 3 ) + { + // Ctrl-C: breakpoint. +// HAL_BREAKPOINT(_breakinst); + typedef void bpt_fn(); + bpt_fn *bfn = ((bpt_fn **)0x80000100)[61]; + + bfn(); + + break; + } +#elif defined(CYG_HAL_USE_ROM_MONITOR) && defined(CYG_HAL_USE_ROM_MONITOR_CYGMON) + if( c1 == 3 ) + { + // Ctrl-C: breakpoint. + HAL_BREAKPOINT(_breakinst); + + break; + } +#endif + +#else + break; +#endif + } + + pos = 0; + + // Wait for all data from serial line to drain + // and clear ready-to-send indication. + hal_diag_drain_serial0(); + + // And re-enable interrupts + HAL_RESTORE_INTERRUPTS( oldstate ); + + } +#endif +#else + hal_diag_write_char_serial0(c); +#endif +} + +void hal_diag_read_char(char *c) +{ + for(;;) + { +#if defined(CYG_KERNEL_DIAG_GDB) && defined(CYG_HAL_USE_ROM_MONITOR) + + typedef void rom_read_fn(char *c); + rom_read_fn *fn = ((rom_read_fn **)0x80000100)[62]; + + fn(c); + +#else + hal_diag_read_char_serial0(c); + +#endif + +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) + if( *c == 3 ) + { + // Ctrl-C: breakpoint. + extern void breakpoint(void); + breakpoint(); + continue; + } +#elif defined(CYG_HAL_USE_ROM_MONITOR) + if( *c == 3 ) + { + // Ctrl-C: breakpoint. + +// HAL_BREAKPOINT(_breakinst); + typedef void bpt_fn(void); + bpt_fn *bfn = ((bpt_fn **)0x80000100)[61]; + + bfn(); + continue; + } +#endif + + break; + } +} + +#endif + +/*---------------------------------------------------------------------------*/ + +#if defined(CYGPKG_HAL_MIPS_TX39_JMR3904) && defined(CYG_KERNEL_DIAG_LCD) + +/* ----------------------------------------------------------- */ +#define ISA_BASE 0xA0000000 +#define LCD_DATA *(volatile unsigned char*)(0x13400000+ISA_BASE) +#define LCD_CMD *(volatile unsigned char*)(0x13000000+ISA_BASE) + +#define DISPCLR 0x01 /* Display Clear */ +#define ECURINC 0x06 /* Cursor Increment */ +#define DISPCONT 0x08 /* Display Control */ +#define BLINK 0x01 /* Blink */ +#define CURON 0x02 /* Cursor ON */ +#define DISPON 0x04 /* Display ON */ +#define INITCMD 0x38 /* Initial Command */ +#define DDRAM 0x80 /* DDRAM address */ +#define LCDBUSY 0x80 /* Busy */ + +/* ----------------------------------------------------------- */ + +/* */ +/* JMZ-LCD202 LCD Display Unit */ +/* - Sample Program (for JMR-TX3904) - */ +/* */ + +static void readyLCD(){ + while(LCD_CMD & LCDBUSY); +} + +static void outLCD(unsigned char d){ + readyLCD(); + LCD_DATA = d; +} + +static void outLCD_CMD(unsigned char d){ + readyLCD(); + LCD_CMD = d; +} + +static void INIT_LCD(){ + outLCD_CMD(INITCMD); + outLCD_CMD(DISPCONT); + outLCD_CMD(DISPCLR); + outLCD_CMD(ECURINC); + outLCD_CMD(DISPCONT|BLINK|CURON|DISPON); +} + +#if 0 +static void MAIN(){ + int i; + static char c[]="JMZ-LCD202 LCD UNIT"; + static char d[]="Display Test Sample"; + + INIT_LCD(); + outLCD_CMD(DDRAM); + for (i=0;i<20;i++) outLCD(c[i]); + outLCD_CMD(DDRAM+0x40); + for (i=0;i<20;i++) outLCD(d[i]); +} +#endif + +#define LCD_LINE0 0x00 +#define LCD_LINE1 0x40 + +#define LCD_LINE_LENGTH 20 + +static char lcd_line0[LCD_LINE_LENGTH+1]; +static char lcd_line1[LCD_LINE_LENGTH+1]; +static char *lcd_line[2] = { lcd_line0, lcd_line1 }; +static int lcd_curline = 0; +static int lcd_linepos = 0; + +static void lcd_dis(int add, char *string); + +void hal_diag_init() +{ + int i; +//hal_diag_led(0x10); + + INIT_LCD(); + + lcd_curline = 0; + lcd_linepos = 0; + + for( i = 0; i < LCD_LINE_LENGTH; i++ ) + lcd_line[0][i] = lcd_line[1][i] = ' '; + + lcd_line[0][LCD_LINE_LENGTH] = lcd_line[1][LCD_LINE_LENGTH] = 0; + + lcd_dis( LCD_LINE0, lcd_line[0] ); + lcd_dis( LCD_LINE1, lcd_line[1] ); + +#if 0 + { + int i; + static char c[]="JMZ-LCD202 LCD UNIT"; + static char d[]="Display Test Sample"; + + outLCD_CMD(DDRAM); + for (i=0;i<20;i++) outLCD(c[i]); + outLCD_CMD(DDRAM+0x40); + for (i=0;i<20;i++) outLCD(d[i]); + } +#endif + +//hal_diag_led(0x10); +} + +/* this routine writes the string to the LCD */ +/* display after setting the address to add */ +static void lcd_dis(int add, char *string) +{ + int i; + + outLCD_CMD(DDRAM+add); + + for (i=0 ; i<LCD_LINE_LENGTH ; i++) outLCD(string[i]); +} + +void hal_diag_write_char( char c) +{ + int i; + +//hal_diag_led(0x20); + + // Truncate long lines + if( lcd_linepos >= LCD_LINE_LENGTH ) return; + + // ignore CR + if( c == '\r' ) return; + + if( c == '\n' ) + { + lcd_dis( LCD_LINE0, &lcd_line[lcd_curline^1][0] ); + lcd_dis( LCD_LINE1, &lcd_line[lcd_curline][0] ); + + // Do a line feed + lcd_curline ^= 1; + lcd_linepos = 0; + + for( i = 0; i < LCD_LINE_LENGTH; i++ ) + lcd_line[lcd_curline][i] = ' '; + + return; + } + + lcd_line[lcd_curline][lcd_linepos++] = c; + +//hal_diag_led(0x20); +} + +void hal_diag_read_char(char *c) +{ +//hal_diag_led(0x40); + +//hal_diag_led(0x40); +} + + +#endif + + +/*---------------------------------------------------------------------------*/ +/* End of hal_diag.c */
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx39/current/src/mips_tx39.ld @@ -0,0 +1,160 @@ +//=========================================================================== +// +// MLT linker script for MIPS TX39 +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +#include <pkgconf/system.h> + +STARTUP(vectors.o) +ENTRY(reset_vector) +#ifdef EXTRAS +INPUT(extras.o) +#endif +GROUP(libtarget.a libgcc.a) + +#define ALIGN_LMA 8 +#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1)) +#define LMA_EQ_VMA +#define FORCE_OUTPUT . = . + +#define SECTIONS_BEGIN + +#if defined(CYG_HAL_STARTUP_RAM) + +/* this version for RAM startup */ +#define SECTION_rom_vectors(_region_, _vma_, _lma_) \ + .rom_vectors _vma_ : _lma_ \ + { KEEP (*(.utlb_vector)) \ + . = ALIGN(0x80); KEEP(*(.other_vector)) \ + /* debug and reset vector not used in RAM version */ \ + KEEP(*(.debug_vector)) \ + KEEP (*(.reset_vector)) } \ + > _region_ + +#elif defined(CYG_HAL_STARTUP_ROM) + +/* this version for ROM startup */ +#define SECTION_rom_vectors(_region_, _vma_, _lma_) \ + .rom_vectors _vma_ : _lma_ \ + { KEEP (*(.reset_vector)) \ + . = ALIGN(0x100); KEEP (*(.utlb_vector)) \ + . = ALIGN(0x80); KEEP(*(.other_vector)) \ + . = ALIGN(0x100); KEEP(*(.debug_vector)) } \ + > _region_ + +#endif /* ROM startup version of ROM vectors */ + +#define SECTION_text(_region_, _vma_, _lma_) \ + .text _vma_ : _lma_ \ + { _stext = ABSOLUTE(.); \ + *(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) } \ + > _region_ \ + _etext = .; PROVIDE (etext = .); + +#define SECTION_fini(_region_, _vma_, _lma_) \ + .fini _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.fini) } \ + > _region_ + +#define SECTION_rodata(_region_, _vma_, _lma_) \ + .rodata _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.rodata*) } \ + > _region_ + +#define SECTION_vsr_table(_region_, _vma_, _lma_) \ + .vsr_table _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.vsr_table) } \ + > _region_ + +#define SECTION_rodata1(_region_, _vma_, _lma_) \ + .rodata1 _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.rodata1) } \ + > _region_ + +#define SECTION_fixup(_region_, _vma_, _lma_) \ + .fixup _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.fixup) } \ + > _region_ + +#define SECTION_rel__dyn(_region_, _vma_, _lma_) \ + .rel.dyn _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.rel.dyn) } \ + > _region_ + +#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \ + .gcc_except_table _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.gcc_except_table) } \ + > _region_ + +#define SECTION_data(_region_, _vma_, _lma_) \ + .data _vma_ : _lma_ \ + { __ram_data_start = ABSOLUTE (.); \ + *(.data*) *(.data1) \ + _GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \ + _GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \ + . = ALIGN (8); \ + SORT (CONSTRUCTORS) *(.ctors*) *(.dtors*) \ + . = ALIGN (8); \ + __DEVTAB__ = ABSOLUTE (.); KEEP (*(SORT (.devtab*))) __DEVTAB_END__ = ABSOLUTE (.); \ + . = ALIGN (8); \ + _GOT_START = ABSOLUTE (.); _gp = ABSOLUTE (.); __global = _gp; _GLOBAL_OFFSET_TABLE_ = ABSOLUTE (.); _SDA_BASE_ = ABSOLUTE (.); \ + *(.got.plt) *(.got) _GOT_END_ = ABSOLUTE (.); \ + *(.dynamic) *(.sdata*) *(.sbss*) *(.eh_frame) } \ + > _region_ \ + __rom_data_start = LOADADDR (.data); \ + __ram_data_end = .; PROVIDE (__ram_data_end = .); _edata = .; PROVIDE (edata = .); + +#define SECTION_bss(_region_, _vma_, _lma_) \ + .bss _vma_ : _lma_ \ + { __bss_start = ABSOLUTE (.); \ + *(.scommon) *(.dynbss) *(.bss) *(COMMON) \ + __bss_end = ABSOLUTE (.); } \ + > _region_ + +#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); \ + .debug 0 : { *(.debug) } \ + .line 0 : { *(.line) } \ + .debug_srcinfo 0 : { *(.debug_srcinfo) } \ + .debug_sfnames 0 : { *(.debug_sfnames) } \ + .debug_aranges 0 : { *(.debug_aranges) } \ + .debug_pubnames 0 : { *(.debug_pubnames) } \ + .debug_info 0 : { *(.debug_info) } \ + .debug_abbrev 0 : { *(.debug_abbrev) } \ + .debug_line 0 : { *(.debug_line) } \ + .debug_frame 0 : { *(.debug_frame) } \ + .debug_str 0 : { *(.debug_str) } \ + .debug_loc 0 : { *(.debug_loc) } \ + .debug_macinfo 0 : { *(.debug_macinfo) } \ + .debug_weaknames 0 : { *(.debug_weaknames) } \ + .debug_funcnames 0 : { *(.debug_funcnames) } \ + .debug_typenames 0 : { *(.debug_typenames) } \ + .debug_varnames 0 : { *(.debug_varnames) } + +#include CYGHWR_MEMORY_LAYOUT_LDI + +#ifndef CYGPKG_HAL_MIPS_SIM +hal_vsr_table = 0x80000100; +#endif
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx39/current/src/var_misc.c @@ -0,0 +1,64 @@ +//========================================================================== +// +// var_misc.c +// +// HAL implementation miscellaneous functions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jlarmour +// Date: 1999-01-21 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // Base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_intr.h> + +/*------------------------------------------------------------------------*/ +// Array which stores the configured priority levels for the configured +// interrupts. + +volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT]; + +/*------------------------------------------------------------------------*/ + +void hal_variant_init(void) +{ +} + +/*------------------------------------------------------------------------*/ +/* End of var_misc.c */
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/tx39/current/src/variant.S @@ -0,0 +1,97 @@ +##============================================================================= +## +## variant.S +## +## MIPS JMR-TX3904 variant code +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors: nickg +## Date: 1999-04-20 +## Purpose: MIPS JMR-TX3904 variant code +## Description: Variant specific code for JMR-TX3904 board. +## +## +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +#endif + +#include <cyg/hal/arch.inc> + +##----------------------------------------------------------------------------- +# Interrupt vector tables. +# These tables contain the isr, data and object pointers used to deliver +# interrupts to user code. + + .extern hal_default_isr + + .data + + .globl hal_interrupt_handlers +hal_interrupt_handlers: + .long hal_default_isr + .long hal_default_isr + .long hal_default_isr + .long hal_default_isr + .long hal_default_isr + .long hal_default_isr + .long hal_default_isr + .long hal_default_isr + .long hal_default_isr + .long hal_default_isr + .long hal_default_isr + .long hal_default_isr + .long hal_default_isr + .long hal_default_isr + .long hal_default_isr + .long hal_default_isr + .long hal_default_isr + + .globl hal_interrupt_data +hal_interrupt_data: + .rept 17 + .long 0 + .endr + + .globl hal_interrupt_objects +hal_interrupt_objects: + .rept 17 + .long 0 + .endr + +##----------------------------------------------------------------------------- +## end of variant.S + \ No newline at end of file
--- a/packages/hal/mn10300/arch/current/ChangeLog +++ b/packages/hal/mn10300/arch/current/ChangeLog @@ -1,3 +1,8 @@ +1999-05-13 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_arch.h (HAL_THREAD_INIT_CONTEXT): Align stack + (rather conservatively) before use. + 1999-04-28 Bart Veer <bartv@cygnus.co.uk> * src/PKGconf.mak:
--- a/packages/hal/mn10300/arch/current/include/hal_arch.h +++ b/packages/hal/mn10300/arch/current/include/hal_arch.h @@ -106,7 +106,7 @@ externC cyg_uint32 hal_msbit_index(cyg_u #define HAL_THREAD_INIT_CONTEXT( _sp_, _thread_, _entry_, _id_ ) \ { \ register HAL_SavedRegisters *_regs_; \ - _regs_ = (HAL_SavedRegisters *)(((CYG_ADDRWORD)(_sp_)&(~3)) - \ + _regs_ = (HAL_SavedRegisters *)(((CYG_ADDRWORD)(_sp_)&~15) - \ sizeof(HAL_SavedRegisters)*2); \ _regs_->d0 = (CYG_WORD)(_thread_); \ _regs_->d1 = (_id_)|0xddd1; \
--- a/packages/hal/powerpc/arch/current/ChangeLog +++ b/packages/hal/powerpc/arch/current/ChangeLog @@ -1,3 +1,8 @@ +1999-05-13 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_arch.h (HAL_THREAD_INIT_CONTEXT): Align stack + (rather conservatively) before use. + 1999-04-28 Bart Veer <bartv@cygnus.co.uk> * src/PKGconf.mak:
--- a/packages/hal/powerpc/arch/current/include/hal_arch.h +++ b/packages/hal/powerpc/arch/current/include/hal_arch.h @@ -118,7 +118,8 @@ externC void cyg_hal_deliver_exception( #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ CYG_MACRO_START \ - register CYG_WORD _sp_ = ((CYG_WORD)_sparg_)-CYGARC_PPC_STACK_FRAME_SIZE; \ + register CYG_WORD _sp_ = (((CYG_WORD)_sparg_) &~15) \ + - CYGARC_PPC_STACK_FRAME_SIZE; \ register HAL_SavedRegisters *_regs_; \ int _i_; \ _regs_ = (HAL_SavedRegisters *)((_sp_) - sizeof(HAL_SavedRegisters)); \
--- a/packages/hal/sparclite/arch/current/ChangeLog +++ b/packages/hal/sparclite/arch/current/ChangeLog @@ -1,3 +1,8 @@ +1999-05-13 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_arch.h (HAL_THREAD_INIT_CONTEXT): Align stack + (rather conservatively) before use. + 1999-04-28 Bart Veer <bartv@cygnus.co.uk> * src/PKGconf.mak:
--- a/packages/hal/sparclite/arch/current/src/icontext.c +++ b/packages/hal/sparclite/arch/current/src/icontext.c @@ -99,7 +99,7 @@ hal_thread_init_context( CYG_WORD sparg if ( 0 == (id & 0xffff0000) ) id <<= 16; - fp &= ~7; // round down to double alignment + fp &= ~15; // round down to double alignment frame = (HAL_FrameStructure *)( fp - sizeof( HAL_FrameStructure ) );
--- a/packages/infra/current/ChangeLog +++ b/packages/infra/current/ChangeLog @@ -1,3 +1,9 @@ +1999-05-14 Hugo Tyson <hmt@cygnus.co.uk> + + * include/cyg_type.h (CYG_INIT_COMPAT): add a new init priority + level for compatibility layers (for uITRON that is, but + potentially POSIX also perhaps, after libc anyway). + 1999-04-14 John Dallaway <jld@cygnus.co.uk> * include/pkgconf/infra.h: Add cdl_package doc attribute.
--- a/packages/infra/current/include/cyg_type.h +++ b/packages/infra/current/include/cyg_type.h @@ -255,6 +255,7 @@ typedef cyg_haladdrword CYG_ADDRWORD; #define CYG_INIT_KERNEL 40000 #define CYG_INIT_IO 49000 #define CYG_INIT_LIBC 50000 +#define CYG_INIT_COMPAT 55000 #define CYG_INIT_APPLICATION 60000 #define CYG_INIT_PREDEFAULT 65534 #define CYG_INIT_DEFAULT 65535
--- a/packages/io/serial/current/ChangeLog +++ b/packages/io/serial/current/ChangeLog @@ -1,3 +1,26 @@ +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + 1999-05-05 Jesper Skov <jskov@cygnus.co.uk>
--- a/packages/io/serial/current/include/pkgconf/io_serial.h +++ b/packages/io/serial/current/include/pkgconf/io_serial.h @@ -182,6 +182,7 @@ #undef CYGPKG_IO_SERIAL_TTY_TTY2 #define CYGDAT_IO_SERIAL_TTY_TTY2_DEV "/dev/ser2" + /* ---------------------------------------------------------------------------- {{CFG_DATA cdl_component CYGPKG_IO_SERIAL_ARM_PID { @@ -602,7 +603,7 @@ type bool requires CYGPKG_IO_SERIAL # parent CYGPKG_IO_SERIAL - parent CYGPKG_HAL_TX39_JMR3904 + parent CYGPKG_HAL_MIPS_TX39_JMR3904 description " This option enables the serial device drivers for the TX39 JMR3904." doc ref/ecos-ref/ecos-device-drivers.html @@ -711,6 +712,7 @@ #define CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BAUD 38400 #define CYGNUM_IO_SERIAL_TX39_JMR3904_SERIAL1_BUFSIZE 128 + // Note: this is not currently tied to a specific board since the ports are "on chip" /* ----------------------------------------------------------------------------
--- a/packages/io/serial/current/include/serial.h +++ b/packages/io/serial/current/include/serial.h @@ -80,7 +80,7 @@ typedef struct { cyg_drv_cond_t wait; cyg_drv_mutex_t lock; bool waiting; - bool abort; // Set by an outsider to kill processing + volatile bool abort; // Set by an outsider to kill processing volatile cyg_int32 pending; // This many bytes waiting to be sent } cbuf_t;
--- a/packages/io/serial/current/misc/serial.c +++ b/packages/io/serial/current/misc/serial.c @@ -141,7 +141,7 @@ serial_test( void ) cyg_uint32 stamp; #endif - res = cyg_io_lookup("/dev/tty1", &handle); + res = cyg_io_lookup("/dev/tty0", &handle); if (res != ENOERR) { diag_printf("Can't lookup - DEVIO error: %d\n", res); return;
--- a/packages/io/serial/current/src/PKGconf.mak +++ b/packages/io/serial/current/src/PKGconf.mak @@ -32,7 +32,7 @@ PACKAGE := io_serial include ../../../../pkgconf/pkgconf.mak include ../../../../pkgconf/system.mak -LIBRARY := +LIBRARY := libtarget.a EXTRAS_COMPILE := common/serial.c common/tty.c common/haldiag.c ifdef CYG_HAL_ARM_PID EXTRAS_COMPILE += arm/pid_serial_with_ints.c
--- a/packages/io/serial/current/src/arm/aeb_serial.c +++ b/packages/io/serial/current/src/arm/aeb_serial.c @@ -306,11 +306,10 @@ aeb_serial_DSR(cyg_vector_t vector, cyg_ aeb_serial_info *aeb_chan = (aeb_serial_info *)chan->dev_priv; volatile struct serial_port *port = (volatile struct serial_port *)aeb_chan->base; unsigned char isr; - isr = port->isr; - if ((isr & 0x0E) == ISR_Tx) { + isr = port->isr & 0x0E; + if (isr == ISR_Tx) { (chan->callbacks->xmt_char)(chan); - } else { - // Assume receive interrupt + } else if (isr == ISR_Rx) { (chan->callbacks->rcv_char)(chan, port->rhr); } cyg_drv_interrupt_unmask(aeb_chan->int_num);
--- a/packages/io/serial/current/src/arm/aeb_serial.h +++ b/packages/io/serial/current/src/arm/aeb_serial.h @@ -98,6 +98,7 @@ struct serial_port { // Interrupt status register #define ISR_Tx 0x02 +#define ISR_Rx 0x04 static unsigned char select_word_length[] = { LCR_WL5, // 5 bits / word (char)
--- a/packages/io/serial/current/src/arm/pid_serial.h +++ b/packages/io/serial/current/src/arm/pid_serial.h @@ -98,6 +98,7 @@ struct serial_port { // Interrupt status register #define ISR_Tx 0x02 +#define ISR_Rx 0x04 static unsigned char select_word_length[] = { LCR_WL5, // 5 bits / word (char)
--- a/packages/io/serial/current/src/arm/pid_serial_with_ints.c +++ b/packages/io/serial/current/src/arm/pid_serial_with_ints.c @@ -304,11 +304,10 @@ pid_serial_DSR(cyg_vector_t vector, cyg_ pid_serial_info *pid_chan = (pid_serial_info *)chan->dev_priv; volatile struct serial_port *port = (volatile struct serial_port *)pid_chan->base; unsigned char isr; - isr = port->isr; - if ((isr & 0x0E) == ISR_Tx) { + isr = port->isr & 0x0E; + if (isr == ISR_Tx) { (chan->callbacks->xmt_char)(chan); - } else { - // Assume receive interrupt + } else if (isr == ISR_Rx) { (chan->callbacks->rcv_char)(chan, port->rhr); } cyg_drv_interrupt_unmask(pid_chan->int_num);
--- a/packages/io/serial/current/src/powerpc/cogent_serial.h +++ b/packages/io/serial/current/src/powerpc/cogent_serial.h @@ -71,6 +71,7 @@ // Interrupt status register #define ISR_Tx 0x02 +#define ISR_Rx 0x04 // FIFO control register #define FCR_ENABLE 0x01
--- a/packages/io/serial/current/src/powerpc/cogent_serial_with_ints.c +++ b/packages/io/serial/current/src/powerpc/cogent_serial_with_ints.c @@ -373,10 +373,10 @@ cogent_serial_DSR(cyg_vector_t vector, c cyg_uint8 _iir; HAL_READ_UINT8(port+SER_16550_IIR, _iir); - if ((_iir & SIO_IIR_ID_MASK) == ISR_Tx) { + _iir &= SIO_IIR_ID_MASK; + if ( ISR_Tx == _iir ) { (chan->callbacks->xmt_char)(chan); - } else { - // Assume receive interrupt + } else if ( ISR_Rx == _iir ) { cyg_uint8 _c; HAL_READ_UINT8(port+SER_16550_RBR, _c); (chan->callbacks->rcv_char)(chan, _c);
--- a/packages/io/serial/current/tests/ser_test_protocol.inl +++ b/packages/io/serial/current/tests/ser_test_protocol.inl @@ -142,11 +142,6 @@ #endif //---------------------------------------------------------------------------- -// FIXME: The PPC sometimes sees a spurious byte. There is workaround code -// that can be enabled here. -#define HANDLE_SPURIOUS 1 - -//---------------------------------------------------------------------------- // The data in buffer and the cmd buffer #define IN_BUFFER_SIZE 1024 cyg_uint8 in_buffer[IN_BUFFER_SIZE]; @@ -666,7 +661,6 @@ test_binary(cyg_io_handle_t handle, int int icrc, host_crc; cyg_uint8 *p1; cyg_int8 host_status = 'O'; // host is happy by default - int spurious = 0; // Verify that the test can be run with available ressources. if (MODE_EOP_ECHO == mode && size > IN_BUFFER_SIZE) @@ -738,20 +732,6 @@ test_binary(cyg_io_handle_t handle, int Tcyg_io_read(handle, &in_buffer[0], &chunk_len); host_status = in_buffer[0]; -#if HANDLE_SPURIOUS - // FIXME: This occassionally reads back a spurious character - // from the transmission. It's not just noise, it's definitely - // a byte from the previously transmitted data. - if (in_buffer[0] != 'O' && in_buffer[1] == 'O') { - spurious = in_buffer[0]; - chunk_len = 1; - Tcyg_io_read(handle, &in_buffer[0], &chunk_len); - if (in_buffer[0] == 'K') { - host_status = 'O'; - } - } -#endif - // Reply that we have completed the test. { const char msg_done[] = "DONE"; @@ -759,13 +739,6 @@ test_binary(cyg_io_handle_t handle, int chunk_len = strlen(&msg_done[0]); Tcyg_io_write(handle, &msg_done[0], &chunk_len); } - -#if HANDLE_SPURIOUS - if (spurious) { - diag_printf("******* Spurious byte 0x%02x *******\n", spurious); - } -#endif - } break; case MODE_DUPLEX_ECHO: @@ -820,20 +793,6 @@ test_binary(cyg_io_handle_t handle, int Tcyg_io_read(handle, &in_buffer[0], &chunk_len); host_status = in_buffer[0]; -#if HANDLE_SPURIOUS - // FIXME: This occassionally reads back a spurious character - // from the transmission. It's not just noise, it's definitely - // a byte from the previously transmitted data. - if (in_buffer[0] != 'O' && in_buffer[1] == 'O') { - spurious = in_buffer[0]; - chunk_len = 1; - Tcyg_io_read(handle, &in_buffer[0], &chunk_len); - if (in_buffer[0] == 'K') { - host_status = 'O'; - } - } -#endif - // Reply that we have completed the test. { const char msg_done[] = "DONE"; @@ -841,12 +800,6 @@ test_binary(cyg_io_handle_t handle, int chunk_len = strlen(&msg_done[0]); Tcyg_io_write(handle, &msg_done[0], &chunk_len); } - -#if HANDLE_SPURIOUS - if (spurious) { - diag_printf("******* Spurious byte 0x%02x *******\n", spurious); - } -#endif } break; default:
--- a/packages/kernel/current/ChangeLog +++ b/packages/kernel/current/ChangeLog @@ -1,3 +1,31 @@ +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The following changes were all made in a branch and are now being + merged: + + 1999-05-06 Nick Garnett <nickg@cygnus.co.uk> + + * src/debug/dbg-thread-demux.c: + Use dbg-thread-syscall.h from HAL rather than local version. + Made dbg_thread_syscall_rmt_1() generic to all MIPS targets. + + * src/debug/dbg-thread-syscall.h: + Removed. Replaced by identical file in hal/common. + + 1999-04-21 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/kernel.h: + Added CYGDBG_KERNEL_INSTRUMENT_BUFFER_WRAP option. + + * include/instrmnt.h: Added CYG_INSTRUMENT_EVENT_THREAD_ENTER + event. + + * src/instrmnt/meminst.cxx (cyg_instrument): Added implementation + of CYGDBG_KERNEL_INSTRUMENT_BUFFER_WRAP option. + + * src/common/thread.cxx: Added extra instrumentation point on + thread entry. + 1999-05-10 Jesper Skov <jskov@cygnus.co.uk> * tests/stress_threads.c (main_program): Added workaround for a
--- a/packages/kernel/current/include/instrmnt.h +++ b/packages/kernel/current/include/instrmnt.h @@ -120,6 +120,7 @@ externC void cyg_instrument_disable( cyg #define CYG_INSTRUMENT_EVENT_THREAD_PRIORITY 6 #define CYG_INSTRUMENT_EVENT_THREAD_DELAY 7 #define CYG_INSTRUMENT_EVENT_THREAD_ALARM 8 +#define CYG_INSTRUMENT_EVENT_THREAD_ENTER 9 // Interrupt events #define CYG_INSTRUMENT_EVENT_INTR_RAISE 1
--- a/packages/kernel/current/include/pkgconf/kernel.h +++ b/packages/kernel/current/include/pkgconf/kernel.h @@ -791,6 +791,17 @@ of memory." } + cdl_option CYGNUM_KERNEL_INSTRUMENT_BUFFER_WRAP { + display "Wrap instrument buffer" + parent CYGPKG_KERNEL_INSTRUMENT + description " + When the instrumentation buffer is full it can either be restarted + from the beginning, overwriting older data, or it can stop at the + end. The former is useful if you want to look at the last entries + made while the latter is useful if you want to look at the first + few." + } + cdl_option CYGDBG_KERNEL_INSTRUMENT_FLAGS { display "Perform selective instrumentation" parent CYGPKG_KERNEL_INSTRUMENT @@ -946,6 +957,7 @@ #undef CYGPKG_KERNEL_INSTRUMENT #undef CYGVAR_KERNEL_INSTRUMENT_EXTERNAL_BUFFER #define CYGNUM_KERNEL_INSTRUMENT_BUFFER_SIZE 256 +#define CYGDBG_KERNEL_INSTRUMENT_BUFFER_WRAP #define CYGDBG_KERNEL_INSTRUMENT_FLAGS #define CYGDBG_KERNEL_INSTRUMENT_SCHED #define CYGDBG_KERNEL_INSTRUMENT_THREAD @@ -1120,7 +1132,7 @@ #endif -#if defined(CYG_HAL_MIPS_JMR3904) +#if defined(CYG_HAL_MIPS_TX39_JMR3904) #define CYGNUM_KERNEL_COUNTERS_RTC_RESOLUTION {1000000000, 100} #if (CYGHWR_HAL_MIPS_CPU_FREQ == 50) @@ -1139,6 +1151,7 @@ #endif + #if defined(CYG_HAL_POWERPC_MPC860) // Period is busclock/16/100.
--- a/packages/kernel/current/src/common/thread.cxx +++ b/packages/kernel/current/src/common/thread.cxx @@ -74,6 +74,8 @@ Cyg_HardwareThread::thread_entry( Cyg_Th Cyg_Scheduler::scheduler.need_reschedule = false; // finished rescheduling Cyg_Scheduler::scheduler.current_thread = thread; // restore current thread pointer + CYG_INSTRUMENT_THREAD(ENTER,thread,0); + #ifdef CYGSEM_KERNEL_SCHED_TIMESLICE // Reset the timeslice counter so that this thread gets a full // quantum.
--- a/packages/kernel/current/src/debug/dbg-thread-demux.c +++ b/packages/kernel/current/src/debug/dbg-thread-demux.c @@ -73,7 +73,7 @@ #include <cyg/infra/cyg_type.h> #include "cyg/hal/dbg-threads-api.h" -#include "dbg-thread-syscall.h" +#include "cyg/hal/dbg-thread-syscall.h" // ------------------------------------------------------------------------- @@ -125,10 +125,10 @@ static int dbg_thread_syscall_rmt( } // ------------------------------------------------------------------------- -// When Cygmon calls us on the TX39 It has its own value in GP. We need to +// When Cygmon calls us on the MIPS It has its own value in GP. We need to // save that and set our own before proceeding. -#ifdef CYG_HAL_TX39 +#ifdef CYGPKG_HAL_MIPS static int dbg_thread_syscall_rmt_1( enum dbg_syscall_ids id, union dbg_thread_syscall_parms * p @@ -137,15 +137,15 @@ static int dbg_thread_syscall_rmt_1( register long gp_save; int r; - asm ( "move %0,$28;" - ".extern _gp;" - "la $gp,_gp;" - : "=r"(gp_save) - ); + asm volatile ( "move %0,$28;" + ".extern _gp;" + "la $gp,_gp;" + : "=r"(gp_save) + ); r = dbg_thread_syscall_rmt( id, p ); - asm ( "move $gp,%0;" :: "r"(gp_save) ); + asm volatile ( "move $gp,%0;" :: "r"(gp_save) ); return r; @@ -177,7 +177,7 @@ void patch_dbg_syscalls(void * vector) #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT -#ifdef CYG_HAL_TX39 +#ifdef CYGPKG_HAL_MIPS f[DBG_SYSCALL_THREAD_VEC_NUM] = dbg_thread_syscall_rmt_1 ; #else f[DBG_SYSCALL_THREAD_VEC_NUM] = dbg_thread_syscall_rmt ;
deleted file mode 100644 --- a/packages/kernel/current/src/debug/dbg-thread-syscall.h +++ /dev/null @@ -1,77 +0,0 @@ - -/* - * Copyright (c) 1998,1999 Cygnus Solutions - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -/* This file should be included only by - thread-syscall-relay.c and - dbg-thread-demux.c - */ - - - -enum dbg_syscall_ids - { - dbg_null_func , - dbg_capabilities_func, - dbg_currthread_func, - dbg_threadlist_func, - dbg_threadinfo_func, - dbg_getthreadreg_func, - dbg_setthreadreg_func, - dbg_scheduler_func, - } ; - - -union dbg_thread_syscall_parms -{ - struct - { - struct dbg_capabilities * abilities ; - } cap_parms ; - - struct - { - threadref * ref ; - } currthread_parms ; - - struct - { - int startflag ; - threadref * lastid ; - threadref * nextthreadid ; - } threadlist_parms ; - - struct - { - threadref * ref ; - struct cygmon_thread_debug_info * info ; - } info_parms ; - - struct - { - threadref * thread ; - int regcount ; - void * registers ; - } reg_parms ; - struct - { - threadref * thread ; /* 64-bit thread identifier */ - int lock; /* 0 == unlock, 1 == lock */ - int mode; /* 0 == short (step), 1 == continue */ - } scheduler_parms ; -} ; - - -typedef int (*dbg_syscall_func) (enum dbg_syscall_ids id, - union dbg_thread_syscall_parms * p ) ;
--- a/packages/kernel/current/src/instrmnt/meminst.cxx +++ b/packages/kernel/current/src/instrmnt/meminst.cxx @@ -144,10 +144,16 @@ void cyg_instrument( cyg_uint32 type, CY p->arg2 = arg2; p++; +#ifdef CYGDBG_KERNEL_INSTRUMENT_BUFFER_WRAP if( p == &instrument_buffer_end ) instrument_buffer_pointer = &instrument_buffer_start; else instrument_buffer_pointer = p; - +#else + // when not wrapping, just continue to put further entries + // in the last slot. + if( p != &instrument_buffer_end ) + instrument_buffer_pointer = p; +#endif HAL_RESTORE_INTERRUPTS(old_ints); }
--- a/packages/packages +++ b/packages/packages @@ -159,6 +159,20 @@ package CYGPKG_HAL_I386_LINUX { hardware } +package CYGPKG_HAL_MIPS { + alias { "MIPS common HAL" hal_mips mips_hal mips_arch_hal } + directory hal/mips/arch/ + include_dir cyg/hal + hardware +} + +package CYGPKG_HAL_MIPS_SIM { + alias { "MIPS simulator support" hal_mips_sim mips_sim_hal } + directory hal/mips/sim + include_dir cyg/hal + hardware +} + package CYGPKG_HAL_MN10300 { alias { "MN10300 common HAL" hal_mn10300 mn10300_hal mn10300_arch_hal } directory hal/mn10300/arch @@ -229,26 +243,20 @@ package CYGPKG_HAL_SPARCLITE_SIM { hardware } -package CYGPKG_HAL_TX39 { - alias { "TX39 common HAL" hal_tx39 tx39_hal tx39_arch_hal } - directory hal/mips/arch/ +package CYGPKG_HAL_MIPS_TX39 { + alias { "TX39 chip HAL" hal_tx39 tx39_hal tx39_arch_hal } + directory hal/mips/tx39/ include_dir cyg/hal hardware } -package CYGPKG_HAL_TX39_JMR3904 { +package CYGPKG_HAL_MIPS_TX39_JMR3904 { alias { "TX39 jmr3904 support" hal_tx39_jmr3904 tx39_jmr3904_hal } directory hal/mips/jmr3904 include_dir cyg/hal hardware } -package CYGPKG_HAL_TX39_SIM { - alias { "TX39 simulator support" hal_tx39_sim tx39_sim_hal } - directory hal/mips/sim - include_dir cyg/hal - hardware -} package CYGPKG_IO { alias { "Common I/O Code" io io_common } @@ -257,7 +265,6 @@ package CYGPKG_IO { include_dir cyg/io } - package CYGPKG_IO_SERIAL { alias { "Serial Device Drivers" io_serial io_serial_common } directory io/serial @@ -278,3 +285,4 @@ package CYGPKG_DEVICES_WATCHDOG { default_value 1 include_dir cyg/devs } +
--- a/packages/targets +++ b/packages/targets @@ -107,10 +107,10 @@ target mn10300 { } -target tx39 { +target mips_tx39 { alias { TX39 mips-tx39 mips-tx39-elf } command_prefix mips-tx39-elf - packages CYGPKG_HAL_TX39 + packages { CYGPKG_HAL_MIPS CYGPKG_HAL_MIPS_TX39 } cflags { ERRFLAGS "-Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef" @@ -126,25 +126,26 @@ target tx39 { hal hal/mips/jmr3904 startup { ram rom } packages { - CYGPKG_HAL_TX39_JMR3904 + CYGPKG_HAL_MIPS_TX39_JMR3904 } } platform sim { alias { "Simulator" } startup { ram } packages { - CYGPKG_HAL_TX39_SIM + CYGPKG_HAL_MIPS_SIM } } } + target powerpc { alias { PowerPC powerpc-eabi } command_prefix powerpc-eabi packages { CYGPKG_HAL_POWERPC } cflags { - ARCHFLAGS "-mcpu=860 -D_SOFT_FLOAT" + ARCHFLAGS "-msoft-float -mcpu=860" ERRFLAGS "-Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef" CXXERRFLAGS "-Woverloaded-virtual" LANGFLAGS "-ffunction-sections -fdata-sections"