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1 /*============================================================================= |
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2 // |
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3 // hal_diag.c |
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4 // |
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5 // HAL diagnostic output code |
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6 // |
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7 //============================================================================= |
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8 //####COPYRIGHTBEGIN#### |
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9 // |
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10 // ------------------------------------------- |
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11 // The contents of this file are subject to the Cygnus eCos Public License |
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12 // Version 1.0 (the "License"); you may not use this file except in |
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13 // compliance with the License. You may obtain a copy of the License at |
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14 // http://sourceware.cygnus.com/ecos |
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15 // |
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16 // Software distributed under the License is distributed on an "AS IS" |
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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18 // License for the specific language governing rights and limitations under |
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19 // the License. |
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20 // |
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21 // The Original Code is eCos - Embedded Cygnus Operating System, released |
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22 // September 30, 1998. |
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23 // |
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24 // The Initial Developer of the Original Code is Cygnus. Portions created |
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25 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved. |
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26 // ------------------------------------------- |
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27 // |
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28 //####COPYRIGHTEND#### |
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29 //============================================================================= |
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30 //#####DESCRIPTIONBEGIN#### |
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31 // |
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32 // Author(s): nickg |
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33 // Contributors: nickg |
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34 // Date: 1998-03-02 |
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35 // Purpose: HAL diagnostic output |
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36 // Description: Implementations of HAL diagnostic output support. |
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37 // |
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38 //####DESCRIPTIONEND#### |
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39 // |
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40 //===========================================================================*/ |
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41 |
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42 #include <pkgconf/hal.h> |
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43 |
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44 #include <cyg/infra/cyg_type.h> // base types |
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45 #include <cyg/infra/cyg_trac.h> // tracing macros |
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46 #include <cyg/infra/cyg_ass.h> // assertion macros |
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47 |
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48 #include <cyg/hal/hal_diag.h> |
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49 #include <cyg/hal/hal_intr.h> |
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50 |
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51 /*---------------------------------------------------------------------------*/ |
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52 /* Select default diag channel to use */ |
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53 |
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54 //#define CYG_KERNEL_DIAG_ROMART |
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55 //#define CYG_KERNEL_DIAG_SERIAL1 |
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56 //#define CYG_KERNEL_DIAG_SERIAL2 |
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57 //#define CYG_KERNEL_DIAG_GDB |
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58 |
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59 #if !defined(CYG_KERNEL_DIAG_SERIAL1) && \ |
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60 !defined(CYG_KERNEL_DIAG_SERIAL2) && \ |
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61 !defined(CYG_KERNEL_DIAG_ROMART) |
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62 |
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63 # if defined(CYG_HAL_MN10300_STDEVAL1) |
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64 |
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65 # if defined(CYG_HAL_STARTUP_RAM) |
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66 |
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67 # if defined(CYG_HAL_USE_ROM_MONITOR_CYGMON) |
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68 |
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69 // If loaded into RAM via CYGMON we diag via |
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70 // serial 2 using GDB protocol |
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71 |
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72 # define CYG_KERNEL_DIAG_SERIAL2 |
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73 # define CYG_KERNEL_DIAG_GDB |
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74 |
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75 # elif defined(CYG_HAL_USE_ROM_MONITOR_SLOAD) |
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76 |
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77 // If loaded into RAM via SLOAD we diag via |
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78 // serial 1 |
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79 |
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80 # define CYG_KERNEL_DIAG_SERIAL1 |
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81 |
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82 # elif defined(CYG_HAL_USE_ROM_MONITOR_GDB_STUBS) |
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83 |
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84 // If loaded into RAM via GDB STUB ROM we diag via |
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85 // serial 1 using GDB protocol |
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86 |
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87 # define CYG_KERNEL_DIAG_SERIAL1 |
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88 # define CYG_KERNEL_DIAG_GDB |
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89 |
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90 # endif // defined(CYG_HAL_USE_ROM_MONITOR_CYGMON) |
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91 |
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92 # elif defined(CYG_HAL_STARTUP_ROM) |
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93 |
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94 // If we are ROM resident, we diag via serial 1 |
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95 |
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96 # define CYG_KERNEL_DIAG_SERIAL1 |
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97 |
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98 # endif // defined(CYG_HAL_STARTUP_RAM) |
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99 |
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100 # endif // defined(CYG_HAL_MN10300_STDEVAL1) |
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101 |
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102 #endif // if ... |
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103 |
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104 /*---------------------------------------------------------------------------*/ |
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105 // PromICE AI interface |
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106 |
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107 #if defined(CYG_HAL_MN10300_STDEVAL1_ROMART) || defined(CYG_KERNEL_DIAG_ROMART) |
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108 |
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109 #ifdef CYG_HAL_MN10300_STDEVAL1 |
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110 #define PROMICE_AILOC 0x40008000 |
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111 #endif |
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112 |
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113 #define PROMICE_BUS_SIZE 16 |
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114 #define PROMICE_BURST_SIZE 1 |
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115 |
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116 #if PROMICE_BUS_SIZE == 16 |
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117 |
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118 typedef volatile struct |
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119 { |
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120 volatile cyg_uint16 zero; |
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121 // cyg_uint16 pad1[PROMICE_BURST_SIZE]; |
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122 volatile cyg_uint16 one; |
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123 // cyg_uint16 pad2[PROMICE_BURST_SIZE]; |
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124 volatile cyg_uint16 data; |
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125 // cyg_uint16 pad3[PROMICE_BURST_SIZE]; |
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126 volatile cyg_uint16 status; |
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127 |
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128 } AISTRUCT; |
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129 |
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130 #endif |
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131 |
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132 AISTRUCT *AI = (AISTRUCT *)PROMICE_AILOC; |
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133 |
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134 #define PROMICE_STATUS_TDA 0x01 |
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135 #define PROMICE_STATUS_HDA 0x02 |
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136 #define PROMICE_STATUS_OVR 0x04 |
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137 |
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138 |
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139 void ai_diag_init() |
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140 { |
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141 volatile cyg_uint8 junk; |
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142 |
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143 while( AI->status == 0xCC ) |
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144 continue; |
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145 |
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146 junk = AI->data; |
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147 } |
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148 |
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149 static void ai_write_char(cyg_uint8 data) |
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150 { |
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151 volatile cyg_uint8 junk; |
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152 int i; |
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153 |
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154 // Wait for tda == 0 |
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155 while( (AI->status & PROMICE_STATUS_TDA) == PROMICE_STATUS_TDA ) |
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156 continue; |
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157 |
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158 // Send start bit |
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159 junk = AI->one; |
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160 |
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161 for( i = 0; i < 8; i++ ) |
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162 { |
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163 // send ls bit of data |
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164 if( (data & 1) == 1 ) |
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165 junk = AI->one; |
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166 else |
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167 junk = AI->zero; |
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168 |
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169 // shift down for next bit |
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170 data >>= 1; |
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171 } |
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172 |
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173 // Send stop bit |
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174 junk = AI->one; |
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175 |
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176 // all done |
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177 } |
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178 |
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179 void ai_diag_write_char(char c) |
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180 { |
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181 ai_write_char((cyg_uint8)c); |
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182 } |
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183 |
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184 void ai_diag_drain() {} |
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185 |
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186 void ai_diag_read_char(char *c) { *c = '\n'; } |
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187 |
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188 void ai_writes(char *s) |
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189 { |
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190 while( *s ) ai_write_char( *s++ ); |
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191 } |
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192 |
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193 void ai_write_hex( cyg_uint32 x) |
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194 { |
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195 int i; |
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196 ai_writes("0x"); |
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197 for( i = 28; i >=0 ; i-=4 ) |
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198 { |
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199 char *d = "0123456789ABCDEF"; |
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200 ai_write_char( d[(x>>i)&0xf] ); |
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201 } |
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202 ai_write_char(' '); |
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203 } |
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204 |
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205 #if defined(CYG_KERNEL_DIAG_ROMART) |
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206 |
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207 #define hal_diag_init_serial ai_diag_init |
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208 #define hal_diag_write_char_serial ai_diag_write_char |
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209 #define hal_diag_drain_serial ai_diag_drain |
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210 #define hal_diag_read_char_serial ai_diag_read_char |
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211 |
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212 #endif |
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213 |
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214 #endif |
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215 |
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216 /*---------------------------------------------------------------------------*/ |
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217 // MN10300 Serial line |
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218 |
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219 #if defined(CYG_HAL_MN10300_STDEVAL1_SERIAL1) || defined(CYG_KERNEL_DIAG_SERIAL1) |
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220 |
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221 // We use serial1 on MN103002 |
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222 #define SERIAL1_CR ((volatile cyg_uint16 *)0x34000810) |
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223 #define SERIAL1_ICR ((volatile cyg_uint8 *) 0x34000814) |
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224 #define SERIAL1_TXR ((volatile cyg_uint8 *) 0x34000818) |
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225 #define SERIAL1_RXR ((volatile cyg_uint8 *) 0x34000819) |
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226 #define SERIAL1_SR ((volatile cyg_uint16 *)0x3400081c) |
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227 |
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228 // Timer 1 provided baud rate divisor |
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229 #define TIMER1_MD ((volatile cyg_uint8 *)0x34001001) |
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230 #define TIMER1_BR ((volatile cyg_uint8 *)0x34001011) |
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231 #define TIMER1_CR ((volatile cyg_uint8 *)0x34001021) |
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232 |
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233 #define PORT3_MD ((volatile cyg_uint8 *)0x36008025) |
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234 |
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235 // Mystery register |
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236 #define TMPSCNT ((volatile cyg_uint8 *)0x34001071) |
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237 |
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238 #define SIO1_LSTAT_TRDY 0x20 |
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239 #define SIO1_LSTAT_RRDY 0x10 |
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240 |
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241 void hal_diag_init_serial1(void) |
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242 { |
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243 // 48 translates to 38400 baud. |
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244 *TIMER1_BR = 48; |
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245 |
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246 // Timer1 sourced from IOCLK |
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247 *TIMER1_MD = 0x80; |
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248 |
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249 // Mode on PORT3, used for serial line controls. |
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250 *PORT3_MD = 0x01; |
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251 |
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252 // No interrupts for now. |
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253 *SERIAL1_ICR = 0x00; |
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254 |
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255 // Source from timer 1, 8bit chars, enable tx and rx |
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256 *SERIAL1_CR = 0xc084; |
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257 } |
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258 |
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259 void hal_diag_write_char_serial1(char c) |
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260 { |
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261 register volatile cyg_uint16 *volatile tty_status = SERIAL1_SR; |
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262 register volatile cyg_uint8 *volatile tty_tx = SERIAL1_TXR; |
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263 |
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264 while( (*tty_status & SIO1_LSTAT_TRDY) != 0 ) continue; |
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265 |
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266 *tty_tx = c; |
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267 } |
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268 |
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269 void hal_diag_drain_serial1(void) |
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270 { |
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271 register volatile cyg_uint16 *volatile tty_status = SERIAL1_SR; |
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272 |
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273 while( (*tty_status & SIO1_LSTAT_TRDY) != 0 ) continue; |
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274 } |
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275 |
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276 void hal_diag_read_char_serial1(char *c) |
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277 { |
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278 register volatile cyg_uint16 *volatile tty_status = SERIAL1_SR; |
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279 register volatile cyg_uint8 *volatile tty_rx = SERIAL1_RXR; |
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280 |
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281 while( (*tty_status & SIO1_LSTAT_RRDY) == 0 ) continue; |
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282 |
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283 *c = *tty_rx; |
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284 |
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285 } |
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286 |
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287 #if defined(CYG_KERNEL_DIAG_SERIAL1) |
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288 |
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289 #define hal_diag_init_serial hal_diag_init_serial1 |
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290 #define hal_diag_write_char_serial hal_diag_write_char_serial1 |
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291 #define hal_diag_drain_serial hal_diag_drain_serial1 |
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292 #define hal_diag_read_char_serial hal_diag_read_char_serial1 |
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293 |
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294 #endif |
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295 |
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296 #endif |
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297 |
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298 #if defined(CYG_HAL_MN10300_STDEVAL1) |
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299 |
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300 void led(int x) |
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301 { |
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302 *((cyg_uint8 *)0x36008004) = x<<4; |
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303 } |
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304 |
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305 #endif |
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306 |
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307 |
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308 /*---------------------------------------------------------------------------*/ |
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309 |
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310 #if defined(CYG_HAL_MN10300_STDEVAL1_SERIAL2) || defined(CYG_KERNEL_DIAG_SERIAL2) |
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311 |
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312 // We use serial2 on MN103002 |
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313 #define SERIAL2_CR ((volatile cyg_uint16 *)0x34000820) |
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314 #define SERIAL2_ICR ((volatile cyg_uint8 *) 0x34000824) |
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315 #define SERIAL2_TXR ((volatile cyg_uint8 *) 0x34000828) |
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316 #define SERIAL2_RXR ((volatile cyg_uint8 *) 0x34000829) |
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317 #define SERIAL2_SR ((volatile cyg_uint8 *)0x3400082c) |
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318 #define SERIAL2_TR ((volatile cyg_uint8 *)0x3400082d) |
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319 |
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320 // Timer 2 provided baud rate divisor |
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321 #define TIMER2_MD ((volatile cyg_uint8 *)0x34001002) |
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322 #define TIMER2_BR ((volatile cyg_uint8 *)0x34001012) |
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323 #define TIMER2_CR ((volatile cyg_uint8 *)0x34001022) |
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324 |
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325 #define PORT3_MD ((volatile cyg_uint8 *)0x36008025) |
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326 |
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327 // Mystery register |
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328 #define TMPSCNT ((volatile cyg_uint8 *)0x34001071) |
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329 |
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330 #define SIO2_LSTAT_TRDY 0x20 |
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331 #define SIO2_LSTAT_RRDY 0x10 |
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332 |
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333 void hal_diag_init_serial2(void) |
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334 { |
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335 #if !defined(CYG_HAL_USE_ROM_MONITOR_CYGMON) |
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336 |
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337 // 16 and 22 translate to 38400 baud. |
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338 *TIMER2_BR = 16; |
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339 *SERIAL2_TR = 22; |
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340 |
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341 // Timer2 sourced from IOCLK |
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342 *TIMER2_MD = 0x80; |
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343 |
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344 // Mode on PORT3, used for serial line controls. |
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345 *PORT3_MD = 0x01; |
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346 |
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347 // No interrupts for now. |
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348 *SERIAL2_ICR = 0x00; |
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349 |
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350 // Source from timer 2, 8bit chars, enable tx and rx |
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351 *SERIAL2_CR = 0xc081; |
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352 |
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353 #endif |
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354 } |
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355 |
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356 void hal_diag_write_char_serial2(char c) |
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357 { |
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358 register volatile cyg_uint8 *volatile tty_status = SERIAL2_SR; |
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359 register volatile cyg_uint8 *volatile tty_tx = SERIAL2_TXR; |
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360 |
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361 while( (*tty_status & SIO2_LSTAT_TRDY) != 0 ) continue; |
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362 |
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363 *tty_tx = c; |
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364 } |
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365 |
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366 void hal_diag_drain_serial2(void) |
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367 { |
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368 register volatile cyg_uint8 *volatile tty_status = SERIAL2_SR; |
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369 |
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370 while( (*tty_status & SIO2_LSTAT_TRDY) != 0 ) continue; |
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371 } |
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372 |
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373 void hal_diag_read_char_serial2(char *c) |
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374 { |
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375 register volatile cyg_uint8 *volatile tty_status = SERIAL2_SR; |
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376 register volatile cyg_uint8 *volatile tty_rx = SERIAL2_RXR; |
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377 |
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378 while( (*tty_status & SIO2_LSTAT_RRDY) == 0 ) continue; |
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379 |
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380 *c = *tty_rx; |
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381 } |
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382 |
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383 #if defined(CYG_KERNEL_DIAG_SERIAL2) |
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384 |
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385 #define hal_diag_init_serial hal_diag_init_serial2 |
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386 #define hal_diag_write_char_serial hal_diag_write_char_serial2 |
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387 #define hal_diag_drain_serial hal_diag_drain_serial2 |
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388 #define hal_diag_read_char_serial hal_diag_read_char_serial2 |
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389 |
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390 #endif |
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391 |
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392 #endif |
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393 |
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394 /*---------------------------------------------------------------------------*/ |
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395 |
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396 void hal_diag_init(void) |
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397 { |
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398 hal_diag_init_serial(); |
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399 } |
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400 |
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401 void hal_diag_write_char(char c) |
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402 { |
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403 #ifdef CYG_KERNEL_DIAG_GDB |
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404 |
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405 static char line[100]; |
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406 static int pos = 0; |
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407 |
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408 // No need to send CRs |
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409 if( c == '\r' ) return; |
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410 |
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411 line[pos++] = c; |
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412 |
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413 if( c == '\n' || pos == sizeof(line) ) |
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414 { |
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415 CYG_INTERRUPT_STATE old; |
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416 |
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417 // Disable interrupts. This prevents GDB trying to interrupt us |
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418 // while we are in the middle of sending a packet. The serial |
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419 // receive interrupt will be seen when we re-enable interrupts |
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420 // later. |
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421 |
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422 HAL_DISABLE_INTERRUPTS(old); |
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423 |
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424 while(1) |
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425 { |
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426 static char hex[] = "0123456789ABCDEF"; |
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427 cyg_uint8 csum = 0; |
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428 int i; |
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429 |
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430 hal_diag_write_char_serial('$'); |
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431 hal_diag_write_char_serial('O'); |
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432 csum += 'O'; |
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433 for( i = 0; i < pos; i++ ) |
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434 { |
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435 char ch = line[i]; |
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436 char h = hex[(ch>>4)&0xF]; |
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437 char l = hex[ch&0xF]; |
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438 hal_diag_write_char_serial(h); |
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439 hal_diag_write_char_serial(l); |
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440 csum += h; |
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441 csum += l; |
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442 } |
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443 hal_diag_write_char_serial('#'); |
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444 hal_diag_write_char_serial(hex[(csum>>4)&0xF]); |
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445 hal_diag_write_char_serial(hex[csum&0xF]); |
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446 |
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447 #if 0 |
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448 { |
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449 char c1; |
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450 |
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451 hal_diag_read_char_serial( &c1 ); |
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452 |
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453 // We must ack the interrupt caused by that read to avoid |
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454 // confusing the GDB stub ROM. |
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455 HAL_INTERRUPT_ACKNOWLEDGE( CYG_VECTOR_EXTERNAL_2 ); |
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456 |
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457 if( c1 == '+' ) break; |
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458 |
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459 ai_writes("hal_diag_read_char_serial("); |
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460 ai_write_char(c1); |
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461 ai_writes(")\r\n"); |
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462 ai_writes("retry\r\n"); |
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463 |
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464 #if defined(CYG_HAL_USE_ROM_MONITOR) && defined(CYG_HAL_USE_ROM_MONITOR_CYGMON) |
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465 if( c1 == 3 ) |
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466 { |
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467 // Ctrl-C: breakpoint. |
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468 // HAL_BREAKPOINT(_breakinst); |
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469 typedef void bpt_fn(); |
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470 bpt_fn *bfn = ((bpt_fn **)0x80000100)[61]; |
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471 |
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472 bfn(); |
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473 |
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474 break; |
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475 } |
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476 #endif |
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477 |
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478 } |
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479 #else |
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480 break; |
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481 #endif |
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482 } |
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483 |
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484 pos = 0; |
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485 |
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486 // Wait for tx buffer to drain |
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487 hal_diag_drain_serial(); |
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488 |
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489 // And re-enable interrupts |
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490 HAL_RESTORE_INTERRUPTS(old); |
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491 |
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492 } |
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493 |
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494 #else |
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495 hal_diag_write_char_serial(c); |
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496 #endif |
|
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497 } |
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|
498 |
|
|
499 |
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|
500 |
|
|
501 |
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|
502 void hal_diag_read_char(char *c) |
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503 { |
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504 hal_diag_read_char_serial(c); |
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505 } |
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506 |
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507 |
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508 /*---------------------------------------------------------------------------*/ |
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509 /* End of hal_diag.c */ |
