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annotate packages/hal/arm/ebsa285/current/src/hal_diag.c @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
parents
children 84e4bde58b26
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76
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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1 /*=============================================================================
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2 //
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3 // hal_diag.c
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4 //
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5 // HAL diagnostic output code
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6 //
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7 //=============================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //=============================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): nickg, gthomas
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35 // Contributors:nickg, gthomas
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36 // Date: 1998-03-02
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37 // Purpose: HAL diagnostic output
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38 // Description: Implementations of HAL diagnostic output support.
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39 //
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40 //####DESCRIPTIONEND####
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41 //
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42 //===========================================================================*/
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43
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44 #include <pkgconf/hal.h>
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45 #include <pkgconf/system.h>
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46 #include CYGBLD_HAL_PLATFORM_H
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47
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48 #include <cyg/infra/cyg_type.h> // base types
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49 #include <cyg/infra/cyg_trac.h> // tracing macros
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50 #include <cyg/infra/cyg_ass.h> // assertion macros
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51
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52 #include <cyg/hal/hal_arch.h> // basic machine info
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53 #include <cyg/hal/hal_intr.h> // interrupt macros
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54 #include <cyg/hal/hal_io.h> // IO macros
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55 #include <cyg/hal/hal_diag.h>
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56 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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57 #include <cyg/hal/drv_api.h> // cyg_drv_interrupt_acknowledge
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58 #include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
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59 #endif
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60 #include <cyg/hal/hal_ebsa285.h> // Hardware definitions
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61
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62 #ifdef CYGSEM_HAL_ROM_MONITOR
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63 #define CYG_HAL_STARTUP_ROM
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64 #undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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65 #endif
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66
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67 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL)
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68 #define HAL_DIAG_USES_HARDWARE
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69 #endif
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70
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71 /*---------------------------------------------------------------------------*/
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72 // EBSA285 Serial Port (UARTx) for Debug
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73
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74 // Actually send character down the wire
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75 static void
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76 hal_diag_write_char_serial(char c)
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77 {
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78 // Wait for Tx FIFO not full
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79 while ((*SA110_UART_FLAG_REGISTER & SA110_TX_FIFO_STATUS_MASK) == SA110_TX_FIFO_BUSY)
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80 ;
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81 *SA110_UART_DATA_REGISTER = c;
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82 }
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83
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84 static bool
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85 hal_diag_read_serial(char *c)
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86 {
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87 long timeout = 1000000000; // A long time...
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88 while ((*SA110_UART_FLAG_REGISTER & SA110_RX_FIFO_STATUS_MASK) == SA110_RX_FIFO_EMPTY)
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89 if ( --timeout == 0 )
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90 return false;
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91 *c = (char)(*SA110_UART_DATA_REGISTER & 0xFF);
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92 return true;
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93 }
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94
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95 /*
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96 * Baud rate selection stuff
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97 */
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98 #if 0
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99 struct _baud {
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100 int baud;
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101 unsigned short divisor_high, divisor_low;
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102 };
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103
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104 const static struct _baud bauds[] = {
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105 #if (FCLK_MHZ == 50)
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106 { 300, 0xA, 0x2B}, /* 2603 = 0x0A2B */
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107 { 600, 0x5, 0x15}, /* 1301 = 0x0515 */
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108 { 1200, 0x2, 0x8A}, /* 650 = 0x028A */
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109 { 2400, 0x1, 0x45}, /* 325 = 0x0145 */
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110 { 4800, 0x0, 0xA2}, /* 162 = 0x00A2 */
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111 { 9600, 0x0, 0x50}, /* 80 = 0x0050 */
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112 { 19200, 0x0, 0x28}, /* 40 = 0x0028 */
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113 { 38400, 0x0, 0x13}, /* 19 = 0x0013 */
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114 #elif (FCLK_MHZ == 60)
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115 { 300, 0xC, 0x34}, /* 2603 = 0x0A2B */
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116 { 600, 0x6, 0x19}, /* 1301 = 0x0515 */
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117 { 1200, 0x3, 0x0C}, /* 650 = 0x028A */
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118 { 2400, 0x1, 0x86}, /* 325 = 0x0145 */
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119 { 4800, 0x0, 0xC2}, /* 162 = 0x00A2 */
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120 { 9600, 0x0, 0x61}, /* 80 = 0x0050 */
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121 { 19200, 0x0, 0x30}, /* 40 = 0x0028 */
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122 { 38400, 0x0, 0x17}, /* 19 = 0x0013 */
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123 #endif
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124 };
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125 #endif
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126
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127 void hal_diag_init(void)
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128 {
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129 int dummy;
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130 /*
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131 * Make sure everything is off
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132 */
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133 *SA110_UART_CONTROL_REGISTER = SA110_UART_DISABLED | SA110_SIR_DISABLED;
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134
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135 /*
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136 * Read the RXStat to drain the fifo
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137 */
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138 dummy = *SA110_UART_RXSTAT;
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139
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140 /*
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141 * Set the baud rate - this also turns the uart on.
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142 *
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143 * Note that the ordering of these writes is critical,
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144 * and the writes to the H_BAUD_CONTROL and CONTROL_REGISTER
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145 * are necessary to force the UART to update its register
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146 * contents.
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147 */
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148 *SA110_UART_L_BAUD_CONTROL = 0x13; // bp->divisor_low;
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149 *SA110_UART_M_BAUD_CONTROL = 0x00; // bp->divisor_high;
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150 *SA110_UART_H_BAUD_CONTROL = SA110_UART_BREAK_DISABLED |
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151 SA110_UART_PARITY_DISABLED |
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152 SA110_UART_STOP_BITS_ONE |
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153 SA110_UART_FIFO_ENABLED |
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154 SA110_UART_DATA_LENGTH_8_BITS;
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155 *SA110_UART_CONTROL_REGISTER = SA110_UART_ENABLED |
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156 SA110_SIR_DISABLED;
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157 // All done
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158 }
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159
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160 #ifdef HAL_DIAG_USES_HARDWARE
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161
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162 #ifdef DEBUG_DIAG
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163 #ifndef CYG_HAL_STARTUP_ROM
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164 #define DIAG_BUFSIZE 2048
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165 static char diag_buffer[DIAG_BUFSIZE];
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166 static int diag_bp = 0;
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167 #endif
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168 #endif
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169
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170 void hal_diag_read_char(char *c)
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171 {
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172 while (!hal_diag_read_serial(c)) ;
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173 }
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174
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175 void hal_diag_write_char(char c)
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176 {
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177 #ifdef DEBUG_DIAG
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178 #ifndef CYG_HAL_STARTUP_ROM
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179 diag_buffer[diag_bp++] = c;
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180 if (diag_bp == sizeof(diag_buffer)) diag_bp = 0;
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181 #endif
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182 #endif
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183 hal_diag_write_char_serial(c);
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184 }
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185
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186 #else // not HAL_DIAG_USES_HARDWARE - it uses GDB protocol
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187
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188 void
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189 hal_diag_read_char(char *c)
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190 {
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191 while (!hal_diag_read_serial(c)) ;
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192 }
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193
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194 void
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195 hal_diag_write_char(char c)
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196 {
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197 static char line[100];
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198 static int pos = 0;
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199
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200 #if 0
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201 // Do not unconditionally poke the XBUS LED location - XBUS may not be
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202 // available if external arbiter is in use. This fragment may still be
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203 // useful for debugging in the future, so left thus:
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204 {
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205 // int i;
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206 *(cyg_uint32 *)0x40012000 = 7 & (cyg_uint32)c; // LED XBUS location
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207 // for ( i = 0x1000000; i > 0; i-- ) ;
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208 }
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209 #endif
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210
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211 // No need to send CRs
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212 if( c == '\r' ) return;
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213
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214 line[pos++] = c;
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215
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216 if( c == '\n' || pos == sizeof(line) )
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217 {
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218
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219 CYG_INTERRUPT_STATE old;
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220
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221 // Disable interrupts. This prevents GDB trying to interrupt us
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222 // while we are in the middle of sending a packet. The serial
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223 // receive interrupt will be seen when we re-enable interrupts
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224 // later.
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225
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226 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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227 CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
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228 #else
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229 HAL_DISABLE_INTERRUPTS(old);
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230 #endif
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231
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232 while(1)
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233 {
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234 static char hex[] = "0123456789ABCDEF";
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235 cyg_uint8 csum = 0;
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236 int i;
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237 #ifndef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
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238 char c1;
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239 #endif
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240 hal_diag_write_char_serial('$');
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241 hal_diag_write_char_serial('O');
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242 csum += 'O';
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243 for( i = 0; i < pos; i++ )
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244 {
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245 char ch = line[i];
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246 char h = hex[(ch>>4)&0xF];
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247 char l = hex[ch&0xF];
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248 hal_diag_write_char_serial(h);
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249 hal_diag_write_char_serial(l);
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250 csum += h;
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251 csum += l;
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252 }
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253 hal_diag_write_char_serial('#');
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254 hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
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255 hal_diag_write_char_serial(hex[csum&0xF]);
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256
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257 #ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
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258
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259 break; // regardless
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260
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261 #else // not CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT Ie. usually...
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262
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263 // Wait for the ACK character '+' from GDB here and handle
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264 // receiving a ^C instead. This is the reason for this clause
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265 // being a loop.
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266 if (!hal_diag_read_serial(&c1))
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267 continue; // No response - try sending packet again
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268
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269 if( c1 == '+' )
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270 break; // a good acknowledge
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271
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272 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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273 cyg_drv_interrupt_acknowledge(CYG_DIAG_DEV_INT);
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274 if( c1 == 3 ) {
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275 // Ctrl-C: breakpoint.
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276 cyg_hal_gdb_interrupt(
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277 (target_register_t)__builtin_return_address(0) );
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278 break;
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279 }
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280 #endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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281
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282 #endif // ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
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283 // otherwise, loop round again
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284 }
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285
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286 pos = 0;
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287
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288
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289 // And re-enable interrupts
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290 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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291 CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
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292 #else
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293 HAL_RESTORE_INTERRUPTS(old);
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294 #endif
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295
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296 }
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297 }
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298 #endif
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299
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300 /*---------------------------------------------------------------------------*/
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301 #ifndef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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302 #ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
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303 // This routine is polled from the default ISR - the assumption is that any
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304 // other ISR installed knows what it's going and can handle a ^C correctly.
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305 int hal_ctrlc_isr( CYG_ADDRWORD vector, CYG_ADDRWORD data)
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306 {
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307 char c;
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308 int reg;
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309 if ( CYG_DIAG_DEV_INT != vector )
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310 return 0; // not for us
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311
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312 reg = *SA110_UART_FLAG_REGISTER;
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313 // read it anyway just in case - no harm done and we might prevent an
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314 // interrup loop
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315 c = (char)(*SA110_UART_DATA_REGISTER & 0xFF);
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316 if ( (reg & SA110_RX_FIFO_STATUS_MASK) != SA110_RX_FIFO_EMPTY ) {
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317 if ( 3 == c ) {
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318 HAL_BREAKPOINT( hal_ctrlc_isr_breakinst );
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319 }
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320 }
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321 return 1;
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322 }
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323 #endif
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324 #endif
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325
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326 /*---------------------------------------------------------------------------*/
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327 /* End of hal_diag.c */