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1 #ifndef CYGONCE_HAL_CACHE_H |
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2 #define CYGONCE_HAL_CACHE_H |
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3 |
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4 //============================================================================= |
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5 // |
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6 // hal_cache.h |
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7 // |
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8 // HAL cache control API |
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9 // |
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10 //============================================================================= |
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11 //####COPYRIGHTBEGIN#### |
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12 // |
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13 // ------------------------------------------- |
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14 // The contents of this file are subject to the Cygnus eCos Public License |
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15 // Version 1.0 (the "License"); you may not use this file except in |
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16 // compliance with the License. You may obtain a copy of the License at |
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17 // http://sourceware.cygnus.com/ecos |
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18 // |
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19 // Software distributed under the License is distributed on an "AS IS" |
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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21 // License for the specific language governing rights and limitations under |
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22 // the License. |
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23 // |
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released |
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25 // September 30, 1998. |
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26 // |
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27 // The Initial Developer of the Original Code is Cygnus. Portions created |
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28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
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29 // ------------------------------------------- |
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30 // |
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31 //####COPYRIGHTEND#### |
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32 //============================================================================= |
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33 //#####DESCRIPTIONBEGIN#### |
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34 // |
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35 // Author(s): nickg |
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36 // Contributors: nickg |
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37 // Date: 1998-02-17 |
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38 // Purpose: Cache control API |
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39 // Description: The macros defined here provide the HAL APIs for handling |
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40 // cache control operations. |
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41 // Usage: |
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42 // #include <cyg/hal/hal_cache.h> |
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43 // ... |
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44 // |
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45 // |
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46 //####DESCRIPTIONEND#### |
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47 // |
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48 //============================================================================= |
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49 |
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50 #include <pkgconf/hal.h> |
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51 #include <cyg/infra/cyg_type.h> |
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52 |
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53 //============================================================================= |
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54 // MIPS simulator |
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55 |
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56 #ifdef CYG_HAL_MIPS_SIM |
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57 |
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58 //----------------------------------------------------------------------------- |
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59 // Cache dimensions |
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60 |
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61 // Data cache |
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62 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes |
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63 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line |
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64 #define HAL_DCACHE_WAYS 2 // Associativity of the cache |
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65 |
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66 // Instruction cache |
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67 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes |
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68 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line |
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69 #define HAL_ICACHE_WAYS 2 // Associativity of the cache |
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70 |
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71 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) |
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72 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) |
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73 |
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74 //----------------------------------------------------------------------------- |
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75 // Global control of data cache |
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76 |
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77 // Enable the data cache |
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78 #define HAL_DCACHE_ENABLE() |
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79 |
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80 // Disable the data cache |
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81 #define HAL_DCACHE_DISABLE() |
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82 |
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83 // Invalidate the entire cache |
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84 #define HAL_DCACHE_INVALIDATE_ALL() |
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85 |
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86 // Synchronize the contents of the cache with memory. |
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87 #define HAL_DCACHE_SYNC() |
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88 |
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89 // Set the data cache refill burst size |
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90 //#define HAL_DCACHE_BURST_SIZE(_size_) |
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91 |
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92 // Set the data cache write mode |
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93 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) |
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94 |
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95 //#define HAL_DCACHE_WRITETHRU_MODE 0 |
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96 //#define HAL_DCACHE_WRITEBACK_MODE 1 |
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97 |
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98 // Load the contents of the given address range into the data cache |
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99 // and then lock the cache so that it stays there. |
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100 //#define HAL_DCACHE_LOCK(_base_, _size_) |
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101 |
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102 // Undo a previous lock operation |
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103 //#define HAL_DCACHE_UNLOCK(_base_, _size_) |
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104 |
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105 // Unlock entire cache |
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106 //#define HAL_DCACHE_UNLOCK_ALL() |
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107 |
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108 //----------------------------------------------------------------------------- |
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109 // Data cache line control |
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110 |
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111 // Allocate cache lines for the given address range without reading its |
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112 // contents from memory. |
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113 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) |
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114 |
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115 // Write dirty cache lines to memory and invalidate the cache entries |
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116 // for the given address range. |
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117 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) |
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118 |
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119 // Invalidate cache lines in the given range without writing to memory. |
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120 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) |
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121 |
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122 // Write dirty cache lines to memory for the given address range. |
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123 //#define HAL_DCACHE_STORE( _base_ , _size_ ) |
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124 |
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125 // Preread the given range into the cache with the intention of reading |
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126 // from it later. |
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127 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) |
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128 |
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129 // Preread the given range into the cache with the intention of writing |
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130 // to it later. |
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131 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) |
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132 |
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133 // Allocate and zero the cache lines associated with the given range. |
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134 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) |
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135 |
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136 //----------------------------------------------------------------------------- |
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137 // Global control of Instruction cache |
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138 |
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139 // Enable the instruction cache |
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140 #define HAL_ICACHE_ENABLE() |
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141 |
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142 // Disable the instruction cache |
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143 #define HAL_ICACHE_DISABLE() |
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144 |
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145 // Invalidate the entire cache |
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146 #define HAL_ICACHE_INVALIDATE_ALL() |
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147 |
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148 // Synchronize the contents of the cache with memory. |
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149 #define HAL_ICACHE_SYNC() |
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150 |
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151 // Set the instruction cache refill burst size |
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152 //#define HAL_ICACHE_BURST_SIZE(_size_) |
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153 |
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154 // Load the contents of the given address range into the instruction cache |
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155 // and then lock the cache so that it stays there. |
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156 //#define HAL_ICACHE_LOCK(_base_, _size_) |
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157 |
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158 // Undo a previous lock operation |
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159 //#define HAL_ICACHE_UNLOCK(_base_, _size_) |
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160 |
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161 // Unlock entire cache |
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162 //#define HAL_ICACHE_UNLOCK_ALL() |
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163 |
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164 //----------------------------------------------------------------------------- |
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165 // Instruction cache line control |
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166 |
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167 // Invalidate cache lines in the given range without writing to memory. |
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168 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) |
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169 |
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170 #endif |
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171 |
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172 |
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173 //============================================================================= |
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174 // Toshiba TX3904 |
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175 |
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176 #ifdef CYG_HAL_MIPS_TX3904 |
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177 |
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178 //----------------------------------------------------------------------------- |
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179 // Cache dimensions |
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180 |
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181 // Data cache |
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182 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes |
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183 #define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line |
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184 #define HAL_DCACHE_WAYS 2 // Associativity of the cache |
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185 |
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186 // Instruction cache |
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187 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes |
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188 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line |
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189 #define HAL_ICACHE_WAYS 1 // Associativity of the cache |
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190 |
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191 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) |
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192 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) |
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193 |
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194 //----------------------------------------------------------------------------- |
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195 // Global control of data cache |
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196 |
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197 // Enable the data cache |
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198 #define HAL_DCACHE_ENABLE() \ |
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199 { \ |
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200 asm volatile ("mfc0 $2,$3;" \ |
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201 "ori $2,$2,0x0010;" \ |
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202 "mtc0 $2,$3;" \ |
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203 : \ |
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204 : \ |
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205 : "$2" \ |
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206 ); \ |
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207 \ |
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208 } |
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209 |
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210 // Disable the data cache |
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211 #define HAL_DCACHE_DISABLE() \ |
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212 { \ |
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213 asm volatile ("mfc0 $2,$3;" \ |
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214 "la $3,0xFFFFFFEF;" \ |
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215 "and $2,$2,$3;" \ |
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216 "mtc0 $2,$3;" \ |
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217 : \ |
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218 : \ |
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219 : "$2", "$3" \ |
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220 ); \ |
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221 \ |
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222 } |
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223 |
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224 // Invalidate the entire cache |
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225 // The TX39 only has hit-invalidate on the DCACHE, not |
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226 // index-invalidate, so we cannot just empty the cache out without |
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227 // knowing what is in it. This is annoying. So, the best we can do is |
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228 // fill the cache with data that is unlikely to be there |
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229 // otherwise. Hence we read bytes from the ROM space since this is |
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230 // most likely to be code, and will not get out of sync even if it is not. |
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231 #define HAL_DCACHE_INVALIDATE_ALL() \ |
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232 { \ |
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233 CYG_BYTE volatile *addr = (CYG_BYTE *)(0x9fc00000); \ |
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234 CYG_BYTE volatile tmp = 0; \ |
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235 int i; \ |
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236 for( i = 0; i < (HAL_DCACHE_SIZE*2); i += HAL_DCACHE_LINE_SIZE ) \ |
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237 { \ |
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238 tmp = addr[i]; \ |
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239 } \ |
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240 } |
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241 |
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242 // Synchronize the contents of the cache with memory. |
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243 #define HAL_DCACHE_SYNC() HAL_DCACHE_INVALIDATE_ALL() |
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244 |
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245 // Set the data cache refill burst size |
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246 //#define HAL_DCACHE_BURST_SIZE(_size_) |
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247 |
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248 // Set the data cache write mode |
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249 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) |
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250 |
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251 //#define HAL_DCACHE_WRITETHRU_MODE 0 |
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252 //#define HAL_DCACHE_WRITEBACK_MODE 1 |
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253 |
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254 // Load the contents of the given address range into the data cache |
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255 // and then lock the cache so that it stays there. |
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256 #define HAL_DCACHE_LOCK(_base_, _size_) \ |
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257 { \ |
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258 asm volatile ("mfc0 $2,$7;" \ |
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259 "ori $2,$2,0x0100;" \ |
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260 "mtc0 $2,$7;" \ |
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261 : \ |
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262 : \ |
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263 : "$2" \ |
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264 ); \ |
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265 } |
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266 |
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267 // Undo a previous lock operation |
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268 #define HAL_DCACHE_UNLOCK(_base_, _size_) \ |
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269 { \ |
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270 asm volatile ("mfc0 $2,$7;" \ |
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271 "la $3,0xFFFFFEFF;" \ |
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272 "and $2,$2,$3;" \ |
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273 "mtc0 $2,$7;" \ |
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274 : \ |
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275 : \ |
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276 : "$2", "$3" \ |
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277 ); \ |
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278 } |
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279 |
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280 // Unlock entire cache |
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281 #define HAL_DCACHE_UNLOCK_ALL() |
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282 |
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283 //----------------------------------------------------------------------------- |
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284 // Data cache line control |
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285 |
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286 // Allocate cache lines for the given address range without reading its |
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287 // contents from memory. |
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288 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) |
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289 |
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290 // Write dirty cache lines to memory and invalidate the cache entries |
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291 // for the given address range. |
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292 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) |
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293 |
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294 // Invalidate cache lines in the given range without writing to memory. |
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295 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \ |
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296 { \ |
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297 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ |
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298 register CYG_WORD _size_ = (_asize_); \ |
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299 HAL_DCACHE_DISABLE(); \ |
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300 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ |
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301 { \ |
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302 asm volatile ("cache 17,0(%0)" : : "r"(_addr_) ); \ |
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303 } \ |
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304 HAL_DCACHE_ENABLE(); \ |
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305 } |
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306 |
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307 // Write dirty cache lines to memory for the given address range. |
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308 //#define HAL_DCACHE_STORE( _base_ , _size_ ) |
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309 |
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310 // Preread the given range into the cache with the intention of reading |
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311 // from it later. |
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312 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) |
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313 |
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314 // Preread the given range into the cache with the intention of writing |
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315 // to it later. |
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316 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) |
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317 |
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318 // Allocate and zero the cache lines associated with the given range. |
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319 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) |
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320 |
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321 //----------------------------------------------------------------------------- |
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322 // Global control of Instruction cache |
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323 |
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324 // Enable the instruction cache |
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325 #define HAL_ICACHE_ENABLE() \ |
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326 { \ |
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327 asm volatile ("mfc0 $2,$3;" \ |
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328 "ori $2,$2,0x0020;" \ |
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329 "mtc0 $2,$3;" \ |
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330 : \ |
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331 : \ |
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332 : "$2" \ |
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333 ); \ |
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334 \ |
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335 } |
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336 |
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337 // Disable the instruction cache |
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338 #define HAL_ICACHE_DISABLE() \ |
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339 { \ |
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340 asm volatile ("mfc0 $2,$3;" \ |
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341 "la $3,0xFFFFFFDF;" \ |
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342 "and $2,$2,$3;" \ |
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343 "mtc0 $2,$3;" \ |
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344 : \ |
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345 : \ |
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346 : "$2", "$3" \ |
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347 ); \ |
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348 \ |
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349 } |
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350 |
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351 // Invalidate the entire cache |
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352 #define HAL_ICACHE_INVALIDATE_ALL() \ |
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353 { \ |
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354 register CYG_ADDRESS _addr_; \ |
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355 HAL_ICACHE_DISABLE(); \ |
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356 for( _addr_ = 0; _addr_ < HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ |
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357 { \ |
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358 asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \ |
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359 } \ |
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360 HAL_ICACHE_ENABLE(); \ |
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361 } |
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362 |
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363 // Synchronize the contents of the cache with memory. |
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364 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL() |
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365 |
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366 // Set the instruction cache refill burst size |
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367 //#define HAL_ICACHE_BURST_SIZE(_size_) |
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368 |
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369 // Load the contents of the given address range into the instruction cache |
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370 // and then lock the cache so that it stays there. |
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371 #define HAL_ICACHE_LOCK(_base_, _size_) \ |
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372 { \ |
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373 asm volatile ("mfc0 $2,$7;" \ |
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374 "ori $2,$2,0x0200;" \ |
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375 "mtc0 $2,$7;" \ |
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376 : \ |
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377 : \ |
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378 : "$2" \ |
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379 ); \ |
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380 } |
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381 |
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382 // Undo a previous lock operation |
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383 #define HAL_ICACHE_UNLOCK(_base_, _size_) \ |
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384 { \ |
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385 asm volatile ("mfc0 $2,$7;" \ |
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386 "la $3,0xFFFFFDFF;" \ |
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387 "and $2,$2,$3;" \ |
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388 "mtc0 $2,$7;" \ |
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389 : \ |
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390 : \ |
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391 : "$2", "$3" \ |
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392 ); \ |
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393 } |
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394 |
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395 // Unlock entire cache |
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396 #define HAL_ICACHE_UNLOCK_ALL() |
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397 |
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398 //----------------------------------------------------------------------------- |
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399 // Instruction cache line control |
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400 |
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401 // Invalidate cache lines in the given range without writing to memory. |
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402 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ |
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403 { \ |
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404 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ |
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405 register CYG_WORD _size_ = (_asize_); \ |
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406 HAL_ICACHE_DISABLE(); \ |
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407 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ |
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408 { \ |
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409 asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \ |
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410 } \ |
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411 HAL_ICACHE_ENABLE(); \ |
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412 } |
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413 |
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414 #endif |
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415 |
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416 //----------------------------------------------------------------------------- |
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417 // Check that a supported configuration has actually defined some macros. |
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418 |
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419 #ifndef HAL_DCACHE_ENABLE |
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420 |
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421 #error Unsupported MIPS configuration |
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422 |
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423 #endif |
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424 |
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425 //----------------------------------------------------------------------------- |
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426 #endif // ifndef CYGONCE_HAL_CACHE_H |
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427 // End of hal_cache.h |
