Mercurial > ecos-v2_0-branch
annotate packages/hal/powerpc/arch/current/include/hal_cache.h @ 16:4f2df4ab82c8 ecos-sw-1999-06-18
Merge from eCos master repository on 1999-06-18-15:25:04-BST
| author | jlarmour |
|---|---|
| date | Fri, 18 Jun 1999 07:59:09 +0000 |
| parents | d3fbcdfa1b2f |
| children | e7ba79f6d3a8 |
| rev | line source |
|---|---|
| 0 | 1 #ifndef CYGONCE_HAL_CACHE_H |
| 2 #define CYGONCE_HAL_CACHE_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 6 // hal_cache.h | |
| 7 // | |
| 8 // HAL cache control API | |
| 9 // | |
| 10 //============================================================================= | |
| 11 //####COPYRIGHTBEGIN#### | |
| 12 // | |
| 13 // ------------------------------------------- | |
| 14 // The contents of this file are subject to the Cygnus eCos Public License | |
| 15 // Version 1.0 (the "License"); you may not use this file except in | |
| 16 // compliance with the License. You may obtain a copy of the License at | |
| 17 // http://sourceware.cygnus.com/ecos | |
| 18 // | |
| 19 // Software distributed under the License is distributed on an "AS IS" | |
| 20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 21 // License for the specific language governing rights and limitations under | |
| 22 // the License. | |
| 23 // | |
| 24 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 25 // September 30, 1998. | |
| 26 // | |
| 27 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 2 | 28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
| 0 | 29 // ------------------------------------------- |
| 30 // | |
| 31 //####COPYRIGHTEND#### | |
| 32 //============================================================================= | |
| 33 //#####DESCRIPTIONBEGIN#### | |
| 34 // | |
| 35 // Author(s): nickg | |
| 36 // Contributors: nickg | |
| 37 // Date: 1998-02-17 | |
| 38 // Purpose: Cache control API | |
| 39 // Description: The macros defined here provide the HAL APIs for handling | |
| 40 // cache control operations. | |
| 41 // Usage: | |
| 42 // #include <cyg/hal/hal_cache.h> | |
| 43 // ... | |
| 44 // | |
| 45 // | |
| 46 //####DESCRIPTIONEND#### | |
| 47 // | |
| 48 //============================================================================= | |
| 49 | |
| 50 #include <pkgconf/hal.h> | |
| 51 #include <cyg/infra/cyg_type.h> | |
| 2 | 52 |
| 0 | 53 #include <cyg/hal/ppc_regs.h> |
| 54 | |
| 55 //============================================================================= | |
| 2 | 56 // Memory mapping |
| 57 typedef struct { | |
| 58 CYG_ADDRESS virtual_addr; | |
| 59 CYG_ADDRESS physical_addr; | |
| 60 cyg_int32 size; | |
| 61 cyg_uint8 flags; | |
| 62 } cyg_memdesc_t; | |
| 63 | |
|
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64 // each platform HAL must provide one of these to describe how memory |
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65 // should be mapped/cached, ideally weak aliased so that apps can override: |
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66 externC cyg_memdesc_t cyg_hal_mem_map[]; |
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67 |
| 2 | 68 #define CYGARC_MEMDESC_CI 1 // cache inhibit |
| 69 #define CYGARC_MEMDESC_GUARDED 2 // guarded | |
| 70 | |
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71 // these macros should ease that task, and ease any future extension of the |
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72 // structure (physical == virtual addresses): |
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73 #define CYGARC_MEMDESC_CACHE( _va_, _sz_ ) \ |
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74 { (_va_), (_va_), (_sz_), 0 } |
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75 |
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76 #define CYGARC_MEMDESC_NOCACHE( _va_, _sz_ ) \ |
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77 { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_CI } |
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78 |
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79 #define CYGARC_MEMDESC_CACHEGUARD( _va_, _sz_ ) \ |
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80 { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED } |
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81 |
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82 #define CYGARC_MEMDESC_NOCACHEGUARD( _va_, _sz_ ) \ |
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83 { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED|CYGARC_MEMDESC_CI } |
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84 |
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85 #define CYGARC_MEMDESC_TABLE_END {0, 0, 0, 0} |
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86 #define CYGARC_MEMDESC_TABLE cyg_memdesc_t cyg_hal_mem_map[] |
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87 #define CYGARC_MEMDESC_EMPTY_TABLE { CYGARC_MEMDESC_TABLE_END } |
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88 |
| 2 | 89 //============================================================================= |
| 0 | 90 // PowerPC simulator |
| 91 | |
| 92 #ifdef CYG_HAL_POWERPC_SIM | |
| 93 | |
| 94 //----------------------------------------------------------------------------- | |
| 95 // Cache dimensions | |
| 96 | |
| 97 // Data cache | |
| 98 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes | |
| 99 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line | |
| 100 #define HAL_DCACHE_WAYS 2 // Associativity of the cache | |
| 101 | |
| 102 // Instruction cache | |
| 103 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes | |
| 104 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line | |
| 105 #define HAL_ICACHE_WAYS 2 // Associativity of the cache | |
| 106 | |
| 107 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) | |
| 108 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) | |
| 109 | |
| 110 //----------------------------------------------------------------------------- | |
| 111 // Global control of data cache | |
| 112 | |
| 113 // Enable the data cache | |
| 114 #define HAL_DCACHE_ENABLE() | |
| 115 | |
| 116 // Disable the data cache | |
| 117 #define HAL_DCACHE_DISABLE() | |
| 118 | |
| 119 // Invalidate the entire cache | |
| 120 #define HAL_DCACHE_INVALIDATE_ALL() | |
| 121 | |
| 122 // Synchronize the contents of the cache with memory. | |
| 123 #define HAL_DCACHE_SYNC() | |
| 124 | |
| 2 | 125 // Query the state of the data cache |
| 126 #define HAL_DCACHE_IS_ENABLED(_state_) \ | |
| 127 CYG_MACRO_START \ | |
| 128 (_state_) = 0; \ | |
| 129 CYG_MACRO_END | |
| 130 | |
| 0 | 131 // Set the data cache refill burst size |
| 132 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 133 | |
| 134 // Set the data cache write mode | |
| 135 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 136 | |
| 137 //#define HAL_DCACHE_WRITETHRU_MODE 0 | |
| 138 //#define HAL_DCACHE_WRITEBACK_MODE 1 | |
| 139 | |
| 140 // Load the contents of the given address range into the data cache | |
| 141 // and then lock the cache so that it stays there. | |
| 142 //#define HAL_DCACHE_LOCK(_base_, _size_) | |
| 143 | |
| 144 // Undo a previous lock operation | |
| 145 //#define HAL_DCACHE_UNLOCK(_base_, _size_) | |
| 146 | |
| 2 | 147 // Unlock entire cache |
| 148 //#define HAL_DCACHE_UNLOCK_ALL() | |
| 149 | |
| 0 | 150 //----------------------------------------------------------------------------- |
| 151 // Data cache line control | |
| 152 | |
| 153 // Allocate cache lines for the given address range without reading its | |
| 154 // contents from memory. | |
| 155 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 156 | |
| 157 // Write dirty cache lines to memory and invalidate the cache entries | |
| 158 // for the given address range. | |
| 159 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) | |
| 160 | |
| 161 // Invalidate cache lines in the given range without writing to memory. | |
| 162 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) | |
| 163 | |
| 164 // Write dirty cache lines to memory for the given address range. | |
| 165 //#define HAL_DCACHE_STORE( _base_ , _size_ ) | |
| 166 | |
| 167 // Preread the given range into the cache with the intention of reading | |
| 168 // from it later. | |
| 169 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) | |
| 170 | |
| 171 // Preread the given range into the cache with the intention of writing | |
| 172 // to it later. | |
| 173 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) | |
| 174 | |
| 175 // Allocate and zero the cache lines associated with the given range. | |
| 176 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) | |
| 177 | |
| 178 //----------------------------------------------------------------------------- | |
| 179 // Global control of Instruction cache | |
| 180 | |
| 181 // Enable the instruction cache | |
| 182 #define HAL_ICACHE_ENABLE() | |
| 183 | |
| 184 // Disable the instruction cache | |
| 185 #define HAL_ICACHE_DISABLE() | |
| 186 | |
| 187 // Invalidate the entire cache | |
| 188 #define HAL_ICACHE_INVALIDATE_ALL() | |
| 189 | |
| 190 // Synchronize the contents of the cache with memory. | |
| 191 #define HAL_ICACHE_SYNC() | |
| 192 | |
| 2 | 193 // Query the state of the instruction cache |
| 194 #define HAL_ICACHE_IS_ENABLED(_state_) \ | |
| 195 CYG_MACRO_START \ | |
| 196 (_state_) = 0; \ | |
| 197 CYG_MACRO_END | |
| 198 | |
| 0 | 199 // Set the instruction cache refill burst size |
| 200 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 201 | |
| 202 // Load the contents of the given address range into the instruction cache | |
| 203 // and then lock the cache so that it stays there. | |
| 204 //#define HAL_ICACHE_LOCK(_base_, _size_) | |
| 205 | |
| 206 // Undo a previous lock operation | |
| 207 //#define HAL_ICACHE_UNLOCK(_base_, _size_) | |
| 208 | |
| 2 | 209 // Unlock entire cache |
| 210 //#define HAL_ICACHE_UNLOCK_ALL() | |
| 211 | |
| 0 | 212 //----------------------------------------------------------------------------- |
| 213 // Instruction cache line control | |
| 214 | |
| 215 // Invalidate cache lines in the given range without writing to memory. | |
| 216 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 217 | |
| 218 | |
| 219 //============================================================================= | |
| 2 | 220 // Motorola MPC8xx |
| 0 | 221 |
| 2 | 222 #elif defined(CYG_HAL_POWERPC_MPC8xx) |
| 0 | 223 |
| 224 //----------------------------------------------------------------------------- | |
| 225 // Cache dimensions | |
| 226 | |
| 2 | 227 #if defined(CYG_HAL_POWERPC_MPC860) |
| 0 | 228 // Data cache |
| 229 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes | |
| 230 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line | |
| 231 #define HAL_DCACHE_WAYS 2 // Associativity of the cache | |
| 232 | |
| 233 // Instruction cache | |
| 234 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes | |
| 235 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line | |
| 236 #define HAL_ICACHE_WAYS 2 // Associativity of the cache | |
| 2 | 237 #endif // defined(CYG_HAL_POWERPC_MPC860) |
| 238 | |
| 239 #if defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) | |
| 240 // Data cache | |
| 241 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes | |
| 242 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line | |
| 243 #define HAL_DCACHE_WAYS 2 // Associativity of the cache | |
| 244 | |
| 245 // Instruction cache | |
| 246 #define HAL_ICACHE_SIZE 2048 // Size of cache in bytes | |
| 247 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line | |
| 248 #define HAL_ICACHE_WAYS 2 // Associativity of the cache | |
| 249 #endif // defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) | |
| 0 | 250 |
| 251 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) | |
| 252 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) | |
| 253 | |
| 254 //----------------------------------------------------------------------------- | |
| 255 // Global control of data cache | |
| 256 | |
| 257 // Enable the data cache | |
| 258 #define HAL_DCACHE_ENABLE() \ | |
| 259 asm volatile ("sync;" \ | |
| 2 | 260 "mtspr %0, %1;" \ |
| 261 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CE)) | |
| 0 | 262 |
| 263 // Disable the data cache | |
| 264 #define HAL_DCACHE_DISABLE() \ | |
| 265 asm volatile ("sync;" \ | |
| 2 | 266 "mtspr %0, %1;" \ |
| 267 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CD)) | |
| 0 | 268 |
| 269 // Invalidate the entire cache | |
| 2 | 270 // Note: Any locked lines will not be invalidated. |
| 271 #define HAL_DCACHE_INVALIDATE_ALL() \ | |
| 272 asm volatile ("sync;" \ | |
| 273 "mtspr %0, %1;" \ | |
| 274 : : "I" (CYGARC_REG_DC_CST), \ | |
| 275 "r" (CYGARC_REG_DC_CMD_IA)) | |
| 0 | 276 |
| 277 // Synchronize the contents of the cache with memory. | |
| 2 | 278 #define HAL_DCACHE_SYNC() \ |
| 279 CYG_MACRO_START \ | |
| 280 cyg_int32 i; \ | |
| 281 for (i = 0; i < HAL_DCACHE_SETS; i++){ \ | |
| 282 asm volatile ("sync;" \ | |
| 283 "mtspr %0, %2;" \ | |
| 284 "mtspr %1, %4;" \ | |
| 285 "mtspr %0, %3;" \ | |
| 286 "mtspr %1, %4;" \ | |
| 287 : /* no output */ \ | |
| 288 : /* %0 */ "I" (CYGARC_REG_DC_ADR), \ | |
| 289 /* %1 */ "I" (CYGARC_REG_DC_CST), \ | |
| 290 /* %2 */ "r" (CYGARC_REG_DC_ADR_WAY0 \ | |
| 291 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \ | |
| 292 /* %3 */ "r" (CYGARC_REG_DC_ADR_WAY1 \ | |
| 293 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \ | |
| 294 /* %4 */ "r" (CYGARC_REG_DC_CMD_FL)); \ | |
| 295 } \ | |
| 0 | 296 CYG_MACRO_END |
| 2 | 297 |
| 298 // Query the state of the data cache | |
| 299 #define HAL_DCACHE_IS_ENABLED(_state_) \ | |
| 300 asm volatile ("mfspr %0, %1;" \ | |
| 301 "rlwinm %0,%0,1,31,31;" \ | |
| 302 : "=r" (_state_) : "I" (CYGARC_REG_DC_CST)) | |
| 0 | 303 |
| 304 // Set the data cache refill burst size | |
| 305 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 306 | |
| 307 // Set the data cache write mode | |
| 308 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 309 | |
| 310 //#define HAL_DCACHE_WRITETHRU_MODE 0 | |
| 311 //#define HAL_DCACHE_WRITEBACK_MODE 1 | |
| 312 | |
| 2 | 313 |
| 314 // Load the contents of the given address range into the data cache | |
| 315 // and then lock the cache so that it stays there. | |
| 316 | |
| 317 // Restrictions: This implementation only allows a single area to be | |
| 318 // locked at any one time. This area must be 2kB or less in size. | |
| 319 | |
| 320 // Implementation: Flush entire cache, then invalidate it. This | |
| 321 // ensures that the fetched data go into way0. | |
| 0 | 322 |
| 2 | 323 #define HAL_DCACHE_LOCK(_base_, _size_) \ |
| 324 CYG_MACRO_START \ | |
| 325 cyg_int32 __scratch; \ | |
| 326 cyg_uint32 __base = (cyg_uint32)(_base_); \ | |
| 327 cyg_int32 __l = ((__base / HAL_DCACHE_LINE_SIZE) % HAL_DCACHE_SETS); \ | |
| 328 cyg_int32 __count = ((_size_) / HAL_DCACHE_LINE_SIZE); \ | |
| 329 HAL_DCACHE_DISABLE(); \ | |
| 330 HAL_DCACHE_SYNC (); \ | |
| 331 HAL_DCACHE_INVALIDATE_ALL (); \ | |
| 332 HAL_DCACHE_ENABLE(); \ | |
| 333 do { \ | |
| 334 asm volatile ("lbz %0,0(%1);" \ | |
| 335 "sync;" \ | |
| 336 "mtspr %2, %4;" \ | |
| 337 "mtspr %3, %5;" \ | |
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338 : /* %0 */ "=&r" (__scratch) \ |
| 2 | 339 : /* %1 */ "b" (__base), \ |
| 340 /* %2 */ "I" (CYGARC_REG_DC_ADR), \ | |
| 341 /* %3 */ "I" (CYGARC_REG_DC_CST), \ | |
| 342 /* %4 */ "r" (CYGARC_REG_DC_ADR_WAY0 \ | |
| 343 |(__l<<CYGARC_REG_DC_ADR_SETID_SHIFT)), \ | |
| 344 /* %5 */ "r" (CYGARC_REG_DC_CMD_LL)); \ | |
| 345 __l++; \ | |
| 346 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 347 } while (__count--); \ | |
| 348 CYG_MACRO_END | |
| 349 | |
| 350 | |
| 0 | 351 // Undo a previous lock operation |
| 2 | 352 |
| 353 // Implementation: Unlocks entire cache. | |
| 354 | |
| 355 #define HAL_DCACHE_UNLOCK(_base_, _size_) \ | |
| 356 HAL_DCACHE_UNLOCK_ALL() | |
| 357 | |
| 358 | |
| 359 // Unlock entire cache | |
| 360 #define HAL_DCACHE_UNLOCK_ALL() \ | |
| 361 CYG_MACRO_START \ | |
| 362 asm volatile ("sync;" \ | |
| 363 "mtspr %0, %1;" \ | |
| 364 : : "I" (CYGARC_REG_DC_CST), \ | |
| 365 "r" (CYGARC_REG_DC_CMD_UA)); \ | |
| 366 CYG_MACRO_END | |
| 367 | |
| 368 | |
| 0 | 369 |
| 370 //----------------------------------------------------------------------------- | |
| 371 // Data cache line control | |
| 372 | |
| 373 // Allocate cache lines for the given address range without reading its | |
| 374 // contents from memory. | |
| 375 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 376 | |
| 377 // Write dirty cache lines to memory and invalidate the cache entries | |
| 378 // for the given address range. | |
| 2 | 379 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) \ |
| 380 CYG_MACRO_START \ | |
| 381 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 382 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 383 while (__size > 0) { \ | |
| 384 asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \ | |
| 385 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 386 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 387 } \ | |
| 388 CYG_MACRO_END | |
| 389 | |
| 0 | 390 // Invalidate cache lines in the given range without writing to memory. |
| 2 | 391 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \ |
| 392 CYG_MACRO_START \ | |
| 393 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 394 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 395 while (__size > 0) { \ | |
| 396 asm volatile ("dcbi 0,%0;sync;" : : "r" (__base)); \ | |
| 397 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 398 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 399 } \ | |
| 400 CYG_MACRO_END | |
| 0 | 401 |
| 402 // Write dirty cache lines to memory for the given address range. | |
| 2 | 403 #define HAL_DCACHE_STORE( _base_ , _size_ ) \ |
| 404 CYG_MACRO_START \ | |
| 405 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 406 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 407 while (__size > 0) { \ | |
| 408 asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \ | |
| 409 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 410 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 411 } \ | |
| 412 CYG_MACRO_END | |
| 0 | 413 |
| 414 // Preread the given range into the cache with the intention of reading | |
| 415 // from it later. | |
| 2 | 416 #define HAL_DCACHE_READ_HINT( _base_ , _size_ ) \ |
| 417 CYG_MACRO_START \ | |
| 418 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 419 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 420 while (__size > 0) { \ | |
| 421 asm volatile ("dcbt 0,%0;" : : "r" (__base)); \ | |
| 422 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 423 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 424 } \ | |
| 425 CYG_MACRO_END | |
| 0 | 426 |
| 427 // Preread the given range into the cache with the intention of writing | |
| 428 // to it later. | |
| 2 | 429 #define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) \ |
| 430 CYG_MACRO_START \ | |
| 431 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 432 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 433 while (__size > 0) { \ | |
| 434 asm volatile ("dcbtst 0,%0;" : : "r" (__base)); \ | |
| 435 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 436 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 437 } \ | |
| 438 CYG_MACRO_END | |
| 0 | 439 |
| 440 // Allocate and zero the cache lines associated with the given range. | |
| 2 | 441 #define HAL_DCACHE_ZERO( _base_ , _size_ ) \ |
| 442 CYG_MACRO_START \ | |
| 443 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 444 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 445 while (__size > 0) { \ | |
| 446 asm volatile ("dcbz 0,%0;" : : "r" (__base)); \ | |
| 447 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 448 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 449 } \ | |
| 450 CYG_MACRO_END | |
| 0 | 451 |
| 452 //----------------------------------------------------------------------------- | |
| 453 // Global control of Instruction cache | |
| 454 | |
| 455 // Enable the instruction cache | |
| 2 | 456 #define HAL_ICACHE_ENABLE() \ |
| 457 asm volatile ("isync;" \ | |
| 458 "mtspr %0, %1;" \ | |
| 459 "isync" \ | |
| 460 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE)) | |
| 0 | 461 |
| 462 // Disable the instruction cache | |
| 2 | 463 #define HAL_ICACHE_DISABLE() \ |
| 464 asm volatile ("isync;" \ | |
| 465 "mtspr %0, %1;" \ | |
| 466 "isync" \ | |
| 467 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CD)) | |
| 0 | 468 |
| 469 // Invalidate the entire cache | |
| 2 | 470 #define HAL_ICACHE_INVALIDATE_ALL() \ |
| 471 asm volatile ("isync;" \ | |
| 472 "mtspr %0, %1;" \ | |
| 473 "isync" \ | |
| 474 : : "I" (CYGARC_REG_IC_CST), \ | |
| 475 "r" (CYGARC_REG_IC_CMD_IA)) | |
| 0 | 476 |
| 477 // Synchronize the contents of the cache with memory. | |
| 478 #define HAL_ICACHE_SYNC() | |
| 479 | |
| 2 | 480 // Query the state of the instruction cache |
| 481 #define HAL_ICACHE_IS_ENABLED(_state_) \ | |
| 482 asm volatile ("mfspr %0, %1;" \ | |
| 483 "rlwinm %0,%0,1,31,31;" \ | |
| 484 : "=r" (_state_) : "I" (CYGARC_REG_IC_CST)) | |
| 0 | 485 |
| 486 // Set the instruction cache refill burst size | |
| 487 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 488 | |
| 2 | 489 |
| 0 | 490 // Load the contents of the given address range into the instruction cache |
| 491 // and then lock the cache so that it stays there. | |
| 2 | 492 |
| 493 // Restrictions: This implementation only allows a single area to be | |
| 494 // locked at any one time. This area must be 2kB or less in size. | |
| 495 | |
| 496 // Implementation: Flush entire cache, then invalidate it. This | |
| 497 // ensures that the fetched data go into way0. | |
| 498 | |
| 499 #define HAL_ICACHE_LOCK(_base_, _size_) \ | |
| 500 CYG_MACRO_START \ | |
| 501 unsigned long __base = \ | |
| 502 ((unsigned long) (_base_)) & ~(HAL_ICACHE_LINE_SIZE-1); \ | |
| 503 int __count = ((_size_) / HAL_ICACHE_LINE_SIZE); \ | |
| 504 do { \ | |
| 505 asm volatile ("mtspr %0, %2;" \ | |
| 506 "mtspr %1, %3;" \ | |
| 507 "isync;" \ | |
| 508 : /* no output */ \ | |
| 509 : /* %0 */ "I" (CYGARC_REG_IC_ADR), \ | |
| 510 /* %1 */ "I" (CYGARC_REG_IC_CST), \ | |
| 511 /* %2 */ "r" (__base), \ | |
| 512 /* %3 */ "r" (CYGARC_REG_IC_CMD_LL)); \ | |
| 513 __base += HAL_ICACHE_LINE_SIZE; \ | |
| 514 } while (__count--); \ | |
| 515 CYG_MACRO_END | |
| 0 | 516 |
| 517 // Undo a previous lock operation | |
| 2 | 518 |
| 519 // Implementation: Unlocks entire cache. | |
| 520 #define HAL_ICACHE_UNLOCK(_base_, _size_) \ | |
| 521 HAL_ICACHE_UNLOCK_ALL() | |
| 522 | |
| 523 // Unlock entire cache | |
| 524 #define HAL_ICACHE_UNLOCK_ALL() \ | |
| 525 CYG_MACRO_START \ | |
| 526 asm volatile ("sync;" \ | |
| 527 "mtspr %0, %1;" \ | |
| 528 : : "I" (CYGARC_REG_IC_CST), \ | |
| 529 "r" (CYGARC_REG_IC_CMD_UA)); \ | |
| 530 CYG_MACRO_END | |
| 0 | 531 |
| 532 //----------------------------------------------------------------------------- | |
| 533 // Instruction cache line control | |
| 534 | |
| 535 // Invalidate cache lines in the given range without writing to memory. | |
| 536 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 537 | |
| 538 #endif | |
| 539 | |
| 540 //----------------------------------------------------------------------------- | |
| 541 #endif // ifndef CYGONCE_HAL_CACHE_H | |
| 542 // End of hal_cache.h |