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annotate packages/devs/serial/arm/pid/current/src/pid_serial.h @ 115:6ed91473a1cd ecos-sw-2000-08-21

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Merge from eCos master repository on 2000-08-21-22:40:54-BST
author jlarmour
date Fri, 25 Aug 2000 17:32:38 +0000
parents c37d3a9e1b28
children
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1 #ifndef CYGONCE_ARM_PID_SERIAL_H
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2 #define CYGONCE_ARM_PID_SERIAL_H
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3
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4 // ====================================================================
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5 //
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6 // pid_serial.h
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7 //
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8 // Device I/O - Description of ARM PID7T serial hardware
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9 //
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10 // ====================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 // ====================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): gthomas
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38 // Contributors: gthomas
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39 // Date: 1999-02-04
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40 // Purpose: Internal interfaces for serial I/O drivers
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41 // Description:
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42 //
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43 //####DESCRIPTIONEND####
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44 //
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45 // ====================================================================
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46
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47 // Description of serial ports on ARM PID7T
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48
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49 struct serial_port {
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50 volatile unsigned char _byte[32];
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51 };
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52
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53 // Little-endian version
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54 #if (CYG_BYTEORDER == CYG_LSBFIRST)
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55
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56 #define REG(n) _byte[n*4]
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57
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58 #else // Big-endian version
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59
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60 #define REG(n) _byte[(n*4)^3]
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61
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62 #endif
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63
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64 // Receive control Registers
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65 #define REG_rhr REG(0) // Receive holding register
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66 #define REG_isr REG(2) // Interrupt status register
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67 #define REG_lsr REG(5) // Line status register
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68 #define REG_msr REG(6) // Modem status register
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69 #define REG_scr REG(7) // Scratch register
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71 // Transmit control Registers
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72 #define REG_thr REG(0) // Transmit holding register
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73 #define REG_ier REG(1) // Interrupt enable register
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74 #define REG_fcr REG(2) // FIFO control register
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75 #define REG_lcr REG(3) // Line control register
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76 #define REG_mcr REG(4) // Modem control register
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77 #define REG_ldl REG(0) // LSB of baud rate
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78 #define REG_mdl REG(1) // MSB of baud rate
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79
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80 // Interrupt Enable Register
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81 #define IER_RCV 0x01
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82 #define IER_XMT 0x02
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83 #define IER_LS 0x04
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84 #define IER_MS 0x08
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85
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86 // Line Control Register
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87 #define LCR_WL5 0x00 // Word length
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88 #define LCR_WL6 0x01
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89 #define LCR_WL7 0x02
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90 #define LCR_WL8 0x03
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91 #define LCR_SB1 0x00 // Number of stop bits
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92 #define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words
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93 #define LCR_SB2 0x04
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94 #define LCR_PN 0x00 // Parity mode - none
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95 #define LCR_PE 0x0C // Parity mode - even
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96 #define LCR_PO 0x08 // Parity mode - odd
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97 #define LCR_PM 0x28 // Forced "mark" parity
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98 #define LCR_PS 0x38 // Forced "space" parity
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99 #define LCR_DL 0x80 // Enable baud rate latch
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100
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101 // Line Status Register
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102 #define LSR_RSR 0x01
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103 #define LSR_OE 0x02
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104 #define LSR_PE 0x04
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105 #define LSR_FE 0x08
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106 #define LSR_BI 0x10
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107 #define LSR_THE 0x20
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108 #define LSR_TEMT 0x40
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109 #define LSR_FIE 0x80
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110
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111 // Modem Control Register
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112 #define MCR_DTR 0x01
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113 #define MCR_RTS 0x02
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114 #define MCR_INT 0x08 // Enable interrupts
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115
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116 // Interrupt status Register
115
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117 #define ISR_MS 0x00
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118 #define ISR_nIP 0x01
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119 #define ISR_Tx 0x02
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120 #define ISR_LS 0x03
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121 #define ISR_Rx 0x04
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122 #define ISR_RxTO 0x0C
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123
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124 // Modem Status Register
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125 #define MSR_DCTS 0x01
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126 #define MSR_DDSR 0x02
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127 #define MSR_TERI 0x04
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128 #define MSR_DDCD 0x08
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129 #define MSR_CTS 0x10
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130 #define MSR_DSR 0x20
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131 #define MSR_RI 0x40
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132 #define MSR_CD 0x80
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133
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134 static unsigned char select_word_length[] = {
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135 LCR_WL5, // 5 bits / word (char)
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136 LCR_WL6,
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137 LCR_WL7,
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138 LCR_WL8
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139 };
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140
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141 static unsigned char select_stop_bits[] = {
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142 0,
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143 LCR_SB1, // 1 stop bit
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144 LCR_SB1_5, // 1.5 stop bit
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145 LCR_SB2 // 2 stop bits
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146 };
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147
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148 static unsigned char select_parity[] = {
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149 LCR_PN, // No parity
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150 LCR_PE, // Even parity
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151 LCR_PO, // Odd parity
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152 LCR_PM, // Mark parity
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153 LCR_PS, // Space parity
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154 };
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155
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156 static unsigned short select_baud[] = {
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157 0, // Unused
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158 0, // 50
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159 0, // 75
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160 1047, // 110
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161 0, // 134.5
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162 768, // 150
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163 0, // 200
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164 384, // 300
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165 192, // 600
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166 96, // 1200
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167 24, // 1800
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168 48, // 2400
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169 0, // 3600
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170 24, // 4800
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171 16, // 7200
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172 12, // 9600
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173 8, // 14400
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174 6, // 19200
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175 3, // 38400
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176 2, // 57600
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177 1, // 115200
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178 0, // 230400
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179 };
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180
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181 #endif // CYGONCE_ARM_PID_SERIAL_H