Mercurial > ecos-v2_0-branch
annotate packages/hal/powerpc/arch/current/tests/intr0.c @ 40:a3cc6665b684 ecos-sw-1999-10-01
Merge from eCos master repository on 1999-10-01-07:47:04-BST
| author | jlarmour |
|---|---|
| date | Fri, 01 Oct 1999 13:25:47 +0000 |
| parents | 5af43b635655 |
| children | c38311975d4f |
| rev | line source |
|---|---|
| 2 | 1 //================================================================= |
| 2 // | |
| 3 // intr0.c | |
| 4 // | |
| 5 // Interrupt test 0 | |
| 6 // | |
| 7 //================================================================= | |
| 8 //####COPYRIGHTBEGIN#### | |
| 9 // | |
| 10 // ------------------------------------------- | |
| 11 // The contents of this file are subject to the Cygnus eCos Public License | |
| 12 // Version 1.0 (the "License"); you may not use this file except in | |
| 13 // compliance with the License. You may obtain a copy of the License at | |
| 14 // http://sourceware.cygnus.com/ecos | |
| 15 // | |
| 16 // Software distributed under the License is distributed on an "AS IS" | |
| 17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 18 // License for the specific language governing rights and limitations under | |
| 19 // the License. | |
| 20 // | |
| 21 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 22 // September 30, 1998. | |
| 23 // | |
| 24 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 25 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. | |
| 26 // ------------------------------------------- | |
| 27 // | |
| 28 //####COPYRIGHTEND#### | |
| 29 //================================================================= | |
| 30 //#####DESCRIPTIONBEGIN#### | |
| 31 // | |
| 32 // Author(s): jskov | |
| 33 // Contributors: jskov | |
| 34 // Date: 1998-12-01 | |
| 35 // Description: Simple test of MPC860 interrupt handling when the | |
| 36 // kernel has not been configured. Uses timer interrupts. | |
| 37 // Options: | |
| 38 //####DESCRIPTIONEND#### | |
| 39 | |
|
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40 //#define DEBUG_PRINTFS |
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41 #ifdef DEBUG_PRINTFS |
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42 extern diag_printf( char *format, ... ); |
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43 #endif |
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44 |
| 2 | 45 #include <pkgconf/hal.h> |
| 46 | |
| 47 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS | |
| 48 #include <cyg/hal/ppc_regs.h> | |
| 49 | |
| 50 #include <cyg/hal/hal_intr.h> | |
| 51 | |
| 52 #include <cyg/infra/testcase.h> | |
| 53 | |
| 54 #if defined(CYG_HAL_POWERPC_MPC860) | |
| 55 | |
| 56 #undef CHECK(b) | |
| 57 #define CHECK(b) CYG_TEST_CHECK(b,#b) | |
| 58 | |
| 59 // Can't rely on Cyg_Interrupt class being defined. | |
| 60 #define Cyg_InterruptHANDLED 1 | |
| 61 | |
| 62 // This is the period between interrupts, measured in decrementer ticks. | |
| 63 // Period must be longer than the time required for setting up all the | |
| 64 // interrupt handlers. | |
| 65 #define PIT_PERIOD 5000 | |
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66 |
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67 #ifdef CYG_HAL_POWERPC_MBX |
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68 #define TB_PERIOD (PIT_PERIOD*384) // PTA period is 15.36 uS |
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69 #else |
| 2 | 70 #define TB_PERIOD (PIT_PERIOD*32) // assuming 512/16 divisors |
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71 #endif |
| 2 | 72 |
| 73 #define ID_RTC_SEC 12345 | |
| 74 #define ID_RTC_ALR 23451 | |
| 75 #define ID_PIT 34512 | |
| 76 #define ID_TBA 45123 | |
| 77 #define ID_TBB 51234 | |
| 78 | |
| 79 volatile cyg_uint32 count = 0; | |
| 80 | |
| 81 // Time/PERIOD 0 1 2 3 4 5 6 7 8 9 10 | |
| 82 // Interrupt PIT TBA PIT PIT TBB PIT PIT | |
| 83 // pit_count 0 0 0 1 1 2 2 3 3 4 4 | |
| 84 // count 0 0 1 3 4 4 5 40 41 42 | |
| 85 | |
| 86 static cyg_uint32 count_verify_table[] = {1, 4, 5, 41, 42}; | |
| 87 static int pit_count = 0; | |
| 88 | |
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89 // These are useful for debugging: |
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90 static cyg_uint32 count_actual_table[] = { -1, -1, -1, -1, -1}; |
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91 static cyg_uint32 tbr_actual_table[] = { -1, -1, -1, -1, -1}; |
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92 |
| 2 | 93 // Periodic timer ISR. Should be executing 5 times. |
| 94 static cyg_uint32 isr_pit(CYG_ADDRWORD vector, CYG_ADDRWORD data) | |
| 95 { | |
| 96 cyg_uint32 verify_value; | |
| 97 | |
| 98 CYG_UNUSED_PARAM(CYG_ADDRWORD, data); | |
| 99 | |
| 100 CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_PIT == vector, "Wrong vector!"); | |
| 101 CYG_ASSERT (ID_PIT == data, "Wrong data!"); | |
| 102 | |
| 103 HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_PIT); | |
| 104 | |
| 105 count++; | |
| 106 | |
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107 count_actual_table[pit_count] = count; |
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108 { |
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109 cyg_uint32 tbl; |
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110 CYGARC_MFTB (TBL_R, tbl); |
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111 tbr_actual_table[pit_count] = tbl; |
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112 } |
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113 |
| 2 | 114 verify_value = count_verify_table[pit_count++]; |
| 115 | |
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116 #ifdef DEBUG_PRINTFS |
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117 diag_printf( "ISR_PIT executed %d of 5\n", pit_count ); |
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118 #endif |
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119 |
| 2 | 120 CYG_ASSERT (count == verify_value, "Count wrong!"); |
| 121 | |
| 122 // End of test when count is 42. Mask interrupts and print PASS text. | |
| 123 if (42 <= count || 5 == pit_count) { | |
| 124 HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_PIT); | |
| 125 HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A); | |
| 126 HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B); | |
| 127 | |
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128 #ifdef DEBUG_PRINTFS |
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129 diag_printf( "INFO: Actual counts: %d %d %d %d %d\n", |
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130 count_actual_table[0], |
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131 count_actual_table[1], |
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132 count_actual_table[2], |
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133 count_actual_table[3], |
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134 count_actual_table[4] ); |
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135 diag_printf( "INFO: Actuals tbrs: %d %d %d %d %d\n", |
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136 tbr_actual_table[0], |
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137 tbr_actual_table[1], |
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138 tbr_actual_table[2], |
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139 tbr_actual_table[3], |
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140 tbr_actual_table[4] ); |
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141 #endif |
| 2 | 142 if (42 == count && 5 == pit_count) |
| 143 CYG_TEST_PASS_FINISH("Intr 0 OK"); | |
| 144 else | |
| 145 CYG_TEST_FAIL_FINISH("Intr 0 Failed."); | |
| 146 } | |
| 147 | |
| 148 return Cyg_InterruptHANDLED; | |
| 149 } | |
| 150 | |
| 151 // TimeBase A ISR. Should be executing once. | |
| 152 static cyg_uint32 isr_tba(CYG_ADDRWORD vector, CYG_ADDRWORD data) | |
| 153 { | |
| 154 CYG_UNUSED_PARAM(CYG_ADDRWORD, data); | |
| 155 | |
| 156 CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_A == vector, "Wrong vector!"); | |
| 157 CYG_ASSERT (ID_TBA == data, "Wrong data!"); | |
| 158 | |
| 159 HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_TB_A); | |
| 160 | |
| 161 count = count * 3; | |
| 162 | |
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163 #ifdef DEBUG_PRINTFS |
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164 diag_printf( "ISR_TBA executed\n" ); |
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165 #endif |
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166 |
| 2 | 167 return Cyg_InterruptHANDLED; |
| 168 } | |
| 169 | |
| 170 // TimeBase B ISR. Should be executing once. | |
| 171 static cyg_uint32 isr_tbb(CYG_ADDRWORD vector, CYG_ADDRWORD data) | |
| 172 { | |
| 173 CYG_UNUSED_PARAM(CYG_ADDRWORD, data); | |
| 174 | |
| 175 CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_B == vector, "Wrong vector!"); | |
| 176 CYG_ASSERT (ID_TBB == data, "Wrong data!"); | |
| 177 | |
| 178 HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_TB_B); | |
| 179 | |
| 180 count = count * 8; | |
| 181 | |
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182 #ifdef DEBUG_PRINTFS |
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183 diag_printf( "ISR_TBB executed\n" ); |
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184 #endif |
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185 |
| 2 | 186 return Cyg_InterruptHANDLED; |
| 187 } | |
| 188 | |
| 189 void intr0_main( void ) | |
| 190 { | |
| 191 CYG_TEST_INIT(); | |
| 192 | |
| 193 #if 0 | |
| 194 // The A.3 revision of the CPU I'm using at the moment generates a | |
| 195 // machine check exception when writing to IMM_RTCSC. Smells a | |
| 196 // bit like the "SIU4. Spurious External Bus Transaction Following | |
| 197 // PLPRCR Write." CPU errata. Have to find out for sure. Run real | |
| 198 // time clock interrupts on level 0 | |
| 199 { | |
| 200 // Still to do. | |
| 201 } | |
| 202 #endif | |
| 203 | |
| 204 // Run periodic timer interrupt on level 1 | |
| 205 { | |
| 206 cyg_uint16 piscr; | |
| 207 | |
| 208 // Attach pit arbiter. | |
| 209 HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_LVL1, | |
| 210 &hal_arbitration_isr_pit, ID_PIT, 0); | |
| 211 HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_LVL1); | |
| 212 | |
| 213 // Attach pit isr. | |
| 214 HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_PIT, &isr_pit, | |
| 215 ID_PIT, 0); | |
| 216 HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_PIT, 1); | |
| 217 HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_PIT); | |
| 218 | |
| 219 | |
| 220 // Set period. | |
| 221 HAL_WRITE_UINT32 (CYGARC_REG_IMM_PITC, | |
| 222 (2*PIT_PERIOD) << CYGARC_REG_IMM_PITC_COUNT_SHIFT); | |
| 223 | |
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224 #ifdef DEBUG_PRINTFS |
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225 diag_printf( "PIT set to %d\n", 2*PIT_PERIOD ); |
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226 #endif |
| 2 | 227 // Enable. |
| 228 HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); | |
| 229 piscr |= CYGARC_REG_IMM_PISCR_PTE; | |
| 230 HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); | |
| 231 } | |
| 232 | |
| 233 // Run timebase interrupts on level 2 | |
| 234 { | |
| 235 cyg_uint16 tbscr; | |
| 236 cyg_uint32 tbl; | |
| 237 | |
| 238 // Attach tb arbiter. | |
| 239 HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_LVL2, | |
| 240 &hal_arbitration_isr_tb, ID_TBA, 0); | |
| 241 HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_LVL2); | |
| 242 | |
| 243 // Attach tb isrs. | |
| 244 HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_A, &isr_tba, | |
| 245 ID_TBA, 0); | |
| 246 HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_B, &isr_tbb, | |
| 247 ID_TBB, 0); | |
| 248 HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_TB_A, 2); | |
| 249 HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A); | |
| 250 HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B); | |
| 251 | |
| 252 // Set reference A & B registers. | |
| 253 CYGARC_MFTB (TBL_R, tbl); | |
| 254 tbl += TB_PERIOD*3; | |
| 255 HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF0, tbl); | |
| 256 tbl += TB_PERIOD*4; | |
| 257 HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF1, tbl); | |
| 258 | |
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259 #ifdef DEBUG_PRINTFS |
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260 diag_printf( "TB initial %d, !1 %d !2 %d\n", |
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261 tbl - 7*TB_PERIOD, |
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262 tbl - 4*TB_PERIOD, |
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263 tbl - 0*TB_PERIOD ); |
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264 #endif |
| 2 | 265 // Enable. |
| 266 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 267 tbscr |= (CYGARC_REG_IMM_TBSCR_REFA | CYGARC_REG_IMM_TBSCR_REFB | | |
| 268 CYGARC_REG_IMM_TBSCR_TBE); | |
| 269 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 270 tbscr |= CYGARC_REG_IMM_TBSCR_REFAE | CYGARC_REG_IMM_TBSCR_REFBE; | |
| 271 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 272 } | |
| 273 | |
| 274 HAL_ENABLE_INTERRUPTS(); | |
| 275 | |
| 276 for (;;); | |
| 277 } | |
| 278 | |
| 279 externC void | |
| 280 cyg_start( void ) | |
| 281 { | |
| 282 intr0_main(); | |
| 283 } | |
| 284 | |
| 285 #else // ifdef CYG_HAL_POWERPC_MPC860 | |
| 286 | |
| 287 externC void | |
| 288 cyg_start( void ) | |
| 289 { | |
| 290 CYG_TEST_INIT(); | |
| 291 CYG_TEST_PASS_FINISH("N/A: Not a MPC860"); | |
| 292 } | |
| 293 | |
| 294 #endif // ifdef CYG_HAL_POWERPC_MPC860 | |
| 295 | |
| 296 // EOF intr0.c |