Mercurial > ecos-v2_0-branch

annotate packages/hal/arm/arch/current/include/hal_intr.h @ 66:bf00f99aec69 ecos-sw-2000-02-02

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Merge from eCos master repository on 2000-02-02-19:16:44-GMT
author jlarmour
date Wed, 02 Feb 2000 19:57:02 +0000
parents c38311975d4f
children 435cced73e2f
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1 #ifndef CYGONCE_HAL_INTR_H
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2 #define CYGONCE_HAL_INTR_H
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3
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4 //==========================================================================
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5 //
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6 // hal_intr.h
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7 //
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8 // HAL Interrupt and clock support
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9 //
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10 //==========================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //==========================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): nickg, gthomas
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38 // Contributors: nickg, gthomas,
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39 // jlarmour
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40 // Date: 1999-02-20
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41 // Purpose: Define Interrupt support
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42 // Description: The macros defined here provide the HAL APIs for handling
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43 // interrupts and the clock.
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44 //
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45 // Usage: #include <cyg/hal/hal_intr.h>
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46 // ...
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47 //
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48 //
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49 //####DESCRIPTIONEND####
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50 //
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51 //==========================================================================
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52
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53 #include <pkgconf/hal.h>
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54
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55 #include <cyg/infra/cyg_type.h>
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56 #include <cyg/hal/hal_platform_ints.h>
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57
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58 //--------------------------------------------------------------------------
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59 // ARM exception vectors.
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60
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61 // These vectors correspond to VSRs. These values are the ones to use for
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62 // HAL_VSR_GET/SET
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63
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64 #define CYGNUM_HAL_VECTOR_RESET 0
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65 #define CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION 1
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66 #define CYGNUM_HAL_VECTOR_SOFTWARE_INTERRUPT 2
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67 #define CYGNUM_HAL_VECTOR_ABORT_PREFETCH 3
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68 #define CYGNUM_HAL_VECTOR_ABORT_DATA 4
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69 #define CYGNUM_HAL_VECTOR_reserved 5
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70 #define CYGNUM_HAL_VECTOR_IRQ 6
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71 #define CYGNUM_HAL_VECTOR_FIQ 7
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73 #define CYGNUM_HAL_VSR_MIN 0
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74 #define CYGNUM_HAL_VSR_MAX 7
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75 #define CYGNUM_HAL_VSR_COUNT 8
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77 // Exception vectors. These are the values used when passed out to an
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78 // external exception handler using cyg_hal_deliver_exception()
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79
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80 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \
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81 CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION
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82 #define CYGNUM_HAL_EXCEPTION_INTERRUPT \
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83 CYGNUM_HAL_VECTOR_SOFTWARE_INTERRUPT
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84 #define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_ABORT_PREFETCH
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85 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_ABORT_DATA
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86 #define CYGNUM_HAL_EXCEPTION_FIQ CYGNUM_HAL_VECTOR_FIQ
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87
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88 #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION
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89 #define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_FIQ
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90 #define CYGNUM_HAL_EXCEPTION_COUNT (CYGNUM_HAL_EXCEPTION_MAX - \
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91 CYGNUM_HAL_EXCEPTION_MIN + 1)
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92
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93 //--------------------------------------------------------------------------
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94 // Static data used by HAL
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95
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96 // ISR tables
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97 externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
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98 externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
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99 externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
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100
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101 // VSR table
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102 //externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
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103
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104 // actually, it is immediately after the hardware vectors
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105 #define hal_vsr_table ((volatile CYG_ADDRESS *)(0x20))
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106
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107 // and followed by a DRAM size variable used during bootup. This is in a
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108 // fixed location so that it can be shared between an eCos Stub ROM and a
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109 // RAM start eCos app. Ie. so that RAM startup code knows DRAM size.
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110 // If this variable is zero, RAM size is unknown/is the default.
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111 #define hal_dram_size (*(CYG_WORD *)(0x40))
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112
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113 //--------------------------------------------------------------------------
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114 // Default ISR
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115
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116 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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117
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118 //--------------------------------------------------------------------------
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119 // Interrupt state storage
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120
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121 typedef cyg_uint32 CYG_INTERRUPT_STATE;
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122
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123 //--------------------------------------------------------------------------
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124 // Interrupt control macros
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125
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126 // Note: This disables both FIQ and IRQ interrupts!
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127 #define HAL_DISABLE_INTERRUPTS(_old_) \
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128 asm volatile ( \
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129 "mrs %0,cpsr;" \
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130 "mrs r4,cpsr;" \
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131 "orr r4,r4,#0xC0;" \
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132 "msr cpsr,r4" \
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133 : "=r"(_old_) \
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134 : \
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135 : "r4" \
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136 );
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137
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138 #define HAL_ENABLE_INTERRUPTS() \
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139 asm volatile ( \
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140 "mrs r3,cpsr;" \
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141 "bic r3,r3,#0xC0;" \
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142 "msr cpsr,r3" \
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143 : \
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144 : \
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145 : "r3" \
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146 );
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147
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148 #define HAL_RESTORE_INTERRUPTS(_old_) \
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149 asm volatile ( \
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150 "mrs r3,cpsr;" \
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151 "and r4,%0,#0xC0;" \
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152 "bic r3,r3,#0xC0;" \
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153 "orr r3,r3,r4;" \
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154 "msr cpsr,r3" \
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155 : \
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156 : "r"(_old_) \
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157 : "r3", "r4" \
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158 );
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159
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160 #define HAL_QUERY_INTERRUPTS(_old_) \
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161 asm volatile ( \
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162 "mrs r4,cpsr;" \
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163 "and r4,r4,#0xC0;" \
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164 "eor %0,r4,#0xC0;" \
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165 : "=r"(_old_) \
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166 : \
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167 : "r4" \
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168 );
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169
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170 //--------------------------------------------------------------------------
8
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171 // Routine to execute DSRs using separate interrupt stack
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172
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173 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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174 externC void hal_interrupt_stack_call_pending_DSRs(void);
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175 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
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176 hal_interrupt_stack_call_pending_DSRs()
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177
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178 // these are offered solely for stack usage testing
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179 // if they are not defined, then there is no interrupt stack.
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180 #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
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181 #define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
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182 // use them to declare these extern however you want:
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183 // extern char HAL_INTERRUPT_STACK_BASE[];
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184 // extern char HAL_INTERRUPT_STACK_TOP[];
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185 // is recommended
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186 #endif
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187
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188 //--------------------------------------------------------------------------
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189 // Vector translation.
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190
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191 #ifndef HAL_TRANSLATE_VECTOR
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192 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
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193 (_index_) = (_vector_)
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194 #endif
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195
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196 //--------------------------------------------------------------------------
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197 // Interrupt and VSR attachment macros
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198
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199 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
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200 CYG_MACRO_START \
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201 cyg_uint32 _index_; \
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202 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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203 \
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204 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
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205 (_state_) = 0; \
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206 else \
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207 (_state_) = 1; \
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208 CYG_MACRO_END
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209
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210 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
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211 CYG_MACRO_START \
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212 if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)hal_default_isr ) \
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213 { \
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214 hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)_isr_; \
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215 hal_interrupt_data[_vector_] = (CYG_ADDRWORD) _data_; \
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216 hal_interrupt_objects[_vector_] = (CYG_ADDRESS)_object_; \
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217 } \
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218 CYG_MACRO_END
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219
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220 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
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221 CYG_MACRO_START \
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222 if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)_isr_ ) \
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223 { \
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224 hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)hal_default_isr; \
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225 hal_interrupt_data[_vector_] = 0; \
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226 hal_interrupt_objects[_vector_] = 0; \
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227 } \
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228 CYG_MACRO_END
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229
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230 #define HAL_VSR_GET( _vector_, _pvsr_ ) \
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231 *(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
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232
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233
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234 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
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235 CYG_MACRO_START \
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236 if( _poldvsr_ != NULL ) \
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237 *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
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238 hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
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239 CYG_MACRO_END
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240
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241 //--------------------------------------------------------------------------
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242 // Interrupt controller access
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243
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244 externC void hal_interrupt_mask(int);
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245 externC void hal_interrupt_unmask(int);
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246 externC void hal_interrupt_acknowledge(int);
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247 externC void hal_interrupt_configure(int, int, int);
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248 externC void hal_interrupt_set_level(int, int);
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249
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250 #define HAL_INTERRUPT_MASK( _vector_ ) \
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251 hal_interrupt_mask( _vector_ )
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252 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
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253 hal_interrupt_unmask( _vector_ )
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254 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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255 hal_interrupt_acknowledge( _vector_ )
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256 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
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257 hal_interrupt_configure( _vector_, _level_, _up_ )
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258 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
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259 hal_interrupt_set_level( _vector_, _level_ )
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260
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261 //--------------------------------------------------------------------------
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262 // Clock control
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263
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264 externC void hal_clock_initialize(cyg_uint32);
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265 externC void hal_clock_read(cyg_uint32 *);
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266 externC void hal_clock_reset(cyg_uint32, cyg_uint32);
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267
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268 #define HAL_CLOCK_INITIALIZE( _period_ ) hal_clock_initialize( _period_ )
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269 #define HAL_CLOCK_RESET( _vec_, _period_ ) hal_clock_reset( _vec_, _period_ )
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270 #define HAL_CLOCK_READ( _pvalue_ ) hal_clock_read( _pvalue_ )
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271 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
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272 #define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ( (cyg_uint32 *)_pvalue_ )
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273 #endif
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274
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275 //--------------------------------------------------------------------------
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276 #endif // ifndef CYGONCE_HAL_INTR_H
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277 // End of hal_intr.h