Mercurial > ecos-v2_0-branch
annotate packages/kernel/current/src/intr/intr.cxx @ 66:bf00f99aec69 ecos-sw-2000-02-02
Merge from eCos master repository on 2000-02-02-19:16:44-GMT
| author | jlarmour |
|---|---|
| date | Wed, 02 Feb 2000 19:57:02 +0000 |
| parents | c38311975d4f |
| children | 6512add4f5d6 |
| rev | line source |
|---|---|
| 0 | 1 //========================================================================== |
| 2 // | |
| 2 | 3 // intr/intr.cxx |
| 0 | 4 // |
| 2 | 5 // Interrupt class implementations |
| 0 | 6 // |
| 7 //========================================================================== | |
| 8 //####COPYRIGHTBEGIN#### | |
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9 // |
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10 // ------------------------------------------- |
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11 // The contents of this file are subject to the Red Hat eCos Public License |
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12 // Version 1.1 (the "License"); you may not use this file except in |
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13 // compliance with the License. You may obtain a copy of the License at |
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14 // http://www.redhat.com/ |
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15 // |
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16 // Software distributed under the License is distributed on an "AS IS" |
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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18 // License for the specific language governing rights and limitations under |
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19 // the License. |
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20 // |
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21 // The Original Code is eCos - Embedded Configurable Operating System, |
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22 // released September 30, 1998. |
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23 // |
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24 // The Initial Developer of the Original Code is Red Hat. |
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25 // Portions created by Red Hat are |
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
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27 // All Rights Reserved. |
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28 // ------------------------------------------- |
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29 // |
| 0 | 30 //####COPYRIGHTEND#### |
| 31 //========================================================================== | |
| 32 //#####DESCRIPTIONBEGIN#### | |
| 33 // | |
| 2 | 34 // Author(s): nickg |
| 35 // Contributors: nickg | |
| 36 // Date: 1999-02-17 | |
| 37 // Purpose: Interrupt class implementation | |
| 38 // Description: This file contains the definitions of the interrupt | |
| 39 // class. | |
| 0 | 40 // |
| 41 //####DESCRIPTIONEND#### | |
| 42 // | |
| 43 //========================================================================== | |
| 44 | |
| 45 #include <pkgconf/kernel.h> | |
| 46 | |
| 47 #include <cyg/kernel/ktypes.h> // base kernel types | |
| 48 #include <cyg/infra/cyg_trac.h> // tracing macros | |
| 49 #include <cyg/infra/cyg_ass.h> // assertion macros | |
| 50 #include <cyg/kernel/instrmnt.h> // instrumentation | |
| 51 | |
| 52 #include <cyg/kernel/intr.hxx> // our header | |
| 53 | |
| 54 #include <cyg/kernel/sched.hxx> // scheduler | |
| 55 | |
| 56 #include <cyg/kernel/sched.inl> | |
| 57 | |
| 58 // ------------------------------------------------------------------------- | |
| 2 | 59 // Statics |
| 60 | |
| 61 // Interrupt disable counter. Note that this is initialized to 1 since | |
| 62 // enable_interrupts() is called in Cyg_Scheduler::start(). | |
| 63 | |
| 64 cyg_int32 Cyg_Interrupt::disable_counter = 1; | |
| 65 | |
| 66 // ------------------------------------------------------------------------- | |
| 0 | 67 |
| 68 Cyg_Interrupt::Cyg_Interrupt( | |
| 69 cyg_vector vec, // Vector to attach to | |
| 70 cyg_priority pri, // Queue priority | |
| 71 CYG_ADDRWORD d, // Data pointer | |
| 72 cyg_ISR *ir, // Interrupt Service Routine | |
| 73 cyg_DSR *dr // Deferred Service Routine | |
| 74 ) | |
| 75 { | |
| 2 | 76 CYG_REPORT_FUNCTION(); |
| 77 CYG_REPORT_FUNCARG5("vector=%d, priority=%d, data=%08x, isr=%08x, " | |
| 78 "dsr=%08x", vec, pri, d, ir, dr); | |
| 79 | |
| 0 | 80 vector = vec; |
| 81 priority = pri; | |
| 82 isr = ir; | |
| 83 dsr = dr; | |
| 84 data = d; | |
| 85 | |
| 86 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 87 | |
| 88 dsr_count = 0; | |
| 89 next_dsr = NULL; | |
| 90 | |
| 91 #endif | |
| 92 | |
| 93 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 94 | |
| 95 next = NULL; | |
| 96 | |
| 97 #endif | |
| 2 | 98 |
| 99 CYG_REPORT_RETURN(); | |
| 0 | 100 |
| 101 }; | |
| 102 | |
| 103 // ------------------------------------------------------------------------- | |
| 104 | |
| 105 Cyg_Interrupt::~Cyg_Interrupt() | |
| 106 { | |
| 2 | 107 CYG_REPORT_FUNCTION(); |
| 0 | 108 detach(); |
| 2 | 109 CYG_REPORT_RETURN(); |
| 0 | 110 }; |
| 111 | |
| 112 // ------------------------------------------------------------------------- | |
| 113 // DSR handling statics: | |
| 114 | |
| 115 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 116 | |
| 2 | 117 Cyg_Interrupt * |
| 118 Cyg_Interrupt::dsr_table[CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE]; | |
| 0 | 119 |
| 120 cyg_ucount32 Cyg_Interrupt::dsr_table_head = 0; | |
| 121 | |
| 122 cyg_ucount32 Cyg_Interrupt::dsr_table_tail = 0; | |
| 123 | |
| 124 #endif | |
| 125 | |
| 126 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 127 | |
| 128 Cyg_Interrupt *Cyg_Interrupt::dsr_list = NULL; | |
| 129 | |
| 130 #endif | |
| 131 | |
| 132 // ------------------------------------------------------------------------- | |
| 133 // Call any pending DSRs | |
| 134 | |
| 2 | 135 void |
| 136 Cyg_Interrupt::call_pending_DSRs_inner(void) | |
| 0 | 137 { |
| 138 // CYG_REPORT_FUNCTION(); | |
| 139 | |
| 140 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 141 | |
| 142 while( dsr_table_head != dsr_table_tail ) | |
| 143 { | |
| 144 Cyg_Interrupt *intr = dsr_table[dsr_table_head]; | |
| 145 | |
| 146 dsr_table_head++; | |
| 147 if( dsr_table_head >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) | |
| 148 dsr_table_head = 0; | |
| 149 | |
| 150 CYG_INSTRUMENT_INTR(CALL_DSR, intr->vector, 0); | |
| 151 | |
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152 CYG_ASSERT( intr->dsr != NULL , "No DSR defined"); |
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153 |
| 0 | 154 intr->dsr( intr->vector, 1, (CYG_ADDRWORD)intr->data ); |
| 155 } | |
| 156 | |
| 157 #endif | |
| 158 | |
| 159 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 160 | |
| 161 while( dsr_list != NULL ) | |
| 162 { | |
| 163 Cyg_Interrupt *intr; | |
| 164 cyg_uint32 old_intr; | |
| 165 cyg_count32 count; | |
| 166 | |
| 167 HAL_DISABLE_INTERRUPTS(old_intr); | |
| 168 | |
| 169 intr = dsr_list; | |
| 170 dsr_list = intr->next_dsr; | |
| 171 count = intr->dsr_count; | |
| 172 intr->dsr_count = 0; | |
| 173 | |
| 174 HAL_RESTORE_INTERRUPTS(old_intr); | |
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175 |
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176 CYG_ASSERT( intr->dsr != NULL , "No DSR defined"); |
| 0 | 177 |
| 178 intr->dsr( intr->vector, count, (CYG_ADDRWORD)intr->data ); | |
| 179 | |
| 180 } | |
| 181 | |
| 182 #endif | |
| 183 | |
| 184 }; | |
| 185 | |
| 2 | 186 externC void |
| 187 cyg_interrupt_call_pending_DSRs(void) | |
| 188 { | |
| 189 Cyg_Interrupt::call_pending_DSRs_inner(); | |
| 190 } | |
| 191 | |
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192 // |
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193 // Use HAL supported function to run through the DSRs, but executing using |
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194 // the separate interrupt stack if available. This function calls back |
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195 // into this module via 'cyg_interrupt_call_pending_DSRs' above, to keep |
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196 // the whole process as general as possible. |
| 2 | 197 |
| 198 void | |
| 199 Cyg_Interrupt::call_pending_DSRs(void) | |
| 200 { | |
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201 HAL_INTERRUPT_STACK_CALL_PENDING_DSRS(); |
| 2 | 202 } |
| 203 | |
| 204 | |
| 0 | 205 // ------------------------------------------------------------------------- |
| 206 | |
| 2 | 207 void |
| 208 Cyg_Interrupt::post_dsr(void) | |
| 0 | 209 { |
| 210 // CYG_REPORT_FUNCTION(); | |
| 211 | |
| 212 CYG_INSTRUMENT_INTR(POST_DSR, vector, 0); | |
| 213 | |
| 214 cyg_uint32 old_intr; | |
| 215 | |
| 216 // We need to disable interrupts during this part to | |
| 217 // guard against nested interrupts. | |
| 218 | |
| 219 HAL_DISABLE_INTERRUPTS(old_intr); | |
| 220 | |
| 221 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 222 | |
| 223 dsr_table[dsr_table_tail++] = this; | |
| 224 if( dsr_table_tail >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) | |
| 225 dsr_table_tail = 0; | |
| 226 | |
| 227 #endif | |
| 228 | |
| 229 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 230 | |
| 231 // Only add the interrupt to the dsr list if this is | |
| 232 // the first DSR call. | |
| 233 // At present DSRs are pushed onto the list and will be | |
| 234 // called in reverse order. We do not define the order | |
| 235 // in which DSRs are called, so this is acceptable. | |
| 236 | |
| 237 if( dsr_count++ == 0 ) | |
| 238 { | |
| 239 next_dsr = dsr_list; | |
| 240 dsr_list = this; | |
| 241 } | |
| 242 | |
| 243 #endif | |
| 244 | |
| 245 HAL_RESTORE_INTERRUPTS(old_intr); | |
| 246 }; | |
| 247 | |
| 248 // ------------------------------------------------------------------------- | |
| 2 | 249 // A C callable interface to Cyg_Interrupt::post_dsr() that can be used from |
| 250 // the HAL. | |
| 0 | 251 |
| 2 | 252 externC void |
| 253 cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj ) | |
| 254 { | |
| 255 Cyg_Interrupt* intr = (Cyg_Interrupt*) intr_obj; | |
| 256 intr->post_dsr (); | |
| 257 } | |
| 258 | |
| 259 // ------------------------------------------------------------------------- | |
| 260 | |
| 261 // FIXME: should have better name - Jifl | |
| 262 externC void | |
| 263 interrupt_end( | |
| 0 | 264 cyg_uint32 isr_ret, |
| 265 Cyg_Interrupt *intr, | |
| 266 HAL_SavedRegisters *regs | |
| 267 ) | |
| 268 { | |
| 269 // CYG_REPORT_FUNCTION(); | |
| 270 | |
| 2 | 271 // Sometimes we have a NULL intr object pointer. |
| 272 cyg_vector vector = (intr!=NULL)?intr->vector:0; | |
| 273 | |
| 274 CYG_INSTRUMENT_INTR(END, vector, isr_ret); | |
| 275 | |
| 276 | |
| 0 | 277 #ifndef CYGIMP_KERNEL_INTERRUPTS_CHAIN |
| 278 | |
| 279 // Only do this if we are in a non-chained configuration. | |
| 280 // If we are chained, then chain_isr below will do the DSR | |
| 281 // posting. | |
| 282 | |
| 2 | 283 if( isr_ret & Cyg_Interrupt::CALL_DSR && intr != NULL ) intr->post_dsr(); |
| 0 | 284 |
| 285 #endif | |
| 286 | |
| 287 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT | |
| 288 | |
| 289 // If we have GDB support enabled, and there is the possibility | |
| 290 // that this thread will be context switched as a result of this | |
| 291 // interrupt, then save the pointer to the saved thread context in | |
| 292 // the thread object so that GDB can get a meaningful context to | |
| 293 // look at. | |
| 294 | |
| 295 Cyg_Scheduler::get_current_thread()->set_saved_context(regs); | |
| 296 | |
| 297 #endif | |
| 298 | |
| 299 // Now unlock the scheduler, which may also call DSRs | |
| 300 // and cause a thread switch to happen. | |
| 301 | |
| 302 Cyg_Scheduler::unlock(); | |
| 303 | |
| 304 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT | |
| 305 | |
| 306 Cyg_Scheduler::get_current_thread()->set_saved_context(0); | |
| 307 | |
| 308 #endif | |
| 309 | |
| 2 | 310 CYG_INSTRUMENT_INTR(RESTORE, vector, 0); |
| 0 | 311 } |
| 312 | |
| 313 // ------------------------------------------------------------------------- | |
| 314 // Interrupt chaining statics. | |
| 315 | |
| 316 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 317 | |
| 2 | 318 Cyg_Interrupt *Cyg_Interrupt::chain_list[CYGNUM_HAL_ISR_COUNT]; |
| 0 | 319 |
| 320 #endif | |
| 321 | |
| 322 // ------------------------------------------------------------------------- | |
| 323 // Chaining ISR inserted in HAL vector | |
| 324 | |
| 325 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 326 | |
| 2 | 327 cyg_uint32 |
| 328 Cyg_Interrupt::chain_isr(cyg_vector vector, CYG_ADDRWORD data) | |
| 0 | 329 { |
| 330 Cyg_Interrupt *p = *(Cyg_Interrupt **)data; | |
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331 register cyg_uint32 isr_ret = 0; |
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332 |
| 0 | 333 CYG_INSTRUMENT_INTR(CHAIN_ISR, vector, 0); |
| 334 | |
| 335 while( p != NULL ) | |
| 336 { | |
| 337 if( p->vector == vector ) | |
| 338 { | |
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339 isr_ret = p->isr(vector, p->data); |
| 0 | 340 |
| 2 | 341 if( isr_ret & Cyg_Interrupt::CALL_DSR ) p->post_dsr(); |
| 0 | 342 |
| 2 | 343 if( isr_ret & Cyg_Interrupt::HANDLED ) break; |
| 0 | 344 } |
| 345 | |
| 346 p = p->next; | |
| 347 } | |
| 348 | |
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349 #ifdef HAL_DEFAULT_ISR |
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350 if( (isr_ret & Cyg_Interrupt::HANDLED) == 0 ) |
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351 { |
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352 // If we finished the loop for some reason other than that an |
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353 // ISR has handled the interrupt, call any default ISR to either |
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354 // report the spurious interrupt, or do some other HAL level processing |
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355 // such as GDB interrupt detection etc. |
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356 |
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357 HAL_DEFAULT_ISR( vector, NULL ); |
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358 } |
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359 #endif |
| 0 | 360 return 0; |
| 361 } | |
| 362 | |
| 363 #endif | |
| 364 | |
| 365 // ------------------------------------------------------------------------- | |
| 366 // Attach an ISR to an interrupt vector. | |
| 367 | |
| 2 | 368 void |
| 369 Cyg_Interrupt::attach(void) | |
| 0 | 370 { |
| 371 CYG_REPORT_FUNCTION(); | |
| 372 | |
| 2 | 373 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 374 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 375 |
| 376 CYG_INSTRUMENT_INTR(ATTACH, vector, 0); | |
| 377 | |
| 378 HAL_INTERRUPT_SET_LEVEL( vector, priority ); | |
| 379 | |
| 380 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 381 | |
| 382 CYG_ASSERT( next == NULL , "Cyg_Interrupt already on a list"); | |
| 383 | |
| 384 cyg_uint32 index; | |
| 385 | |
| 386 HAL_TRANSLATE_VECTOR( vector, index ); | |
| 387 | |
| 388 if( chain_list[index] == NULL ) | |
| 389 { | |
| 2 | 390 int in_use; |
| 0 | 391 // First Interrupt on this chain, just assign it and register |
| 392 // the chain_isr with the HAL. | |
| 393 | |
| 394 chain_list[index] = this; | |
| 395 | |
| 2 | 396 HAL_INTERRUPT_IN_USE( vector, in_use ); |
| 397 CYG_ASSERT( 0 == in_use, "Interrupt vector not free."); | |
| 0 | 398 HAL_INTERRUPT_ATTACH( vector, chain_isr, &chain_list[index], NULL ); |
| 399 } | |
| 400 else | |
| 401 { | |
| 402 // There are already interrupts chained, add this one into the | |
| 403 // chain in priority order. | |
| 404 | |
| 405 Cyg_Interrupt **p = &chain_list[index]; | |
| 406 | |
| 407 while( *p != NULL ) | |
| 408 { | |
| 409 Cyg_Interrupt *n = *p; | |
| 410 | |
| 411 if( n->priority < priority ) break; | |
| 412 | |
| 413 p = &n->next; | |
| 414 } | |
| 415 next = *p; | |
| 416 *p = this; | |
| 417 } | |
| 418 | |
| 419 #else | |
| 420 | |
| 2 | 421 { |
| 422 int in_use; | |
| 423 | |
| 424 | |
| 425 HAL_INTERRUPT_IN_USE( vector, in_use ); | |
| 426 CYG_ASSERT( 0 == in_use, "Interrupt vector not free."); | |
| 427 | |
| 428 HAL_INTERRUPT_ATTACH( vector, isr, data, this ); | |
| 429 } | |
| 0 | 430 |
| 431 #endif | |
| 2 | 432 CYG_REPORT_RETURN(); |
| 0 | 433 } |
| 434 | |
| 435 // ------------------------------------------------------------------------- | |
| 436 // Detach the ISR from the vector | |
| 437 | |
| 2 | 438 void |
| 439 Cyg_Interrupt::detach(void) | |
| 0 | 440 { |
| 441 CYG_REPORT_FUNCTION(); | |
| 442 | |
| 2 | 443 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 444 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 445 |
| 446 CYG_INSTRUMENT_INTR(DETACH, vector, 0); | |
| 447 | |
| 448 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 449 | |
| 450 // Remove the interrupt object from the vector chain. | |
| 451 | |
| 2 | 452 cyg_uint32 index; |
| 453 | |
| 454 HAL_TRANSLATE_VECTOR( vector, index ); | |
| 455 | |
| 456 Cyg_Interrupt **p = &chain_list[index]; | |
| 0 | 457 |
| 458 while( *p != NULL ) | |
| 459 { | |
| 460 Cyg_Interrupt *n = *p; | |
| 461 | |
| 462 if( n == this ) | |
| 463 { | |
| 464 *p = next; | |
| 465 break; | |
| 466 } | |
| 467 | |
| 468 p = &n->next; | |
| 469 } | |
| 470 | |
| 471 // If this was the last one, detach the vector. | |
| 472 | |
| 2 | 473 if( chain_list[index] == NULL ) |
| 0 | 474 HAL_INTERRUPT_DETACH( vector, chain_isr ); |
| 475 | |
| 476 #else | |
| 477 | |
| 478 HAL_INTERRUPT_DETACH( vector, isr ); | |
| 479 | |
| 480 #endif | |
| 2 | 481 |
| 482 CYG_REPORT_RETURN(); | |
| 0 | 483 |
| 484 } | |
| 485 | |
| 486 // ------------------------------------------------------------------------- | |
| 487 // Get the current service routine | |
| 488 | |
| 2 | 489 void |
| 490 Cyg_Interrupt::get_vsr(cyg_vector vector, cyg_VSR **vsr) | |
| 0 | 491 { |
| 492 CYG_REPORT_FUNCTION(); | |
| 2 | 493 CYG_REPORT_FUNCARG2("vector = %d, mem to put VSR in is at %08x", vector, |
| 494 vsr); | |
| 0 | 495 |
| 2 | 496 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector"); |
| 497 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector"); | |
| 0 | 498 |
| 499 HAL_VSR_GET( vector, vsr ); | |
| 2 | 500 |
| 501 CYG_REPORT_RETURN(); | |
| 0 | 502 } |
| 503 | |
| 504 // ------------------------------------------------------------------------- | |
| 505 // Install a vector service routine | |
| 506 | |
| 2 | 507 void |
| 508 Cyg_Interrupt::set_vsr(cyg_vector vector, cyg_VSR *vsr, cyg_VSR **old) | |
| 0 | 509 { |
| 510 CYG_REPORT_FUNCTION(); | |
| 511 | |
| 2 | 512 CYG_REPORT_FUNCARG3( "vector = %d, new vsr is at %08x, mem to put " |
| 513 "old VSR in is at %08x", vector, vsr, old); | |
| 514 | |
| 0 | 515 CYG_INSTRUMENT_INTR(SET_VSR, vector, vsr); |
| 516 | |
| 2 | 517 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector"); |
| 518 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector"); | |
| 0 | 519 |
| 520 CYG_INTERRUPT_STATE old_ints; | |
| 521 | |
| 522 HAL_DISABLE_INTERRUPTS(old_ints); | |
| 523 | |
| 524 HAL_VSR_SET( vector, vsr, old ); | |
| 525 | |
| 526 HAL_RESTORE_INTERRUPTS(old_ints); | |
| 2 | 527 |
| 528 CYG_REPORT_RETURN(); | |
| 0 | 529 } |
| 530 | |
| 531 // ------------------------------------------------------------------------- | |
| 532 // Disable interrupts at the CPU | |
| 533 | |
| 534 | |
| 2 | 535 void |
| 536 Cyg_Interrupt::disable_interrupts(void) | |
| 0 | 537 { |
| 538 CYG_REPORT_FUNCTION(); | |
| 539 | |
| 2 | 540 CYG_INSTRUMENT_INTR(DISABLE, disable_counter+1, 0); |
| 0 | 541 |
| 542 CYG_INTERRUPT_STATE dummy; | |
| 543 | |
| 544 HAL_DISABLE_INTERRUPTS(dummy); | |
| 545 | |
| 2 | 546 CYG_ASSERT( disable_counter >= 0 , "Disable counter negative"); |
| 547 | |
| 548 disable_counter++; | |
| 549 | |
| 550 CYG_REPORT_RETURN(); | |
| 0 | 551 } |
| 552 | |
| 553 | |
| 554 // ------------------------------------------------------------------------- | |
| 555 // Re-enable CPU interrupts | |
| 556 | |
| 2 | 557 void |
| 558 Cyg_Interrupt::enable_interrupts(void) | |
| 0 | 559 { |
| 560 CYG_REPORT_FUNCTION(); | |
| 561 | |
| 2 | 562 CYG_INSTRUMENT_INTR(ENABLE, disable_counter, 0); |
| 563 | |
| 564 CYG_ASSERT( disable_counter > 0 , "Disable counter not greater than zero"); | |
| 565 | |
| 566 disable_counter--; | |
| 0 | 567 |
| 2 | 568 if ( disable_counter == 0 ) |
| 569 { | |
| 570 HAL_ENABLE_INTERRUPTS(); | |
| 571 } | |
| 572 | |
| 573 CYG_REPORT_RETURN(); | |
| 0 | 574 } |
| 575 | |
| 576 // ------------------------------------------------------------------------- | |
| 577 // Mask a specific interrupt in a PIC | |
| 578 | |
| 2 | 579 void |
| 580 Cyg_Interrupt::mask_interrupt(cyg_vector vector) | |
| 0 | 581 { |
| 582 CYG_REPORT_FUNCTION(); | |
| 2 | 583 CYG_REPORT_FUNCARG1("vector=%d", vector); |
| 0 | 584 |
| 2 | 585 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 586 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 587 |
| 588 CYG_INSTRUMENT_INTR(MASK, vector, 0); | |
| 589 | |
| 2 | 590 HAL_INTERRUPT_MASK( vector ); |
| 591 | |
| 592 CYG_REPORT_RETURN(); | |
| 0 | 593 } |
| 594 | |
| 595 // ------------------------------------------------------------------------- | |
| 596 // Clear PIC mask | |
| 597 | |
| 2 | 598 void |
| 599 Cyg_Interrupt::unmask_interrupt(cyg_vector vector) | |
| 0 | 600 { |
| 601 CYG_REPORT_FUNCTION(); | |
| 602 | |
| 2 | 603 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 604 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 605 |
| 606 CYG_INSTRUMENT_INTR(UNMASK, vector, 0); | |
| 607 | |
| 608 HAL_INTERRUPT_UNMASK( vector ); | |
| 2 | 609 |
| 610 CYG_REPORT_RETURN(); | |
| 0 | 611 } |
| 612 | |
| 613 | |
| 614 // ------------------------------------------------------------------------- | |
| 615 // Acknowledge interrupt at PIC | |
| 616 | |
| 2 | 617 void |
| 618 Cyg_Interrupt::acknowledge_interrupt(cyg_vector vector) | |
| 0 | 619 { |
| 620 // CYG_REPORT_FUNCTION(); | |
| 621 | |
| 2 | 622 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 623 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 624 |
| 625 CYG_INSTRUMENT_INTR(ACK, vector, 0); | |
| 626 | |
| 627 HAL_INTERRUPT_ACKNOWLEDGE( vector ); | |
| 628 } | |
| 629 | |
| 630 // ------------------------------------------------------------------------- | |
| 631 // Change interrupt detection at PIC | |
| 632 | |
| 2 | 633 void |
| 634 Cyg_Interrupt::configure_interrupt( | |
| 0 | 635 cyg_vector vector, // vector to control |
| 636 cyg_bool level, // level or edge triggered | |
| 637 cyg_bool up // hi/lo level, rising/falling edge | |
| 638 ) | |
| 639 { | |
| 640 CYG_REPORT_FUNCTION(); | |
| 2 | 641 CYG_REPORT_FUNCARG3("vector = %d, level = %d, up = %d", vector, level, |
| 642 up); | |
| 0 | 643 |
| 2 | 644 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 645 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 646 |
| 647 CYG_INSTRUMENT_INTR(CONFIGURE, vector, (level<<1)|up); | |
| 648 | |
| 649 HAL_INTERRUPT_CONFIGURE( vector, level, up ); | |
| 2 | 650 |
| 651 CYG_REPORT_RETURN(); | |
| 0 | 652 } |
| 653 | |
| 654 // ------------------------------------------------------------------------- | |
| 655 // EOF intr/intr.cxx |