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annotate packages/devs/eth/powerpc/quicc/current/src/quicc_eth.h @ 772:f5585bc94013

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Fixed copyright assignment.
author nickg
date Fri, 21 Mar 2003 18:24:44 +0000
parents ee025918fc58
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 //==========================================================================
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2 //
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3 // quicc_eth.h
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4 //
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5 // PowerPC QUICC (MPC8xx) ethernet
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6 //
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7 //==========================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 // Copyright (C) 2002 Gary Thomas
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13 // Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
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14 //
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15 // eCos is free software; you can redistribute it and/or modify it under
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16 // the terms of the GNU General Public License as published by the Free
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17 // Software Foundation; either version 2 or (at your option) any later version.
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18 //
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19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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22 // for more details.
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23 //
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24 // You should have received a copy of the GNU General Public License along
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25 // with eCos; if not, write to the Free Software Foundation, Inc.,
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26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 //
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28 // As a special exception, if other files instantiate templates or use macros
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29 // or inline functions from this file, or you compile this file and link it
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30 // with other works to produce a work based on this file, this file does not
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31 // by itself cause the resulting work to be covered by the GNU General Public
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32 // License. However the source code for this file must still be made available
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33 // in accordance with section (3) of the GNU General Public License.
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34 //
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35 // This exception does not invalidate any other reasons why a work based on
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36 // this file might be covered by the GNU General Public License.
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37 //
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38 // Alternative licenses for eCos may be arranged by contacting the copyright
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39 // holders.
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40 // -------------------------------------------
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41 //####ECOSGPLCOPYRIGHTEND####
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42 //####BSDCOPYRIGHTBEGIN####
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43 //
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44 // -------------------------------------------
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45 //
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46 // Portions of this software may have been derived from OpenBSD or other sources,
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47 // and are covered by the appropriate copyright disclaimers included herein.
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48 //
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49 // -------------------------------------------
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50 //
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51 //####BSDCOPYRIGHTEND####
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52 //==========================================================================
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53 //#####DESCRIPTIONBEGIN####
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54 //
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55 // Author(s): gthomas
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56 // Contributors: gthomas, nickg
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57 // Date: 2000-01-10
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58 // Purpose:
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59 // Description:
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60 //
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61 //
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62 //####DESCRIPTIONEND####
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63 //
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64 //==========================================================================
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65
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66 // PowerPC QUICC (MPC8xx) Ethernet
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67
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68 #include <cyg/hal/quicc/ppc8xx.h> // QUICC structure definitions
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70 struct quicc_eth_info {
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71 volatile struct ethernet_pram *pram; // Parameter RAM pointer
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72 volatile struct scc_regs *ctl; // SCC control registers
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73 volatile struct cp_bufdesc *txbd, *rxbd; // Next Tx,Rx descriptor to use
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74 struct cp_bufdesc *tbase, *rbase; // First Tx,Rx descriptor
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75 struct cp_bufdesc *tnext, *rnext; // Next descriptor to check for interrupt
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76 int txsize, rxsize; // Length of individual buffers
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77 int txactive; // Count of active Tx buffers
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78 unsigned long txkey[CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM];
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79
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80 // Keep some statistics
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81 cyg_uint32 interrupts;
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82
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83 cyg_uint32 rx_count;
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84 cyg_uint32 rx_deliver;
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85 cyg_uint32 rx_resource;
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86 cyg_uint32 rx_restart;
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87 cyg_uint32 rx_good;
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88 cyg_uint32 rx_crc_errors;
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89 cyg_uint32 rx_align_errors;
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90 cyg_uint32 rx_resource_errors;
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91 cyg_uint32 rx_overrun_errors;
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92 cyg_uint32 rx_collisions;
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93 cyg_uint32 rx_short_frames;
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94 cyg_uint32 rx_long_frames;
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95 cyg_uint32 rx_miss;
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96
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97 cyg_uint32 tx_count;
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98 cyg_uint32 tx_complete;
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99 cyg_uint32 tx_restart;
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100 cyg_uint32 tx_good;
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101 cyg_uint32 tx_dropped;
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102 cyg_uint32 tx_underrun;
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103 cyg_uint32 tx_late_collisions;
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104 cyg_uint32 tx_carrier_loss;
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105 cyg_uint32 tx_retransmit_error;
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106 cyg_uint32 tx_heartbeat_loss;
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107 cyg_uint32 tx_deferred;
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108 };
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109
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110 // SCC registers - ethernet mode
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111
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112 // General SCC mode register
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113 #define QUICC_SCC_GSMH_IRP 0x00040000 // Infared polarity
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114 #define QUICC_SCC_GSMH_GDE 0x00010000 // Glitch detect enable
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115 #define QUICC_SCC_GSMH_TCRC 0x00008000 // Transparent CRC
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116 #define QUICC_SCC_GSMH_REVD 0x00004000 // Reverse data (transparent)
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117 #define QUICC_SCC_GSMH_TRX 0x00002000 // Transparent Rx
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118 #define QUICC_SCC_GSMH_TTX 0x00001000 // Transparent Tx
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119
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120 #define QUICC_SCC_GSML_TCI 0x10000000 // Transmit clock invert
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121 #define QUICC_SCC_GSML_TPL 0x00E00000 // Tx preamble bits
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122 #define QUICC_SCC_GSML_TPL_8 0x00200000 // 8 bits
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123 #define QUICC_SCC_GSML_TPL_16 0x00400000 // 16 bits
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124 #define QUICC_SCC_GSML_TPL_32 0x00600000 // 32 bits
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125 #define QUICC_SCC_GSML_TPL_48 0x00800000 // 48 bits (used for ethernet)
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126 #define QUICC_SCC_GSML_TPL_64 0x00A00000 // 64 bits
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127 #define QUICC_SCC_GSML_TPL_128 0x00C00000 // 128 bits
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128 #define QUICC_SCC_GSML_TPP 0x00180000 // Tx preamble pattern
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129 #define QUICC_SCC_GSML_TPP_00 0x00000000 // all zeroes
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130 #define QUICC_SCC_GSML_TPP_01 0x00080000 // 10 repeats (ethernet)
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131 #define QUICC_SCC_GSML_TPP_10 0x00100000 // 01 repeats
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132 #define QUICC_SCC_GSML_TPP_11 0x00180000 // all ones (localtalk)
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133 #define QUICC_SCC_GSML_ENR 0x00000020 // Enable receiver
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134 #define QUICC_SCC_GSML_ENT 0x00000010 // Enable transmitter
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135 #define QUICC_SCC_GSML_MODE 0x0000000F // Operating mode
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136 #define QUICC_SCC_GSML_MODE_HDLC 0x00000000
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137 #define QUICC_SCC_GSML_MODE_ATALK 0x00000002
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138 #define QUICC_SCC_GSML_MODE_ENET 0x0000000C
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139
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140 // Function code
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141 #define QUICC_SCC_FCR_BE 0x0010 // Big Endian operation
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142
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143 // Event register
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144 #define QUICC_SCCE_GRC 0x0080 // Gracefull stop complete
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145 #define QUICC_SCCE_TXE 0x0010 // Transmit error
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146 #define QUICC_SCCE_RXF 0x0008 // Received full frame
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147 #define QUICC_SCCE_BSY 0x0004 // No free receive buffers
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148 #define QUICC_SCCE_TX 0x0002 // Buffer transmit complete
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149 #define QUICC_SCCE_RX 0x0001 // Buffer received
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150 #define QUICC_SCCE_INTS (QUICC_SCCE_TXE | QUICC_SCCE_RXF | QUICC_SCCE_TX)
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151
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152 // Protocol specific mode register
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153 #define QUICC_PMSR_HEARTBEAT 0x8000 // Enable heartbeat
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154 #define QUICC_PMSR_FORCE_COLLISION 0x4000 // Force a collision
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155 #define QUICC_PMSR_RCV_SHORT_FRAMES 0x2000 // Accept short frames
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156 #define QUICC_PMSR_INDIV_ADDR_MODE 0x1000 // Check individual address (hash)
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157 #define QUICC_PMSR_ENET_CRC 0x0800 // Enable ethernet CRC mode
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158 #define QUICC_PMSR_PROMISCUOUS 0x0200 // Enable promiscuous mode
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159 #define QUICC_PMSR_BROADCAST 0x0100 // Accept broadcast packets
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160 #define QUICC_PMSR_SPECIAL_BACKOFF 0x0080 // Enable special backoff timer
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161 #define QUICC_PMSR_LOOPBACK 0x0040 // Enable loopback mode
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162 #define QUICC_PMSR_SAMPLE_INPUTS 0x0020 // Discretely look at input pins
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163 #define QUICC_PMSR_LATE_COLLISION 0x0010 // Enable late collision window
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164 #define QUICC_PMSR_SEARCH_AFTER_22 0x000A // Start frame search after 22 bits
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165 #define QUICC_PMSR_FULL_DUPLEX 0x0001 // Full duplex mode
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166
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167 // Receive buffer status
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168 #define QUICC_BD_RX_LAST 0x0800 // Last buffer in chain
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169 #define QUICC_BD_RX_FIRST 0x0400 // First buffer in chain
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170 #define QUICC_BD_RX_MISS 0x0100 // Missed data
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171 #define QUICC_BD_RX_LG 0x0020 // Rx frame too long
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172 #define QUICC_BD_RX_NO 0x0010 // Rx frame not properly aligned
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173 #define QUICC_BD_RX_SH 0x0008 // Rx frame too short
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174 #define QUICC_BD_RX_CR 0x0004 // Bad CRC
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175 #define QUICC_BD_RX_OV 0x0002 // Rx overrun
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176 #define QUICC_BD_RX_CL 0x0001 // Collision during frame
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177
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178 #define QUICC_BD_RX_ERRORS ( QUICC_BD_RX_CL | QUICC_BD_RX_OV | \
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179 QUICC_BD_RX_CR | QUICC_BD_RX_SH | \
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180 QUICC_BD_RX_NO | QUICC_BD_RX_LG | \
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181 QUICC_BD_RX_MISS )
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182
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183 // Transmit buffer status
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184 #define QUICC_BD_TX_PAD 0x4000 // Pad short packets
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185 #define QUICC_BD_TX_LAST 0x0800 // Last buffer in chain
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186 #define QUICC_BD_TX_TC 0x0400 // Transmit CRC after buffer
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187 #define QUICC_BD_TX_DEF 0x0200 // Transmission was deferred
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188 #define QUICC_BD_TX_HB 0x0100 // Heartbeat detected
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189 #define QUICC_BD_TX_LC 0x0080 // Late collision
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190 #define QUICC_BD_TX_RL 0x0040 // Retransmit limit exceeded
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191 #define QUICC_BD_TX_RC 0x003C // Retry count
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192 #define QUICC_BD_TX_UN 0x0002 // Tx underrun
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193 #define QUICC_BD_TX_CSL 0x0001 // Carrier lost
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194
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195 #define QUICC_BD_TX_ERRORS (QUICC_BD_TX_CSL | QUICC_BD_TX_UN | \
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196 QUICC_BD_TX_RL | QUICC_BD_TX_LC | \
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197 QUICC_BD_TX_HB | QUICC_BD_TX_DEF )
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198
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199 #include CYGDAT_DEVS_QUICC_ETH_INL // Platform specifics
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200
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201 #define IEEE_8023_MAX_FRAME 1518 // Largest possible ethernet frame
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202 #define IEEE_8023_MIN_FRAME 64 // Smallest possible ethernet frame
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203