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annotate packages/hal/powerpc/quicc/current/src/quicc_smc1.c @ 68:f74b2666b30d ecos-sw-2000-02-04

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Merge from eCos master repository on 2000-02-04-07:47:04-GMT
author jlarmour
date Fri, 04 Feb 2000 15:01:01 +0000
parents bf00f99aec69
children c5536bad4c24
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1 //==========================================================================
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2 //
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3 // quicc_smc1.c
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4 //
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5 // PowerPC QUICC basic Serial IO using port SMC1
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): Red Hat
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35 // Contributors: hmt
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36 // Date: 1999-06-08
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37 // Purpose: Provide basic Serial IO for MBX board
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38 // Description: Serial IO for MBX boards which connect their debug channel
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39 // to SMC1; or any QUICC user who wants to use SMC1.
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40 // Usage:
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41 //
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42 //
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43 //####DESCRIPTIONEND####
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44 //
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45 //==========================================================================
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46
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47 #include <pkgconf/hal.h>
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48 #include <cyg/infra/cyg_type.h>
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49 #include <cyg/hal/hal_cache.h>
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50
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51 #ifdef CYGPKG_HAL_POWERPC_MPC860
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52
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53 // eCos headers decribing PowerQUICC:
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54 #include <cyg/hal/quicc/ppc8xx.h>
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55
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56 #include <cyg/hal/quicc/quicc_smc1.h>
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57
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58 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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59 #include <cyg/hal/hal_stub.h> // target_register_t
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60 #include <cyg/hal/hal_intr.h> // HAL_INTERRUPT_UNMASK(...)
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61 #endif
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62
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63 #define UART_BIT_RATE(n) (((CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED*1000000)/16)/n)
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64 #define UART_BAUD_RATE 38400
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66 #define Rxbd 0x2800 /* Rx Buffer Descriptor Offset */
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67 #define Txbd 0x2808 /* Tx Buffer Descriptor Offset */
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68
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69 #define Rxbuf ((volatile char *)eppc + 0x2810)
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70 #define Txbuf ((volatile char *)eppc + 0x2820)
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72
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73 /*
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74 * Initialize SMC1 as a uart.
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75 *
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76 * Comments below reference Motorola's "MPC860 User Manual".
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77 * The basic initialization steps are from Section 16.15.8
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78 * of that manual.
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79 */
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80 static void
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81 init_smc1_uart(void)
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82 {
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83 EPPC *eppc;
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84 volatile struct smc_uart_pram *uart_pram;
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85 struct cp_bufdesc *txbd, *rxbd;
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86
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87 static int init_done = 0;
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88 if (init_done) return;
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89 init_done++;
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90
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91 eppc = eppc_base();
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92
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93 /* SMC1 Uart parameter ram */
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94 uart_pram = &eppc->pram[2].scc.pothers.smc_modem.psmc.u;
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95
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96 /* tx and rx buffer descriptors */
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97 txbd = (struct cp_bufdesc *)((char *)eppc + Txbd);
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98 rxbd = (struct cp_bufdesc *)((char *)eppc + Rxbd);
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99
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100 /*
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101 * Set up the PortB pins for UART operation.
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102 * Set PAR and DIR to allow SMCTXD1 and SMRXD1
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103 * (Table 16-39)
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104 */
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105 eppc->pip_pbpar |= 0xc0;
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106 eppc->pip_pbdir &= ~0xc0;
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107
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108
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109 /* Configure baud rate generator (Section 16.13.2) */
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110 eppc->brgc1 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
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111
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112
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113 /*
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114 * NMSI mode, BRG1 to SMC1
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115 * (Section 16.12.5.2)
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116 */
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117 eppc->si_simode = 0;
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118
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119 /*
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120 * Set pointers to buffer descriptors.
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121 * (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13)
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122 */
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123 uart_pram->rbase = Rxbd;
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124 uart_pram->tbase = Txbd;
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125
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126 /*
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127 * Init Rx & Tx params for SMC1
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128 */
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129 eppc->cp_cr = 0x91;
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130
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131 /*
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132 * SDMA & LCD bus request level 5
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133 * (Section 16.10.2.1)
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134 */
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135 eppc->dma_sdcr = 1;
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136
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137 /*
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138 * Set Rx and Tx function code
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139 * (Section 16.15.4.2)
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140 */
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141 uart_pram->rfcr = 0x18;
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142 uart_pram->tfcr = 0x18;
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143
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144 /* max receive buffer length */
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145 uart_pram->mrblr = 1;
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146
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147 /* disable max_idle feature */
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148 uart_pram->max_idl = 0;
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149
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150 /* no last brk char received */
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151 uart_pram->brkln = 0;
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152
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153 /* no break condition occurred */
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154 uart_pram->brkec = 0;
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155
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156 /* 1 break char sent on top XMIT */
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157 uart_pram->brkcr = 1;
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158
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159 /* setup RX buffer descriptor */
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160 rxbd->length = 0;
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161 rxbd->buffer = Rxbuf;
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162 rxbd->ctrl = 0xb000;
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163
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164 /* setup TX buffer descriptor */
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165 txbd->length = 1;
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166 txbd->buffer = Txbuf;
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167 txbd->ctrl = 0x2000;
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168
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169 /*
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170 * Clear any previous events. Mask interrupts.
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171 * (Section 16.15.7.14 and 16.15.7.15)
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172 */
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173 eppc->smc_regs[0].smc_smce = 0xff;
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174 eppc->smc_regs[0].smc_smcm = 5;
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175
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176 /*
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177 * Set 8,n,1 characters, then also enable rx and tx.
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178 * (Section 16.15.7.11)
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179 */
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180 eppc->smc_regs[0].smc_smcmr = 0x4820;
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181 eppc->smc_regs[0].smc_smcmr = 0x4823;
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182
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183 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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184 HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_CPM_SMC1 );
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185 #endif
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186 }
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187
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188
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189 //#define UART_BUFSIZE 32
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190
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191 //static bsp_queue_t uart_queue;
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192 //static char uart_buffer[UART_BUFSIZE];
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193
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194 #define QUICC_BD_CTL_Busy 0x8000 // Descriptor/buffer busy
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195 #define QUICC_BD_CTL_Wrap 0x2000 // Last buffer in ring
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196 #define QUICC_BD_CTL_Int 0x1000 // Interrupt enable
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197 #define QUICC_BD_CTL_MASK 0xB000 // User settable bits
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198 #define QUICC_SMCE_TX 0x02 // Tx interrupt
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199 #define QUICC_SMCE_RX 0x01 // Rx interrupt
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200 #define QUICC_SMCMR_TEN (1<<1) // Enable transmitter
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201 #define QUICC_SMCMR_REN (1<<0) // Enable receiver
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202
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203 #ifdef CYGDBG_DIAG_BUF
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204 extern int enable_diag_uart;
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205 #endif // CYGDBG_DIAG_BUF
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206
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207 void
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208 cyg_quicc_smc1_uart_putchar(char ch)
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209 {
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210 volatile struct cp_bufdesc *bd, *first;
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211 EPPC *eppc = eppc_base();
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212 volatile struct smc_uart_pram *uart_pram = &eppc->pram[2].scc.pothers.smc_modem.psmc.u;
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213 int timeout;
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214
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215 /* tx buffer descriptor */
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216 bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbptr);
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217
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218 // Scan for a free buffer
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219 first = bd;
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220 while (bd->ctrl & QUICC_BD_CTL_Busy) {
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221 if (bd->ctrl & QUICC_BD_CTL_Wrap) {
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222 bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbase);
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223 } else {
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224 bd++;
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225 }
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226 if (bd == first) break;
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227 }
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228
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229 while (bd->ctrl & QUICC_BD_CTL_Busy) ; // Wait for buffer free
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230 if (bd->ctrl & QUICC_BD_CTL_Int) {
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231 // This buffer has just completed interrupt output. Reset bits
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232 bd->ctrl &= ~QUICC_BD_CTL_Int;
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233 bd->length = 0;
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234 }
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235
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236 bd->buffer[bd->length++] = ch;
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237 bd->ctrl |= QUICC_BD_CTL_Busy;
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238
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239 #ifdef CYGDBG_DIAG_BUF
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240 enable_diag_uart = 0;
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241 #endif // CYGDBG_DIAG_BUF
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242 timeout = 0;
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243 while (bd->ctrl & QUICC_BD_CTL_Busy) {
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244 // Wait until buffer free
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245 if (++timeout == 0x7FFFF) {
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246 // A really long time!
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247 #ifdef CYGDBG_DIAG_BUF
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248 diag_printf("bd fail? bd: %x, ctrl: %x, tx state: %x\n", bd, bd->ctrl, uart_pram->tstate);
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249 #endif // CYGDBG_DIAG_BUF
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250 eppc->smc_regs[0].smc_smcmr &= ~QUICC_SMCMR_TEN; // Disable transmitter
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251 bd->ctrl &= ~QUICC_BD_CTL_Busy;
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252 eppc->smc_regs[0].smc_smcmr |= QUICC_SMCMR_TEN; // Enable transmitter
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253 bd->ctrl |= QUICC_BD_CTL_Busy;
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254 timeout = 0;
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255 #ifdef CYGDBG_DIAG_BUF
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256 diag_printf("bd retry? bd: %x, ctrl: %x, tx state: %x\n", bd, bd->ctrl, uart_pram->tstate);
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257 first = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbase);
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258 while (true) {
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259 diag_printf("bd: %x, ctrl: %x, length: %x\n", first, first->ctrl, first->length);
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260 if (first->ctrl & QUICC_BD_CTL_Wrap) break;
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261 first++;
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262 }
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263 #endif // CYGDBG_DIAG_BUF
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264 }
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265 }
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266 while (bd->ctrl & QUICC_BD_CTL_Busy) ; // Wait until buffer free
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267 bd->length = 0;
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268 #ifdef CYGDBG_DIAG_BUF
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269 enable_diag_uart = 1;
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270 #endif // CYGDBG_DIAG_BUF
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271 }
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272
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273
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274 int
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275 cyg_quicc_smc1_uart_rcvchar(void)
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276 {
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277 volatile struct cp_bufdesc *bd;
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278 char ch;
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279 EPPC *eppc = eppc_base();
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280 volatile struct smc_uart_pram *uart_pram = &eppc->pram[2].scc.pothers.smc_modem.psmc.u;
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281 int cache_state;
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282
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283 /* rx buffer descriptor */
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284 bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->rbptr);
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285
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286 while (bd->ctrl & QUICC_BD_CTL_Busy) ;
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287
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288 ch = bd->buffer[0];
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289
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290 bd->length = 0;
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291 bd->buffer[0] = '\0';
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292 bd->ctrl |= QUICC_BD_CTL_Busy;
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293 // Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
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294 HAL_DCACHE_IS_ENABLED(cache_state);
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295 if (cache_state) {
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296 HAL_DCACHE_INVALIDATE(bd->buffer, uart_pram->mrblr); // Make sure no stale data
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297 }
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298
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299 return ch;
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300 }
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301
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302 /*
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303 * Early initialization of comm channels. Must not rely
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304 * on interrupts, yet. Interrupt operation can be enabled
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305 * in _bsp_board_init().
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306 */
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307 void
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308 cyg_quicc_init_smc1(void)
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309 {
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310 EPPC *eppc = eppc_base();
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311 int i;
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312
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313 static int init = 0; // It's wrong to do this more than once
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314 if (init) return;
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315 init++;
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316
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317 /*
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318 * Reset communications processor
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319 */
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320 eppc->cp_cr = 0x8001;
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321 for (i = 0; i < 100000; i++);
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322
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323 init_smc1_uart();
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324 }
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325
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326 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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327 // This ISR is called from the interrupt handler. This should only
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328 // happen when there is no real serial driver, so the code shouldn't
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329 // mess anything up.
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330 int cyg_hal_gdb_isr( target_register_t pc )
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331 {
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332 EPPC *eppc = eppc_base();
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333 struct cp_bufdesc *bd;
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334 char ch;
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335
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336 eppc->smc_regs[0].smc_smce = 0xff;
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337
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338 /* rx buffer descriptors */
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339 bd = (struct cp_bufdesc *)((char *)eppc_base() + Rxbd);
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340
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341 if ((bd->ctrl & 0x8000) == 0) {
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342 // then there be a character waiting
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343 ch = bd->buffer[0];
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344 bd->length = 1;
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345 bd->ctrl = 0xb000;
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346
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347 if ( 3 == ch ) {
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348 // Ctrl-C: set a breakpoint at PC so GDB will display the
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349 // correct program context when stopping rather than the
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350 // interrupt handler.
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351 cyg_hal_gdb_interrupt( pc );
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352
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353 // Interrupt handled. Don't call ISR proper. At return
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354 // from the VSR, execution will stop at the breakpoint
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355 // just set.
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356
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357 eppc->cpmi_cisr = 0x10;
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358 return 0;
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359 }
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360 }
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361 eppc->cpmi_cisr = 0x10; // acknowledge the Rx event anyway
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362 // in case it was left over from polled reception
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363 // Not caused by GDB. Call ISR proper.
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364 return 1;
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365 }
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366 #endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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367
68
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368 #endif // CYGPKG_HAL_POWERPC_MPC860
32
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369 // EOF quicc_smc1.c