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comparison packages/hal/powerpc/quicc/current/src/quicc_smc1.c @ 770:65a9cab241ce

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Merge DPRAM/CPM changes from trunk
author gthomas
date Thu, 20 Mar 2003 18:48:27 +0000
parents 4ad7466aa844
children 8bbe5c525052
comparison
equal deleted inserted replaced
769:13900f830106 770:65a9cab241ce
7 //========================================================================== 7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN#### 8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // ------------------------------------------- 9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System. 10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. 11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas 12 // Copyright (C) 2002, 2003 Gary Thomas
13 // 13 //
14 // eCos is free software; you can redistribute it and/or modify it under 14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free 15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version. 16 // Software Foundation; either version 2 or (at your option) any later version.
17 // 17 //
131 #define QUICC_SMCE_BSY 0x04 // Busy - receive buffer overrun 131 #define QUICC_SMCE_BSY 0x04 // Busy - receive buffer overrun
132 #define QUICC_SMCE_TX 0x02 // Tx interrupt 132 #define QUICC_SMCE_TX 0x02 // Tx interrupt
133 #define QUICC_SMCE_RX 0x01 // Rx interrupt 133 #define QUICC_SMCE_RX 0x01 // Rx interrupt
134 134
135 /* 135 /*
136 * Reset the communications processor
137 */
138
139 static short nextBd = QUICC_BD_BASE + 0x400;
140
141 static void
142 reset_cpm(void)
143 {
144 EPPC *eppc = eppc_base();
145 int i;
146 static int init_done = 0;
147
148 if (init_done) return;
149 init_done++;
150
151 eppc->cp_cr = QUICC_CPM_CR_RESET | QUICC_CPM_CR_BUSY;
152 memset(eppc->pram, 0, 0x400);
153 for (i = 0; i < 100000; i++);
154
155 nextBd = QUICC_BD_BASE;
156
157 }
158
159 //
160 // Allocate a chunk of memory in the shared CPM memory, typically
161 // used for buffer descriptors, etc. The length will be aligned
162 // to a multiple of 8 bytes.
163 //
164 unsigned short
165 cyg_hal_allocBd(int len)
166 {
167 unsigned short bd = nextBd;
168
169 len = (len + 7) & ~7; // Multiple of 8 bytes
170 nextBd += len;
171 return bd;
172 }
173
174 /*
175 * Initialize SMCX as a uart. 136 * Initialize SMCX as a uart.
176 * 137 *
177 * Comments below reference Motorola's "MPC860 User Manual". 138 * Comments below reference Motorola's "MPC860 User Manual".
178 * The basic initialization steps are from Section 16.15.8 139 * The basic initialization steps are from Section 16.15.8
179 * of that manual. 140 * of that manual.
188 struct cp_bufdesc *txbd, *rxbd; 149 struct cp_bufdesc *txbd, *rxbd;
189 150
190 if (info->init) return; 151 if (info->init) return;
191 info->init = 1; 152 info->init = 1;
192 153
193 reset_cpm(); 154 _mpc8xx_reset_cpm();
194 155
195 switch (port) { 156 switch (port) {
196 #if CYGNUM_HAL_QUICC_SMC1 > 0 157 #if CYGNUM_HAL_QUICC_SMC1 > 0
197 case QUICC_CPM_SMC1: 158 case QUICC_CPM_SMC1:
198 /* 159 /*
238 199
239 /* 200 /*
240 * Set pointers to buffer descriptors. 201 * Set pointers to buffer descriptors.
241 * (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13) 202 * (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13)
242 */ 203 */
243 uart_pram->rbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum); 204 uart_pram->rbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
244 uart_pram->tbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum); 205 uart_pram->tbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
245 206
246 /* 207 /*
247 * SDMA & LCD bus request level 5 208 * SDMA & LCD bus request level 5
248 * (Section 16.10.2.1) 209 * (Section 16.10.2.1)
249 */ 210 */
333 EPPC *eppc = eppc_base(); 294 EPPC *eppc = eppc_base();
334 struct port_info *info = (struct port_info *)__ch_data; 295 struct port_info *info = (struct port_info *)__ch_data;
335 volatile struct smc_uart_pram *uart_pram = (volatile struct smc_uart_pram *)((char *)eppc + info->pram); 296 volatile struct smc_uart_pram *uart_pram = (volatile struct smc_uart_pram *)((char *)eppc + info->pram);
336 volatile struct smc_regs *regs = (volatile struct smc_regs *)((char *)eppc + info->regs); 297 volatile struct smc_regs *regs = (volatile struct smc_regs *)((char *)eppc + info->regs);
337 int timeout; 298 int timeout;
299 int cache_state;
338 CYGARC_HAL_SAVE_GP(); 300 CYGARC_HAL_SAVE_GP();
339 301
340 /* tx buffer descriptor */ 302 /* tx buffer descriptor */
341 bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbptr); 303 bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbptr);
342 304
356 // This buffer has just completed interrupt output. Reset bits 318 // This buffer has just completed interrupt output. Reset bits
357 bd->ctrl &= ~QUICC_BD_CTL_Int; 319 bd->ctrl &= ~QUICC_BD_CTL_Int;
358 bd->length = 0; 320 bd->length = 0;
359 } 321 }
360 322
361 bd->buffer[bd->length++] = ch; 323 bd->length = 1;
324 bd->buffer[0] = ch;
362 bd->ctrl |= QUICC_BD_CTL_Ready; 325 bd->ctrl |= QUICC_BD_CTL_Ready;
326 // Flush cache if necessary - buffer may be in cacheable memory
327 HAL_DCACHE_IS_ENABLED(cache_state);
328 if (cache_state) {
329 HAL_DCACHE_FLUSH(bd->buffer, 1);
330 }
363 331
364 #ifdef CYGDBG_DIAG_BUF 332 #ifdef CYGDBG_DIAG_BUF
365 enable_diag_uart = 0; 333 enable_diag_uart = 0;
366 #endif // CYGDBG_DIAG_BUF 334 #endif // CYGDBG_DIAG_BUF
367 timeout = 0; 335 timeout = 0;
617 struct cp_bufdesc *txbd, *rxbd; 585 struct cp_bufdesc *txbd, *rxbd;
618 586
619 if (info->init) return; 587 if (info->init) return;
620 info->init = 1; 588 info->init = 1;
621 589
622 reset_cpm(); 590 _mpc8xx_reset_cpm();
623 591
624 /* 592 /*
625 * Set up the Port pins for UART operation. 593 * Set up the Port pins for UART operation.
626 */ 594 */
627 switch (port) { 595 switch (port) {
650 break; 618 break;
651 #endif 619 #endif
652 #if CYGNUM_HAL_QUICC_SCC2 > 0 620 #if CYGNUM_HAL_QUICC_SCC2 > 0
653 case QUICC_CPM_SCC2: 621 case QUICC_CPM_SCC2:
654 #error FIXME 622 #error FIXME
655 eppc->pio_papar |= 0x03; 623 eppc->pio_papar |= 0x0C;
656 eppc->pio_padir &= ~0x03; 624 eppc->pio_padir &= ~0x0C;
657 eppc->pio_paodr &= ~0x03; 625 eppc->pio_paodr &= ~0x0C;
658 626
659 /* CTS on PortC.11 */ 627 /* CTS on PortC.11 */
660 eppc->pio_pcdir &= 0x800; 628 eppc->pio_pcdir &= 0xC00;
661 eppc->pio_pcpar &= 0x800; 629 eppc->pio_pcpar &= 0xC00;
662 eppc->pio_pcso |= 0x800; 630 eppc->pio_pcso |= 0xC00;
663 631
664 /* RTS on PortB.19 */ 632 /* RTS on PortB.19 */
665 eppc->pip_pbpar |= 0x1000; 633 eppc->pip_pbpar |= 0x2000;
666 eppc->pip_pbdir |= 0x1000; 634 eppc->pip_pbdir |= 0x2000;
667 635
668 /* Configure baud rate generator (Section 16.13.2) */ 636 /* Configure baud rate generator (Section 16.13.2) */
669 eppc->brgc2 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1); 637 eppc->brgc2 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
670 638
671 /* 639 /*
672 * NMSI mode, BRG2 to SCC1 640 * NMSI mode, BRG2 to SCC2
673 */ 641 */
674 eppc->si_sicr |= (1<<3)|(1<<0); 642 eppc->si_sicr |= (1<<11)|(1<<8);
675 break; 643 break;
676 #endif 644 #endif
677 #if CYGNUM_HAL_QUICC_SCC3 > 0 645 #if CYGNUM_HAL_QUICC_SCC3 > 0
678 case QUICC_CPM_SCC3: 646 case QUICC_CPM_SCC3:
679 #if 0 647 #if 0
704 672
705 /* 673 /*
706 * Set pointers to buffer descriptors. 674 * Set pointers to buffer descriptors.
707 */ 675 */
708 memset((void *)uart_pram, 0xFF, 0x100); 676 memset((void *)uart_pram, 0xFF, 0x100);
709 uart_pram->rbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum); 677 uart_pram->rbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
710 uart_pram->tbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum); 678 uart_pram->tbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
711 679
712 /* 680 /*
713 * SDMA & LCD bus request level 5 681 * SDMA & LCD bus request level 5
714 */ 682 */
715 eppc->dma_sdcr = 1; 683 eppc->dma_sdcr = 1;