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changeset 770:65a9cab241ce

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Merge DPRAM/CPM changes from trunk
author gthomas
date Thu, 20 Mar 2003 18:48:27 +0000
parents 13900f830106
children ee025918fc58
files packages/devs/eth/powerpc/quicc/current/ChangeLog packages/devs/eth/powerpc/quicc/current/src/if_quicc.c packages/devs/serial/powerpc/quicc/current/ChangeLog packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c packages/hal/powerpc/quicc/current/ChangeLog packages/hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl packages/hal/powerpc/quicc/current/include/ppc8xx.h packages/hal/powerpc/quicc/current/src/quicc_smc1.c
diffstat 8 files changed, 66 insertions(+), 67 deletions(-) [+]
line wrap: on
line diff
--- a/packages/devs/eth/powerpc/quicc/current/ChangeLog
+++ b/packages/devs/eth/powerpc/quicc/current/ChangeLog
@@ -1,3 +1,7 @@
+2003-03-06  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/if_quicc.c (quicc_eth_init): New name for CPM/DPRAM allocator.
+
 2002-11-25  Gary Thomas  <gthomas@ecoscentric.com>
 
 	* src/quicc_eth.h: 
--- a/packages/devs/eth/powerpc/quicc/current/src/if_quicc.c
+++ b/packages/devs/eth/powerpc/quicc/current/src/if_quicc.c
@@ -247,8 +247,8 @@ quicc_eth_init(struct cyg_netdevtab_entr
 
     memset((void *)enet_pram, 0, sizeof(*enet_pram));
 
-    TxBD = cyg_hal_allocBd(CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM * sizeof(struct cp_bufdesc));
-    RxBD = cyg_hal_allocBd(CYGNUM_DEVS_ETH_POWERPC_QUICC_RxNUM * sizeof(struct cp_bufdesc));
+    TxBD = _mpc8xx_allocBd(CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM * sizeof(struct cp_bufdesc));
+    RxBD = _mpc8xx_allocBd(CYGNUM_DEVS_ETH_POWERPC_QUICC_RxNUM * sizeof(struct cp_bufdesc));
 
     txbd = (struct cp_bufdesc *)((char *)eppc + TxBD);
     rxbd = (struct cp_bufdesc *)((char *)eppc + RxBD);
--- a/packages/devs/serial/powerpc/quicc/current/ChangeLog
+++ b/packages/devs/serial/powerpc/quicc/current/ChangeLog
@@ -1,3 +1,8 @@
+2003-03-05  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/quicc_smc_serial.c: Use common routines to manage CPM/DPRAM
+	pointers - much nicer in a multi-driver environment.
+
 2003-02-24  Jonathan Larmour  <jifl@eCosCentric.com>
 
 	* cdl/ser_quicc_smc.cdl: Remove irrelevant doc link.
--- a/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
+++ b/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
@@ -9,6 +9,7 @@
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
@@ -59,6 +60,7 @@
 #include <cyg/io/serial.h>
 #include <cyg/infra/diag.h>
 #include <cyg/hal/hal_cache.h>
+#include <cyg/hal/quicc/ppc8xx.h>
 #include CYGBLD_HAL_PLATFORM_H
 
 #ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
@@ -390,6 +392,7 @@ quicc_smc_serial_init(struct cyg_devtab_
     int TxBD, RxBD;
     static int first_init = 1;
     int cache_state;
+
     HAL_DCACHE_IS_ENABLED(cache_state);
     HAL_DCACHE_SYNC();
     HAL_DCACHE_DISABLE();
@@ -402,8 +405,8 @@ quicc_smc_serial_init(struct cyg_devtab_
 #ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1
         eppc->cp_cr = QUICC_SMC_CMD_Reset | QUICC_SMC_CMD_Go;  // Totally reset CP
         while (eppc->cp_cr & QUICC_SMC_CMD_Reset) ;
-        TxBD = 0x2800;  // Note: this should be configurable
-        RxBD = TxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM*8;
+        TxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM);
+        RxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM);
         quicc_smc_serial_init_info(&quicc_smc_serial_info1,
                                    &eppc->pram[2].scc.pothers.smc_modem.psmc.u, // PRAM
                                    &eppc->smc_regs[0], // Control registers
@@ -419,7 +422,6 @@ quicc_smc_serial_init(struct cyg_devtab_
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BRG,
                                    12  // SI mask position
             );
-        TxBD = RxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM*8;
 #else
 #ifdef CYGPKG_HAL_POWERPC_MBX
         // Ensure the SMC1 side is initialized first and use shared mem
@@ -435,7 +437,8 @@ quicc_smc_serial_init(struct cyg_devtab_
 #endif        
 #endif
 #ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2
-        RxBD = TxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM*8;
+        TxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM);
+        RxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM);
         quicc_smc_serial_init_info(&quicc_smc_serial_info2,
                                    &eppc->pram[3].scc.pothers.smc_modem.psmc.u, // PRAM
                                    &eppc->smc_regs[1], // Control registers
--- a/packages/hal/powerpc/quicc/current/ChangeLog
+++ b/packages/hal/powerpc/quicc/current/ChangeLog
@@ -1,3 +1,20 @@
+2003-03-06  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/cpm.c: Handle case where DPRAM allocation is unknown.
+	
+	* include/ppc8xx.h: Define limits of CPM/DPRAM space.
+
+2003-03-05  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/quicc_smc1.c: Need to flush data cache because the serial
+	driver may set use buffers in cacheable memory.  Without this,
+	diag_printf() falls over if the serial driver is ever used.
+
+	* src/cpm.c: New file with CPM/DPRAM support.
+
+	* include/ppc8xx.h: 
+	* cdl/hal_powerpc_quicc.cdl: Split out support for CPM/DPRAM.
+
 2002-11-26  Gary Thomas  <gthomas@ecoscentric.com>
 
 	* src/quicc_smc1.c: Initialize BD allocation point.  Note that it is
--- a/packages/hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl
+++ b/packages/hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl
@@ -9,7 +9,7 @@
 ## -------------------------------------------
 ## This file is part of eCos, the Embedded Configurable Operating System.
 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2002 Gary Thomas
+## Copyright (C) 2002, 2003 Gary Thomas
 ##
 ## eCos is free software; you can redistribute it and/or modify it under
 ## the terms of the GNU General Public License as published by the Free
@@ -100,7 +100,7 @@ cdl_package CYGPKG_HAL_QUICC {
           Port SCC3 is available for serial I/O"
     }
 
-    compile       quicc_smc1.c
+    compile       quicc_smc1.c cpm.c
 
    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
        display      "Number of communication channels on the board"
--- a/packages/hal/powerpc/quicc/current/include/ppc8xx.h
+++ b/packages/hal/powerpc/quicc/current/include/ppc8xx.h
@@ -12,7 +12,7 @@
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2002 Gary Thomas
+// Copyright (C) 2002, 2003 Gary Thomas
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
@@ -939,9 +939,11 @@ static inline EPPC *eppc_base(void)
 
 // Function used to allocate space in shared memory area
 // typically used for buffer descriptors, etc.
-__externC unsigned short cyg_hal_allocBd(int len);
+__externC void _mpc8xx_reset_cpm(void);
+__externC unsigned short _mpc8xx_allocBd(int len);
 
 #define QUICC_BD_BASE               0x2000  // Start of shared memory
+#define QUICC_BD_END                0x3000  // End of shared memory
 
 
 #endif /* __ASSEMBLER__ */
--- a/packages/hal/powerpc/quicc/current/src/quicc_smc1.c
+++ b/packages/hal/powerpc/quicc/current/src/quicc_smc1.c
@@ -9,7 +9,7 @@
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2002 Gary Thomas
+// Copyright (C) 2002, 2003 Gary Thomas
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
@@ -133,45 +133,6 @@ static struct port_info ports[] = {
 #define QUICC_SMCE_RX  0x01  // Rx interrupt
 
 /*
- * Reset the communications processor
- */
-
-static short nextBd = QUICC_BD_BASE + 0x400;
-
-static void
-reset_cpm(void)
-{
-    EPPC *eppc = eppc_base();
-    int i;
-    static int init_done = 0;
-
-    if (init_done) return;
-    init_done++;
-
-    eppc->cp_cr = QUICC_CPM_CR_RESET | QUICC_CPM_CR_BUSY;
-    memset(eppc->pram, 0, 0x400);
-    for (i = 0; i < 100000; i++);
-
-    nextBd = QUICC_BD_BASE;
-
-}
-
-//
-// Allocate a chunk of memory in the shared CPM memory, typically
-// used for buffer descriptors, etc.  The length will be aligned
-// to a multiple of 8 bytes.
-//
-unsigned short
-cyg_hal_allocBd(int len)
-{
-    unsigned short bd = nextBd;
-
-    len = (len + 7) & ~7;  // Multiple of 8 bytes
-    nextBd += len;
-    return bd;
-}
-
-/*
  *  Initialize SMCX as a uart.
  *
  *  Comments below reference Motorola's "MPC860 User Manual".
@@ -190,7 +151,7 @@ cyg_hal_smcx_init_channel(struct port_in
     if (info->init) return;
     info->init = 1;
 
-    reset_cpm();
+    _mpc8xx_reset_cpm();
 
     switch (port) {
 #if CYGNUM_HAL_QUICC_SMC1 > 0
@@ -240,8 +201,8 @@ cyg_hal_smcx_init_channel(struct port_in
      *  Set pointers to buffer descriptors.
      *  (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13)
      */
-    uart_pram->rbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
-    uart_pram->tbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
+    uart_pram->rbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
+    uart_pram->tbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
 
     /*
      *  SDMA & LCD bus request level 5
@@ -335,6 +296,7 @@ cyg_hal_smcx_putc(void* __ch_data, cyg_u
     volatile struct smc_uart_pram *uart_pram = (volatile struct smc_uart_pram *)((char *)eppc + info->pram);
     volatile struct smc_regs *regs = (volatile struct smc_regs *)((char *)eppc + info->regs);
     int timeout;
+    int cache_state;
     CYGARC_HAL_SAVE_GP();
 
     /* tx buffer descriptor */
@@ -358,8 +320,14 @@ cyg_hal_smcx_putc(void* __ch_data, cyg_u
         bd->length = 0;
     }
 
-    bd->buffer[bd->length++] = ch;
+    bd->length = 1;
+    bd->buffer[0] = ch;
     bd->ctrl      |= QUICC_BD_CTL_Ready;
+    // Flush cache if necessary - buffer may be in cacheable memory
+    HAL_DCACHE_IS_ENABLED(cache_state);
+    if (cache_state) {
+      HAL_DCACHE_FLUSH(bd->buffer, 1);
+    }
 
 #ifdef CYGDBG_DIAG_BUF
         enable_diag_uart = 0;
@@ -619,7 +587,7 @@ cyg_hal_sccx_init_channel(struct port_in
     if (info->init) return;
     info->init = 1;
 
-    reset_cpm();
+    _mpc8xx_reset_cpm();
 
     /*
      *  Set up the Port pins for UART operation.
@@ -652,26 +620,26 @@ cyg_hal_sccx_init_channel(struct port_in
 #if CYGNUM_HAL_QUICC_SCC2 > 0
     case QUICC_CPM_SCC2:
 #error FIXME
-        eppc->pio_papar |= 0x03;
-        eppc->pio_padir &= ~0x03;
-        eppc->pio_paodr &= ~0x03;
+        eppc->pio_papar |= 0x0C;
+        eppc->pio_padir &= ~0x0C;
+        eppc->pio_paodr &= ~0x0C;
 
         /* CTS on PortC.11 */
-        eppc->pio_pcdir &= 0x800;
-        eppc->pio_pcpar &= 0x800;
-        eppc->pio_pcso  |= 0x800;
+        eppc->pio_pcdir &= 0xC00;
+        eppc->pio_pcpar &= 0xC00;
+        eppc->pio_pcso  |= 0xC00;
 
         /* RTS on PortB.19 */
-        eppc->pip_pbpar |= 0x1000;
-        eppc->pip_pbdir |= 0x1000;
+        eppc->pip_pbpar |= 0x2000;
+        eppc->pip_pbdir |= 0x2000;
 
         /* Configure baud rate generator (Section 16.13.2) */
         eppc->brgc2 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
 
         /*
-         *  NMSI mode, BRG2 to SCC1
+         *  NMSI mode, BRG2 to SCC2
          */
-        eppc->si_sicr |= (1<<3)|(1<<0);
+        eppc->si_sicr |= (1<<11)|(1<<8);
         break;
 #endif
 #if CYGNUM_HAL_QUICC_SCC3 > 0
@@ -706,8 +674,8 @@ cyg_hal_sccx_init_channel(struct port_in
      *  Set pointers to buffer descriptors.
      */
     memset((void *)uart_pram, 0xFF, 0x100);
-    uart_pram->rbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
-    uart_pram->tbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
+    uart_pram->rbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
+    uart_pram->tbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
 
     /*
      *  SDMA & LCD bus request level 5