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Merge from eCos master repository on 1999-11-19-22:24:39-GMT
author jlarmour
date Fri, 19 Nov 1999 23:37:56 +0000
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53:bf22a672b71b 54:f10165814f1e
1 #ifndef CYGONCE_HAL_EDB7XXX_H
2 #define CYGONCE_HAL_EDB7XXX_H
3
4 /*=============================================================================
5 //
6 // hal_edb7xxx.h
7 //
8 // HAL Support for Kernel Diagnostic Routines
9 //
10 //=============================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Cygnus eCos Public License
15 // Version 1.0 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://sourceware.cygnus.com/ecos
18 //
19 // Software distributed under the License is distributed on an "AS IS"
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Cygnus Operating System, released
25 // September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Cygnus. Portions created
28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
29 // -------------------------------------------
30 //
31 //####COPYRIGHTEND####
32 //=============================================================================
33 //#####DESCRIPTIONBEGIN####
34 //
35 // Author(s): gthomas
36 // Contributors: gthomas
37 // Date: 1999-04-19
38 // Purpose: Cirrus Logic EDB7XXX hardware description
39 // Description:
40 // Usage: #include <cyg/hal/hal_edb7xxx.h>
41 //
42 //####DESCRIPTIONEND####
43 //
44 //===========================================================================*/
45
46 // Note: these defintions match the documentation, thus no attempt is made
47 // to sanitize (mangle) the names. Also, care should be taken to keep this
48 // clean for use in assembly code (no "C" constructs).
49
50 #define PADR 0x80000000 // Port A data register
51 #define PBDR 0x80000001 // Port B data register
52 #define PDDR 0x80000003 // Port D data register
53 #define PADDR 0x80000040 // Port A data direction register
54 #define PBDDR 0x80000041 // Port B data direction register
55 #define PDDDR 0x80000043 // Port D data direction register
56 #define PEDR 0x80000080 // Port E data register
57 #define PEDDR 0x800000C0 // Port E data direction register
58
59 #define SYSCON1 0x80000100 // System control register #1
60 #define SYSCON1_KBD_CTL 0xF // Keyboard scan - mask
61 #define SYSCON1_KBD_HIGH 0 // Keyboard scan - all columns high
62 #define SYSCON1_KBD_LOW 1 // Keyboard scan - all columns low
63 #define SYSCON1_KBD_TRISTATE 2 // Keyboard scan - all columns tri-state
64 #define SYSCON1_KBD_COL(n) (n+8)// Keyboard scan - select column 'n'
65 #define SYSCON1_TC1M (1<<4) // Timer/counter #1 - prescale mode
66 #define SYSCON1_TC1S (1<<5) // Timer/counter #1 - source (1=512KHz,0=2KHz)
67 #define SYSCON1_TC2M (1<<6) // Timer/counter #2 - prescale mode
68 #define SYSCON1_TC2S (1<<7) // Timer/counter #2 - source (1=512KHz,0=2KHz)
69 #define SYSCON1_UART1EN (1<<8) // UART #1 enable
70 #define SYSCON1_BZTOG (1<<9) // Buzzer bit
71 #define SYSCON1_BZMOD (1<<10) // Buzzer mode (0=direct,1=TC1)
72 #define SYSCON1_DBGEN (1<<11) // Enable debug mode
73 #define SYSCON1_LCDEN (1<<12) // Enable LCD
74 #define SYSCON1_CDENTX (1<<13) // Enable Tx on CODEC
75 #define SYSCON1_CDENRX (1<<14) // Enable Rx on CODEC
76 #define SYSCON1_SIREN (1<<15) // Enable SIR protocol on UART #1
77 #define SYSCON1_ADCKSEL (3<<16) // Microwire clock
78 #define SYSCON1_ADC_CLOCK_4kHZ (0<<16)
79 #define SYSCON1_ADC_CLOCK_16kHZ (1<<16)
80 #define SYSCON1_ADC_CLOCK_64kHZ (2<<16)
81 #define SYSCON1_ADC_CLOCK_128kHZ (3<<16)
82 #define SYSCON1_EXCKEN (1<<18) // External expansion clock enable
83 #define SYSCON1_WAKEDIS (1<<19) // Disable wakeup from snooze (do not disturb)
84 #define SYSCON1_IRTXM (1<<20) // IrDA Tx mode
85
86 #define SYSCON2 0x80001100 // System control register #2
87 #define SYSCON2_SERSEL (1<<0) // 0=master/slave SSI, 1=CODEC
88 #define SYSCON2_KBD6 (1<<1) // 0=8 bit keyboard, 1=6 bit
89 #define SYSCON2_DRAMSZ (1<<2) // DRAM width 0=32, 1=16
90 #define SYSCON2_KBWEN (1<<3) // 1=allow wake up from keyboard
91 #define SYSCON2_SS2TXEN (1<<4) // Enable Tx on SS2
92 #define SYSCON2_PCMCIA1 (1<<5) // Enable PCMCIA slot #1
93 #define SYSCON2_PCMCIA2 (1<<6) // Enable PCMCIA slot #2
94 #define SYSCON2_SS2RXEN (1<<7) // Enable Rx on SS2
95 #define SYSCON2_UART2EN (1<<8) // Enable UART #2
96 #define SYSCON2_SS2MAEN (1<<9) // Enable master mode on SS2
97 #define SYSCON2_SNZPOL (1<<10) // Polarity of LCD during snooze
98 #define SYSCON2_LCDSNZE (1<<11)
99 #define SYSCON2_OSTB (1<<12) // Operating system timing 0=512KHz, 1=500KHz
100 #define SYSCON2_CLKENSL (1<<13) // Source of run/clken signal 0=CLKEN, 1=RUN
101 #define SYSCON2_BUZFREQ (1<<14) // Buzzer frequency 0=timer, 1=fixed PLL/xtal
102
103 #define SYSCON3 0x80002200 // System control #3
104 #define SYSCON3_ADCCON (1<<0) // ADC enable
105 #define SYSCON3_CLKCTL(n) (n<<1) // Processor block speed ((n+1)*18.432)MHz
106
107 #define SYSFLG1 0x80000140 // System flags #1
108 #define SYSFLG1_MCDR (1<<0) // Media changed - direct read
109 #define SYSFLG1_DCDET (1<<1) // 0=mains power, 1=battery
110 #define SYSFLG1_WUDR (1<<2) // Wakeup direct
111 #define SYSFLG1_WUON (1<<3) // Woken up
112 #define SYSFLG1_DID (0xF<<4) // Display ID
113 #define SYSFLG1_CTS (1<<8) // UART1 CTS
114 #define SYSFLG1_DSR (1<<9) // UART1 DSR
115 #define SYSFLG1_DCD (1<<10) // UART1 DCD
116 #define SYSFLG1_UBUSY1 (1<<11) // UART1 Tx busy
117 #define SYSFLG1_NBFLG (1<<12) // New battery flag
118 #define SYSFLG1_RSTFLG (1<<13) // Reset (button) flag
119 #define SYSFLG1_PFFLG (1<<14) // Power fail flag
120 #define SYSFLG1_CLDFLG (1<<15) // Cold start flag
121 #define SYSFLG1_RTCDIV (0x3F<<16) // Real time clock divider (counter)
122 #define SYSFLG1_URXFE1 (1<<22) // UART1 Rx FIFO empty
123 #define SYSFLG1_UTXFF1 (1<<23) // UART1 Tx FIFO full
124 #define SYSFLG1_CRXFE (1<<24) // CODEC Rx FIFO empty
125 #define SYSFLG1_CTXFF (1<<25) // CODEC Tx FIFO full
126 #define SYSFLG1_SSIBUSY (1<<26) // Synchronous serial interface busy
127 #define SYSFLG1_BOOTBITS (3<<27) // Boot mode (0=32,1=8,2=16,3=XX)
128 #define SYSFLG1_ID (1<<29) // ID=1
129 #define SYSFLG1_VERID (3<<30) // Board version
130
131 #define SYSFLG2 0x80001140 // System flags #2
132
133 #define INTSR1 0x80000240 // Interrupt status register #1
134 #define INTSR1_EXTFIQ (1<<0) // External fast interrupt
135 #define INTSR1_BLINT (1<<1) // Battery low interrupt
136 #define INTSR1_WEINT (1<<2) // Watchdog expired interrupt
137 #define INTSR1_MCINT (1<<3) // Media changed interrupt
138 #define INTSR1_CSINT (1<<4) // CODEC sound interrupt
139 #define INTSR1_EINT1 (1<<5) // External interrupt #1
140 #define INTSR1_EINT2 (1<<6) // External interrupt #2
141 #define INTSR1_EINT3 (1<<7) // External interrupt #3
142 #define INTSR1_TC1OI (1<<8) // Timer/counter #1 underflow
143 #define INTSR1_TC2OI (1<<9) // Timer/counter #2 underflow
144 #define INTSR1_RTCMI (1<<10) // Real time clock match
145 #define INTSR1_TINT (1<<11) // 64Hz tick
146 #define INTSR1_UTXINT1 (1<<12) // UART1 Tx interrupt
147 #define INTSR1_URXINT1 (1<<13) // UART1 Rx interrupt
148 #define INTSR1_UMSINT (1<<14) // UART1 modem line change
149 #define INTSR1_SSEOTI (1<<15) // Synchronous serial end of transfer
150 #define INTMR1 0x80000280 // Interrupt mask register #1
151
152 #define INTSR2 0x80001240 // Interrupt status #2
153 #define INTSR2_KBDINT (1<<0) // Keyboard interrupt
154 #define INTSR2_SS2RX (1<<1) // Synchronous serial #2 Rx
155 #define INTSR2_SS2TX (1<<2) // Synchronous serial #2 Tx
156 #define INTSR2_UTXINT2 (1<<12) // UART #2 Tx interrupt
157 #define INTSR2_URXINT2 (1<<13) // UART #2 Rx interrupt
158 #define INTMR2 0x80001280 // Interrupt mask #2
159
160 #define INTSR3 0x80002240 // Interrupt status #3
161 #if defined(__EDB7211)
162 #define INTSR3_MCPINT (1<<0) // MCP interrupt
163 #endif
164 #define INTMR3 0x80002280 // Interrupt mask #3
165
166 #define UARTDR1 0x80000480 // UART #1 data register
167 #define UARTDR2 0x80001480 // UART #2 data register
168 #define UBLCR1 0x800004C0 // UART #1 baud rate / line control
169 #define UBLCR2 0x800014C0 // UART #2 baud rate / line control
170 #define UBLCR_BRDV 0xFFF // Baud rate
171 #define UBLCR_BREAK (1<<12) // Generate break signal
172 #define UBLCR_PRTEN (1<<13) // Enable parity
173 #define UBLCR_EVENPRT (1<<14) // 1=even parity, 0=odd
174 #define UBLCR_XSTOP (1<<15) // 0=1 stop bit, 1=2 stop bits
175 #define UBLCR_FIFOEN (1<<16) // Enable Tx/Rx FIFOs
176 #define UBLCR_WRDLEN (3<<17) // Word (character) length field
177 #define UBLCR_WRDLEN5 (0<<17)
178 #define UBLCR_WRDLEN6 (1<<17)
179 #define UBLCR_WRDLEN7 (2<<17)
180 #define UBLCR_WRDLEN8 (3<<17)
181 #define UART_DIVISOR 230400
182 #define UART_BITRATE(baud) ((UART_DIVISOR/(baud))-1)
183
184 #define MEMCFG1 0x80000180 // Memory configuration register #1
185 #define MEMCFG2 0x800001C0 // Memory configuration register #2
186
187 #define DRFPR 0x80000200 // DRAM refresh period
188
189 #define LCDCON 0x800002C0 // LDC control
190 #define LCDCON_BUFSIZ 0x00001FFF // Video buffer size
191 #define LCDCON_BUFSIZ_S 0 // Position of buffer size
192 #define LCDCON_LINE_LENGTH 0x0007E000 // Line length
193 #define LCDCON_LINE_LENGTH_S 13 // Position of line length
194 #define LCDCON_PIX_PRESCALE 0x01F80000 // Pixel prescale value
195 #define LCDCON_PIX_PRESCALE_S 19 // Position of prescale value
196 #define LCDCON_AC_PRESCALE 0x3E000000 // LCD AC bias frequency
197 #define LCDCON_AC_PRESCALE_S 25 // Position to AC bias
198 #define LCDCON_GSEN 0x40000000 // Enable greyscale
199 #define LCDCON_GSMD 0x80000000 // Greyscale mode
200 // 00 - 1bpp, 01 - 2bpp, 11 - 4 bpp
201
202 #define TC1D 0x80000300 // Timer/Counter #1 register
203 #define TC2D 0x80000340 // Timer/Counter #2 register
204 #define RTCDR 0x80000380 // Real time clock data register
205 #define RTCMR 0x800003C0 // Real time clock match register
206
207 #define PMPCON 0x80000400 // DC-DC pump control
208
209 #define CODR 0x80000440 // CODEC data register
210
211 #define SYNCIO 0x80000500 // Synchronous I/O data register
212
213 #define PALLSW 0x80000540 // LCD palette - LSW (Pixel values 0..7)
214 #define PALMSW 0x80000580 // LCD palette - MSW (Pixel values 8..15)
215
216 #define STFCLR 0x800005C0 // Clear startup reason flags
217 #define BLEOI 0x80000600 // Clear battery low interrupt
218 #define MCEOI 0x80000640 // Clear media changed interrupt
219 #define TEOI 0x80000680 // Clear tick/watchdog interrupt
220 #define TC1EOI 0x800006C0 // Clear timer/counter #1 interrupt
221 #define TC2EOI 0x80000700 // Clear timer/counter #2 interrupt
222 #define RTCEOI 0x80000740 // Clear real time clock interrupt
223 #define UMSEOI 0x80000780 // Clear UART modem status change interrupt
224 #define COEOI 0x800007C0 // Clear CODEC sound interrupt
225
226 #define HALT 0x80000800 // Enter 'idle' state
227 #define STDBY 0x80000840 // Enter 'standby' state
228
229 #define FRBADDR 0x80001000 // LCD frame buffer start
230
231 #define SNZDISP 0x800012C0 // Snooze display size
232
233 #define SS2DR 0x80001500 // Master/slave SSI2 register
234
235 #define SRXEOF 0x80001600 // Clear Rx FIFO overflow flag
236 #define SS2POP 0x800016C0 // Pop SSI2 residual byte into FIFO
237
238 #define KBDEOI 0x80001700 // Clear keyboard interrupt
239
240 #define SNOOZE 0x80001800 // Enter 'snooze' state
241
242 #if defined(__EDB7211)
243 #define MCCR 0x80002000 // MCP control register
244 #define MCDR0 0x80002040 // MCP data register #0
245 #define MCDR1 0x80002080 // MCP data register #1
246 #define MCDR2 0x800020C0 // MCP data register #2
247 #define MCSR 0x80002100 // MCP status register
248 #endif
249
250
251 #define LEDFLSH 0x800022C0 // LED flash control
252 #define LEDFLSH_ENABLE (1<<6) // LED enabled
253 #define LEDFLSH_DUTY(n) ((n-1)<<2) // LED on ratio
254 #define LEDFLSH_PERIOD(n) (n-1) // LED active time (1..4)
255
256 #define KBD_PORT 0x30010000 // Extra 8 bits of keyboard data
257
258 /*---------------------------------------------------------------------------*/
259 /* end of hal_edb7xxx.h */
260 #endif /* CYGONCE_HAL_EDB7XXX_H */