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comparison packages/hal/arm/edb7xxx/current/include/hal_platform_setup.h @ 54:f10165814f1e ecos-sw-1999-11-19

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Merge from eCos master repository on 1999-11-19-22:24:39-GMT
author jlarmour
date Fri, 19 Nov 1999 23:37:56 +0000
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children 755351606154
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53:bf22a672b71b 54:f10165814f1e
1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
3
4 /*=============================================================================
5 //
6 // hal_platform_setup.h
7 //
8 // Platform specific support for HAL (assembly code)
9 //
10 //=============================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Cygnus eCos Public License
15 // Version 1.0 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://sourceware.cygnus.com/ecos
18 //
19 // Software distributed under the License is distributed on an "AS IS"
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Cygnus Operating System, released
25 // September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Cygnus. Portions created
28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
29 // -------------------------------------------
30 //
31 //####COPYRIGHTEND####
32 //=============================================================================
33 //#####DESCRIPTIONBEGIN####
34 //
35 // Author(s): gthomas
36 // Contributors: gthomas
37 // Date: 1999-04-21
38 // Purpose: Cirrus EDB7XXX platform specific support routines
39 // Description:
40 // Usage: #include <cyg/hal/hal_platform_setup.h>
41 //
42 //####DESCRIPTIONEND####
43 //
44 //===========================================================================*/
45
46 #include <pkgconf/system.h> // System-wide configuration info
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_edb7xxx.h> // Platform specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50
51 #define CYGHWR_HAL_ARM_HAS_MMU // This processor has an MMU
52
53 //
54 // Memory map - set up by ROM (GDB stubs)
55 //
56 // Region Logical Address Physical Address
57 // DRAM 0x00000000..0x00xFFFFF 0xC00x0000 (see below)
58 // Expansion 2 0x20000000 0x20000000
59 // Expansion 3 0x30000000 0x30000000
60 // PCMCIA 0 0x40000000 0x40000000
61 // PCMCIA 1 0x50000000 0x50000000
62 // SRAM 0x60000000..0x600007FF 0x60000000
63 // I/O 0x80000000 0x80000000
64 // MMU Tables 0xC00y0000
65 // LCD buffer 0xC0000000..0xC001FFFF 0xC0000000
66 // ROM 0xE0000000..0xEFFFFFFF 0x00000000
67 // ROM 0xF0000000..0xFFFFFFFF 0x10000000
68
69 #ifdef CYGHWR_HAL_ARM_EDB7XXX_LCD_INSTALLED
70 #define LCD_BUFFER_SIZE 0x00020000
71 #else
72 #define LCD_BUFFER_SIZE 0x00000000
73 #endif
74 #define DRAM_PA_START 0xC0000000
75 #define MMU_BASE DRAM_PA_START+LCD_BUFFER_SIZE
76 #define PTE_BASE DRAM_PA_START+0x4000+LCD_BUFFER_SIZE
77 #if (CYGHWR_HAL_ARM_EDB7XXX_DRAM_SIZE == 2)
78 #define MMU_TABLES_SIZE (0x4000+0x1000+0x1000) // RAM used for PTE entries
79 #define DRAM_LA_END (0x00200000-MMU_TABLES_SIZE-LCD_BUFFER_SIZE)
80 #elif (CYGHWR_HAL_ARM_EDB7XXX_DRAM_SIZE == 16)
81 #define MMU_TABLES_SIZE (0x4000+0x4000+0x1000) // RAM used for PTE entries
82 #define DRAM_LA_END (0x01000000-MMU_TABLES_SIZE-LCD_BUFFER_SIZE)
83 #endif
84 #define DRAM_LA_START 0x00000000
85 #define DRAM_PA MMU_BASE+MMU_TABLES_SIZE
86 #define LCD_LA_START 0xC0000000
87 #define LCD_LA_END 0xC0020000
88 #define LCD_PA 0xC0000000
89 #define ROM0_LA_START 0xE0000000
90 #define ROM0_PA 0x00000000
91 #define ROM0_LA_END 0xF0000000
92 #define ROM1_LA_START 0xF0000000
93 #define ROM1_LA_END 0x00000000
94 #define ROM1_PA 0x10000000
95 #define EXPANSION2_LA_START 0x20000000
96 #define EXPANSION2_PA 0x20000000
97 #define EXPANSION3_LA_START 0x30000000
98 #define EXPANSION3_PA 0x30000000
99 #define PCMCIA0_LA_START 0x40000000
100 #define PCMCIA0_PA 0x40000000
101 #define PCMCIA1_LA_START 0x50000000
102 #define PCMCIA1_PA 0x50000000
103 #define SRAM_LA_START 0x60000000
104 #define SRAM_LA_END 0x60001000
105 #define SRAM_PA 0x60000000
106 #define IO_LA_START 0x80000000
107 #define IO_LA_END 0x80003000
108 #define IO_PA 0x80000000
109
110 // Define startup code [macros]
111 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS)
112
113 #if (CYGHWR_HAL_ARM_EDB7XXX_DRAM_SIZE == 2)
114 // Note: The DRAM on this board is very irregular in that every
115 // other 256K piece is missing. E.g. only these [physical]
116 // addresses are valid:
117 // 0xC0000000..0xC003FFFF
118 // 0xC0080000..0xC00BFFFF
119 // 0xC0200000..0xC023FFFF Note the additional GAP!
120 // etc.
121 // 0xC0800000..0xC083FFFF Note the additional GAP!
122 // 0xC0880000..0xC08CFFFF
123 // 0xC0A00000..0xC0A3FFFF
124 // etc.
125 // The MMU mapping code takes this into consideration and creates
126 // a continuous logical map for the DRAM.
127 #define MAP_DRAM \
128 /* Map DRAM */ ;\
129 ldr r3,=DRAM_LA_START ;\
130 ldr r4,=DRAM_LA_END ;\
131 ldr r5,=DRAM_PA ;\
132 /* 0x00000000..0x000FFFFF */ ;\
133 mov r6,r2 /* Set up page table descriptor */ ;\
134 ldr r7,=MMU_L1_TYPE_Page ;\
135 orr r6,r6,r7 ;\
136 str r6,[r1],#4 /* Store PTE, update pointer */ ;\
137 10: mov r6,r5 /* Build page table entry */ ;\
138 ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\
139 orr r6,r6,r7 ;\
140 ldr r7,=MMU_PAGE_SIZE ;\
141 str r6,[r2],#4 /* Next page */ ;\
142 add r3,r3,r7 ;\
143 add r5,r5,r7 ;\
144 ldr r8,=DRAM_LA_START+MMU_SECTION_SIZE ;\
145 cmp r3,r8 /* Done with first 1M? */ ;\
146 beq 20f ;\
147 ldr r7,=0x40000 /* Special check for 256K boundary */ ;\
148 and r7,r7,r5 ;\
149 cmp r7,#0 ;\
150 beq 10b ;\
151 add r5,r5,r7 /* Skip 256K hole */ ;\
152 ldr r7,=0x100000 ;\
153 and r7,r5,r7 ;\
154 beq 10b ;\
155 add r5,r5,r7 /* Nothing at 0xC0100000 */ ;\
156 ldr r7,=0x400000 /* Also nothing at 0xC0400000 */ ;\
157 and r7,r5,r7 ;\
158 beq 10b ;\
159 add r5,r5,r7 ;\
160 b 10b ;\
161 20: ;\
162 /* 0x00100000..0x001FFFFF */ ;\
163 mov r6,r2 /* Set up page table descriptor */ ;\
164 ldr r7,=MMU_L1_TYPE_Page ;\
165 orr r6,r6,r7 ;\
166 str r6,[r1],#4 /* Store PTE, update pointer */ ;\
167 10: mov r6,r5 /* Build page table entry */ ;\
168 ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\
169 orr r6,r6,r7 ;\
170 ldr r7,=MMU_PAGE_SIZE ;\
171 str r6,[r2],#4 /* Next page */ ;\
172 add r3,r3,r7 ;\
173 cmp r3,r4 /* Done with first DRAM? */ ;\
174 beq 20f ;\
175 add r5,r5,r7 ;\
176 ldr r7,=0x40000 /* Special check for 256K boundary */ ;\
177 and r7,r7,r5 ;\
178 cmp r7,#0 ;\
179 beq 10b ;\
180 add r5,r5,r7 /* Skip 256K hole */ ;\
181 ldr r7,=0x100000 ;\
182 and r7,r5,r7 ;\
183 beq 10b ;\
184 add r5,r5,r7 /* Nothing at 0xC0300000 */ ;\
185 ldr r7,=0x400000 /* Also nothing at 0xC0400000 */ ;\
186 and r7,r5,r7 ;\
187 beq 10b ;\
188 add r5,r5,r7 ;\
189 b 10b ;\
190 20: ;
191 #elif (CYGHWR_HAL_ARM_EDB7XXX_DRAM_SIZE == 16)
192 // The 16M board is arranged as:
193 // 0xC0000000..0xC07FFFFF
194 // 0xC1000000..0xC17FFFFF
195 #define MAP_DRAM \
196 /* Map DRAM */ ;\
197 ldr r3,=DRAM_LA_START ;\
198 ldr r4,=DRAM_LA_END ;\
199 ldr r5,=DRAM_PA ;\
200 /* 0xXXX00000..0xXXXFFFFF */ ;\
201 10: mov r6,r2 /* Set up page table descriptor */ ;\
202 ldr r7,=MMU_L1_TYPE_Page ;\
203 orr r6,r6,r7 ;\
204 str r6,[r1],#4 /* Store PTE, update pointer */ ;\
205 ldr r8,=MMU_SECTION_SIZE/MMU_PAGE_SIZE ;\
206 ldr r9,=DRAM_PA_START+0x00800000 /* Need to skip at 8M boundary */ ;\
207 12: cmp r5,r9 ;\
208 bne 15f ;\
209 ldr r5,=DRAM_PA_START+0x01000000 /* Next chunk of DRAM */ ;\
210 15: mov r6,r5 /* Build page table entry */ ;\
211 ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\
212 orr r6,r6,r7 ;\
213 ldr r7,=MMU_PAGE_SIZE ;\
214 str r6,[r2],#4 /* Next page */ ;\
215 add r3,r3,r7 ;\
216 add r5,r5,r7 ;\
217 cmp r3,r4 /* End of DRAM? */ ;\
218 beq 20f ;\
219 sub r8,r8,#1 /* End of 1M section? */ ;\
220 cmp r8,#0 ;\
221 bne 12b /* Next page */ ;\
222 b 10b /* Next section */ ;\
223 20:
224 #else
225 #err Invalid DRAM size selected
226 #endif
227
228 #ifdef CYG_HAL_ARM_CL7111 // CL7111, 710 processor
229 #define MMU_INITIALIZE \
230 ldr r1,=MMU_Control_Init ;\
231 mcr MMU_CP,0,r1,MMU_Control,c0 /* MMU off */ ;\
232 ldr r1,=MMU_BASE ;\
233 mcr MMU_CP,0,r1,MMU_Base,c0 ;\
234 mcr MMU_CP,0,r1,MMU_FlushTLB,c0,0 /* Invalidate TLB */ ;\
235 mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */ ;\
236 ldr r1,=0xFFFFFFFF ;\
237 mcr MMU_CP,0,r1,MMU_DomainAccess,c0 ;\
238 ldr r2,=10f ;\
239 ldr r1,=MMU_Control_Init|MMU_Control_M ;\
240 mcr MMU_CP,0,r1,MMU_Control,c0 ;\
241 mov pc,r2 /* Change address spaces */ ;\
242 nop ;\
243 nop ;\
244 nop ;\
245 10:
246 #else // EP7211, 720T processor
247 #define MMU_INITIALIZE ;\
248 ldr r1,=MMU_Control_Init ;\
249 mcr MMU_CP,0,r1,MMU_Control,c0 /* MMU off */ ;\
250 ldr r1,=MMU_BASE ;\
251 mcr MMU_CP,0,r1,MMU_Base,c0 ;\
252 mcr MMU_CP,0,r1,MMU_TLB,c7,0 /* Invalidate TLB - 720 style */ ;\
253 mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */ ;\
254 ldr r1,=0xFFFFFFFF ;\
255 mcr MMU_CP,0,r1,MMU_DomainAccess,c0 ;\
256 ldr r2,=10f ;\
257 ldr r3,=__exception_handlers ;\
258 sub r2,r2,r3 ;\
259 ldr r3,=ROM0_LA_START ;\
260 add r2,r2,r3 ;\
261 ldr r1,=MMU_Control_Init|MMU_Control_M ;\
262 mcr MMU_CP,0,r1,MMU_Control,c0 ;\
263 mov pc,r2 /* Change address spaces */ ;\
264 nop ;\
265 nop ;\
266 nop ;\
267 10:
268 #endif
269
270 #define PLATFORM_SETUP1 \
271 /* Initialize memory configuration */ ;\
272 ldr r1,=MEMCFG1 ;\
273 ldr r2,=0x8200A080 /* FIXME - what is this? */ ;\
274 str r2,[r1] ;\
275 ldr r1,=MEMCFG2 ;\
276 ldr r2,=0xFEFC0000 ;\
277 str r2,[r1] ;\
278 ldr r1,=DRFPR ;\
279 ldr r2,=0x81 /* DRAM refresh = 64KHz */ ;\
280 strb r2,[r1] ;\
281 /* Initialize MMU to create new memory map */ ;\
282 ldr r1,=MMU_BASE ;\
283 ldr r2,=PTE_BASE ;\
284 MAP_DRAM ;\
285 /* Nothing until PCMCIA0 */ ;\
286 ldr r3,=0x3FF /* Page tables need 2K boundary */ ;\
287 add r2,r2,r3 ;\
288 ldr r3,=~0x3FF ;\
289 and r2,r2,r3 ;\
290 ldr r3,=(DRAM_LA_END+0x000FFFFF)&0xFFF00000 ;\
291 ldr r4,=EXPANSION2_LA_START ;\
292 ldr r5,=MMU_L1_TYPE_Fault ;\
293 ldr r7,=MMU_SECTION_SIZE ;\
294 10: str r5,[r1],#4 ;\
295 add r3,r3,r7 ;\
296 cmp r3,r4 ;\
297 bne 10b ;\
298 /* EXPANSION2, EXPANSION3, PCMCIA0, PCMCIA1 */ ;\
299 ldr r3,=EXPANSION2_LA_START ;\
300 ldr r4,=SRAM_LA_START ;\
301 ldr r5,=EXPANSION2_PA ;\
302 ldr r6,=MMU_L1_TYPE_Section|MMU_AP_Any ;\
303 ldr r7,=MMU_SECTION_SIZE ;\
304 10: orr r0,r5,r6 ;\
305 str r0,[r1],#4 ;\
306 add r5,r5,r7 ;\
307 add r3,r3,r7 ;\
308 cmp r3,r4 ;\
309 bne 10b ;\
310 /* SRAM */ ;\
311 ldr r3,=SRAM_LA_START ;\
312 ldr r4,=MMU_L1_TYPE_Page|MMU_DOMAIN(0) ;\
313 orr r4,r4,r2 ;\
314 str r4,[r1],#4 ;\
315 ldr r4,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\
316 orr r4,r3,r4 ;\
317 str r4,[r2],#4 ;\
318 ldr r3,=SRAM_LA_START+MMU_PAGE_SIZE ;\
319 ldr r4,=SRAM_LA_START+MMU_SECTION_SIZE ;\
320 ldr r5,=MMU_L2_TYPE_Fault ;\
321 ldr r7,=MMU_PAGE_SIZE ;\
322 10: str r5,[r2],#4 ;\
323 add r3,r3,r7 ;\
324 cmp r3,r4 ;\
325 bne 10b ;\
326 ldr r4,=IO_LA_START ;\
327 ldr r5,=MMU_L1_TYPE_Fault ;\
328 ldr r7,=MMU_SECTION_SIZE ;\
329 20: str r5,[r1],#4 ;\
330 add r3,r3,r7 ;\
331 cmp r3,r4 ;\
332 bne 20b ;\
333 /* I/O */ ;\
334 ldr r3,=0x3FF /* Page tables need 2K boundary */ ;\
335 add r2,r2,r3 ;\
336 ldr r3,=~0x3FF ;\
337 and r2,r2,r3 ;\
338 ldr r4,=MMU_L1_TYPE_Page|MMU_DOMAIN(0) ;\
339 orr r4,r4,r2 ;\
340 str r4,[r1],#4 ;\
341 ldr r3,=IO_LA_START ;\
342 ldr r4,=IO_LA_END ;\
343 ldr r7,=MMU_PAGE_SIZE ;\
344 ldr r5,=IO_PA|MMU_L2_TYPE_Small|MMU_AP_All ;\
345 10: str r5,[r2],#4 ;\
346 add r5,r5,r7 ;\
347 add r3,r3,r7 ;\
348 cmp r3,r4 ;\
349 bne 10b ;\
350 ldr r4,=IO_LA_START+MMU_SECTION_SIZE ;\
351 ldr r5,=MMU_L2_TYPE_Fault ;\
352 ldr r7,=MMU_PAGE_SIZE ;\
353 10: str r5,[r2],#4 ;\
354 add r3,r3,r7 ;\
355 cmp r3,r4 ;\
356 bne 10b ;\
357 ldr r4,=LCD_LA_START ;\
358 ldr r5,=MMU_L1_TYPE_Fault ;\
359 ldr r7,=MMU_SECTION_SIZE ;\
360 20: str r5,[r1],#4 ;\
361 add r3,r3,r7 ;\
362 cmp r3,r4 ;\
363 bne 20b ;\
364 /* LCD Buffer & Unmapped DRAM (holes and all) */ ;\
365 ldr r3,=LCD_LA_START ;\
366 ldr r4,=ROM0_LA_START ;\
367 ldr r5,=LCD_PA ;\
368 ldr r6,=MMU_L1_TYPE_Section|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\
369 ldr r7,=MMU_SECTION_SIZE ;\
370 10: orr r0,r5,r6 ;\
371 str r0,[r1],#4 ;\
372 add r5,r5,r7 ;\
373 add r3,r3,r7 ;\
374 cmp r3,r4 ;\
375 bne 10b ;\
376 /* ROM0 */ ;\
377 ldr r3,=ROM0_LA_START ;\
378 ldr r4,=ROM0_LA_END ;\
379 ldr r5,=ROM0_PA ;\
380 ldr r6,=MMU_L1_TYPE_Section|MMU_AP_Any|MMU_Cacheable ;\
381 ldr r7,=MMU_SECTION_SIZE ;\
382 10: orr r0,r5,r6 ;\
383 str r0,[r1],#4 ;\
384 add r5,r5,r7 ;\
385 add r3,r3,r7 ;\
386 cmp r3,r4 ;\
387 bne 10b ;\
388 /* ROM1 */ ;\
389 ldr r3,=ROM1_LA_START ;\
390 ldr r4,=ROM1_LA_END ;\
391 ldr r5,=ROM1_PA ;\
392 ldr r6,=MMU_L1_TYPE_Section|MMU_AP_Any ;\
393 ldr r7,=MMU_SECTION_SIZE ;\
394 10: orr r0,r5,r6 ;\
395 str r0,[r1],#4 ;\
396 add r5,r5,r7 ;\
397 add r3,r3,r7 ;\
398 cmp r3,r4 ;\
399 bne 10b ;\
400 /* Now initialize the MMU to use this new page table */ ;\
401 MMU_INITIALIZE ;\
402 ldr r2,=__exception_handlers ;\
403 ldr r3,=ROM0_LA_START ;\
404 cmp r2,r3 ;\
405 beq 20f ;\
406 ldr r4,=__rom_data_end ;\
407 15: ;\
408 ldr r0,[r3],#4 ;\
409 str r0,[r2],#4 ;\
410 cmp r2,r4 ;\
411 bne 15b ;\
412 20:
413
414 #else
415
416 #define PLATFORM_SETUP1
417 #endif
418
419
420 /*---------------------------------------------------------------------------*/
421 /* end of hal_platform_setup.h */
422 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */