Mercurial > ecos-v3_0-branch
annotate packages/hal/arm/arch/current/src/vectors.S @ 14:01ce82f3e11a ecos-sw-1999-06-11
Merge from eCos master repository on 1999-06-11-17:05:41-BST
| author | jlarmour |
|---|---|
| date | Fri, 11 Jun 1999 09:36:56 +0000 |
| parents | d3fbcdfa1b2f |
| children | 4f2df4ab82c8 |
| rev | line source |
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| 2 | 1 // #======================================================================== |
| 2 // # | |
| 3 // # vectors.S | |
| 4 // # | |
| 5 // # ARM exception vectors | |
| 6 // # | |
| 7 // #======================================================================== | |
| 8 // ####COPYRIGHTBEGIN#### | |
| 9 // | |
| 10 // ------------------------------------------- | |
| 11 // The contents of this file are subject to the Cygnus eCos Public License | |
| 12 // Version 1.0 (the "License"); you may not use this file except in | |
| 13 // compliance with the License. You may obtain a copy of the License at | |
| 14 // http://sourceware.cygnus.com/ecos | |
| 15 // | |
| 16 // Software distributed under the License is distributed on an "AS IS" | |
| 17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 18 // License for the specific language governing rights and limitations under | |
| 19 // the License. | |
| 20 // | |
| 21 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 22 // September 30, 1998. | |
| 23 // | |
| 24 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 25 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. | |
| 26 // ------------------------------------------- | |
| 27 // | |
| 28 // ####COPYRIGHTEND#### | |
| 29 // #======================================================================== | |
| 30 // ######DESCRIPTIONBEGIN#### | |
| 31 // # | |
| 32 // # Author(s): nickg, gthomas | |
| 33 // # Contributors: nickg, gthomas | |
| 34 // # Date: 1999-02-20 | |
| 35 // # Purpose: ARM exception vectors | |
| 36 // # Description: This file defines the code placed into the exception | |
| 37 // # vectors. It also contains the first level default VSRs | |
| 38 // # that save and restore state for both exceptions and | |
| 39 // # interrupts. | |
| 40 // # | |
| 41 // #####DESCRIPTIONEND#### | |
| 42 // # | |
| 43 // #======================================================================== | |
| 44 | |
| 45 #include <pkgconf/hal.h> | |
| 46 #include <pkgconf/hal_arm.h> | |
| 47 #ifdef CYGPKG_KERNEL // no CDL yet | |
| 48 #include <pkgconf/kernel.h> | |
| 49 #else | |
| 50 # undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
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51 # undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
| 2 | 52 #endif |
| 53 #include <cyg/hal/hal_platform_setup.h> | |
| 54 | |
| 55 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 56 // The CDL should enforce this | |
| 57 #undef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 58 #endif | |
| 59 | |
| 60 #include "arm.inc" | |
| 61 | |
| 62 #define FUNC_START(name) \ | |
| 63 .globl _name; \ | |
| 64 _name: | |
| 65 | |
| 66 #define PTR(name) \ | |
| 67 .##name: .word name | |
| 68 | |
| 69 | |
| 70 .file "vectors.S" | |
| 71 | |
| 72 | |
| 73 //========================================================================== | |
| 74 // Hardware exception vectors. | |
| 75 // This entire section will be copied to location 0x0000 at startup time. | |
| 76 // | |
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77 .code 32 |
| 2 | 78 .section ".vectors","ax" |
| 79 .global __exception_handlers | |
| 80 __exception_handlers: | |
| 81 ldr pc,.reset_vector // 0x00 | |
| 82 ldr pc,.undefined_instruction // 0x04 | |
| 83 ldr pc,.software_interrupt // 0x08 start && software int | |
| 84 ldr pc,.abort_prefetch // 0x0C | |
| 85 ldr pc,.abort_data // 0x10 | |
| 86 .word 0 // unused | |
| 87 ldr pc,.IRQ // 0x18 | |
| 88 ldr pc,.FIQ // 0x1C | |
| 89 | |
| 90 // The layout of these pointers should match the vector table above since | |
| 91 // they are copied in pairs. | |
| 92 .global vectors | |
| 93 vectors: | |
| 94 PTR(reset_vector) | |
| 95 PTR(undefined_instruction) | |
| 96 PTR(software_interrupt) | |
| 97 PTR(abort_prefetch) | |
| 98 PTR(abort_data) | |
| 99 .word 0 | |
| 100 PTR(IRQ) | |
| 101 PTR(FIQ) | |
| 102 PTR(start) | |
| 103 | |
| 104 .text | |
| 105 // Startup code which will get the machine into supervisor mode | |
| 106 .global reset_vector | |
| 107 .type reset_vector,function | |
| 108 reset_vector: | |
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109 |
| 2 | 110 #if defined(CYG_HAL_STARTUP_RAM) && \ |
| 111 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 112 mrs r7,cpsr // move back to IRQ mode | |
| 113 and r7,r7,#CPSR_MODE_BITS | |
| 114 cmp r7,#CPSR_SUPERVISOR_MODE | |
| 115 beq start | |
| 116 #endif | |
| 117 | |
| 118 PLATFORM_SETUP1 // Early stage platform initialization | |
| 119 // see <cyg/hal/hal_platform_setup.h> | |
| 120 | |
| 121 mov r0,#0 // move vectors | |
| 122 ldr r1,.__exception_handlers | |
| 123 ldr r2,[r1,#0x04] // undefined instruction | |
| 124 str r2,[r0,#0x04] | |
| 125 ldr r2,[r1,#0x24] | |
| 126 str r2,[r0,#0x24] | |
| 127 ldr r2,[r1,#0x08] // software interrupt | |
| 128 str r2,[r0,#0x08] | |
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129 #if defined(CYG_HAL_STARTUP_RAM) |
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130 // Ugly hack to get into supervisor mode |
| 2 | 131 ldr r2,[r1,#0x40] |
| 132 str r2,[r0,#0x28] | |
| 133 swi // switch to supervisor mode | |
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134 #endif |
| 2 | 135 |
| 136 // ========================================================================= | |
| 137 // Real startup code. We jump here from the reset vector to set up the world. | |
| 138 .globl start | |
| 139 start: | |
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140 |
| 2 | 141 #if defined(CYG_HAL_STARTUP_RAM) && \ |
| 142 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 143 // If we get restarted, hang here to avoid corrupting memory | |
| 144 ldr r0,.init_flag | |
| 145 ldr r1,[r0] | |
| 146 1: cmp r1,#0 | |
| 147 bne 1b | |
| 148 ldr r1,init_done | |
| 149 str r1,[r0] | |
| 150 #endif | |
| 151 | |
| 152 // Reset software interrupt pointer | |
| 153 mov r0,#0 // move vectors | |
| 154 ldr r1,.__exception_handlers | |
| 155 #if defined(CYG_HAL_STARTUP_RAM) && \ | |
| 156 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 157 cmp r7,#CPSR_SUPERVISOR_MODE | |
| 158 beq 10f | |
| 159 #endif | |
| 160 ldr r2,[r1,#0x28] // software interrupt | |
| 161 str r2,[r0,#0x28] | |
| 162 10: | |
| 163 ldr r2,[r1,#0x18] // IRQ | |
| 164 str r2,[r0,#0x18] | |
| 165 ldr r2,[r1,#0x38] | |
| 166 str r2,[r0,#0x38] | |
| 167 ldr r2,[r1,#0x1C] // FIQ | |
| 168 str r2,[r0,#0x1C] | |
| 169 ldr r2,[r1,#0x3C] | |
| 170 str r2,[r0,#0x3C] | |
| 171 ldr r2,[r1,#0x0C] // abort (prefetch) | |
| 172 str r2,[r0,#0x0C] | |
| 173 ldr r2,[r1,#0x2C] | |
| 174 str r2,[r0,#0x2C] | |
| 175 ldr r2,[r1,#0x10] // abort (data) | |
| 176 str r2,[r0,#0x10] | |
| 177 ldr r2,[r1,#0x30] | |
| 178 str r2,[r0,#0x30] | |
| 179 | |
| 180 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) | |
| 181 // Relocate [copy] data from ROM to RAM | |
| 182 ldr r3,.__rom_data_start | |
| 183 ldr r4,.__ram_data_start | |
| 184 ldr r5,.__ram_data_end | |
| 185 cmp r4,r5 // jump if no data to move | |
| 186 beq 2f | |
| 187 sub r3,r3,#4 // loop adjustments | |
| 188 sub r4,r4,#4 | |
| 189 1: ldr r0,[r3,#4]! // copy info | |
| 190 str r0,[r4,#4]! | |
| 191 cmp r4,r5 | |
| 192 bne 1b | |
| 193 2: | |
| 194 #endif | |
| 195 | |
| 196 // initialize interrupt/exception environments | |
| 197 ldr sp,.__startup_stack | |
| 198 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_IRQ_MODE) | |
| 199 msr cpsr,r0 | |
| 200 ldr sp,.__exception_stack | |
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201 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_FIQ_MODE) |
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202 msr cpsr,r0 |
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203 ldr sp,.__exception_stack |
| 2 | 204 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_UNDEF_MODE) |
| 205 msr cpsr,r0 | |
| 206 ldr sp,.__exception_stack | |
| 207 | |
| 208 // initialize CPSR (machine state register) | |
| 209 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) | |
| 210 msr cpsr,r0 | |
| 211 | |
| 212 // Note: some functions in LIBGCC1 will cause a "restore from SPSR"!! | |
| 213 msr spsr,r0 | |
| 214 | |
| 215 // initialize stack | |
| 216 ldr sp,.__startup_stack | |
| 217 | |
| 218 // clear BSS | |
| 219 ldr r1,.__bss_start | |
| 220 ldr r2,.__bss_end | |
| 221 mov r0,#0 | |
| 222 cmp r1,r2 | |
| 223 beq 2f | |
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224 1: str r0,[r1],#4 |
| 2 | 225 cmp r1,r2 |
| 226 bne 1b | |
| 227 2: | |
| 228 | |
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229 |
| 2 | 230 // Call platform specific hardware initialization |
| 231 bl hal_hardware_init | |
| 232 | |
| 233 // Run through static constructors | |
| 234 bl cyg_hal_invoke_constructors | |
| 235 | |
| 236 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 237 bl initialize_stub | |
| 238 #endif | |
| 239 | |
| 240 // This starts up the eCos kernel | |
| 241 bl cyg_start | |
| 242 _start_hang: | |
| 243 b _start_hang | |
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244 .code 32 |
| 2 | 245 |
| 246 init_done: | |
| 247 .long 0xDEADB00B | |
| 248 | |
| 249 // | |
| 250 // Exception handlers | |
| 251 // Assmumption: get here from a Supervisor context [mode] | |
| 252 // | |
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253 .code 32 |
| 2 | 254 undefined_instruction: |
| 255 ldr sp,.__undef_exception_stack // get good stack | |
| 256 sub lr,lr,#4 // PC at time of interrupt | |
| 257 stmfd sp!,{r0,fp,ip,lr} | |
| 258 mrs r0,spsr | |
| 259 stmfd sp!,{r0} | |
| 260 mov ip,sp // save SP which will vanish with | |
| 261 // mode switch | |
| 262 mrs r0,cpsr // switch to Supervisor Mode | |
| 263 bic r0,r0,#CPSR_MODE_BITS | |
| 264 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 265 msr cpsr,r0 // sp,lr are now old values | |
| 266 mov fp,sp | |
| 267 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 268 ldr sp,.__GDB_stack | |
| 269 cmp fp,sp // already on GDB stack? | |
| 270 bhi 10f | |
| 271 ldr r0,.__GDB_stack_base | |
| 272 cmp fp,r0 | |
| 273 bls 10f // no - switch to GDB stack | |
| 274 // (already in sp) | |
| 275 mov sp,fp // yes - no switch | |
| 276 10: | |
| 277 #endif | |
| 278 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 279 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 280 ldmfd ip,{r0-r4} // saved registers | |
| 281 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 282 str r1,[sp,#armreg_r0] // saved R0 | |
| 283 str r2,[sp,#armreg_fp] // saved FP | |
| 284 str r3,[sp,#armreg_ip] // saved IP | |
| 285 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 286 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 287 add r0,ip,#ARMREG_SIZE | |
| 288 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 289 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 290 mov r0,sp | |
| 291 bl undefined_instruction | |
| 292 #endif | |
| 293 mov v1,#CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION | |
| 294 b call_exception_handler | |
| 295 | |
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296 .code 32 |
| 2 | 297 software_interrupt: |
| 298 ldr sp,.__startup_stack // get good stack | |
| 299 sub lr,lr,#4 // PC at time of interrupt | |
| 300 stmfd sp!,{r0,ip,lr} | |
| 301 mrs r0,spsr | |
| 302 stmfd sp!,{r0} | |
| 303 mov ip,sp // save SP which will vanish with | |
| 304 // mode switch | |
| 305 mrs r0,cpsr // switch to Supervisor Mode | |
| 306 bic r0,r0,#CPSR_MODE_BITS | |
| 307 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 308 msr cpsr,r0 // sp,lr are now old values | |
| 309 mov ip,sp | |
| 310 ldr sp,.__startup_stack // get good stack | |
| 311 sub sp,sp,#ARMREG_SIZE+16 // make space for frame | |
| 312 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 313 ldmfd ip,{r0-r3} // saved registers | |
| 314 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 315 str r1,[sp,#armreg_r0] // saved R0 | |
| 316 str r2,[sp,#armreg_ip] // saved IP | |
| 317 str r3,[sp,#armreg_pc] // PC at time of interrupt | |
| 318 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 319 add r0,ip,#ARMREG_SIZE | |
| 320 str r0,[sp,#armreg_sp] // SP at time of interrupt | |
| 321 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 322 mov r0,sp | |
| 323 bl software_interrupt | |
| 324 #endif | |
| 325 mov v1,#CYGNUM_HAL_EXCEPTION_INTERRUPT | |
| 326 b call_exception_handler | |
| 327 | |
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328 .code 32 |
| 2 | 329 abort_prefetch: |
| 330 ldr sp,.__undef_exception_stack // get good stack | |
| 331 sub lr,lr,#4 // PC at time of interrupt | |
| 332 stmfd sp!,{r0,fp,ip,lr} | |
| 333 mrs r0,spsr | |
| 334 stmfd sp!,{r0} | |
| 335 mov ip,sp // save SP which will vanish with | |
| 336 // mode switch | |
| 337 mrs r0,cpsr // switch to Supervisor Mode | |
| 338 bic r0,r0,#CPSR_MODE_BITS | |
| 339 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 340 msr cpsr,r0 // sp,lr are now old values | |
| 341 mov fp,sp | |
| 342 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 343 ldr sp,.__GDB_stack | |
| 344 cmp fp,sp // already on GDB stack? | |
| 345 bhi 10f | |
| 346 ldr r0,.__GDB_stack_base | |
| 347 cmp fp,r0 | |
| 348 bls 10f // no - switch to GDB stack | |
| 349 // (already in sp) | |
| 350 mov sp,fp // yes - no switch | |
| 351 10: | |
| 352 #endif | |
| 353 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 354 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 355 ldmfd ip,{r0-r4} // saved registers | |
| 356 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 357 str r1,[sp,#armreg_r0] // saved R0 | |
| 358 str r2,[sp,#armreg_fp] // saved FP | |
| 359 str r3,[sp,#armreg_ip] // saved IP | |
| 360 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 361 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 362 add r0,ip,#ARMREG_SIZE | |
| 363 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 364 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 365 mov r0,sp | |
| 366 bl abort_prefetch | |
| 367 #endif | |
| 368 mov v1,#CYGNUM_HAL_EXCEPTION_CODE_ACCESS | |
| 369 b call_exception_handler | |
| 370 | |
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371 .code 32 |
| 2 | 372 abort_data: |
| 373 ldr sp,.__undef_exception_stack // get good stack | |
| 374 sub lr,lr,#4 // PC at time of interrupt | |
| 375 stmfd sp!,{r0,fp,ip,lr} | |
| 376 mrs r0,spsr | |
| 377 stmfd sp!,{r0} | |
| 378 mov ip,sp // save SP which will vanish with | |
| 379 // mode switch | |
| 380 mrs r0,cpsr // switch to Supervisor Mode | |
| 381 bic r0,r0,#CPSR_MODE_BITS | |
| 382 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 383 msr cpsr,r0 // sp,lr are now old values | |
| 384 mov fp,sp | |
| 385 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 386 ldr sp,.__GDB_stack | |
| 387 cmp fp,sp // already on GDB stack? | |
| 388 bhi 10f | |
| 389 ldr r0,.__GDB_stack_base | |
| 390 cmp fp,r0 | |
| 391 bls 10f // no - switch to GDB stack | |
| 392 // (already in sp) | |
| 393 mov sp,fp // yes - no switch | |
| 394 10: | |
| 395 #endif | |
| 396 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 397 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 398 ldmfd ip,{r0-r4} // saved registers | |
| 399 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 400 str r1,[sp,#armreg_r0] // saved R0 | |
| 401 str r2,[sp,#armreg_fp] // saved FP | |
| 402 str r3,[sp,#armreg_ip] // saved IP | |
| 403 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 404 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 405 add r0,ip,#ARMREG_SIZE | |
| 406 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 407 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 408 mov r0,sp | |
| 409 bl abort_data | |
| 410 #endif | |
| 411 mov v1,#CYGNUM_HAL_EXCEPTION_DATA_ACCESS | |
| 412 b call_exception_handler | |
| 413 | |
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414 .code 32 |
| 2 | 415 FIQ: |
| 416 ldr sp,.__startup_stack // get good stack | |
| 417 sub lr,lr,#4 // PC at time of interrupt | |
| 418 stmfd sp!,{r0,ip,lr} | |
| 419 mrs r0,spsr | |
| 420 stmfd sp!,{r0} | |
| 421 mov ip,sp // save SP which will vanish with | |
| 422 // mode switch | |
| 423 mrs r0,cpsr // switch to Supervisor Mode | |
| 424 bic r0,r0,#CPSR_MODE_BITS | |
| 425 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 426 msr cpsr,r0 // sp,lr are now old values | |
| 427 mov ip,sp | |
| 428 ldr sp,.__startup_stack // get good stack | |
| 429 sub sp,sp,#ARMREG_SIZE+16 // make space for frame | |
| 430 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 431 ldmfd ip,{r0-r3} // saved registers | |
| 432 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 433 str r1,[sp,#armreg_r0] // saved R0 | |
| 434 str r2,[sp,#armreg_ip] // saved IP | |
| 435 str r3,[sp,#armreg_pc] // PC at time of interrupt | |
| 436 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 437 add r0,ip,#ARMREG_SIZE | |
| 438 str r0,[sp,#armreg_sp] // SP at time of interrupt | |
| 439 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 440 mov r0,sp | |
| 441 bl FIQ | |
| 442 #endif | |
| 443 mov v1,#CYGNUM_HAL_EXCEPTION_FIQ | |
| 444 b call_exception_handler | |
| 445 | |
| 446 // | |
| 447 // Dispatch an exception handler. | |
| 448 | |
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449 .code 32 |
| 2 | 450 call_exception_handler: |
| 451 str v1,[sp,#armreg_vector] | |
| 452 mov r0,sp | |
| 453 bl exception_handler | |
| 454 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 455 mov r0,sp | |
| 456 bl exception_handler_returned | |
| 457 #endif | |
| 458 | |
| 459 // Restore [interrupted] context | |
| 460 mov ip,sp // get stack pointer | |
| 461 | |
| 462 ldr lr,[ip,#armreg_lr] | |
| 463 ldr sp,[sp,#armreg_sp] | |
| 464 | |
| 465 mrs r0,cpsr // move back to IRQ mode | |
| 466 bic r0,r0,#CPSR_MODE_BITS | |
| 467 orr r0,r0,#CPSR_IRQ_MODE | |
| 468 msr cpsr,r0 | |
| 469 | |
| 470 mov sp,ip | |
| 471 ldr lr,[sp,#armreg_pc] | |
| 472 ldr r0,[sp,#armreg_cpsr] | |
| 473 ldr ip,[sp,#armreg_ip] | |
| 474 msr spsr,r0 | |
| 475 ldmfd sp,{r0-r10,fp} | |
| 476 | |
| 477 movs pc,lr // restore PC from LR, CPSR from SPSR | |
| 478 | |
| 479 // Handle device interrupts | |
| 480 // This is slightly more complicated than the other exception handlers because | |
| 481 // it needs to interface with the kernel (if present). | |
| 482 | |
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483 .code 32 |
| 2 | 484 IRQ: |
| 485 // Note: I use this exception stack while saving the context because | |
| 486 // the current SP does not seem to be always valid in this CPU mode. | |
| 487 ldr sp,.__exception_stack // get good stack | |
| 488 sub lr,lr,#4 // PC at time of interrupt | |
| 489 stmfd sp!,{r0,fp,ip,lr} | |
| 490 mrs r0,spsr | |
| 491 stmfd sp!,{r0} | |
| 492 mov ip,sp // save SP which will vanish with | |
| 493 // mode switch | |
| 494 mrs r0,cpsr // switch to Supervisor Mode | |
| 495 bic r0,r0,#CPSR_MODE_BITS | |
| 496 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 497 msr cpsr,r0 // sp,lr are now old values | |
| 498 mov fp,sp // save old SP | |
| 499 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 500 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 501 ldmfd ip,{r0-r4} // saved registers | |
| 502 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 503 str r1,[sp,#armreg_r0] // saved R0 | |
| 504 str r2,[sp,#armreg_fp] // saved FP | |
| 505 str r3,[sp,#armreg_ip] // saved IP | |
| 506 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 507 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 508 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 509 mov v6,sp // Save pointer to register frame | |
| 510 | |
| 511 // mov r0,sp | |
| 512 // bl _show_frame_in | |
| 513 | |
| 514 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 515 // Switch to interrupt stack | |
| 516 ldr r2,.irq_level // current number of nested interrupts | |
| 517 ldr r0,[r2] | |
| 518 add r1,r0,#1 | |
| 519 str r1,[r2] // if was zero, switch stacks | |
| 520 cmp r0,#0 | |
| 521 moveq r1,sp // save old stack pointer | |
| 522 ldreq sp,.__interrupt_stack | |
| 523 stmeqfd sp!,{r1} | |
| 524 10: | |
| 525 #endif | |
| 526 | |
| 527 // The entire CPU state is now stashed on the stack, | |
| 528 // increment the scheduler lock and handle the interrupt | |
| 529 | |
| 530 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 531 .extern cyg_scheduler_sched_lock | |
| 532 ldr r3,.cyg_scheduler_sched_lock | |
| 533 ldr r4,[r3] | |
| 534 add r4,r4,#1 | |
| 535 str r4,[r3] | |
| 536 #endif | |
| 537 | |
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538 // TEMP |
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539 mov r0,v6 |
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540 // TEMP |
| 2 | 541 bl hal_IRQ_handler // determine interrupt source |
| 542 mov v1,r0 // returned vector # | |
| 543 | |
| 544 #if defined(CYGPKG_KERNEL_INSTRUMENT) && \ | |
| 545 defined(CYGDBG_KERNEL_INSTRUMENT_INTR) | |
| 546 ldr r0,=RAISE_INTR // arg0 = type = INTR,RAISE | |
| 547 mov r1,v1 // arg1 = vector | |
| 548 mov r2,#0 // arg2 = 0 | |
| 549 bl cyg_instrument // call instrument function | |
| 550 #endif | |
| 551 | |
| 552 mov r0,v1 // vector # | |
| 553 ldr r1,.hal_interrupt_data | |
| 554 ldr r1,[r1,v1,lsl #2] // handler data | |
| 555 ldr r2,.hal_interrupt_handlers | |
| 556 ldr v3,[r2,v1,lsl #2] // handler (indexed by vector #) | |
| 557 mov r2,v6 // register frame | |
| 558 | |
| 559 mov lr,pc // invoke handler (call indirect | |
| 560 mov pc,v3 // thru v3) | |
| 561 | |
| 562 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 563 // If we are returning from the last nested interrupt, move back | |
| 564 // to the thread stack. interrupt_end() must be called on the | |
| 565 // thread stack since it potentially causes a context switch. | |
| 566 ldr r2,.irq_level | |
| 567 ldr r3,[r2] | |
| 568 subs r1,r3,#1 | |
| 569 str r1,[r2] | |
| 570 ldreq sp,[sp] // This should be the saved stack pointer | |
| 571 #endif | |
| 572 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 573 // The return value from the handler (in r0) will indicate whether a | |
| 574 // DSR is to be posted. Pass this together with a pointer to the | |
| 575 // interrupt object we have just used to the interrupt tidy up routine. | |
| 576 | |
| 577 ldr r1,.hal_interrupt_objects | |
| 578 ldr r1,[r1,v1,lsl #2] | |
| 579 bl interrupt_end // post any bottom layer handler | |
| 580 // threads and call scheduler | |
| 581 #endif | |
| 582 | |
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583 |
| 2 | 584 // mov r0,sp |
| 585 // bl show_frame_out | |
| 586 | |
| 587 mov ip,sp // get stack pointer | |
| 588 | |
| 589 ldr lr,[ip,#armreg_lr] | |
| 590 ldr sp,[sp,#armreg_sp] | |
| 591 | |
| 592 mrs r0,cpsr // move back to IRQ mode | |
| 593 bic r0,r0,#CPSR_MODE_BITS | |
| 594 orr r0,r0,#CPSR_IRQ_MODE | |
| 595 msr cpsr,r0 | |
| 596 | |
| 597 mov sp,ip | |
| 598 ldr lr,[sp,#armreg_pc] | |
| 599 ldr r0,[sp,#armreg_cpsr] | |
| 600 ldr ip,[sp,#armreg_ip] | |
| 601 msr spsr,r0 | |
| 602 ldmfd sp,{r0-r10,fp} | |
| 603 movs pc,lr // restore PC from LR, CPSR from SPSR | |
| 604 | |
| 605 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 606 // Execute pending DSRs the interrupt stack | |
| 607 // Note: this can only be called from code running on a thread stack | |
| 608 .global hal_interrupt_stack_call_pending_DSRs | |
| 609 hal_interrupt_stack_call_pending_DSRs: | |
| 610 stmfd sp!,{r4,r5,lr} | |
| 611 // Disable interrupts | |
| 612 mrs r4,cpsr // disable IRQ's | |
| 613 orr r2,r4,#CPSR_IRQ_DISABLE | |
| 614 bic r5,r4,#CPSR_IRQ_DISABLE | |
| 615 msr cpsr,r2 | |
| 616 // Switch to interrupt stack | |
| 617 mov r3,sp // save old stack pointer | |
| 618 ldr sp,.__interrupt_stack | |
| 619 stmfd sp!,{r3} // stored at top of interrupt stack | |
| 620 ldr r2,.irq_level // current number of nested interrupts | |
| 621 ldr r3,[r2] | |
| 622 add r3,r3,#1 // bump nesting level | |
| 623 str r3,[r2] | |
| 624 msr cpsr,r5 // enable interrupts | |
| 625 | |
| 626 bl cyg_interrupt_call_pending_DSRs | |
| 627 | |
| 628 // Disable interrupts | |
| 629 mrs r1,cpsr // disable IRQ's | |
| 630 orr r2,r1,#CPSR_IRQ_DISABLE | |
| 631 msr cpsr,r2 | |
| 632 | |
| 633 // Move back to the thread stack. | |
| 634 ldr r2,.irq_level | |
| 635 ldr r3,[r2] | |
| 636 sub r3,r3,#1 // decrement nesting level | |
| 637 str r3,[r2] | |
| 638 ldr sp,[sp] // This should be the saved stack pointer | |
| 639 msr cpsr,r4 // restore interrupts to original state | |
| 640 | |
| 641 ldmfd sp!,{r4,r5,pc} // return | |
| 642 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
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643 |
| 2 | 644 |
| 645 // Dummy functions | |
| 646 | |
| 647 .global __gccmain | |
| 648 __gccmain: | |
| 649 mov pc,lr | |
| 650 | |
| 651 .global _psr | |
| 652 _psr: | |
| 653 mrs r0,cpsr | |
| 654 mov pc,lr | |
| 655 | |
| 656 .global _sp | |
| 657 _sp: | |
| 658 mov r0,sp | |
| 659 mov pc,lr | |
| 660 | |
| 661 | |
| 662 // | |
| 663 // Pointers to various objects. | |
| 664 // | |
| 665 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 666 PTR(__GDB_stack_base) | |
| 667 PTR(__GDB_stack) | |
| 668 #endif | |
| 669 PTR(__startup_stack) | |
| 670 PTR(__exception_stack) | |
| 671 PTR(__undef_exception_stack) | |
| 672 PTR(__bss_start) | |
| 673 PTR(__bss_end) | |
| 674 PTR(_end) | |
| 675 PTR(__rom_data_start) | |
| 676 PTR(__ram_data_start) | |
| 677 PTR(__ram_data_end) | |
| 678 PTR(hal_interrupt_handlers) | |
| 679 PTR(hal_interrupt_data) | |
| 680 PTR(hal_interrupt_objects) | |
| 681 PTR(__exception_handlers) | |
| 682 PTR(init_flag) | |
| 683 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 684 PTR(cyg_scheduler_sched_lock) | |
| 685 #endif | |
| 686 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 687 PTR(irq_level) | |
| 688 PTR(__interrupt_stack) | |
| 689 #endif | |
| 690 | |
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691 // |
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692 // Identification - useful to find out when a system was configured |
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693 _eCos_id: |
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694 .asciz "eCos v1.2.1: " __DATE__ |
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695 |
| 2 | 696 |
| 697 // ------------------------------------------------------------------------- | |
| 698 // Interrupt vector tables. | |
| 699 // These tables contain the isr, data and object pointers used to deliver | |
| 700 // interrupts to user code. | |
| 701 | |
| 702 .data | |
| 703 | |
| 704 init_flag: | |
| 705 .long 0 | |
| 706 | |
| 707 .extern hal_default_isr | |
| 708 | |
| 709 .globl hal_vsr_table | |
| 710 hal_vsr_table: | |
| 711 .rept CYGNUM_HAL_VSR_COUNT | |
| 712 .long 0 // hal_default_isr | |
| 713 .endr | |
| 714 | |
| 715 .globl hal_interrupt_handlers | |
| 716 hal_interrupt_handlers: | |
| 717 .rept CYGNUM_HAL_ISR_COUNT | |
| 718 .long hal_default_isr | |
| 719 .endr | |
| 720 | |
| 721 .globl hal_interrupt_data | |
| 722 hal_interrupt_data: | |
| 723 .rept CYGNUM_HAL_ISR_COUNT | |
| 724 .long 0 | |
| 725 .endr | |
| 726 | |
| 727 .globl hal_interrupt_objects | |
| 728 hal_interrupt_objects: | |
| 729 .rept CYGNUM_HAL_ISR_COUNT | |
| 730 .long 0 | |
| 731 .endr | |
| 732 | |
| 733 // ------------------------------------------------------------------------- | |
| 734 // Temporary interrupt stack | |
| 735 | |
| 736 .section ".bss" | |
| 737 | |
| 738 // Small stacks, only used for saving information between CPU modes | |
| 739 __exception_stack_base: | |
| 740 .rept 32 | |
| 741 .long 0 | |
| 742 .endr | |
| 743 __exception_stack: | |
| 744 .rept 32 | |
| 745 .long 0 | |
| 746 .endr | |
| 747 __undef_exception_stack: | |
| 748 | |
| 749 // Runtime stack used during all interrupt processing | |
| 750 #ifndef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 751 #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096 | |
| 752 #endif | |
| 753 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 754 .balign 16 | |
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755 .global cyg_interrupt_stack_base |
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756 cyg_interrupt_stack_base: |
| 2 | 757 __interrupt_stack_base: |
| 758 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 759 .byte 0 | |
| 760 .endr | |
| 761 .balign 16 | |
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762 .global cyg_interrupt_stack |
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763 cyg_interrupt_stack: |
| 2 | 764 __interrupt_stack: |
| 765 irq_level: | |
| 766 .long 0 | |
| 767 #endif | |
| 768 | |
| 769 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 770 .balign 16 | |
| 771 __GDB_stack_base: | |
| 772 .rept 0x400 | |
| 773 .byte 0 | |
| 774 .endr | |
| 775 __GDB_stack: | |
| 776 #endif | |
| 777 .balign 16 | |
| 778 __startup_stack_base: | |
| 779 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 780 .rept 512 | |
| 781 #else | |
| 782 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 783 #endif | |
| 784 .byte 0 | |
| 785 .endr | |
| 786 .balign 16 | |
| 787 __startup_stack: | |
| 788 | |
| 789 // -------------------------------------------------------------------------- | |
| 790 // end of vectors.S |