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annotate packages/hal/mips/arch/current/include/hal_intr.h @ 124:0ec04793409a ecos-sw-2000-09-11

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Merge from eCos master repository on 2000-09-11-03:00:13-BST
author jlarmour
date Mon, 11 Sep 2000 02:42:46 +0000
parents 02ea4320376c
children 518f42066aba
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1 #ifndef CYGONCE_HAL_HAL_INTR_H
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2 #define CYGONCE_HAL_HAL_INTR_H
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3
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4 //==========================================================================
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5 //
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6 // hal_intr.h
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7 //
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8 // HAL Interrupt and clock support
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9 //
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10 //==========================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //==========================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): nickg
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38 // Contributors: nickg, jskov,
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39 // gthomas, jlarmour
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40 // Date: 1999-02-16
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41 // Purpose: Define Interrupt support
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42 // Description: The macros defined here provide the HAL APIs for handling
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43 // interrupts and the clock.
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44 //
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45 // Usage:
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46 // #include <cyg/hal/hal_intr.h>
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47 // ...
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48 //
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49 //
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50 //####DESCRIPTIONEND####
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51 //
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52 //==========================================================================
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53
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54 #include <pkgconf/hal.h>
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55
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56 #include <cyg/infra/cyg_type.h>
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57 #include <cyg/hal/hal_io.h>
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58
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59 #include <cyg/hal/var_intr.h>
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60
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61 //--------------------------------------------------------------------------
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62 // MIPS vectors.
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63
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64 // These are the exception codes presented in the Cause register and
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65 // correspond to VSRs. These values are the ones to use for HAL_VSR_GET/SET
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66
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67 // External interrupt
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68 #define CYGNUM_HAL_VECTOR_INTERRUPT 0
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69 // TLB modification exception
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70 #define CYGNUM_HAL_VECTOR_TLB_MOD 1
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71 // TLB miss (Load or IFetch)
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72 #define CYGNUM_HAL_VECTOR_TLB_LOAD_REFILL 2
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73 // TLB miss (Store)
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74 #define CYGNUM_HAL_VECTOR_TLB_STORE_REFILL 3
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75 // Address error (Load or Ifetch)
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76 #define CYGNUM_HAL_VECTOR_LOAD_ADDRESS 4
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77 // Address error (store)
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78 #define CYGNUM_HAL_VECTOR_STORE_ADDRESS 5
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79 // Bus error (Ifetch)
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80 #define CYGNUM_HAL_VECTOR_IBE 6
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81 // Bus error (data load or store)
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82 #define CYGNUM_HAL_VECTOR_DBE 7
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83 // System call
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84 #define CYGNUM_HAL_VECTOR_SYSTEM_CALL 8
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85 // Break point
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86 #define CYGNUM_HAL_VECTOR_BREAKPOINT 9
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87 // Reserved instruction
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88 #define CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION 10
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89 // Coprocessor unusable
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90 #define CYGNUM_HAL_VECTOR_COPROCESSOR 11
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91 // Arithmetic overflow
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92 #define CYGNUM_HAL_VECTOR_OVERFLOW 12
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93 // Reserved
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94 #define CYGNUM_HAL_VECTOR_RESERVED_13 13
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95 // Division-by-zero [reserved vector]
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96 // This is caused by 'trap 0x7' which GCC puts in the code to check
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97 // for division by zero. The break_vsr_springboard in vectors.S is the
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98 // only caller of this vector.
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99 #define CYGNUM_HAL_VECTOR_DIV_BY_ZERO 14
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100 // Floating point exception
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101 #ifdef CYGHWR_HAL_MIPS_FPU
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102 #define CYGNUM_HAL_VECTOR_FPE 15
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103 #endif
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104
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105 #define CYGNUM_HAL_VSR_MIN 0
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106 #define CYGNUM_HAL_VSR_MAX 15
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107 #define CYGNUM_HAL_VSR_COUNT 16
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108
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109 // Exception vectors. These are the values used when passed out to an
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110 // external exception handler using cyg_hal_deliver_exception()
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111
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112 #define CYGNUM_HAL_EXCEPTION_DATA_TLBERROR_ACCESS CYGNUM_HAL_VECTOR_TLB_MOD
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113 #define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS \
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114 CYGNUM_HAL_VECTOR_TLB_LOAD_REFILL
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115 #define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_WRITE \
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116 CYGNUM_HAL_VECTOR_TLB_STORE_REFILL
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117 #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \
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118 CYGNUM_HAL_VECTOR_LOAD_ADDRESS
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119 #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_WRITE \
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120 CYGNUM_HAL_VECTOR_STORE_ADDRESS
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121 #define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_IBE
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122 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DBE
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123 #define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL CYGNUM_HAL_VECTOR_SYSTEM_CALL
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124 #define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP CYGNUM_HAL_VECTOR_BREAKPOINT
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125 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \
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126 CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION
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127 #define CYGNUM_HAL_EXCEPTION_COPROCESSOR CYGNUM_HAL_VECTOR_COPROCESSOR
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128 #define CYGNUM_HAL_EXCEPTION_OVERFLOW CYGNUM_HAL_VECTOR_OVERFLOW
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129 #define CYGNUM_HAL_EXCEPTION_DIV_BY_ZERO CYGNUM_HAL_VECTOR_DIV_BY_ZERO
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130 #define CYGNUM_HAL_EXCEPTION_FPU CYGNUM_HAL_VECTOR_FPE
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131
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132 #define CYGNUM_HAL_EXCEPTION_INTERRUPT CYGNUM_HAL_VECTOR_BREAKPOINT
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133
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134 // Min/Max exception numbers and how many there are
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135 #define CYGNUM_HAL_EXCEPTION_MIN 1
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136 #define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX
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137 #define CYGNUM_HAL_EXCEPTION_COUNT CYGNUM_HAL_VSR_MAX
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138
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139
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140 #ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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141
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142 // the default for all MIPS variants is to use the 6 bits
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143 // in the cause register.
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144
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145 #define CYGNUM_HAL_INTERRUPT_0 0
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146 #define CYGNUM_HAL_INTERRUPT_1 1
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147 #define CYGNUM_HAL_INTERRUPT_2 2
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148 #define CYGNUM_HAL_INTERRUPT_3 3
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149 #define CYGNUM_HAL_INTERRUPT_4 4
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150 #define CYGNUM_HAL_INTERRUPT_5 5
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151
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152 // Min/Max ISR numbers and how many there are
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153 #define CYGNUM_HAL_ISR_MIN 0
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154 #define CYGNUM_HAL_ISR_MAX 5
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155 #define CYGNUM_HAL_ISR_COUNT 6
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156
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157 // The vector used by the Real time clock. The default here is to use
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158 // interrupt 5, which is connected to the counter/comparator registers
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159 // in many MIPS variants.
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160
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161 #ifndef CYGNUM_HAL_INTERRUPT_RTC
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162 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_5
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163 #endif
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164
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165 #define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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166
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167 #endif
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168
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169 //--------------------------------------------------------------------------
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170 // Static data used by HAL
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171
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172 // ISR tables
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173 externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
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174 externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
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175 externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
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176
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177 // VSR table
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178 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_MAX+1];
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179
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180 //--------------------------------------------------------------------------
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181 // Default ISR
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182 // The #define is used to test whether this routine exists, and to allow
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183 // us to call it.
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184
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185 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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186
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187 #define HAL_DEFAULT_ISR hal_default_isr
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188
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189 //--------------------------------------------------------------------------
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190 // Interrupt state storage
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191
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192 typedef cyg_uint32 CYG_INTERRUPT_STATE;
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193
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194 //--------------------------------------------------------------------------
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195 // Interrupt control macros
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196 // Beware of nops in this code. They fill delay slots and avoid CP0 hazards
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197 // that might otherwise cause following code to run in the wrong state or
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198 // cause a resource conflict.
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199
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200 #define HAL_DISABLE_INTERRUPTS(_old_) \
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201 { \
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202 asm volatile ( \
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203 "mfc0 $8,$12; nop;" \
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204 "move %0,$8;" \
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205 "and $8,$8,0XFFFFFFFE;" \
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206 "mtc0 $8,$12;" \
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207 "nop; nop; nop;" \
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208 "and %0,%0,0X1;" \
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209 : "=r"(_old_) \
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210 : \
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211 : "$8" \
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212 ); \
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213 }
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214
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215 #define HAL_ENABLE_INTERRUPTS() \
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216 { \
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217 asm volatile ( \
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218 "mfc0 $8,$12; nop;" \
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219 "or $8,$8,1;" \
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220 "mtc0 $8,$12;" \
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221 "nop; nop; nop;" \
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222 : \
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223 : \
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224 : "$8" \
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225 ); \
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226 }
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227
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228 #define HAL_RESTORE_INTERRUPTS(_old_) \
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229 { \
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230 asm volatile ( \
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231 "mfc0 $8,$12; nop;" \
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232 "and %0,%0,0x1;" \
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233 "or $8,$8,%0;" \
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234 "mtc0 $8,$12;" \
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235 "nop; nop; nop;" \
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236 : \
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237 : "r"(_old_) \
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238 : "$8" \
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239 ); \
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240 }
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241
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242 #define HAL_QUERY_INTERRUPTS( _state_ ) \
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243 { \
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244 asm volatile ( \
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245 "mfc0 %0,$12; nop;" \
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246 "and %0,%0,0x1;" \
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247 : "=r"(_state_) \
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248 : \
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249 : "$8" \
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250 ); \
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251 }
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252
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253 //--------------------------------------------------------------------------
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254 // Routine to execute DSRs using separate interrupt stack
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255
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256 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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257 externC void hal_interrupt_stack_call_pending_DSRs(void);
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258 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
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259 hal_interrupt_stack_call_pending_DSRs()
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260
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261 // these are offered solely for stack usage testing
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262 // if they are not defined, then there is no interrupt stack.
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263 #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
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264 #define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
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265 // use them to declare these extern however you want:
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266 // extern char HAL_INTERRUPT_STACK_BASE[];
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267 // extern char HAL_INTERRUPT_STACK_TOP[];
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268 // is recommended
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269 #endif
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270
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271 //--------------------------------------------------------------------------
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272 // Vector translation.
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273 // For chained interrupts we only have a single vector though which all
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274 // are passed. For unchained interrupts we have a vector per interrupt.
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275
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276 #ifndef HAL_TRANSLATE_VECTOR
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277
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278 #if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
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279
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280 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0
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281
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282 #else
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283
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284 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_)
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285
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286 #endif
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287
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288 #endif
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289
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290 //--------------------------------------------------------------------------
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291 // Interrupt and VSR attachment macros
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292
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293 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
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294 CYG_MACRO_START \
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295 cyg_uint32 _index_; \
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296 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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297 \
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298 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
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299 (_state_) = 0; \
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300 else \
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301 (_state_) = 1; \
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302 CYG_MACRO_END
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303
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304 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
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305 { \
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306 cyg_uint32 _index_; \
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307 HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \
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308 \
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309 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
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310 { \
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311 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
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312 hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \
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313 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
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314 } \
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315 }
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316
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317 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
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318 { \
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319 cyg_uint32 _index_; \
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320 HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \
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321 \
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322 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
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323 { \
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324 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \
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325 hal_interrupt_data[_index_] = 0; \
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326 hal_interrupt_objects[_index_] = 0; \
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327 } \
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328 }
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329
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330 #define HAL_VSR_GET( _vector_, _pvsr_ ) \
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331 *(_pvsr_) = (void (*)())hal_vsr_table[_vector_];
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332
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333
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334 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) CYG_MACRO_START \
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335 if( _poldvsr_ != NULL) \
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336 *(CYG_ADDRESS *)_poldvsr_ = (CYG_ADDRESS)hal_vsr_table[_vector_]; \
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337 hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
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338 CYG_MACRO_END
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339
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340 // This is an ugly name, but what it means is: grab the VSR back to eCos
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341 // internal handling, or if you like, the default handler. But if
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342 // cooperating with GDB and CygMon, the default behaviour is to pass most
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343 // exceptions to CygMon. This macro undoes that so that eCos handles the
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344 // exception. So use it with care.
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345
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346 externC void __default_exception_vsr(void);
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347 externC void __default_interrupt_vsr(void);
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348 externC void __break_vsr_springboard(void);
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349
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350 #define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START \
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351 HAL_VSR_SET( _vector_, _vector_ == CYGNUM_HAL_VECTOR_INTERRUPT \
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352 ? (CYG_ADDRESS)__default_interrupt_vsr \
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353 : _vector_ == CYGNUM_HAL_VECTOR_BREAKPOINT \
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354 ? (CYG_ADDRESS)__break_vsr_springboard \
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355 : (CYG_ADDRESS)__default_exception_vsr, \
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356 _poldvsr_ ); \
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357 CYG_MACRO_END
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358
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359 //--------------------------------------------------------------------------
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360 // Interrupt controller access
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361 // The default code here simply uses the fields present in the CP0 status
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362 // and cause registers to implement this functionality.
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363 // Beware of nops in this code. They fill delay slots and avoid CP0 hazards
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364 // that might otherwise cause following code to run in the wrong state or
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365 // cause a resource conflict.
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366
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367 #ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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368
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369 #define HAL_INTERRUPT_MASK( _vector_ ) \
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370 CYG_MACRO_START \
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371 asm volatile ( \
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372 "mfc0 $3,$12\n" \
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373 "la $2,0x00000400\n" \
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374 "sllv $2,$2,%0\n" \
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375 "nor $2,$2,$0\n" \
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376 "and $3,$3,$2\n" \
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377 "mtc0 $3,$12\n" \
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378 "nop; nop; nop\n" \
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379 : \
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380 : "r"(_vector_) \
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381 : "$2", "$3" \
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382 ); \
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383 CYG_MACRO_END
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384
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385 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
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386 CYG_MACRO_START \
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387 asm volatile ( \
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388 "mfc0 $3,$12\n" \
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389 "la $2,0x00000400\n" \
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390 "sllv $2,$2,%0\n" \
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391 "or $3,$3,$2\n" \
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392 "mtc0 $3,$12\n" \
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393 "nop; nop; nop\n" \
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394 : \
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395 : "r"(_vector_) \
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396 : "$2", "$3" \
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397 ); \
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398 CYG_MACRO_END
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399
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400 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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401 CYG_MACRO_START \
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402 asm volatile ( \
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403 "mfc0 $3,$13\n" \
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404 "la $2,0x00000400\n" \
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405 "sllv $2,$2,%0\n" \
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406 "nor $2,$2,$0\n" \
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407 "and $3,$3,$2\n" \
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408 "mtc0 $3,$13\n" \
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409 "nop; nop; nop\n" \
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410 : \
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411 : "r"(_vector_) \
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412 : "$2", "$3" \
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413 ); \
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414 CYG_MACRO_END
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415
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416 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
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417
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418 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
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419
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420 #define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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421
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422 #endif
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423
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424 //--------------------------------------------------------------------------
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425 // Clock control.
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426 // This code uses the count and compare registers that are present in many
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427 // MIPS variants.
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428 // Beware of nops in this code. They fill delay slots and avoid CP0 hazards
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429 // that might otherwise cause following code to run in the wrong state or
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430 // cause a resource conflict.
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431
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432 #ifndef CYGHWR_HAL_CLOCK_CONTROL_DEFINED
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433
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434 externC CYG_WORD32 cyg_hal_clock_period;
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435 #define CYGHWR_HAL_CLOCK_PERIOD_DEFINED
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436
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437 #define HAL_CLOCK_INITIALIZE( _period_ ) \
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438 CYG_MACRO_START \
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439 asm volatile ( \
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440 "mtc0 $0,$9\n" \
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441 "nop; nop; nop\n" \
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442 "mtc0 %0,$11\n" \
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443 "nop; nop; nop\n" \
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444 : \
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445 : "r"(_period_) \
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446 ); \
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447 cyg_hal_clock_period = _period_; \
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448 CYG_MACRO_END
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449
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450 #define HAL_CLOCK_RESET( _vector_, _period_ ) \
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451 CYG_MACRO_START \
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452 asm volatile ( \
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453 "mtc0 $0,$9\n" \
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454 "nop; nop; nop\n" \
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455 "mtc0 %0,$11\n" \
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456 "nop; nop; nop\n" \
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457 : \
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458 : "r"(_period_) \
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459 ); \
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460 CYG_MACRO_END
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461
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462 #define HAL_CLOCK_READ( _pvalue_ ) \
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463 CYG_MACRO_START \
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464 register CYG_WORD32 result; \
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465 asm volatile ( \
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466 "mfc0 %0,$9\n" \
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467 : "=r"(result) \
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468 ); \
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469 *(_pvalue_) = result; \
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470 CYG_MACRO_END
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471
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472 #define CYGHWR_HAL_CLOCK_CONTROL_DEFINED
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473
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474 #endif
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475
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476 #if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \
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477 !defined(HAL_CLOCK_LATENCY)
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478 #define HAL_CLOCK_LATENCY( _pvalue_ ) \
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479 CYG_MACRO_START \
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480 register CYG_WORD32 _cval_; \
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481 HAL_CLOCK_READ(&_cval_); \
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482 *(_pvalue_) = _cval_ - cyg_hal_clock_period; \
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483 CYG_MACRO_END
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484 #endif
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485
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486 //--------------------------------------------------------------------------
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487 #endif // ifndef CYGONCE_HAL_HAL_INTR_H
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488 // End of hal_intr.h