Mercurial > ecos-v3_0-branch
annotate packages/hal/arm/arm9/smdk2410/current/src/smdk2410_misc.c @ 2830:3caad2060bd3
Strip erroneous CR chars from text files in the eCos repository.
[ Bugzilla 1000694]
| author | jld |
|---|---|
| date | Wed, 25 Feb 2009 12:50:14 +0000 |
| parents | 74dbf4c3f2e1 |
| children |
| rev | line source |
|---|---|
| 1152 | 1 //========================================================================== |
| 2 // | |
| 3 // smdk2410_misc.c | |
| 4 // | |
| 5 // HAL misc board support code for ARM9/SMDK2410 | |
| 6 // | |
| 7 //========================================================================== | |
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8 // ####ECOSGPLCOPYRIGHTBEGIN#### |
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9 // ------------------------------------------- |
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10 // This file is part of eCos, the Embedded Configurable Operating System. |
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
| 1152 | 12 // |
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13 // eCos is free software; you can redistribute it and/or modify it under |
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14 // the terms of the GNU General Public License as published by the Free |
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15 // Software Foundation; either version 2 or (at your option) any later |
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16 // version. |
| 1152 | 17 // |
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT |
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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21 // for more details. |
| 1152 | 22 // |
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23 // You should have received a copy of the GNU General Public License |
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24 // along with eCos; if not, write to the Free Software Foundation, Inc., |
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
| 1152 | 26 // |
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27 // As a special exception, if other files instantiate templates or use |
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28 // macros or inline functions from this file, or you compile this file |
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29 // and link it with other works to produce a work based on this file, |
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30 // this file does not by itself cause the resulting work to be covered by |
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31 // the GNU General Public License. However the source code for this file |
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32 // must still be made available in accordance with section (3) of the GNU |
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33 // General Public License v2. |
| 1152 | 34 // |
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35 // This exception does not invalidate any other reasons why a work based |
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36 // on this file might be covered by the GNU General Public License. |
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37 // ------------------------------------------- |
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38 // ####ECOSGPLCOPYRIGHTEND#### |
| 1152 | 39 //========================================================================== |
| 40 //#####DESCRIPTIONBEGIN#### | |
| 41 // | |
| 42 // Author(s): michael anburaj <michaelanburaj@hotmail.com> | |
| 43 // Contributors: michael anburaj <michaelanburaj@hotmail.com> | |
| 44 // Date: 2003-08-01 | |
| 45 // Purpose: HAL board support | |
| 46 // Description: Implementations of HAL board interfaces | |
| 47 // | |
| 48 //####DESCRIPTIONEND#### | |
| 49 // | |
| 50 //========================================================================== | |
| 51 | |
| 52 #include <pkgconf/hal.h> | |
| 53 #include <pkgconf/system.h> | |
| 54 #include CYGBLD_HAL_PLATFORM_H | |
| 55 | |
| 56 #include <cyg/infra/cyg_type.h> // base types | |
| 57 #include <cyg/infra/cyg_trac.h> // tracing macros | |
| 58 #include <cyg/infra/cyg_ass.h> // assertion macros | |
| 59 | |
| 60 #include <cyg/hal/hal_io.h> // IO macros | |
| 61 #include <cyg/hal/hal_arch.h> // Register state info | |
| 62 #include <cyg/hal/hal_diag.h> | |
| 63 #include <cyg/hal/hal_intr.h> // Interrupt names | |
| 64 #include <cyg/hal/hal_cache.h> | |
| 65 #include <cyg/hal/s3c2410x.h> // Platform specifics | |
| 66 | |
| 67 #include <cyg/infra/diag.h> // diag_printf | |
| 68 | |
| 69 #include <string.h> // memset | |
| 70 | |
| 71 // ------------------------------------------------------------------------- | |
| 72 // MMU initialization: | |
| 73 // | |
| 74 // These structures are laid down in memory to define the translation | |
| 75 // table. | |
| 76 // | |
| 77 | |
| 78 // ARM Translation Table Base Bit Masks | |
| 79 #define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000 | |
| 80 | |
| 81 // ARM Domain Access Control Bit Masks | |
| 82 #define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2) | |
| 83 #define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2) | |
| 84 #define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2) | |
| 85 | |
| 86 struct ARM_MMU_FIRST_LEVEL_FAULT { | |
| 87 int id : 2; | |
| 88 int sbz : 30; | |
| 89 }; | |
| 90 #define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0 | |
| 91 | |
| 92 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE { | |
| 93 int id : 2; | |
| 94 int imp : 2; | |
| 95 int domain : 4; | |
| 96 int sbz : 1; | |
| 97 int base_address : 23; | |
| 98 }; | |
| 99 #define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1 | |
| 100 | |
| 101 struct ARM_MMU_FIRST_LEVEL_SECTION { | |
| 102 int id : 2; | |
| 103 int b : 1; | |
| 104 int c : 1; | |
| 105 int imp : 1; | |
| 106 int domain : 4; | |
| 107 int sbz0 : 1; | |
| 108 int ap : 2; | |
| 109 int sbz1 : 8; | |
| 110 int base_address : 12; | |
| 111 }; | |
| 112 #define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2 | |
| 113 | |
| 114 struct ARM_MMU_FIRST_LEVEL_RESERVED { | |
| 115 int id : 2; | |
| 116 int sbz : 30; | |
| 117 }; | |
| 118 #define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3 | |
| 119 | |
| 120 #define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \ | |
| 121 (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2)) | |
| 122 | |
| 123 #define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000 | |
| 124 | |
| 125 #define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \ | |
| 126 cacheable, bufferable, perm) \ | |
| 127 CYG_MACRO_START \ | |
| 128 register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \ | |
| 129 \ | |
| 130 desc.word = 0; \ | |
| 131 desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \ | |
| 132 desc.section.imp = 1; \ | |
| 133 desc.section.domain = 0; \ | |
| 134 desc.section.c = (cacheable); \ | |
| 135 desc.section.b = (bufferable); \ | |
| 136 desc.section.ap = (perm); \ | |
| 137 desc.section.base_address = (actual_base); \ | |
| 138 *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \ | |
| 139 = desc.word; \ | |
| 140 CYG_MACRO_END | |
| 141 | |
| 142 #define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \ | |
| 143 { int i; int j = abase; int k = vbase; \ | |
| 144 for (i = size; i > 0 ; i--,j++,k++) \ | |
| 145 { \ | |
| 146 ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \ | |
| 147 } \ | |
| 148 } | |
| 149 | |
| 150 union ARM_MMU_FIRST_LEVEL_DESCRIPTOR { | |
| 151 unsigned long word; | |
| 152 struct ARM_MMU_FIRST_LEVEL_FAULT fault; | |
| 153 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table; | |
| 154 struct ARM_MMU_FIRST_LEVEL_SECTION section; | |
| 155 struct ARM_MMU_FIRST_LEVEL_RESERVED reserved; | |
| 156 }; | |
| 157 | |
| 158 #define ARM_UNCACHEABLE 0 | |
| 159 #define ARM_CACHEABLE 1 | |
| 160 #define ARM_UNBUFFERABLE 0 | |
| 161 #define ARM_BUFFERABLE 1 | |
| 162 | |
| 163 #define ARM_ACCESS_PERM_NONE_NONE 0 | |
| 164 #define ARM_ACCESS_PERM_RO_NONE 0 | |
| 165 #define ARM_ACCESS_PERM_RO_RO 0 | |
| 166 #define ARM_ACCESS_PERM_RW_NONE 1 | |
| 167 #define ARM_ACCESS_PERM_RW_RO 2 | |
| 168 #define ARM_ACCESS_PERM_RW_RW 3 | |
| 169 | |
| 170 void | |
| 171 hal_mmu_init(void) | |
| 172 { | |
| 173 unsigned long ttb_base = SMDK2410_SDRAM_PHYS_BASE + 0x4000; | |
| 174 unsigned long i; | |
| 175 | |
| 176 // Set the TTB register | |
| 177 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); | |
| 178 | |
| 179 // Set the Domain Access Control Register | |
| 180 i = ARM_ACCESS_TYPE_MANAGER(0) | | |
| 181 ARM_ACCESS_TYPE_NO_ACCESS(1) | | |
| 182 ARM_ACCESS_TYPE_NO_ACCESS(2) | | |
| 183 ARM_ACCESS_TYPE_NO_ACCESS(3) | | |
| 184 ARM_ACCESS_TYPE_NO_ACCESS(4) | | |
| 185 ARM_ACCESS_TYPE_NO_ACCESS(5) | | |
| 186 ARM_ACCESS_TYPE_NO_ACCESS(6) | | |
| 187 ARM_ACCESS_TYPE_NO_ACCESS(7) | | |
| 188 ARM_ACCESS_TYPE_NO_ACCESS(8) | | |
| 189 ARM_ACCESS_TYPE_NO_ACCESS(9) | | |
| 190 ARM_ACCESS_TYPE_NO_ACCESS(10) | | |
| 191 ARM_ACCESS_TYPE_NO_ACCESS(11) | | |
| 192 ARM_ACCESS_TYPE_NO_ACCESS(12) | | |
| 193 ARM_ACCESS_TYPE_NO_ACCESS(13) | | |
| 194 ARM_ACCESS_TYPE_NO_ACCESS(14) | | |
| 195 ARM_ACCESS_TYPE_NO_ACCESS(15); | |
| 196 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); | |
| 197 | |
| 198 // First clear all TT entries - ie Set them to Faulting | |
| 199 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); | |
| 200 | |
| 201 // Memory layout after MMU is turned on | |
| 202 // | |
| 203 // SDRAM_BASE_ADDRESS: 0x00000000, 64M | |
| 204 // SRAM_BASE_ADDRESS: 0x40000000, 4K | |
| 205 // SFR_BASE_ADDRESS: 0x48000000, 512M | |
| 206 // FLASH_BASE_ADDRESS: 0x80000000, 2M | |
| 207 | |
| 208 // Actual Virtual Size Attributes Function | |
| 209 // Base Base MB cached? buffered? access permissions | |
| 210 // xxx00000 xxx00000 | |
| 211 X_ARM_MMU_SECTION(0x000, 0x800, 2, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // Flash | |
| 212 X_ARM_MMU_SECTION(0x300, 0x000, 64, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); // SDRAM | |
| 213 X_ARM_MMU_SECTION(0x400, 0x400, 1, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); // SRAM | |
| 214 X_ARM_MMU_SECTION(0x480, 0x480, 512, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // SFRs | |
| 215 X_ARM_MMU_SECTION(0x300, 0x300, 64, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // Raw SDRAM | |
| 216 } | |
| 217 | |
| 218 //---------------------------------------------------------------------------- | |
| 219 // Platform specific initialization | |
| 220 | |
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221 // This routine sets the default GPIO condition |
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222 static void port_init(void) |
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223 { |
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224 // Note: Follow the configuration order for setting the ports. |
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225 // 1) Set data register (GPnDAT) |
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226 // 2) Set control register (GPnCON) |
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227 // 3) Configure pull-up's (GPnUP) |
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228 |
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229 //*** PORT A GROUP |
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230 //Ports : GPA22 GPA21 GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12 |
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231 //Signal : nFCE nRSTOUT nFRE nFWE ALE CLE nGCS5 nGCS4 nGCS3 nGCS2 nGCS1 |
| 1152 | 232 //Binary : 1 1 1 1 1 1 1 1 1 1 1 |
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233 //----------------------------------------------------------------------------------------- |
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234 //Ports : GPA11 GPA10 GPA9 GPA8 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 |
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235 //Signal : ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0 |
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236 //Binary : 1 1 1 1 1 1 1 1 1 1 1 1 |
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237 HAL_WRITE_UINT32(GPACON, 0x7fffff); |
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238 |
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239 //**** PORT B GROUP |
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240 //Ports : GPB10 GPB9 GPB8 GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0 |
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241 //Signal : nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nSS_KBD nDIS_OFF L3CLOCK L3DATA L3MODE nIrDATXDEN Keyboard |
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242 //Setting: INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT |
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243 //Binary : 00 01 00 01 00 01 01 01 01 01 01 |
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244 HAL_WRITE_UINT32(GPBCON, 0x044555); |
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245 HAL_WRITE_UINT32(GPBUP, 0x7ff); // The pull up function is disabled GPB[10:0] |
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246 |
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247 //*** PORT C GROUP |
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248 //Ports : GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8 GPC7 GPC6 GPC5 GPC4 GPC3 GPC2 GPC1 GPC0 |
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249 //Signal : VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 LCDVF2 LCDVF1 LCDVF0 VM VFRAME VLINE VCLK LEND |
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250 //Binary : 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 |
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251 HAL_WRITE_UINT32(GPCCON, 0xaaaaaaaa); |
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252 HAL_WRITE_UINT32(GPCUP, 0xffff); // The pull up function is disabled GPC[15:0] |
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253 |
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254 //*** PORT D GROUP |
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255 //Ports : GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0 |
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256 //Signal : VD23 VD22 VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 |
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257 //Binary : 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 |
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258 HAL_WRITE_UINT32(GPDCON, 0xaaaaaaaa); |
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259 HAL_WRITE_UINT32(GPDUP, 0xffff); // The pull up function is disabled GPD[15:0] |
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260 |
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261 //*** PORT E GROUP |
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262 //Ports : GPE15 GPE14 GPE13 GPE12 GPE11 GPE10 GPE9 GPE8 GPE7 GPE6 GPE5 GPE4 |
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263 //Signal : IICSDA IICSCL SPICLK SPIMOSI SPIMISO SDDATA3 SDDATA2 SDDATA1 SDDATA0 SDCMD SDCLK I2SSDO |
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264 //Binary : 10 10 10 10 10 10 10 10 10 10 10 10 |
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265 //------------------------------------------------------------------------------------------------ |
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266 //Ports : GPE3 GPE2 GPE1 GPE0 |
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267 //Signal : I2SSDI CDCLK I2SSCLK I2SLRCK |
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268 //Binary : 10 10 10 10 |
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269 HAL_WRITE_UINT32(GPECON, 0xaaaaaaaa); |
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270 HAL_WRITE_UINT32(GPEUP, 0xffff); // The pull up function is disabled GPE[15:0] |
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271 |
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272 //*** PORT F GROUP |
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273 //Ports : GPF7 GPF6 GPF5 GPF4 GPF3 GPF2 GPF1 GPF0 |
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274 //Signal : nLED_8 nLED_4 nLED_2 nLED_1 nIRQ_PCMCIA EINT2 KBDINT EINT0 |
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275 //Setting: Output Output Output Output EINT3 EINT2 EINT1 EINT0 |
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276 //Binary : 01 01 01 01 10 10 10 10 |
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277 HAL_WRITE_UINT32(GPFCON, 0x55aa); |
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278 HAL_WRITE_UINT32(GPFUP, 0xff); // The pull up function is disabled GPF[7:0] |
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279 |
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280 //*** PORT G GROUP |
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281 //Ports : GPG15 GPG14 GPG13 GPG12 GPG11 GPG10 GPG9 GPG8 GPG7 GPG6 |
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282 //Signal : nYPON YMON nXPON XMON EINT19 DMAMODE1 DMAMODE0 DMASTART KBDSPICLK KBDSPIMOSI |
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283 //Setting: nYPON YMON nXPON XMON EINT19 Output Output Output SPICLK1 SPIMOSI1 |
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284 //Binary : 11 11 11 11 10 01 01 01 11 11 |
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285 //----------------------------------------------------------------------------------------- |
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286 //Ports : GPG5 GPG4 GPG3 GPG2 GPG1 GPG0 |
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287 //Signal : KBDSPIMISO LCD_PWREN EINT11 nSS_SPI IRQ_LAN IRQ_PCMCIA |
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288 //Setting: SPIMISO1 LCD_PWRDN EINT11 nSS0 EINT9 EINT8 |
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289 //Binary : 11 11 10 11 10 10 |
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290 HAL_WRITE_UINT32(GPGCON, 0xff95ffba); |
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291 HAL_WRITE_UINT32(GPGUP, 0xffff); // The pull up function is disabled GPG[15:0] |
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292 |
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293 //*** PORT H GROUP |
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294 //Ports : GPH10 GPH9 GPH8 GPH7 GPH6 GPH5 GPH4 GPH3 GPH2 GPH1 GPH0 |
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295 //Signal : CLKOUT1 CLKOUT0 UCLK nCTS1 nRTS1 RXD1 TXD1 RXD0 TXD0 nRTS0 nCTS0 |
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296 //Binary : 10 10 10 11 11 10 10 10 10 10 10 |
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297 HAL_WRITE_UINT32(GPHCON, 0x2afaaa); |
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298 HAL_WRITE_UINT32(GPHUP, 0x7ff); // The pull up function is disabled GPH[10:0] |
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299 |
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300 //External interrupts will be falling edge triggered. |
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301 HAL_WRITE_UINT32(EXTINT0, 0x22222222); // EINT[7:0] |
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302 HAL_WRITE_UINT32(EXTINT1, 0x22222222); // EINT[15:8] |
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303 HAL_WRITE_UINT32(EXTINT2, 0x22222222); // EINT[23:16] |
| 1152 | 304 } |
| 305 | |
| 306 void | |
| 307 plf_hardware_init(void) | |
| 308 { | |
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309 HAL_WRITE_UINT32(INTMOD, 0x0); //All=IRQ mode |
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310 HAL_WRITE_UINT32(INTMSK, BIT_ALLMSK); //All interrupt is masked. |
| 1152 | 311 HAL_WRITE_UINT32(INTSUBMSK, BIT_SUB_ALLMSK); //All sub-interrupt is masked. |
| 312 | |
| 313 port_init(); | |
| 314 | |
| 315 // Initialize real-time clock (for delays, etc, even if kernel doesn't use it) | |
| 316 hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD); | |
| 317 } | |
| 318 | |
| 319 // ------------------------------------------------------------------------- | |
| 320 // Use Timer4 for system clock | |
| 321 void | |
| 322 hal_clock_initialize(cyg_uint32 period) | |
| 323 { | |
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324 cyg_uint32 temp; |
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325 |
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326 // Configure the Prescaler1 |
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327 HAL_READ_UINT32(TCFG0, temp); |
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328 temp &= ~(0xff<<8); |
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329 temp |= (CYGNUM_HAL_ARM_SMDK2410_TIMER_PRESCALE<<8); |
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330 HAL_WRITE_UINT32(TCFG0, temp); |
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331 |
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332 // Configure the MUX to select the 1/2 divider |
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333 HAL_READ_UINT32(TCFG1, temp); |
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334 temp &= ~(0xf<<16); |
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335 temp |= (0x0<<16); |
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336 HAL_WRITE_UINT32(TCFG1, temp); |
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337 |
| 1152 | 338 // Set up the Timer4 for period |
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339 HAL_WRITE_UINT32(TCNTB4, period); |
| 1152 | 340 |
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341 // Start Timer4 |
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342 HAL_READ_UINT32(TCON, temp); |
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343 temp &= ~(0xf << 20); |
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344 HAL_WRITE_UINT32(TCON, (temp|(6<<20))); |
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345 HAL_WRITE_UINT32(TCON, (temp|(5<<20))); |
| 1152 | 346 |
| 347 // Unmask Timer4 interrupt, need not be done here | |
| 348 //HAL_INTERRUPT_CONFIGURE( CYGNUM_HAL_INTERRUPT_RTC, 1, 1 ); | |
| 349 //HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_RTC ); | |
| 350 } | |
| 351 | |
| 352 // This routine is called during a clock interrupt. | |
| 353 void | |
| 354 hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) | |
| 355 { | |
| 356 // Do nothing | |
| 357 } | |
| 358 | |
| 359 // Read the current value of the clock, returning the number of hardware | |
| 360 // "ticks" that have occurred (i.e. how far away the current value is from | |
| 361 // the start) | |
| 362 void | |
| 363 hal_clock_read(cyg_uint32 *pvalue) | |
| 364 { | |
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365 cyg_int32 clock_val; |
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366 |
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367 // Read Timer4's current value |
| 1152 | 368 HAL_READ_UINT32(TCNTO4, clock_val); |
| 369 | |
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370 *pvalue = CYGNUM_HAL_RTC_PERIOD - (clock_val & 0xFFFF); // Note: counter is only 16 bits |
| 1152 | 371 // and decreases |
| 372 } | |
| 373 | |
| 374 | |
| 375 // Delay for some number of micro-seconds | |
| 376 void | |
| 377 hal_delay_us(cyg_int32 usecs) | |
| 378 { | |
| 379 cyg_uint32 ticks = 0; | |
| 380 // Divide by 1000000 in two steps to preserve precision. | |
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381 cyg_uint32 wait_ticks = (((PCLK/100000)*usecs)/CYGNUM_HAL_ARM_SMDK2410_TIMER_PRESCALE/2/10); |
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382 cyg_int32 val, prev, diff; |
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383 |
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384 // Read Timer4's current value |
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385 HAL_READ_UINT32(TCNTO4, prev); |
| 1152 | 386 prev &= 0xFFFF; |
| 387 | |
| 388 while (ticks < wait_ticks) { | |
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389 while (true) { |
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390 // Read Timer4's current value |
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391 HAL_READ_UINT32(TCNTO4, val); |
| 1152 | 392 val &= 0xFFFF; |
| 393 | |
| 394 diff = prev - val; | |
| 395 if (diff != 0) { | |
| 396 if(diff < 0) | |
| 397 diff += (CYGNUM_HAL_RTC_PERIOD+1); | |
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398 |
| 1152 | 399 break; // atleast 1 tick has passed |
| 400 } | |
| 401 } | |
| 402 prev = val; | |
| 403 ticks += diff; | |
| 404 } | |
| 405 } | |
| 406 | |
| 407 // ------------------------------------------------------------------------- | |
| 408 | |
| 409 // This routine is called to respond to a hardware interrupt (IRQ). It | |
| 410 // should interrogate the hardware and return the IRQ vector number. | |
| 411 int | |
| 412 hal_IRQ_handler(void) | |
| 413 { | |
| 414 cyg_uint32 ior; | |
| 415 | |
| 416 HAL_READ_UINT32(INTOFFSET, ior); | |
| 417 return (int)ior; | |
| 418 } | |
| 419 | |
| 420 //---------------------------------------------------------------------------- | |
| 421 // Interrupt control | |
| 422 | |
| 423 void | |
| 424 hal_interrupt_mask(int vector) | |
| 425 { | |
| 426 cyg_uint32 imr; | |
| 427 | |
| 428 CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && | |
| 429 vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); | |
| 430 | |
| 431 HAL_READ_UINT32(INTMSK, imr); | |
| 432 imr |= (1<<vector); | |
| 433 HAL_WRITE_UINT32(INTMSK, imr); | |
| 434 } | |
| 435 | |
| 436 void | |
| 437 hal_interrupt_unmask(int vector) | |
| 438 { | |
| 439 cyg_uint32 imr; | |
| 440 | |
| 441 CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && | |
| 442 vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); | |
| 443 | |
| 444 HAL_READ_UINT32(INTMSK, imr); | |
| 445 imr &= ~(1<<vector); | |
| 446 HAL_WRITE_UINT32(INTMSK, imr); | |
| 447 } | |
| 448 | |
| 449 void | |
| 450 hal_interrupt_acknowledge(int vector) | |
| 451 { | |
| 452 cyg_uint32 ipr; | |
| 453 | |
| 454 CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && | |
| 455 vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); | |
| 456 | |
| 457 HAL_WRITE_UINT32(SRCPND, (1<<vector)); | |
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458 HAL_READ_UINT32(INTPND, ipr); |
| 1152 | 459 HAL_WRITE_UINT32(INTPND, ipr); |
| 460 } | |
| 461 | |
| 462 void | |
| 463 hal_interrupt_configure(int vector, int level, int up) | |
| 464 { | |
| 465 CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && | |
| 466 vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); | |
| 467 } | |
| 468 | |
| 469 void hal_interrupt_set_level(int vector, int level) | |
| 470 { | |
| 471 CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && | |
| 472 vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); | |
| 473 } | |
| 474 | |
| 475 | |
| 476 //----------------------------------------------------------------------------- | |
| 477 // End of smdk2410_misc.c |
