Mercurial > ecos-v3_0-branch

annotate packages/devs/eth/cf/current/src/dp8390.h @ 126:518f42066aba ecos-sw-2000-09-19

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Merge from eCos master repository on 2000-09-19-06:25:26-BST
author jlarmour
date Tue, 19 Sep 2000 05:53:51 +0000
parents 6ed91473a1cd
children
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1 //==========================================================================
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2 //
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3 // dev/dp8390.h
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4 //
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5 // National Semiconductor ethernet chip
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //####BSDCOPYRIGHTBEGIN####
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32 //
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33 // -------------------------------------------
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34 //
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35 // Portions of this software may have been derived from OpenBSD or other sources,
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36 // and are covered by the appropriate copyright disclaimers included herein.
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37 //
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38 // -------------------------------------------
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39 //
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40 //####BSDCOPYRIGHTEND####
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41 //==========================================================================
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42 //#####DESCRIPTIONBEGIN####
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43 //
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44 // Author(s): gthomas
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45 // Contributors: gthomas
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46 // Date: 2000-07-07
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47 // Purpose:
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48 // Description:
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49 //
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50 //
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51 //####DESCRIPTIONEND####
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52 //
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53 //==========================================================================
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54
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55 typedef volatile union {
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56 union {
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57 struct {
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58 unsigned char cr;
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59 unsigned char clda0;
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60 unsigned char clda1;
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61 unsigned char bndry;
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62 unsigned char tsr;
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63 unsigned char ncr;
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64 unsigned char fifo;
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65 unsigned char isr;
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66 unsigned char crda0;
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67 unsigned char crda1;
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68 unsigned char _reserved[2];
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69 unsigned char rsr;
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70 unsigned char fer;
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71 unsigned char cer;
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72 unsigned char missed;
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73 unsigned char data;
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74 unsigned char _reserved2[14];
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75 unsigned char reset;
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76 } page0;
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77 struct {
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78 unsigned char cr;
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79 unsigned char par[6];
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80 unsigned char curp;
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81 unsigned char mar[8];
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82 } page1;
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83 struct {
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84 unsigned char cr;
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85 unsigned char pstart;
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86 unsigned char pstop;
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87 unsigned char rnpp;
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88 unsigned char tpsr;
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89 unsigned char lnpp;
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90 unsigned char ach;
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91 unsigned char acl;
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92 unsigned char _reserved[4];
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93 unsigned char rcr;
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94 unsigned char tcr;
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95 unsigned char dcr;
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96 unsigned char imr;
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97 } page2;
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98 unsigned char data;
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99 } r; // Read registers
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100 union {
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101 struct {
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102 unsigned char cr;
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103 unsigned char pstart;
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104 unsigned char pstop;
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105 unsigned char bndry;
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106 unsigned char tpsr;
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107 unsigned char tbcl;
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108 unsigned char tbch;
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109 unsigned char isr;
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110 unsigned char rsal;
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111 unsigned char rsah;
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112 unsigned char rbcl;
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113 unsigned char rbch;
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114 unsigned char rcr;
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115 unsigned char tcr;
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116 unsigned char dcr;
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117 unsigned char imr;
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118 unsigned char data;
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119 unsigned char _reserved[14];
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120 unsigned char reset;
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121 } page0;
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122 struct {
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123 unsigned char cr;
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124 unsigned char par[6];
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125 unsigned char curp;
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126 unsigned char mar[8];
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127 } page1;
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128 struct {
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129 unsigned char cr;
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130 unsigned char clda0;
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131 unsigned char clda1;
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132 unsigned char rnpp;
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133 unsigned char tpsr;
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134 unsigned char lnpp;
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135 unsigned char ach;
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136 unsigned char acl;
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137 unsigned char _reserved[8];
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138 } page2;
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139 } w; // Write registers
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140 } dp8390_regs; // __attribute__ ((aligned(1), packed));
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141
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142 // Command register - common to all pages
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143
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144 #define DP8390_CR_STOP 0x01 // Stop: software reset
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145 #define DP8390_CR_START 0x02 // Start: initialize device
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146 #define DP8390_CR_TXPKT 0x04 // Transmit packet
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147 #define DP8390_CR_RDMA 0x08 // Read DMA (recv data from device)
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148 #define DP8390_CR_WDMA 0x10 // Write DMA (send data to device)
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149 #define DP8390_CR_SEND 0x18 // Send packet
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150 #define DP8390_CR_NODMA 0x20 // Remote (or no) DMA
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151 #define DP8390_CR_PAGE0 0x00 // Page select
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152 #define DP8390_CR_PAGE1 0x40
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153 #define DP8390_CR_PAGE2 0x80
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154 #define DP8390_CR_PAGEMSK 0x3F // Used to mask out page bits
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155
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156 // Data configuration register
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157
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158 #define DP8390_DCR_WTS 0x01 // 1=16 bit word transfers
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159 #define DP8390_DCR_BOS 0x02 // 1=Little Endian
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160 #define DP8390_DCR_LAS 0x04 // 1=Single 32 bit DMA mode
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161 #define DP8390_DCR_LS 0x08 // 1=normal mode, 0=loopback
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162 #define DP8390_DCR_ARM 0x10 // 0=no send command (program I/O)
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163 #define DP8390_DCR_FIFO_1 0x00 // FIFO threshold
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164 #define DP8390_DCR_FIFO_2 0x20
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165 #define DP8390_DCR_FIFO_4 0x40
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166 #define DP8390_DCR_FIFO_6 0x60
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167
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168 #define DP8390_DCR_INIT (DP8390_DCR_LS|DP8390_DCR_FIFO_4)
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169
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170 // Interrupt status register
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171
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172 #define DP8390_ISR_RxP 0x01 // Packet received
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173 #define DP8390_ISR_TxP 0x02 // Packet transmitted
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174 #define DP8390_ISR_RxE 0x04 // Receive error
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175 #define DP8390_ISR_TxE 0x08 // Transmit error
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176 #define DP8390_ISR_OFLW 0x10 // Receive overflow
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177 #define DP8390_ISR_CNT 0x20 // Tally counters need emptying
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178 #define DP8390_ISR_RDC 0x40 // Remote DMA complete
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179 #define DP8390_ISR_RESET 0x80 // Device has reset (shutdown, error)
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180
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181 // Interrupt mask register
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182
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183 #define DP8390_IMR_RxP 0x01 // Packet received
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184 #define DP8390_IMR_TxP 0x02 // Packet transmitted
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185 #define DP8390_IMR_RxE 0x04 // Receive error
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186 #define DP8390_IMR_TxE 0x08 // Transmit error
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187 #define DP8390_IMR_OFLW 0x10 // Receive overflow
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188 #define DP8390_IMR_CNT 0x20 // Tall counters need emptying
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189 #define DP8390_IMR_RDC 0x40 // Remote DMA complete
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190
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191 #define DP8390_IMR_All 0x3F // Everything but remote DMA
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192
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193 // Receiver control register
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194
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195 #define DP8390_RCR_SEP 0x01 // Save bad(error) packets
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196 #define DP8390_RCR_AR 0x02 // Accept runt packets
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197 #define DP8390_RCR_AB 0x04 // Accept broadcast packets
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198 #define DP8390_RCR_AM 0x08 // Accept multicast packets
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199 #define DP8390_RCR_PROM 0x10 // Promiscuous mode
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200 #define DP8390_RCR_MON 0x20 // Monitor mode - 1=accept no packets
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201
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202 // Receiver status register
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203
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204 #define DP8390_RSR_RxP 0x01 // Packet received
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205 #define DP8390_RSR_CRC 0x02 // CRC error
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206 #define DP8390_RSR_FRAME 0x04 // Framing error
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207 #define DP8390_RSR_FO 0x08 // FIFO overrun
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208 #define DP8390_RSR_MISS 0x10 // Missed packet
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209 #define DP8390_RSR_PHY 0x20 // 0=pad match, 1=mad match
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210 #define DP8390_RSR_DIS 0x40 // Receiver disabled
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211 #define DP8390_RSR_DFR 0x80 // Receiver processing deferred
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212
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213 // Transmitter control register
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214
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215 #define DP8390_TCR_NOCRC 0x01 // 1=inhibit CRC
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216 #define DP8390_TCR_NORMAL 0x00 // Normal transmitter operation
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217 #define DP8390_TCR_LOCAL 0x02 // Internal NIC loopback
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218 #define DP8390_TCR_INLOOP 0x04 // Full internal loopback
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219 #define DP8390_TCR_OUTLOOP 0x08 // External loopback
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220 #define DP8390_TCR_ATD 0x10 // Auto transmit disable
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221 #define DP8390_TCR_OFFSET 0x20 // Collision offset adjust
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222
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223 // Transmit status register
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224
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225 #define DP8390_TSR_TxP 0x01 // Packet transmitted
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226 #define DP8390_TSR_COL 0x04 // Collision (at least one)
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227 #define DP8390_TSR_ABT 0x08 // Aborted because of too many collisions
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228 #define DP8390_TSR_CRS 0x10 // Lost carrier
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229 #define DP8390_TSR_FU 0x20 // FIFO underrun
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230 #define DP8390_TSR_CDH 0x40 // Collision Detect Heartbeat
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231 #define DP8390_TSR_OWC 0x80 // Collision outside normal window
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232
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233 // Page (buffer) allocation
126
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234 #define DP8390_TX_BUF1 0x40
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235 #define DP8390_TX_BUF2 0x48
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236 #define DP8390_RX_START 0x50
115
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237 #define DP8390_RX_STOP 0x80
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238
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239 #define IEEE_8023_MAX_FRAME 1518 // Largest possible ethernet frame
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240 #define IEEE_8023_MIN_FRAME 64 // Smallest possible ethernet frame
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241
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242 #define SC_LPE_MANUF 0x0104
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243