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annotate packages/devs/serial/mips/vrc4373/current/src/vrc4373_serial.c @ 82:6736c52df507 ecos-sw-2000-04-14

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Merge from eCos master repository on 2000-04-14-13:35:46-BST
author jlarmour
date Tue, 18 Apr 2000 21:51:55 +0000
parents
children 6ed91473a1cd
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1 //==========================================================================
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2 //
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3 // io/serial/mips/vrc4373_serial.c
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4 //
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5 // Mips VRC4373 Serial I/O Interface Module (interrupt driven)
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): gthomas
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35 // Contributors: gthomas
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36 // Date: 1999-04-15
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37 // Purpose: VRC4373 Serial I/O module (interrupt driven version)
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38 // Description:
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39 //
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40 //####DESCRIPTIONEND####
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41 //
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42 //==========================================================================
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43
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44 #include <pkgconf/system.h>
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45 #include <pkgconf/io_serial.h>
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46 #include <pkgconf/io.h>
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47 #include <cyg/io/io.h>
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48 #include <cyg/hal/hal_intr.h>
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49 #include <cyg/io/devtab.h>
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50 #include <cyg/io/serial.h>
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51
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52 #ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373
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53
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54 #include "vrc4373_serial.h"
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55
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56 #if defined(CYGPKG_HAL_MIPS_LSBFIRST)
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57 #define VRC4373_SCC_BASE 0xC1000000
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58 #elif defined(CYGPKG_HAL_MIPS_MSBFIRST)
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59 #define VRC4373_SCC_BASE 0xC1000003
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60 #else
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61 #error MIPS endianness not defined by configuration
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62 #endif
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63
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64 #define VRC4373_SCC_INT CYGNUM_HAL_INTERRUPT_DUART
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65 #define SCC_CHANNEL_A 4
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66 #define SCC_CHANNEL_B 0
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67
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68 extern void diag_printf(const char *fmt, ...);
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69
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70 typedef struct vrc4373_serial_info {
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71 CYG_ADDRWORD base;
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72 unsigned char regs[16]; // Known register state (since hardware is write-only!)
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73 } vrc4373_serial_info;
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74
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75 static bool vrc4373_serial_init(struct cyg_devtab_entry *tab);
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76 static bool vrc4373_serial_putc(serial_channel *chan, unsigned char c);
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77 static Cyg_ErrNo vrc4373_serial_lookup(struct cyg_devtab_entry **tab,
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78 struct cyg_devtab_entry *sub_tab,
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79 const char *name);
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80 static unsigned char vrc4373_serial_getc(serial_channel *chan);
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81 static bool vrc4373_serial_set_config(serial_channel *chan, cyg_serial_info_t *config);
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82 static void vrc4373_serial_start_xmit(serial_channel *chan);
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83 static void vrc4373_serial_stop_xmit(serial_channel *chan);
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84
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85 static cyg_uint32 vrc4373_serial_ISR(cyg_vector_t vector, cyg_addrword_t data);
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86 static void vrc4373_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data);
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87
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88 static SERIAL_FUNS(vrc4373_serial_funs,
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89 vrc4373_serial_putc,
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90 vrc4373_serial_getc,
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91 vrc4373_serial_set_config,
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92 vrc4373_serial_start_xmit,
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93 vrc4373_serial_stop_xmit
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94 );
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95
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96 #ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL0
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97 static vrc4373_serial_info vrc4373_serial_info0 = {VRC4373_SCC_BASE+SCC_CHANNEL_A};
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98 #if CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BUFSIZE > 0
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99 static unsigned char vrc4373_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BUFSIZE];
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100 static unsigned char vrc4373_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BUFSIZE];
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101
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102 static SERIAL_CHANNEL_USING_INTERRUPTS(vrc4373_serial_channel0,
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103 vrc4373_serial_funs,
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104 vrc4373_serial_info0,
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105 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BAUD),
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106 CYG_SERIAL_STOP_DEFAULT,
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107 CYG_SERIAL_PARITY_DEFAULT,
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108 CYG_SERIAL_WORD_LENGTH_DEFAULT,
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109 CYG_SERIAL_FLAGS_DEFAULT,
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110 &vrc4373_serial_out_buf0[0], sizeof(vrc4373_serial_out_buf0),
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111 &vrc4373_serial_in_buf0[0], sizeof(vrc4373_serial_in_buf0)
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112 );
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113 #else
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114 static SERIAL_CHANNEL(vrc4373_serial_channel0,
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115 vrc4373_serial_funs,
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116 vrc4373_serial_info0,
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117 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BAUD),
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118 CYG_SERIAL_STOP_DEFAULT,
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119 CYG_SERIAL_PARITY_DEFAULT,
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120 CYG_SERIAL_WORD_LENGTH_DEFAULT,
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121 CYG_SERIAL_FLAGS_DEFAULT
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122 );
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123 #endif
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124
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125 DEVTAB_ENTRY(vrc4373_serial_io0,
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126 CYGDAT_IO_SERIAL_MIPS_VRC4373_SERIAL0_NAME,
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127 0, // Does not depend on a lower level interface
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128 &cyg_io_serial_devio,
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129 vrc4373_serial_init,
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130 vrc4373_serial_lookup, // Serial driver may need initializing
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131 &vrc4373_serial_channel0
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132 );
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133 #endif // CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL0
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134
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135 #ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL1
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136 static vrc4373_serial_info vrc4373_serial_info1 = {VRC4373_SCC_BASE+SCC_CHANNEL_B};
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137 #if CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BUFSIZE > 0
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138 static unsigned char vrc4373_serial_out_buf1[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BUFSIZE];
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139 static unsigned char vrc4373_serial_in_buf1[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BUFSIZE];
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140
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141 static SERIAL_CHANNEL_USING_INTERRUPTS(vrc4373_serial_channel1,
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142 vrc4373_serial_funs,
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143 vrc4373_serial_info1,
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144 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BAUD),
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145 CYG_SERIAL_STOP_DEFAULT,
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146 CYG_SERIAL_PARITY_DEFAULT,
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147 CYG_SERIAL_WORD_LENGTH_DEFAULT,
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148 CYG_SERIAL_FLAGS_DEFAULT,
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149 &vrc4373_serial_out_buf1[0], sizeof(vrc4373_serial_out_buf1),
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150 &vrc4373_serial_in_buf1[0], sizeof(vrc4373_serial_in_buf1)
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151 );
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152 #else
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153 static SERIAL_CHANNEL(vrc4373_serial_channel1,
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154 vrc4373_serial_funs,
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155 vrc4373_serial_info1,
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156 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BAUD),
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157 CYG_SERIAL_STOP_DEFAULT,
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158 CYG_SERIAL_PARITY_DEFAULT,
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159 CYG_SERIAL_WORD_LENGTH_DEFAULT,
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160 CYG_SERIAL_FLAGS_DEFAULT
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161 );
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162 #endif
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163
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164 DEVTAB_ENTRY(vrc4373_serial_io1,
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165 CYGDAT_IO_SERIAL_MIPS_VRC4373_SERIAL1_NAME,
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166 0, // Does not depend on a lower level interface
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167 &cyg_io_serial_devio,
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168 vrc4373_serial_init,
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169 vrc4373_serial_lookup, // Serial driver may need initializing
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170 &vrc4373_serial_channel1
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171 );
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172 #endif // CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL1
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173
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174 static cyg_interrupt vrc4373_serial_interrupt;
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175 static cyg_handle_t vrc4373_serial_interrupt_handle;
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176
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177 // Table which maps hardware channels (A,B) to software ones
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178 struct serial_channel *vrc4373_chans[] = {
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179 #ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL0 // Hardware channel A
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180 &vrc4373_serial_channel0,
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181 #else
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182 0,
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183 #endif
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184 #ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL1 // Hardware channel B
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185 &vrc4373_serial_channel1,
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186 #else
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187 0,
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188 #endif
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189 };
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190
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191 // Support functions which access the serial device. Note that this chip requires
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192 // a substantial delay after each access.
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193
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194 #define SCC_DELAY 100
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195 inline static void
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196 scc_delay(void)
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197 {
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198 int i;
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199 for (i = 0; i < SCC_DELAY; i++) ;
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200 }
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201
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202 inline static void
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203 scc_write_reg(volatile unsigned char *reg, unsigned char val)
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204 {
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205 scc_delay();
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206 *reg = val;
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207 }
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208
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209 inline static unsigned char
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210 scc_read_reg(volatile unsigned char *reg)
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211 {
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212 unsigned char val;
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213 scc_delay();
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214 val = *reg;
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215 return (val);
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216 }
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217
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218 inline static unsigned char
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219 scc_read_ctl(volatile struct serial_port *port, int reg)
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220 {
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221 if (reg != 0) {
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222 scc_write_reg(&port->scc_ctl, reg);
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223 }
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224 return (scc_read_reg(&port->scc_ctl));
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225 }
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226
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227 inline static void
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228 scc_write_ctl(volatile struct serial_port *port, int reg, unsigned char val)
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229 {
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230 if (reg != 0) {
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231 scc_write_reg(&port->scc_ctl, reg);
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232 }
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233 scc_write_reg(&port->scc_ctl, val);
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234 }
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235
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236 inline static unsigned char
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237 scc_read_dat(volatile struct serial_port *port)
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238 {
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239 return (scc_read_reg(&port->scc_dat));
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240 }
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241
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242 inline static void
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243 scc_write_dat(volatile struct serial_port *port, unsigned char val)
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244 {
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245 scc_write_reg(&port->scc_dat, val);
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246 }
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247
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248 // Internal function to actually configure the hardware to desired baud rate, etc.
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249 static bool
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250 vrc4373_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
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251 {
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252 vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv;
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253 volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base;
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254 cyg_int32 baud_rate = select_baud[new_config->baud];
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255 cyg_int32 baud_divisor;
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256 unsigned char *regs = &vrc4373_chan->regs[0];
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257 if (baud_rate == 0) return false;
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258 // Compute state of registers. The register/control state needs to be kept in
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259 // the shadow variable 'regs' because the hardware registers can only be written,
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260 // not read (in general).
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261 if (init) {
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262 // Insert appropriate resets?
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263 if (chan->out_cbuf.len != 0) {
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264 regs[R1] = WR1_IntAllRx;
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265 regs[R9] = WR9_MIE | WR9_NoVector;
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266 } else {
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267 regs[R1] = 0;
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268 regs[R9] = 0;
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269 }
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270 // Clocks are from the baud rate generator
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271 regs[R11] = WR11_TRxCBR | WR11_TRxCOI | WR11_TxCBR | WR11_RxCBR;
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272 regs[R14] = WR14_BRenable | WR14_BRSRC;
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273 regs[R10] = 0; // Unused in this [async] mode
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274 regs[R15] = 0;
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275 }
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276 regs[R3] = WR3_RxEnable | select_word_length_WR3[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5];
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277 regs[R4] = WR4_X16CLK | select_stop_bits[new_config->stop] | select_parity[new_config->parity];
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278 regs[R5] = WR5_TxEnable | select_word_length_WR5[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5];
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279 baud_divisor = BRTC(baud_rate);
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280 regs[R12] = baud_divisor & 0xFF;
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281 regs[R13] = baud_divisor >> 8;
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282 // Now load the registers
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283 scc_write_ctl(port, R4, regs[R4]);
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284 scc_write_ctl(port, R10, regs[R10]);
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285 scc_write_ctl(port, R3, regs[R3] & ~WR3_RxEnable);
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286 scc_write_ctl(port, R5, regs[R5] & ~WR5_TxEnable);
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287 scc_write_ctl(port, R1, regs[R1]);
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288 scc_write_ctl(port, R9, regs[R9]);
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289 scc_write_ctl(port, R11, regs[R11]);
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290 scc_write_ctl(port, R12, regs[R12]);
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291 scc_write_ctl(port, R13, regs[R13]);
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292 scc_write_ctl(port, R14, regs[R14]);
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293 scc_write_ctl(port, R15, regs[R15]);
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294 scc_write_ctl(port, R3, regs[R3]);
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295 scc_write_ctl(port, R5, regs[R5]);
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296 // Update configuration
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297 if (new_config != &chan->config) {
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298 chan->config = *new_config;
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299 }
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300 return true;
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301 }
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302
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303 // Function to initialize the device. Called at bootstrap time.
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304 static bool
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305 vrc4373_serial_init(struct cyg_devtab_entry *tab)
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306 {
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307 serial_channel *chan = (serial_channel *)tab->priv;
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308 vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv;
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309 static bool init = false;
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310 #ifdef CYGDBG_IO_INIT
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311 diag_printf("VRC4373 SERIAL init '%s' - dev: %x\n", tab->name, vrc4373_chan->base);
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312 #endif
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313 (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices
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314 if (!init && chan->out_cbuf.len != 0) {
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315 init = true;
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316 cyg_drv_interrupt_create(VRC4373_SCC_INT,
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317 99,
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318 (cyg_addrword_t)VRC4373_SCC_BASE+SCC_CHANNEL_A,
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319 vrc4373_serial_ISR,
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320 vrc4373_serial_DSR,
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321 &vrc4373_serial_interrupt_handle,
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322 &vrc4373_serial_interrupt);
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323 cyg_drv_interrupt_attach(vrc4373_serial_interrupt_handle);
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324 cyg_drv_interrupt_unmask(VRC4373_SCC_INT);
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325 }
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326 vrc4373_serial_config_port(chan, &chan->config, true);
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327 return true;
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328 }
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329
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330 // This routine is called when the device is "looked" up (i.e. attached)
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331 static Cyg_ErrNo
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332 vrc4373_serial_lookup(struct cyg_devtab_entry **tab,
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333 struct cyg_devtab_entry *sub_tab,
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334 const char *name)
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335 {
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336 serial_channel *chan = (serial_channel *)(*tab)->priv;
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337 (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices
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338 return ENOERR;
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339 }
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340
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341 // Send a character to the device output buffer.
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342 // Return 'true' if character is sent to device
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343 static bool
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344 vrc4373_serial_putc(serial_channel *chan, unsigned char c)
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345 {
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346 vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv;
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347 volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base;
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348 if (scc_read_ctl(port, R0) & RR0_TxEmpty) {
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349 // Transmit buffer is empty
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350 scc_write_dat(port, c);
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351 return true;
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352 } else {
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353 // No space
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354 return false;
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355 }
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356 }
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357
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358 // Fetch a character from the device input buffer, waiting if necessary
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359 static unsigned char
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360 vrc4373_serial_getc(serial_channel *chan)
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361 {
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362 unsigned char c;
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363 vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv;
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364 volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base;
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365 while ((scc_read_ctl(port, R0) & RR0_RxAvail) == 0) ; // Wait for char
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366 c = scc_read_dat(port);
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367 return c;
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368 }
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369
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370 // Set up the device characteristics; baud rate, etc.
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371 static bool
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372 vrc4373_serial_set_config(serial_channel *chan, cyg_serial_info_t *config)
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373 {
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374 return vrc4373_serial_config_port(chan, config, false);
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375 }
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376
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377 // Enable the transmitter on the device
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378 static void
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379 vrc4373_serial_start_xmit(serial_channel *chan)
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380 {
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381 vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv;
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382 volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base;
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383 if ((vrc4373_chan->regs[R1] & WR1_TxIntEnab) == 0) {
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384 CYG_INTERRUPT_STATE old;
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385 HAL_DISABLE_INTERRUPTS(old);
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386 vrc4373_chan->regs[R1] |= WR1_TxIntEnab; // Enable Tx interrupt
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387 scc_write_ctl(port, R1, vrc4373_chan->regs[R1]);
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388 (chan->callbacks->xmt_char)(chan); // Send first character to start xmitter
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389 HAL_RESTORE_INTERRUPTS(old);
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390 }
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391 }
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392
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393 // Disable the transmitter on the device
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394 static void
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395 vrc4373_serial_stop_xmit(serial_channel *chan)
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396 {
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397 vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv;
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398 volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base;
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399 if ((vrc4373_chan->regs[R1] & WR1_TxIntEnab) != 0) {
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400 CYG_INTERRUPT_STATE old;
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401 HAL_DISABLE_INTERRUPTS(old);
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402 vrc4373_chan->regs[R1] &= ~WR1_TxIntEnab; // Disable Tx interrupt
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403 scc_write_ctl(port, R1, vrc4373_chan->regs[R1]);
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404 HAL_RESTORE_INTERRUPTS(old);
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405 }
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406 }
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407
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408 // Serial I/O - low level interrupt handler (ISR)
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409 static cyg_uint32
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410 vrc4373_serial_ISR(cyg_vector_t vector, cyg_addrword_t data)
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411 {
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412 cyg_drv_interrupt_mask(VRC4373_SCC_INT);
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413 cyg_drv_interrupt_acknowledge(VRC4373_SCC_INT);
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414 return CYG_ISR_CALL_DSR; // Cause DSR to be run
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415 }
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416
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417 inline static void
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418 vrc4373_int(serial_channel *chan, unsigned char stat)
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419 {
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420 vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv;
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421 volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base;
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422 // Note: 'stat' value is interrupt status register, shifted into "B" position
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423 if (stat & RR3_BRxIP) {
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424 // Receive interrupt
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425 unsigned char c;
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426 c = scc_read_dat(port);
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427 (chan->callbacks->rcv_char)(chan, c);
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428 }
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429 if (stat & RR3_BTxIP) {
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430 // Transmit interrupt
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431 (chan->callbacks->xmt_char)(chan);
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432 }
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433 if (stat & RR3_BExt) {
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434 // Status interrupt (parity error, framing error, etc)
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435 }
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436 }
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437
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438 // Serial I/O - high level interrupt handler (DSR)
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439 // Note: This device presents a single interrupt for both channels. Thus the
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440 // interrupt handler has to query the device and decide which channel needs service.
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441 // Additionally, more than one interrupt condition may be present so this needs to
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442 // be done in a loop until all interrupt requests have been handled.
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443 // Also note that the hardware is rather broken. The interrupt status needs to
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444 // be read using only channel A (pointed to by 'data')
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445 static void
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446 vrc4373_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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447 {
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448 serial_channel *chan;
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449 volatile struct serial_port *port = (volatile struct serial_port *)data;
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450 unsigned char stat;
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451 while (true) {
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452 stat = scc_read_ctl(port, R3);
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453 if (stat & (RR3_AExt | RR3_ATxIP | RR3_ARxIP)) {
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454 chan = vrc4373_chans[0]; // Hardware channel A
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455 vrc4373_int(chan, stat>>3); // Handle interrupt
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456 } else if (stat & (RR3_BExt | RR3_BTxIP | RR3_BRxIP)) {
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457 chan = vrc4373_chans[1]; // Hardware channel A
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458 vrc4373_int(chan, stat); // Handle interrupt
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459 } else {
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460 // No more interrupts, all done
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461 break;
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462 }
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463 }
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464 cyg_drv_interrupt_unmask(VRC4373_SCC_INT);
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465 }
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466 #endif