Mercurial > ecos-v3_0-branch
annotate packages/devs/watchdog/arm/at91/current/src/watchdog_at91.cxx @ 2729:74dbf4c3f2e1 after-copyright-change-20090129
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
| author | jlarmour |
|---|---|
| date | Thu, 29 Jan 2009 17:47:46 +0000 |
| parents | ac3572aaf2c9 |
| children |
| rev | line source |
|---|---|
| 266 | 1 //========================================================================== |
| 2 // | |
| 3 // devs/watchdog/arm/at91/watchdog_at91.cxx | |
| 4 // | |
| 5 // Watchdog implementation for ARM AT91 CPU | |
| 6 // | |
| 7 //========================================================================== | |
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8 // ####ECOSGPLCOPYRIGHTBEGIN#### |
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9 // ------------------------------------------- |
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10 // This file is part of eCos, the Embedded Configurable Operating System. |
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
| 266 | 12 // |
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13 // eCos is free software; you can redistribute it and/or modify it under |
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14 // the terms of the GNU General Public License as published by the Free |
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15 // Software Foundation; either version 2 or (at your option) any later |
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16 // version. |
| 266 | 17 // |
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT |
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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21 // for more details. |
| 266 | 22 // |
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23 // You should have received a copy of the GNU General Public License |
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24 // along with eCos; if not, write to the Free Software Foundation, Inc., |
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
| 266 | 26 // |
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27 // As a special exception, if other files instantiate templates or use |
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28 // macros or inline functions from this file, or you compile this file |
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29 // and link it with other works to produce a work based on this file, |
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30 // this file does not by itself cause the resulting work to be covered by |
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31 // the GNU General Public License. However the source code for this file |
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32 // must still be made available in accordance with section (3) of the GNU |
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33 // General Public License v2. |
| 266 | 34 // |
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35 // This exception does not invalidate any other reasons why a work based |
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74dbf4c3f2e1
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36 // on this file might be covered by the GNU General Public License. |
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74dbf4c3f2e1
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37 // ------------------------------------------- |
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38 // ####ECOSGPLCOPYRIGHTEND#### |
| 266 | 39 //========================================================================== |
| 40 //#####DESCRIPTIONBEGIN#### | |
| 41 // | |
| 42 // Author(s): tkoeller | |
| 1015 | 43 // Contributors: tkoeller, nickg |
| 266 | 44 // Date: 2002-05-05 |
| 45 // Purpose: Watchdog class implementation | |
| 46 // Description: Contains an implementation of the Watchdog class for use | |
| 47 // with the ATMEL AT91 watchdog timer. | |
| 48 // | |
| 49 //####DESCRIPTIONEND#### | |
| 50 // | |
| 51 //========================================================================== | |
| 52 | |
| 53 #include <pkgconf/kernel.h> | |
| 54 #include <pkgconf/infra.h> | |
| 55 #include <pkgconf/kernel.h> | |
| 56 #include <pkgconf/watchdog.h> | |
| 57 #include <pkgconf/devs_watchdog_arm_at91.h> | |
| 1015 | 58 |
| 266 | 59 #include <cyg/infra/cyg_type.h> |
| 60 #include <cyg/infra/cyg_ass.h> | |
| 61 #include <cyg/infra/cyg_trac.h> | |
| 62 #include <cyg/hal/hal_io.h> | |
| 63 #include <cyg/hal/hal_diag.h> | |
| 1015 | 64 |
| 266 | 65 #include <cyg/io/watchdog.hxx> |
| 1015 | 66 |
| 266 | 67 #if !defined(CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT) |
| 68 #include <cyg/hal/hal_platform_ints.h> | |
| 69 #include <cyg/kernel/intr.hxx> | |
| 70 #endif | |
| 71 | |
| 1015 | 72 //========================================================================== |
| 73 | |
| 74 #define MCLK_FREQUENCY_KHZ (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/1000) | |
| 266 | 75 #define MAX_TICKS 0x0000ffff |
| 1015 | 76 #define BASE_TICKS (MCLK_FREQUENCY_KHZ * CYGNUM_DEVS_WATCHDOG_ARM_AT91_DESIRED_TIMEOUT_MS) |
| 77 | |
| 78 #if defined(CYGHWR_HAL_ARM_AT91_R40008) || \ | |
| 79 defined(CYGHWR_HAL_ARM_AT91_R40807) | |
| 266 | 80 |
| 81 #if BASE_TICKS / 8 <= MAX_TICKS | |
| 82 #define DIVIDER 0 | |
| 83 #define DIV_FACTOR 8 | |
| 84 #elif BASE_TICKS / 32 <= MAX_TICKS | |
| 85 #define DIVIDER 1 | |
| 86 #define DIV_FACTOR 32 | |
| 87 #elif BASE_TICKS / 128 <= MAX_TICKS | |
| 88 #define DIVIDER 2 | |
| 89 #define DIV_FACTOR 128 | |
| 90 #elif BASE_TICKS / 1024 <= MAX_TICKS | |
| 91 #define DIVIDER 3 | |
| 92 #define DIV_FACTOR 1024 | |
| 93 #else | |
| 94 #error Desired resolution beyond hardware capabilities | |
| 95 #endif | |
| 96 | |
| 1015 | 97 #elif defined(CYGHWR_HAL_ARM_AT91_M55800A) |
| 98 | |
| 99 #if BASE_TICKS / 32 <= MAX_TICKS | |
| 100 #define DIVIDER 0 | |
| 101 #define DIV_FACTOR 32 | |
| 102 #elif BASE_TICKS / 128 <= MAX_TICKS | |
| 103 #define DIVIDER 1 | |
| 104 #define DIV_FACTOR 128 | |
| 105 #elif BASE_TICKS / 1024 <= MAX_TICKS | |
| 106 #define DIVIDER 2 | |
| 107 #define DIV_FACTOR 1024 | |
| 108 #elif BASE_TICKS / 4096 <= MAX_TICKS | |
| 109 #define DIVIDER 3 | |
| 110 #define DIV_FACTOR 4096 | |
| 111 #else | |
| 112 #error Desired resolution beyond hardware capabilities | |
| 113 #endif | |
| 1797 | 114 #elif defined(CYGHWR_HAL_ARM_AT91_JTST) |
| 115 #if BASE_TICKS / 32 <= MAX_TICKS | |
| 116 #define DIVIDER 0 | |
| 117 #define DIV_FACTOR 32 | |
| 118 #elif BASE_TICKS / 128 <= MAX_TICKS | |
| 119 #define DIVIDER 1 | |
| 120 #define DIV_FACTOR 128 | |
| 121 #elif BASE_TICKS / 1024 <= MAX_TICKS | |
| 122 #define DIVIDER 2 | |
| 123 #define DIV_FACTOR 1024 | |
| 124 #elif BASE_TICKS / 2046 <= MAX_TICKS | |
| 125 #define DIVIDER 3 | |
| 126 #define DIV_FACTOR 2046 | |
| 127 #else | |
| 128 #error Desired resolution beyond hardware capabilities | |
| 129 #endif | |
| 1015 | 130 |
| 131 #endif | |
| 132 | |
| 266 | 133 #define TICKS ((BASE_TICKS / DIV_FACTOR) | 0xfff) |
| 134 #define RESOLUTION ((cyg_uint64) (TICKS * DIV_FACTOR ) * 1000000 / MCLK_FREQUENCY_KHZ) | |
| 135 | |
| 1015 | 136 //========================================================================== |
| 266 | 137 |
| 138 #if defined(CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT) | |
| 139 | |
| 140 #define OMRVAL (AT91_WD_OMR_OKEY | AT91_WD_OMR_RSTEN | AT91_WD_OMR_WDEN) | |
| 141 | |
| 142 void | |
| 143 Cyg_Watchdog::init_hw(void) | |
| 144 { | |
| 145 CYG_REPORT_FUNCTION(); | |
| 146 CYG_REPORT_FUNCARGVOID(); | |
| 147 resolution = RESOLUTION; | |
| 148 CYG_REPORT_RETURN(); | |
| 149 } | |
| 150 | |
| 151 #else /* defined(CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT) */ | |
| 152 | |
| 1015 | 153 //========================================================================== |
| 154 | |
| 266 | 155 #define OMRVAL (AT91_WD_OMR_OKEY | AT91_WD_OMR_IRQEN | AT91_WD_OMR_WDEN) |
| 156 #define INT_PRIO 7 | |
| 157 | |
| 1015 | 158 //========================================================================== |
| 266 | 159 |
| 1015 | 160 static Cyg_Watchdog *wd; |
| 161 | |
| 162 //========================================================================== | |
| 266 | 163 |
| 164 static cyg_uint32 | |
| 165 isr(cyg_vector vector, CYG_ADDRWORD data) | |
| 166 { | |
| 167 CYG_REPORT_FUNCTION(); | |
| 168 CYG_REPORT_FUNCARG2XV(vector, data); | |
| 169 | |
| 1015 | 170 wd->trigger(); |
| 266 | 171 Cyg_Interrupt::acknowledge_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG); |
| 172 CYG_REPORT_RETVAL(Cyg_Interrupt::HANDLED); | |
| 173 return Cyg_Interrupt::HANDLED; | |
| 174 } | |
| 175 | |
| 1015 | 176 //========================================================================== |
| 177 | |
| 178 static Cyg_Interrupt wdint( | |
| 179 CYGNUM_HAL_INTERRUPT_WATCHDOG, | |
| 180 INT_PRIO, | |
| 181 0, | |
| 182 isr, | |
| 183 NULL | |
| 184 ); | |
| 185 | |
| 186 //========================================================================== | |
| 266 | 187 |
| 188 void | |
| 189 Cyg_Watchdog::init_hw(void) | |
| 190 { | |
| 191 CYG_REPORT_FUNCTION(); | |
| 192 CYG_REPORT_FUNCARGVOID(); | |
| 193 | |
| 1015 | 194 wd = this; |
| 266 | 195 resolution = RESOLUTION; |
| 1015 | 196 wdint.configure_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG, false, true); |
| 197 wdint.attach(); | |
| 198 wdint.acknowledge_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG); | |
| 199 wdint.unmask_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG); | |
| 266 | 200 CYG_REPORT_RETURN(); |
| 201 } | |
| 202 | |
| 203 #endif /* defined(CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT) */ | |
| 204 | |
| 1015 | 205 //========================================================================== |
| 266 | 206 /* |
| 207 * Reset watchdog timer. This needs to be called regularly to prevent | |
| 208 * the watchdog from firing. | |
| 209 */ | |
| 1015 | 210 |
| 266 | 211 void |
| 212 Cyg_Watchdog::reset(void) | |
| 213 { | |
| 214 CYG_REPORT_FUNCTION(); | |
| 215 CYG_REPORT_FUNCARGVOID(); | |
| 216 | |
| 217 /* Write magic code to reset the watchdog. */ | |
| 218 HAL_WRITE_UINT32(AT91_WD + AT91_WD_CR, AT91_WD_CR_RSTKEY); | |
| 219 CYG_REPORT_RETURN(); | |
| 220 } | |
| 221 | |
| 1015 | 222 //========================================================================== |
| 266 | 223 /* |
| 224 * Start watchdog to generate a hardware reset | |
| 225 * or interrupt when expiring. | |
| 226 */ | |
| 1015 | 227 |
| 266 | 228 void |
| 229 Cyg_Watchdog::start(void) | |
| 230 { | |
| 231 CYG_REPORT_FUNCTION(); | |
| 232 CYG_REPORT_FUNCARGVOID(); | |
| 233 | |
| 234 HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, AT91_WD_OMR_OKEY); | |
| 235 HAL_WRITE_UINT32( | |
| 236 AT91_WD + AT91_WD_CMR, | |
| 237 AT91_WD_CMR_CKEY | ((TICKS >> 10) & AT91_WD_CMR_HPCV) | DIVIDER | |
| 238 ); | |
| 239 HAL_WRITE_UINT32(AT91_WD + AT91_WD_CR, AT91_WD_CR_RSTKEY); | |
| 240 HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, OMRVAL); | |
| 241 CYG_REPORT_RETURN(); | |
| 242 } | |
| 1015 | 243 |
| 244 //========================================================================== | |
| 245 // End of watchdog_at91.cxx |