Mercurial > ecos-v3_0-branch
annotate packages/hal/arm/at91/jtst/current/include/plf_io.h @ 2729:74dbf4c3f2e1 after-copyright-change-20090129
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
| author | jlarmour |
|---|---|
| date | Thu, 29 Jan 2009 17:47:46 +0000 |
| parents | 022b1537390b |
| children |
| rev | line source |
|---|---|
| 1769 | 1 #ifndef CYGONCE_HAL_PLF_IO_H |
| 2 #define CYGONCE_HAL_PLF_IO_H | |
| 3 //============================================================================= | |
| 4 // | |
| 5 // plf_io.h | |
| 6 // | |
| 7 // JTST board specific registers | |
| 8 // | |
| 9 //============================================================================= | |
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10 // ####ECOSGPLCOPYRIGHTBEGIN#### |
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11 // ------------------------------------------- |
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12 // This file is part of eCos, the Embedded Configurable Operating System. |
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13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
| 1769 | 14 // |
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15 // eCos is free software; you can redistribute it and/or modify it under |
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16 // the terms of the GNU General Public License as published by the Free |
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17 // Software Foundation; either version 2 or (at your option) any later |
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18 // version. |
| 1769 | 19 // |
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT |
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21 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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23 // for more details. |
| 1769 | 24 // |
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25 // You should have received a copy of the GNU General Public License |
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26 // along with eCos; if not, write to the Free Software Foundation, Inc., |
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27 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
| 1769 | 28 // |
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29 // As a special exception, if other files instantiate templates or use |
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30 // macros or inline functions from this file, or you compile this file |
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31 // and link it with other works to produce a work based on this file, |
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32 // this file does not by itself cause the resulting work to be covered by |
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33 // the GNU General Public License. However the source code for this file |
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34 // must still be made available in accordance with section (3) of the GNU |
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35 // General Public License v2. |
| 1769 | 36 // |
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37 // This exception does not invalidate any other reasons why a work based |
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74dbf4c3f2e1
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38 // on this file might be covered by the GNU General Public License. |
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74dbf4c3f2e1
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39 // ------------------------------------------- |
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40 // ####ECOSGPLCOPYRIGHTEND#### |
| 1769 | 41 //============================================================================= |
| 42 //#####DESCRIPTIONBEGIN#### | |
| 43 // | |
| 44 // Author(s): tkoeller | |
| 45 // Contributors: amichelotti | |
| 46 // Date: 2004-06-6 | |
| 47 // Purpose: Atmel JTST board specific registers | |
| 48 // Description: | |
| 49 // Usage: #include <cyg/hal/plf_io.h> | |
| 50 // | |
| 51 //####DESCRIPTIONEND#### | |
| 52 // | |
| 53 //============================================================================= | |
| 54 | |
| 55 #define CYGARC_PHYSICAL_ADDRESS(_x_) | |
| 56 | |
| 57 // mapping diopsis internal resources | |
| 58 #define AT91_USART0 0xFFFC0000 | |
| 59 #define AT91_USART1 0xFFFC4000 | |
| 60 #define AT91_SPI0 0xFFFC8000 | |
| 61 #define AT91_SPI1 0xFFFCC000 | |
| 62 | |
| 63 #define AT91_PIO 0xFFFF0000 | |
| 64 #define AT91_AIC 0xFFFFF000 | |
| 65 #define AT91_TC 0xFFFEC000 | |
| 66 #define AT91_EBI 0xFFFE4000 | |
| 67 #define AT91_WD 0xFFFF8000 | |
| 68 #define AT91_CLKGEN 0xFFF00000 // clock divider | |
| 69 #define AT91_ADDA 0xFFF08000 // ADDA Analog Digital Digital Analog | |
| 70 | |
| 71 // PDC2 USART control | |
| 72 #define AT91_US_RPR 0x100 // Receive Pointer Register | |
| 73 #define AT91_US_RCR 0x104 // Receive Counter Register | |
| 74 #define AT91_US_TPR 0x108 // Transmit Pointer Register | |
| 75 #define AT91_US_TCR 0x10C // Transmit Counter Register | |
| 76 #define AT91_US_NRPR 0x110 // Next Receive Pointer Register | |
| 77 #define AT91_US_NRCR 0x114 // Next Receive Counter Register | |
| 78 #define AT91_US_NTPR 0x118 // Next Transmit Pointer Register | |
| 79 #define AT91_US_NTCR 0x11C // Next Trsnsmit Counter Register | |
| 80 | |
| 81 // PDC2 SPI control | |
| 82 #define AT91_SPI_RPR 0x100 // equal meaning for SPI | |
| 83 #define AT91_SPI_RCR 0x104 | |
| 84 #define AT91_SPI_TPR 0x108 | |
| 85 #define AT91_SPI_TCR 0x10C | |
| 86 #define AT91_SPI_NRPR 0x110 | |
| 87 #define AT91_SPI_NRCR 0x114 | |
| 88 #define AT91_SPI_NTPR 0x118 | |
| 89 #define AT91_SPI_NTCR 0x11C | |
| 90 | |
| 91 | |
| 92 #define AT91_PDC_PTCR 0x120 // Pdc Transfer control register | |
| 93 #define AT91_PDC_PTCR_TXEN 0x100 | |
| 94 #define AT91_PDC_PTCR_RXEN 0x1 | |
| 95 | |
| 96 #define AT91_PDC_PTCR_TXDIS 0x200 | |
| 97 #define AT91_PDC_PTCR_RXDIS 0x2 | |
| 98 | |
| 99 | |
| 100 // CLOCK divider interface | |
| 101 | |
| 102 #define AT91_CLKGEN_CPTMAX0 0x0 //counter 0 | |
| 103 #define AT91_CLKGEN_CPTMAX1 0x4 //counter 1 | |
| 104 #define AT91_CLKGEN_CPTMAX2 0x8 //.. | |
| 105 #define AT91_CLKGEN_CPTMAX3 0xC | |
| 106 #define AT91_CLKGEN_CPTMAX4 0x10 | |
| 107 #define AT91_CLKGEN_CPTMAX5 0x14 | |
| 108 #define AT91_CLKGEN_CPTMAX6 0x18 | |
| 109 #define AT91_CLKGEN_CPTMAX7 0x1C | |
| 110 #define AT91_CLKGEN_CPTMAX8 0x20 | |
| 111 #define AT91_CLKGEN_CLKENABLE 0x24 // enable clocks out, wronly | |
| 112 #define AT91_CLKGEN_CLKDISABLE 0x28 // disable clocks out, wronly | |
| 113 | |
| 114 // ADDA Analog Digital Digital Analog interface | |
| 115 | |
| 116 #define AT91_ADDA_CR 0x0 // adda configuration | |
| 117 #define AT91_ADDA_ADCL0 0x20 // ADC input channel0 LEFT | |
| 118 #define AT91_ADDA_ADCR0 0x24 // ADC input channel0 RIGHT | |
| 119 #define AT91_ADDA_ADCL1 0x28 // ADC input channel1 LEFT | |
| 120 #define AT91_ADDA_ADCR1 0x2C // ADC input channel1 RIGHT | |
| 121 #define AT91_ADDA_ADCL2 0x30 // ADC input channel2 LEFT | |
| 122 #define AT91_ADDA_ADCR2 0x34 // ADC input channel2 RIGHT | |
| 123 #define AT91_ADDA_ADCL3 0x38 // ADC input channel3 LEFT | |
| 124 #define AT91_ADDA_ADCR3 0x3C // ADC input channel3 RIGHT | |
| 125 | |
| 126 #define AT91_ADDA_DACL0 0x20 // DAC output channel0 LEFT | |
| 127 #define AT91_ADDA_DACR0 0x24 // DAC output channel0 RIGHT | |
| 128 #define AT91_ADDA_DACL1 0x28 // DAC output channel1 LEFT | |
| 129 #define AT91_ADDA_DACR1 0x2C // DAC output channel1 RIGHT | |
| 130 #define AT91_ADDA_DACL2 0x30 // DAC output channel2 LEFT | |
| 131 #define AT91_ADDA_DACR2 0x34 // DAC output channel2 RIGHT | |
| 132 #define AT91_ADDA_DACL3 0x38 // DAC output channel3 LEFT | |
| 133 #define AT91_ADDA_DACR4 0x3C // DAC output channel3 RIGHT | |
| 134 | |
| 135 ///// MAGIC DSP | |
| 136 // Magic Data Memory Left BASE 40 bit width (64 bit aligned) | |
| 137 #define AT91_MAARDML 0x00410000 | |
| 138 // Magic Data Memory Right BASE 40 bit width (64 bit aligned) | |
| 139 #define AT91_MAARDMR 0x00420000 | |
| 140 // Magic Parm Left Base (arm interchange memory) 40 bit width (64 bit aligned) | |
| 141 #define AT91_MAARPARML 0x00490000 | |
| 142 // Magic Parm Right Base (arm interchange memory) 40 bit width (64 bit aligned) | |
| 143 #define AT91_MAARPARMR 0x004A0000 | |
| 144 // Magic Program Memory | |
| 145 #define AT91_MAARPM 0x00430000 | |
| 146 | |
| 147 // Magic Global Controller registers | |
| 148 #define AT91_MAARGSR 0x00450000 | |
| 149 #define AT91_MAARGSR_SAR 0x0 // start magic program address | |
| 150 #define AT91_MAARGSR_CONF 0x4 // magic configuration | |
| 151 #define AT91_MAARGSR_STAT 0x8 // magic status rdonly | |
| 152 #define AT91_MAARGSR_EXC 0xC // magic exception rdonly | |
| 153 #define AT91_MAARGSR_EXC_MSK 0x10 // magic exception mask | |
| 154 #define AT91_MAARGSR_PC 0x14 // magic program counter | |
| 155 #define AT91_MAARGSR_QCS 0x18 // magic condition stack Q | |
| 156 #define AT91_MAARGSR_ICS 0x1C // magic condition stack I | |
| 157 #define AT91_MAARGSR_PMS 0x20 // magic pma stack | |
| 158 #define AT91_MAARGSR_DMA_TYPE 0x24 // magic dma type | |
| 159 #define AT91_MAARGSR_DMA_LEN 0x28 // magic dma len | |
| 160 #define AT91_MAARGSR_DMA_MOD 0x2C // magic modifier/stride | |
| 161 #define AT91_MAARGSR_DMA_BADD 0x30 // magic dma buffer address | |
| 162 // (internal address) | |
| 163 #define AT91_MAARGSR_DMA_XADD 0x34 // magic dma external address | |
| 164 #define AT91_MAARGSR_DMA_START 0x38 // magic start dma | |
| 165 #define AT91_MAARGSR_STEP_MODE 0x3C // magic single cycle mode | |
| 166 | |
| 167 // Magic MAAR (MAgic ARm interface) Controller registers base | |
| 168 #define AT91_MAARCSE 0x00460000 | |
| 169 #define AT91_MAARCSE_CMD 0x0 // command register | |
| 170 #define AT91_MAARCSE_CMD_RUN 0x1 // run | |
| 171 #define AT91_MAARCSE_SR 0x4 // status register | |
| 172 #define AT91_MAARCSE_EXC 0x8 // exception register | |
| 173 #define AT91_MAARCSE_EXC_MSK 0xC // mask exception register | |
| 174 | |
| 175 // usarts are connected to clock divider | |
| 176 #define AT91_US_BAUD(baud) (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(16*(baud))) | |
| 177 #define AT91_SPI_BAUD(baud) (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(4*(baud))) | |
| 178 | |
| 179 #endif // CYGONCE_HAL_PLF_IO_H |