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annotate packages/hal/arm/snds/current/src/snds100_misc.c @ 2729:74dbf4c3f2e1 after-copyright-change-20090129

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Update all copyright banners to reflect FSF ownership; fix and improve licence text.
author jlarmour
date Thu, 29 Jan 2009 17:47:46 +0000
parents d2c90368aeef
children
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1 //==========================================================================
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2 //
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3 // snds100_misc.c
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4 //
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5 // HAL misc board support code for Samsung SNDS100
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6 //
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7 //==========================================================================
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8 // ####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later
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16 // version.
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17 //
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 // for more details.
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22 //
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23 // You should have received a copy of the GNU General Public License
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24 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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26 //
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27 // As a special exception, if other files instantiate templates or use
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28 // macros or inline functions from this file, or you compile this file
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29 // and link it with other works to produce a work based on this file,
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30 // this file does not by itself cause the resulting work to be covered by
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31 // the GNU General Public License. However the source code for this file
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32 // must still be made available in accordance with section (3) of the GNU
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33 // General Public License v2.
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34 //
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35 // This exception does not invalidate any other reasons why a work based
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36 // on this file might be covered by the GNU General Public License.
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37 // -------------------------------------------
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38 // ####ECOSGPLCOPYRIGHTEND####
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39 //==========================================================================
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40 //#####DESCRIPTIONBEGIN####
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41 //
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42 // Author(s): gthomas
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43 // Contributors: gthomas, jskov
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44 // Grant Edwards <grante@visi.com>
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45 // Date: 2001-07-31
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46 // Purpose: HAL board support
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47 // Description: Implementations of HAL board interfaces
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48 //
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49 //####DESCRIPTIONEND####
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50 //
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51 //========================================================================*/
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52
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53 #include <pkgconf/hal.h>
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54
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55 #include <cyg/infra/cyg_type.h> // base types
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56 #include <cyg/infra/cyg_trac.h> // tracing macros
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57 #include <cyg/infra/cyg_ass.h> // assertion macros
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58 #include <cyg/infra/diag.h> // diag_printf()
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59
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60 #include <cyg/hal/hal_io.h> // IO macros
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61 #include <cyg/hal/hal_arch.h> // Register state info
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62 #include <cyg/hal/hal_diag.h>
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63 #include <cyg/hal/hal_cache.h>
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64 #include <cyg/hal/hal_intr.h> // necessary?
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65 #include <cyg/hal/hal_if.h> // calling interface
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66 #include <cyg/hal/hal_misc.h> // helper functions
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67 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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68 #include <cyg/hal/drv_api.h> // HAL ISR support
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69 #endif
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70
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71 #include "ks32c5000.h"
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72 #include <cyg/hal/plf_io.h>
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73
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74 //======================================================================
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75 // Use Timer0 for kernel clock
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76
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77 static cyg_uint32 _period;
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78
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79 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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80 static cyg_interrupt abort_interrupt;
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81 static cyg_handle_t abort_interrupt_handle;
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82
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83 // This ISR is called only for the Abort button interrupt
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84 static int
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85 ks32c_abort_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
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86 {
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87 cyg_hal_user_break((CYG_ADDRWORD*)regs);
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88 cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_EXT0);
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89 return 0; // No need to run DSR
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90 }
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91 #endif
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92
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93 void hal_clock_initialize(cyg_uint32 period)
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94 {
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95 cyg_uint32 tmod;
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96
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97 // Disable timer 0
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98 HAL_READ_UINT32(KS32C_TMOD, tmod);
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99 tmod &= ~(KS32C_TMOD_TE0);
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100 HAL_WRITE_UINT32(KS32C_TMOD, 0);
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101
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102 tmod &= ~(KS32C_TMOD_TMD0 | KS32C_TMOD_TCLR0);
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103 tmod |= KS32C_TMOD_TE0;
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104
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105 // Set counter
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106 HAL_WRITE_UINT32(KS32C_TDATA0, period);
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107
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108 // And enable timer
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109 HAL_WRITE_UINT32(KS32C_TMOD, tmod);
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110
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111 _period = period;
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112
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113 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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114 cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_EXT0,
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115 99, // Priority
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116 0, // Data item passed to interrupt handler
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117 ks32c_abort_isr,
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118 0,
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119 &abort_interrupt_handle,
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120 &abort_interrupt);
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121 cyg_drv_interrupt_attach(abort_interrupt_handle);
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122 cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_EXT0);
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123 #endif
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124 }
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125
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126 void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
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127 {
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128 _period = period;
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129 }
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130
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131 void hal_clock_read(cyg_uint32 *pvalue)
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132 {
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133 cyg_uint32 value;
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134
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135 HAL_READ_UINT32(KS32C_TCNT0, value);
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136 *pvalue = _period - value;
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137 }
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138
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139 //======================================================================
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140 // Interrupt controller stuff
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141
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142 extern volatile tInterruptController ks32c5000_int; // Interrupt controller registers
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143 extern volatile unsigned long EXTACON0; // Extern access control reg
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144 extern volatile unsigned long EXTACON1; // Extern access control reg
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145 extern volatile unsigned long IOPCON; // I/O Port Control reg
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146 extern volatile unsigned long IOPMOD;
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147 extern volatile unsigned long SYSCON;
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148
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149 void hal_hardware_init(void)
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150 {
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151 cyg_uint32 intmask, syscfg;
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152
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153 // Set up eCos/ROM interfaces
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154 hal_if_init();
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155
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156 // Enable cache
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157 HAL_READ_UINT32(KS32C_SYSCFG, syscfg);
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158 syscfg &= ~KS32C_SYSCFG_CM_MASK;
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159 syscfg |= KS32C_SYSCFG_CM_0R_8C|KS32C_SYSCFG_WE;
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160 HAL_WRITE_UINT32(KS32C_SYSCFG, syscfg);
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161 HAL_UCACHE_INVALIDATE_ALL();
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162 HAL_UCACHE_ENABLE();
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163
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164 // Clear global interrupt mask bit
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165 HAL_READ_UINT32(KS32C_INTMSK, intmask);
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166 intmask &= ~KS32C_INTMSK_GLOBAL;
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167 HAL_WRITE_UINT32(KS32C_INTMSK, intmask);
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168 }
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169
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170
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171 // This routine is called to respond to a hardware interrupt (IRQ). It
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172 // should interrogate the hardware and return the IRQ vector number.
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173
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174 int hal_IRQ_handler(void)
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175 {
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176 // Do hardware-level IRQ handling
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177 cyg_uint32 irq_status;
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178 HAL_READ_UINT32(KS32C_INTOFFSET_IRQ, irq_status);
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179 irq_status = irq_status / 4;
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180 if (CYGNUM_HAL_ISR_MAX >= irq_status)
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181 return irq_status;
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182 // It's a bit bogus to test for FIQs after IRQs, but we use the
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183 // latter more, so don't impose the overhead of checking for FIQs
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184 HAL_READ_UINT32(KS32C_INTOFFSET_FIQ, irq_status);
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185 irq_status = irq_status / 4;
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186 if (CYGNUM_HAL_ISR_MAX >= irq_status)
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187 return irq_status;
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188 return CYGNUM_HAL_INTERRUPT_NONE;
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189 }
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190
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191
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192 //
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193 // Interrupt control
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194 //
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195
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196 void hal_interrupt_mask(int vector)
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197 {
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198 cyg_uint32 mask, old_mask;
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199 HAL_READ_UINT32(KS32C_INTMSK, mask);
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200 old_mask = mask;
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201 mask |= (1<<vector);
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202 HAL_WRITE_UINT32(KS32C_INTMSK, mask);
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203 }
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204
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205 void hal_interrupt_unmask(int vector)
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206 {
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207 cyg_uint32 mask, old_mask;
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208 HAL_READ_UINT32(KS32C_INTMSK, mask);
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209 old_mask = mask;
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210 mask &= ~(1<<vector);
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211 HAL_WRITE_UINT32(KS32C_INTMSK, mask);
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212 }
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213
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214 void hal_interrupt_acknowledge(int vector)
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215 {
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216 HAL_WRITE_UINT32(KS32C_INTPND, (1<<vector));
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217 }
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218
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219 void hal_interrupt_configure(int vector, int level, int up)
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220 {
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221 }
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222
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223 void hal_interrupt_set_level(int vector, int level)
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224 {
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225 }
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226
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227 void hal_show_IRQ(int vector, int data, int handler)
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228 {
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229 }
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230
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231 // -------------------------------------------------------------------------
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232 //
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233 // Delay for some number of micro-seconds
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234 //
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235 void hal_delay_us(cyg_int32 usecs)
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236 {
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237 cyg_uint32 count;
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238 cyg_uint32 ticks = ((CYGNUM_HAL_RTC_PERIOD*CYGNUM_HAL_RTC_DENOMINATOR)/1000000) * usecs;
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239 cyg_uint32 tmod;
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240
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241 // Disable timer 1
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242 HAL_READ_UINT32(KS32C_TMOD, tmod);
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243 tmod &= ~(KS32C_TMOD_TE1);
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244 HAL_WRITE_UINT32(KS32C_TMOD, tmod);
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245
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246 tmod &= ~(KS32C_TMOD_TMD1 | KS32C_TMOD_TCLR1);
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247 tmod |= KS32C_TMOD_TE1;
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248
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249 // Clear pending flag
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250 HAL_WRITE_UINT32(KS32C_INTPND, (1 << CYGNUM_HAL_INTERRUPT_TIMER1));
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251
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252 // Set counter
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253 HAL_WRITE_UINT32(KS32C_TDATA1, ticks);
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254
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255 // And enable timer
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256 HAL_WRITE_UINT32(KS32C_TMOD, tmod);
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257
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258 // Wait for timer to underflow. Can't test the timer completion
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259 // bit without actually enabling the interrupt. So instead watch
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260 // the counter.
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261 ticks /= 2; // wait for this threshold
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262
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263 // Wait till timer counts below threshold
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264 do {
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265 HAL_READ_UINT32(KS32C_TCNT1, count);
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266 } while (count >= ticks);
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267 // then wait for it to be reloaded
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268 do {
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269 HAL_READ_UINT32(KS32C_TCNT1, count);
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270 } while (count < ticks);
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271
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272 // Then disable timer 1 again
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273 tmod &= ~KS32C_TMOD_TE1;
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274 HAL_WRITE_UINT32(KS32C_TMOD, tmod);
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275 }
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276
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277 // No way to reset board
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278
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279 void hal_reset(void)
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280 {
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281 CYG_INTERRUPT_STATE old;
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282 HAL_DISABLE_INTERRUPTS(old);
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283 while (1)
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284 ;
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285 }