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annotate packages/hal/arm/xscale/iop310/current/src/hal_diag.c @ 2729:74dbf4c3f2e1 after-copyright-change-20090129

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Update all copyright banners to reflect FSF ownership; fix and improve licence text.
author jlarmour
date Thu, 29 Jan 2009 17:47:46 +0000
parents de449c532876
children
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1 /*=============================================================================
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2 //
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3 // hal_diag.c
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4 //
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5 // HAL diagnostic output code
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6 //
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7 //=============================================================================
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8 // ####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later
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16 // version.
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17 //
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 // for more details.
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22 //
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23 // You should have received a copy of the GNU General Public License
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24 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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26 //
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27 // As a special exception, if other files instantiate templates or use
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28 // macros or inline functions from this file, or you compile this file
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29 // and link it with other works to produce a work based on this file,
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30 // this file does not by itself cause the resulting work to be covered by
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31 // the GNU General Public License. However the source code for this file
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32 // must still be made available in accordance with section (3) of the GNU
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33 // General Public License v2.
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34 //
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35 // This exception does not invalidate any other reasons why a work based
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36 // on this file might be covered by the GNU General Public License.
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37 // -------------------------------------------
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38 // ####ECOSGPLCOPYRIGHTEND####
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39 //=============================================================================
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40 //#####DESCRIPTIONBEGIN####
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41 //
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42 // Author(s): msalter
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43 // Contributors:msalter, gthomas
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44 // Date: 2000-10-10
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45 // Purpose: HAL diagnostic output
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46 // Description: Implementations of HAL diagnostic output support.
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47 //
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48 //####DESCRIPTIONEND####
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49 //
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50 //===========================================================================*/
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51
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52 #include <pkgconf/hal.h>
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53 #include <pkgconf/system.h>
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54 #include CYGBLD_HAL_PLATFORM_H
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55
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56 #include <cyg/infra/cyg_type.h> // base types
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57 #include <cyg/infra/cyg_trac.h> // tracing macros
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58 #include <cyg/infra/cyg_ass.h> // assertion macros
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59
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60 #include <cyg/hal/hal_arch.h> // basic machine info
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61 #include <cyg/hal/hal_intr.h> // interrupt macros
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62 #include <cyg/hal/hal_io.h> // IO macros
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63 #include <cyg/hal/hal_if.h> // calling interface API
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64 #include <cyg/hal/hal_misc.h> // helper functions
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65 #include <cyg/hal/hal_diag.h>
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66 #include <cyg/hal/hal_iop310.h> // Hardware definitions
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67 #include <cyg/hal/drv_api.h> // cyg_drv_interrupt_acknowledge
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68
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69
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70 static void cyg_hal_plf_serial_init(void);
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71
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72 void
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73 cyg_hal_plf_comms_init(void)
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74 {
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75 static int initialized = 0;
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76
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77 if (initialized)
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78 return;
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79
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80 initialized = 1;
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81
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82 cyg_hal_plf_serial_init();
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83 }
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84
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85 //=============================================================================
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86 // Serial driver
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87 //=============================================================================
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88
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89 //-----------------------------------------------------------------------------
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90 // Based on 3.6864 MHz xtal
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91 struct baud_config {
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92 cyg_int32 baud_rate;
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93 cyg_uint8 msb;
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94 cyg_uint8 lsb;
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95 };
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96
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97 struct baud_config baud_conf[] = {
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98 {9600, 0x00, 0x0c},
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99 {19200, 0x00, 0x06},
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100 {38400, 0x00, 0x03},
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101 {57600, 0x00, 0x02},
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102 {115200, 0x00, 0x01}};
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103
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104 //-----------------------------------------------------------------------------
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105 // Define the serial registers. The Cogent board is equipped with a 16552
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106 // serial chip.
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107 #define CYG_DEV_SERIAL_RBR 0x00 // receiver buffer register, read, dlab = 0
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108 #define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
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109 #define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
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110 #define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0
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111 #define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
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112 #define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0
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113 #define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0
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114 #define CYG_DEV_SERIAL_LCR 0x03 // line control register, write
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115 #define CYG_DEV_SERIAL_MCR 0x04 // modem control register, write
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116 #define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
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117 #define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
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118 #define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
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119
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120 // The interrupt enable register bits.
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121 #define SIO_IER_ERDAI 0x01 // enable received data available irq
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122 #define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
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123 #define SIO_IER_ELSI 0x04 // enable receiver line status irq
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124 #define SIO_IER_EMSI 0x08 // enable modem status interrupt
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125
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126 // The interrupt identification register bits.
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127 #define SIO_IIR_IP 0x01 // 0 if interrupt pending
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128 #define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
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129 #define ISR_Tx 0x02
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130 #define ISR_Rx 0x04
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131
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132 // The line status register bits.
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133 #define SIO_LSR_DR 0x01 // data ready
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134 #define SIO_LSR_OE 0x02 // overrun error
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135 #define SIO_LSR_PE 0x04 // parity error
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136 #define SIO_LSR_FE 0x08 // framing error
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137 #define SIO_LSR_BI 0x10 // break interrupt
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138 #define SIO_LSR_THRE 0x20 // transmitter holding register empty
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139 #define SIO_LSR_TEMT 0x40 // transmitter register empty
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140 #define SIO_LSR_ERR 0x80 // any error condition
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141
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142 // The modem status register bits.
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143 #define SIO_MSR_DCTS 0x01 // delta clear to send
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144 #define SIO_MSR_DDSR 0x02 // delta data set ready
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145 #define SIO_MSR_TERI 0x04 // trailing edge ring indicator
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146 #define SIO_MSR_DDCD 0x08 // delta data carrier detect
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147 #define SIO_MSR_CTS 0x10 // clear to send
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148 #define SIO_MSR_DSR 0x20 // data set ready
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149 #define SIO_MSR_RI 0x40 // ring indicator
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150 #define SIO_MSR_DCD 0x80 // data carrier detect
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151
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152 // The line control register bits.
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153 #define SIO_LCR_WLS0 0x01 // word length select bit 0
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154 #define SIO_LCR_WLS1 0x02 // word length select bit 1
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155 #define SIO_LCR_STB 0x04 // number of stop bits
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156 #define SIO_LCR_PEN 0x08 // parity enable
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157 #define SIO_LCR_EPS 0x10 // even parity select
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158 #define SIO_LCR_SP 0x20 // stick parity
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159 #define SIO_LCR_SB 0x40 // set break
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160 #define SIO_LCR_DLAB 0x80 // divisor latch access bit
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161
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162 // The FIFO control register
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163 #define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
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164 #define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
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165 #define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
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166
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167
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168 //-----------------------------------------------------------------------------
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169 typedef struct {
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170 cyg_uint8* base;
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171 cyg_int32 msec_timeout;
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172 int isr_vector;
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173 cyg_int32 baud_rate;
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174 } channel_data_t;
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175
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176 //-----------------------------------------------------------------------------
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177 static int
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178 set_baud( channel_data_t *chan )
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179 {
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180 cyg_uint8* base = chan->base;
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181 cyg_uint8 i;
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182
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183 for (i=0; i<(sizeof(baud_conf)/sizeof(baud_conf[0])); i++)
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184 {
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185 if (chan->baud_rate == baud_conf[i].baud_rate) {
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186 cyg_uint8 lcr;
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187 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
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188 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr|SIO_LCR_DLAB);
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189 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLL, baud_conf[i].lsb);
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190 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLM, baud_conf[i].msb);
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191 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
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192 return 1;
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193 }
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194 }
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195 return -1;
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196 }
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197
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198 static void
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199 init_serial_channel(channel_data_t* __ch_data)
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200 {
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201 cyg_uint8* base = __ch_data->base;
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202 channel_data_t* chan = (channel_data_t*)__ch_data;
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203
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204 // 8-1-no parity.
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205 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1);
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206 chan->baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD;
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207 set_baud( chan );
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208 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, 0x07); // Enable & clear FIFO
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209 }
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210
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211 static cyg_bool
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212 cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
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213 {
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214 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
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215 cyg_uint8 lsr;
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216
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217 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
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218 if ((lsr & SIO_LSR_DR) == 0)
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219 return false;
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220
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221 HAL_READ_UINT8(base+CYG_DEV_SERIAL_RBR, *ch);
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222
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223 return true;
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224 }
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225
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226
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227 cyg_uint8
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228 cyg_hal_plf_serial_getc(void* __ch_data)
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229 {
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230 cyg_uint8 ch;
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231 CYGARC_HAL_SAVE_GP();
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232
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233 while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
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234
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235 CYGARC_HAL_RESTORE_GP();
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236 return ch;
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237 }
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238
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239 void
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240 cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 c)
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241 {
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242 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
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243 cyg_uint8 lsr;
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244 CYGARC_HAL_SAVE_GP();
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245
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246 do {
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247 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
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248 } while ((lsr & SIO_LSR_THRE) == 0);
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249
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250 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_THR, c);
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251
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252 // Hang around until the character has been safely sent.
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253 do {
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254 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
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255 } while ((lsr & SIO_LSR_THRE) == 0);
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256
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257 CYGARC_HAL_RESTORE_GP();
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258 }
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259
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260 static channel_data_t channels[2] = {
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261 #if CYGHWR_HAL_ARM_IOP310_SERIAL_PORTA != 0
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262 { (cyg_uint8*)IOP310_SERIAL_PORT_A, 1000, CYGNUM_HAL_INTERRUPT_SERIAL_A},
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263 #endif
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264 #if CYGHWR_HAL_ARM_IOP310_SERIAL_PORTB != 0
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265 { (cyg_uint8*)IOP310_SERIAL_PORT_B, 1000, CYGNUM_HAL_INTERRUPT_SERIAL_B},
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266 #endif
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267 };
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268
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269 static void
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270 cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
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271 cyg_uint32 __len)
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272 {
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273 CYGARC_HAL_SAVE_GP();
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274
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275 while(__len-- > 0)
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276 cyg_hal_plf_serial_putc(__ch_data, *__buf++);
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277
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278 CYGARC_HAL_RESTORE_GP();
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279 }
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280
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281 static void
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282 cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
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283 {
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284 CYGARC_HAL_SAVE_GP();
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285
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286 while(__len-- > 0)
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287 *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
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288
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289 CYGARC_HAL_RESTORE_GP();
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290 }
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291
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292 cyg_bool
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293 cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
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294 {
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295 int delay_count;
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296 channel_data_t* chan = (channel_data_t*)__ch_data;
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297 cyg_bool res;
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298 CYGARC_HAL_SAVE_GP();
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299
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300 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
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301 for(;;) {
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302 res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
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303 if (res || 0 == delay_count--)
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304 break;
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305
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306 CYGACC_CALL_IF_DELAY_US(100);
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307 }
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308
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309 CYGARC_HAL_RESTORE_GP();
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310 return res;
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311 }
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312
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313 static int
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314 cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
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315 {
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316 static int irq_state = 0;
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317 channel_data_t* chan = (channel_data_t*)__ch_data;
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318 cyg_uint8 ier;
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319 int ret = 0;
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320 CYGARC_HAL_SAVE_GP();
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321
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322 switch (__func) {
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323 case __COMMCTL_IRQ_ENABLE:
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324 HAL_INTERRUPT_UNMASK(chan->isr_vector);
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325 HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
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326 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
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327 ier |= SIO_IER_ERDAI;
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328 HAL_WRITE_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
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329 irq_state = 1;
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330 break;
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331 case __COMMCTL_IRQ_DISABLE:
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332 ret = irq_state;
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333 irq_state = 0;
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334 HAL_INTERRUPT_MASK(chan->isr_vector);
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gthomas
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335 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
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gthomas
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diff changeset
336 ier &= ~SIO_IER_ERDAI;
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
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337 HAL_WRITE_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
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338 break;
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diff changeset
339 case __COMMCTL_DBG_ISR_VECTOR:
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
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340 ret = chan->isr_vector;
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
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341 break;
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gthomas
parents:
diff changeset
342 case __COMMCTL_SET_TIMEOUT:
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
343 {
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344 va_list ap;
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345
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346 va_start(ap, __func);
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347
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348 ret = chan->msec_timeout;
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349 chan->msec_timeout = va_arg(ap, cyg_uint32);
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350
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351 va_end(ap);
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gthomas
parents:
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352 }
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diff changeset
353 case __COMMCTL_GETBAUD:
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gthomas
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354 ret = chan->baud_rate;
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gthomas
parents:
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355 break;
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gthomas
parents:
diff changeset
356 case __COMMCTL_SETBAUD:
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gthomas
parents:
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357 {
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358 va_list ap;
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gthomas
parents:
diff changeset
359 va_start(ap, __func);
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gthomas
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360 chan->baud_rate = va_arg(ap, cyg_int32);
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gthomas
parents:
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361 va_end(ap);
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gthomas
parents:
diff changeset
362 ret = set_baud(chan);
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gthomas
parents:
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363 break;
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gthomas
parents:
diff changeset
364 }
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
365 default:
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gthomas
parents:
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366 break;
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gthomas
parents:
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367 }
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gthomas
parents:
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368 CYGARC_HAL_RESTORE_GP();
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gthomas
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369 return ret;
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gthomas
parents:
diff changeset
370 }
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gthomas
parents:
diff changeset
371
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372 static int
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373 cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
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gthomas
parents:
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374 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
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375 {
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gthomas
parents:
diff changeset
376 channel_data_t* chan = (channel_data_t*)__ch_data;
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gthomas
parents:
diff changeset
377 cyg_uint8 _iir;
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gthomas
parents:
diff changeset
378 int res = 0;
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gthomas
parents:
diff changeset
379 CYGARC_HAL_SAVE_GP();
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gthomas
parents:
diff changeset
380
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gthomas
parents:
diff changeset
381 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IIR, _iir);
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gthomas
parents:
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382 _iir &= SIO_IIR_ID_MASK;
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gthomas
parents:
diff changeset
383
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gthomas
parents:
diff changeset
384 *__ctrlc = 0;
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gthomas
parents:
diff changeset
385 if ( ISR_Rx == _iir ) {
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gthomas
parents:
diff changeset
386 cyg_uint8 c, lsr;
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gthomas
parents:
diff changeset
387 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_LSR, lsr);
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gthomas
parents:
diff changeset
388 if (lsr & SIO_LSR_DR) {
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gthomas
parents:
diff changeset
389
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gthomas
parents:
diff changeset
390 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_RBR, c);
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gthomas
parents:
diff changeset
391
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gthomas
parents:
diff changeset
392 if( cyg_hal_is_break( &c , 1 ) )
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gthomas
parents:
diff changeset
393 *__ctrlc = 1;
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
394 }
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
395
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
396 // Acknowledge the interrupt
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
397 HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
398 res = CYG_ISR_HANDLED;
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
399 }
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
400
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
401 CYGARC_HAL_RESTORE_GP();
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
402 return res;
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
403 }
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
404
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
405 static void
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
406 cyg_hal_plf_serial_init(void)
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
407 {
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
408 hal_virtual_comm_table_t* comm;
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
409 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
410
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
411 // Disable interrupts.
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
412 HAL_INTERRUPT_MASK(channels[0].isr_vector);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
413 #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
414 HAL_INTERRUPT_MASK(channels[1].isr_vector);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
415 #endif
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
416
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
417 // Init channels
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
418 init_serial_channel(&channels[0]);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
419 #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
420 init_serial_channel(&channels[1]);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
421 #endif
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
422
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
423 // Setup procs in the vector table
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
424
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
425 // Set channel 0
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
426 CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
427 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
428 CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
429 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
430 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
431 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
432 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
433 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
434 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
435 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
436
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
437 #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
438 // Set channel 1
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
439 CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
440 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
441 CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
442 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
443 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
444 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
445 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
446 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
447 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
448 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
449 #endif
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
450
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
451 // Restore original console
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
452 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
453 }
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
454
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
455 /*---------------------------------------------------------------------------*/
de449c532876 Add NPWR Linux Engine, update Xscale IOP310 based platforms
gthomas
parents:
diff changeset
456 /* End of hal_diag.c */