Mercurial > ecos-v3_0-branch
annotate packages/hal/arm/xscale/ixp425/current/src/ixp425_diag.c @ 2729:74dbf4c3f2e1 after-copyright-change-20090129
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
| author | jlarmour |
|---|---|
| date | Thu, 29 Jan 2009 17:47:46 +0000 |
| parents | d6cfbed66cf9 |
| children |
| rev | line source |
|---|---|
| 835 | 1 /*============================================================================= |
| 2 // | |
| 3 // ixp425_diag.c | |
| 4 // | |
| 5 // HAL diagnostic output code | |
| 6 // | |
| 7 //============================================================================= | |
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8 // ####ECOSGPLCOPYRIGHTBEGIN#### |
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9 // ------------------------------------------- |
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10 // This file is part of eCos, the Embedded Configurable Operating System. |
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74dbf4c3f2e1
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
| 835 | 12 // |
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13 // eCos is free software; you can redistribute it and/or modify it under |
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74dbf4c3f2e1
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14 // the terms of the GNU General Public License as published by the Free |
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15 // Software Foundation; either version 2 or (at your option) any later |
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16 // version. |
| 835 | 17 // |
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT |
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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21 // for more details. |
| 835 | 22 // |
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23 // You should have received a copy of the GNU General Public License |
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24 // along with eCos; if not, write to the Free Software Foundation, Inc., |
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
| 835 | 26 // |
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27 // As a special exception, if other files instantiate templates or use |
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28 // macros or inline functions from this file, or you compile this file |
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29 // and link it with other works to produce a work based on this file, |
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30 // this file does not by itself cause the resulting work to be covered by |
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31 // the GNU General Public License. However the source code for this file |
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32 // must still be made available in accordance with section (3) of the GNU |
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33 // General Public License v2. |
| 835 | 34 // |
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35 // This exception does not invalidate any other reasons why a work based |
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74dbf4c3f2e1
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jlarmour
parents:
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36 // on this file might be covered by the GNU General Public License. |
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74dbf4c3f2e1
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jlarmour
parents:
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37 // ------------------------------------------- |
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38 // ####ECOSGPLCOPYRIGHTEND#### |
| 835 | 39 //============================================================================= |
| 40 //#####DESCRIPTIONBEGIN#### | |
| 41 // | |
| 42 // Author(s): msalter | |
| 43 // Contributors:msalter | |
| 44 // Date: 2002-12-08 | |
| 45 // Purpose: HAL diagnostic output | |
| 46 // Description: Implementations of HAL diagnostic output support. | |
| 47 // | |
| 48 //####DESCRIPTIONEND#### | |
| 49 // | |
| 50 //===========================================================================*/ | |
| 51 | |
| 52 #include <pkgconf/hal.h> | |
| 53 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration | |
| 54 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration | |
| 55 | |
| 56 #include <cyg/infra/cyg_type.h> // base types | |
| 57 #include <cyg/infra/cyg_trac.h> // tracing macros | |
| 58 #include <cyg/infra/cyg_ass.h> // assertion macros | |
| 59 | |
| 60 #include <cyg/hal/hal_arch.h> // basic machine info | |
| 61 #include <cyg/hal/hal_intr.h> // interrupt macros | |
| 62 #include <cyg/hal/hal_io.h> // IO macros | |
| 63 #include <cyg/hal/hal_diag.h> | |
| 64 #include <cyg/hal/drv_api.h> | |
| 65 #include <cyg/hal/hal_if.h> // interface API | |
| 66 #include <cyg/hal/hal_misc.h> // Helper functions | |
| 67 | |
| 68 #if !defined(CYGSEM_HAL_IXP425_PLF_USES_UART1) && !defined(CYGSEM_HAL_IXP425_PLF_USES_UART2) | |
| 69 #define IXP425_NUM_UARTS 0 | |
| 70 #elif defined(CYGSEM_HAL_IXP425_PLF_USES_UART1) && defined(CYGSEM_HAL_IXP425_PLF_USES_UART2) | |
| 71 #define IXP425_NUM_UARTS 2 | |
| 72 #else | |
| 73 #define IXP425_NUM_UARTS 1 | |
| 74 #endif | |
| 75 | |
| 76 #if IXP425_NUM_UARTS > 0 | |
| 77 | |
| 78 /*---------------------------------------------------------------------------*/ | |
| 79 /* 16550 compatible UARTS */ | |
| 80 | |
| 81 // Define the serial registers. | |
| 82 #define CYG_DEV_RBR 0x00 // receiver buffer register, read, dlab = 0 | |
| 83 #define CYG_DEV_THR 0x00 // transmitter holding register, write, dlab = 0 | |
| 84 #define CYG_DEV_DLL 0x00 // divisor latch (LS), read/write, dlab = 1 | |
| 85 #define CYG_DEV_IER 0x01 // interrupt enable register, read/write, dlab = 0 | |
| 86 #define CYG_DEV_DLM 0x01 // divisor latch (MS), read/write, dlab = 1 | |
| 87 #define CYG_DEV_IIR 0x02 // interrupt identification register, read, dlab = 0 | |
| 88 #define CYG_DEV_FCR 0x02 // fifo control register, write, dlab = 0 | |
| 89 #define CYG_DEV_LCR 0x03 // line control register, write | |
| 90 #define CYG_DEV_MCR 0x04 // modem control register, write | |
| 91 #define CYG_DEV_LSR 0x05 // line status register, read | |
| 92 #define CYG_DEV_MSR 0x06 // modem status register, read | |
| 93 #define CYG_DEV_SCR 0x07 // scratch pad register | |
| 94 | |
| 95 // Interrupt Enable Register | |
| 96 #define SIO_IER_RCV 0x01 | |
| 97 #define SIO_IER_XMT 0x02 | |
| 98 #define SIO_IER_LS 0x04 | |
| 99 #define SIO_IER_MS 0x08 | |
| 100 #define SIO_IER_UUE 0x40 // UART Unit Enable | |
| 101 | |
| 102 // The line status register bits. | |
| 103 #define SIO_LSR_DR 0x01 // data ready | |
| 104 #define SIO_LSR_OE 0x02 // overrun error | |
| 105 #define SIO_LSR_PE 0x04 // parity error | |
| 106 #define SIO_LSR_FE 0x08 // framing error | |
| 107 #define SIO_LSR_BI 0x10 // break interrupt | |
| 108 #define SIO_LSR_THRE 0x20 // transmitter holding register empty | |
| 109 #define SIO_LSR_TEMT 0x40 // transmitter register empty | |
| 110 #define SIO_LSR_ERR 0x80 // any error condition | |
| 111 | |
| 112 // The modem status register bits. | |
| 113 #define SIO_MSR_DCTS 0x01 // delta clear to send | |
| 114 #define SIO_MSR_DDSR 0x02 // delta data set ready | |
| 115 #define SIO_MSR_TERI 0x04 // trailing edge ring indicator | |
| 116 #define SIO_MSR_DDCD 0x08 // delta data carrier detect | |
| 117 #define SIO_MSR_CTS 0x10 // clear to send | |
| 118 #define SIO_MSR_DSR 0x20 // data set ready | |
| 119 #define SIO_MSR_RI 0x40 // ring indicator | |
| 120 #define SIO_MSR_DCD 0x80 // data carrier detect | |
| 121 | |
| 122 // The line control register bits. | |
| 123 #define SIO_LCR_WLS0 0x01 // word length select bit 0 | |
| 124 #define SIO_LCR_WLS1 0x02 // word length select bit 1 | |
| 125 #define SIO_LCR_STB 0x04 // number of stop bits | |
| 126 #define SIO_LCR_PEN 0x08 // parity enable | |
| 127 #define SIO_LCR_EPS 0x10 // even parity select | |
| 128 #define SIO_LCR_SP 0x20 // stick parity | |
| 129 #define SIO_LCR_SB 0x40 // set break | |
| 130 #define SIO_LCR_DLAB 0x80 // divisor latch access bit | |
| 131 | |
| 132 // Modem Control Register | |
| 133 #define SIO_MCR_DTR 0x01 | |
| 134 #define SIO_MCR_RTS 0x02 | |
| 135 #define SIO_MCR_OUT1 0x04 | |
| 136 #define SIO_MCR_OUT2 0x08 | |
| 137 #define SIO_MCR_LOOP 0x10 | |
| 138 #define SIO_MCR_AFE 0x20 | |
| 139 | |
| 140 #define UART1_BASE 0xC8000000 | |
| 141 #define UART2_BASE 0xC8001000 | |
| 142 | |
| 143 //----------------------------------------------------------------------------- | |
| 144 typedef struct { | |
| 145 cyg_uint32* base; | |
| 146 cyg_int32 msec_timeout; | |
| 147 int isr_vector; | |
| 148 cyg_int32 baud_rate; | |
| 149 } channel_data_t; | |
| 150 | |
| 151 | |
| 152 //----------------------------------------------------------------------------- | |
| 153 // Based on 14.7456 MHz xtal | |
| 154 static int | |
| 155 set_baud( channel_data_t *chan ) | |
| 156 { | |
| 157 cyg_uint32* base = chan->base; | |
| 158 cyg_uint16 div = 921600 / chan->baud_rate; | |
| 159 cyg_uint32 lcr; | |
| 160 | |
| 161 HAL_READ_UINT32(base+CYG_DEV_LCR, lcr); | |
| 162 HAL_WRITE_UINT32(base+CYG_DEV_LCR, lcr|SIO_LCR_DLAB); | |
| 163 HAL_WRITE_UINT32(base+CYG_DEV_DLL, div & 0xff); | |
| 164 HAL_WRITE_UINT32(base+CYG_DEV_DLM, (div >> 8) & 0xff); | |
| 165 HAL_WRITE_UINT32(base+CYG_DEV_LCR, lcr); | |
| 166 return 1; | |
| 167 } | |
| 168 | |
| 169 static void | |
| 170 cyg_hal_plf_serial_init_channel(void* __ch_data) | |
| 171 { | |
| 172 cyg_uint32* base = ((channel_data_t*)__ch_data)->base; | |
| 173 channel_data_t* chan = (channel_data_t*)__ch_data; | |
| 174 | |
| 175 HAL_WRITE_UINT32(chan->base+CYG_DEV_IER, SIO_IER_UUE); | |
| 176 | |
| 177 // 8-1-no parity. | |
| 178 HAL_WRITE_UINT32(base+CYG_DEV_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1); | |
| 179 chan->baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD; | |
| 180 set_baud( chan ); | |
| 181 HAL_WRITE_UINT32(base+CYG_DEV_FCR, 0x07); // Enable & clear FIFO | |
| 182 HAL_WRITE_UINT32(base+CYG_DEV_MCR, SIO_MCR_OUT2); // Enable interrupt to core | |
| 183 } | |
| 184 | |
| 185 void | |
| 186 cyg_hal_plf_serial_putc(void *__ch_data, char c) | |
| 187 { | |
| 188 cyg_uint32* base = ((channel_data_t*)__ch_data)->base; | |
| 189 cyg_uint32 lsr, val; | |
| 190 CYGARC_HAL_SAVE_GP(); | |
| 191 | |
| 192 do { | |
| 193 HAL_READ_UINT32(base+CYG_DEV_LSR, lsr); | |
| 194 } while ((lsr & SIO_LSR_THRE) == 0); | |
| 195 | |
| 196 val = c; | |
| 197 HAL_WRITE_UINT32(base+CYG_DEV_THR, val); | |
| 198 | |
| 199 CYGARC_HAL_RESTORE_GP(); | |
| 200 } | |
| 201 | |
| 202 static cyg_bool | |
| 203 cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) | |
| 204 { | |
| 205 cyg_uint32* base = ((channel_data_t*)__ch_data)->base; | |
| 206 cyg_uint32 lsr, val; | |
| 207 | |
| 208 HAL_READ_UINT32(base+CYG_DEV_LSR, lsr); | |
| 209 if ((lsr & SIO_LSR_DR) == 0) | |
| 210 return false; | |
| 211 | |
| 212 HAL_READ_UINT32(base+CYG_DEV_RBR, val); | |
| 213 *ch = val; | |
| 214 | |
| 215 return true; | |
| 216 } | |
| 217 | |
| 218 cyg_uint8 | |
| 219 cyg_hal_plf_serial_getc(void* __ch_data) | |
| 220 { | |
| 221 cyg_uint8 ch; | |
| 222 CYGARC_HAL_SAVE_GP(); | |
| 223 | |
| 224 while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); | |
| 225 | |
| 226 CYGARC_HAL_RESTORE_GP(); | |
| 227 return ch; | |
| 228 } | |
| 229 | |
| 230 static channel_data_t plf_ser_channels[] = { | |
| 231 #if defined(CYGSEM_HAL_IXP425_PLF_USES_UART1) && !defined(HAL_PLATFORM_UART2_FIRST) | |
| 232 { (cyg_uint32*)UART1_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART1 }, | |
| 233 #endif | |
| 234 #if defined(CYGSEM_HAL_IXP425_PLF_USES_UART2) | |
| 235 { (cyg_uint32*)UART2_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART2 } | |
| 236 #endif | |
| 237 #if defined(CYGSEM_HAL_IXP425_PLF_USES_UART1) && defined(HAL_PLATFORM_UART2_FIRST) | |
| 238 { (cyg_uint32*)UART1_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART1 }, | |
| 239 #endif | |
| 240 }; | |
| 241 | |
| 242 static void | |
| 243 cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, | |
| 244 cyg_uint32 __len) | |
| 245 { | |
| 246 CYGARC_HAL_SAVE_GP(); | |
| 247 | |
| 248 while(__len-- > 0) | |
| 249 cyg_hal_plf_serial_putc(__ch_data, *__buf++); | |
| 250 | |
| 251 CYGARC_HAL_RESTORE_GP(); | |
| 252 } | |
| 253 | |
| 254 static void | |
| 255 cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) | |
| 256 { | |
| 257 CYGARC_HAL_SAVE_GP(); | |
| 258 | |
| 259 while(__len-- > 0) | |
| 260 *__buf++ = cyg_hal_plf_serial_getc(__ch_data); | |
| 261 | |
| 262 CYGARC_HAL_RESTORE_GP(); | |
| 263 } | |
| 264 | |
| 265 cyg_bool | |
| 266 cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) | |
| 267 { | |
| 268 int delay_count; | |
| 269 channel_data_t* chan = (channel_data_t*)__ch_data; | |
| 270 cyg_bool res; | |
| 271 CYGARC_HAL_SAVE_GP(); | |
| 272 | |
| 273 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps | |
| 274 | |
| 275 for(;;) { | |
| 276 res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); | |
| 277 if (res || 0 == delay_count--) | |
| 278 break; | |
| 279 | |
| 280 CYGACC_CALL_IF_DELAY_US(100); | |
| 281 } | |
| 282 | |
| 283 CYGARC_HAL_RESTORE_GP(); | |
| 284 return res; | |
| 285 } | |
| 286 | |
| 287 static int | |
| 288 cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) | |
| 289 { | |
| 290 static int irq_state = 0; | |
| 291 channel_data_t* chan = (channel_data_t*)__ch_data; | |
| 292 int ret = 0; | |
| 293 CYGARC_HAL_SAVE_GP(); | |
| 294 | |
| 295 switch (__func) { | |
| 296 case __COMMCTL_IRQ_ENABLE: | |
| 297 irq_state = 1; | |
| 298 | |
| 299 HAL_WRITE_UINT32(chan->base+CYG_DEV_IER, SIO_IER_RCV | SIO_IER_UUE); | |
| 300 HAL_INTERRUPT_UNMASK(chan->isr_vector); | |
| 301 break; | |
| 302 case __COMMCTL_IRQ_DISABLE: | |
| 303 ret = irq_state; | |
| 304 irq_state = 0; | |
| 305 | |
| 306 HAL_WRITE_UINT32(chan->base+CYG_DEV_IER, SIO_IER_UUE); | |
| 307 HAL_INTERRUPT_MASK(chan->isr_vector); | |
| 308 break; | |
| 309 case __COMMCTL_DBG_ISR_VECTOR: | |
| 310 ret = chan->isr_vector; | |
| 311 break; | |
| 312 case __COMMCTL_SET_TIMEOUT: | |
| 313 { | |
| 314 va_list ap; | |
| 315 | |
| 316 va_start(ap, __func); | |
| 317 | |
| 318 ret = chan->msec_timeout; | |
| 319 chan->msec_timeout = va_arg(ap, cyg_uint32); | |
| 320 | |
| 321 va_end(ap); | |
| 322 } | |
| 323 case __COMMCTL_GETBAUD: | |
| 324 ret = chan->baud_rate; | |
| 325 break; | |
| 326 case __COMMCTL_SETBAUD: | |
| 327 { | |
| 328 cyg_uint32 b; | |
| 329 va_list ap; | |
| 330 | |
| 331 va_start(ap, __func); | |
| 332 b = va_arg(ap, cyg_int32); | |
| 333 va_end(ap); | |
| 334 | |
| 335 if (b < 300 || b > 115200) | |
| 336 ret = -1; | |
| 337 else { | |
| 338 chan->baud_rate = b; | |
| 339 ret = set_baud(chan); | |
| 340 } | |
| 341 break; | |
| 342 } | |
| 343 default: | |
| 344 break; | |
| 345 } | |
| 346 CYGARC_HAL_RESTORE_GP(); | |
| 347 return ret; | |
| 348 } | |
| 349 | |
| 350 static int | |
| 351 cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, | |
| 352 CYG_ADDRWORD __vector, CYG_ADDRWORD __data) | |
| 353 { | |
| 354 int res = 0; | |
| 355 channel_data_t* chan = (channel_data_t*)__ch_data; | |
| 356 char c; | |
| 357 cyg_uint8 lsr; | |
| 358 CYGARC_HAL_SAVE_GP(); | |
| 359 | |
| 360 cyg_drv_interrupt_acknowledge(chan->isr_vector); | |
| 361 | |
| 362 *__ctrlc = 0; | |
| 363 HAL_READ_UINT32(chan->base+CYG_DEV_LSR, lsr); | |
| 364 if ( (lsr & SIO_LSR_DR) != 0 ) { | |
| 365 | |
| 366 HAL_READ_UINT32(chan->base+CYG_DEV_RBR, c); | |
| 367 if( cyg_hal_is_break( &c , 1 ) ) | |
| 368 *__ctrlc = 1; | |
| 369 | |
| 370 res = CYG_ISR_HANDLED; | |
| 371 } | |
| 372 | |
| 373 CYGARC_HAL_RESTORE_GP(); | |
| 374 return res; | |
| 375 } | |
| 376 | |
| 377 void | |
| 378 cyg_hal_ixp425_serial_init(void) | |
| 379 { | |
| 380 hal_virtual_comm_table_t* comm; | |
| 381 int i, cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); | |
| 382 | |
| 383 for (i = 0; i < IXP425_NUM_UARTS; i++) { | |
| 384 | |
| 385 // Disable interrupts. | |
| 386 HAL_INTERRUPT_MASK(plf_ser_channels[i].isr_vector); | |
| 387 | |
| 388 // Init channels | |
| 389 cyg_hal_plf_serial_init_channel(&plf_ser_channels[i]); | |
| 390 | |
| 391 // Setup procs in the vector table | |
| 392 CYGACC_CALL_IF_SET_CONSOLE_COMM(i); | |
| 393 comm = CYGACC_CALL_IF_CONSOLE_PROCS(); | |
| 394 CYGACC_COMM_IF_CH_DATA_SET(*comm, &plf_ser_channels[i]); | |
| 395 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); | |
| 396 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); | |
| 397 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); | |
| 398 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); | |
| 399 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); | |
| 400 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); | |
| 401 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); | |
| 402 } | |
| 403 // Restore original console | |
| 404 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); | |
| 405 } | |
| 406 | |
| 407 // If the platform provides some channels of its own, then this function will be | |
| 408 // provided by that platform. | |
| 409 #if !defined(CYGNUM_HAL_IXP425_PLF_SERIAL_CHANNELS) || !CYGNUM_HAL_IXP425_PLF_SERIAL_CHANNELS | |
| 410 void | |
| 411 cyg_hal_plf_comms_init(void) | |
| 412 { | |
| 413 static int initialized = 0; | |
| 414 | |
| 415 if (initialized) | |
| 416 return; | |
| 417 | |
| 418 initialized = 1; | |
| 419 | |
| 420 cyg_hal_ixp425_serial_init(); | |
| 421 } | |
| 422 #endif | |
| 423 | |
| 424 #endif // IXP425_NUM_UARTS > 0 | |
| 425 | |
| 426 /*---------------------------------------------------------------------------*/ | |
| 427 | |
| 428 void | |
| 429 hal_diag_led(int n) | |
| 430 { | |
| 431 } | |
| 432 | |
| 433 /*---------------------------------------------------------------------------*/ | |
| 434 /* End of hal_diag.c */ |