annotate packages/hal/coldfire/m5272c3/current/src/plf_startup.c @ 2729:74dbf4c3f2e1 after-copyright-change-20090129

Update all copyright banners to reflect FSF ownership; fix and improve licence text.
author jlarmour
date Thu, 29 Jan 2009 17:47:46 +0000
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1 //==========================================================================
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2 //
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3 // plf_startup.c
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4 //
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5 // M5272C3 platform HAL startup code
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6 //
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7 //==========================================================================
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8 // ####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later
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16 // version.
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17 //
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 // for more details.
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22 //
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23 // You should have received a copy of the GNU General Public License
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24 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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26 //
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27 // As a special exception, if other files instantiate templates or use
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28 // macros or inline functions from this file, or you compile this file
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29 // and link it with other works to produce a work based on this file,
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30 // this file does not by itself cause the resulting work to be covered by
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31 // the GNU General Public License. However the source code for this file
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32 // must still be made available in accordance with section (3) of the GNU
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33 // General Public License v2.
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34 //
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35 // This exception does not invalidate any other reasons why a work based
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36 // on this file might be covered by the GNU General Public License.
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37 // -------------------------------------------
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38 // ####ECOSGPLCOPYRIGHTEND####
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39 //==========================================================================
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40 //#####DESCRIPTIONBEGIN####
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41 //
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42 // Author(s): Enrico Piria
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43 // Contributors:
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44 // Date: 2005-25-06
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45 // Purpose: Platform startup code.
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46 // Description: This module contains code that sets up the platform specific
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47 // hardware and data. All the code must be contained in the
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48 // section called ".boot", in order for the ROMRAM startup
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49 // to work properly.
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50 //
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51 //####DESCRIPTIONEND####
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52 //========================================================================
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53
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54 #include <cyg/infra/cyg_type.h>
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55 #include <pkgconf/hal.h>
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56 #include <cyg/hal/hal_startup.h>
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57 #include CYGHWR_MEMORY_LAYOUT_H
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58 #include <cyg/hal/hal_arch.h>
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59 #include <cyg/hal/hal_io.h>
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60 #include <cyg/hal/coldfire_regs.h>
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61
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62 static void plf_init_sim(void) __attribute__ ((section (".boot")));
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63 static void plf_init_intc(void) __attribute__ ((section (".boot")));
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64 static void plf_init_cs(void) __attribute__ ((section (".boot")));
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65 static void plf_init_sdramc(void) __attribute__ ((section (".boot")));
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66 static void plf_init_cache_acr(void) __attribute__ ((section (".boot")));
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67
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68
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69 // Platform-specific reset vector initialization routine
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70 void plf_reset(void)
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71 {
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72 plf_init_sim();
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73 plf_init_intc();
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74 plf_init_cs();
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75 plf_init_sdramc();
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76
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77 // Call a routine to set up the cache and ACRs for this specific
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78 // platform.
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79 plf_init_cache_acr();
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80 }
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81
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82
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83 // Initialize the cache and access control registers.
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84 // The reset procedure already invalidated the cache and ACRs.
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85 // This routine only needs to enable the ACRs that it will use.
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86 static void plf_init_cache_acr(void)
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87 {
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88 // Enable the instruction cache with the following options:
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89 // Enable CPUSHL invalidation.
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90 // No freeze.
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91 // Invalidate all cache lines (flush).
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92 // No external arbiter control.
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93 // Disable non-cacheable instruction bursting.
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94 // Default memory is cacheable.
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95 // Enable buffered writes.
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96 // Read and write access permitted by default.
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97 // Instruction fetch size is cache line.
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98
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99 #ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
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100 CYGARC_MOVEC((CYG_WORD32) 0x81000102, CYGARC_REG_CACR);
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101 #endif
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102
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103 // Leave the access control registers disabled.
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104 }
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105
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106
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107 // Initialize SIM module and system configuration registers
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108 void plf_init_sim(void)
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109 {
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110 // Set up the mapping of our internal registers. The LSB indicates that
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111 // the register contents are valid.
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112 CYGARC_MOVEC((CYG_WORD32)(CYGMEM_REGION_devs | 1), CYGARC_REG_MBAR);
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113
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114 // Initialize System Config Register
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115 // Setup Watch Dog Timeout
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116 HAL_WRITE_UINT16(&MCF5272_DEVS->cfg.scr, MCF5272_SIM_SCR_HWWD_1024);
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117
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118 // Initialize System Protection Register
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119 // Enable all bus error exceptions
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120 HAL_WRITE_UINT16(&MCF5272_DEVS->cfg.spr,
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121 (0 | MCF5272_SIM_SPR_ADC | MCF5272_SIM_SPR_ADCEN
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122 | MCF5272_SIM_SPR_WPV | MCF5272_SIM_SPR_WPVEN
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123 | MCF5272_SIM_SPR_SMV | MCF5272_SIM_SPR_SMVEN
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124 | MCF5272_SIM_SPR_SBE | MCF5272_SIM_SPR_SBEEN
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125 | MCF5272_SIM_SPR_HWT | MCF5272_SIM_SPR_HWTEN
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126 | MCF5272_SIM_SPR_RPV | MCF5272_SIM_SPR_RPVEN
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127 | MCF5272_SIM_SPR_EXT | MCF5272_SIM_SPR_EXTEN
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128 | MCF5272_SIM_SPR_SUV | MCF5272_SIM_SPR_SUVEN
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129 )) ;
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130 }
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131
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132
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133 // Initialize interrupt controller
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134 void plf_init_intc(void)
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135 {
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136 int i;
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137
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138 // Initialize the vector base register in the interrupt controller.
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139 HAL_WRITE_UINT8(&MCF5272_DEVS->intc.ipvr, HAL_PROG_INT_VEC_BASE);
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140
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141 // Initialize the interrupt control register.
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142 // Disable all interrupts by setting all priorities to zero.
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143 for (i = 0; i < 4; i++)
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144 {
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145 HAL_WRITE_UINT32(&MCF5272_DEVS->intc.icr[i], 0x88888888);
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146 }
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147
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148 // Initialize the processor's vector base register (align to 1M boundary).
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149 CYGARC_MOVEC((CYG_WORD32) __ramvec_start & 0xFFF00000, CYGARC_REG_VBR);
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150 }
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151
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152
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153 // Initialize chip-select modules
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154 void plf_init_cs(void)
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155 {
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156 // ChipSelect 0 - 2MB FLASH
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157 // At startup, CS0 is configured so that addresses starting at 0xXXX00000
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158 // are aliased to 0x00000000, so, in ROM startup configuration, code can
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159 // be placed starting at VMA address 0xFFE00000. When we are here,
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160 // the PC points to addresses in 0xFFE00000 space, and we can safely
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161 // reconfigure CS0 to respond uniquely to those addresses.
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162 HAL_WRITE_UINT32(&MCF5272_DEVS->cs[0].csbr, (0
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163 | MCF5272_CS_BR_BASE(CYGMEM_REGION_flash)
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164 | MCF5272_CS_BR_SRAM
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165 | MCF5272_CS_BR_PS_16
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166 | MCF5272_CS_BR_EN));
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167
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168 HAL_WRITE_UINT32(&MCF5272_DEVS->cs[0].csor,
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169 (0 | MCF5272_CS_OR_MASK_2M
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170 | MCF5272_CS_OR_WS(5)));
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171
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172 #ifdef CYGHWR_EXT_SRAM_INSTALLED
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173 // Chip Select 2 - 512KB SRAM
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174 HAL_WRITE_UINT32(&MCF5272_DEVS->cs[2].csbr, (0
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175 | MCF5272_CS_BR_BASE(CYGMEM_REGION_ext_sram)
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176 | MCF5272_CS_BR_SRAM
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177 | MCF5272_CS_BR_PS_32
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178 | MCF5272_CS_BR_EN));
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179
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180 HAL_WRITE_UINT32(&MCF5272_DEVS->cs[2].csor, (0
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181 | MCF5272_CS_OR_MASK_512K
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182 | MCF5272_CS_OR_WS(0)));
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183 #endif // CYGHWR_EXT_SRAM_INSTALLED
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184
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185 // ChipSelect 7 - 16MB SDRAM
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186 HAL_WRITE_UINT32(&MCF5272_DEVS->cs[7].csbr, (0
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187 | MCF5272_CS_BR_BASE(CYGMEM_REGION_sdram)
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188 | MCF5272_CS_BR_SDRAM
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189 | MCF5272_CS_BR_PS_LINE
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190 | MCF5272_CS_BR_EN));
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191
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192 HAL_WRITE_UINT32(&MCF5272_DEVS->cs[7].csor, (0
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193 #if (CYGHWR_INSTALLED_SDRAM_SIZE == 4)
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194 | MCF5272_CS_OR_MASK_4M
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195 #else
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196 | MCF5272_CS_OR_MASK_16M
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197 #endif
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198 | MCF5272_CS_OR_WS(0x1F)));
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199 }
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200
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201
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202 // Initialize SDRAM controller
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203 void plf_init_sdramc(void)
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204 {
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205 cyg_uint16 sdcr;
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206
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207
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208 HAL_READ_UINT16(&MCF5272_DEVS->sdramc.sdcr, sdcr);
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209
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210 // Do not initialize SDRAM if it is already active
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211 if (!(sdcr & MCF5272_SDRAMC_SDCCR_ACT))
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212 {
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213 #if (CYGHWR_HAL_SYSTEM_CLOCK_MHZ == 66)
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214 HAL_WRITE_UINT16(&MCF5272_DEVS->sdramc.sdtr, (0
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215 | MCF5272_SDRAMC_SDCTR_RTP_66MHz
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216 | MCF5272_SDRAMC_SDCTR_RC(0)
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217 | MCF5272_SDRAMC_SDCTR_RP(1)
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218 | MCF5272_SDRAMC_SDCTR_RCD(1)
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219 | MCF5272_SDRAMC_SDCTR_CLT_2));
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220 #else
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221 // Clock frequency must be 48 Mhz
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222 HAL_WRITE_UINT16(&MCF5272_DEVS->sdramc.sdtr, (0
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223 | MCF5272_SDRAMC_SDCTR_RTP_48MHz
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224 | MCF5272_SDRAMC_SDCTR_RC(0)
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225 | MCF5272_SDRAMC_SDCTR_RP(1)
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226 | MCF5272_SDRAMC_SDCTR_RCD(0)
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227 | MCF5272_SDRAMC_SDCTR_CLT_2));
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228 #endif
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229
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230 HAL_WRITE_UINT16(&MCF5272_DEVS->sdramc.sdcr, (0
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231 | MCF5272_SDRAMC_SDCCR_MCAS_A9
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232 #if (CYGHWR_INSTALLED_SDRAM_SIZE == 4)
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233 | MCF5272_SDRAMC_SDCCR_BALOC_A21
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234 #else
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235 | MCF5272_SDRAMC_SDCCR_BALOC_A22
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236 #endif
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237 | MCF5272_SDRAMC_SDCCR_REG
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238 | MCF5272_SDRAMC_SDCCR_INIT));
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239
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240 // Start SDRAM controller with a memory write
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241 *((volatile char *) CYGMEM_REGION_sdram) = 0;
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242
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243 // Wait until controller is ready
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244 do
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245 {
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246 HAL_READ_UINT16(&MCF5272_DEVS->sdramc.sdcr, sdcr);
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247 } while(!(sdcr & MCF5272_SDRAMC_SDCCR_ACT));
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248 }
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249 }
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250
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251
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252 // Platform specific data initialization routine
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253 void plf_init_data(void)
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254 {
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255 // Nothing to do
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256 }