Mercurial > ecos-v3_0-branch
annotate packages/hal/coldfire/mcf5272/current/include/mcf5272_devs.h @ 2729:74dbf4c3f2e1 after-copyright-change-20090129
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
| author | jlarmour |
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| date | Thu, 29 Jan 2009 17:47:46 +0000 |
| parents | a62600d0e7b5 |
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| rev | line source |
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1 #ifndef CYGONCE_MCF5272_DEVS_H |
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2 #define CYGONCE_MCF5272_DEVS_H |
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3 |
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4 //============================================================================= |
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5 // |
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6 // mcf5272_devs.h |
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7 // |
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8 // Definitions for the MCF5272 on-chip peripherals |
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9 // |
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10 //========================================================================== |
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11 // ####ECOSGPLCOPYRIGHTBEGIN#### |
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12 // ------------------------------------------- |
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13 // This file is part of eCos, the Embedded Configurable Operating System. |
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. |
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15 // |
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16 // eCos is free software; you can redistribute it and/or modify it under |
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17 // the terms of the GNU General Public License as published by the Free |
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18 // Software Foundation; either version 2 or (at your option) any later |
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19 // version. |
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20 // |
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT |
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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24 // for more details. |
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25 // |
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26 // You should have received a copy of the GNU General Public License |
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27 // along with eCos; if not, write to the Free Software Foundation, Inc., |
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
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29 // |
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30 // As a special exception, if other files instantiate templates or use |
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31 // macros or inline functions from this file, or you compile this file |
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32 // and link it with other works to produce a work based on this file, |
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33 // this file does not by itself cause the resulting work to be covered by |
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34 // the GNU General Public License. However the source code for this file |
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35 // must still be made available in accordance with section (3) of the GNU |
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36 // General Public License v2. |
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37 // |
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38 // This exception does not invalidate any other reasons why a work based |
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39 // on this file might be covered by the GNU General Public License. |
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40 // ------------------------------------------- |
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41 // ####ECOSGPLCOPYRIGHTEND#### |
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42 //========================================================================== |
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43 //#####DESCRIPTIONBEGIN#### |
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44 // |
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45 // Author(s): Enrico Piria, Wade Jensen |
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46 // Contributors: |
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47 // Date: 2005-25-06 |
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48 // Purpose: Definitions for the MCF5272 on-chip peripherals. |
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49 // Usage: #include <cyg/hal/mcf5272_devs.h> |
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50 // |
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51 //####DESCRIPTIONEND#### |
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52 //======================================================================== |
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53 |
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54 #include <pkgconf/hal.h> |
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55 #include <cyg/infra/cyg_type.h> |
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56 |
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57 // General configuration registers |
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58 typedef struct |
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59 { |
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60 |
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61 // Module base address register |
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62 cyg_uint32 mbar; |
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63 |
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64 // System configuration register |
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65 cyg_uint16 scr; |
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66 |
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67 // System protection register |
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68 cyg_uint16 spr; |
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69 |
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70 // Power management register |
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71 cyg_uint32 pmr; |
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72 |
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73 // Gap |
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74 cyg_uint16 _res1; |
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75 |
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76 // Active low power register |
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77 cyg_uint16 alpr; |
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78 |
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79 // Device identification register |
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80 cyg_uint32 dir; |
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81 |
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82 // Gap |
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83 cyg_uint32 _res2[3]; |
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84 |
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85 } __attribute__ ((aligned (4), packed)) mcf5272_sim_cfg_t; |
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86 |
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87 // Configuration registers macros |
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88 |
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89 #define MCF5272_SIM_SCR_HWWD_1024 0x0003 |
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90 |
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91 #define MCF5272_SIM_SPR_ADC 0x8000 |
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92 #define MCF5272_SIM_SPR_ADCEN 0x0080 |
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93 #define MCF5272_SIM_SPR_WPV 0x4000 |
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94 #define MCF5272_SIM_SPR_WPVEN 0x0040 |
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95 #define MCF5272_SIM_SPR_SMV 0x2000 |
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96 #define MCF5272_SIM_SPR_SMVEN 0x0020 |
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97 #define MCF5272_SIM_SPR_SBE 0x1000 |
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98 #define MCF5272_SIM_SPR_SBEEN 0x0010 |
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99 #define MCF5272_SIM_SPR_HWT 0x0800 |
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100 #define MCF5272_SIM_SPR_HWTEN 0x0008 |
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101 #define MCF5272_SIM_SPR_RPV 0x0400 |
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102 #define MCF5272_SIM_SPR_RPVEN 0x0004 |
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103 #define MCF5272_SIM_SPR_EXT 0x0200 |
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104 #define MCF5272_SIM_SPR_EXTEN 0x0002 |
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105 #define MCF5272_SIM_SPR_SUV 0x0100 |
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106 #define MCF5272_SIM_SPR_SUVEN 0x0001 |
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107 |
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108 // --------------------------------------------------------------------------- |
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109 |
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110 // Interrupt controller registers |
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111 typedef struct |
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112 { |
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113 |
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114 // Interrupt control register 1-4 |
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115 cyg_uint32 icr[4]; |
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116 |
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117 // Interrupt source register |
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118 cyg_uint32 isr; |
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119 |
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120 // Programmable interrupt transition register |
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121 cyg_uint32 pitr; |
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122 |
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123 // Programmable interrupt wakeup register |
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124 cyg_uint32 piwr; |
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125 |
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126 // Gap |
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127 cyg_uint8 _res1[3]; |
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128 |
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129 // Programmable interrupt vector register |
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130 cyg_uint8 ipvr; |
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131 |
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132 } __attribute__ ((aligned (4), packed)) mcf5272_sim_int_t; |
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133 |
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134 // Interrupt controller related macros |
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135 |
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136 #define MCF5272_SIM_PITR_INT1_POS_EDGE (0x80000000) |
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137 #define MCF5272_SIM_PITR_INT2_POS_EDGE (0x40000000) |
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138 #define MCF5272_SIM_PITR_INT3_POS_EDGE (0x20000000) |
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139 #define MCF5272_SIM_PITR_INT4_POS_EDGE (0x10000000) |
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140 #define MCF5272_SIM_PITR_INT5_POS_EDGE (0x00000040) |
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141 #define MCF5272_SIM_PITR_INT6_POS_EDGE (0x00000020) |
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142 |
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143 #define MCF5272_SIM_PIWR_INT1_WAKE (0x80000000) |
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144 #define MCF5272_SIM_PIWR_INT2_WAKE (0x40000000) |
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145 #define MCF5272_SIM_PIWR_INT3_WAKE (0x20000000) |
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146 #define MCF5272_SIM_PIWR_INT4_WAKE (0x10000000) |
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147 #define MCF5272_SIM_PIWR_TMR0_WAKE (0x08000000) |
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148 #define MCF5272_SIM_PIWR_TMR1_WAKE (0x04000000) |
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149 #define MCF5272_SIM_PIWR_TMR2_WAKE (0x02000000) |
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150 #define MCF5272_SIM_PIWR_TMR3_WAKE (0x01000000) |
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151 #define MCF5272_SIM_PIWR_UART1_WAKE (0x00800000) |
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152 #define MCF5272_SIM_PIWR_UART2_WAKE (0x00400000) |
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153 #define MCF5272_SIM_PIWR_PLIP_WAKE (0x00200000) |
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154 #define MCF5272_SIM_PIWR_PLIA_WAKE (0x00100000) |
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155 #define MCF5272_SIM_PIWR_USB0_WAKE (0x00080000) |
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156 #define MCF5272_SIM_PIWR_USB1_WAKE (0x00040000) |
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157 #define MCF5272_SIM_PIWR_USB2_WAKE (0x00020000) |
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158 #define MCF5272_SIM_PIWR_USB3_WAKE (0x00010000) |
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159 #define MCF5272_SIM_PIWR_USB4_WAKE (0x00008000) |
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160 #define MCF5272_SIM_PIWR_USB5_WAKE (0x00004000) |
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161 #define MCF5272_SIM_PIWR_USB6_WAKE (0x00002000) |
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162 #define MCF5272_SIM_PIWR_USB7_WAKE (0x00001000) |
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163 #define MCF5272_SIM_PIWR_DMA_WAKE (0x00000800) |
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164 #define MCF5272_SIM_PIWR_ERX_WAKE (0x00000400) |
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165 #define MCF5272_SIM_PIWR_ETX_WAKE (0x00000200) |
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166 #define MCF5272_SIM_PIWR_ENTC_WAKE (0x00000100) |
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167 #define MCF5272_SIM_PIWR_QSPI_WAKE (0x00000080) |
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168 #define MCF5272_SIM_PIWR_INT5_WAKE (0x00000040) |
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169 #define MCF5272_SIM_PIWR_INT6_WAKE (0x00000020) |
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170 #define MCF5272_SIM_PIWR_SWTO_WAKE (0x00000010) |
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171 |
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172 // --------------------------------------------------------------------------- |
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173 |
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174 // Chip-select module |
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175 typedef struct |
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176 { |
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177 |
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178 // CS base register |
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179 cyg_uint32 csbr; |
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180 |
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181 // CS option register |
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182 cyg_uint32 csor; |
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183 |
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184 } __attribute__ ((aligned (4), packed)) mcf5272_sim_cs_t; |
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185 |
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186 // Chip-select modules related macros |
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187 |
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188 #define MCF5272_CS_BR_BASE(a) ((a) & 0xFFFFF000) |
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189 |
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190 #define MCF5272_CS_OR_MASK_128M (0xF8000000) |
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191 #define MCF5272_CS_OR_MASK_64M (0xFC000000) |
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192 #define MCF5272_CS_OR_MASK_32M (0xFE000000) |
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193 #define MCF5272_CS_OR_MASK_16M (0xFF000000) |
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194 #define MCF5272_CS_OR_MASK_8M (0xFF800000) |
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195 #define MCF5272_CS_OR_MASK_4M (0xFFC00000) |
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196 #define MCF5272_CS_OR_MASK_2M (0xFFE00000) |
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197 #define MCF5272_CS_OR_MASK_1M (0xFFF00000) |
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198 #define MCF5272_CS_OR_MASK_512K (0xFFF80000) |
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199 #define MCF5272_CS_OR_MASK_256K (0xFFFC0000) |
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200 #define MCF5272_CS_OR_MASK_128K (0xFFFE0000) |
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201 #define MCF5272_CS_OR_MASK_64K (0xFFFF0000) |
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202 #define MCF5272_CS_OR_MASK_32K (0xFFFF8000) |
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203 #define MCF5272_CS_OR_MASK_16K (0xFFFFC000) |
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204 #define MCF5272_CS_OR_MASK_8K (0xFFFFE000) |
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205 #define MCF5272_CS_OR_MASK_4K (0xFFFFF000) |
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206 #define MCF5272_CS_OR_WS_MASK (0x007C) |
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207 #define MCF5272_CS_OR_WS(a) (((a) & 0x1F) << 2) |
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208 #define MCF5272_CS_OR_BRST (0x0100) |
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209 #define MCF5272_CS_OR_WR_ONLY (0x0003) |
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210 #define MCF5272_CS_OR_RD_ONLY (0x0001) |
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211 |
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212 #define MCF5272_CS_BR_PS_8 (0x0100) |
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213 #define MCF5272_CS_BR_PS_16 (0x0200) |
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214 #define MCF5272_CS_BR_PS_32 (0x0000) |
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215 #define MCF5272_CS_BR_PS_LINE (0x0300) |
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216 #define MCF5272_CS_BR_ROM (0x0000) |
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217 #define MCF5272_CS_BR_SRAM (0x0000) |
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218 #define MCF5272_CS_BR_SRAM_8 (0x0C00) |
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219 #define MCF5272_CS_BR_SDRAM (0x0400) |
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220 #define MCF5272_CS_BR_ISA (0x0800) |
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221 #define MCF5272_CS_BR_SV (0x0080) |
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222 #define MCF5272_CS_BR_EN (0x0001) |
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223 |
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224 // --------------------------------------------------------------------------- |
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225 |
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226 // General purpose I/O module |
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227 typedef struct |
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228 { |
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229 |
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230 // Port A control register |
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231 cyg_uint32 pacnt; |
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232 |
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233 // Port A data direction register |
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234 cyg_uint16 paddr; |
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235 |
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236 // Port A data register |
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237 cyg_uint16 padat; |
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238 |
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239 // Port B control register |
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240 cyg_uint32 pbcnt; |
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241 |
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242 // Port B data direction register |
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243 cyg_uint16 pbddr; |
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244 |
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245 // Port B data register |
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246 cyg_uint16 pbdat; |
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247 |
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248 // Gap |
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249 cyg_uint32 _res1; |
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250 |
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251 // Port C data direction register |
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252 cyg_uint16 pcddr; |
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253 |
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254 // Port C data register |
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255 cyg_uint16 pcdat; |
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256 |
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257 // Port D control register |
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258 cyg_uint32 pdcnt; |
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259 |
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260 // Gap |
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261 cyg_uint16 _res2; |
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262 cyg_uint16 _res3; |
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263 |
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264 } __attribute__ ((aligned (4), packed)) mcf5272_sim_gpio_t; |
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265 |
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266 // GPIO ports related macros |
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267 |
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268 #define MCF5272_GPIO_DDR_IN (0) |
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269 #define MCF5272_GPIO_DDR_OUT (1) |
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270 |
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271 #define MCF5272_GPIO_PBCNT_ETH_EN (0x55550000) |
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272 #define MCF5272_GPIO_PBCNT_ETH_DE (0x00000000) |
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273 #define MCF5272_GPIO_PBCNT_ETH_MSK (0xFFFF0000) |
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274 |
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275 #define MCF5272_GPIO_PBCNT_TA_EN (0x00000400) |
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276 #define MCF5272_GPIO_PBCNT_TA_DE (0x00000000) |
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277 #define MCF5272_GPIO_PBCNT_TA_MSK (0x00000C00) |
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278 |
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279 #define MCF5272_GPIO_PBCNT_URT0_EN (0x00000155) |
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280 #define MCF5272_GPIO_PBCNT_URT0_DE (0x00000000) |
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281 #define MCF5272_GPIO_PBCNT_URT0_MSK (0x000003FF) |
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282 |
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283 #define MCF5272_GPIO_PDCNT_INT4_EN (0x00000C00) |
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284 #define MCF5272_GPIO_PDCNT_INT4_DE (0x00000000) |
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285 #define MCF5272_GPIO_PDCNT_INT4_MSK (0x00000C00) |
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286 |
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287 #define MCF5272_GPIO_PDCNT_URT1_EN (0x000002AA) |
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288 #define MCF5272_GPIO_PDCNT_URT1_DE (0x00000000) |
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289 #define MCF5272_GPIO_PDCNT_URT1_MSK (0x000003FF) |
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290 |
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291 // --------------------------------------------------------------------------- |
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292 |
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293 // UART module |
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294 typedef struct |
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295 { |
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296 |
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297 // UART mode register |
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298 cyg_uint8 umr; |
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299 |
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300 // Gap |
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301 cyg_uint8 _res1[3]; |
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302 |
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303 // UART status register (R) and clock-select register (W) |
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304 cyg_uint8 usr_ucsr; |
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305 |
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306 // Gap |
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307 cyg_uint8 _res2[3]; |
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Import of the new ColdFire architecture HAL and M52272C port, with
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|
308 |
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309 // UART command register |
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Import of the new ColdFire architecture HAL and M52272C port, with
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310 cyg_uint8 ucr; |
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Import of the new ColdFire architecture HAL and M52272C port, with
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311 |
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Import of the new ColdFire architecture HAL and M52272C port, with
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312 // Gap |
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313 cyg_uint8 _res3[3]; |
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Import of the new ColdFire architecture HAL and M52272C port, with
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314 |
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315 // UART receiver buffers (R) and transmitter buffers (W) |
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316 cyg_uint8 urb_utb; |
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|
317 |
|
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318 // Gap |
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319 cyg_uint8 _res4[3]; |
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Import of the new ColdFire architecture HAL and M52272C port, with
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|
320 |
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Import of the new ColdFire architecture HAL and M52272C port, with
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321 // UART input port change register (R) and auxiliary control register (W) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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322 cyg_uint8 uipcr_uacr; |
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|
323 |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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324 // Gap |
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325 cyg_uint8 _res5[3]; |
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Import of the new ColdFire architecture HAL and M52272C port, with
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|
326 |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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327 // UART interrupt status register (R) and interrupt mask register (W) |
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Import of the new ColdFire architecture HAL and M52272C port, with
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|
328 cyg_uint8 uisr_uimr; |
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|
329 |
|
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|
330 // Gap |
|
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|
331 cyg_uint8 _res6[3]; |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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|
332 |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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diff
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|
333 // UART divider upper register |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
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changeset
|
334 cyg_uint8 udu; |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
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changeset
|
335 |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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diff
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|
336 // Gap |
|
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|
337 cyg_uint8 _res7[3]; |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
changeset
|
338 |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
changeset
|
339 // UART divider lower register |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
340 cyg_uint8 udl; |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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changeset
|
341 |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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|
342 // Gap |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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|
343 cyg_uint8 _res8[3]; |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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|
344 |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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|
345 // UART autobaud register MSB |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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|
346 cyg_uint8 uabu; |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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changeset
|
347 |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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changeset
|
348 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
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|
349 cyg_uint8 _res9[3]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
changeset
|
350 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
351 // UART autobaud register LSB |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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changeset
|
352 cyg_uint8 uabl; |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
353 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
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diff
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|
354 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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|
355 cyg_uint8 _res10[3]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
356 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
357 // UART transmitter FIFO register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
changeset
|
358 cyg_uint8 utf; |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
changeset
|
359 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
changeset
|
360 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
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|
361 cyg_uint8 _res11[3]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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|
362 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
changeset
|
363 // UART receiver FIFO register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
changeset
|
364 cyg_uint8 urf; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
changeset
|
365 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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changeset
|
366 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
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|
367 cyg_uint8 _res12[3]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
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|
368 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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changeset
|
369 // UART fractional precision divider register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
changeset
|
370 cyg_uint8 ufpd; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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changeset
|
371 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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changeset
|
372 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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|
373 cyg_uint8 _res13[3]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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changeset
|
374 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
375 // UART input port register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
376 cyg_uint8 uip; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
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changeset
|
377 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
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changeset
|
378 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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changeset
|
379 cyg_uint8 _res14[3]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
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changeset
|
380 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
381 // UART output port register 1 |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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|
382 cyg_uint8 uop1; |
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383 |
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|
384 // Gap |
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diff
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|
385 cyg_uint8 _res15[3]; |
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Import of the new ColdFire architecture HAL and M52272C port, with
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parents:
diff
changeset
|
386 |
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asl
parents:
diff
changeset
|
387 // UART output port register 0 |
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asl
parents:
diff
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|
388 cyg_uint8 uop0; |
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asl
parents:
diff
changeset
|
389 |
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parents:
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|
390 // Gap |
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diff
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|
391 cyg_uint8 _res16[3]; |
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
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|
392 |
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|
393 } __attribute__ ((aligned (4), packed)) mcf5272_uart_t; |
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394 |
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395 // --------------------------------------------------------------------------- |
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396 |
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397 // SDRAM controller |
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asl
parents:
diff
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|
398 typedef struct |
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parents:
diff
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|
399 { |
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parents:
diff
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|
400 |
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
401 // Gap |
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402 cyg_uint8 _res1[2]; |
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Import of the new ColdFire architecture HAL and M52272C port, with
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parents:
diff
changeset
|
403 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
404 // SDRAM configuration register |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
405 cyg_uint16 sdcr; |
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
406 |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
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changeset
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407 // Gap |
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
408 cyg_uint8 _res2[2]; |
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
409 |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
410 // SDRAM timing register |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
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|
411 cyg_uint16 sdtr; |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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diff
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|
412 |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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parents:
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413 // Gap |
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Import of the new ColdFire architecture HAL and M52272C port, with
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414 cyg_uint8 _res3[120]; |
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
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|
415 |
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Import of the new ColdFire architecture HAL and M52272C port, with
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|
416 } __attribute__ ((aligned (4), packed)) mcf5272_sim_sdramctrl_t; |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
417 |
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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|
418 // SDRAM controller related macros |
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
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|
419 |
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Import of the new ColdFire architecture HAL and M52272C port, with
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420 #define MCF5272_SDRAMC_SDCCR_MCAS_A7 (0x0 << 13) |
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421 #define MCF5272_SDRAMC_SDCCR_MCAS_A8 (0x1 << 13) |
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Import of the new ColdFire architecture HAL and M52272C port, with
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422 #define MCF5272_SDRAMC_SDCCR_MCAS_A9 (0x2 << 13) |
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Import of the new ColdFire architecture HAL and M52272C port, with
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423 #define MCF5272_SDRAMC_SDCCR_MCAS_A10 (0x3 << 13) |
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Import of the new ColdFire architecture HAL and M52272C port, with
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424 #define MCF5272_SDRAMC_SDCCR_BALOC_A19 (0x0 << 8) |
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Import of the new ColdFire architecture HAL and M52272C port, with
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425 #define MCF5272_SDRAMC_SDCCR_BALOC_A20 (0x1 << 8) |
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Import of the new ColdFire architecture HAL and M52272C port, with
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426 #define MCF5272_SDRAMC_SDCCR_BALOC_A21 (0x2 << 8) |
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Import of the new ColdFire architecture HAL and M52272C port, with
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diff
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427 #define MCF5272_SDRAMC_SDCCR_BALOC_A22 (0x3 << 8) |
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Import of the new ColdFire architecture HAL and M52272C port, with
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428 #define MCF5272_SDRAMC_SDCCR_BALOC_A23 (0x4 << 8) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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429 #define MCF5272_SDRAMC_SDCCR_BALOC_A24 (0x5 << 8) |
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
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430 #define MCF5272_SDRAMC_SDCCR_BALOC_A25 (0x6 << 8) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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431 #define MCF5272_SDRAMC_SDCCR_BALOC_A26 (0x7 << 8) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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432 #define MCF5272_SDRAMC_SDCCR_GSL (0x00000080) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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433 #define MCF5272_SDRAMC_SDCCR_REG (0x00000010) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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|
434 #define MCF5272_SDRAMC_SDCCR_INV (0x00000008) |
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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435 #define MCF5272_SDRAMC_SDCCR_SLEEP (0x00000004) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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436 #define MCF5272_SDRAMC_SDCCR_ACT (0x00000002) |
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Import of the new ColdFire architecture HAL and M52272C port, with
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437 #define MCF5272_SDRAMC_SDCCR_INIT (0x00000001) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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|
438 |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
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439 #define MCF5272_SDRAMC_SDCTR_RTP_66MHz (0x3D << 10) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
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440 #define MCF5272_SDRAMC_SDCTR_RTP_48MHz (0x2B << 10) |
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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441 #define MCF5272_SDRAMC_SDCTR_RTP_33MHz (0x1D << 10) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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442 #define MCF5272_SDRAMC_SDCTR_RTP_25MHz (0x16 << 10) |
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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|
443 #define MCF5272_SDRAMC_SDCTR_RC(x) ((x & 0x3) << 8) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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444 #define MCF5272_SDRAMC_SDCTR_RP(x) ((x & 0x3) << 4) |
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asl
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diff
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|
445 #define MCF5272_SDRAMC_SDCTR_RCD(x) ((x & 0x3) << 2) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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|
446 #define MCF5272_SDRAMC_SDCTR_CLT_2 (0x00000001) |
|
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asl
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447 #define MCF5272_SDRAMC_SDCTR_CLT_3 (0x00000002) |
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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|
448 #define MCF5272_SDRAMC_SDCTR_CLT_4 (0x00000003) |
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|
449 |
|
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|
450 // --------------------------------------------------------------------------- |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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|
451 |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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|
452 // Timer module |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
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|
453 typedef struct |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
changeset
|
454 { |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
455 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
456 // Timer mode register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
457 cyg_uint16 tmr; |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
458 |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
459 // Gap |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
460 cyg_uint16 _res1; |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
461 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
462 // Timer reference register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
463 cyg_uint16 trr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
464 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
465 // Gap |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
466 cyg_uint16 _res2; |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
467 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
468 // Timer capture register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
469 cyg_uint16 tcap; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
470 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
471 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
472 cyg_uint16 _res3; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
473 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
474 // Timer counter register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
475 cyg_uint16 tcn; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
476 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
477 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
478 cyg_uint16 _res4; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
479 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
480 // Timer event register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
481 cyg_uint16 ter; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
482 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
483 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
484 cyg_uint16 _res5; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
485 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
486 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
487 cyg_uint32 _res6[3]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
488 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
489 } __attribute__ ((aligned (4), packed)) mcf5272_timer_t; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
490 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
491 // Related macros |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
492 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
493 #define MCF5272_TIMER_TMR_PS (0xFF00) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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|
494 #define MCF5272_TIMER_TMR_PS_BIT (8) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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|
495 #define MCF5272_TIMER_TMR_CE (0x00C0) |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
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diff
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|
496 #define MCF5272_TIMER_TMR_CE_BIT (6) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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|
497 #define MCF5272_TIMER_TMR_OM (0x0020) |
|
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Import of the new ColdFire architecture HAL and M52272C port, with
asl
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|
498 #define MCF5272_TIMER_TMR_OM_BIT (5) |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
499 #define MCF5272_TIMER_TMR_ORI (0x0010) |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
500 #define MCF5272_TIMER_TMR_ORI_BIT (4) |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
501 #define MCF5272_TIMER_TMR_FRR (0x0008) |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
502 #define MCF5272_TIMER_TMR_FRR_BIT (3) |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
503 #define MCF5272_TIMER_TMR_CLK (0x0006) |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
504 #define MCF5272_TIMER_TMR_CLK_BIT (1) |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
505 #define MCF5272_TIMER_TMR_RST (0x0001) |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
506 #define MCF5272_TIMER_TMR_RST_BIT (0) |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
507 #define MCF5272_TIMER_TER_REF (0x0002) |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
508 #define MCF5272_TIMER_TER_REF_BIT (1) |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
509 #define MCF5272_TIMER_TER_CAP (0x0001) |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
510 #define MCF5272_TIMER_TER_CAP_BIT (0) |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
511 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
512 // --------------------------------------------------------------------------- |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
513 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
514 // Watchdog timer |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
515 typedef struct |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
516 { |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
517 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
518 // Watchdog reset reference register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
519 cyg_uint16 wrrr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
520 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
521 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
522 cyg_uint16 _res1; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
523 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
524 // Watchdog interrupt reference register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
525 cyg_uint16 wirr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
526 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
527 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
528 cyg_uint16 _res2; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
529 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
530 // Watchdog counter register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
531 cyg_uint16 wcr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
532 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
533 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
534 cyg_uint16 _res3; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
535 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
536 // Watchdog event register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
537 cyg_uint16 wer; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
538 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
539 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
540 cyg_uint16 _res4; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
541 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
542 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
543 cyg_uint32 _res5[28]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
544 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
545 } __attribute__ ((aligned (4), packed)) mcf5272_sim_wdtmr_t; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
546 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
547 // --------------------------------------------------------------------------- |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
548 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
549 // Fast Ethernet Controller module |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
550 typedef struct |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
551 { |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
552 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
553 // Ethernet control register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
554 cyg_uint32 ecr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
555 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
556 // Ethernet interrupt event register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
557 cyg_uint32 eir; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
558 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
559 // Ethernet interrupt mask register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
560 cyg_uint32 eimr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
561 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
562 // Interrupt vector status register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
563 cyg_uint32 ivsr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
564 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
565 // Receive descriptor active register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
566 cyg_uint32 rdar; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
567 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
568 // Transmit descriptor active register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
569 cyg_uint32 tdar; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
570 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
571 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
572 cyg_uint8 _res2[0x0880 - 0x0858]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
573 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
574 // MII management frame register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
575 cyg_uint32 mmfr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
576 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
577 // MII speed control register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
578 cyg_uint32 mscr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
579 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
580 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
581 cyg_uint8 _res3[0x08cc - 0x0888]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
582 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
583 // FIFO receive bound register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
584 cyg_uint32 frbr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
585 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
586 // FIFO receive start register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
587 cyg_uint32 frsr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
588 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
589 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
590 cyg_uint8 _res4[0x08e4 - 0x08d4]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
591 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
592 // Transmit FIFO watermark |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
593 cyg_uint32 tfwr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
594 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
595 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
596 cyg_uint8 _res5[0x08ec - 0x08e8]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
597 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
598 // Transmit FIFO start register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
599 cyg_uint32 tfsr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
600 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
601 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
602 cyg_uint8 _res6[0x0944 - 0x08f0]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
603 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
604 // Receive control register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
605 cyg_uint32 rcr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
606 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
607 // Maximum frame length register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
608 cyg_uint32 mflr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
609 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
610 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
611 cyg_uint8 _res7[0x0984 - 0x094c]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
612 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
613 // Transmit control register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
614 cyg_uint32 tcr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
615 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
616 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
617 cyg_uint8 _res8[0x0c00 - 0x0988]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
618 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
619 // RAM perfect match address low register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
620 cyg_uint32 malr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
621 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
622 // RAM perfect match address high register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
623 cyg_uint32 maur; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
624 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
625 // Hash table high register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
626 cyg_uint32 htur; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
627 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
628 // Hash table low register |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
629 cyg_uint32 htlr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
630 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
631 // Pointer to receive descriptor ring |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
632 cyg_uint32 erdsr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
633 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
634 // Pointer to transmit descriptor ring |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
635 cyg_uint32 etdsr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
636 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
637 // Maximum receive buffer size |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
638 cyg_uint32 emrbr; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
639 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
640 // Gap |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
641 cyg_uint8 _res9[0x0c40 - 0x0c1c]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
642 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
643 // FIFO RAM space |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
644 cyg_uint8 efifo[0x0e00 - 0x0c40]; |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
645 |
|
a62600d0e7b5
Import of the new ColdFire architecture HAL and M52272C port, with
asl
parents:
diff
changeset
|
646 // Gap |
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647 cyg_uint8 _res10[0x1000 - 0x0e00]; |
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648 |
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649 } __attribute__ ((aligned (4), packed)) mcf5272_fec_t; |
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650 |
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651 // --------------------------------------------------------------------------- |
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652 |
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653 // On-chip peripherals: this structure defines each register's offset from the |
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654 // current value of the MBAR register. |
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655 typedef struct |
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656 { |
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657 |
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658 // 0x0000: System Integration Module (SIM) general configuration registers |
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659 mcf5272_sim_cfg_t cfg; |
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660 |
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661 // 0x0020: SIM interrupt controller registers |
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662 mcf5272_sim_int_t intc; |
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663 |
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664 // 0x0040: SIM chip-select modules |
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665 mcf5272_sim_cs_t cs[8]; |
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666 |
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667 // 0x0080: SIM general purpose I/O control registers |
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668 mcf5272_sim_gpio_t gpio; |
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669 |
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670 // 0x00a0: QSPI module |
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671 // TODO: a specific data structure is needed |
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672 cyg_uint32 qspi[8]; |
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673 |
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674 // 0x00c0: PWM module |
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675 // TODO: a specific data structure is needed |
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676 cyg_uint32 pwm[8]; |
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677 |
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678 // 0x00e0: DMA controller |
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679 // TODO: a specific data structure is needed |
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680 cyg_uint32 dmac[8]; |
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681 |
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682 // 0x0100: UART modules |
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683 mcf5272_uart_t uart[2]; |
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684 |
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685 // 0x0180: SIM SDRAM controller |
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686 mcf5272_sim_sdramctrl_t sdramc; |
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687 |
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688 // 0x0200: timer module |
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689 mcf5272_timer_t timer[4]; |
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690 |
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691 // 0x0280: SIM watchdog timer module |
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692 mcf5272_sim_wdtmr_t wdtimer; |
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693 |
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694 // 0x0300: physical layer interface controller |
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695 // TODO: a specific data structure is needed |
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696 cyg_uint32 plic[336]; |
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697 |
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698 // 0x0840: ethernet module |
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699 mcf5272_fec_t fec; |
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700 |
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701 // 0x1000: USB module |
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702 // TODO: a specific data structure is needed |
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703 cyg_uint32 usb[512]; |
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704 |
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705 } __attribute__ ((aligned (4), packed)) mcf5272_devs_t; |
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706 |
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707 // --------------------------------------------------------------------------- |
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708 // End of mcf5272_devs.h |
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709 #endif // CYGONCE_MCF5272_DEVS_H |
