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annotate packages/hal/mips/mips64/current/include/var_cache.h @ 2729:74dbf4c3f2e1 after-copyright-change-20090129

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Update all copyright banners to reflect FSF ownership; fix and improve licence text.
author jlarmour
date Thu, 29 Jan 2009 17:47:46 +0000
parents d2c90368aeef
children
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1 #ifndef CYGONCE_IMP_CACHE_H
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2 #define CYGONCE_IMP_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // imp_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 // ####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later
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19 // version.
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20 //
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // for more details.
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25 //
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26 // You should have received a copy of the GNU General Public License
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27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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29 //
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30 // As a special exception, if other files instantiate templates or use
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31 // macros or inline functions from this file, or you compile this file
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32 // and link it with other works to produce a work based on this file,
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33 // this file does not by itself cause the resulting work to be covered by
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34 // the GNU General Public License. However the source code for this file
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35 // must still be made available in accordance with section (3) of the GNU
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36 // General Public License v2.
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37 //
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38 // This exception does not invalidate any other reasons why a work based
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39 // on this file might be covered by the GNU General Public License.
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40 // -------------------------------------------
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41 // ####ECOSGPLCOPYRIGHTEND####
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42 //=============================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): nickg
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46 // Contributors: nickg, dmoseley
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47 // Date: 1998-02-17
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48 // Purpose: Cache control API
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49 // Description: The macros defined here provide the HAL APIs for handling
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50 // cache control operations.
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51 // Usage:
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52 // #include <cyg/hal/imp_cache.h>
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53 // ...
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54 //
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55 //
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56 //####DESCRIPTIONEND####
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57 //
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58 //=============================================================================
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59
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60 #include <pkgconf/hal.h>
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61 #include <cyg/infra/cyg_type.h>
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62
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63 #include <cyg/hal/mips-regs.h>
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64 #include <cyg/hal/hal_arch.h>
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65 #include <cyg/hal/plf_cache.h>
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66 #include <cyg/hal/var_arch.h>
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67
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68 #ifdef CYGHWR_HAL_MIPS_MIPS64_CORE_5K
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69
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70 //-----------------------------------------------------------------------------
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71 // Cache dimensions
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72
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73 // Data cache
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74 #define HAL_DCACHE_SIZE 8192 // Size of data cache in bytes
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75 #define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
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76 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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77
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78 // Instruction cache
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79 #define HAL_ICACHE_SIZE 8192 // Size of cache in bytes
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80 #define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
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81 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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82
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83 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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84 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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85
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86 #define HAL_DCACHE_WRITETHRU_MODE 1
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87 #define HAL_DCACHE_WRITEBACK_MODE 0
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88
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89 #else
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90
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91 #error Unknown MIPS32 Variant
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92
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93 #endif
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94
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95 //-----------------------------------------------------------------------------
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96 // General cache defines.
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97 #define HAL_CLEAR_TAGLO() asm volatile (" mtc0 $0, $28;" \
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98 " nop;" \
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99 " nop;" \
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100 " nop;")
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101 #define HAL_CLEAR_TAGHI() asm volatile (" mtc0 $0, $29;" \
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102 " nop;" \
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103 " nop;" \
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104 " nop;")
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105
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106 /* Cache instruction opcodes */
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107 #define HAL_CACHE_OP(which, op) (which | (op << 2))
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108
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109 #define HAL_WHICH_ICACHE 0x0
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110 #define HAL_WHICH_DCACHE 0x1
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111
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112 #define HAL_INDEX_INVALIDATE 0x0
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113 #define HAL_INDEX_LOAD_TAG 0x1
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114 #define HAL_INDEX_STORE_TAG 0x2
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115 #define HAL_HIT_INVALIDATE 0x4
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116 #define HAL_ICACHE_FILL 0x5
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117 #define HAL_DCACHE_HIT_INVALIDATE 0x5
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118 #define HAL_DCACHE_HIT_WRITEBACK 0x6
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119 #define HAL_FETCH_AND_LOCK 0x7
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120
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121 //-----------------------------------------------------------------------------
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122 // Global control of data cache
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123
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124 // Invalidate the entire cache
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125 #define HAL_DCACHE_INVALIDATE_ALL_DEFINED
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126 #define HAL_DCACHE_INVALIDATE_ALL() \
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127 CYG_MACRO_START \
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128 register volatile CYG_BYTE *addr; \
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129 HAL_CLEAR_TAGLO(); \
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130 HAL_CLEAR_TAGHI(); \
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131 for (addr = (CYG_BYTE *)CYGARC_KSEG_CACHED_BASE; \
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132 addr < (CYG_BYTE *)(CYGARC_KSEG_CACHED_BASE + HAL_DCACHE_SIZE); \
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133 addr += HAL_DCACHE_LINE_SIZE ) \
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134 { \
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135 asm volatile (" cache %0, 0(%1)" \
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136 : \
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137 : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_INDEX_STORE_TAG)), \
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138 "r"(addr)); \
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139 } \
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140 CYG_MACRO_END
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141
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142 // Synchronize the contents of the cache with memory.
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143 extern void hal_dcache_sync(void);
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144 #define HAL_DCACHE_SYNC_DEFINED
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145 #define HAL_DCACHE_SYNC() hal_dcache_sync()
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146
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147 // Set the data cache refill burst size
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148 //#define HAL_DCACHE_BURST_SIZE(_asize_)
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149
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150 // Set the data cache write mode
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151 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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152
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153 // Load the contents of the given address range into the data cache
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154 // and then lock the cache so that it stays there.
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155 #define HAL_DCACHE_LOCK_DEFINED
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156 #define HAL_DCACHE_LOCK(_base_, _asize_) \
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157 CYG_MACRO_START \
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158 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
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159 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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160 register CYG_WORD _size_ = (_asize_); \
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161 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
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162 asm volatile (" cache %0, 0(%1)" \
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163 : \
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164 : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_FETCH_AND_LOCK)), \
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165 "r"(_addr_)); \
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166 CYG_MACRO_END
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167
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168 // Undo a previous lock operation
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169 #define HAL_DCACHE_UNLOCK_DEFINED
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170 #define HAL_DCACHE_UNLOCK(_base_, _asize_) \
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171 CYG_MACRO_START \
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172 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
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173 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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174 register CYG_WORD _size_ = (_asize_); \
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175 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
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176 asm volatile (" cache %0, 0(%1)" \
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177 : \
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178 : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)), \
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179 "r"(_addr_)); \
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180 CYG_MACRO_END
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181
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182 // Unlock entire cache
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183 #define HAL_DCACHE_UNLOCK_ALL_DEFINED
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184 #define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE)
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185
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186
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187 //-----------------------------------------------------------------------------
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188 // Data cache line control
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189
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190 // Allocate cache lines for the given address range without reading its
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191 // contents from memory.
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192 //#define HAL_DCACHE_ALLOCATE( _base_ , _asize_ )
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193
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194 // Write dirty cache lines to memory and invalidate the cache entries
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195 // for the given address range.
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196 #define HAL_DCACHE_FLUSH_DEFINED
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197 #if HAL_DCACHE_WRITETHRU_MODE == 1
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198 // No need to flush a writethrough cache
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199 #define HAL_DCACHE_FLUSH( _base_ , _asize_ )
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200 #else
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201 #error HAL_DCACHE_FLUSH undefined for MIPS32 writeback cache
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202 #endif
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203
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204 // Write dirty cache lines to memory for the given address range.
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205 #define HAL_DCACHE_STORE_DEFINED
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206 #if HAL_DCACHE_WRITETHRU_MODE == 1
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207 // No need to store a writethrough cache
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208 #define HAL_DCACHE_STORE( _base_ , _asize_ )
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209 #else
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210 #error HAL_DCACHE_STORE undefined for MIPS32 writeback cache
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211 #endif
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212
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213 // Invalidate cache lines in the given range without writing to memory.
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214 #define HAL_DCACHE_INVALIDATE_DEFINED
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215 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
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216 CYG_MACRO_START \
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217 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
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218 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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219 register CYG_WORD _size_ = (_asize_); \
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220 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
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221 asm volatile (" cache %0, 0(%1)" \
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222 : \
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223 : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)), \
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224 "r"(_addr_)); \
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225 CYG_MACRO_END
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226
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227
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228
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229
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230
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231
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232 //-----------------------------------------------------------------------------
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233 // Global control of Instruction cache
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234
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235 // Invalidate the entire cache
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236 #define HAL_ICACHE_INVALIDATE_ALL_DEFINED
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237 #define HAL_ICACHE_INVALIDATE_ALL() \
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238 CYG_MACRO_START \
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239 register volatile CYG_BYTE *addr; \
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240 HAL_CLEAR_TAGLO(); \
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241 HAL_CLEAR_TAGHI(); \
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242 for (addr = (CYG_BYTE *)CYGARC_KSEG_CACHED_BASE; \
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243 addr < (CYG_BYTE *)(CYGARC_KSEG_CACHED_BASE + HAL_ICACHE_SIZE); \
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244 addr += HAL_ICACHE_LINE_SIZE ) \
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245 { \
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246 asm volatile (" cache %0, 0(%1)" \
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247 : \
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248 : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_INDEX_STORE_TAG)), \
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249 "r"(addr)); \
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250 } \
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251 CYG_MACRO_END
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252
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253 // Synchronize the contents of the cache with memory.
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254 extern void hal_icache_sync(void);
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255 #define HAL_ICACHE_SYNC_DEFINED
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256 #define HAL_ICACHE_SYNC() hal_icache_sync()
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257
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258 // Set the instruction cache refill burst size
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259 //#define HAL_ICACHE_BURST_SIZE(_asize_)
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260
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261 // Load the contents of the given address range into the data cache
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262 // and then lock the cache so that it stays there.
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263 #define HAL_ICACHE_LOCK_DEFINED
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264 #define HAL_ICACHE_LOCK(_base_, _asize_) \
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265 CYG_MACRO_START \
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266 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
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267 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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268 register CYG_WORD _size_ = (_asize_); \
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269 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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270 asm volatile (" cache %0, 0(%1)" \
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271 : \
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272 : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_FETCH_AND_LOCK)), \
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273 "r"(_addr_)); \
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274 CYG_MACRO_END
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275
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276 // Undo a previous lock operation
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277 #define HAL_ICACHE_UNLOCK_DEFINED
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278 #define HAL_ICACHE_UNLOCK(_base_, _asize_) \
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279 CYG_MACRO_START \
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280 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
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281 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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282 register CYG_WORD _size_ = (_asize_); \
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283 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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284 asm volatile (" cache %0, 0(%1)" \
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285 : \
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286 : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)), \
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287 "r"(_addr_)); \
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288 CYG_MACRO_END
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289
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290 // Unlock entire cache
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291 #define HAL_ICACHE_UNLOCK_ALL_DEFINED
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292 #define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0,HAL_ICACHE_SIZE)
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293
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294 //-----------------------------------------------------------------------------
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295 // Instruction cache line control
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296
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297 // Invalidate cache lines in the given range without writing to memory.
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298 #define HAL_ICACHE_INVALIDATE_DEFINED
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299 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
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300 CYG_MACRO_START \
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301 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
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302 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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303 register CYG_WORD _size_ = (_asize_); \
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304 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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305 asm volatile (" cache %0, 0(%1)" \
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306 : \
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307 : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)), \
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308 "r"(_addr_)); \
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309 CYG_MACRO_END
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310
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311 //-----------------------------------------------------------------------------
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312 #endif // ifndef CYGONCE_IMP_CACHE_H
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313 // End of imp_cache.h