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annotate packages/hal/openrisc/arch/current/include/hal_arch.h @ 2729:74dbf4c3f2e1 after-copyright-change-20090129
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
| author | jlarmour |
|---|---|
| date | Thu, 29 Jan 2009 17:47:46 +0000 |
| parents | 38840e07f305 |
| children |
| rev | line source |
|---|---|
| 964 | 1 //========================================================================== |
| 2 // | |
| 3 // hal_arch.h | |
| 4 // | |
| 5 // Architecture specific abstractions | |
| 6 // | |
| 7 //========================================================================== | |
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8 // ####ECOSGPLCOPYRIGHTBEGIN#### |
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9 // ------------------------------------------- |
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10 // This file is part of eCos, the Embedded Configurable Operating System. |
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
| 964 | 12 // |
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13 // eCos is free software; you can redistribute it and/or modify it under |
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14 // the terms of the GNU General Public License as published by the Free |
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15 // Software Foundation; either version 2 or (at your option) any later |
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16 // version. |
| 964 | 17 // |
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT |
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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21 // for more details. |
| 964 | 22 // |
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23 // You should have received a copy of the GNU General Public License |
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24 // along with eCos; if not, write to the Free Software Foundation, Inc., |
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
| 964 | 26 // |
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27 // As a special exception, if other files instantiate templates or use |
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28 // macros or inline functions from this file, or you compile this file |
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29 // and link it with other works to produce a work based on this file, |
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30 // this file does not by itself cause the resulting work to be covered by |
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31 // the GNU General Public License. However the source code for this file |
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32 // must still be made available in accordance with section (3) of the GNU |
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33 // General Public License v2. |
| 964 | 34 // |
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35 // This exception does not invalidate any other reasons why a work based |
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36 // on this file might be covered by the GNU General Public License. |
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37 // ------------------------------------------- |
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38 // ####ECOSGPLCOPYRIGHTEND#### |
| 964 | 39 //========================================================================== |
| 40 //#####DESCRIPTIONBEGIN#### | |
| 41 // | |
| 42 // Author(s): sfurman | |
| 43 // Contributors: | |
| 44 // Date: 2003-01-17 | |
| 45 // Purpose: Define architecture abstractions | |
| 46 // Usage: #include <cyg/hal/hal_arch.h> | |
| 47 // | |
| 48 //####DESCRIPTIONEND#### | |
| 49 // | |
| 50 //========================================================================== | |
| 51 | |
| 52 #ifndef CYGONCE_HAL_HAL_ARCH_H | |
| 53 #define CYGONCE_HAL_HAL_ARCH_H | |
| 54 | |
| 55 // Include macros to access special-purpose registers (SPRs) | |
| 56 #include <cyg/hal/spr_defs.h> | |
| 57 | |
| 58 #define CYG_HAL_OPENRISC_REG_SIZE 4 | |
| 59 | |
| 60 #ifndef __ASSEMBLER__ | |
| 61 #include <pkgconf/hal.h> | |
| 62 #include <cyg/infra/cyg_type.h> | |
| 63 | |
| 64 //-------------------------------------------------------------------------- | |
| 65 // Processor saved states: | |
| 66 // The layout of this structure is also defined in "arch.inc", for assembly | |
| 67 // code. Do not change this without changing that (or vice versa). | |
| 68 | |
| 69 #define CYG_HAL_OPENRISC_REG CYG_WORD32 | |
| 70 | |
| 71 typedef struct | |
| 72 { | |
| 73 // These are common to all saved states | |
| 74 CYG_HAL_OPENRISC_REG r[32]; // GPR regs | |
| 75 CYG_HAL_OPENRISC_REG machi; // High and low words of | |
| 76 CYG_HAL_OPENRISC_REG maclo; // multiply/accumulate reg | |
| 77 | |
| 78 // These are only saved for exceptions and interrupts | |
| 79 CYG_WORD32 vector; /* Vector number */ | |
| 80 CYG_WORD32 sr; /* Status Reg */ | |
| 81 CYG_HAL_OPENRISC_REG pc; /* Program Counter */ | |
| 82 | |
| 83 // Saved only for exceptions, and not restored when continued: | |
| 84 // Effective address of instruction/data access that caused exception | |
| 85 CYG_HAL_OPENRISC_REG eear; /* Exception effective address reg */ | |
| 86 } HAL_SavedRegisters; | |
| 87 | |
| 88 //-------------------------------------------------------------------------- | |
| 89 // Utilities | |
| 90 | |
| 91 // Move from architecture special register (SPR) | |
| 92 #define MFSPR(_spr_) \ | |
| 93 ({ CYG_HAL_OPENRISC_REG _result_; \ | |
| 94 asm volatile ("l.mfspr %0, r0, %1;" \ | |
| 95 : "=r"(_result_) \ | |
| 96 : "K"(_spr_) \ | |
| 97 ); \ | |
| 98 _result_;}) | |
| 99 | |
| 100 // Move data to architecture special registers (SPR) | |
| 101 #define MTSPR(_spr_, _val_) \ | |
| 102 CYG_MACRO_START \ | |
| 103 CYG_HAL_OPENRISC_REG val = _val_; \ | |
| 104 asm volatile ("l.mtspr r0, %0, %1;" \ | |
| 105 : \ | |
| 106 : "r"(val), "K"(_spr_) \ | |
| 107 ); \ | |
| 108 CYG_MACRO_END | |
| 109 | |
| 110 //-------------------------------------------------------------------------- | |
| 111 // Exception handling function. | |
| 112 // This function is defined by the kernel according to this prototype. It is | |
| 113 // invoked from the HAL to deal with any CPU exceptions that the HAL does | |
| 114 // not want to deal with itself. It usually invokes the kernel's exception | |
| 115 // delivery mechanism. | |
| 116 | |
| 117 externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data ); | |
| 118 | |
| 119 //-------------------------------------------------------------------------- | |
| 120 // Bit manipulation macros | |
| 121 | |
| 122 externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask); | |
| 123 externC cyg_uint32 hal_msbit_index(cyg_uint32 mask); | |
| 124 | |
| 125 #define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask); | |
| 126 | |
| 127 // NOTE - Below can be optimized with l.ff1 instruction if that optional | |
| 128 // instruction is implemented in HW. OR12k does not implement | |
| 129 // it at this time, however. | |
| 130 #define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask); | |
| 131 | |
| 132 //-------------------------------------------------------------------------- | |
| 133 // Context Initialization | |
| 134 | |
| 135 | |
| 136 // Initialize the context of a thread. | |
| 137 // Arguments: | |
| 138 // _sparg_ name of variable containing current sp, will be written with new sp | |
| 139 // _thread_ thread object address, passed as argument to entry point | |
| 140 // _entry_ entry point address. | |
| 141 // _id_ bit pattern used in initializing registers, for debugging. | |
| 142 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ | |
| 143 { \ | |
| 144 int _i_; \ | |
| 145 register CYG_WORD _sp_ = ((CYG_WORD)_sparg_); \ | |
| 146 register HAL_SavedRegisters *_regs_; \ | |
| 147 _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters)) & ~(CYGARC_ALIGNMENT));\ | |
| 148 _sp_ &= ~(CYGARC_ALIGNMENT); \ | |
| 149 for( _i_ = 1; _i_ < 32; _i_++ ) (_regs_)->r[_i_] = (_id_)|_i_; \ | |
| 150 (_regs_)->r[1] = (CYG_HAL_OPENRISC_REG)(_sp_); /* SP = top of stack */ \ | |
| 151 (_regs_)->r[2] = (CYG_HAL_OPENRISC_REG)(_sp_); /* FP = top of stack */ \ | |
| 152 (_regs_)->r[3] = (CYG_HAL_OPENRISC_REG)(_thread_); /* R3 = arg1 = thread ptr */ \ | |
| 153 (_regs_)->maclo = 0; /* MACLO = 0 */ \ | |
| 154 (_regs_)->machi = 0; /* MACHI = 0 */ \ | |
| 155 (_regs_)->sr = (SPR_SR_TEE|SPR_SR_IEE); /* Interrupts enabled */ \ | |
| 156 (_regs_)->pc = (CYG_HAL_OPENRISC_REG)(_entry_); /* PC = entry point */ \ | |
| 157 (_regs_)->r[9] = (CYG_HAL_OPENRISC_REG)(_entry_); /* PC = entry point */ \ | |
| 158 _sparg_ = (CYG_ADDRESS)_regs_; \ | |
| 159 } | |
| 160 | |
| 161 //-------------------------------------------------------------------------- | |
| 162 // Context switch macros. | |
| 163 | |
| 164 // The arguments to these macros are *pointers* to locations where the | |
| 165 // stack pointer of the thread is to be stored/retrieved, i.e. *not* | |
| 166 // the value of the stack pointer itself. | |
| 167 | |
| 168 externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); | |
| 169 externC void hal_thread_load_context( CYG_ADDRESS to ) | |
| 170 __attribute__ ((noreturn)); | |
| 171 | |
| 172 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \ | |
| 173 hal_thread_switch_context( (CYG_ADDRESS)_tspptr_, \ | |
| 174 (CYG_ADDRESS)_fspptr_); | |
| 175 | |
| 176 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \ | |
| 177 hal_thread_load_context( (CYG_ADDRESS)_tspptr_ ); | |
| 178 | |
| 179 // Translate a stack pointer as saved by the thread context macros above into | |
| 180 // a pointer to a HAL_SavedRegisters structure. | |
| 181 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ | |
| 182 (_regs_) = (HAL_SavedRegisters *)(_sp_) | |
| 183 | |
| 184 //-------------------------------------------------------------------------- | |
| 185 // Execution reorder barrier. | |
| 186 // When optimizing the compiler can reorder code. In multithreaded systems | |
| 187 // where the order of actions is vital, this can sometimes cause problems. | |
| 188 // This macro may be inserted into places where reordering should not happen. | |
| 189 // The "memory" keyword is potentially unnecessary, but it is harmless to | |
| 190 // keep it. | |
| 191 | |
| 192 #define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) | |
| 193 | |
| 194 //-------------------------------------------------------------------------- | |
| 195 // Breakpoint support | |
| 196 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to | |
| 197 // occur if executed. | |
| 198 // HAL_BREAKINST is the value of the breakpoint instruction and... | |
| 199 // HAL_BREAKINST_SIZE is its size in bytes and... | |
| 200 // HAL_BREAKINST_TYPE is its type. | |
| 201 | |
| 202 #define HAL_BREAKPOINT(_label_) \ | |
| 203 asm volatile (" .globl _" #_label_ ";" \ | |
| 204 "_" #_label_ ":" \ | |
| 205 " l.trap 1;" \ | |
| 206 ); | |
| 207 | |
| 208 #define HAL_BREAKINST (0x21000001) // l.trap 1 instruction | |
| 209 | |
| 210 #define HAL_BREAKINST_SIZE 4 | |
| 211 | |
| 212 #define HAL_BREAKINST_TYPE cyg_uint32 | |
| 213 | |
| 214 //-------------------------------------------------------------------------- | |
| 215 // Thread register state manipulation for GDB support. | |
| 216 | |
| 217 // Default to a 32 bit register size for GDB register dumps. | |
| 218 #ifndef CYG_HAL_GDB_REG | |
| 219 #define CYG_HAL_GDB_REG CYG_WORD32 | |
| 220 #endif | |
| 221 | |
| 222 // Register layout expected by GDB | |
| 223 typedef struct | |
| 224 { | |
| 225 CYG_HAL_OPENRISC_REG r[32]; // GPR regs | |
| 226 CYG_HAL_OPENRISC_REG pc; // Program Counter | |
| 227 CYG_HAL_OPENRISC_REG sr; // Supervisor/Status Reg | |
| 228 } GDB_Registers; | |
| 229 | |
| 230 // Copy a set of registers from a HAL_SavedRegisters structure into a | |
| 231 // GDB_Registers structure. | |
| 232 #define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \ | |
| 233 CYG_MACRO_START \ | |
| 234 GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_); \ | |
| 235 int _i_; \ | |
| 236 \ | |
| 237 for( _i_ = 0; _i_ < 32; _i_++ ) { \ | |
| 238 _gdb_->r[_i_] = (_regs_)->r[_i_]; \ | |
| 239 } \ | |
| 240 \ | |
| 241 _gdb_->pc = (_regs_)->pc; \ | |
| 242 _gdb_->sr = (_regs_)->sr; \ | |
| 243 CYG_MACRO_END | |
| 244 | |
| 245 // Copy a set of registers from a GDB_Registers structure into a | |
| 246 // HAL_SavedRegisters structure. | |
| 247 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ | |
| 248 CYG_MACRO_START \ | |
| 249 GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_); \ | |
| 250 int _i_; \ | |
| 251 \ | |
| 252 for( _i_ = 0; _i_ < 32; _i_++ ) \ | |
| 253 (_regs_)->r[_i_] = _gdb_->r[_i_]; \ | |
| 254 \ | |
| 255 (_regs_)->pc = _gdb_->pc; \ | |
| 256 (_regs_)->sr = _gdb_->sr; \ | |
| 257 CYG_MACRO_END | |
| 258 | |
| 259 //-------------------------------------------------------------------------- | |
| 260 // HAL setjmp | |
| 261 // Note: These definitions are repeated in context.S. If changes are | |
| 262 // required remember to update both sets. | |
| 263 | |
| 264 #define CYGARC_JMP_BUF_R1 0 | |
| 265 #define CYGARC_JMP_BUF_R2 1 | |
| 266 #define CYGARC_JMP_BUF_R9 2 | |
| 267 #define CYGARC_JMP_BUF_R10 3 | |
| 268 #define CYGARC_JMP_BUF_R12 4 | |
| 269 #define CYGARC_JMP_BUF_R14 5 | |
| 270 #define CYGARC_JMP_BUF_R16 6 | |
| 271 #define CYGARC_JMP_BUF_R18 7 | |
| 272 #define CYGARC_JMP_BUF_R20 8 | |
| 273 #define CYGARC_JMP_BUF_R22 9 | |
| 274 #define CYGARC_JMP_BUF_R24 10 | |
| 275 #define CYGARC_JMP_BUF_R26 11 | |
| 276 #define CYGARC_JMP_BUF_R28 12 | |
| 277 #define CYGARC_JMP_BUF_R30 13 | |
| 278 | |
| 279 #define CYGARC_JMP_BUF_SIZE 14 | |
| 280 | |
| 281 typedef CYG_HAL_OPENRISC_REG hal_jmp_buf[CYGARC_JMP_BUF_SIZE]; | |
| 282 | |
| 283 externC int hal_setjmp(hal_jmp_buf env); | |
| 284 externC void hal_longjmp(hal_jmp_buf env, int val); | |
| 285 | |
| 286 //------------------------------------------------------------------------- | |
| 287 // Idle thread code. | |
| 288 // This macro is called in the idle thread loop, and gives the HAL the | |
| 289 // chance to run code when no threads are runnable. Typical idle | |
| 290 // thread behaviour might be to halt the processor. | |
| 291 | |
| 292 externC void hal_idle_thread_action(cyg_uint32 loop_count); | |
| 293 | |
| 294 #define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_) | |
| 295 | |
| 296 //-------------------------------------------------------------------------- | |
| 297 // Minimal and sensible stack sizes: the intention is that applications | |
| 298 // will use these to provide a stack size in the first instance prior to | |
| 299 // proper analysis. Idle thread stack should be this big. | |
| 300 | |
| 301 // *** THESE ARE NOT INTENDED TO BE GUARANTEED SUFFICIENT STACK SIZES *** | |
| 302 // They are, however, enough to start programming. | |
| 303 // You might, for example, need to make your stacks larger if you have | |
| 304 // large "auto" variables. | |
| 305 | |
| 306 // This is not a config option because it should not be adjusted except | |
| 307 // under "enough rope to hang yourself" sort of disclaimers. | |
| 308 | |
| 309 // Typical case stack frame size: return link + 10 caller-saved temporaries + 4 locals. | |
| 310 #define CYGNUM_HAL_STACK_FRAME_SIZE (15 * CYG_HAL_OPENRISC_REG_SIZE) | |
| 311 | |
| 312 // Stack needed for a context switch: | |
| 313 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (38 * 4) // sizeof(HAL_SavedRegisters) | |
| 314 | |
| 315 // Interrupt + call to ISR, interrupt_end() and the DSR | |
| 316 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE (CYGNUM_HAL_STACK_CONTEXT_SIZE + 2*CYGNUM_HAL_STACK_FRAME_SIZE) | |
| 317 | |
| 318 // We define a minimum stack size as the minimum any thread could ever | |
| 319 // legitimately get away with. We can throw asserts if users ask for less | |
| 320 // than this. Allow enough for three interrupt sources - clock, serial and | |
| 321 // one other | |
| 322 | |
| 323 // If interrupts are segregated onto their own stack... | |
| 324 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 325 | |
| 326 // An interrupt stack which is large enough for all possible interrupt | |
| 327 // conditions (and only used for that purpose) exists. "User" stacks | |
| 328 // can therefore be much smaller | |
| 329 // NOTE - interrupt stack sizes can be smaller if we don't allow interrupts | |
| 330 // to nest. | |
| 331 | |
| 332 # define CYGNUM_HAL_STACK_SIZE_MINIMUM \ | |
| 333 ((3 * 5)*CYGNUM_HAL_STACK_FRAME_SIZE + 2*CYGNUM_HAL_STACK_INTERRUPT_SIZE) | |
| 334 | |
| 335 #else | |
| 336 | |
| 337 // No separate interrupt stack exists. Make sure all threads contain | |
| 338 // a stack sufficiently large | |
| 339 # define CYGNUM_HAL_STACK_SIZE_MINIMUM \ | |
| 340 (( 3*CYGNUM_HAL_STACK_INTERRUPT_SIZE) + \ | |
| 341 (25*CYGNUM_HAL_STACK_FRAME_SIZE)) | |
| 342 #endif | |
| 343 | |
| 344 // Now make a reasonable choice for a typical thread size. Pluck figures | |
| 345 // from thin air and say 40 call frames | |
| 346 #define CYGNUM_HAL_STACK_SIZE_TYPICAL \ | |
| 347 (CYGNUM_HAL_STACK_SIZE_MINIMUM + \ | |
| 348 40 * (CYGNUM_HAL_STACK_FRAME_SIZE)) | |
| 349 | |
| 350 #endif /* __ASSEMBLER__ */ | |
| 351 | |
| 352 //-------------------------------------------------------------------------- | |
| 353 // Macros for switching context between two eCos instances (jump from | |
| 354 // code in ROM to code in RAM or vice versa). | |
| 355 // These are NOP's in the case of OpenRISC. | |
| 356 #define CYGARC_HAL_SAVE_GP() | |
| 357 #define CYGARC_HAL_RESTORE_GP() | |
| 358 | |
| 359 //-------------------------------------------------------------------------- | |
| 360 // Macro for finding return address of current function | |
| 361 #define CYGARC_HAL_GET_RETURN_ADDRESS(_x_, _dummy_) \ | |
| 362 asm volatile ( "l.ori %0,r9,0;" : "=r" (_x_) ) | |
| 363 | |
| 364 #define CYGARC_HAL_GET_RETURN_ADDRESS_BACKUP(_dummy_) | |
| 365 | |
| 366 //-------------------------------------------------------------------------- | |
| 367 #endif // CYGONCE_HAL_HAL_ARCH_H | |
| 368 // End of hal_arch.h |