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annotate packages/hal/powerpc/ec555/current/src/ec555.S @ 2729:74dbf4c3f2e1 after-copyright-change-20090129

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Update all copyright banners to reflect FSF ownership; fix and improve licence text.
author jlarmour
date Thu, 29 Jan 2009 17:47:46 +0000
parents 1d6110795758
children
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1 ##=============================================================================
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2 ##
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3 ## ec555.S
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4 ##
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5 ## ec555 board hardware setup
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6 ##
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7 ##=============================================================================
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8 ## ####ECOSGPLCOPYRIGHTBEGIN####
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9 ## -------------------------------------------
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10 ## This file is part of eCos, the Embedded Configurable Operating System.
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11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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12 ##
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13 ## eCos is free software; you can redistribute it and/or modify it under
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14 ## the terms of the GNU General Public License as published by the Free
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15 ## Software Foundation; either version 2 or (at your option) any later
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16 ## version.
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17 ##
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18 ## eCos is distributed in the hope that it will be useful, but WITHOUT
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19 ## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 ## for more details.
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22 ##
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23 ## You should have received a copy of the GNU General Public License
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24 ## along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 ## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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26 ##
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27 ## As a special exception, if other files instantiate templates or use
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28 ## macros or inline functions from this file, or you compile this file
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29 ## and link it with other works to produce a work based on this file,
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30 ## this file does not by itself cause the resulting work to be covered by
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31 ## the GNU General Public License. However the source code for this file
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32 ## must still be made available in accordance with section (3) of the GNU
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33 ## General Public License v2.
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34 ##
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35 ## This exception does not invalidate any other reasons why a work based
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36 ## on this file might be covered by the GNU General Public License.
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37 ## -------------------------------------------
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38 ## ####ECOSGPLCOPYRIGHTEND####
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39 ##=============================================================================
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40 #######DESCRIPTIONBEGIN####
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41 ##
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42 ## Author(s): Bob Koninckx
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43 ## Contributors:Bob Koninckx
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44 ## Date: 2002-01-01
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45 ## Purpose: ec555 board hardware setup
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46 ## Description: This file contains any code needed to initialize the
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47 ## hardware on a ec555 mpc555 board.
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48 ##
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49 ######DESCRIPTIONEND####
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50 ##
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51 ##=============================================================================
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52
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53 #include <pkgconf/hal.h>
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54
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55 #include <cyg/hal/ppc_regs.h>
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56 #include <cyg/hal/arch.inc>
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57
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58 #include <pkgconf/system.h>
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59 #ifdef CYGPKG_DEVS_ETH_POWERPC_EC555
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60 #include <pkgconf/devs_eth_powerpc_ec555.h>
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61 #endif
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62
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63 ## FIXME
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64 ## The following probably belongs in the variant hal rather than the board specifics ...
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65 #ifdef CYGPKG_DEVICES_WATCHDOG_MPC5xx
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66 #include <pkgconf/devices_watchdog_mpc5xx.h>
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67 #define CYG_SYPCR 0x0000ff8e | (CYGNUM_DEVICES_WATCHDOG_POWERPC_MPC5XX_RELOAD << 16) | CYGDAT_DEVICES_WATCHDOG_POWERPC_MPC5XX_PRESCALE
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68 #else
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69 #define CYG_SYPCR 0x0000ff88
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70 #endif
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71
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72 #define ADDRESS_MASK_1MB 0xfff00000
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73 #define ADDRESS_MASK_2MB 0xffe00000
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74 #define ADDRESS_MASK_4MB 0xffc00000
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75 #define ADDRESS_MASK_8MB 0xff800000
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76 #define ADDRESS_MASK_16MB 0xff000000
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77
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78 #define EC555_RAM_BASE_ADDRESS 0x01000000
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79 #define EC555_FLASH_BASE_ADDRESS 0x02000000
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80 #define EC555_CS2_BASE_ADDRESS 0x04000000
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81 #define EC555_CS3_BASE_ADDRESS 0x08000000
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82
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83 #if defined(CYGHWR_HAL_EC555_BOARD_VARIANT_F02_S01)
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84 #define EC555_RAM_ADDRESS_MASK ADDRESS_MASK_1MB
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85 #define EC555_FLASH_ADDRESS_MASK ADDRESS_MASK_2MB
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86 #elif defined(CYGHWR_HAL_EC555_BOARD_VARIANT_F04_S02)
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87 #define EC555_RAM_ADDRESS_MASK ADDRESS_MASK_2MB
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88 #define EC555_FLASH_ADDRESS_MASK ADDRESS_MASK_4MB
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89 #elif defined(CYGHWR_HAL_EC555_BOARD_VARIANT_F08_S04)
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90 #define EC555_RAM_ADDRESS_MASK ADDRESS_MASK_4MB
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91 #define EC555_FLASH_ADDRESS_MASK ADDRESS_MASK_8MB
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92 #elif defined(CYGHWR_HAL_EC555_BOARD_VARIANT_F08_S08)
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93 #define EC555_RAM_ADDRESS_MASK ADDRESS_MASK_8MB
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94 #define EC555_FLASH_ADDRESS_MASK ADDRESS_MASK_16MB
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95 #else
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96 #error "EC555 Board variant unspecified"
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97 #endif
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98
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99 #define EC555_CS2_ADDRESS_MASK 0xffff8000
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100 #define EC555_CS3_ADDRESS_MASK 0xffff8000
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101
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102 #------------------------------------------------------------------------------
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103
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104 .globl hal_hardware_init
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105 hal_hardware_init:
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106 #if defined(CYGPKG_HAL_POWERPC_EC555) && defined(CYGPKG_HAL_POWERPC_MPC5xx)
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107 lwi r3, CYGARC_REG_IMM_BASE # Base address of control registers
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108
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109 #if defined(CYG_HAL_STARTUP_ROM)
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110 // Burst enable
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111 lwi r0, 0x00002000
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112 mtspr 560, r0
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113
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114 // FIXME
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115 // The following probably belongs in the variant hal rather than the board specifics ...
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116 // Disable / enable the Watchdog
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117 lwi r4, CYG_SYPCR
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118 stw r4, (CYGARC_REG_IMM_SYPCR-CYGARC_REG_IMM_BASE)(r3)
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119 lwi r4, 0x00000000
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120 stw r4, (CYGARC_REG_IMM_SIUMCR-CYGARC_REG_IMM_BASE)(r3)
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121
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122 // Unlock locked registers
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123 lwi r4, 0x55ccaa33
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124 stw r4, (CYGARC_REG_IMM_TBSCRK-CYGARC_REG_IMM_BASE)(r3)
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125 stw r4, (CYGARC_REG_IMM_TBREF0K-CYGARC_REG_IMM_BASE)(r3)
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126 stw r4, (CYGARC_REG_IMM_TBREF1K-CYGARC_REG_IMM_BASE)(r3)
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127 stw r4, (CYGARC_REG_IMM_TBK-CYGARC_REG_IMM_BASE)(r3)
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128 stw r4, (CYGARC_REG_IMM_RTCSCK-CYGARC_REG_IMM_BASE)(r3)
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129 stw r4, (CYGARC_REG_IMM_RTCK-CYGARC_REG_IMM_BASE)(r3)
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130 stw r4, (CYGARC_REG_IMM_RTSECK-CYGARC_REG_IMM_BASE)(r3)
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131 stw r4, (CYGARC_REG_IMM_RTCALK-CYGARC_REG_IMM_BASE)(r3)
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132 stw r4, (CYGARC_REG_IMM_PISCRK-CYGARC_REG_IMM_BASE)(r3)
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133 stw r4, (CYGARC_REG_IMM_PITCK-CYGARC_REG_IMM_BASE)(r3)
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jlarmour
parents:
diff changeset
134 stw r4, (CYGARC_REG_IMM_SCCRK-CYGARC_REG_IMM_BASE)(r3)
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jlarmour
parents:
diff changeset
135 stw r4, (CYGARC_REG_IMM_PLPRCRK-CYGARC_REG_IMM_BASE)(r3)
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jlarmour
parents:
diff changeset
136 stw r4, (CYGARC_REG_IMM_RSRK-CYGARC_REG_IMM_BASE)(r3)
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jlarmour
parents:
diff changeset
137
1397
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gthomas
parents: 210
diff changeset
138 // Either Redboot or BDM will have already done it otherwise
208
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jlarmour
parents:
diff changeset
139 // Boost the clock to 40MHz
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jlarmour
parents:
diff changeset
140 lwi r4, 0x03000000
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jlarmour
parents:
diff changeset
141 stw r4, (CYGARC_REG_IMM_SCCR-CYGARC_REG_IMM_BASE)(r3)
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jlarmour
parents:
diff changeset
142 lwi r4, 0x009150c0
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jlarmour
parents:
diff changeset
143 stw r4, (CYGARC_REG_IMM_PLPRCR-CYGARC_REG_IMM_BASE)(r3)
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jlarmour
parents:
diff changeset
144 lwi r4, 0x0080
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jlarmour
parents:
diff changeset
145 sth r4, (CYGARC_REG_IMM_COLIR-CYGARC_REG_IMM_BASE)(r3)
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jlarmour
parents:
diff changeset
146
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jlarmour
parents:
diff changeset
147 // Set up the memory map
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parents:
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148 // Do NOT write protect the flash memory, flash drivers won't work
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parents:
diff changeset
149 // if we do
1616
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
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150
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
parents: 1397
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151 // flash banks
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
parents: 1397
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152 lwi r4, (EC555_FLASH_BASE_ADDRESS | 0x00000003)
208
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jlarmour
parents:
diff changeset
153 stw r4, (CYGARC_REG_IMM_BR0-CYGARC_REG_IMM_BASE)(r3)
1616
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
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parents: 1397
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154 lwi r4, (EC555_FLASH_ADDRESS_MASK | 0x00000530)
208
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jlarmour
parents:
diff changeset
155 stw r4, (CYGARC_REG_IMM_OR0-CYGARC_REG_IMM_BASE)(r3)
1616
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156
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
parents: 1397
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157 // ram banks
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
parents: 1397
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158 lwi r4, (EC555_RAM_BASE_ADDRESS | 0x00000011)
208
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jlarmour
parents:
diff changeset
159 stw r4, (CYGARC_REG_IMM_BR1-CYGARC_REG_IMM_BASE)(r3)
1616
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
parents: 1397
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160 lwi r4, (EC555_RAM_ADDRESS_MASK | 0x00000000)
208
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parents:
diff changeset
161 stw r4, (CYGARC_REG_IMM_OR1-CYGARC_REG_IMM_BASE)(r3)
1397
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gthomas
parents: 210
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162 #endif
9c818dd5d9fa Updates for EC555 targets - from Bob Koninckx
gthomas
parents: 210
diff changeset
163
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gthomas
parents: 210
diff changeset
164 #ifdef CYGPKG_DEVS_ETH_POWERPC_EC555
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165 #if (CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_CS == 2)
1616
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
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166 lwi r4, (EC555_CS2_BASE_ADDRESS | 0x00000803)
1397
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gthomas
parents: 210
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167 stw r4, (CYGARC_REG_IMM_BR2-CYGARC_REG_IMM_BASE)(r3)
1764
1d6110795758 * src/ec555.S: Updated memory controller settings for ethernet card. Now
asl
parents: 1616
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168 lwi r4, 0xffff8ca0
1397
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gthomas
parents: 210
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169 stw r4, (CYGARC_REG_IMM_OR2-CYGARC_REG_IMM_BASE)(r3)
1616
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170
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
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171 lwi r4, EC555_CS3_BASE_ADDRESS
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gthomas
parents: 210
diff changeset
172 stw r4, (CYGARC_REG_IMM_BR3-CYGARC_REG_IMM_BASE)(r3)
1616
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
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173 lwi r4, EC555_CS3_ADDRESS_MASK
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
parents: 1397
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174 stw r4, (CYGARC_REG_IMM_OR3-CYGARC_REG_IMM_BASE)(r3)
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parents: 210
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175 #elif (CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_CS == 3)
1616
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jlarmour
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176 lwi r4, EC555_CS2_BASE_ADDRESS
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
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177 stw r4, (CYGARC_REG_IMM_BR2-CYGARC_REG_IMM_BASE)(r3)
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
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178 lwi r4, EC555_CS2_ADDRESS_MASK
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
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179 stw r4, (CYGARC_REG_IMM_OR2-CYGARC_REG_IMM_BASE)(r3)
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
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180
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
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181 lwi r4, (EC555_CS3_BASE_ADDRESS | 0x00000803)
1397
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gthomas
parents: 210
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182 stw r4, (CYGARC_REG_IMM_BR3-CYGARC_REG_IMM_BASE)(r3)
1764
1d6110795758 * src/ec555.S: Updated memory controller settings for ethernet card. Now
asl
parents: 1616
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183 lwi r4, 0xffff8ca0
1397
9c818dd5d9fa Updates for EC555 targets - from Bob Koninckx
gthomas
parents: 210
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184 stw r4, (CYGARC_REG_IMM_OR3-CYGARC_REG_IMM_BASE)(r3)
9c818dd5d9fa Updates for EC555 targets - from Bob Koninckx
gthomas
parents: 210
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185 #else
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186 #error "Invalid chip select for ethernet card specified"
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gthomas
parents: 210
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187 #endif
9c818dd5d9fa Updates for EC555 targets - from Bob Koninckx
gthomas
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188 #else
1616
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
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189 lwi r4, EC555_CS2_BASE_ADDRESS
208
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190 stw r4, (CYGARC_REG_IMM_BR2-CYGARC_REG_IMM_BASE)(r3)
1616
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
parents: 1397
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191 lwi r4, EC555_CS2_ADDRESS_MASK
208
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parents:
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192 stw r4, (CYGARC_REG_IMM_OR2-CYGARC_REG_IMM_BASE)(r3)
1616
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193
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
parents: 1397
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194 lwi r4, EC555_CS3_BASE_ADDRESS
208
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parents:
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195 stw r4, (CYGARC_REG_IMM_BR3-CYGARC_REG_IMM_BASE)(r3)
1616
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
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parents: 1397
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196 lwi r4, EC555_CS3_ADDRESS_MASK
208
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197 stw r4, (CYGARC_REG_IMM_OR3-CYGARC_REG_IMM_BASE)(r3)
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parents: 210
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198 #endif
208
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199
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parents:
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200 #if defined(CYGSEM_HAL_POWERPC_MPC5XX_IFLASH_DUAL_MAP)
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201 lwi r4, 1
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202 #else
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203 lwi r4, 0
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204 #endif
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205 stw r4, (CYGARC_REG_IMM_DMBR-CYGARC_REG_IMM_BASE)(r3)
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jlarmour
parents:
diff changeset
206 lwi r4, 0
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parents:
diff changeset
207 stw r4, (CYGARC_REG_IMM_DMOR-CYGARC_REG_IMM_BASE)(r3)
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parents:
diff changeset
208
1616
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
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209 // Enable the time base, but do _not_ set the freeze flag
126cd98e4832 * src/ec555.S: Corrected typo in initialisation of SYPCR to make sure
jlarmour
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diff changeset
210 lwi r4, 0xc1
208
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parents:
diff changeset
211 sth r4, (CYGARC_REG_IMM_TBSCR-CYGARC_REG_IMM_BASE)(r3)
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jlarmour
parents:
diff changeset
212
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jlarmour
parents:
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213 // RTC is clocked by 4MHz crystal, set the freeze flag
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jlarmour
parents:
diff changeset
214 lwi r4, 0xd2
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jlarmour
parents:
diff changeset
215 sth r4, (CYGARC_REG_IMM_RTCSC-CYGARC_REG_IMM_BASE)(r3)
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jlarmour
parents:
diff changeset
216
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jlarmour
parents:
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217 // Set the freeze flag for the Periodic interrupt timer
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jlarmour
parents:
diff changeset
218 lwi r4, 0x82
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parents:
diff changeset
219 sth r4, (CYGARC_REG_IMM_PISCR-CYGARC_REG_IMM_BASE)(r3)
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jlarmour
parents:
diff changeset
220
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jlarmour
parents:
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221 // USIU rest.
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jlarmour
parents:
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222 lwi r4, 0x00000000
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parents:
diff changeset
223 lwi r5, (CYGARC_REG_IMM_SGPIODT1-CYGARC_REG_IMM_BASE)
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jlarmour
parents:
diff changeset
224 stwx r4, r3, r5
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jlarmour
parents:
diff changeset
225 lwi r5, (CYGARC_REG_IMM_SGPIODT2-CYGARC_REG_IMM_BASE)
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jlarmour
parents:
diff changeset
226 stwx r4, r3, r5
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parents:
diff changeset
227 lwi r5, (CYGARC_REG_IMM_SGPIOCR-CYGARC_REG_IMM_BASE)
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jlarmour
parents:
diff changeset
228 stwx r4, r3, r5
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jlarmour
parents:
diff changeset
229 lwi r4, 0x00000ac6
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jlarmour
parents:
diff changeset
230 lwi r5, (CYGARC_REG_IMM_EMCR-CYGARC_REG_IMM_BASE)
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jlarmour
parents:
diff changeset
231 stwx r4, r3, r5
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jlarmour
parents:
diff changeset
232
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jlarmour
parents:
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233 // Dual ported TPU RAM
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jlarmour
parents:
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234 lwi r4, 0x0000
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jlarmour
parents:
diff changeset
235 lwi r5, (CYGARC_REG_IMM_DPTMCR-CYGARC_REG_IMM_BASE)
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jlarmour
parents:
diff changeset
236 sthx r4, r3, r5
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jlarmour
parents:
diff changeset
237
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jlarmour
parents:
diff changeset
238 lwi r4, 0xffa0
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jlarmour
parents:
diff changeset
239 lwi r5, (CYGARC_REG_IMM_RAMBAR-CYGARC_REG_IMM_BASE)
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jlarmour
parents:
diff changeset
240 sthx r4, r3, r5
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jlarmour
parents:
diff changeset
241
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jlarmour
parents:
diff changeset
242 lwi r4, 0x00
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jlarmour
parents:
diff changeset
243 lwi r5, (CYGARC_REG_IMM_PORTQS-CYGARC_REG_IMM_BASE)
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jlarmour
parents:
diff changeset
244 sthx r4, r3, r5
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jlarmour
parents:
diff changeset
245
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jlarmour
parents:
diff changeset
246 lwi r4, 0x00
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jlarmour
parents:
diff changeset
247 lwi r5, (CYGARC_REG_IMM_PQSPAR_DDRQST-CYGARC_REG_IMM_BASE)
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jlarmour
parents:
diff changeset
248 sthx r4, r3, r5
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jlarmour
parents:
diff changeset
249 lwi r5, (CYGARC_REG_IMM_MPIOSMDR-CYGARC_REG_IMM_BASE)
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jlarmour
parents:
diff changeset
250 sthx r4, r3, r5
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parents:
diff changeset
251 lwi r5, (CYGARC_REG_IMM_MPIOSMDDR-CYGARC_REG_IMM_BASE)
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jlarmour
parents:
diff changeset
252 sthx r4, r3, r5
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jlarmour
parents:
diff changeset
253 lwi r5, (CYGARC_REG_IMM_SRAMMCR_A-CYGARC_REG_IMM_BASE)
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jlarmour
parents:
diff changeset
254 sthx r4, r3, r5
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jlarmour
parents:
diff changeset
255
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jlarmour
parents:
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256 // They are assigned OCD functionality on this board
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jlarmour
parents:
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257 // Change the following to anything else and BDM will not work anymore
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parents:
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258 // on the ec555. This is not true for all MPC555 based boards, eg. cme555
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jlarmour
parents:
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259 // does not have this requirement
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260 lwi r4, 0x3
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261 lwi r5, (CYGARC_REG_IMM_MIOS1TPCR-CYGARC_REG_IMM_BASE)
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262 sthx r4, r3, r5
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263
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264 // Enable 32 interrupt priorities on the IMB3 unit
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265 lwi r4, 0x60000000
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266 lwi r5, (CYGARC_REG_IMM_UMCR-CYGARC_REG_IMM_BASE)
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267 stwx r4, r3, r5
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268 #endif
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269 sync
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270 blr
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271
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272 #------------------------------------------------------------------------------
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273 # end of ec555.S