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annotate packages/hal/sh/cq7750/current/cdl/hal_sh_sh7750_cq7750.cdl @ 2729:74dbf4c3f2e1 after-copyright-change-20090129

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Update all copyright banners to reflect FSF ownership; fix and improve licence text.
author jlarmour
date Thu, 29 Jan 2009 17:47:46 +0000
parents d2c90368aeef
children b3aec2531be4
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1 # ====================================================================
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2 #
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3 # hal_sh_sh7750_cq7750.cdl
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4 #
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5 # CQ7750 board HAL package configuration data
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6 #
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7 # ====================================================================
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8 ## ####ECOSGPLCOPYRIGHTBEGIN####
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9 ## -------------------------------------------
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10 ## This file is part of eCos, the Embedded Configurable Operating System.
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11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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12 ##
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13 ## eCos is free software; you can redistribute it and/or modify it under
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14 ## the terms of the GNU General Public License as published by the Free
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15 ## Software Foundation; either version 2 or (at your option) any later
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16 ## version.
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17 ##
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18 ## eCos is distributed in the hope that it will be useful, but WITHOUT
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19 ## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 ## for more details.
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22 ##
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23 ## You should have received a copy of the GNU General Public License
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24 ## along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 ## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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26 ##
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27 ## As a special exception, if other files instantiate templates or use
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28 ## macros or inline functions from this file, or you compile this file
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29 ## and link it with other works to produce a work based on this file,
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30 ## this file does not by itself cause the resulting work to be covered by
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31 ## the GNU General Public License. However the source code for this file
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32 ## must still be made available in accordance with section (3) of the GNU
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33 ## General Public License v2.
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34 ##
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35 ## This exception does not invalidate any other reasons why a work based
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36 ## on this file might be covered by the GNU General Public License.
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37 ## -------------------------------------------
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38 ## ####ECOSGPLCOPYRIGHTEND####
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39 # ====================================================================
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40 ######DESCRIPTIONBEGIN####
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41 #
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42 # Author(s): jskov
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43 # Original data: jskov
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44 # Contributors: Ryozaburo Suzuki
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45 # Date: 1999-10-29
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46 #
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47 #####DESCRIPTIONEND####
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48 #
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49 # ====================================================================
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50
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51 cdl_package CYGPKG_HAL_SH_SH7750_CQ7750 {
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52 display "CqREEK SH7750 board"
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53 parent CYGPKG_HAL_SH
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54 requires CYGPKG_HAL_SH_7750
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55 define_header hal_sh_sh7750_cq7750.h
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56 include_dir cyg/hal
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57 description "
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58 The cq HAL package provides the support needed to run
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59 eCos on a CqREEK SH7750 board."
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60
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61 compile hal_diag.c plf_misc.c
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62
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63 implements CYGINT_HAL_DEBUG_GDB_STUBS
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64 implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
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65 implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
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66 implements CYGINT_HAL_SH_PLF_BIGENDIAN_DEFAULT
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67
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68 define_proc {
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69 puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sh.h>"
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70 puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sh_sh7750_cq7750.h>"
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71
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72 puts $::cdl_header "#define CYGNUM_HAL_SH_SH4_SCIF_PORTS 1"
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73 puts $::cdl_header "#define CYGHWR_HAL_VSR_TABLE 0x08000000"
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74 puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0x08000100"
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75 }
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76
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77 cdl_component CYG_HAL_STARTUP {
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78 display "Startup type"
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79 flavor data
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80 legal_values {"RAM" "ROM"}
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81 default_value {"RAM"}
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82 no_define
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83 define -file system.h CYG_HAL_STARTUP
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84 description "
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85 When targetting the CQ7750 board it is possible to build
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86 the system for either RAM bootstrap or ROM bootstrap.
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87 RAM bootstrap generally requires that the board
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88 is equipped with ROMs containing a suitable ROM monitor or
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89 equivalent software that allows GDB to download the eCos
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90 application on to the board. The ROM bootstrap typically
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91 requires that the eCos application be blown into EPROMs or
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92 equivalent technology."
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93 }
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94
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95
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96 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
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97 display "Number of communication channels on the board"
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98 flavor data
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99 calculated 1
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100 }
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101
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102 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
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103 display "Debug serial port"
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104 flavor data
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105 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
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106 default_value 0
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107 description "
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108 The CQ/7750 board has only one serial port. This option
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109 chooses which port will be used to connect to a host
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110 running GDB."
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111 }
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112
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113 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
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114 display "Diagnostic serial port"
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115 flavor data
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116 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
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117 default_value 0
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118 description "
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119 The CQ/7750 board has only one serial port. This option
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120 chooses which port will be used for diagnostic output."
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121 }
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122
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123 cdl_component CYGHWR_HAL_SH_PLF_CLOCK_SETTINGS {
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124 display "SH on-chip platform clock controls"
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125 description "
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126 The various clocks used by the system are derived from
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127 these options."
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128 flavor none
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129 no_define
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130
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131 cdl_option CYGHWR_HAL_SH_OOC_XTAL {
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132 display "SH clock crystal"
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133 flavor data
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134 legal_values 9000000 to 66000000
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135 default_value 33333333
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136 no_define
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137 description "
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138 This option specifies the frequency of the crystal all
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139 other clocks are derived from."
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140 }
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141
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142 cdl_option CYGHWR_HAL_SH_OOC_PLL_1 {
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143 display "SH clock PLL circuit 1"
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144 flavor data
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145 default_value 6
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146 legal_values { 0 6 }
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147 description "
171
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148 This selects the multiplication factor provided by
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149 PLL1."
134
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150 }
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151
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152 cdl_option CYGHWR_HAL_SH_OOC_PLL_2 {
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153 display "SH clock PLL circuit 2"
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154 flavor data
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155 default_value 1
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156 legal_values { 0 1 }
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157 description "
171
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158 This selects the multiplication factor provided by
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159 PLL2. If PLL2 is disabled this option should
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160 be set to zero."
134
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161 }
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162
196
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163 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_1 {
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164 display "SH clock first clock divider"
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165 flavor data
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166 legal_values { 1 2 }
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167 default_value 1
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168 no_define
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169 description "
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170 First stage clock divider according to the mode (MD0..2).
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171 Set 2 for mode 2 and 4, otherwise set 1."
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172 }
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173
134
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174 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_IFC {
171
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175 display "SH CPU clock divider"
134
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176 flavor data
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177 default_value 1
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178 legal_values { 1 2 3 4 6 8 }
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179 description "
171
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180 This divider option affects the CPU clock."
134
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181 }
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182
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183 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_BFC {
171
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184 display "SH bus clock divider"
134
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185 flavor data
136
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186 default_value 3
134
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187 legal_values { 1 2 3 4 6 8 }
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188 description "
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189 This divider option affects the bus clock."
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190 }
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191
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192 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_PFC {
171
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193 display "SH peripheral clock divider"
134
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194 flavor data
136
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195 default_value 6
134
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196 legal_values { 1 2 3 4 6 8 }
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197 description "
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198 This divider option affects the peripheral clock."
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199 }
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200
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201 cdl_option CYGHWR_HAL_SH_OOC_CLOCK_MODE {
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202 display "SH clock mode"
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203 flavor data
136
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204 default_value 5
134
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205 legal_values { 0 1 2 3 4 5 }
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206 description "
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207 This option must mirror the clock mode hardwired on
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208 the MD0-MD2 pins of the CPU in order to correctly
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209 initialize the FRQCR register."
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210 }
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211 }
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212
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213 cdl_component CYGBLD_GLOBAL_OPTIONS {
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214 display "Global build options"
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215 flavor none
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216 parent CYGPKG_NONE
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217 description "
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218 Global build options including control over
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219 compiler flags, linker flags and choice of toolchain."
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220
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221
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222 cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
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223 display "Global command prefix"
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224 flavor data
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225 no_define
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226 default_value { "sh-elf" }
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227 description "
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228 This option specifies the command prefix used when
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229 invoking the build tools."
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230 }
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231
136
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232 # CPU flags should be -m4-nofpu
134
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233 cdl_option CYGBLD_GLOBAL_CFLAGS {
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234 display "Global compiler flags"
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235 flavor data
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236 no_define
136
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237 default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" : "-ml -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
134
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238 description "
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239 This option controls the global compiler flags which
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240 are used to compile all packages by
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241 default. Individual packages may define
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242 options which override these global flags."
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243 }
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244
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245 cdl_option CYGBLD_GLOBAL_LDFLAGS {
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246 display "Global linker flags"
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247 flavor data
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248 no_define
136
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249 default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" : "-ml -m3 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" }
134
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250 description "
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251 This option controls the global linker flags. Individual
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252 packages may define options which override these global flags."
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253 }
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254
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255 cdl_option CYGBLD_BUILD_GDB_STUBS {
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256 display "Build GDB stub ROM image"
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257 default_value 0
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258 requires { CYG_HAL_STARTUP == "ROM" }
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259 requires CYGSEM_HAL_ROM_MONITOR
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260 requires CYGBLD_BUILD_COMMON_GDB_STUBS
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261 requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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262 requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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263 requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
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264 requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
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265 requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
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266 no_define
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267 description "
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268 This option enables the building of the GDB stubs for the
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269 board. The common HAL controls takes care of most of the
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270 build process, but the final conversion from ELF image to
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271 binary data is handled by the platform CDL, allowing
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272 relocation of the data if necessary."
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273
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274 make -priority 320 {
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275 <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
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276 $(OBJCOPY) -O binary $< $@
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277 }
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278 }
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279 }
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280
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281 cdl_component CYGHWR_MEMORY_LAYOUT {
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282 display "Memory layout"
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283 flavor data
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284 no_define
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285 calculated { CYG_HAL_STARTUP == "RAM" ? "sh_sh7750_cq7750_ram" : \
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286 "sh_sh7750_cq7750_rom" }
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287
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288 cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
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289 display "Memory layout linker script fragment"
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290 flavor data
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291 no_define
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292 define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
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293 calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh7750_cq7750_ram.ldi>" : \
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294 "<pkgconf/mlt_sh_sh7750_cq7750_rom.ldi>" }
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295 }
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296
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297 cdl_option CYGHWR_MEMORY_LAYOUT_H {
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298 display "Memory layout header file"
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299 flavor data
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300 no_define
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301 define -file system.h CYGHWR_MEMORY_LAYOUT_H
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302 calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh7750_cq7750_ram.h>" : \
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303 "<pkgconf/mlt_sh_sh7750_cq7750_rom.h>" }
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304 }
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305 }
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306
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307 cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
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308 display "Work with a ROM monitor"
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309 flavor booldata
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310 legal_values { "GDB_stubs" }
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311 default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
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312 requires { CYG_HAL_STARTUP == "RAM" }
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313 parent CYGPKG_HAL_ROM_MONITOR
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314 requires !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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315 description "
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316 Support can be enabled for boot ROMs or ROM monitors which contain
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317 GDB stubs. This support changes various eCos semantics such as
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318 the encoding of diagnostic output, and the overriding of hardware
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319 interrupt vectors."
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320 }
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321
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322 cdl_option CYGSEM_HAL_ROM_MONITOR {
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323 display "Behave as a ROM monitor"
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324 flavor bool
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325 default_value 0
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326 parent CYGPKG_HAL_ROM_MONITOR
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327 requires { CYG_HAL_STARTUP == "ROM" }
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328 description "
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329 Enable this option if this program is to be used as a ROM monitor,
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330 i.e. applications will be loaded into RAM on the board, and this
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331 ROM monitor may process exceptions or interrupts generated from the
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332 application. This enables features such as utilizing a separate
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333 interrupt stack when exceptions are generated."
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334 }
177
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335
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336 cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
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337 display "Redboot HAL options"
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338 flavor none
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339 no_define
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340 parent CYGPKG_REDBOOT
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341 active_if CYGPKG_REDBOOT
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342 description "
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343 This option lists the target's requirements for a valid Redboot
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344 configuration."
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345
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346 cdl_option CYGBLD_BUILD_REDBOOT_BIN {
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347 display "Build Redboot ROM binary image"
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348 active_if CYGBLD_BUILD_REDBOOT
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349 default_value 1
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350 no_define
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351 description "This option enables the conversion of the Redboot ELF
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352 image to a binary image suitable for ROM programming."
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353
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354 make -priority 325 {
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355 <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
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356 $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
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357 $(OBJCOPY) -O srec $< $(@:.bin=.srec)
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358 $(OBJCOPY) -O binary $< $@
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359 }
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360 }
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361 }
134
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362 }