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annotate packages/hal/sh/hs7729pci/current/include/plf_io.h @ 2729:74dbf4c3f2e1 after-copyright-change-20090129

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Update all copyright banners to reflect FSF ownership; fix and improve licence text.
author jlarmour
date Thu, 29 Jan 2009 17:47:46 +0000
parents d2c90368aeef
children
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1 #ifndef CYGONCE_PLF_IO_H
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2 #define CYGONCE_PLF_IO_H
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3
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4 //=============================================================================
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5 //
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6 // plf_io.h
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7 //
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8 // Platform specific IO support
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9 //
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10 //=============================================================================
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11 // ####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later
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19 // version.
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20 //
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // for more details.
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25 //
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26 // You should have received a copy of the GNU General Public License
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27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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29 //
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30 // As a special exception, if other files instantiate templates or use
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31 // macros or inline functions from this file, or you compile this file
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32 // and link it with other works to produce a work based on this file,
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33 // this file does not by itself cause the resulting work to be covered by
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34 // the GNU General Public License. However the source code for this file
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35 // must still be made available in accordance with section (3) of the GNU
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36 // General Public License v2.
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37 //
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38 // This exception does not invalidate any other reasons why a work based
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39 // on this file might be covered by the GNU General Public License.
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40 // -------------------------------------------
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41 // ####ECOSGPLCOPYRIGHTEND####
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42 //=============================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): jskov
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46 // Contributors: jskov
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47 // Date: 2001-05-29
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48 // Purpose: HS7729PCI SD0001 PCI IO support macros
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49 // Description:
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50 // Usage: #include <cyg/hal/plf_io.h>
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51 //
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52 //####DESCRIPTIONEND####
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53 //
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54 //=============================================================================
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55
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56 #include <cyg/hal/hal_io.h> // IO macros
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57 #include <cyg/hal/sd0001.h> // SD0001 registers
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58 #include <cyg/hal/hal_intr.h> // interrupt
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59
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60 extern cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus, cyg_uint32 devfn,
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61 cyg_uint32 offset);
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62 extern cyg_uint16 cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus, cyg_uint32 devfn,
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63 cyg_uint32 offset);
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64 extern cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus, cyg_uint32 devfn,
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65 cyg_uint32 offset);
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66 extern void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus, cyg_uint32 devfn,
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67 cyg_uint32 offset, cyg_uint32 val);
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68 extern void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus, cyg_uint32 devfn,
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69 cyg_uint32 offset, cyg_uint16 val);
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70 extern void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus, cyg_uint32 devfn,
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71 cyg_uint32 offset, cyg_uint8 val);
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72
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73
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74 // Initialize the PCI bus.
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75 externC void cyg_hal_plf_pci_init(void);
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76 #define HAL_PCI_INIT() cyg_hal_plf_pci_init()
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77
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78 // Map PCI device resources starting from these addresses in PCI space.
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79 #define HAL_PCI_ALLOC_BASE_IO 0x00000000
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80 #define HAL_PCI_ALLOC_BASE_MEMORY 0x00000000
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81
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82 // This is where the PCI spaces are mapped in the CPU's address space.
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83 #define HAL_PCI_PHYSICAL_IO_BASE 0xb0800000
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84 #define HAL_PCI_PHYSICAL_MEMORY_BASE 0xb1000000
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85
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86 // Read a value from the PCI configuration space of the appropriate
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87 // size at an address composed from the bus, devfn and offset.
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88 #define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
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89 __val = cyg_hal_plf_pci_cfg_read_byte((__bus), (__devfn), (__offset))
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90
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91 #define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
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92 __val = cyg_hal_plf_pci_cfg_read_word((__bus), (__devfn), (__offset))
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93
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94 #define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
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95 __val = cyg_hal_plf_pci_cfg_read_dword((__bus), (__devfn), (__offset))
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96
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97 // Write a value to the PCI configuration space of the appropriate
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98 // size at an address composed from the bus, devfn and offset.
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99 #define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
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100 cyg_hal_plf_pci_cfg_write_byte((__bus), (__devfn), (__offset), (__val))
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101
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102 #define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
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103 cyg_hal_plf_pci_cfg_write_word((__bus), (__devfn), (__offset), (__val))
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104
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105 #define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
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106 cyg_hal_plf_pci_cfg_write_dword((__bus), (__devfn), (__offset), (__val))
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107
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108 // Read/write data to PCI IO space
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109 #if 0
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110
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111 extern void cyg_hal_plf_pci_io_write_byte (cyg_uint32 addr, cyg_uint8 data);
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112 extern void cyg_hal_plf_pci_io_write_word (cyg_uint32 addr, cyg_uint16 data);
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113 extern void cyg_hal_plf_pci_io_write_dword (cyg_uint32 addr, cyg_uint32 data);
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114 extern cyg_uint8 cyg_hal_plf_pci_io_read_byte (cyg_uint32 addr);
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115 extern cyg_uint16 cyg_hal_plf_pci_io_read_word (cyg_uint32 addr);
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116 extern cyg_uint32 cyg_hal_plf_pci_io_read_dword (cyg_uint32 addr);
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117
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118 #define HAL_PCI_IO_READ_UINT8(addr, datum) datum = cyg_hal_plf_pci_io_read_byte((cyg_uint32)addr)
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119 #define HAL_PCI_IO_READ_UINT16(addr, datum) datum = cyg_hal_plf_pci_io_read_word((cyg_uint32)addr)
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120 #define HAL_PCI_IO_READ_UINT32(addr, datum) datum = cyg_hal_plf_pci_io_read_dword((cyg_uint32)addr)
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121 #define HAL_PCI_IO_WRITE_UINT8(addr, datum) cyg_hal_plf_pci_io_write_byte((cyg_uint32)addr, datum)
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122 #define HAL_PCI_IO_WRITE_UINT16(addr, datum) cyg_hal_plf_pci_io_write_word((cyg_uint32)addr, datum)
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123 #define HAL_PCI_IO_WRITE_UINT32(addr, datum) cyg_hal_plf_pci_io_write_dword((cyg_uint32)addr, datum)
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124 #endif
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125
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126 // Translate the PCI interrupt requested by the device (INTA#, INTB#,
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127 // INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
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128 #define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
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129 CYG_MACRO_START \
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130 cyg_uint8 __req; \
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131 HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
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132 if (0 != __req) { \
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133 CYG_ADDRWORD __translation[4] = { \
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134 CYGNUM_HAL_INTERRUPT_PCIC, \
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135 CYGNUM_HAL_INTERRUPT_PCIB, \
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136 CYGNUM_HAL_INTERRUPT_PCIA, \
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137 CYGNUM_HAL_INTERRUPT_PCID}; \
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138 \
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139 __vec = __translation[((__req+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \
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140 __valid = true; \
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141 } else { \
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142 /* Device will not generate interrupt requests. */ \
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143 __valid = false; \
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144 } \
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145 CYG_MACRO_END
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146
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147
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148 // Can only do local bus (I think, my Japanese isn't good enough to be sure :)
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149 // Ignore all but the first function on the SD0001
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150 #define HAL_PCI_IGNORE_DEVICE(__bus, __dev, __fn) \
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151 ((0 != __bus) \
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152 || ((0 == __dev) && (0 != __fn)))
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153
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154 // Bus address translation macros
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155 #define HAL_PCI_CPU_TO_BUS(__cpu_addr, __bus_addr) \
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156 CYG_MACRO_START \
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157 (__bus_addr) = CYGARC_BUS_ADDRESS(__cpu_addr); \
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158 CYG_MACRO_END
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159
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160 #define HAL_PCI_BUS_TO_CPU(__bus_addr, __cpu_addr) \
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161 CYG_MACRO_START \
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162 (__cpu_addr) = CYGARC_UNCACHED_ADDRESS(__bus_addr); \
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163 CYG_MACRO_END
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164
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165
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166 //-----------------------------------------------------------------------------
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167 // end of plf_io.h
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168 #endif // CYGONCE_PLF_IO_H