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annotate packages/hal/sh/se7751/current/cdl/hal_sh_sh7751_se7751.cdl @ 2729:74dbf4c3f2e1 after-copyright-change-20090129

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Update all copyright banners to reflect FSF ownership; fix and improve licence text.
author jlarmour
date Thu, 29 Jan 2009 17:47:46 +0000
parents d2c90368aeef
children b3aec2531be4
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1 # ====================================================================
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2 #
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3 # hal_sh_sh7751_se7751.cdl
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4 #
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5 # Hitachi SE7751 board HAL package configuration data
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6 #
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7 # ====================================================================
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8 ## ####ECOSGPLCOPYRIGHTBEGIN####
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9 ## -------------------------------------------
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10 ## This file is part of eCos, the Embedded Configurable Operating System.
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11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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12 ##
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13 ## eCos is free software; you can redistribute it and/or modify it under
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14 ## the terms of the GNU General Public License as published by the Free
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15 ## Software Foundation; either version 2 or (at your option) any later
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16 ## version.
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17 ##
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18 ## eCos is distributed in the hope that it will be useful, but WITHOUT
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19 ## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 ## for more details.
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22 ##
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23 ## You should have received a copy of the GNU General Public License
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24 ## along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 ## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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26 ##
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27 ## As a special exception, if other files instantiate templates or use
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28 ## macros or inline functions from this file, or you compile this file
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29 ## and link it with other works to produce a work based on this file,
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30 ## this file does not by itself cause the resulting work to be covered by
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31 ## the GNU General Public License. However the source code for this file
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32 ## must still be made available in accordance with section (3) of the GNU
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33 ## General Public License v2.
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34 ##
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35 ## This exception does not invalidate any other reasons why a work based
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36 ## on this file might be covered by the GNU General Public License.
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37 ## -------------------------------------------
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38 ## ####ECOSGPLCOPYRIGHTEND####
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39 # ====================================================================
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40 ######DESCRIPTIONBEGIN####
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41 #
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42 # Author(s): jskov
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43 # Original data: jskov
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44 # Contributors:
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45 # Date: 2001-07-09
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46 #
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47 #####DESCRIPTIONEND####
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48 #
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49 # ====================================================================
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50
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51 cdl_package CYGPKG_HAL_SH_SH7751_SE7751 {
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52 display "Hitachi/SH7751 SE7751 board"
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53 parent CYGPKG_HAL_SH
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54 requires CYGPKG_HAL_SH_7751
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55 requires ! CYGHWR_HAL_SH_BIGENDIAN
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56 requires CYGHWR_HAL_SH_IRQ_USE_IRQLVL
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57 define_header hal_sh_sh7751_se7751.h
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58 include_dir cyg/hal
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59 description "
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60 The SE7751 HAL package provides the support needed to run
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61 eCos on a Hitachi/SH SE7751 board."
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62
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63 compile hal_diag.c plf_misc.c ser16c550c.c m1543c.c
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64
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65 implements CYGINT_HAL_DEBUG_GDB_STUBS
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66 implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
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67 implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
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68 implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
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69
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70 define_proc {
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71 puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sh.h>"
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72 puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sh_sh7751_se7751.h>"
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73
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74 puts $::cdl_header "#define CYGNUM_HAL_SH_SH4_SCIF_PORTS 1"
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75 puts $::cdl_header "#define CYGHWR_HAL_VSR_TABLE 0x8c000000"
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76 puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0x8c000100"
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77
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78 puts $::cdl_header "#define HAL_PLATFORM_CPU \"SH 7751\""
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79 puts $::cdl_header "#define HAL_PLATFORM_BOARD \"SE7751\""
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80 puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
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81 }
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82
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83 cdl_component CYG_HAL_STARTUP {
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84 display "Startup type"
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85 flavor data
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86 legal_values {"RAM" "ROM" "ROMRAM" }
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87 default_value {"RAM"}
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88 no_define
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89 define -file system.h CYG_HAL_STARTUP
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90 description "
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91 When targetting the SE7751 board it is possible to build
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92 the system for either RAM bootstrap or ROM bootstrap.
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93 RAM bootstrap generally requires that the board
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94 is equipped with ROMs containing a suitable ROM monitor or
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95 equivalent software that allows GDB to download the eCos
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96 application on to the board. The ROM bootstrap typically
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97 requires that the eCos application be blown into EPROMs or
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98 equivalent technology. ROMRAM bootstrap is similar to ROM
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99 bootstrap, but everything is copied to RAM before execution
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100 starts thus improving performance, but at the cost of an
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101 increased RAM footprint."
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102 }
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103
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104 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
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105 display "Number of communication channels on the board"
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106 flavor data
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107 calculated 2
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108 }
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109
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110 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
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111 display "Debug serial port"
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112 flavor data
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113 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
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114 default_value 0
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115 description "
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116 The SE7751 board has one serial port. This option
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117 chooses which port will be used to connect to a host
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118 running GDB."
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119 }
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120
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121 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
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122 display "Default console channel."
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123 flavor data
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124 calculated 0
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125 }
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126
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127 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
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128 display "Diagnostic serial port"
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129 flavor data
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130 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
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131 default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
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132 description "
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133 The SE7751 board has two serial ports. This option
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134 chooses which port will be used for diagnostic output."
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135 }
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136
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137 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD {
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138 display "Console/GDB serial port baud rate"
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139 flavor data
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140 legal_values 9600 19200 38400 57600 115200
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141 default_value 38400
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142 define CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
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143 description "
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144 This option controls the default baud rate used for the
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145 Console/GDB connection."
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146 }
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147
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148 cdl_component CYGHWR_HAL_SH_PLF_CLOCK_SETTINGS {
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149 display "SH on-chip platform clock controls"
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150 description "
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151 The various clocks used by the system are derived from
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152 these options."
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153 flavor none
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154 no_define
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155
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156 cdl_option CYGHWR_HAL_SH_OOC_XTAL {
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157 display "SH clock crystal"
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158 flavor data
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159 legal_values 8000000 to 50000000
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160 default_value 27000000
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161 no_define
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162 description "
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163 This option specifies the frequency of the crystal all
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164 other clocks are derived from."
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165 }
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166
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167 cdl_option CYGHWR_HAL_SH_OOC_CKIO {
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168 display "SH clock CKIO output enable"
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169 default_value 1
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170 description "
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171 This selects whether CKIO output is enabled."
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172 }
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173
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174 cdl_option CYGHWR_HAL_SH_OOC_PLL_1 {
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175 display "SH clock PLL circuit 1"
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176 flavor data
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177 default_value 6
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178 legal_values { 0 6 }
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179 description "
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180 This selects the multiplication factor provided by
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181 PLL1."
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182 }
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183
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184 cdl_option CYGHWR_HAL_SH_OOC_PLL_2 {
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185 display "SH clock PLL circuit 2"
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186 flavor data
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187 default_value 1
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188 legal_values { 0 1 }
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189 description "
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190 This selects the multiplication factor provided by
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191 PLL2. If PLL2 is disabled this option should
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192 be set to zero."
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193 }
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194
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195 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_1 {
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196 display "SH clock divider 1"
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197 flavor data
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198 default_value 1
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199 legal_values { 1 2 }
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200 description "
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201 This divider option affects all clocks."
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202 }
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203
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204 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_IFC {
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205 display "SH CPU clock divider"
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206 flavor data
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207 default_value 1
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208 legal_values { 1 2 3 4 6 8 }
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209 description "
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210 This divider option affects the CPU clock."
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211 }
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212
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213 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_BFC {
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214 display "SH bus clock divider"
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215 flavor data
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216 default_value 3
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217 legal_values { 1 2 3 4 6 8 }
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218 description "
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219 This divider option affects the bus clock."
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220 }
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221
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222 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_PFC {
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223 display "SH peripheral clock divider"
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224 flavor data
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225 default_value 6
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226 legal_values { 1 2 3 4 6 8 }
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227 description "
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228 This divider option affects the peripheral clock."
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229 }
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230
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231 cdl_option CYGHWR_HAL_SH_OOC_CLOCK_MODE {
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232 display "SH clock mode"
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233 flavor data
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234 default_value 3
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235 legal_values { 0 1 2 3 4 5 }
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236 description "
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237 This option must mirror the clock mode hardwired on
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238 the MD0-MD2 pins of the CPU in order to correctly
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239 initialize the FRQCR register."
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240 }
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241 }
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242
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243 cdl_component CYGBLD_GLOBAL_OPTIONS {
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244 display "Global build options"
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245 flavor none
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246 parent CYGPKG_NONE
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247 no_define
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248 description "
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249 Global build options including control over
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250 compiler flags, linker flags and choice of toolchain."
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251
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252
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253 cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
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254 display "Global command prefix"
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255 flavor data
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256 no_define
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257 default_value { "sh-elf" }
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258 description "
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259 This option specifies the command prefix used when
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260 invoking the build tools."
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261 }
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262
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263 cdl_option CYGBLD_GLOBAL_CFLAGS {
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264 display "Global compiler flags"
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265 flavor data
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266 no_define
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267 default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" : "-ml -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
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268 description "
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269 This option controls the global compiler flags which
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270 are used to compile all packages by
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271 default. Individual packages may define
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272 options which override these global flags."
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273 }
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274
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275 cdl_option CYGBLD_GLOBAL_LDFLAGS {
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276 display "Global linker flags"
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277 flavor data
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278 no_define
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279 default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" : "-ml -m3 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" }
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280 description "
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281 This option controls the global linker flags. Individual
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282 packages may define options which override these global flags."
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283 }
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284
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285 cdl_option CYGBLD_BUILD_GDB_STUBS {
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286 display "Build GDB stub ROM image"
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287 default_value 0
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288 requires { CYG_HAL_STARTUP == "ROM" }
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289 requires CYGSEM_HAL_ROM_MONITOR
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290 requires CYGBLD_BUILD_COMMON_GDB_STUBS
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291 requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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292 requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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293 requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
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294 requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
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295 requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
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296 no_define
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297 description "
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298 This option enables the building of the GDB stubs for the
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299 board. The common HAL controls takes care of most of the
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300 build process, but the final conversion from ELF image to
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301 binary data is handled by the platform CDL, allowing
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302 relocation of the data if necessary."
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303
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304 make -priority 320 {
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305 <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
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306 $(OBJCOPY) -O binary $< $@
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307 }
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308 }
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309 }
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310
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311 cdl_component CYGHWR_MEMORY_LAYOUT {
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312 display "Memory layout"
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313 flavor data
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314 no_define
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315 calculated { CYG_HAL_STARTUP == "RAM" ? "sh_sh7751_se7751_ram" : \
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316 CYG_HAL_STARTUP == "ROM" ? "sh_sh7751_se7751_rom" : \
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317 "sh_sh7751_se7751_romram" }
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318
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319 cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
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320 display "Memory layout linker script fragment"
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321 flavor data
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322 no_define
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323 define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
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324 calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh7751_se7751_ram.ldi>" : \
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325 CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_sh_sh7751_se7751_rom.ldi>" : \
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326 "<pkgconf/mlt_sh_sh7751_se7751_romram.ldi>" }
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327 }
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328
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329 cdl_option CYGHWR_MEMORY_LAYOUT_H {
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330 display "Memory layout header file"
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331 flavor data
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332 no_define
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333 define -file system.h CYGHWR_MEMORY_LAYOUT_H
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334 calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh7751_se7751_ram.h>" : \
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335 CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_sh_sh7751_se7751_rom.h>" : \
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336 "<pkgconf/mlt_sh_sh7751_se7751_romram.h>" }
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337 }
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338 }
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339
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340 cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
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341 display "Work with a ROM monitor"
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342 flavor booldata
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343 legal_values { "GDB_stubs" }
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344 default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
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345 requires { CYG_HAL_STARTUP == "RAM" }
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346 parent CYGPKG_HAL_ROM_MONITOR
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347 description "
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348 Support can be enabled for boot ROMs or ROM monitors which contain
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349 GDB stubs. This support changes various eCos semantics such as
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350 the encoding of diagnostic output, and the overriding of hardware
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351 interrupt vectors."
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352 }
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353
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354 cdl_option CYGSEM_HAL_ROM_MONITOR {
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355 display "Behave as a ROM monitor"
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356 flavor bool
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357 default_value 0
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358 parent CYGPKG_HAL_ROM_MONITOR
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359 requires { CYG_HAL_STARTUP == "ROM" }
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360 description "
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361 Enable this option if this program is to be used as a ROM monitor,
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362 i.e. applications will be loaded into RAM on the board, and this
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363 ROM monitor may process exceptions or interrupts generated from the
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364 application. This enables features such as utilizing a separate
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365 interrupt stack when exceptions are generated."
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366 }
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367
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368 cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
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369 display "Redboot HAL options"
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370 flavor none
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371 no_define
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372 parent CYGPKG_REDBOOT
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373 active_if CYGPKG_REDBOOT
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374 description "
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375 This option lists the target's requirements for a valid Redboot
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376 configuration."
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377
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378 cdl_option CYGBLD_BUILD_REDBOOT_BIN {
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379 display "Build Redboot ROM binary image"
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380 active_if CYGBLD_BUILD_REDBOOT
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381 default_value 1
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382 no_define
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383 description "This option enables the conversion of the Redboot ELF
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384 image to a binary image suitable for ROM programming."
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385
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386 make -priority 325 {
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387 <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
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388 $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
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389 $(OBJCOPY) -O srec $< $(@:.bin=.srec)
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390 $(OBJCOPY) --change-address 0x21000000 -O srec $< $(@:.bin=.eprom.srec)
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391 $(OBJCOPY) -O binary $< $@
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392 }
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393 }
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394 }
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395 }