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annotate packages/hal/sh/se77x9/current/cdl/hal_sh_sh77x9_se77x9.cdl @ 2729:74dbf4c3f2e1 after-copyright-change-20090129

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Update all copyright banners to reflect FSF ownership; fix and improve licence text.
author jlarmour
date Thu, 29 Jan 2009 17:47:46 +0000
parents d2c90368aeef
children b3aec2531be4
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1 # ====================================================================
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2 #
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3 # hal_sh_sh77x9_se77x9.cdl
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4 #
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5 # Hitachi SE77X9 board HAL package configuration data
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6 #
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7 # ====================================================================
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8 ## ####ECOSGPLCOPYRIGHTBEGIN####
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9 ## -------------------------------------------
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10 ## This file is part of eCos, the Embedded Configurable Operating System.
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11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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12 ##
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13 ## eCos is free software; you can redistribute it and/or modify it under
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14 ## the terms of the GNU General Public License as published by the Free
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15 ## Software Foundation; either version 2 or (at your option) any later
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16 ## version.
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17 ##
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18 ## eCos is distributed in the hope that it will be useful, but WITHOUT
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19 ## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 ## for more details.
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22 ##
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23 ## You should have received a copy of the GNU General Public License
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24 ## along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 ## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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26 ##
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27 ## As a special exception, if other files instantiate templates or use
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28 ## macros or inline functions from this file, or you compile this file
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29 ## and link it with other works to produce a work based on this file,
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30 ## this file does not by itself cause the resulting work to be covered by
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31 ## the GNU General Public License. However the source code for this file
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32 ## must still be made available in accordance with section (3) of the GNU
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33 ## General Public License v2.
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34 ##
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35 ## This exception does not invalidate any other reasons why a work based
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36 ## on this file might be covered by the GNU General Public License.
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37 ## -------------------------------------------
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38 ## ####ECOSGPLCOPYRIGHTEND####
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39 # ====================================================================
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40 ######DESCRIPTIONBEGIN####
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41 #
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42 # Author(s): jskov
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43 # Original data: jskov
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44 # Contributors:
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45 # Date: 2001-05-25
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46 #
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47 #####DESCRIPTIONEND####
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48 #
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49 # ====================================================================
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50
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51 cdl_package CYGPKG_HAL_SH_SH77X9_SE77X9 {
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52 display "Hitachi/SH77X9 SE77X9 board"
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53 parent CYGPKG_HAL_SH
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54 requires ! CYGHWR_HAL_SH_BIGENDIAN
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55 requires CYGHWR_HAL_SH_IRQ_USE_IRQLVL
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56 define_header hal_sh_sh77x9_se77x9.h
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57 include_dir cyg/hal
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58 description "
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59 The SE77X9 HAL package provides the support needed to run
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60 eCos on a Hitachi/SH SE77X9 board."
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61
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62 compile hal_diag.c plf_misc.c ser16c550c.c
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63
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64 implements CYGINT_HAL_DEBUG_GDB_STUBS
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65 implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
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66 implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
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67 implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
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68
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69 define_proc {
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70 puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sh.h>"
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71 puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sh_sh77x9_se77x9.h>"
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72
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73 puts $::cdl_header "#define CYGNUM_HAL_SH_SH3_SCIF_PORTS 1"
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74 puts $::cdl_header "#define CYGHWR_HAL_VSR_TABLE 0x8c000000"
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75 puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0x8c000100"
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76
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77 puts $::cdl_header "#define HAL_PLATFORM_BOARD \"SE77X9\""
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78 puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
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79 }
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80
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81 cdl_option CYGPRI_HAL_SH_SH77X9_VARIANT {
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82 display "Board variant"
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83 flavor data
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84 legal_values {"SE7709RP01" "SE7709SE01" "SE7729SE01"}
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85 default_value {"SE7709SE01"}
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86 no_define
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87 description "
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88 Select the particular board variant used."
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89 }
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90
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91 cdl_option CYGPRI_HAL_SH_SH77X9_SUPERIO {
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92 display "Board variant has SuperIO controller"
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93 default_value 0
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94 compile smsc37c93x.c
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95 description "
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96 Set if the board has a SuperIO controller."
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97 }
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98
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99
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100 cdl_option CYGPRI_HAL_SH_SH77X9_VARIANT_7709R {
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101 display "SE7709RP01 board"
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102 active_if { CYGPRI_HAL_SH_SH77X9_VARIANT == "SE7709RP01" }
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103 calculated 1
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104
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105 requires CYGPKG_HAL_SH_7709R
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106 requires !CYGPKG_HAL_SH_7709S
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107 requires !CYGPKG_HAL_SH_7729
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108 requires !CYGPRI_HAL_SH_SH77X9_SUPERIO
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109 requires { CYGNUM_HAL_SH_OOC_XTAL_DEFAULT == 20000000 }
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110 define_proc {
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111 puts $::cdl_header "#define HAL_PLATFORM_CPU \"SH 7709R\""
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112 puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_16550_CLOCK 14745000"
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113 puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_16550_BASE 0xb0800000"
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114 puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_LEDS_BASE 0xb1800000"
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115 }
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116
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117 description "Settings for the 7709R variant of the board."
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118 }
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119
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120 cdl_option CYGPRI_HAL_SH_SH77X9_VARIANT_7709S {
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121 display "SE7709SE01 board"
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122 active_if { CYGPRI_HAL_SH_SH77X9_VARIANT == "SE7709SE01" }
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123 calculated 1
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124 requires CYGPRI_HAL_SH_SH77X9_SUPERIO
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125 requires !CYGPKG_HAL_SH_7709R
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126 requires CYGPKG_HAL_SH_7709S
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127 requires !CYGPKG_HAL_SH_7729
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128 define_proc {
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129 puts $::cdl_header "#define HAL_PLATFORM_CPU \"SH 7709S\""
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130 puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_16550_CLOCK 1846200"
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131 puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_16550_BASE 0xb04007f0"
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132 puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_LEDS_BASE 0xb0c00000"
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133 puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_SDRAM_SETUP"
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134 }
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diff changeset
135
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136 description "Settings for the 7709S variant of the board."
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137 }
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diff changeset
138
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139 cdl_option CYGPRI_HAL_SH_SH77X9_VARIANT_7729 {
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140 display "SE7729SE01 board"
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141 active_if { CYGPRI_HAL_SH_SH77X9_VARIANT == "SE7729SE01" }
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142 calculated 1
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143 requires CYGPRI_HAL_SH_SH77X9_SUPERIO
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144 requires !CYGPKG_HAL_SH_7709R
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145 requires !CYGPKG_HAL_SH_7709S
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146 requires CYGPKG_HAL_SH_7729
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147 define_proc {
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148 puts $::cdl_header "#define HAL_PLATFORM_CPU \"SH 7729\""
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149 puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_16550_CLOCK 1846200"
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150 puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_16550_BASE 0xb04007f0"
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151 puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_LEDS_BASE 0xb0c00000"
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152 puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_SDRAM_SETUP"
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153 }
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diff changeset
154
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155 description "Settings for the 7729 variant of the board."
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156 }
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diff changeset
157
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158
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159 cdl_component CYG_HAL_STARTUP {
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160 display "Startup type"
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161 flavor data
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162 legal_values {"RAM" "ROM" "ROMRAM" }
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163 default_value {"RAM"}
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164 no_define
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165 define -file system.h CYG_HAL_STARTUP
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166 description "
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167 When targetting the SE77X9 board it is possible to build
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168 the system for either RAM bootstrap or ROM bootstrap.
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169 RAM bootstrap generally requires that the board
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170 is equipped with ROMs containing a suitable ROM monitor or
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171 equivalent software that allows GDB to download the eCos
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172 application on to the board. The ROM bootstrap typically
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173 requires that the eCos application be blown into EPROMs or
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174 equivalent technology. ROMRAM bootstrap is similar to ROM
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175 bootstrap, but everything is copied to RAM before execution
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176 starts thus improving performance, but at the cost of an
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177 increased RAM footprint."
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178 }
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179
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180 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
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181 display "Number of communication channels on the board"
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182 flavor data
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183 calculated 2
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184 }
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185
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186 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
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187 display "Debug serial port"
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188 flavor data
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189 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
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190 default_value 0
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191 description "
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192 The SE77X9 board has one serial port. This option
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193 chooses which port will be used to connect to a host
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194 running GDB."
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195 }
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196
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197 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
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198 display "Default console channel."
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199 flavor data
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200 calculated 0
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201 }
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202
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203 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
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204 display "Diagnostic serial port"
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205 flavor data
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206 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
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207 default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
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208 description "
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209 The SE77X9 board has two serial ports. This option
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210 chooses which port will be used for diagnostic output."
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211 }
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212
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213 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD {
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214 display "Console/GDB serial port baud rate"
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215 flavor data
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216 legal_values 9600 19200 38400 57600 115200
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217 default_value 38400
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218 define CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
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219 description "
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220 This option controls the default baud rate used for the
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221 Console/GDB connection."
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222 }
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223
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224 cdl_component CYGHWR_HAL_SH_PLF_CLOCK_SETTINGS {
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225 display "SH on-chip platform clock controls"
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226 description "
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227 The various clocks used by the system are derived from
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228 these options."
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229 flavor none
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230 no_define
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231
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232 cdl_option CYGNUM_HAL_SH_OOC_XTAL_DEFAULT {
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233 display "SH clock crystal default value"
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234 flavor data
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235 default_value 33333300
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236 no_define
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237 }
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238
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239 cdl_option CYGHWR_HAL_SH_OOC_XTAL {
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240 display "SH clock crystal"
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241 flavor data
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242 legal_values 8000000 to 50000000
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243 default_value { CYGNUM_HAL_SH_OOC_XTAL_DEFAULT }
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244 no_define
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245 description "
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246 This option specifies the frequency of the crystal all
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247 other clocks are derived from."
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248 }
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249
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250 cdl_option CYGHWR_HAL_SH_OOC_PLL_1 {
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251 display "SH clock PLL circuit 1"
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252 flavor data
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253 default_value 4
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254 legal_values { 0 1 2 3 4 6 8 }
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255 description "
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256 This selects the multiplication factor provided by
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257 PLL1. If PLL1 is disabled via CAP1, this option should
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258 be set to zero."
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259 }
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260
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261 cdl_option CYGHWR_HAL_SH_OOC_PLL_2 {
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262 display "SH clock PLL circuit 2"
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263 flavor data
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264 default_value 1
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265 legal_values { 0 1 4 }
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266 no_define
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267 description "
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268 This selects the multiplication factor provided by
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269 PLL2. If PLL2 is disabled via CAP2, this option should
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270 be set to zero."
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271 }
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272
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273 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_1 {
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274 display "SH clock divider 1"
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diff changeset
275 flavor data
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276 default_value 1
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277 legal_values { 1 2 3 4 6 }
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278 description "
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279 This divider option affects the CPU core clock."
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280 }
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281
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282 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_2 {
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283 display "SH clock divider 2"
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diff changeset
284 flavor data
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285 default_value 4
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286 legal_values { 1 2 3 4 6 }
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287 description "
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288 This divider option affects the peripheral clock."
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289 }
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290
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291 cdl_option CYGHWR_HAL_SH_OOC_CLOCK_MODE {
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292 display "SH clock mode"
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293 flavor data
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294 default_value 0
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295 legal_values { 0 1 2 3 4 7 }
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296 description "
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297 This option must mirror the clock mode hardwired on
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298 the MD0-MD2 pins of the CPU in order to correctly
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299 initialize the FRQCR register."
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300 }
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301 }
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302
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303 cdl_component CYGBLD_GLOBAL_OPTIONS {
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304 display "Global build options"
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305 flavor none
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306 parent CYGPKG_NONE
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307 no_define
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308 description "
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diff changeset
309 Global build options including control over
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diff changeset
310 compiler flags, linker flags and choice of toolchain."
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diff changeset
311
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312
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313 cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
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314 display "Global command prefix"
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315 flavor data
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316 no_define
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317 default_value { "sh-elf" }
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318 description "
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319 This option specifies the command prefix used when
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320 invoking the build tools."
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321 }
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diff changeset
322
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323 cdl_option CYGBLD_GLOBAL_CFLAGS {
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324 display "Global compiler flags"
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325 flavor data
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326 no_define
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327 default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" : "-ml -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
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328 description "
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329 This option controls the global compiler flags which
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diff changeset
330 are used to compile all packages by
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331 default. Individual packages may define
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diff changeset
332 options which override these global flags."
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333 }
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diff changeset
334
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diff changeset
335 cdl_option CYGBLD_GLOBAL_LDFLAGS {
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336 display "Global linker flags"
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diff changeset
337 flavor data
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338 no_define
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339 default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" : "-ml -m3 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" }
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340 description "
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341 This option controls the global linker flags. Individual
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diff changeset
342 packages may define options which override these global flags."
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343 }
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diff changeset
344
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345 cdl_option CYGBLD_BUILD_GDB_STUBS {
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346 display "Build GDB stub ROM image"
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347 default_value 0
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348 requires { CYG_HAL_STARTUP == "ROM" }
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349 requires CYGSEM_HAL_ROM_MONITOR
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350 requires CYGBLD_BUILD_COMMON_GDB_STUBS
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351 requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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352 requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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353 requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
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354 requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
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355 requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
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356 no_define
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357 description "
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358 This option enables the building of the GDB stubs for the
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diff changeset
359 board. The common HAL controls takes care of most of the
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diff changeset
360 build process, but the final conversion from ELF image to
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diff changeset
361 binary data is handled by the platform CDL, allowing
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diff changeset
362 relocation of the data if necessary."
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diff changeset
363
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364 make -priority 320 {
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365 <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
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366 $(OBJCOPY) -O binary $< $@
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367 }
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diff changeset
368 }
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diff changeset
369 }
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diff changeset
370
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371 cdl_component CYGHWR_MEMORY_LAYOUT {
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372 display "Memory layout"
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373 flavor data
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374 no_define
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375 calculated { CYG_HAL_STARTUP == "RAM" ? "sh_sh77x9_se77x9_ram" : \
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376 CYG_HAL_STARTUP == "ROM" ? "sh_sh77x9_se77x9_rom" : \
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377 "sh_sh77x9_se77x9_romram" }
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378
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379 cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
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380 display "Memory layout linker script fragment"
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381 flavor data
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382 no_define
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383 define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
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384 calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh77x9_se77x9_ram.ldi>" : \
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385 CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_sh_sh77x9_se77x9_rom.ldi>" : \
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386 "<pkgconf/mlt_sh_sh77x9_se77x9_romram.ldi>" }
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387 }
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diff changeset
388
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389 cdl_option CYGHWR_MEMORY_LAYOUT_H {
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390 display "Memory layout header file"
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diff changeset
391 flavor data
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392 no_define
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393 define -file system.h CYGHWR_MEMORY_LAYOUT_H
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394 calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh77x9_se77x9_ram.h>" : \
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395 CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_sh_sh77x9_se77x9_rom.h>" : \
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396 "<pkgconf/mlt_sh_sh77x9_se77x9_romram.h>" }
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diff changeset
397 }
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diff changeset
398 }
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diff changeset
399
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diff changeset
400 cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
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diff changeset
401 display "Work with a ROM monitor"
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diff changeset
402 flavor booldata
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diff changeset
403 legal_values { "GDB_stubs" }
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404 default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
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405 requires { CYG_HAL_STARTUP == "RAM" }
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diff changeset
406 parent CYGPKG_HAL_ROM_MONITOR
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diff changeset
407 description "
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408 Support can be enabled for boot ROMs or ROM monitors which contain
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diff changeset
409 GDB stubs. This support changes various eCos semantics such as
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diff changeset
410 the encoding of diagnostic output, and the overriding of hardware
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diff changeset
411 interrupt vectors."
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412 }
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413
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414 cdl_option CYGSEM_HAL_ROM_MONITOR {
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415 display "Behave as a ROM monitor"
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416 flavor bool
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417 default_value 0
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418 parent CYGPKG_HAL_ROM_MONITOR
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419 requires { CYG_HAL_STARTUP == "ROM" }
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420 description "
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421 Enable this option if this program is to be used as a ROM monitor,
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422 i.e. applications will be loaded into RAM on the board, and this
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423 ROM monitor may process exceptions or interrupts generated from the
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424 application. This enables features such as utilizing a separate
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425 interrupt stack when exceptions are generated."
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426 }
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427
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428 cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
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429 display "Redboot HAL options"
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430 flavor none
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431 no_define
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432 parent CYGPKG_REDBOOT
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433 active_if CYGPKG_REDBOOT
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434 description "
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435 This option lists the target's requirements for a valid Redboot
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436 configuration."
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437
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438 cdl_option CYGBLD_BUILD_REDBOOT_BIN {
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439 display "Build Redboot ROM binary image"
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440 active_if CYGBLD_BUILD_REDBOOT
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441 default_value 1
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442 no_define
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443 description "This option enables the conversion of the Redboot ELF
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444 image to a binary image suitable for ROM programming."
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445
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446 make -priority 325 {
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447 <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
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448 $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
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449 $(OBJCOPY) -O srec $< $(@:.bin=.srec)
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450 $(OBJCOPY) --change-address 0x21000000 -O srec $< $(@:.bin=.eprom.srec)
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451 $(OBJCOPY) -O binary $< $@
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452 }
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453 }
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454 }
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455 }