Mercurial > ecos-v3_0-branch
annotate packages/hal/sparclite/sleb/current/include/hal_cpu.h @ 2729:74dbf4c3f2e1 after-copyright-change-20090129
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
| author | jlarmour |
|---|---|
| date | Thu, 29 Jan 2009 17:47:46 +0000 |
| parents | d2c90368aeef |
| children |
| rev | line source |
|---|---|
| 2 | 1 #ifndef CYGONCE_HAL_SPARCLITE_HAL_CPU_H |
| 2 #define CYGONCE_HAL_SPARCLITE_HAL_CPU_H | |
| 3 // ==================================================================== | |
| 4 // | |
| 5 // hal_cpu.h | |
| 6 // | |
| 7 // HAL CPU architecture file for MB8683x | |
| 8 // | |
| 9 // ==================================================================== | |
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10 // ####ECOSGPLCOPYRIGHTBEGIN#### |
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11 // ------------------------------------------- |
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12 // This file is part of eCos, the Embedded Configurable Operating System. |
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13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
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14 // |
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15 // eCos is free software; you can redistribute it and/or modify it under |
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16 // the terms of the GNU General Public License as published by the Free |
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17 // Software Foundation; either version 2 or (at your option) any later |
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18 // version. |
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19 // |
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT |
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21 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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23 // for more details. |
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24 // |
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25 // You should have received a copy of the GNU General Public License |
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26 // along with eCos; if not, write to the Free Software Foundation, Inc., |
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27 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
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28 // |
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29 // As a special exception, if other files instantiate templates or use |
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30 // macros or inline functions from this file, or you compile this file |
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31 // and link it with other works to produce a work based on this file, |
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32 // this file does not by itself cause the resulting work to be covered by |
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33 // the GNU General Public License. However the source code for this file |
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34 // must still be made available in accordance with section (3) of the GNU |
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35 // General Public License v2. |
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36 // |
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37 // This exception does not invalidate any other reasons why a work based |
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38 // on this file might be covered by the GNU General Public License. |
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39 // ------------------------------------------- |
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40 // ####ECOSGPLCOPYRIGHTEND#### |
| 2 | 41 // ==================================================================== |
| 42 //#####DESCRIPTIONBEGIN#### | |
| 43 // | |
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44 // Author(s): Red Hat |
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45 // Contributors: Red Hat, hmt |
| 2 | 46 // Date: 1999-03-01 |
| 47 // Purpose: MB8683x SPARClite CPU symbols | |
| 48 // Description: | |
| 49 // | |
| 50 //####DESCRIPTIONEND#### | |
| 51 // | |
| 52 // ==================================================================== | |
| 53 | |
| 54 | |
| 55 // NOTE: THIS FILE HAS NOT BEEN "CLEANED UP" WRT NAMESPACE USE | |
| 56 // | |
| 57 // it is only used internally to the SLEB HAL | |
| 58 // | |
| 59 // it should not be exported by inclusion in API header files | |
| 60 // | |
| 61 | |
| 62 #ifndef __ASSEMBLER__ | |
| 63 /* | |
| 64 * Register numbers. These are assumed to match the | |
| 65 * register numbers used by GDB. | |
| 66 */ | |
| 67 enum __regnames { | |
| 68 REG_G0, REG_G1, REG_G2, REG_G3, | |
| 69 REG_G4, REG_G5, REG_G6, REG_G7, | |
| 70 REG_O0, REG_O1, REG_O2, REG_O3, | |
| 71 REG_O4, REG_O5, REG_SP, REG_O7, | |
| 72 REG_L0, REG_L1, REG_L2, REG_L3, | |
| 73 REG_L4, REG_L5, REG_L6, REG_L7, | |
| 74 REG_I0, REG_I1, REG_I2, REG_I3, | |
| 75 REG_I4, REG_I5, REG_FP, REG_I7, | |
| 76 | |
| 77 REG_F0, REG_F1, REG_F2, REG_F3, | |
| 78 REG_F4, REG_F5, REG_F6, REG_F7, | |
| 79 REG_F8, REG_F9, REG_F10, REG_F11, | |
| 80 REG_F12, REG_F13, REG_F14, REG_F15, | |
| 81 REG_F16, REG_F17, REG_F18, REG_F19, | |
| 82 REG_F20, REG_F21, REG_F22, REG_F23, | |
| 83 REG_F24, REG_F25, REG_F26, REG_F27, | |
| 84 REG_F28, REG_F29, REG_F30, REG_F31, | |
| 85 | |
| 86 REG_Y, REG_PSR, REG_WIM, REG_TBR, | |
| 87 REG_PC, REG_NPC, REG_FPSR, REG_CPSR, | |
| 88 REG_DIA1, REG_DIA2, REG_DDA1, REG_DDA2, | |
| 89 REG_DDV1, REG_DDV2, REG_DCR, REG_DSR, | |
| 90 | |
| 91 REG_LAST | |
| 92 }; | |
| 93 #endif | |
| 94 | |
| 95 #ifdef __ASSEMBLER__ | |
| 96 /* | |
| 97 * Macros to glue together two tokens. | |
| 98 */ | |
| 99 #ifdef __STDC__ | |
| 100 #define XGLUE(a,b) a##b | |
| 101 #else | |
| 102 #define XGLUE(a,b) a/**/b | |
| 103 #endif | |
| 104 | |
| 105 #define GLUE(a,b) XGLUE(a,b) | |
| 106 | |
| 107 #ifdef NEED_UNDERSCORE | |
| 108 #define SYM_NAME(name) GLUE(_,name) | |
| 109 | |
| 110 .macro FUNC_START name | |
| 111 .align 4 | |
| 112 .globl _\name | |
| 113 .type _\name,#function | |
| 114 .proc 04 | |
| 115 _\name: | |
| 116 .endm | |
| 117 | |
| 118 .macro FUNC_END name | |
| 119 .LL_\name: | |
| 120 .size _\name,.LL_\name - _\name | |
| 121 .endm | |
| 122 | |
| 123 #else | |
| 124 #define SYM_NAME(name) name | |
| 125 | |
| 126 .macro FUNC_START name | |
| 127 .align 4 | |
| 128 .globl \name | |
| 129 .type \name,#function | |
| 130 .proc 04 | |
| 131 \name: | |
| 132 .endm | |
| 133 | |
| 134 .macro FUNC_END name | |
| 135 .LL\name: | |
| 136 .size \name,.LL\name - \name | |
| 137 .endm | |
| 138 | |
| 139 #endif | |
| 140 | |
| 141 #endif /* __ASSEMBLER__ */ | |
| 142 | |
| 143 /* | |
| 144 * breakpoint opcode. | |
| 145 */ | |
| 146 #define BREAKPOINT_OPCODE 0x91d02001 | |
| 147 | |
| 148 /* | |
| 149 * inline asm statement to cause breakpoint. | |
| 150 */ | |
| 151 #define BREAKPOINT() asm volatile ("ta 1\n") | |
| 152 | |
| 153 /* | |
| 154 * Core Exception vectors. | |
| 155 */ | |
| 156 #define BSP_EXC_IACCESS 0 | |
| 157 #define BSP_EXC_ILL 1 | |
| 158 #define BSP_EXC_IPRIV 2 | |
| 159 #define BSP_EXC_FPDIS 3 | |
| 160 #define BSP_EXC_WINOVF 4 | |
| 161 #define BSP_EXC_WINUND 5 | |
| 162 #define BSP_EXC_ALIGN 6 | |
| 163 #define BSP_EXC_DACCESS 7 | |
| 164 #define BSP_EXC_TAGOVF 8 | |
| 165 #define BSP_EXC_INT1 9 | |
| 166 #define BSP_EXC_INT2 10 | |
| 167 #define BSP_EXC_INT3 11 | |
| 168 #define BSP_EXC_INT4 12 | |
| 169 #define BSP_EXC_INT5 13 | |
| 170 #define BSP_EXC_INT6 14 | |
| 171 #define BSP_EXC_INT7 15 | |
| 172 #define BSP_EXC_INT8 16 | |
| 173 #define BSP_EXC_INT9 17 | |
| 174 #define BSP_EXC_INT10 18 | |
| 175 #define BSP_EXC_INT11 19 | |
| 176 #define BSP_EXC_INT12 20 | |
| 177 #define BSP_EXC_INT13 21 | |
| 178 #define BSP_EXC_INT14 22 | |
| 179 #define BSP_EXC_INT15 23 | |
| 180 #define BSP_EXC_CPDIS 24 | |
| 181 #define BSP_EXC_BREAK 25 | |
| 182 #define BSP_EXC_WINFLUSH 26 | |
| 183 #define BSP_EXC_SYSCALL 27 | |
| 184 #define BSP_EXC_DEBUG 28 | |
| 185 #define BSP_EXC_TRAP 29 | |
| 186 | |
| 187 #define BSP_MAX_EXCEPTIONS 30 | |
| 188 | |
| 189 #define BSP_VEC_MT_DEBUG 30 | |
| 190 #define BSP_VEC_STUB_ENTRY 31 | |
| 191 #define BSP_VEC_BSPDATA 32 | |
| 192 | |
| 193 #define NUM_VTAB_ENTRIES 33 | |
| 194 | |
| 195 #define CPU_WINSIZE 8 | |
| 196 | |
| 197 /* | |
| 198 * Exception frame offsets. | |
| 199 */ | |
| 200 #define GPR_SIZE 4 | |
| 201 #define FPR_SIZE 4 | |
| 202 #define PTR_BYTES 4 | |
| 203 | |
| 204 /* Leave room for locals + hidden arg + arg spill + dword align */ | |
| 205 #define FR_BIAS ((16+1+6+1)*GPR_SIZE) | |
| 206 | |
| 207 #define FR_G0 FR_BIAS | |
| 208 #define FR_G1 (FR_G0 + GPR_SIZE) | |
| 209 #define FR_G2 (FR_G1 + GPR_SIZE) | |
| 210 #define FR_G3 (FR_G2 + GPR_SIZE) | |
| 211 #define FR_G4 (FR_G3 + GPR_SIZE) | |
| 212 #define FR_G5 (FR_G4 + GPR_SIZE) | |
| 213 #define FR_G6 (FR_G5 + GPR_SIZE) | |
| 214 #define FR_G7 (FR_G6 + GPR_SIZE) | |
| 215 #define FR_O0 (FR_G7 + GPR_SIZE) | |
| 216 #define FR_O1 (FR_O0 + GPR_SIZE) | |
| 217 #define FR_O2 (FR_O1 + GPR_SIZE) | |
| 218 #define FR_O3 (FR_O2 + GPR_SIZE) | |
| 219 #define FR_O4 (FR_O3 + GPR_SIZE) | |
| 220 #define FR_O5 (FR_O4 + GPR_SIZE) | |
| 221 #define FR_O6 (FR_O5 + GPR_SIZE) | |
| 222 #define FR_SP FR_O6 | |
| 223 #define FR_O7 (FR_SP + GPR_SIZE) | |
| 224 #define FR_L0 (FR_O7 + GPR_SIZE) | |
| 225 #define FR_L1 (FR_L0 + GPR_SIZE) | |
| 226 #define FR_L2 (FR_L1 + GPR_SIZE) | |
| 227 #define FR_L3 (FR_L2 + GPR_SIZE) | |
| 228 #define FR_L4 (FR_L3 + GPR_SIZE) | |
| 229 #define FR_L5 (FR_L4 + GPR_SIZE) | |
| 230 #define FR_L6 (FR_L5 + GPR_SIZE) | |
| 231 #define FR_L7 (FR_L6 + GPR_SIZE) | |
| 232 #define FR_I0 (FR_L7 + GPR_SIZE) | |
| 233 #define FR_I1 (FR_I0 + GPR_SIZE) | |
| 234 #define FR_I2 (FR_I1 + GPR_SIZE) | |
| 235 #define FR_I3 (FR_I2 + GPR_SIZE) | |
| 236 #define FR_I4 (FR_I3 + GPR_SIZE) | |
| 237 #define FR_I5 (FR_I4 + GPR_SIZE) | |
| 238 #define FR_I6 (FR_I5 + GPR_SIZE) | |
| 239 #define FR_FP FR_I6 | |
| 240 #define FR_I7 (FR_FP + GPR_SIZE) | |
| 241 | |
| 242 #define FR_FREG0 (FR_I7 + GPR_SIZE) | |
| 243 #define FR_FREG1 (FR_FREG0 + FPR_SIZE) | |
| 244 #define FR_FREG2 (FR_FREG1 + FPR_SIZE) | |
| 245 #define FR_FREG3 (FR_FREG2 + FPR_SIZE) | |
| 246 #define FR_FREG4 (FR_FREG3 + FPR_SIZE) | |
| 247 #define FR_FREG5 (FR_FREG4 + FPR_SIZE) | |
| 248 #define FR_FREG6 (FR_FREG5 + FPR_SIZE) | |
| 249 #define FR_FREG7 (FR_FREG6 + FPR_SIZE) | |
| 250 #define FR_FREG8 (FR_FREG7 + FPR_SIZE) | |
| 251 #define FR_FREG9 (FR_FREG8 + FPR_SIZE) | |
| 252 #define FR_FREG10 (FR_FREG9 + FPR_SIZE) | |
| 253 #define FR_FREG11 (FR_FREG10 + FPR_SIZE) | |
| 254 #define FR_FREG12 (FR_FREG11 + FPR_SIZE) | |
| 255 #define FR_FREG13 (FR_FREG12 + FPR_SIZE) | |
| 256 #define FR_FREG14 (FR_FREG13 + FPR_SIZE) | |
| 257 #define FR_FREG15 (FR_FREG14 + FPR_SIZE) | |
| 258 #define FR_FREG16 (FR_FREG15 + FPR_SIZE) | |
| 259 #define FR_FREG17 (FR_FREG16 + FPR_SIZE) | |
| 260 #define FR_FREG18 (FR_FREG17 + FPR_SIZE) | |
| 261 #define FR_FREG19 (FR_FREG18 + FPR_SIZE) | |
| 262 #define FR_FREG20 (FR_FREG19 + FPR_SIZE) | |
| 263 #define FR_FREG21 (FR_FREG20 + FPR_SIZE) | |
| 264 #define FR_FREG22 (FR_FREG21 + FPR_SIZE) | |
| 265 #define FR_FREG23 (FR_FREG22 + FPR_SIZE) | |
| 266 #define FR_FREG24 (FR_FREG23 + FPR_SIZE) | |
| 267 #define FR_FREG25 (FR_FREG24 + FPR_SIZE) | |
| 268 #define FR_FREG26 (FR_FREG25 + FPR_SIZE) | |
| 269 #define FR_FREG27 (FR_FREG26 + FPR_SIZE) | |
| 270 #define FR_FREG28 (FR_FREG27 + FPR_SIZE) | |
| 271 #define FR_FREG29 (FR_FREG28 + FPR_SIZE) | |
| 272 #define FR_FREG30 (FR_FREG29 + FPR_SIZE) | |
| 273 #define FR_FREG31 (FR_FREG30 + FPR_SIZE) | |
| 274 | |
| 275 #define FR_Y (FR_FREG31 + FPR_SIZE) | |
| 276 #define FR_PSR (FR_Y + GPR_SIZE) | |
| 277 #define FR_WIM (FR_PSR + GPR_SIZE) | |
| 278 #define FR_TBR (FR_WIM + GPR_SIZE) | |
| 279 #define FR_PC (FR_TBR + GPR_SIZE) | |
| 280 #define FR_NPC (FR_PC + GPR_SIZE) | |
| 281 #define FR_FPSR (FR_NPC + GPR_SIZE) | |
| 282 #define FR_CPSR (FR_FPSR + GPR_SIZE) | |
| 283 #define FR_DIA1 (FR_CPSR + GPR_SIZE) | |
| 284 #define FR_DIA2 (FR_DIA1 + GPR_SIZE) | |
| 285 #define FR_DDA1 (FR_DIA2 + GPR_SIZE) | |
| 286 #define FR_DDA2 (FR_DDA1 + GPR_SIZE) | |
| 287 #define FR_DDV1 (FR_DDA2 + GPR_SIZE) | |
| 288 #define FR_DDV2 (FR_DDV1 + GPR_SIZE) | |
| 289 #define FR_DCR (FR_DDV2 + GPR_SIZE) | |
| 290 #define FR_DSR (FR_DCR + GPR_SIZE) | |
| 291 #define FR_ASR17 (FR_DSR + GPR_SIZE) | |
| 292 | |
| 293 #define EX_STACK_SIZE (FR_ASR17 + GPR_SIZE) | |
| 294 | |
| 295 #ifndef __ASSEMBLER__ | |
| 296 /* | |
| 297 * How registers are stored for exceptions. | |
| 298 */ | |
| 299 typedef struct | |
| 300 { | |
| 301 unsigned long _g0; | |
| 302 unsigned long _g1; | |
| 303 unsigned long _g2; | |
| 304 unsigned long _g3; | |
| 305 unsigned long _g4; | |
| 306 unsigned long _g5; | |
| 307 unsigned long _g6; | |
| 308 unsigned long _g7; | |
| 309 unsigned long _o0; | |
| 310 unsigned long _o1; | |
| 311 unsigned long _o2; | |
| 312 unsigned long _o3; | |
| 313 unsigned long _o4; | |
| 314 unsigned long _o5; | |
| 315 unsigned long _sp; | |
| 316 unsigned long _o7; | |
| 317 unsigned long _l0; | |
| 318 unsigned long _l1; | |
| 319 unsigned long _l2; | |
| 320 unsigned long _l3; | |
| 321 unsigned long _l4; | |
| 322 unsigned long _l5; | |
| 323 unsigned long _l6; | |
| 324 unsigned long _l7; | |
| 325 unsigned long _i0; | |
| 326 unsigned long _i1; | |
| 327 unsigned long _i2; | |
| 328 unsigned long _i3; | |
| 329 unsigned long _i4; | |
| 330 unsigned long _i5; | |
| 331 unsigned long _fp; | |
| 332 unsigned long _i7; | |
| 333 | |
| 334 unsigned long _fpr[32]; | |
| 335 | |
| 336 unsigned long _y; | |
| 337 unsigned long _psr; | |
| 338 unsigned long _wim; | |
| 339 unsigned long _tbr; | |
| 340 | |
| 341 unsigned long _pc; | |
| 342 unsigned long _npc; | |
| 343 unsigned long _fpsr; | |
| 344 unsigned long _cpsr; | |
| 345 unsigned long _dia1; | |
| 346 unsigned long _dia2; | |
| 347 unsigned long _dda1; | |
| 348 unsigned long _dda2; | |
| 349 unsigned long _ddv1; | |
| 350 unsigned long _ddv2; | |
| 351 unsigned long _dcr; | |
| 352 unsigned long _dsr; | |
| 353 | |
| 354 unsigned long _asr17; | |
| 355 | |
| 356 } ex_regs_t; | |
| 357 | |
| 358 /* | |
| 359 * How gdb expects registers to be stored. | |
| 360 */ | |
| 361 typedef struct | |
| 362 { | |
| 363 unsigned long _g0; | |
| 364 unsigned long _g1; | |
| 365 unsigned long _g2; | |
| 366 unsigned long _g3; | |
| 367 unsigned long _g4; | |
| 368 unsigned long _g5; | |
| 369 unsigned long _g6; | |
| 370 unsigned long _g7; | |
| 371 unsigned long _o0; | |
| 372 unsigned long _o1; | |
| 373 unsigned long _o2; | |
| 374 unsigned long _o3; | |
| 375 unsigned long _o4; | |
| 376 unsigned long _o5; | |
| 377 unsigned long _sp; | |
| 378 unsigned long _o7; | |
| 379 unsigned long _l0; | |
| 380 unsigned long _l1; | |
| 381 unsigned long _l2; | |
| 382 unsigned long _l3; | |
| 383 unsigned long _l4; | |
| 384 unsigned long _l5; | |
| 385 unsigned long _l6; | |
| 386 unsigned long _l7; | |
| 387 unsigned long _i0; | |
| 388 unsigned long _i1; | |
| 389 unsigned long _i2; | |
| 390 unsigned long _i3; | |
| 391 unsigned long _i4; | |
| 392 unsigned long _i5; | |
| 393 unsigned long _fp; | |
| 394 unsigned long _i7; | |
| 395 unsigned long _fpr[32]; | |
| 396 unsigned long _y; | |
| 397 unsigned long _psr; | |
| 398 unsigned long _wim; | |
| 399 unsigned long _tbr; | |
| 400 unsigned long _pc; | |
| 401 unsigned long _npc; | |
| 402 unsigned long _fpsr; | |
| 403 unsigned long _cpsr; | |
| 404 unsigned long _dia1; | |
| 405 unsigned long _dia2; | |
| 406 unsigned long _dda1; | |
| 407 unsigned long _dda2; | |
| 408 unsigned long _ddv1; | |
| 409 unsigned long _ddv2; | |
| 410 unsigned long _dcr; | |
| 411 unsigned long _dsr; | |
| 412 } gdb_regs_t; | |
| 413 | |
| 414 | |
| 415 extern void __dcache_flush(void *addr, int nbytes); | |
| 416 extern void __icache_flush(void *addr, int nbytes); | |
| 417 extern int __dcache_disable(void); | |
| 418 extern void __dcache_enable(void); | |
| 419 extern void __icache_disable(void); | |
| 420 extern void __icache_enable(void); | |
| 421 | |
| 422 | |
| 423 #endif /* !__ASSEMBLER__ */ | |
| 424 | |
| 425 | |
| 426 #define PSR_INIT 0xfa7 | |
| 427 | |
| 428 | |
| 429 /* | |
| 430 * Memory-mapped (ASI=1) registers for MB8683x series. | |
| 431 */ | |
| 432 #define CBIR 0x00000000 | |
| 433 #define LCR 0x00000004 | |
| 434 #define LCSR 0x00000008 | |
| 435 #define CSR 0x0000000C | |
| 436 #define RLCR 0x00000010 | |
| 437 #define BCR 0x00000020 | |
| 438 #define SSCR 0x00000080 | |
| 439 | |
| 440 #define SPGMR 0x00000120 | |
| 441 #define ARSR1 0x00000124 | |
| 442 #define ARSR2 0x00000128 | |
| 443 #define ARSR3 0x0000012C | |
| 444 #define ARSR4 0x00000130 | |
| 445 #define ARSR5 0x00000134 | |
| 446 #define AMR0 0x00000140 | |
| 447 #define AMR1 0x00000144 | |
| 448 #define AMR2 0x00000148 | |
| 449 #define AMR3 0x0000014C | |
| 450 #define AMR4 0x00000150 | |
| 451 #define AMR5 0x00000154 | |
| 452 #define WSSR0 0x00000160 | |
| 453 #define WSSR1 0x00000164 | |
| 454 #define WSSR2 0x00000168 | |
| 455 #define BWCR 0x0000016C | |
| 456 #define REFTMR 0x00000174 | |
| 457 #define DRLD 0x00000178 | |
| 458 #define VER2 0x00020000 | |
| 459 #define SLPMD 0x00020004 | |
| 460 | |
| 461 /* CBIR bit fields */ | |
| 462 #define CBIR_ICEN 0x01 /* Icache enable */ | |
| 463 #define CBIR_ICLOCK 0x02 /* Icache lock */ | |
| 464 #define CBIR_DCEN 0x04 /* Dcache enable */ | |
| 465 #define CBIR_DCLOCK 0x08 /* Dcache lock */ | |
| 466 #define CBIR_PBEN 0x10 /* Prefetch Buffer enable */ | |
| 467 #define CBIR_WBEN 0x20 /* Write Buffer enable */ | |
| 468 | |
| 469 /* LCR bit fields */ | |
| 470 #define LCR_ILOCK 0x01 /* Icache Auto-lock enable */ | |
| 471 #define LCR_DLOCK 0x02 /* Dcache Auto-lock enable */ | |
| 472 | |
| 473 /* WSSRn bit fields */ | |
| 474 #define WSSR_OVERRIDE 1 | |
| 475 #define WSSR_SINGLE 2 | |
| 476 #define WSSR_WAITEN 4 | |
| 477 | |
| 478 #define WSSR_CNT1_SHIFT 8 | |
| 479 #define WSSR_CNT2_SHIFT 3 | |
| 480 #define WSSR_CS0_SHIFT 6 | |
| 481 #define WSSR_CS1_SHIFT 19 | |
| 482 | |
| 483 #define WSSR_SUBVAL(c1,c2,flags) (((c1)<<8)|((c2)<<3)|(flags)) | |
| 484 #define WSSR_VAL(c1b,c2b,flagsb,c1a,c2a,flagsa) \ | |
| 485 ((WSSR_SUBVAL(c1b,c2b,flagsb)<<19)|(WSSR_SUBVAL(c1a,c2a,flagsa)<<6)) | |
| 486 | |
| 487 #define SPGMR_VAL(asi,addr) (((asi)<<23)|(((addr)>>9)&0x007ffffe)) | |
| 488 #define ARSR_VAL(asi,base) ((((asi)&0xff)<<23)|(((base)>>9)&0x007ffffe)) | |
| 489 #define AMR_VAL(asi,base) (((~(asi))<<23)|(((~(base))>>9)&0x007fffff)) | |
| 490 | |
| 491 /* SSCR bit fields */ | |
| 492 #define SSCR_TIMER 0x04 | |
| 493 #define SSCR_WAIT 0x08 | |
| 494 #define SSCR_CS 0x10 | |
| 495 #define SSCR_SAMEPG 0x20 | |
| 496 #define SSCR_DRAM 0x40 | |
| 497 #define SSCR_BURST 0x80 | |
| 498 | |
| 499 /* BCR bit fields */ | |
| 500 #define BCR_IBE 1 | |
| 501 #define BCR_DBE 2 | |
| 502 | |
| 503 | |
| 504 /* DRAM Controller registers as offsets into CS3 space */ | |
| 505 #define DBANKR 0x20 | |
| 506 #define DTIMR 0x24 | |
| 507 | |
| 508 /* DBANKR bit fields */ | |
| 509 #define DBANKR_512K 0 | |
| 510 #define DBANKR_1M 1 | |
| 511 #define DBANKR_2M 2 | |
| 512 #define DBANKR_4M 3 | |
| 513 #define DBANKR_8M 4 | |
| 514 #define DBANKR_16M 5 | |
| 515 #define DBANKR_32M 6 | |
| 516 #define DBANKR_64M 7 | |
| 517 #define DBANKR_CA9 (2<<4) | |
| 518 #define DBANKR_CA10 (3<<4) | |
| 519 #define DBANKR_CA11 (4<<4) | |
| 520 #define DBANKR_CA12 (5<<4) | |
| 521 #define DBANKR_4C1W (0<<7) /* 4CAS/1WE */ | |
| 522 #define DBANKR_1C4W (1<<7) /* 1CAS/4WE */ | |
| 523 #define DBANKR_EDO (1<<8) | |
| 524 #define DBANKR_SA01 (1<<9) | |
| 525 #define DBANKR_SA02 (2<<9) | |
| 526 #define DBANKR_SA04 (3<<9) | |
| 527 | |
| 528 /* DTIMR bit fields */ | |
| 529 #define DTIMR_RP1 0 | |
| 530 #define DTIMR_RP2 1 | |
| 531 #define DTIMR_CAS1 (0<<1) | |
| 532 #define DTIMR_CAS2 (1<<1) | |
| 533 #define DTIMR_CBR1 (0<<2) | |
| 534 #define DTIMR_CBR2 (1<<2) | |
| 535 #define DTIMR_CBR3 (2<<2) | |
| 536 #define DTIMR_RPS2 (0<<4) | |
| 537 #define DTIMR_RPS4 (1<<4) | |
| 538 | |
| 539 | |
| 540 /* -------------------------------------------------------------------*/ | |
| 541 #endif /* CYGONCE_HAL_SPARCLITE_HAL_CPU_H */ | |
| 542 /* EOF hal_cpu.h */ |