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annotate packages/io/serial/current/src/sparclite/sleb_sdtr.h @ 66:bf00f99aec69 ecos-sw-2000-02-02
Merge from eCos master repository on 2000-02-02-19:16:44-GMT
| author | jlarmour |
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| date | Wed, 02 Feb 2000 19:57:02 +0000 |
| parents | c38311975d4f |
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| rev | line source |
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| 2 | 1 #ifndef CYGONCE_SLEB_SDTR_H |
| 2 #define CYGONCE_SLEB_SDTR_H | |
| 3 //========================================================================== | |
| 4 // | |
| 5 // io/serial/sparclite/sleb_sdtr.c | |
| 6 // | |
| 7 // Serial I/O interface module for SPARClite Eval Board (SLEB) | |
| 8 // | |
| 9 //========================================================================== | |
| 10 //####COPYRIGHTBEGIN#### | |
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11 // |
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12 // ------------------------------------------- |
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13 // The contents of this file are subject to the Red Hat eCos Public License |
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14 // Version 1.1 (the "License"); you may not use this file except in |
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15 // compliance with the License. You may obtain a copy of the License at |
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16 // http://www.redhat.com/ |
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17 // |
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18 // Software distributed under the License is distributed on an "AS IS" |
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19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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20 // License for the specific language governing rights and limitations under |
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21 // the License. |
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22 // |
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23 // The Original Code is eCos - Embedded Configurable Operating System, |
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24 // released September 30, 1998. |
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25 // |
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26 // The Initial Developer of the Original Code is Red Hat. |
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27 // Portions created by Red Hat are |
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28 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
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29 // All Rights Reserved. |
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30 // ------------------------------------------- |
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31 // |
| 2 | 32 //####COPYRIGHTEND#### |
| 33 //========================================================================== | |
| 34 //#####DESCRIPTIONBEGIN#### | |
| 35 // | |
| 36 // Author(s): gthomas | |
| 37 // Contributors: gthomas | |
| 38 // Date: 1999-02-04 | |
| 39 // Purpose: SLEB serial I/O module | |
| 40 // Description: | |
| 41 // | |
| 42 //####DESCRIPTIONEND#### | |
| 43 // | |
| 44 //========================================================================== | |
| 45 | |
| 46 #include <cyg/hal/hal_io.h> // For I/O macros | |
| 47 | |
| 48 #define reg(n) ((n)*4) | |
| 49 | |
| 50 // SDTR Registers | |
| 51 #define SDTR_TXDATA(base) base+reg(0) | |
| 52 #define SDTR_RXDATA(base) base+reg(0) | |
| 53 #define SDTR_STATUS(base) base+reg(1) | |
| 54 #define SDTR_CONTROL(base) base+reg(1) | |
| 55 | |
| 56 // Mode register | |
| 57 #define SDTR_MODE_MODE_MASK 0x03 // Mode selection bits (mask) | |
| 58 #define SDTR_MODE_MODE_SYNC 0x00 // Synchronous mode | |
| 59 #define SDTR_MODE_MODE_ASYNC1 0x01 // Async - clock/1 | |
| 60 #define SDTR_MODE_MODE_ASYNC16 0x02 // Async - clock/16 | |
| 61 #define SDTR_MODE_MODE_ASYNC64 0x03 // Async - clock/64 | |
| 62 #define SDTR_MODE_DTB_MASK 0x0C // Number of data bits (mask) | |
| 63 #define SDTR_MODE_DTB_5 0x00 // 5 bits / char | |
| 64 #define SDTR_MODE_DTB_6 0x04 // 6 bits / char | |
| 65 #define SDTR_MODE_DTB_7 0x08 // 7 bits / char | |
| 66 #define SDTR_MODE_DTB_8 0x0C // 8 bits / char | |
| 67 #define SDTR_MODE_PARITY_MASK 0x30 // Parity modes (mask) | |
| 68 #define SDTR_MODE_PARITY_ENABLE 0x10 // Enable parity | |
| 69 #define SDTR_MODE_PARITY_NONE 0x00 // No parity (parity disabled) | |
| 70 #define SDTR_MODE_PARITY_ODD 0x00 // Odd parity | |
| 71 #define SDTR_MODE_PARITY_EVEN 0x20 // Even parity | |
| 72 #define SDTR_MODE_STOP_BITS_MASK 0xC0 // Number of stop bits (mask) | |
| 73 #define SDTR_MODE_STOP_BITS_1 0x40 // 1 stop bit | |
| 74 #define SDTR_MODE_STOP_BITS_1_5 0x80 // 1.5 stop bits | |
| 75 #define SDTR_MODE_STOP_BITS_2 0xC0 // 2 stop bits | |
| 76 | |
| 77 // Command register | |
| 78 #define SDTR_CMD_TxEN 0x01 // Enable transmitter | |
| 79 #define SDTR_CMD_DTR 0x02 // Assert DTR | |
| 80 #define SDTR_CMD_RxEN 0x04 // Enable receiver | |
| 81 #define SDTR_CMD_BREAK 0x08 // Send break | |
| 82 #define SDTR_CMD_EFR 0x10 // Error flag reset | |
| 83 #define SDTR_CMD_RTS 0x20 // Assert RTS | |
| 84 #define SDTR_CMD_RST 0x40 // Internal RESET | |
| 85 #define SDTR_CMD_EHM 0x80 // Enable Hunt mode | |
| 86 | |
| 87 // Status register | |
| 88 #define SDTR_STAT_TxRDY 0x01 // Transmitter ready | |
| 89 #define SDTR_STAT_RxRDY 0x02 // Receiver ready | |
| 90 #define SDTR_STAT_TxEMP 0x04 // Transmitter empty | |
| 91 #define SDTR_STAT_PERR 0x08 // Parity error | |
| 92 #define SDTR_STAT_OERR 0x10 // Overrun error | |
| 93 #define SDTR_STAT_FERR 0x20 // Framing error | |
| 94 #define SDTR_STAT_SYBRK 0x40 // Break | |
| 95 #define SDTR_STAT_DSR 0x80 // State of DSR signal | |
| 96 | |
| 97 // Offsets to standard SDTR elements | |
| 98 #define SLEB_SDTR0_BASE (8*4) | |
| 99 #define SLEB_SDTR0_TX_INT 9 | |
| 100 #define SLEB_SDTR0_RX_INT 10 | |
| 101 #define SLEB_SDTR1_BASE (12*4) | |
| 102 #define SLEB_SDTR1_TX_INT 6 | |
| 103 #define SLEB_SDTR1_RX_INT 7 | |
| 104 #define SLEB_TIMER3_CONTROL reg(29) | |
| 105 #define SLEB_TIMER3_RELOAD reg(30) | |
| 106 | |
| 107 // On-board switch, used to determine baud rate | |
| 108 #define SLEB_CLOCK_SWITCH (volatile unsigned char *)0x01000003 | |
| 109 | |
| 110 static unsigned char select_word_length[] = { | |
| 111 SDTR_MODE_DTB_5, // 5 bits / word (char) | |
| 112 SDTR_MODE_DTB_6, | |
| 113 SDTR_MODE_DTB_7, | |
| 114 SDTR_MODE_DTB_8 | |
| 115 }; | |
| 116 | |
| 117 static unsigned char select_stop_bits[] = { | |
| 118 0, | |
| 119 SDTR_MODE_STOP_BITS_1, // 1 stop bit | |
| 120 SDTR_MODE_STOP_BITS_1_5, // 1.5 stop bit | |
| 121 SDTR_MODE_STOP_BITS_2 // 2 stop bits | |
| 122 }; | |
| 123 | |
| 124 static unsigned char select_parity[] = { | |
| 125 SDTR_MODE_PARITY_NONE, // No parity | |
| 126 SDTR_MODE_PARITY_ENABLE|SDTR_MODE_PARITY_EVEN, // Even parity | |
| 127 SDTR_MODE_PARITY_ENABLE|SDTR_MODE_PARITY_ODD, // ODD parity | |
| 128 0xFF, // Mark parity | |
| 129 0xFF, // Space parity | |
| 130 }; | |
| 131 | |
| 132 static cyg_int32 select_baud[] = { | |
| 133 0, // Unused | |
| 134 50, // 50 | |
| 135 75, // 75 | |
| 136 110, // 110 | |
| 137 0, // 134.5 | |
| 138 150, // 150 | |
| 139 200, // 200 | |
| 140 300, // 300 | |
| 141 600, // 600 | |
| 142 1200, // 1200 | |
| 143 1800, // 1800 | |
| 144 2400, // 2400 | |
| 145 3600, // 3600 | |
| 146 4800, // 4800 | |
| 147 7200, // 7200 | |
| 148 9600, // 9600 | |
| 149 14400, // 14400 | |
| 150 19200, // 19200 | |
| 151 38400, // 38400 | |
| 152 57600, // 57600 | |
| 153 115200, // 115200 | |
| 154 230400, // 230400 | |
| 155 }; | |
| 156 | |
| 157 #endif // CYGONCE_SLEB_SDTR_H | |
| 158 |