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annotate packages/hal/powerpc/arch/current/include/hal_cache.h @ 68:f74b2666b30d ecos-sw-2000-02-04
Merge from eCos master repository on 2000-02-04-07:47:04-GMT
| author | jlarmour |
|---|---|
| date | Fri, 04 Feb 2000 15:01:01 +0000 |
| parents | bf00f99aec69 |
| children | c5536bad4c24 |
| rev | line source |
|---|---|
| 0 | 1 #ifndef CYGONCE_HAL_CACHE_H |
| 2 #define CYGONCE_HAL_CACHE_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 6 // hal_cache.h | |
| 7 // | |
| 8 // HAL cache control API | |
| 9 // | |
| 10 //============================================================================= | |
| 11 //####COPYRIGHTBEGIN#### | |
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12 // |
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13 // ------------------------------------------- |
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14 // The contents of this file are subject to the Red Hat eCos Public License |
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15 // Version 1.1 (the "License"); you may not use this file except in |
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16 // compliance with the License. You may obtain a copy of the License at |
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17 // http://www.redhat.com/ |
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18 // |
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19 // Software distributed under the License is distributed on an "AS IS" |
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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21 // License for the specific language governing rights and limitations under |
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22 // the License. |
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23 // |
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24 // The Original Code is eCos - Embedded Configurable Operating System, |
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25 // released September 30, 1998. |
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26 // |
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27 // The Initial Developer of the Original Code is Red Hat. |
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28 // Portions created by Red Hat are |
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
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30 // All Rights Reserved. |
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31 // ------------------------------------------- |
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32 // |
| 0 | 33 //####COPYRIGHTEND#### |
| 34 //============================================================================= | |
| 35 //#####DESCRIPTIONBEGIN#### | |
| 36 // | |
| 37 // Author(s): nickg | |
| 38 // Contributors: nickg | |
| 39 // Date: 1998-02-17 | |
| 40 // Purpose: Cache control API | |
| 41 // Description: The macros defined here provide the HAL APIs for handling | |
| 42 // cache control operations. | |
| 43 // Usage: | |
| 44 // #include <cyg/hal/hal_cache.h> | |
| 45 // ... | |
| 46 // | |
| 47 // | |
| 48 //####DESCRIPTIONEND#### | |
| 49 // | |
| 50 //============================================================================= | |
| 51 | |
| 52 #include <pkgconf/hal.h> | |
| 53 #include <cyg/infra/cyg_type.h> | |
| 2 | 54 |
| 0 | 55 #include <cyg/hal/ppc_regs.h> |
| 56 | |
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57 #include <cyg/hal/plf_cache.h> |
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58 |
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59 |
| 0 | 60 //============================================================================= |
| 2 | 61 // Memory mapping |
| 62 typedef struct { | |
| 63 CYG_ADDRESS virtual_addr; | |
| 64 CYG_ADDRESS physical_addr; | |
| 65 cyg_int32 size; | |
| 66 cyg_uint8 flags; | |
| 67 } cyg_memdesc_t; | |
| 68 | |
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69 // each platform HAL must provide one of these to describe how memory |
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70 // should be mapped/cached, ideally weak aliased so that apps can override: |
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71 externC cyg_memdesc_t cyg_hal_mem_map[]; |
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72 |
| 2 | 73 #define CYGARC_MEMDESC_CI 1 // cache inhibit |
| 74 #define CYGARC_MEMDESC_GUARDED 2 // guarded | |
| 75 | |
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76 // these macros should ease that task, and ease any future extension of the |
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77 // structure (physical == virtual addresses): |
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78 #define CYGARC_MEMDESC_CACHE( _va_, _sz_ ) \ |
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79 { (_va_), (_va_), (_sz_), 0 } |
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80 |
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81 #define CYGARC_MEMDESC_NOCACHE( _va_, _sz_ ) \ |
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82 { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_CI } |
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83 |
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84 #define CYGARC_MEMDESC_CACHEGUARD( _va_, _sz_ ) \ |
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85 { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED } |
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86 |
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87 #define CYGARC_MEMDESC_NOCACHEGUARD( _va_, _sz_ ) \ |
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88 { (_va_), (_va_), (_sz_), CYGARC_MEMDESC_GUARDED|CYGARC_MEMDESC_CI } |
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89 |
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90 #define CYGARC_MEMDESC_TABLE_END {0, 0, 0, 0} |
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91 #define CYGARC_MEMDESC_TABLE cyg_memdesc_t cyg_hal_mem_map[] |
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92 #define CYGARC_MEMDESC_EMPTY_TABLE { CYGARC_MEMDESC_TABLE_END } |
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93 |
| 2 | 94 //============================================================================= |
| 0 | 95 // PowerPC simulator |
| 96 | |
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97 #ifdef CYGPKG_HAL_POWERPC_SIM |
| 0 | 98 |
| 99 //----------------------------------------------------------------------------- | |
| 100 // Cache dimensions | |
| 101 | |
| 102 // Data cache | |
| 103 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes | |
| 104 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line | |
| 105 #define HAL_DCACHE_WAYS 2 // Associativity of the cache | |
| 106 | |
| 107 // Instruction cache | |
| 108 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes | |
| 109 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line | |
| 110 #define HAL_ICACHE_WAYS 2 // Associativity of the cache | |
| 111 | |
| 112 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) | |
| 113 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) | |
| 114 | |
| 115 //----------------------------------------------------------------------------- | |
| 116 // Global control of data cache | |
| 117 | |
| 118 // Enable the data cache | |
| 119 #define HAL_DCACHE_ENABLE() | |
| 120 | |
| 121 // Disable the data cache | |
| 122 #define HAL_DCACHE_DISABLE() | |
| 123 | |
| 124 // Invalidate the entire cache | |
| 125 #define HAL_DCACHE_INVALIDATE_ALL() | |
| 126 | |
| 127 // Synchronize the contents of the cache with memory. | |
| 128 #define HAL_DCACHE_SYNC() | |
| 129 | |
| 2 | 130 // Query the state of the data cache |
| 131 #define HAL_DCACHE_IS_ENABLED(_state_) \ | |
| 132 CYG_MACRO_START \ | |
| 133 (_state_) = 0; \ | |
| 134 CYG_MACRO_END | |
| 135 | |
| 0 | 136 // Set the data cache refill burst size |
| 137 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 138 | |
| 139 // Set the data cache write mode | |
| 140 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 141 | |
| 142 //#define HAL_DCACHE_WRITETHRU_MODE 0 | |
| 143 //#define HAL_DCACHE_WRITEBACK_MODE 1 | |
| 144 | |
| 145 // Load the contents of the given address range into the data cache | |
| 146 // and then lock the cache so that it stays there. | |
| 147 //#define HAL_DCACHE_LOCK(_base_, _size_) | |
| 148 | |
| 149 // Undo a previous lock operation | |
| 150 //#define HAL_DCACHE_UNLOCK(_base_, _size_) | |
| 151 | |
| 2 | 152 // Unlock entire cache |
| 153 //#define HAL_DCACHE_UNLOCK_ALL() | |
| 154 | |
| 0 | 155 //----------------------------------------------------------------------------- |
| 156 // Data cache line control | |
| 157 | |
| 158 // Allocate cache lines for the given address range without reading its | |
| 159 // contents from memory. | |
| 160 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 161 | |
| 162 // Write dirty cache lines to memory and invalidate the cache entries | |
| 163 // for the given address range. | |
| 164 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) | |
| 165 | |
| 166 // Invalidate cache lines in the given range without writing to memory. | |
| 167 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) | |
| 168 | |
| 169 // Write dirty cache lines to memory for the given address range. | |
| 170 //#define HAL_DCACHE_STORE( _base_ , _size_ ) | |
| 171 | |
| 172 // Preread the given range into the cache with the intention of reading | |
| 173 // from it later. | |
| 174 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) | |
| 175 | |
| 176 // Preread the given range into the cache with the intention of writing | |
| 177 // to it later. | |
| 178 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) | |
| 179 | |
| 180 // Allocate and zero the cache lines associated with the given range. | |
| 181 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) | |
| 182 | |
| 183 //----------------------------------------------------------------------------- | |
| 184 // Global control of Instruction cache | |
| 185 | |
| 186 // Enable the instruction cache | |
| 187 #define HAL_ICACHE_ENABLE() | |
| 188 | |
| 189 // Disable the instruction cache | |
| 190 #define HAL_ICACHE_DISABLE() | |
| 191 | |
| 192 // Invalidate the entire cache | |
| 193 #define HAL_ICACHE_INVALIDATE_ALL() | |
| 194 | |
| 195 // Synchronize the contents of the cache with memory. | |
| 196 #define HAL_ICACHE_SYNC() | |
| 197 | |
| 2 | 198 // Query the state of the instruction cache |
| 199 #define HAL_ICACHE_IS_ENABLED(_state_) \ | |
| 200 CYG_MACRO_START \ | |
| 201 (_state_) = 0; \ | |
| 202 CYG_MACRO_END | |
| 203 | |
| 0 | 204 // Set the instruction cache refill burst size |
| 205 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 206 | |
| 207 // Load the contents of the given address range into the instruction cache | |
| 208 // and then lock the cache so that it stays there. | |
| 209 //#define HAL_ICACHE_LOCK(_base_, _size_) | |
| 210 | |
| 211 // Undo a previous lock operation | |
| 212 //#define HAL_ICACHE_UNLOCK(_base_, _size_) | |
| 213 | |
| 2 | 214 // Unlock entire cache |
| 215 //#define HAL_ICACHE_UNLOCK_ALL() | |
| 216 | |
| 0 | 217 //----------------------------------------------------------------------------- |
| 218 // Instruction cache line control | |
| 219 | |
| 220 // Invalidate cache lines in the given range without writing to memory. | |
| 221 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 222 | |
| 223 | |
| 224 //============================================================================= | |
| 2 | 225 // Motorola MPC8xx |
| 0 | 226 |
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227 #elif defined(CYGPKG_HAL_POWERPC_MPC8xx) |
| 0 | 228 |
| 229 //----------------------------------------------------------------------------- | |
| 230 // Cache dimensions | |
| 231 | |
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232 #if defined(CYGPKG_HAL_POWERPC_MPC860) |
| 0 | 233 // Data cache |
| 234 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes | |
| 235 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line | |
| 236 #define HAL_DCACHE_WAYS 2 // Associativity of the cache | |
| 237 | |
| 238 // Instruction cache | |
| 239 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes | |
| 240 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line | |
| 241 #define HAL_ICACHE_WAYS 2 // Associativity of the cache | |
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242 #endif // defined(CYGPKG_HAL_POWERPC_MPC860) |
| 2 | 243 |
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244 #if defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) |
| 2 | 245 // Data cache |
| 246 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes | |
| 247 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line | |
| 248 #define HAL_DCACHE_WAYS 2 // Associativity of the cache | |
| 249 | |
| 250 // Instruction cache | |
| 251 #define HAL_ICACHE_SIZE 2048 // Size of cache in bytes | |
| 252 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line | |
| 253 #define HAL_ICACHE_WAYS 2 // Associativity of the cache | |
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254 #endif // defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) |
| 0 | 255 |
| 256 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) | |
| 257 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) | |
| 258 | |
| 259 //----------------------------------------------------------------------------- | |
| 260 // Global control of data cache | |
| 261 | |
| 262 // Enable the data cache | |
| 263 #define HAL_DCACHE_ENABLE() \ | |
| 264 asm volatile ("sync;" \ | |
| 2 | 265 "mtspr %0, %1;" \ |
| 266 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CE)) | |
| 0 | 267 |
| 268 // Disable the data cache | |
| 269 #define HAL_DCACHE_DISABLE() \ | |
| 270 asm volatile ("sync;" \ | |
| 2 | 271 "mtspr %0, %1;" \ |
| 272 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CD)) | |
| 0 | 273 |
| 274 // Invalidate the entire cache | |
| 2 | 275 // Note: Any locked lines will not be invalidated. |
| 276 #define HAL_DCACHE_INVALIDATE_ALL() \ | |
| 277 asm volatile ("sync;" \ | |
| 278 "mtspr %0, %1;" \ | |
| 279 : : "I" (CYGARC_REG_DC_CST), \ | |
| 280 "r" (CYGARC_REG_DC_CMD_IA)) | |
| 0 | 281 |
| 282 // Synchronize the contents of the cache with memory. | |
| 2 | 283 #define HAL_DCACHE_SYNC() \ |
| 284 CYG_MACRO_START \ | |
| 285 cyg_int32 i; \ | |
| 286 for (i = 0; i < HAL_DCACHE_SETS; i++){ \ | |
| 287 asm volatile ("sync;" \ | |
| 288 "mtspr %0, %2;" \ | |
| 289 "mtspr %1, %4;" \ | |
| 290 "mtspr %0, %3;" \ | |
| 291 "mtspr %1, %4;" \ | |
| 292 : /* no output */ \ | |
| 293 : /* %0 */ "I" (CYGARC_REG_DC_ADR), \ | |
| 294 /* %1 */ "I" (CYGARC_REG_DC_CST), \ | |
| 295 /* %2 */ "r" (CYGARC_REG_DC_ADR_WAY0 \ | |
| 296 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \ | |
| 297 /* %3 */ "r" (CYGARC_REG_DC_ADR_WAY1 \ | |
| 298 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \ | |
| 299 /* %4 */ "r" (CYGARC_REG_DC_CMD_FL)); \ | |
| 300 } \ | |
| 0 | 301 CYG_MACRO_END |
| 2 | 302 |
| 303 // Query the state of the data cache | |
| 304 #define HAL_DCACHE_IS_ENABLED(_state_) \ | |
| 305 asm volatile ("mfspr %0, %1;" \ | |
| 306 "rlwinm %0,%0,1,31,31;" \ | |
| 307 : "=r" (_state_) : "I" (CYGARC_REG_DC_CST)) | |
| 0 | 308 |
| 309 // Set the data cache refill burst size | |
| 310 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 311 | |
| 312 // Set the data cache write mode | |
| 313 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 314 | |
| 315 //#define HAL_DCACHE_WRITETHRU_MODE 0 | |
| 316 //#define HAL_DCACHE_WRITEBACK_MODE 1 | |
| 317 | |
| 2 | 318 |
| 319 // Load the contents of the given address range into the data cache | |
| 320 // and then lock the cache so that it stays there. | |
| 321 | |
| 322 // Restrictions: This implementation only allows a single area to be | |
| 323 // locked at any one time. This area must be 2kB or less in size. | |
| 324 | |
| 325 // Implementation: Flush entire cache, then invalidate it. This | |
| 326 // ensures that the fetched data go into way0. | |
| 0 | 327 |
| 2 | 328 #define HAL_DCACHE_LOCK(_base_, _size_) \ |
| 329 CYG_MACRO_START \ | |
| 330 cyg_int32 __scratch; \ | |
| 331 cyg_uint32 __base = (cyg_uint32)(_base_); \ | |
| 332 cyg_int32 __l = ((__base / HAL_DCACHE_LINE_SIZE) % HAL_DCACHE_SETS); \ | |
| 333 cyg_int32 __count = ((_size_) / HAL_DCACHE_LINE_SIZE); \ | |
| 334 HAL_DCACHE_DISABLE(); \ | |
| 335 HAL_DCACHE_SYNC (); \ | |
| 336 HAL_DCACHE_INVALIDATE_ALL (); \ | |
| 337 HAL_DCACHE_ENABLE(); \ | |
| 338 do { \ | |
| 339 asm volatile ("lbz %0,0(%1);" \ | |
| 340 "sync;" \ | |
| 341 "mtspr %2, %4;" \ | |
| 342 "mtspr %3, %5;" \ | |
|
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343 : /* %0 */ "=&r" (__scratch) \ |
| 2 | 344 : /* %1 */ "b" (__base), \ |
| 345 /* %2 */ "I" (CYGARC_REG_DC_ADR), \ | |
| 346 /* %3 */ "I" (CYGARC_REG_DC_CST), \ | |
| 347 /* %4 */ "r" (CYGARC_REG_DC_ADR_WAY0 \ | |
| 348 |(__l<<CYGARC_REG_DC_ADR_SETID_SHIFT)), \ | |
| 349 /* %5 */ "r" (CYGARC_REG_DC_CMD_LL)); \ | |
| 350 __l++; \ | |
| 351 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 352 } while (__count--); \ | |
| 353 CYG_MACRO_END | |
| 354 | |
| 355 | |
| 0 | 356 // Undo a previous lock operation |
| 2 | 357 |
| 358 // Implementation: Unlocks entire cache. | |
| 359 | |
| 360 #define HAL_DCACHE_UNLOCK(_base_, _size_) \ | |
| 361 HAL_DCACHE_UNLOCK_ALL() | |
| 362 | |
| 363 | |
| 364 // Unlock entire cache | |
| 365 #define HAL_DCACHE_UNLOCK_ALL() \ | |
| 366 CYG_MACRO_START \ | |
| 367 asm volatile ("sync;" \ | |
| 368 "mtspr %0, %1;" \ | |
| 369 : : "I" (CYGARC_REG_DC_CST), \ | |
| 370 "r" (CYGARC_REG_DC_CMD_UA)); \ | |
| 371 CYG_MACRO_END | |
| 372 | |
| 373 | |
| 0 | 374 |
| 375 //----------------------------------------------------------------------------- | |
| 376 // Data cache line control | |
| 377 | |
| 378 // Allocate cache lines for the given address range without reading its | |
| 379 // contents from memory. | |
| 380 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 381 | |
| 382 // Write dirty cache lines to memory and invalidate the cache entries | |
| 383 // for the given address range. | |
| 2 | 384 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) \ |
| 385 CYG_MACRO_START \ | |
| 386 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 387 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 388 while (__size > 0) { \ | |
| 389 asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \ | |
| 390 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 391 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 392 } \ | |
| 393 CYG_MACRO_END | |
| 394 | |
| 0 | 395 // Invalidate cache lines in the given range without writing to memory. |
| 2 | 396 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \ |
| 397 CYG_MACRO_START \ | |
| 398 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 399 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 400 while (__size > 0) { \ | |
| 401 asm volatile ("dcbi 0,%0;sync;" : : "r" (__base)); \ | |
| 402 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 403 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 404 } \ | |
| 405 CYG_MACRO_END | |
| 0 | 406 |
| 407 // Write dirty cache lines to memory for the given address range. | |
| 2 | 408 #define HAL_DCACHE_STORE( _base_ , _size_ ) \ |
| 409 CYG_MACRO_START \ | |
| 410 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 411 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 412 while (__size > 0) { \ | |
| 413 asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \ | |
| 414 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 415 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 416 } \ | |
| 417 CYG_MACRO_END | |
| 0 | 418 |
| 419 // Preread the given range into the cache with the intention of reading | |
| 420 // from it later. | |
| 2 | 421 #define HAL_DCACHE_READ_HINT( _base_ , _size_ ) \ |
| 422 CYG_MACRO_START \ | |
| 423 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 424 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 425 while (__size > 0) { \ | |
| 426 asm volatile ("dcbt 0,%0;" : : "r" (__base)); \ | |
| 427 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 428 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 429 } \ | |
| 430 CYG_MACRO_END | |
| 0 | 431 |
| 432 // Preread the given range into the cache with the intention of writing | |
| 433 // to it later. | |
| 2 | 434 #define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) \ |
| 435 CYG_MACRO_START \ | |
| 436 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 437 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 438 while (__size > 0) { \ | |
| 439 asm volatile ("dcbtst 0,%0;" : : "r" (__base)); \ | |
| 440 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 441 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 442 } \ | |
| 443 CYG_MACRO_END | |
| 0 | 444 |
| 445 // Allocate and zero the cache lines associated with the given range. | |
| 2 | 446 #define HAL_DCACHE_ZERO( _base_ , _size_ ) \ |
| 447 CYG_MACRO_START \ | |
| 448 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 449 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 450 while (__size > 0) { \ | |
| 451 asm volatile ("dcbz 0,%0;" : : "r" (__base)); \ | |
| 452 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 453 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 454 } \ | |
| 455 CYG_MACRO_END | |
| 0 | 456 |
| 457 //----------------------------------------------------------------------------- | |
| 458 // Global control of Instruction cache | |
| 459 | |
| 460 // Enable the instruction cache | |
| 2 | 461 #define HAL_ICACHE_ENABLE() \ |
| 462 asm volatile ("isync;" \ | |
| 463 "mtspr %0, %1;" \ | |
| 464 "isync" \ | |
| 465 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE)) | |
| 0 | 466 |
| 467 // Disable the instruction cache | |
| 2 | 468 #define HAL_ICACHE_DISABLE() \ |
| 469 asm volatile ("isync;" \ | |
| 470 "mtspr %0, %1;" \ | |
| 471 "isync" \ | |
| 472 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CD)) | |
| 0 | 473 |
| 474 // Invalidate the entire cache | |
| 2 | 475 #define HAL_ICACHE_INVALIDATE_ALL() \ |
| 476 asm volatile ("isync;" \ | |
| 477 "mtspr %0, %1;" \ | |
| 478 "isync" \ | |
| 479 : : "I" (CYGARC_REG_IC_CST), \ | |
| 480 "r" (CYGARC_REG_IC_CMD_IA)) | |
| 0 | 481 |
| 482 // Synchronize the contents of the cache with memory. | |
|
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483 #define HAL_ICACHE_SYNC() \ |
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484 HAL_ICACHE_INVALIDATE_ALL() |
| 0 | 485 |
| 2 | 486 // Query the state of the instruction cache |
| 487 #define HAL_ICACHE_IS_ENABLED(_state_) \ | |
| 488 asm volatile ("mfspr %0, %1;" \ | |
| 489 "rlwinm %0,%0,1,31,31;" \ | |
| 490 : "=r" (_state_) : "I" (CYGARC_REG_IC_CST)) | |
| 0 | 491 |
| 492 // Set the instruction cache refill burst size | |
| 493 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 494 | |
| 2 | 495 |
| 0 | 496 // Load the contents of the given address range into the instruction cache |
| 497 // and then lock the cache so that it stays there. | |
| 2 | 498 |
| 499 // Restrictions: This implementation only allows a single area to be | |
| 500 // locked at any one time. This area must be 2kB or less in size. | |
| 501 | |
| 502 // Implementation: Flush entire cache, then invalidate it. This | |
| 503 // ensures that the fetched data go into way0. | |
| 504 | |
| 505 #define HAL_ICACHE_LOCK(_base_, _size_) \ | |
| 506 CYG_MACRO_START \ | |
| 507 unsigned long __base = \ | |
| 508 ((unsigned long) (_base_)) & ~(HAL_ICACHE_LINE_SIZE-1); \ | |
| 509 int __count = ((_size_) / HAL_ICACHE_LINE_SIZE); \ | |
| 510 do { \ | |
| 511 asm volatile ("mtspr %0, %2;" \ | |
| 512 "mtspr %1, %3;" \ | |
| 513 "isync;" \ | |
| 514 : /* no output */ \ | |
| 515 : /* %0 */ "I" (CYGARC_REG_IC_ADR), \ | |
| 516 /* %1 */ "I" (CYGARC_REG_IC_CST), \ | |
| 517 /* %2 */ "r" (__base), \ | |
| 518 /* %3 */ "r" (CYGARC_REG_IC_CMD_LL)); \ | |
| 519 __base += HAL_ICACHE_LINE_SIZE; \ | |
| 520 } while (__count--); \ | |
| 521 CYG_MACRO_END | |
| 0 | 522 |
| 523 // Undo a previous lock operation | |
| 2 | 524 |
| 525 // Implementation: Unlocks entire cache. | |
| 526 #define HAL_ICACHE_UNLOCK(_base_, _size_) \ | |
| 527 HAL_ICACHE_UNLOCK_ALL() | |
| 528 | |
| 529 // Unlock entire cache | |
| 530 #define HAL_ICACHE_UNLOCK_ALL() \ | |
| 531 CYG_MACRO_START \ | |
| 532 asm volatile ("sync;" \ | |
| 533 "mtspr %0, %1;" \ | |
| 534 : : "I" (CYGARC_REG_IC_CST), \ | |
| 535 "r" (CYGARC_REG_IC_CMD_UA)); \ | |
| 536 CYG_MACRO_END | |
| 0 | 537 |
| 538 //----------------------------------------------------------------------------- | |
| 539 // Instruction cache line control | |
| 540 | |
| 541 // Invalidate cache lines in the given range without writing to memory. | |
| 542 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 543 | |
| 544 #endif | |
| 545 | |
| 546 //----------------------------------------------------------------------------- | |
| 547 #endif // ifndef CYGONCE_HAL_CACHE_H | |
| 548 // End of hal_cache.h |